664 lines
21 KiB
Verilog
664 lines
21 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Mon Jul 6 19:07:18 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1
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// first O 97
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// RDY_first O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 97
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkLSQIssueLdQ(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first,
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RDY_first,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [96 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first
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output [96 : 0] first;
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output RDY_first;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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reg RDY_deq;
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wire [96 : 0] first;
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wire RDY_enq,
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RDY_first,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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reg m_m_valid_for_enq_wire$wget;
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wire m_m_deqP_ehr_lat_0$whas,
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m_m_empty_for_enq_wire$wget,
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m_m_valid_0_lat_0$whas,
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m_m_valid_0_lat_1$whas,
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m_m_valid_1_lat_0$whas,
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m_m_valid_1_lat_1$whas;
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// register m_m_deqP_ehr_rl
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reg m_m_deqP_ehr_rl;
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wire m_m_deqP_ehr_rl$D_IN, m_m_deqP_ehr_rl$EN;
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// register m_m_enqP
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reg m_m_enqP;
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wire m_m_enqP$D_IN, m_m_enqP$EN;
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// register m_m_row_0
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reg [84 : 0] m_m_row_0;
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wire [84 : 0] m_m_row_0$D_IN;
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wire m_m_row_0$EN;
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// register m_m_row_1
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reg [84 : 0] m_m_row_1;
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wire [84 : 0] m_m_row_1$D_IN;
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wire m_m_row_1$EN;
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// register m_m_specBits_0_rl
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reg [11 : 0] m_m_specBits_0_rl;
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wire [11 : 0] m_m_specBits_0_rl$D_IN;
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wire m_m_specBits_0_rl$EN;
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// register m_m_specBits_1_rl
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reg [11 : 0] m_m_specBits_1_rl;
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wire [11 : 0] m_m_specBits_1_rl$D_IN;
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wire m_m_specBits_1_rl$EN;
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// register m_m_valid_0_rl
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reg m_m_valid_0_rl;
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wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
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// register m_m_valid_1_rl
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reg m_m_valid_1_rl;
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wire m_m_valid_1_rl$D_IN, m_m_valid_1_rl$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_m_canon_deqP,
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CAN_FIRE_RL_m_m_deqP_ehr_canon,
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CAN_FIRE_RL_m_m_setWireForEnq,
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CAN_FIRE_RL_m_m_specBits_0_canon,
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CAN_FIRE_RL_m_m_specBits_1_canon,
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CAN_FIRE_RL_m_m_valid_0_canon,
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CAN_FIRE_RL_m_m_valid_1_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_m_canon_deqP,
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WILL_FIRE_RL_m_m_deqP_ehr_canon,
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WILL_FIRE_RL_m_m_setWireForEnq,
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WILL_FIRE_RL_m_m_specBits_0_canon,
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WILL_FIRE_RL_m_m_specBits_1_canon,
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WILL_FIRE_RL_m_m_valid_0_canon,
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WILL_FIRE_RL_m_m_valid_1_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// inputs to muxes for submodule ports
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wire MUX_m_m_valid_0_lat_0$wset_1__SEL_2,
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MUX_m_m_valid_1_lat_0$wset_1__SEL_2;
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// remaining internal signals
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reg [63 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_79_TO_16_ETC__q16;
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reg [11 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q19;
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reg [4 : 0] CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_84_TO_80_ETC__q18;
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reg CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q20,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_0_1_m_m_r_ETC__q17,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_10_1_m_m__ETC__q6,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_13_1_m_m__ETC__q3,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_14_1_m_m__ETC__q2,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_15_1_m_m__ETC__q1,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_1_1_m_m_r_ETC__q15,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_2_1_m_m_r_ETC__q14,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_3_1_m_m_r_ETC__q13,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_4_1_m_m_r_ETC__q12,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_5_1_m_m_r_ETC__q11,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_6_1_m_m_r_ETC__q10,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_7_1_m_m_r_ETC__q9,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_8_1_m_m_r_ETC__q8,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_9_1_m_m_r_ETC__q7;
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wire [79 : 0] SEL_ARR_m_m_row_0_7_BITS_79_TO_16_3_m_m_row_1__ETC___d148;
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wire [14 : 0] SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d143;
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wire [12 : 0] SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d134;
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wire [11 : 0] sb__h11225, sb__h11341, upd__h1621, upd__h1966;
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wire [10 : 0] SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d125;
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wire [8 : 0] SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d116;
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wire [6 : 0] SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d107;
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wire [4 : 0] SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d98;
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wire [2 : 0] SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d89;
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wire upd__h2497;
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// action method enq
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assign RDY_enq =
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m_m_empty_for_enq_wire$wget || m_m_enqP != m_m_deqP_ehr_rl ;
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assign CAN_FIRE_enq =
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m_m_empty_for_enq_wire$wget || m_m_enqP != m_m_deqP_ehr_rl ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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always@(m_m_deqP_ehr_rl or m_m_valid_0_rl or m_m_valid_1_rl)
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begin
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case (m_m_deqP_ehr_rl)
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1'd0: RDY_deq = m_m_valid_0_rl;
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1'd1: RDY_deq = m_m_valid_1_rl;
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endcase
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end
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assign CAN_FIRE_deq = RDY_deq ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first
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assign first =
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{ CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_84_TO_80_ETC__q18,
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SEL_ARR_m_m_row_0_7_BITS_79_TO_16_3_m_m_row_1__ETC___d148,
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CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q19 } ;
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assign RDY_first = RDY_deq ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// rule RL_m_m_canon_deqP
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assign CAN_FIRE_RL_m_m_canon_deqP =
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CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q20 &&
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(m_m_enqP != m_m_deqP_ehr_rl || m_m_valid_0_rl ||
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m_m_valid_1_rl) ;
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assign WILL_FIRE_RL_m_m_canon_deqP =
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CAN_FIRE_RL_m_m_canon_deqP &&
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!EN_specUpdate_incorrectSpeculation ;
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// rule RL_m_m_setWireForEnq
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assign CAN_FIRE_RL_m_m_setWireForEnq = 1'd1 ;
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assign WILL_FIRE_RL_m_m_setWireForEnq = 1'd1 ;
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// rule RL_m_m_valid_0_canon
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assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
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// rule RL_m_m_valid_1_canon
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assign CAN_FIRE_RL_m_m_valid_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_valid_1_canon = 1'd1 ;
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// rule RL_m_m_specBits_0_canon
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assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
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// rule RL_m_m_specBits_1_canon
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assign CAN_FIRE_RL_m_m_specBits_1_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_specBits_1_canon = 1'd1 ;
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// rule RL_m_m_deqP_ehr_canon
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assign CAN_FIRE_RL_m_m_deqP_ehr_canon = 1'd1 ;
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assign WILL_FIRE_RL_m_m_deqP_ehr_canon = 1'd1 ;
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// inputs to muxes for submodule ports
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assign MUX_m_m_valid_0_lat_0$wset_1__SEL_2 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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m_m_specBits_0_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
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assign MUX_m_m_valid_1_lat_0$wset_1__SEL_2 =
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EN_specUpdate_incorrectSpeculation &&
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(specUpdate_incorrectSpeculation_kill_all ||
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m_m_specBits_1_rl[specUpdate_incorrectSpeculation_kill_tag]) ;
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// inlined wires
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assign m_m_valid_0_lat_0$whas =
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EN_deq && m_m_deqP_ehr_rl == 1'd0 ||
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MUX_m_m_valid_0_lat_0$wset_1__SEL_2 ;
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assign m_m_valid_0_lat_1$whas = EN_enq && m_m_enqP == 1'd0 ;
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assign m_m_valid_1_lat_0$whas =
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EN_deq && m_m_deqP_ehr_rl == 1'd1 ||
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MUX_m_m_valid_1_lat_0$wset_1__SEL_2 ;
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assign m_m_valid_1_lat_1$whas = EN_enq && m_m_enqP == 1'd1 ;
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assign m_m_deqP_ehr_lat_0$whas = WILL_FIRE_RL_m_m_canon_deqP || EN_deq ;
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assign m_m_empty_for_enq_wire$wget = !m_m_valid_0_rl && !m_m_valid_1_rl ;
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always@(m_m_enqP or m_m_valid_0_rl or m_m_valid_1_rl)
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begin
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case (m_m_enqP)
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1'd0: m_m_valid_for_enq_wire$wget = m_m_valid_0_rl;
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1'd1: m_m_valid_for_enq_wire$wget = m_m_valid_1_rl;
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endcase
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end
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// register m_m_deqP_ehr_rl
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assign m_m_deqP_ehr_rl$D_IN =
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m_m_deqP_ehr_lat_0$whas ? upd__h2497 : m_m_deqP_ehr_rl ;
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assign m_m_deqP_ehr_rl$EN = 1'd1 ;
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// register m_m_enqP
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assign m_m_enqP$D_IN = m_m_enqP + 1'd1 ;
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assign m_m_enqP$EN = EN_enq ;
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// register m_m_row_0
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assign m_m_row_0$D_IN = enq_x[96:12] ;
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assign m_m_row_0$EN = m_m_valid_0_lat_1$whas ;
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// register m_m_row_1
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assign m_m_row_1$D_IN = enq_x[96:12] ;
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assign m_m_row_1$EN = m_m_valid_1_lat_1$whas ;
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// register m_m_specBits_0_rl
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assign m_m_specBits_0_rl$D_IN =
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EN_specUpdate_correctSpeculation ? upd__h1621 : sb__h11225 ;
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assign m_m_specBits_0_rl$EN = 1'd1 ;
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// register m_m_specBits_1_rl
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assign m_m_specBits_1_rl$D_IN =
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EN_specUpdate_correctSpeculation ? upd__h1966 : sb__h11341 ;
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assign m_m_specBits_1_rl$EN = 1'd1 ;
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// register m_m_valid_0_rl
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assign m_m_valid_0_rl$D_IN =
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m_m_valid_0_lat_1$whas ||
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(m_m_valid_0_lat_0$whas ? 1'd0 : m_m_valid_0_rl) ;
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assign m_m_valid_0_rl$EN = 1'd1 ;
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// register m_m_valid_1_rl
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assign m_m_valid_1_rl$D_IN =
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m_m_valid_1_lat_1$whas ||
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(m_m_valid_1_lat_0$whas ? 1'd0 : m_m_valid_1_rl) ;
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assign m_m_valid_1_rl$EN = 1'd1 ;
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// remaining internal signals
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assign SEL_ARR_m_m_row_0_7_BITS_79_TO_16_3_m_m_row_1__ETC___d148 =
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{ CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_79_TO_16_ETC__q16,
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SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d143,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_0_1_m_m_r_ETC__q17 } ;
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assign SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d107 =
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{ SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d98,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_10_1_m_m__ETC__q6,
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CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_9_1_m_m_r_ETC__q7 } ;
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assign SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d116 =
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{ SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d107,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_8_1_m_m_r_ETC__q8,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_7_1_m_m_r_ETC__q9 } ;
|
|
assign SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d125 =
|
|
{ SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d116,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_6_1_m_m_r_ETC__q10,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_5_1_m_m_r_ETC__q11 } ;
|
|
assign SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d134 =
|
|
{ SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d125,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_4_1_m_m_r_ETC__q12,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_3_1_m_m_r_ETC__q13 } ;
|
|
assign SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d143 =
|
|
{ SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d134,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_2_1_m_m_r_ETC__q14,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_1_1_m_m_r_ETC__q15 } ;
|
|
assign SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d89 =
|
|
{ CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_15_1_m_m__ETC__q1,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_14_1_m_m__ETC__q2,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_13_1_m_m__ETC__q3 } ;
|
|
assign SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d98 =
|
|
{ SEL_ARR_m_m_row_0_7_BIT_15_7_m_m_row_1_9_BIT_1_ETC___d89,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4,
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5 } ;
|
|
assign sb__h11225 =
|
|
m_m_valid_0_lat_1$whas ? enq_x[11:0] : m_m_specBits_0_rl ;
|
|
assign sb__h11341 =
|
|
m_m_valid_1_lat_1$whas ? enq_x[11:0] : m_m_specBits_1_rl ;
|
|
assign upd__h1621 = sb__h11225 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h1966 = sb__h11341 & specUpdate_correctSpeculation_mask ;
|
|
assign upd__h2497 = m_m_deqP_ehr_rl + 1'd1 ;
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_15_1_m_m__ETC__q1 =
|
|
m_m_row_0[15];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_15_1_m_m__ETC__q1 =
|
|
m_m_row_1[15];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_14_1_m_m__ETC__q2 =
|
|
m_m_row_0[14];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_14_1_m_m__ETC__q2 =
|
|
m_m_row_1[14];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_13_1_m_m__ETC__q3 =
|
|
m_m_row_0[13];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_13_1_m_m__ETC__q3 =
|
|
m_m_row_1[13];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4 =
|
|
m_m_row_0[12];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_12_1_m_m__ETC__q4 =
|
|
m_m_row_1[12];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5 =
|
|
m_m_row_0[11];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_11_1_m_m__ETC__q5 =
|
|
m_m_row_1[11];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_10_1_m_m__ETC__q6 =
|
|
m_m_row_0[10];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_10_1_m_m__ETC__q6 =
|
|
m_m_row_1[10];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_9_1_m_m_r_ETC__q7 =
|
|
m_m_row_0[9];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_9_1_m_m_r_ETC__q7 =
|
|
m_m_row_1[9];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_8_1_m_m_r_ETC__q8 =
|
|
m_m_row_0[8];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_8_1_m_m_r_ETC__q8 =
|
|
m_m_row_1[8];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_7_1_m_m_r_ETC__q9 =
|
|
m_m_row_0[7];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_7_1_m_m_r_ETC__q9 =
|
|
m_m_row_1[7];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_6_1_m_m_r_ETC__q10 =
|
|
m_m_row_0[6];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_6_1_m_m_r_ETC__q10 =
|
|
m_m_row_1[6];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_5_1_m_m_r_ETC__q11 =
|
|
m_m_row_0[5];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_5_1_m_m_r_ETC__q11 =
|
|
m_m_row_1[5];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_4_1_m_m_r_ETC__q12 =
|
|
m_m_row_0[4];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_4_1_m_m_r_ETC__q12 =
|
|
m_m_row_1[4];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_3_1_m_m_r_ETC__q13 =
|
|
m_m_row_0[3];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_3_1_m_m_r_ETC__q13 =
|
|
m_m_row_1[3];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_2_1_m_m_r_ETC__q14 =
|
|
m_m_row_0[2];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_2_1_m_m_r_ETC__q14 =
|
|
m_m_row_1[2];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_1_1_m_m_r_ETC__q15 =
|
|
m_m_row_0[1];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_1_1_m_m_r_ETC__q15 =
|
|
m_m_row_1[1];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_79_TO_16_ETC__q16 =
|
|
m_m_row_0[79:16];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_79_TO_16_ETC__q16 =
|
|
m_m_row_1[79:16];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_0_1_m_m_r_ETC__q17 =
|
|
m_m_row_0[0];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BIT_0_1_m_m_r_ETC__q17 =
|
|
m_m_row_1[0];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_row_0 or m_m_row_1)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_84_TO_80_ETC__q18 =
|
|
m_m_row_0[84:80];
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_row_0_BITS_84_TO_80_ETC__q18 =
|
|
m_m_row_1[84:80];
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_specBits_0_rl or m_m_specBits_1_rl)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q19 =
|
|
m_m_specBits_0_rl;
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_m_m_specBits_0_rl_1_m_m_ETC__q19 =
|
|
m_m_specBits_1_rl;
|
|
endcase
|
|
end
|
|
always@(m_m_deqP_ehr_rl or m_m_valid_0_rl or m_m_valid_1_rl)
|
|
begin
|
|
case (m_m_deqP_ehr_rl)
|
|
1'd0:
|
|
CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q20 =
|
|
!m_m_valid_0_rl;
|
|
1'd1:
|
|
CASE_m_m_deqP_ehr_rl_0_NOT_m_m_valid_0_rl_1_NO_ETC__q20 =
|
|
!m_m_valid_1_rl;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_m_deqP_ehr_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_m_deqP_ehr_rl$EN)
|
|
m_m_deqP_ehr_rl <= `BSV_ASSIGNMENT_DELAY m_m_deqP_ehr_rl$D_IN;
|
|
if (m_m_enqP$EN) m_m_enqP <= `BSV_ASSIGNMENT_DELAY m_m_enqP$D_IN;
|
|
if (m_m_specBits_0_rl$EN)
|
|
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
|
|
if (m_m_specBits_1_rl$EN)
|
|
m_m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_1_rl$D_IN;
|
|
if (m_m_valid_0_rl$EN)
|
|
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
|
|
if (m_m_valid_1_rl$EN)
|
|
m_m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_1_rl$D_IN;
|
|
end
|
|
if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
|
|
if (m_m_row_1$EN) m_m_row_1 <= `BSV_ASSIGNMENT_DELAY m_m_row_1$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_m_deqP_ehr_rl = 1'h0;
|
|
m_m_enqP = 1'h0;
|
|
m_m_row_0 = 85'h0AAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_row_1 = 85'h0AAAAAAAAAAAAAAAAAAAAA;
|
|
m_m_specBits_0_rl = 12'hAAA;
|
|
m_m_specBits_1_rl = 12'hAAA;
|
|
m_m_valid_0_rl = 1'h0;
|
|
m_m_valid_1_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_enq && m_m_valid_for_enq_wire$wget)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkLSQIssueLdQ
|
|
|