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72175d87dbf736e56e5702f5e57f65824a9ab5ab
Toooba/src_SSITH_P3/Verilog_RTL/mkAluRegToExeFifo.v
rsnikhil 53aacff7c5 Changes to support 'C' extension (compressed instructions). Details follow. 
>----------------
Status and outlook:

    For RV64GC, out of 229 standard ISA tests, 202 PASS, 27 FAIL.
    Below is a list of current failures, current diagnoses, and outlook.

    'C' instructions:
        rv64uc-v-rvc

        Diagnosis: error in saved regs during instruction page fault
            when a 32-bit instruction straddles a page boundary and
            the second 16-bits encounters a page fault.

            Note: the corresponding rv64uc-p-rvc passes, containing
            the same set of tests except for the virtual-memory
            aspect, so we expect this test to pass once this issue is
            fixed.

        Outlook: Target date for fix: 2019-Apr-09 (today)

    System instructions:
        rv64mi-p-access
        rv64mi-p-csr
        rv64si-p-dirty
        rv64mi-p-illegal

        Diagnosis: we do not have accurate diagnoses yet, although
            some symptoms look similar to what we saw with earlier
            processors (these test various corner-cases of system
            instructions).

        Outlook: Target date for fix: 2019-Apr-15

    'F' and 'D' instructions
        rv64uf-p-fadd        rv64uf-v-fadd
        rv64uf-p-fcmp        rv64uf-v-fcmp
        rv64uf-p-fdiv        rv64uf-v-fdiv
        rv64uf-p-fmin        rv64uf-v-fmin

        rv64ud-p-fadd        rv64ud-v-fadd
        rv64ud-p-fcmp        rv64ud-v-fcmp
        rv64ud-p-fdiv        rv64ud-v-fdiv
        rv64ud-p-fmadd       rv64ud-v-fmadd
        rv64ud-p-fmin        rv64ud-v-fmin
        rv64ud-p-ldst        rv64ud-v-ldst
        rv64ud-p-move        rv64ud-v-move

        Diagnosis: These seem to be simulation-only errors. Simulation
            uses some quick-and-dirty floating-point "model" modules
            written by the MIT authors, which are not accurate.  All
            the errors seem to be regarding incomplete treatment of
            NaNs in the models.  These errors should not happen in
            FPGA since those use Xilinx IP modules instead.  MIT has
            been booting Linux with the Xilinx IP modules, lending
            more confidence in the FPGA version.

            The actual number of root-cause failures is likely to be
            smaller than the list.  For example, the 'fadd' test has
            four variants: {uf/ud} x {-p-/-v-}; they all likely need a
            comon fix.

        Outlook: Target date: 2019-Apr-30
            [Lower priority, since FPGA versions should be ok even now.]

>----------------
Detailed comments on file changes

New files:
    Doc/micro2018.pdf
        MIT's paper on RISCY-OOO at IEEE Micro
    src_Core/CPU/CPU_Decode_C.bsv
        Function to expand 'C' instrs to 32-bit counterparts, taken from Piccolo/Flute

Modified files:
    src_Core/CPU/Core.bsv
        Added rob_getOrig_Inst method

    src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
        Added 'orig_inst' stuff, $displays

    src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
        Mostly verbosity stuff, including printing out brief instruction trace similar to Piccolo/Flute.

    src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
        Major changes for 'C', including call to Decode_C function from Piccolo/Flute
        Pass orig_inst to downpipe.

    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        Added 'orig_inst', input from FetchStage and passed on to ROB
        Tweaked PC+4 check to accommodate 'C' instructions.

    src_Core/RISCY_OOO/procs/lib/BrPred.bsv
        Fixed 'decodeBrPred' to accommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/Exec.bsv
        Fixed 'brAddrCalc', 'getControlFlow', 'basicExec' to acommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/MemLoader.bsv
        Switched off 'verbose' by default

    src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
        Added 'C' to MISA, 'getExtensionBits'

    src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
        Added 'orig_inst' register to basic cell, and methods to set/access.

    src_Core/RISCY_OOO/procs/lib/Types.bsv
        Added typedefs for 'C' instructions
>----------------
2019-04-09 13:50:16 -04:00

505 lines
14 KiB
Verilog
Raw Blame History

//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_enq O 1
// RDY_deq O 1
// first O 422
// RDY_first O 1
// RDY_specUpdate_incorrectSpeculation O 1 const
// RDY_specUpdate_correctSpeculation O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// enq_x I 422
// specUpdate_incorrectSpeculation_kill_all I 1
// specUpdate_incorrectSpeculation_kill_tag I 4
// specUpdate_correctSpeculation_mask I 12
// EN_enq I 1
// EN_deq I 1
// EN_specUpdate_incorrectSpeculation I 1
// EN_specUpdate_correctSpeculation I 1
//
// Combinational paths from inputs to outputs:
// (specUpdate_incorrectSpeculation_kill_all,
// specUpdate_incorrectSpeculation_kill_tag,
// EN_deq,
// EN_specUpdate_incorrectSpeculation) -> RDY_enq
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkAluRegToExeFifo(CLK,
RST_N,
enq_x,
EN_enq,
RDY_enq,
EN_deq,
RDY_deq,
first,
RDY_first,
specUpdate_incorrectSpeculation_kill_all,
specUpdate_incorrectSpeculation_kill_tag,
EN_specUpdate_incorrectSpeculation,
RDY_specUpdate_incorrectSpeculation,
specUpdate_correctSpeculation_mask,
EN_specUpdate_correctSpeculation,
RDY_specUpdate_correctSpeculation);
input CLK;
input RST_N;
// action method enq
input [421 : 0] enq_x;
input EN_enq;
output RDY_enq;
// action method deq
input EN_deq;
output RDY_deq;
// value method first
output [421 : 0] first;
output RDY_first;
// action method specUpdate_incorrectSpeculation
input specUpdate_incorrectSpeculation_kill_all;
input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
input EN_specUpdate_incorrectSpeculation;
output RDY_specUpdate_incorrectSpeculation;
// action method specUpdate_correctSpeculation
input [11 : 0] specUpdate_correctSpeculation_mask;
input EN_specUpdate_correctSpeculation;
output RDY_specUpdate_correctSpeculation;
// signals for module outputs
wire [421 : 0] first;
wire RDY_deq,
RDY_enq,
RDY_first,
RDY_specUpdate_correctSpeculation,
RDY_specUpdate_incorrectSpeculation;
// inlined wires
wire [11 : 0] m_m_specBits_0_lat_1$wget;
wire m_m_valid_0_lat_0$whas;
// register m_m_row_0
reg [409 : 0] m_m_row_0;
wire [409 : 0] m_m_row_0$D_IN;
wire m_m_row_0$EN;
// register m_m_specBits_0_rl
reg [11 : 0] m_m_specBits_0_rl;
wire [11 : 0] m_m_specBits_0_rl$D_IN;
wire m_m_specBits_0_rl$EN;
// register m_m_valid_0_rl
reg m_m_valid_0_rl;
wire m_m_valid_0_rl$D_IN, m_m_valid_0_rl$EN;
// ports of submodule m_m_deqP_ehr_dummy2_0
wire m_m_deqP_ehr_dummy2_0$D_IN, m_m_deqP_ehr_dummy2_0$EN;
// ports of submodule m_m_deqP_ehr_dummy2_1
wire m_m_deqP_ehr_dummy2_1$D_IN, m_m_deqP_ehr_dummy2_1$EN;
// ports of submodule m_m_specBits_0_dummy2_0
wire m_m_specBits_0_dummy2_0$D_IN,
m_m_specBits_0_dummy2_0$EN,
m_m_specBits_0_dummy2_0$Q_OUT;
// ports of submodule m_m_specBits_0_dummy2_1
wire m_m_specBits_0_dummy2_1$D_IN,
m_m_specBits_0_dummy2_1$EN,
m_m_specBits_0_dummy2_1$Q_OUT;
// ports of submodule m_m_valid_0_dummy2_0
wire m_m_valid_0_dummy2_0$D_IN,
m_m_valid_0_dummy2_0$EN,
m_m_valid_0_dummy2_0$Q_OUT;
// ports of submodule m_m_valid_0_dummy2_1
wire m_m_valid_0_dummy2_1$D_IN,
m_m_valid_0_dummy2_1$EN,
m_m_valid_0_dummy2_1$Q_OUT;
// rule scheduling signals
wire CAN_FIRE_RL_m_m_specBits_0_canon,
CAN_FIRE_RL_m_m_valid_0_canon,
CAN_FIRE_deq,
CAN_FIRE_enq,
CAN_FIRE_specUpdate_correctSpeculation,
CAN_FIRE_specUpdate_incorrectSpeculation,
WILL_FIRE_RL_m_m_specBits_0_canon,
WILL_FIRE_RL_m_m_valid_0_canon,
WILL_FIRE_deq,
WILL_FIRE_enq,
WILL_FIRE_specUpdate_correctSpeculation,
WILL_FIRE_specUpdate_incorrectSpeculation;
// inputs to muxes for submodule ports
wire MUX_m_m_valid_0_dummy2_0$write_1__SEL_1;
// remaining internal signals
reg [20 : 0] CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2,
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5;
reg [11 : 0] CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3,
CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6;
reg [2 : 0] CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1,
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4;
wire [11 : 0] IF_m_m_specBits_0_dummy2_0_read__61_AND_m_m_sp_ETC___d264,
IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13,
sb__h10143,
upd__h2322;
// action method enq
assign RDY_enq =
!m_m_valid_0_dummy2_1$Q_OUT ||
(m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl) ;
assign CAN_FIRE_enq =
!m_m_valid_0_dummy2_1$Q_OUT ||
(m_m_valid_0_lat_0$whas ? !1'd0 : !m_m_valid_0_rl) ;
assign WILL_FIRE_enq = EN_enq ;
// action method deq
assign RDY_deq =
m_m_valid_0_dummy2_0$Q_OUT && m_m_valid_0_dummy2_1$Q_OUT &&
m_m_valid_0_rl ;
assign CAN_FIRE_deq = RDY_deq ;
assign WILL_FIRE_deq = EN_deq ;
// value method first
assign first =
{ m_m_row_0[409:405],
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5,
m_m_row_0[383],
CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6,
m_m_row_0[370:0],
IF_m_m_specBits_0_dummy2_0_read__61_AND_m_m_sp_ETC___d264 } ;
assign RDY_first = RDY_deq ;
// action method specUpdate_incorrectSpeculation
assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
assign WILL_FIRE_specUpdate_incorrectSpeculation =
EN_specUpdate_incorrectSpeculation ;
// action method specUpdate_correctSpeculation
assign RDY_specUpdate_correctSpeculation = 1'd1 ;
assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
assign WILL_FIRE_specUpdate_correctSpeculation =
EN_specUpdate_correctSpeculation ;
// submodule m_m_deqP_ehr_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_deqP_ehr_dummy2_0(.CLK(CLK),
.D_IN(m_m_deqP_ehr_dummy2_0$D_IN),
.EN(m_m_deqP_ehr_dummy2_0$EN),
.Q_OUT());
// submodule m_m_deqP_ehr_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_deqP_ehr_dummy2_1(.CLK(CLK),
.D_IN(m_m_deqP_ehr_dummy2_1$D_IN),
.EN(m_m_deqP_ehr_dummy2_1$EN),
.Q_OUT());
// submodule m_m_specBits_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_0(.CLK(CLK),
.D_IN(m_m_specBits_0_dummy2_0$D_IN),
.EN(m_m_specBits_0_dummy2_0$EN),
.Q_OUT(m_m_specBits_0_dummy2_0$Q_OUT));
// submodule m_m_specBits_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_specBits_0_dummy2_1(.CLK(CLK),
.D_IN(m_m_specBits_0_dummy2_1$D_IN),
.EN(m_m_specBits_0_dummy2_1$EN),
.Q_OUT(m_m_specBits_0_dummy2_1$Q_OUT));
// submodule m_m_valid_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_0(.CLK(CLK),
.D_IN(m_m_valid_0_dummy2_0$D_IN),
.EN(m_m_valid_0_dummy2_0$EN),
.Q_OUT(m_m_valid_0_dummy2_0$Q_OUT));
// submodule m_m_valid_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_m_valid_0_dummy2_1(.CLK(CLK),
.D_IN(m_m_valid_0_dummy2_1$D_IN),
.EN(m_m_valid_0_dummy2_1$EN),
.Q_OUT(m_m_valid_0_dummy2_1$Q_OUT));
// rule RL_m_m_valid_0_canon
assign CAN_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_valid_0_canon = 1'd1 ;
// rule RL_m_m_specBits_0_canon
assign CAN_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
assign WILL_FIRE_RL_m_m_specBits_0_canon = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 =
EN_specUpdate_incorrectSpeculation &&
(specUpdate_incorrectSpeculation_kill_all ||
IF_m_m_specBits_0_dummy2_0_read__61_AND_m_m_sp_ETC___d264[specUpdate_incorrectSpeculation_kill_tag]) ;
// inlined wires
assign m_m_valid_0_lat_0$whas =
MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ;
assign m_m_specBits_0_lat_1$wget =
sb__h10143 & specUpdate_correctSpeculation_mask ;
// register m_m_row_0
assign m_m_row_0$D_IN =
{ enq_x[421:417],
CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2,
enq_x[395],
CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3,
enq_x[382:12] } ;
assign m_m_row_0$EN = EN_enq ;
// register m_m_specBits_0_rl
assign m_m_specBits_0_rl$D_IN =
EN_specUpdate_correctSpeculation ?
upd__h2322 :
IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 ;
assign m_m_specBits_0_rl$EN = 1'd1 ;
// register m_m_valid_0_rl
assign m_m_valid_0_rl$D_IN =
EN_enq || (m_m_valid_0_lat_0$whas ? 1'd0 : m_m_valid_0_rl) ;
assign m_m_valid_0_rl$EN = 1'd1 ;
// submodule m_m_deqP_ehr_dummy2_0
assign m_m_deqP_ehr_dummy2_0$D_IN = 1'd1 ;
assign m_m_deqP_ehr_dummy2_0$EN = EN_deq ;
// submodule m_m_deqP_ehr_dummy2_1
assign m_m_deqP_ehr_dummy2_1$D_IN = 1'b0 ;
assign m_m_deqP_ehr_dummy2_1$EN = 1'b0 ;
// submodule m_m_specBits_0_dummy2_0
assign m_m_specBits_0_dummy2_0$D_IN = 1'd1 ;
assign m_m_specBits_0_dummy2_0$EN = EN_enq ;
// submodule m_m_specBits_0_dummy2_1
assign m_m_specBits_0_dummy2_1$D_IN = 1'd1 ;
assign m_m_specBits_0_dummy2_1$EN = EN_specUpdate_correctSpeculation ;
// submodule m_m_valid_0_dummy2_0
assign m_m_valid_0_dummy2_0$D_IN = 1'd1 ;
assign m_m_valid_0_dummy2_0$EN =
MUX_m_m_valid_0_dummy2_0$write_1__SEL_1 || EN_deq ;
// submodule m_m_valid_0_dummy2_1
assign m_m_valid_0_dummy2_1$D_IN = 1'd1 ;
assign m_m_valid_0_dummy2_1$EN = EN_enq ;
// remaining internal signals
assign IF_m_m_specBits_0_dummy2_0_read__61_AND_m_m_sp_ETC___d264 =
(m_m_specBits_0_dummy2_0$Q_OUT &&
m_m_specBits_0_dummy2_1$Q_OUT) ?
m_m_specBits_0_rl :
12'd0 ;
assign IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 =
EN_enq ? enq_x[11:0] : m_m_specBits_0_rl ;
assign sb__h10143 =
m_m_specBits_0_dummy2_1$Q_OUT ?
IF_m_m_specBits_0_lat_0_whas__0_THEN_m_m_specB_ETC___d13 :
12'd0 ;
assign upd__h2322 = m_m_specBits_0_lat_1$wget ;
always@(enq_x)
begin
case (enq_x[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1 =
enq_x[399:397];
default: CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1 = 3'd7;
endcase
end
always@(enq_x or CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1)
begin
case (enq_x[416:414])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
enq_x[416:396];
3'd4:
CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
{ enq_x[416:414],
9'h0AA,
enq_x[404:400],
CASE_enq_x_BITS_399_TO_397_0_enq_x_BITS_399_TO_ETC__q1,
enq_x[396] };
default: CASE_enq_x_BITS_416_TO_414_0_enq_x_BITS_416_TO_ETC__q2 =
21'd1485482;
endcase
end
always@(enq_x)
begin
case (enq_x[394:383])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3 =
enq_x[394:383];
default: CASE_enq_x_BITS_394_TO_383_1_enq_x_BITS_394_TO_ETC__q3 =
12'd2303;
endcase
end
always@(m_m_row_0)
begin
case (m_m_row_0[387:385])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4 =
m_m_row_0[387:385];
default: CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4 = 3'd7;
endcase
end
always@(m_m_row_0 or CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4)
begin
case (m_m_row_0[404:402])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
m_m_row_0[404:384];
3'd4:
CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
{ m_m_row_0[404:402],
9'h0AA,
m_m_row_0[392:388],
CASE_m_m_row_0_BITS_387_TO_385_0_m_m_row_0_BIT_ETC__q4,
m_m_row_0[384] };
default: CASE_m_m_row_0_BITS_404_TO_402_0_m_m_row_0_BIT_ETC__q5 =
21'd1485482;
endcase
end
always@(m_m_row_0)
begin
case (m_m_row_0[382:371])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6 =
m_m_row_0[382:371];
default: CASE_m_m_row_0_BITS_382_TO_371_1_m_m_row_0_BIT_ETC__q6 =
12'd2303;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (m_m_specBits_0_rl$EN)
m_m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_specBits_0_rl$D_IN;
if (m_m_valid_0_rl$EN)
m_m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_m_valid_0_rl$D_IN;
end
if (m_m_row_0$EN) m_m_row_0 <= `BSV_ASSIGNMENT_DELAY m_m_row_0$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_m_row_0 =
410'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
m_m_specBits_0_rl = 12'hAAA;
m_m_valid_0_rl = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkAluRegToExeFifo
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