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Toooba/src_SSITH_P3/Verilog_RTL/mkProc.v
rsnikhil 53aacff7c5 Changes to support 'C' extension (compressed instructions). Details follow. 
>----------------
Status and outlook:

    For RV64GC, out of 229 standard ISA tests, 202 PASS, 27 FAIL.
    Below is a list of current failures, current diagnoses, and outlook.

    'C' instructions:
        rv64uc-v-rvc

        Diagnosis: error in saved regs during instruction page fault
            when a 32-bit instruction straddles a page boundary and
            the second 16-bits encounters a page fault.

            Note: the corresponding rv64uc-p-rvc passes, containing
            the same set of tests except for the virtual-memory
            aspect, so we expect this test to pass once this issue is
            fixed.

        Outlook: Target date for fix: 2019-Apr-09 (today)

    System instructions:
        rv64mi-p-access
        rv64mi-p-csr
        rv64si-p-dirty
        rv64mi-p-illegal

        Diagnosis: we do not have accurate diagnoses yet, although
            some symptoms look similar to what we saw with earlier
            processors (these test various corner-cases of system
            instructions).

        Outlook: Target date for fix: 2019-Apr-15

    'F' and 'D' instructions
        rv64uf-p-fadd        rv64uf-v-fadd
        rv64uf-p-fcmp        rv64uf-v-fcmp
        rv64uf-p-fdiv        rv64uf-v-fdiv
        rv64uf-p-fmin        rv64uf-v-fmin

        rv64ud-p-fadd        rv64ud-v-fadd
        rv64ud-p-fcmp        rv64ud-v-fcmp
        rv64ud-p-fdiv        rv64ud-v-fdiv
        rv64ud-p-fmadd       rv64ud-v-fmadd
        rv64ud-p-fmin        rv64ud-v-fmin
        rv64ud-p-ldst        rv64ud-v-ldst
        rv64ud-p-move        rv64ud-v-move

        Diagnosis: These seem to be simulation-only errors. Simulation
            uses some quick-and-dirty floating-point "model" modules
            written by the MIT authors, which are not accurate.  All
            the errors seem to be regarding incomplete treatment of
            NaNs in the models.  These errors should not happen in
            FPGA since those use Xilinx IP modules instead.  MIT has
            been booting Linux with the Xilinx IP modules, lending
            more confidence in the FPGA version.

            The actual number of root-cause failures is likely to be
            smaller than the list.  For example, the 'fadd' test has
            four variants: {uf/ud} x {-p-/-v-}; they all likely need a
            comon fix.

        Outlook: Target date: 2019-Apr-30
            [Lower priority, since FPGA versions should be ok even now.]

>----------------
Detailed comments on file changes

New files:
    Doc/micro2018.pdf
        MIT's paper on RISCY-OOO at IEEE Micro
    src_Core/CPU/CPU_Decode_C.bsv
        Function to expand 'C' instrs to 32-bit counterparts, taken from Piccolo/Flute

Modified files:
    src_Core/CPU/Core.bsv
        Added rob_getOrig_Inst method

    src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
        Added 'orig_inst' stuff, $displays

    src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
        Mostly verbosity stuff, including printing out brief instruction trace similar to Piccolo/Flute.

    src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
        Major changes for 'C', including call to Decode_C function from Piccolo/Flute
        Pass orig_inst to downpipe.

    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        Added 'orig_inst', input from FetchStage and passed on to ROB
        Tweaked PC+4 check to accommodate 'C' instructions.

    src_Core/RISCY_OOO/procs/lib/BrPred.bsv
        Fixed 'decodeBrPred' to accommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/Exec.bsv
        Fixed 'brAddrCalc', 'getControlFlow', 'basicExec' to acommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/MemLoader.bsv
        Switched off 'verbose' by default

    src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
        Added 'C' to MISA, 'getExtensionBits'

    src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
        Added 'orig_inst' register to basic cell, and methods to set/access.

    src_Core/RISCY_OOO/procs/lib/Types.bsv
        Added typedefs for 'C' instructions
>----------------
2019-04-09 13:50:16 -04:00

10174 lines
408 KiB
Verilog
Raw Blame History

//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_hart0_server_reset_request_put O 1 reg
// RDY_hart0_server_reset_response_get O 1 reg
// RDY_start O 1
// master0_awvalid O 1
// master0_awid O 4 reg
// master0_awaddr O 64 reg
// master0_awlen O 8 reg
// master0_awsize O 3 reg
// master0_awburst O 2 reg
// master0_awlock O 1 reg
// master0_awcache O 4 reg
// master0_awprot O 3 reg
// master0_awqos O 4 reg
// master0_awregion O 4 reg
// master0_wvalid O 1
// master0_wid O 4 reg
// master0_wdata O 64 reg
// master0_wstrb O 8 reg
// master0_wlast O 1 reg
// master0_bready O 1
// master0_arvalid O 1
// master0_arid O 4 reg
// master0_araddr O 64 reg
// master0_arlen O 8 reg
// master0_arsize O 3 reg
// master0_arburst O 2 reg
// master0_arlock O 1 reg
// master0_arcache O 4 reg
// master0_arprot O 3 reg
// master0_arqos O 4 reg
// master0_arregion O 4 reg
// master0_rready O 1
// master1_awvalid O 1
// master1_awid O 4 reg
// master1_awaddr O 64 reg
// master1_awlen O 8 reg
// master1_awsize O 3 reg
// master1_awburst O 2 reg
// master1_awlock O 1 reg
// master1_awcache O 4 reg
// master1_awprot O 3 reg
// master1_awqos O 4 reg
// master1_awregion O 4 reg
// master1_wvalid O 1
// master1_wid O 4 reg
// master1_wdata O 64 reg
// master1_wstrb O 8 reg
// master1_wlast O 1 reg
// master1_bready O 1
// master1_arvalid O 1
// master1_arid O 4 reg
// master1_araddr O 64 reg
// master1_arlen O 8 reg
// master1_arsize O 3 reg
// master1_arburst O 2 reg
// master1_arlock O 1 reg
// master1_arcache O 4 reg
// master1_arprot O 3 reg
// master1_arqos O 4 reg
// master1_arregion O 4 reg
// master1_rready O 1
// RDY_set_verbosity O 1 const
// trace_data_out_get O 362 reg
// RDY_trace_data_out_get O 1 reg
// RDY_hart0_server_run_halt_request_put O 1 reg
// hart0_server_run_halt_response_get O 1 reg
// RDY_hart0_server_run_halt_response_get O 1 reg
// RDY_hart0_put_other_req_put O 1 const
// RDY_hart0_gpr_mem_server_request_put O 1 reg
// hart0_gpr_mem_server_response_get O 65 reg
// RDY_hart0_gpr_mem_server_response_get O 1 reg
// RDY_hart0_fpr_mem_server_request_put O 1 reg
// hart0_fpr_mem_server_response_get O 65 reg
// RDY_hart0_fpr_mem_server_response_get O 1 reg
// RDY_hart0_csr_mem_server_request_put O 1 reg
// hart0_csr_mem_server_response_get O 65 reg
// RDY_hart0_csr_mem_server_response_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// start_startpc I 64
// start_tohostAddr I 64 reg
// start_fromhostAddr I 64 reg
// master0_awready I 1
// master0_wready I 1
// master0_bvalid I 1
// master0_bid I 4 reg
// master0_bresp I 2 reg
// master0_arready I 1
// master0_rvalid I 1
// master0_rid I 4 reg
// master0_rdata I 64 reg
// master0_rresp I 2 reg
// master0_rlast I 1 reg
// master1_awready I 1
// master1_wready I 1
// master1_bvalid I 1
// master1_bid I 4 reg
// master1_bresp I 2 reg
// master1_arready I 1
// master1_rvalid I 1
// master1_rid I 4 reg
// master1_rdata I 64 reg
// master1_rresp I 2 reg
// master1_rlast I 1 reg
// m_external_interrupt_req_set_not_clear I 1
// s_external_interrupt_req_set_not_clear I 1
// debug_external_interrupt_req_set_not_clear I 1
// non_maskable_interrupt_req_set_not_clear I 1 unused
// set_verbosity_verbosity I 4
// hart0_server_run_halt_request_put I 1 reg
// hart0_put_other_req_put I 4
// hart0_gpr_mem_server_request_put I 70 reg
// hart0_fpr_mem_server_request_put I 70 reg
// hart0_csr_mem_server_request_put I 77 reg
// EN_hart0_server_reset_request_put I 1
// EN_hart0_server_reset_response_get I 1
// EN_start I 1
// EN_set_verbosity I 1
// EN_hart0_server_run_halt_request_put I 1
// EN_hart0_put_other_req_put I 1
// EN_hart0_gpr_mem_server_request_put I 1
// EN_hart0_fpr_mem_server_request_put I 1
// EN_hart0_csr_mem_server_request_put I 1
// EN_trace_data_out_get I 1
// EN_hart0_server_run_halt_response_get I 1
// EN_hart0_gpr_mem_server_response_get I 1
// EN_hart0_fpr_mem_server_response_get I 1
// EN_hart0_csr_mem_server_response_get I 1
//
// Combinational paths from inputs to outputs:
// (master0_awready, master0_wready) -> master0_bready
// (master1_awready, master1_wready) -> master1_bready
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkProc(CLK,
RST_N,
EN_hart0_server_reset_request_put,
RDY_hart0_server_reset_request_put,
EN_hart0_server_reset_response_get,
RDY_hart0_server_reset_response_get,
start_startpc,
start_tohostAddr,
start_fromhostAddr,
EN_start,
RDY_start,
master0_awvalid,
master0_awid,
master0_awaddr,
master0_awlen,
master0_awsize,
master0_awburst,
master0_awlock,
master0_awcache,
master0_awprot,
master0_awqos,
master0_awregion,
master0_awready,
master0_wvalid,
master0_wid,
master0_wdata,
master0_wstrb,
master0_wlast,
master0_wready,
master0_bvalid,
master0_bid,
master0_bresp,
master0_bready,
master0_arvalid,
master0_arid,
master0_araddr,
master0_arlen,
master0_arsize,
master0_arburst,
master0_arlock,
master0_arcache,
master0_arprot,
master0_arqos,
master0_arregion,
master0_arready,
master0_rvalid,
master0_rid,
master0_rdata,
master0_rresp,
master0_rlast,
master0_rready,
master1_awvalid,
master1_awid,
master1_awaddr,
master1_awlen,
master1_awsize,
master1_awburst,
master1_awlock,
master1_awcache,
master1_awprot,
master1_awqos,
master1_awregion,
master1_awready,
master1_wvalid,
master1_wid,
master1_wdata,
master1_wstrb,
master1_wlast,
master1_wready,
master1_bvalid,
master1_bid,
master1_bresp,
master1_bready,
master1_arvalid,
master1_arid,
master1_araddr,
master1_arlen,
master1_arsize,
master1_arburst,
master1_arlock,
master1_arcache,
master1_arprot,
master1_arqos,
master1_arregion,
master1_arready,
master1_rvalid,
master1_rid,
master1_rdata,
master1_rresp,
master1_rlast,
master1_rready,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
debug_external_interrupt_req_set_not_clear,
non_maskable_interrupt_req_set_not_clear,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_trace_data_out_get,
trace_data_out_get,
RDY_trace_data_out_get,
hart0_server_run_halt_request_put,
EN_hart0_server_run_halt_request_put,
RDY_hart0_server_run_halt_request_put,
EN_hart0_server_run_halt_response_get,
hart0_server_run_halt_response_get,
RDY_hart0_server_run_halt_response_get,
hart0_put_other_req_put,
EN_hart0_put_other_req_put,
RDY_hart0_put_other_req_put,
hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_response_get,
hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
RDY_hart0_fpr_mem_server_response_get,
hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_response_get,
hart0_csr_mem_server_response_get,
RDY_hart0_csr_mem_server_response_get);
input CLK;
input RST_N;
// action method hart0_server_reset_request_put
input EN_hart0_server_reset_request_put;
output RDY_hart0_server_reset_request_put;
// action method hart0_server_reset_response_get
input EN_hart0_server_reset_response_get;
output RDY_hart0_server_reset_response_get;
// action method start
input [63 : 0] start_startpc;
input [63 : 0] start_tohostAddr;
input [63 : 0] start_fromhostAddr;
input EN_start;
output RDY_start;
// value method master0_m_awvalid
output master0_awvalid;
// value method master0_m_awid
output [3 : 0] master0_awid;
// value method master0_m_awaddr
output [63 : 0] master0_awaddr;
// value method master0_m_awlen
output [7 : 0] master0_awlen;
// value method master0_m_awsize
output [2 : 0] master0_awsize;
// value method master0_m_awburst
output [1 : 0] master0_awburst;
// value method master0_m_awlock
output master0_awlock;
// value method master0_m_awcache
output [3 : 0] master0_awcache;
// value method master0_m_awprot
output [2 : 0] master0_awprot;
// value method master0_m_awqos
output [3 : 0] master0_awqos;
// value method master0_m_awregion
output [3 : 0] master0_awregion;
// value method master0_m_awuser
// action method master0_m_awready
input master0_awready;
// value method master0_m_wvalid
output master0_wvalid;
// value method master0_m_wid
output [3 : 0] master0_wid;
// value method master0_m_wdata
output [63 : 0] master0_wdata;
// value method master0_m_wstrb
output [7 : 0] master0_wstrb;
// value method master0_m_wlast
output master0_wlast;
// value method master0_m_wuser
// action method master0_m_wready
input master0_wready;
// action method master0_m_bvalid
input master0_bvalid;
input [3 : 0] master0_bid;
input [1 : 0] master0_bresp;
// value method master0_m_bready
output master0_bready;
// value method master0_m_arvalid
output master0_arvalid;
// value method master0_m_arid
output [3 : 0] master0_arid;
// value method master0_m_araddr
output [63 : 0] master0_araddr;
// value method master0_m_arlen
output [7 : 0] master0_arlen;
// value method master0_m_arsize
output [2 : 0] master0_arsize;
// value method master0_m_arburst
output [1 : 0] master0_arburst;
// value method master0_m_arlock
output master0_arlock;
// value method master0_m_arcache
output [3 : 0] master0_arcache;
// value method master0_m_arprot
output [2 : 0] master0_arprot;
// value method master0_m_arqos
output [3 : 0] master0_arqos;
// value method master0_m_arregion
output [3 : 0] master0_arregion;
// value method master0_m_aruser
// action method master0_m_arready
input master0_arready;
// action method master0_m_rvalid
input master0_rvalid;
input [3 : 0] master0_rid;
input [63 : 0] master0_rdata;
input [1 : 0] master0_rresp;
input master0_rlast;
// value method master0_m_rready
output master0_rready;
// value method master1_m_awvalid
output master1_awvalid;
// value method master1_m_awid
output [3 : 0] master1_awid;
// value method master1_m_awaddr
output [63 : 0] master1_awaddr;
// value method master1_m_awlen
output [7 : 0] master1_awlen;
// value method master1_m_awsize
output [2 : 0] master1_awsize;
// value method master1_m_awburst
output [1 : 0] master1_awburst;
// value method master1_m_awlock
output master1_awlock;
// value method master1_m_awcache
output [3 : 0] master1_awcache;
// value method master1_m_awprot
output [2 : 0] master1_awprot;
// value method master1_m_awqos
output [3 : 0] master1_awqos;
// value method master1_m_awregion
output [3 : 0] master1_awregion;
// value method master1_m_awuser
// action method master1_m_awready
input master1_awready;
// value method master1_m_wvalid
output master1_wvalid;
// value method master1_m_wid
output [3 : 0] master1_wid;
// value method master1_m_wdata
output [63 : 0] master1_wdata;
// value method master1_m_wstrb
output [7 : 0] master1_wstrb;
// value method master1_m_wlast
output master1_wlast;
// value method master1_m_wuser
// action method master1_m_wready
input master1_wready;
// action method master1_m_bvalid
input master1_bvalid;
input [3 : 0] master1_bid;
input [1 : 0] master1_bresp;
// value method master1_m_bready
output master1_bready;
// value method master1_m_arvalid
output master1_arvalid;
// value method master1_m_arid
output [3 : 0] master1_arid;
// value method master1_m_araddr
output [63 : 0] master1_araddr;
// value method master1_m_arlen
output [7 : 0] master1_arlen;
// value method master1_m_arsize
output [2 : 0] master1_arsize;
// value method master1_m_arburst
output [1 : 0] master1_arburst;
// value method master1_m_arlock
output master1_arlock;
// value method master1_m_arcache
output [3 : 0] master1_arcache;
// value method master1_m_arprot
output [2 : 0] master1_arprot;
// value method master1_m_arqos
output [3 : 0] master1_arqos;
// value method master1_m_arregion
output [3 : 0] master1_arregion;
// value method master1_m_aruser
// action method master1_m_arready
input master1_arready;
// action method master1_m_rvalid
input master1_rvalid;
input [3 : 0] master1_rid;
input [63 : 0] master1_rdata;
input [1 : 0] master1_rresp;
input master1_rlast;
// value method master1_m_rready
output master1_rready;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method debug_external_interrupt_req
input debug_external_interrupt_req_set_not_clear;
// action method non_maskable_interrupt_req
input non_maskable_interrupt_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// actionvalue method trace_data_out_get
input EN_trace_data_out_get;
output [361 : 0] trace_data_out_get;
output RDY_trace_data_out_get;
// action method hart0_server_run_halt_request_put
input hart0_server_run_halt_request_put;
input EN_hart0_server_run_halt_request_put;
output RDY_hart0_server_run_halt_request_put;
// actionvalue method hart0_server_run_halt_response_get
input EN_hart0_server_run_halt_response_get;
output hart0_server_run_halt_response_get;
output RDY_hart0_server_run_halt_response_get;
// action method hart0_put_other_req_put
input [3 : 0] hart0_put_other_req_put;
input EN_hart0_put_other_req_put;
output RDY_hart0_put_other_req_put;
// action method hart0_gpr_mem_server_request_put
input [69 : 0] hart0_gpr_mem_server_request_put;
input EN_hart0_gpr_mem_server_request_put;
output RDY_hart0_gpr_mem_server_request_put;
// actionvalue method hart0_gpr_mem_server_response_get
input EN_hart0_gpr_mem_server_response_get;
output [64 : 0] hart0_gpr_mem_server_response_get;
output RDY_hart0_gpr_mem_server_response_get;
// action method hart0_fpr_mem_server_request_put
input [69 : 0] hart0_fpr_mem_server_request_put;
input EN_hart0_fpr_mem_server_request_put;
output RDY_hart0_fpr_mem_server_request_put;
// actionvalue method hart0_fpr_mem_server_response_get
input EN_hart0_fpr_mem_server_response_get;
output [64 : 0] hart0_fpr_mem_server_response_get;
output RDY_hart0_fpr_mem_server_response_get;
// action method hart0_csr_mem_server_request_put
input [76 : 0] hart0_csr_mem_server_request_put;
input EN_hart0_csr_mem_server_request_put;
output RDY_hart0_csr_mem_server_request_put;
// actionvalue method hart0_csr_mem_server_response_get
input EN_hart0_csr_mem_server_response_get;
output [64 : 0] hart0_csr_mem_server_response_get;
output RDY_hart0_csr_mem_server_response_get;
// signals for module outputs
wire [361 : 0] trace_data_out_get;
wire [64 : 0] hart0_csr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
hart0_gpr_mem_server_response_get;
wire [63 : 0] master0_araddr,
master0_awaddr,
master0_wdata,
master1_araddr,
master1_awaddr,
master1_wdata;
wire [7 : 0] master0_arlen,
master0_awlen,
master0_wstrb,
master1_arlen,
master1_awlen,
master1_wstrb;
wire [3 : 0] master0_arcache,
master0_arid,
master0_arqos,
master0_arregion,
master0_awcache,
master0_awid,
master0_awqos,
master0_awregion,
master0_wid,
master1_arcache,
master1_arid,
master1_arqos,
master1_arregion,
master1_awcache,
master1_awid,
master1_awqos,
master1_awregion,
master1_wid;
wire [2 : 0] master0_arprot,
master0_arsize,
master0_awprot,
master0_awsize,
master1_arprot,
master1_arsize,
master1_awprot,
master1_awsize;
wire [1 : 0] master0_arburst,
master0_awburst,
master1_arburst,
master1_awburst;
wire RDY_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_response_get,
RDY_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_response_get,
RDY_hart0_put_other_req_put,
RDY_hart0_server_reset_request_put,
RDY_hart0_server_reset_response_get,
RDY_hart0_server_run_halt_request_put,
RDY_hart0_server_run_halt_response_get,
RDY_set_verbosity,
RDY_start,
RDY_trace_data_out_get,
hart0_server_run_halt_response_get,
master0_arlock,
master0_arvalid,
master0_awlock,
master0_awvalid,
master0_bready,
master0_rready,
master0_wlast,
master0_wvalid,
master1_arlock,
master1_arvalid,
master1_awlock,
master1_awvalid,
master1_bready,
master1_rready,
master1_wlast,
master1_wvalid;
// inlined wires
wire [580 : 0] enqDst_1_0_lat_0$wget;
wire [579 : 0] propDstData_1_0_lat_0$wget, propDstData_1_1_lat_0$wget;
wire [73 : 0] enqDst_0_lat_0$wget;
wire [72 : 0] propDstData_0_lat_0$wget, propDstData_1_lat_0$wget;
wire [65 : 0] enqDst_0_lat_0_1$wget;
wire [64 : 0] mmioPlatform_toHostQ_enqReq_lat_0$wget;
wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read;
wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write,
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read,
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read,
llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write,
llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read,
llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read,
llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write,
llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read,
llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read,
mmioPlatform_fromHostQ_deqReq_lat_0$whas,
mmioPlatform_toHostQ_enqReq_lat_0$whas,
mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write,
mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read,
mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read,
mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write,
mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read,
mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read,
mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write,
mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read,
mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read,
mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write,
mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read,
mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read,
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write,
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read,
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read,
propDstIdx_0_lat_1$whas,
propDstIdx_1_0_lat_1$whas,
propDstIdx_1_1_lat_1$whas,
propDstIdx_1_lat_1$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register enqDst_0_rl
reg [73 : 0] enqDst_0_rl;
wire [73 : 0] enqDst_0_rl$D_IN;
wire enqDst_0_rl$EN;
// register enqDst_0_rl_1
reg [65 : 0] enqDst_0_rl_1;
wire [65 : 0] enqDst_0_rl_1$D_IN;
wire enqDst_0_rl_1$EN;
// register enqDst_1_0_rl
reg [580 : 0] enqDst_1_0_rl;
wire [580 : 0] enqDst_1_0_rl$D_IN;
wire enqDst_1_0_rl$EN;
// register llc_axi4_adapter_cfg_verbosity
reg [3 : 0] llc_axi4_adapter_cfg_verbosity;
wire [3 : 0] llc_axi4_adapter_cfg_verbosity$D_IN;
wire llc_axi4_adapter_cfg_verbosity$EN;
// register llc_axi4_adapter_ctr_wr_rsps_pending_crg
reg [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg;
wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
wire llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN;
// register llc_axi4_adapter_master_xactor_crg_rd_addr_full
reg llc_axi4_adapter_master_xactor_crg_rd_addr_full;
wire llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN,
llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN;
// register llc_axi4_adapter_master_xactor_crg_rd_data_full
reg llc_axi4_adapter_master_xactor_crg_rd_data_full;
wire llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN,
llc_axi4_adapter_master_xactor_crg_rd_data_full$EN;
// register llc_axi4_adapter_master_xactor_crg_wr_addr_full
reg llc_axi4_adapter_master_xactor_crg_wr_addr_full;
wire llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN,
llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN;
// register llc_axi4_adapter_master_xactor_crg_wr_data_full
reg llc_axi4_adapter_master_xactor_crg_wr_data_full;
wire llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN,
llc_axi4_adapter_master_xactor_crg_wr_data_full$EN;
// register llc_axi4_adapter_master_xactor_crg_wr_resp_full
reg llc_axi4_adapter_master_xactor_crg_wr_resp_full;
wire llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN,
llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN;
// register llc_axi4_adapter_master_xactor_rg_rd_addr
reg [96 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr;
wire [96 : 0] llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
wire llc_axi4_adapter_master_xactor_rg_rd_addr$EN;
// register llc_axi4_adapter_master_xactor_rg_rd_data
reg [70 : 0] llc_axi4_adapter_master_xactor_rg_rd_data;
wire [70 : 0] llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
wire llc_axi4_adapter_master_xactor_rg_rd_data$EN;
// register llc_axi4_adapter_master_xactor_rg_wr_addr
reg [96 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr;
wire [96 : 0] llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
wire llc_axi4_adapter_master_xactor_rg_wr_addr$EN;
// register llc_axi4_adapter_master_xactor_rg_wr_data
reg [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data;
wire [76 : 0] llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
wire llc_axi4_adapter_master_xactor_rg_wr_data$EN;
// register llc_axi4_adapter_master_xactor_rg_wr_resp
reg [5 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp;
wire [5 : 0] llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
wire llc_axi4_adapter_master_xactor_rg_wr_resp$EN;
// register llc_axi4_adapter_rg_cline
reg [511 : 0] llc_axi4_adapter_rg_cline;
wire [511 : 0] llc_axi4_adapter_rg_cline$D_IN;
wire llc_axi4_adapter_rg_cline$EN;
// register llc_axi4_adapter_rg_rd_req_beat
reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat;
wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN;
wire llc_axi4_adapter_rg_rd_req_beat$EN;
// register llc_axi4_adapter_rg_rd_rsp_beat
reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat;
wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
wire llc_axi4_adapter_rg_rd_rsp_beat$EN;
// register llc_axi4_adapter_rg_wr_req_beat
reg [2 : 0] llc_axi4_adapter_rg_wr_req_beat;
wire [2 : 0] llc_axi4_adapter_rg_wr_req_beat$D_IN;
wire llc_axi4_adapter_rg_wr_req_beat$EN;
// register llc_axi4_adapter_rg_wr_rsp_beat
reg [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat;
wire [2 : 0] llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
wire llc_axi4_adapter_rg_wr_rsp_beat$EN;
// register mmioPlatform_amoResp
reg [63 : 0] mmioPlatform_amoResp;
wire [63 : 0] mmioPlatform_amoResp$D_IN;
wire mmioPlatform_amoResp$EN;
// register mmioPlatform_curReq
reg [66 : 0] mmioPlatform_curReq;
wire [66 : 0] mmioPlatform_curReq$D_IN;
wire mmioPlatform_curReq$EN;
// register mmioPlatform_cycle
reg [6 : 0] mmioPlatform_cycle;
wire [6 : 0] mmioPlatform_cycle$D_IN;
wire mmioPlatform_cycle$EN;
// register mmioPlatform_fetchedInsts_0
reg [31 : 0] mmioPlatform_fetchedInsts_0;
wire [31 : 0] mmioPlatform_fetchedInsts_0$D_IN;
wire mmioPlatform_fetchedInsts_0$EN;
// register mmioPlatform_fetchingWay
reg mmioPlatform_fetchingWay;
wire mmioPlatform_fetchingWay$D_IN, mmioPlatform_fetchingWay$EN;
// register mmioPlatform_fromHostAddr
reg [60 : 0] mmioPlatform_fromHostAddr;
wire [60 : 0] mmioPlatform_fromHostAddr$D_IN;
wire mmioPlatform_fromHostAddr$EN;
// register mmioPlatform_fromHostQ_clearReq_rl
reg mmioPlatform_fromHostQ_clearReq_rl;
wire mmioPlatform_fromHostQ_clearReq_rl$D_IN,
mmioPlatform_fromHostQ_clearReq_rl$EN;
// register mmioPlatform_fromHostQ_data_0
reg [63 : 0] mmioPlatform_fromHostQ_data_0;
wire [63 : 0] mmioPlatform_fromHostQ_data_0$D_IN;
wire mmioPlatform_fromHostQ_data_0$EN;
// register mmioPlatform_fromHostQ_deqReq_rl
reg mmioPlatform_fromHostQ_deqReq_rl;
wire mmioPlatform_fromHostQ_deqReq_rl$D_IN,
mmioPlatform_fromHostQ_deqReq_rl$EN;
// register mmioPlatform_fromHostQ_empty
reg mmioPlatform_fromHostQ_empty;
wire mmioPlatform_fromHostQ_empty$D_IN, mmioPlatform_fromHostQ_empty$EN;
// register mmioPlatform_fromHostQ_enqReq_rl
reg [64 : 0] mmioPlatform_fromHostQ_enqReq_rl;
wire [64 : 0] mmioPlatform_fromHostQ_enqReq_rl$D_IN;
wire mmioPlatform_fromHostQ_enqReq_rl$EN;
// register mmioPlatform_fromHostQ_full
reg mmioPlatform_fromHostQ_full;
wire mmioPlatform_fromHostQ_full$D_IN, mmioPlatform_fromHostQ_full$EN;
// register mmioPlatform_instSel
reg mmioPlatform_instSel;
wire mmioPlatform_instSel$D_IN, mmioPlatform_instSel$EN;
// register mmioPlatform_mtime
reg [63 : 0] mmioPlatform_mtime;
wire [63 : 0] mmioPlatform_mtime$D_IN;
wire mmioPlatform_mtime$EN;
// register mmioPlatform_mtimecmp_0
reg [63 : 0] mmioPlatform_mtimecmp_0;
wire [63 : 0] mmioPlatform_mtimecmp_0$D_IN;
wire mmioPlatform_mtimecmp_0$EN;
// register mmioPlatform_mtip_0
reg mmioPlatform_mtip_0;
wire mmioPlatform_mtip_0$D_IN, mmioPlatform_mtip_0$EN;
// register mmioPlatform_reqAmofunc
reg [3 : 0] mmioPlatform_reqAmofunc;
wire [3 : 0] mmioPlatform_reqAmofunc$D_IN;
wire mmioPlatform_reqAmofunc$EN;
// register mmioPlatform_reqBE
reg [7 : 0] mmioPlatform_reqBE;
wire [7 : 0] mmioPlatform_reqBE$D_IN;
wire mmioPlatform_reqBE$EN;
// register mmioPlatform_reqData
reg [63 : 0] mmioPlatform_reqData;
wire [63 : 0] mmioPlatform_reqData$D_IN;
wire mmioPlatform_reqData$EN;
// register mmioPlatform_reqFunc
reg [5 : 0] mmioPlatform_reqFunc;
reg [5 : 0] mmioPlatform_reqFunc$D_IN;
wire mmioPlatform_reqFunc$EN;
// register mmioPlatform_reqSz
reg [1 : 0] mmioPlatform_reqSz;
wire [1 : 0] mmioPlatform_reqSz$D_IN;
wire mmioPlatform_reqSz$EN;
// register mmioPlatform_state
reg [1 : 0] mmioPlatform_state;
reg [1 : 0] mmioPlatform_state$D_IN;
wire mmioPlatform_state$EN;
// register mmioPlatform_toHostAddr
reg [60 : 0] mmioPlatform_toHostAddr;
wire [60 : 0] mmioPlatform_toHostAddr$D_IN;
wire mmioPlatform_toHostAddr$EN;
// register mmioPlatform_toHostQ_clearReq_rl
reg mmioPlatform_toHostQ_clearReq_rl;
wire mmioPlatform_toHostQ_clearReq_rl$D_IN,
mmioPlatform_toHostQ_clearReq_rl$EN;
// register mmioPlatform_toHostQ_data_0
reg [63 : 0] mmioPlatform_toHostQ_data_0;
wire [63 : 0] mmioPlatform_toHostQ_data_0$D_IN;
wire mmioPlatform_toHostQ_data_0$EN;
// register mmioPlatform_toHostQ_deqReq_rl
reg mmioPlatform_toHostQ_deqReq_rl;
wire mmioPlatform_toHostQ_deqReq_rl$D_IN, mmioPlatform_toHostQ_deqReq_rl$EN;
// register mmioPlatform_toHostQ_empty
reg mmioPlatform_toHostQ_empty;
wire mmioPlatform_toHostQ_empty$D_IN, mmioPlatform_toHostQ_empty$EN;
// register mmioPlatform_toHostQ_enqReq_rl
reg [64 : 0] mmioPlatform_toHostQ_enqReq_rl;
wire [64 : 0] mmioPlatform_toHostQ_enqReq_rl$D_IN;
wire mmioPlatform_toHostQ_enqReq_rl$EN;
// register mmioPlatform_toHostQ_full
reg mmioPlatform_toHostQ_full;
wire mmioPlatform_toHostQ_full$D_IN, mmioPlatform_toHostQ_full$EN;
// register mmioPlatform_waitLowerMSIPCRs
reg mmioPlatform_waitLowerMSIPCRs;
wire mmioPlatform_waitLowerMSIPCRs$D_IN, mmioPlatform_waitLowerMSIPCRs$EN;
// register mmioPlatform_waitMTIPCRs
reg mmioPlatform_waitMTIPCRs;
wire mmioPlatform_waitMTIPCRs$D_IN, mmioPlatform_waitMTIPCRs$EN;
// register mmioPlatform_waitUpperMSIPCRs
reg mmioPlatform_waitUpperMSIPCRs;
wire mmioPlatform_waitUpperMSIPCRs$D_IN, mmioPlatform_waitUpperMSIPCRs$EN;
// register mmio_axi4_adapter_cfg_verbosity
reg [3 : 0] mmio_axi4_adapter_cfg_verbosity;
wire [3 : 0] mmio_axi4_adapter_cfg_verbosity$D_IN;
wire mmio_axi4_adapter_cfg_verbosity$EN;
// register mmio_axi4_adapter_ctr_wr_rsps_pending_crg
reg [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg;
wire [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
wire mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN;
// register mmio_axi4_adapter_master_xactor_crg_rd_addr_full
reg mmio_axi4_adapter_master_xactor_crg_rd_addr_full;
wire mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN,
mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN;
// register mmio_axi4_adapter_master_xactor_crg_rd_data_full
reg mmio_axi4_adapter_master_xactor_crg_rd_data_full;
wire mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN,
mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN;
// register mmio_axi4_adapter_master_xactor_crg_wr_addr_full
reg mmio_axi4_adapter_master_xactor_crg_wr_addr_full;
wire mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN,
mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN;
// register mmio_axi4_adapter_master_xactor_crg_wr_data_full
reg mmio_axi4_adapter_master_xactor_crg_wr_data_full;
wire mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN,
mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN;
// register mmio_axi4_adapter_master_xactor_crg_wr_resp_full
reg mmio_axi4_adapter_master_xactor_crg_wr_resp_full;
wire mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN,
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN;
// register mmio_axi4_adapter_master_xactor_rg_rd_addr
reg [96 : 0] mmio_axi4_adapter_master_xactor_rg_rd_addr;
wire [96 : 0] mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
wire mmio_axi4_adapter_master_xactor_rg_rd_addr$EN;
// register mmio_axi4_adapter_master_xactor_rg_rd_data
reg [70 : 0] mmio_axi4_adapter_master_xactor_rg_rd_data;
wire [70 : 0] mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN;
wire mmio_axi4_adapter_master_xactor_rg_rd_data$EN;
// register mmio_axi4_adapter_master_xactor_rg_wr_addr
reg [96 : 0] mmio_axi4_adapter_master_xactor_rg_wr_addr;
wire [96 : 0] mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
wire mmio_axi4_adapter_master_xactor_rg_wr_addr$EN;
// register mmio_axi4_adapter_master_xactor_rg_wr_data
reg [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data;
wire [76 : 0] mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN;
wire mmio_axi4_adapter_master_xactor_rg_wr_data$EN;
// register mmio_axi4_adapter_master_xactor_rg_wr_resp
reg [5 : 0] mmio_axi4_adapter_master_xactor_rg_wr_resp;
wire [5 : 0] mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
wire mmio_axi4_adapter_master_xactor_rg_wr_resp$EN;
// register propDstData_0_rl
reg [72 : 0] propDstData_0_rl;
wire [72 : 0] propDstData_0_rl$D_IN;
wire propDstData_0_rl$EN;
// register propDstData_0_rl_1
reg [64 : 0] propDstData_0_rl_1;
wire [64 : 0] propDstData_0_rl_1$D_IN;
wire propDstData_0_rl_1$EN;
// register propDstData_1_0_rl
reg [579 : 0] propDstData_1_0_rl;
wire [579 : 0] propDstData_1_0_rl$D_IN;
wire propDstData_1_0_rl$EN;
// register propDstData_1_1_rl
reg [579 : 0] propDstData_1_1_rl;
wire [579 : 0] propDstData_1_1_rl$D_IN;
wire propDstData_1_1_rl$EN;
// register propDstData_1_rl
reg [72 : 0] propDstData_1_rl;
wire [72 : 0] propDstData_1_rl$D_IN;
wire propDstData_1_rl$EN;
// register propDstIdx_0_rl
reg propDstIdx_0_rl;
wire propDstIdx_0_rl$D_IN, propDstIdx_0_rl$EN;
// register propDstIdx_0_rl_1
reg propDstIdx_0_rl_1;
wire propDstIdx_0_rl_1$D_IN, propDstIdx_0_rl_1$EN;
// register propDstIdx_1_0_rl
reg propDstIdx_1_0_rl;
wire propDstIdx_1_0_rl$D_IN, propDstIdx_1_0_rl$EN;
// register propDstIdx_1_1_rl
reg propDstIdx_1_1_rl;
wire propDstIdx_1_1_rl$D_IN, propDstIdx_1_1_rl$EN;
// register propDstIdx_1_rl
reg propDstIdx_1_rl;
wire propDstIdx_1_rl$D_IN, propDstIdx_1_rl$EN;
// register rg_step_count
reg rg_step_count;
wire rg_step_count$D_IN, rg_step_count$EN;
// register rg_stop_req
reg rg_stop_req;
wire rg_stop_req$D_IN, rg_stop_req$EN;
// register srcRR_0
reg srcRR_0;
wire srcRR_0$D_IN, srcRR_0$EN;
// register srcRR_1_0
reg srcRR_1_0;
wire srcRR_1_0$D_IN, srcRR_1_0$EN;
// ports of submodule core_0
reg [66 : 0] core_0$mmioToPlatform_pRs_enq_x;
reg [38 : 0] core_0$mmioToPlatform_pRq_enq_x;
wire [582 : 0] core_0$dCacheToParent_fromP_enq_x,
core_0$iCacheToParent_fromP_enq_x;
wire [578 : 0] core_0$dCacheToParent_rsToP_first,
core_0$iCacheToParent_rsToP_first;
wire [141 : 0] core_0$mmioToPlatform_cRq_first;
wire [71 : 0] core_0$dCacheToParent_rqToP_first,
core_0$iCacheToParent_rqToP_first;
wire [64 : 0] core_0$tlbToMem_memReq_first, core_0$tlbToMem_respLd_enq_x;
wire [63 : 0] core_0$coreReq_start_fromHostAddr,
core_0$coreReq_start_startpc,
core_0$coreReq_start_toHostAddr,
core_0$mmioToPlatform_setTime_t;
wire [4 : 0] core_0$coreReq_perfReq_t;
wire [3 : 0] core_0$coreReq_perfReq_loc;
wire core_0$EN_coreIndInv_perfResp,
core_0$EN_coreIndInv_terminate,
core_0$EN_coreReq_perfReq,
core_0$EN_coreReq_start,
core_0$EN_dCacheToParent_fromP_enq,
core_0$EN_dCacheToParent_rqToP_deq,
core_0$EN_dCacheToParent_rsToP_deq,
core_0$EN_deadlock_checkStarted_get,
core_0$EN_deadlock_commitInstStuck_get,
core_0$EN_deadlock_commitUserInstStuck_get,
core_0$EN_deadlock_dCacheCRqStuck_get,
core_0$EN_deadlock_dCachePRqStuck_get,
core_0$EN_deadlock_iCacheCRqStuck_get,
core_0$EN_deadlock_iCachePRqStuck_get,
core_0$EN_deadlock_renameCorrectPathStuck_get,
core_0$EN_deadlock_renameInstStuck_get,
core_0$EN_iCacheToParent_fromP_enq,
core_0$EN_iCacheToParent_rqToP_deq,
core_0$EN_iCacheToParent_rsToP_deq,
core_0$EN_mmioToPlatform_cRq_deq,
core_0$EN_mmioToPlatform_cRs_deq,
core_0$EN_mmioToPlatform_pRq_enq,
core_0$EN_mmioToPlatform_pRs_enq,
core_0$EN_mmioToPlatform_setTime,
core_0$EN_recvDoStats,
core_0$EN_renameDebug_renameErr_get,
core_0$EN_sendDoStats,
core_0$EN_setDEIP,
core_0$EN_setMEIP,
core_0$EN_setSEIP,
core_0$EN_tlbToMem_memReq_deq,
core_0$EN_tlbToMem_respLd_enq,
core_0$RDY_coreIndInv_terminate,
core_0$RDY_dCacheToParent_fromP_enq,
core_0$RDY_dCacheToParent_rqToP_deq,
core_0$RDY_dCacheToParent_rqToP_first,
core_0$RDY_dCacheToParent_rsToP_deq,
core_0$RDY_dCacheToParent_rsToP_first,
core_0$RDY_deadlock_checkStarted_get,
core_0$RDY_deadlock_commitInstStuck_get,
core_0$RDY_deadlock_commitUserInstStuck_get,
core_0$RDY_deadlock_dCacheCRqStuck_get,
core_0$RDY_deadlock_dCachePRqStuck_get,
core_0$RDY_deadlock_iCacheCRqStuck_get,
core_0$RDY_deadlock_iCachePRqStuck_get,
core_0$RDY_deadlock_renameCorrectPathStuck_get,
core_0$RDY_deadlock_renameInstStuck_get,
core_0$RDY_iCacheToParent_fromP_enq,
core_0$RDY_iCacheToParent_rqToP_deq,
core_0$RDY_iCacheToParent_rqToP_first,
core_0$RDY_iCacheToParent_rsToP_deq,
core_0$RDY_iCacheToParent_rsToP_first,
core_0$RDY_mmioToPlatform_cRq_deq,
core_0$RDY_mmioToPlatform_cRq_first,
core_0$RDY_mmioToPlatform_cRs_deq,
core_0$RDY_mmioToPlatform_cRs_first,
core_0$RDY_mmioToPlatform_pRq_enq,
core_0$RDY_mmioToPlatform_pRs_enq,
core_0$RDY_renameDebug_renameErr_get,
core_0$RDY_sendDoStats,
core_0$RDY_tlbToMem_memReq_deq,
core_0$RDY_tlbToMem_memReq_first,
core_0$RDY_tlbToMem_respLd_enq,
core_0$mmioToPlatform_cRq_notEmpty,
core_0$mmioToPlatform_cRs_first,
core_0$recvDoStats_x,
core_0$sendDoStats,
core_0$setDEIP_v,
core_0$setMEIP_v,
core_0$setSEIP_v;
// ports of submodule enqDst_0_dummy2_0
wire enqDst_0_dummy2_0$D_IN, enqDst_0_dummy2_0$EN, enqDst_0_dummy2_0$Q_OUT;
// ports of submodule enqDst_0_dummy2_0_1
wire enqDst_0_dummy2_0_1$D_IN,
enqDst_0_dummy2_0_1$EN,
enqDst_0_dummy2_0_1$Q_OUT;
// ports of submodule enqDst_0_dummy2_1
wire enqDst_0_dummy2_1$D_IN, enqDst_0_dummy2_1$EN, enqDst_0_dummy2_1$Q_OUT;
// ports of submodule enqDst_0_dummy2_1_1
wire enqDst_0_dummy2_1_1$D_IN,
enqDst_0_dummy2_1_1$EN,
enqDst_0_dummy2_1_1$Q_OUT;
// ports of submodule enqDst_1_0_dummy2_0
wire enqDst_1_0_dummy2_0$D_IN,
enqDst_1_0_dummy2_0$EN,
enqDst_1_0_dummy2_0$Q_OUT;
// ports of submodule enqDst_1_0_dummy2_1
wire enqDst_1_0_dummy2_1$D_IN,
enqDst_1_0_dummy2_1$EN,
enqDst_1_0_dummy2_1$Q_OUT;
// ports of submodule f_csr_reqs
wire [76 : 0] f_csr_reqs$D_IN;
wire f_csr_reqs$CLR, f_csr_reqs$DEQ, f_csr_reqs$ENQ, f_csr_reqs$FULL_N;
// ports of submodule f_csr_rsps
wire [64 : 0] f_csr_rsps$D_IN, f_csr_rsps$D_OUT;
wire f_csr_rsps$CLR, f_csr_rsps$DEQ, f_csr_rsps$EMPTY_N, f_csr_rsps$ENQ;
// ports of submodule f_fpr_reqs
wire [69 : 0] f_fpr_reqs$D_IN;
wire f_fpr_reqs$CLR, f_fpr_reqs$DEQ, f_fpr_reqs$ENQ, f_fpr_reqs$FULL_N;
// ports of submodule f_fpr_rsps
wire [64 : 0] f_fpr_rsps$D_IN, f_fpr_rsps$D_OUT;
wire f_fpr_rsps$CLR, f_fpr_rsps$DEQ, f_fpr_rsps$EMPTY_N, f_fpr_rsps$ENQ;
// ports of submodule f_gpr_reqs
wire [69 : 0] f_gpr_reqs$D_IN;
wire f_gpr_reqs$CLR, f_gpr_reqs$DEQ, f_gpr_reqs$ENQ, f_gpr_reqs$FULL_N;
// ports of submodule f_gpr_rsps
wire [64 : 0] f_gpr_rsps$D_IN, f_gpr_rsps$D_OUT;
wire f_gpr_rsps$CLR, f_gpr_rsps$DEQ, f_gpr_rsps$EMPTY_N, f_gpr_rsps$ENQ;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule f_run_halt_reqs
wire f_run_halt_reqs$CLR,
f_run_halt_reqs$DEQ,
f_run_halt_reqs$D_IN,
f_run_halt_reqs$ENQ,
f_run_halt_reqs$FULL_N;
// ports of submodule f_run_halt_rsps
wire f_run_halt_rsps$CLR,
f_run_halt_rsps$DEQ,
f_run_halt_rsps$D_IN,
f_run_halt_rsps$D_OUT,
f_run_halt_rsps$EMPTY_N,
f_run_halt_rsps$ENQ;
// ports of submodule f_trace_data
wire [361 : 0] f_trace_data$D_IN, f_trace_data$D_OUT;
wire f_trace_data$CLR,
f_trace_data$DEQ,
f_trace_data$EMPTY_N,
f_trace_data$ENQ;
// ports of submodule llc
wire [644 : 0] llc$dma_memReq_enq_x;
wire [640 : 0] llc$to_mem_toM_first;
wire [583 : 0] llc$to_child_toC_first;
wire [579 : 0] llc$to_child_rsFromC_enq_x;
wire [516 : 0] llc$dma_respLd_first, llc$to_mem_rsFromM_enq_x;
wire [72 : 0] llc$to_child_rqFromC_enq_x;
wire [4 : 0] llc$dma_respSt_first;
wire [3 : 0] llc$perf_req_r;
wire llc$EN_cRqStuck_get,
llc$EN_dma_memReq_enq,
llc$EN_dma_respLd_deq,
llc$EN_dma_respSt_deq,
llc$EN_perf_req,
llc$EN_perf_resp,
llc$EN_perf_setStatus,
llc$EN_to_child_rqFromC_enq,
llc$EN_to_child_rsFromC_enq,
llc$EN_to_child_toC_deq,
llc$EN_to_mem_rsFromM_enq,
llc$EN_to_mem_toM_deq,
llc$RDY_dma_memReq_enq,
llc$RDY_dma_respLd_deq,
llc$RDY_dma_respLd_first,
llc$RDY_dma_respSt_deq,
llc$RDY_dma_respSt_first,
llc$RDY_to_child_rqFromC_enq,
llc$RDY_to_child_rsFromC_enq,
llc$RDY_to_child_toC_deq,
llc$RDY_to_child_toC_first,
llc$RDY_to_mem_rsFromM_enq,
llc$RDY_to_mem_toM_deq,
llc$RDY_to_mem_toM_first,
llc$perf_setStatus_doStats;
// ports of submodule llc_axi4_adapter_f_pending_reads
wire [68 : 0] llc_axi4_adapter_f_pending_reads$D_IN,
llc_axi4_adapter_f_pending_reads$D_OUT;
wire llc_axi4_adapter_f_pending_reads$CLR,
llc_axi4_adapter_f_pending_reads$DEQ,
llc_axi4_adapter_f_pending_reads$EMPTY_N,
llc_axi4_adapter_f_pending_reads$ENQ,
llc_axi4_adapter_f_pending_reads$FULL_N;
// ports of submodule llc_axi4_adapter_f_pending_writes
wire [639 : 0] llc_axi4_adapter_f_pending_writes$D_IN;
wire llc_axi4_adapter_f_pending_writes$CLR,
llc_axi4_adapter_f_pending_writes$DEQ,
llc_axi4_adapter_f_pending_writes$EMPTY_N,
llc_axi4_adapter_f_pending_writes$ENQ,
llc_axi4_adapter_f_pending_writes$FULL_N;
// ports of submodule mmioPlatform_fromHostQ_clearReq_dummy2_0
wire mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN,
mmioPlatform_fromHostQ_clearReq_dummy2_0$EN;
// ports of submodule mmioPlatform_fromHostQ_clearReq_dummy2_1
wire mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN,
mmioPlatform_fromHostQ_clearReq_dummy2_1$EN,
mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_0
wire mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN,
mmioPlatform_fromHostQ_deqReq_dummy2_0$EN;
// ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_1
wire mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN,
mmioPlatform_fromHostQ_deqReq_dummy2_1$EN;
// ports of submodule mmioPlatform_fromHostQ_deqReq_dummy2_2
wire mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN,
mmioPlatform_fromHostQ_deqReq_dummy2_2$EN,
mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_0
wire mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN,
mmioPlatform_fromHostQ_enqReq_dummy2_0$EN;
// ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_1
wire mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN,
mmioPlatform_fromHostQ_enqReq_dummy2_1$EN;
// ports of submodule mmioPlatform_fromHostQ_enqReq_dummy2_2
wire mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN,
mmioPlatform_fromHostQ_enqReq_dummy2_2$EN,
mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmioPlatform_toHostQ_clearReq_dummy2_0
wire mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN,
mmioPlatform_toHostQ_clearReq_dummy2_0$EN;
// ports of submodule mmioPlatform_toHostQ_clearReq_dummy2_1
wire mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN,
mmioPlatform_toHostQ_clearReq_dummy2_1$EN,
mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_0
wire mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN,
mmioPlatform_toHostQ_deqReq_dummy2_0$EN;
// ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_1
wire mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN,
mmioPlatform_toHostQ_deqReq_dummy2_1$EN;
// ports of submodule mmioPlatform_toHostQ_deqReq_dummy2_2
wire mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN,
mmioPlatform_toHostQ_deqReq_dummy2_2$EN,
mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_0
wire mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN,
mmioPlatform_toHostQ_enqReq_dummy2_0$EN;
// ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_1
wire mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN,
mmioPlatform_toHostQ_enqReq_dummy2_1$EN;
// ports of submodule mmioPlatform_toHostQ_enqReq_dummy2_2
wire mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN,
mmioPlatform_toHostQ_enqReq_dummy2_2$EN,
mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_axi4_adapter_f_reqs_from_core
reg [141 : 0] mmio_axi4_adapter_f_reqs_from_core$D_IN;
wire [141 : 0] mmio_axi4_adapter_f_reqs_from_core$D_OUT;
wire mmio_axi4_adapter_f_reqs_from_core$CLR,
mmio_axi4_adapter_f_reqs_from_core$DEQ,
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N,
mmio_axi4_adapter_f_reqs_from_core$ENQ,
mmio_axi4_adapter_f_reqs_from_core$FULL_N;
// ports of submodule mmio_axi4_adapter_f_rsps_to_core
wire [64 : 0] mmio_axi4_adapter_f_rsps_to_core$D_IN,
mmio_axi4_adapter_f_rsps_to_core$D_OUT;
wire mmio_axi4_adapter_f_rsps_to_core$CLR,
mmio_axi4_adapter_f_rsps_to_core$DEQ,
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N,
mmio_axi4_adapter_f_rsps_to_core$ENQ,
mmio_axi4_adapter_f_rsps_to_core$FULL_N;
// ports of submodule propDstData_0_dummy2_0
wire propDstData_0_dummy2_0$D_IN, propDstData_0_dummy2_0$EN;
// ports of submodule propDstData_0_dummy2_0_1
wire propDstData_0_dummy2_0_1$D_IN, propDstData_0_dummy2_0_1$EN;
// ports of submodule propDstData_0_dummy2_1
wire propDstData_0_dummy2_1$D_IN,
propDstData_0_dummy2_1$EN,
propDstData_0_dummy2_1$Q_OUT;
// ports of submodule propDstData_0_dummy2_1_1
wire propDstData_0_dummy2_1_1$D_IN,
propDstData_0_dummy2_1_1$EN,
propDstData_0_dummy2_1_1$Q_OUT;
// ports of submodule propDstData_1_0_dummy2_0
wire propDstData_1_0_dummy2_0$D_IN, propDstData_1_0_dummy2_0$EN;
// ports of submodule propDstData_1_0_dummy2_1
wire propDstData_1_0_dummy2_1$D_IN,
propDstData_1_0_dummy2_1$EN,
propDstData_1_0_dummy2_1$Q_OUT;
// ports of submodule propDstData_1_1_dummy2_0
wire propDstData_1_1_dummy2_0$D_IN, propDstData_1_1_dummy2_0$EN;
// ports of submodule propDstData_1_1_dummy2_1
wire propDstData_1_1_dummy2_1$D_IN,
propDstData_1_1_dummy2_1$EN,
propDstData_1_1_dummy2_1$Q_OUT;
// ports of submodule propDstData_1_dummy2_0
wire propDstData_1_dummy2_0$D_IN, propDstData_1_dummy2_0$EN;
// ports of submodule propDstData_1_dummy2_1
wire propDstData_1_dummy2_1$D_IN,
propDstData_1_dummy2_1$EN,
propDstData_1_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_0_dummy2_0
wire propDstIdx_0_dummy2_0$D_IN,
propDstIdx_0_dummy2_0$EN,
propDstIdx_0_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_0_dummy2_0_1
wire propDstIdx_0_dummy2_0_1$D_IN,
propDstIdx_0_dummy2_0_1$EN,
propDstIdx_0_dummy2_0_1$Q_OUT;
// ports of submodule propDstIdx_0_dummy2_1
wire propDstIdx_0_dummy2_1$D_IN,
propDstIdx_0_dummy2_1$EN,
propDstIdx_0_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_0_dummy2_1_1
wire propDstIdx_0_dummy2_1_1$D_IN,
propDstIdx_0_dummy2_1_1$EN,
propDstIdx_0_dummy2_1_1$Q_OUT;
// ports of submodule propDstIdx_1_0_dummy2_0
wire propDstIdx_1_0_dummy2_0$D_IN,
propDstIdx_1_0_dummy2_0$EN,
propDstIdx_1_0_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_1_0_dummy2_1
wire propDstIdx_1_0_dummy2_1$D_IN,
propDstIdx_1_0_dummy2_1$EN,
propDstIdx_1_0_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_1_1_dummy2_0
wire propDstIdx_1_1_dummy2_0$D_IN,
propDstIdx_1_1_dummy2_0$EN,
propDstIdx_1_1_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_1_1_dummy2_1
wire propDstIdx_1_1_dummy2_1$D_IN,
propDstIdx_1_1_dummy2_1$EN,
propDstIdx_1_1_dummy2_1$Q_OUT;
// ports of submodule propDstIdx_1_dummy2_0
wire propDstIdx_1_dummy2_0$D_IN,
propDstIdx_1_dummy2_0$EN,
propDstIdx_1_dummy2_0$Q_OUT;
// ports of submodule propDstIdx_1_dummy2_1
wire propDstIdx_1_dummy2_1$D_IN,
propDstIdx_1_dummy2_1$EN,
propDstIdx_1_dummy2_1$Q_OUT;
// ports of submodule tlbQ
wire [64 : 0] tlbQ$D_IN, tlbQ$D_OUT;
wire tlbQ$CLR, tlbQ$DEQ, tlbQ$EMPTY_N, tlbQ$ENQ, tlbQ$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_broadcastStats,
CAN_FIRE_RL_doEnq,
CAN_FIRE_RL_doEnq_1,
CAN_FIRE_RL_doEnq_2,
CAN_FIRE_RL_dstSelectSrc,
CAN_FIRE_RL_dstSelectSrc_1,
CAN_FIRE_RL_dstSelectSrc_2,
CAN_FIRE_RL_enqDst_0_canon,
CAN_FIRE_RL_enqDst_0_canon_1,
CAN_FIRE_RL_enqDst_1_0_canon,
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
CAN_FIRE_RL_mmioPlatform_fromHostQ_canonicalize,
CAN_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon,
CAN_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon,
CAN_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon,
CAN_FIRE_RL_mmioPlatform_incCycle,
CAN_FIRE_RL_mmioPlatform_incTime,
CAN_FIRE_RL_mmioPlatform_processFromHost,
CAN_FIRE_RL_mmioPlatform_processMSIP,
CAN_FIRE_RL_mmioPlatform_processMTime,
CAN_FIRE_RL_mmioPlatform_processMTimeCmp,
CAN_FIRE_RL_mmioPlatform_processToHost,
CAN_FIRE_RL_mmioPlatform_propagateTime,
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp,
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp,
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp,
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req,
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req,
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req,
CAN_FIRE_RL_mmioPlatform_selectReq,
CAN_FIRE_RL_mmioPlatform_toHostQ_canonicalize,
CAN_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon,
CAN_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon,
CAN_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon,
CAN_FIRE_RL_mmioPlatform_waitMSIPDone,
CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone,
CAN_FIRE_RL_mmioPlatform_waitMTimeDone,
CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone,
CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req,
CAN_FIRE_RL_propDstData_0_canon,
CAN_FIRE_RL_propDstData_0_canon_1,
CAN_FIRE_RL_propDstData_1_0_canon,
CAN_FIRE_RL_propDstData_1_1_canon,
CAN_FIRE_RL_propDstData_1_canon,
CAN_FIRE_RL_propDstIdx_0_canon,
CAN_FIRE_RL_propDstIdx_0_canon_1,
CAN_FIRE_RL_propDstIdx_1_0_canon,
CAN_FIRE_RL_propDstIdx_1_1_canon,
CAN_FIRE_RL_propDstIdx_1_canon,
CAN_FIRE_RL_rl_dummy1,
CAN_FIRE_RL_rl_dummy2,
CAN_FIRE_RL_rl_dummy20,
CAN_FIRE_RL_rl_dummy3,
CAN_FIRE_RL_rl_dummy4,
CAN_FIRE_RL_rl_dummy5,
CAN_FIRE_RL_rl_dummy6,
CAN_FIRE_RL_rl_dummy7,
CAN_FIRE_RL_rl_dummy8,
CAN_FIRE_RL_rl_dummy9,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_terminate,
CAN_FIRE_RL_rl_tohost,
CAN_FIRE_RL_sendLdRespToMemLoader,
CAN_FIRE_RL_sendLdRespToTlb,
CAN_FIRE_RL_sendPRq,
CAN_FIRE_RL_sendPRq_1,
CAN_FIRE_RL_sendPRs,
CAN_FIRE_RL_sendPRs_1,
CAN_FIRE_RL_sendStRespToMemLoader,
CAN_FIRE_RL_sendStRespToTlb,
CAN_FIRE_RL_sendTlbReqToLLC,
CAN_FIRE_RL_srcPropose,
CAN_FIRE_RL_srcPropose_1,
CAN_FIRE_RL_srcPropose_2,
CAN_FIRE_RL_srcPropose_3,
CAN_FIRE_RL_srcPropose_4,
CAN_FIRE_debug_external_interrupt_req,
CAN_FIRE_hart0_csr_mem_server_request_put,
CAN_FIRE_hart0_csr_mem_server_response_get,
CAN_FIRE_hart0_fpr_mem_server_request_put,
CAN_FIRE_hart0_fpr_mem_server_response_get,
CAN_FIRE_hart0_gpr_mem_server_request_put,
CAN_FIRE_hart0_gpr_mem_server_response_get,
CAN_FIRE_hart0_put_other_req_put,
CAN_FIRE_hart0_server_reset_request_put,
CAN_FIRE_hart0_server_reset_response_get,
CAN_FIRE_hart0_server_run_halt_request_put,
CAN_FIRE_hart0_server_run_halt_response_get,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_master0_m_arready,
CAN_FIRE_master0_m_awready,
CAN_FIRE_master0_m_bvalid,
CAN_FIRE_master0_m_rvalid,
CAN_FIRE_master0_m_wready,
CAN_FIRE_master1_m_arready,
CAN_FIRE_master1_m_awready,
CAN_FIRE_master1_m_bvalid,
CAN_FIRE_master1_m_rvalid,
CAN_FIRE_master1_m_wready,
CAN_FIRE_non_maskable_interrupt_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_start,
CAN_FIRE_trace_data_out_get,
WILL_FIRE_RL_broadcastStats,
WILL_FIRE_RL_doEnq,
WILL_FIRE_RL_doEnq_1,
WILL_FIRE_RL_doEnq_2,
WILL_FIRE_RL_dstSelectSrc,
WILL_FIRE_RL_dstSelectSrc_1,
WILL_FIRE_RL_dstSelectSrc_2,
WILL_FIRE_RL_enqDst_0_canon,
WILL_FIRE_RL_enqDst_0_canon_1,
WILL_FIRE_RL_enqDst_1_0_canon,
WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
WILL_FIRE_RL_mmioPlatform_fromHostQ_canonicalize,
WILL_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon,
WILL_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon,
WILL_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon,
WILL_FIRE_RL_mmioPlatform_incCycle,
WILL_FIRE_RL_mmioPlatform_incTime,
WILL_FIRE_RL_mmioPlatform_processFromHost,
WILL_FIRE_RL_mmioPlatform_processMSIP,
WILL_FIRE_RL_mmioPlatform_processMTime,
WILL_FIRE_RL_mmioPlatform_processMTimeCmp,
WILL_FIRE_RL_mmioPlatform_processToHost,
WILL_FIRE_RL_mmioPlatform_propagateTime,
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp,
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp,
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp,
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req,
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req,
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req,
WILL_FIRE_RL_mmioPlatform_selectReq,
WILL_FIRE_RL_mmioPlatform_toHostQ_canonicalize,
WILL_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon,
WILL_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon,
WILL_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon,
WILL_FIRE_RL_mmioPlatform_waitMSIPDone,
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone,
WILL_FIRE_RL_mmioPlatform_waitMTimeDone,
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone,
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req,
WILL_FIRE_RL_propDstData_0_canon,
WILL_FIRE_RL_propDstData_0_canon_1,
WILL_FIRE_RL_propDstData_1_0_canon,
WILL_FIRE_RL_propDstData_1_1_canon,
WILL_FIRE_RL_propDstData_1_canon,
WILL_FIRE_RL_propDstIdx_0_canon,
WILL_FIRE_RL_propDstIdx_0_canon_1,
WILL_FIRE_RL_propDstIdx_1_0_canon,
WILL_FIRE_RL_propDstIdx_1_1_canon,
WILL_FIRE_RL_propDstIdx_1_canon,
WILL_FIRE_RL_rl_dummy1,
WILL_FIRE_RL_rl_dummy2,
WILL_FIRE_RL_rl_dummy20,
WILL_FIRE_RL_rl_dummy3,
WILL_FIRE_RL_rl_dummy4,
WILL_FIRE_RL_rl_dummy5,
WILL_FIRE_RL_rl_dummy6,
WILL_FIRE_RL_rl_dummy7,
WILL_FIRE_RL_rl_dummy8,
WILL_FIRE_RL_rl_dummy9,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_terminate,
WILL_FIRE_RL_rl_tohost,
WILL_FIRE_RL_sendLdRespToMemLoader,
WILL_FIRE_RL_sendLdRespToTlb,
WILL_FIRE_RL_sendPRq,
WILL_FIRE_RL_sendPRq_1,
WILL_FIRE_RL_sendPRs,
WILL_FIRE_RL_sendPRs_1,
WILL_FIRE_RL_sendStRespToMemLoader,
WILL_FIRE_RL_sendStRespToTlb,
WILL_FIRE_RL_sendTlbReqToLLC,
WILL_FIRE_RL_srcPropose,
WILL_FIRE_RL_srcPropose_1,
WILL_FIRE_RL_srcPropose_2,
WILL_FIRE_RL_srcPropose_3,
WILL_FIRE_RL_srcPropose_4,
WILL_FIRE_debug_external_interrupt_req,
WILL_FIRE_hart0_csr_mem_server_request_put,
WILL_FIRE_hart0_csr_mem_server_response_get,
WILL_FIRE_hart0_fpr_mem_server_request_put,
WILL_FIRE_hart0_fpr_mem_server_response_get,
WILL_FIRE_hart0_gpr_mem_server_request_put,
WILL_FIRE_hart0_gpr_mem_server_response_get,
WILL_FIRE_hart0_put_other_req_put,
WILL_FIRE_hart0_server_reset_request_put,
WILL_FIRE_hart0_server_reset_response_get,
WILL_FIRE_hart0_server_run_halt_request_put,
WILL_FIRE_hart0_server_run_halt_response_get,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_master0_m_arready,
WILL_FIRE_master0_m_awready,
WILL_FIRE_master0_m_bvalid,
WILL_FIRE_master0_m_rvalid,
WILL_FIRE_master0_m_wready,
WILL_FIRE_master1_m_arready,
WILL_FIRE_master1_m_awready,
WILL_FIRE_master1_m_bvalid,
WILL_FIRE_master1_m_rvalid,
WILL_FIRE_master1_m_wready,
WILL_FIRE_non_maskable_interrupt_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_start,
WILL_FIRE_trace_data_out_get;
// inputs to muxes for submodule ports
reg [1 : 0] MUX_mmioPlatform_state$write_1__VAL_3,
MUX_mmioPlatform_state$write_1__VAL_4;
wire [582 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1,
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2;
wire [141 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4;
wire [66 : 0] MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9,
MUX_mmioPlatform_curReq$write_1__VAL_1,
MUX_mmioPlatform_curReq$write_1__VAL_2;
wire [64 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2;
wire [63 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1,
MUX_mmioPlatform_amoResp$write_1__VAL_2,
MUX_mmioPlatform_mtime$write_1__VAL_2;
wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2,
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3,
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4;
wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1;
wire [1 : 0] MUX_mmioPlatform_state$write_1__VAL_1,
MUX_mmioPlatform_state$write_1__VAL_2,
MUX_mmioPlatform_state$write_1__VAL_5;
wire MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1,
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2,
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3,
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5,
MUX_mmioPlatform_amoResp$write_1__SEL_1,
MUX_mmioPlatform_amoResp$write_1__SEL_2,
MUX_mmioPlatform_curReq$write_1__SEL_1,
MUX_mmioPlatform_fetchingWay$write_1__SEL_1,
MUX_mmioPlatform_fetchingWay$write_1__VAL_2,
MUX_mmioPlatform_instSel$write_1__VAL_2,
MUX_mmioPlatform_mtip_0$write_1__VAL_2,
MUX_mmioPlatform_state$write_1__SEL_6,
MUX_mmioPlatform_state$write_1__SEL_7,
MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1,
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h4988;
reg [31 : 0] v__h5154;
reg [31 : 0] v__h5432;
reg [31 : 0] v__h7471;
reg [31 : 0] v__h3264;
reg [31 : 0] v__h7772;
reg [31 : 0] v__h8263;
reg [31 : 0] v__h8426;
reg [31 : 0] v__h111845;
reg [31 : 0] v__h112012;
reg [31 : 0] v__h114115;
reg [31 : 0] v__h131461;
reg [31 : 0] v__h111226;
reg [31 : 0] v__h138156;
reg [31 : 0] v__h138664;
reg [31 : 0] v__h3258;
reg [31 : 0] v__h4982;
reg [31 : 0] v__h5148;
reg [31 : 0] v__h5426;
reg [31 : 0] v__h7465;
reg [31 : 0] v__h7766;
reg [31 : 0] v__h8257;
reg [31 : 0] v__h8420;
reg [31 : 0] v__h111220;
reg [31 : 0] v__h111839;
reg [31 : 0] v__h112006;
reg [31 : 0] v__h114109;
reg [31 : 0] v__h131455;
reg [31 : 0] v__h138150;
reg [31 : 0] v__h138658;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5,
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6,
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23,
CASE_x7791_0_n__read_addr7969_1_n__read_addr80_ETC__q26,
CASE_x9168_0_n__read_addr9350_1_n__read_addr94_ETC__q15,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908,
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875,
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843,
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845,
data64__h125285,
ld_data__h109019,
w1__h46149,
w1__h46154,
w2__h46150,
w2__h46156,
x__h46145;
reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d942;
reg [7 : 0] strb8__h125286;
reg [5 : 0] IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d440;
reg [2 : 0] x__h59482;
reg [1 : 0] CASE_x7791_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24,
CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13,
CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14;
reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10,
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11,
CASE_x7791_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25,
CASE_x9168_0_propDstData_0_dummy2_1_read__051__ETC__q12,
SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_IF_ETC___d1044,
SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_AND__ETC___d1313,
x__h59489,
x__h80207;
wire [579 : 0] IF_enqDst_1_0_lat_1_whas__217_THEN_enqDst_1_0__ETC___d1264;
wire [515 : 0] SEL_ARR_IF_propDstData_1_0_dummy2_1_read__320__ETC___d1412;
wire [513 : 0] IF_enqDst_1_0_lat_1_whas__217_THEN_enqDst_1_0__ETC___d1263;
wire [511 : 0] IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1255,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1405,
new_cline__h112148;
wire [383 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1388;
wire [255 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1371;
wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1354;
wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__41_BITS_14_ETC___d364;
wire [65 : 0] DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_99_BIT_ETC___d643,
IF_mmio_axi4_adapter_f_rsps_to_core_first__15__ETC___d947;
wire [64 : 0] IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_2_ETC___d682;
wire [63 : 0] IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1235,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785,
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836,
IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d536,
IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d600,
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d511,
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d573,
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d674,
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_1_ETC___d537,
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_1_ETC___d601,
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1149,
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1187,
data__h30239,
failed_testnum__h140054,
mem_req_rd_addr_araddr__h111446,
mem_req_wr_addr_awaddr__h125370,
mmioPlatform_fromHostQ_data_0__h40939,
mmioPlatform_mtime__h35553,
mmioPlatform_reqData__h46741,
n__read_addr__h59350,
n__read_addr__h59435,
n__read_addr__h77969,
n__read_addr__h78048,
n__read_snd_addr__h92140,
newData__h30320,
newData__h33250,
op_result__h46757,
op_result__h47287,
op_result__h47292,
op_result__h47297,
op_result__h47302,
op_result__h47308,
op_result__h47315,
op_result__h47321,
result__h46200,
result__h46324,
result__h46352,
result__h46380,
result__h46408,
result__h46436,
result__h46464,
result__h46492,
result__h46520,
result__h46565,
result__h46593,
result__h46621,
result__h46649,
result__h46690,
result__h46718,
result__h46844,
result__h46871,
result__h46898,
result__h46925,
result__h46952,
result__h46979,
result__h47006,
result__h47033,
result__h47077,
result__h47104,
result__h47131,
result__h47158,
result__h47198,
result__h47225,
result__h47342,
result__h47408,
result__h47474,
result__h47540,
result__h47606,
result__h47672,
result__h47738,
result__h47800,
result__h47845,
result__h47911,
result__h47977,
result__h48035,
result__h48080,
w1___1__h46259,
w2___1__h46260,
x1_avValue_data__h38611,
x1_avValue_data__h43078,
x__h30431,
x__h33341,
x__h35701,
x__h39129,
x__h39140,
x__h41149,
x__h41160,
x__h48257;
wire [47 : 0] IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d503,
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d568,
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d669;
wire [31 : 0] IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d494,
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d563,
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d664,
mmioPlatform_mtime_BITS_31_TO_0__q4,
mmioPlatform_mtime_BITS_63_TO_32__q3,
mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2,
mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1,
v__h30032,
v__h30069,
w16149_BITS_31_TO_0__q7,
w26150_BITS_31_TO_0__q8,
x_data__h28822;
wire [8 : 0] SEL_ARR_IF_propDstData_0_dummy2_1_read__051_TH_ETC___d1115;
wire [5 : 0] x__h111481, x__h125395;
wire [4 : 0] SEL_ARR_propDstData_0_dummy2_1_read__051_AND_I_ETC___d1114;
wire [3 : 0] b__h111153, b__h3158;
wire [2 : 0] n__read_id__h59354, n__read_id__h59439;
wire [1 : 0] IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1240,
IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1067,
IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1077,
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1154,
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1192,
IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1071,
IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1081;
wire IF_IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4__ETC___d518,
IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d415,
IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513,
IF_NOT_propDstIdx_0_dummy2_1_read__013_014_OR__ETC___d1048,
IF_NOT_propDstIdx_1_0_dummy2_1_read__272_273_O_ETC___d1317,
IF_SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_ETC___d1120,
IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_A_ETC___d1417,
IF_enqDst_0_lat_0_1_whas__476_THEN_enqDst_0_la_ETC___d1481,
IF_enqDst_0_lat_0_whas__89_THEN_enqDst_0_lat_0_ETC___d994,
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1225,
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1245,
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1261,
IF_mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioP_ETC___d584,
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d416,
IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__54__ETC___d163,
IF_mmioPlatform_waitLowerMSIPCRs_51_THEN_core__ETC___d459,
IF_mmio_axi4_adapter_f_rsps_to_core_first__15__ETC___d930,
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1175,
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1213,
IF_propDstIdx_0_lat_0_1_whas__461_THEN_propDst_ETC___d1464,
IF_propDstIdx_0_lat_0_whas__60_THEN_propDstIdx_ETC___d963,
IF_propDstIdx_1_0_lat_0_whas__129_THEN_propDst_ETC___d1132,
IF_propDstIdx_1_1_lat_0_whas__136_THEN_propDst_ETC___d1139,
IF_propDstIdx_1_lat_0_whas__67_THEN_propDstIdx_ETC___d970,
NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514,
NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050,
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319,
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610,
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d705,
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d713,
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d719,
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d729,
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d920,
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d933,
NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d281,
NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d302,
NOT_mmioPlatform_mtip_0_18_25_AND_mmioPlatform_ETC___d333,
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d449,
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d544,
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d607,
NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d203,
NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d224,
NOT_propDstData_1_0_dummy2_1_read__320_331_OR__ETC___d1332,
NOT_propDstData_1_1_dummy2_1_read__322_333_OR__ETC___d1334,
NOT_propDstIdx_0_dummy2_1_read__013_014_OR_IF__ETC___d1047,
NOT_propDstIdx_1_0_dummy2_1_read__272_273_OR_I_ETC___d1316,
mmioPlatform_cycle_10_ULT_99___d311,
mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935,
mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d294,
mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575,
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320,
mmioPlatform_reqBE_BIT_0___h28447,
mmioPlatform_reqBE_BIT_4___h28407,
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d426,
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d530,
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d595,
mmioPlatform_toHostQ_enqReq_dummy2_2_read__04__ETC___d216,
n__read_child__h59355,
n__read_child__h59440,
n__read_child__h77972,
n__read_child__h78051,
n__read_snd_id__h92141,
propDstData_0_dummy2_1_read__051_AND_IF_propDs_ETC___d1087,
propDstData_1_dummy2_1_read__056_AND_IF_propDs_ETC___d1091,
x__h59168,
x__h72720,
x__h77791;
// action method hart0_server_reset_request_put
assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_hart0_server_reset_request_put =
EN_hart0_server_reset_request_put ;
// action method hart0_server_reset_response_get
assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_server_reset_response_get =
EN_hart0_server_reset_response_get ;
// action method start
assign RDY_start = mmioPlatform_state == 2'd0 ;
assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ;
assign WILL_FIRE_start = EN_start ;
// value method master0_m_awvalid
assign master0_awvalid = llc_axi4_adapter_master_xactor_crg_wr_addr_full ;
// value method master0_m_awid
assign master0_awid = llc_axi4_adapter_master_xactor_rg_wr_addr[96:93] ;
// value method master0_m_awaddr
assign master0_awaddr = llc_axi4_adapter_master_xactor_rg_wr_addr[92:29] ;
// value method master0_m_awlen
assign master0_awlen = llc_axi4_adapter_master_xactor_rg_wr_addr[28:21] ;
// value method master0_m_awsize
assign master0_awsize = llc_axi4_adapter_master_xactor_rg_wr_addr[20:18] ;
// value method master0_m_awburst
assign master0_awburst = llc_axi4_adapter_master_xactor_rg_wr_addr[17:16] ;
// value method master0_m_awlock
assign master0_awlock = llc_axi4_adapter_master_xactor_rg_wr_addr[15] ;
// value method master0_m_awcache
assign master0_awcache = llc_axi4_adapter_master_xactor_rg_wr_addr[14:11] ;
// value method master0_m_awprot
assign master0_awprot = llc_axi4_adapter_master_xactor_rg_wr_addr[10:8] ;
// value method master0_m_awqos
assign master0_awqos = llc_axi4_adapter_master_xactor_rg_wr_addr[7:4] ;
// value method master0_m_awregion
assign master0_awregion = llc_axi4_adapter_master_xactor_rg_wr_addr[3:0] ;
// action method master0_m_awready
assign CAN_FIRE_master0_m_awready = 1'd1 ;
assign WILL_FIRE_master0_m_awready = 1'd1 ;
// value method master0_m_wvalid
assign master0_wvalid = llc_axi4_adapter_master_xactor_crg_wr_data_full ;
// value method master0_m_wid
assign master0_wid = llc_axi4_adapter_master_xactor_rg_wr_data[76:73] ;
// value method master0_m_wdata
assign master0_wdata = llc_axi4_adapter_master_xactor_rg_wr_data[72:9] ;
// value method master0_m_wstrb
assign master0_wstrb = llc_axi4_adapter_master_xactor_rg_wr_data[8:1] ;
// value method master0_m_wlast
assign master0_wlast = llc_axi4_adapter_master_xactor_rg_wr_data[0] ;
// action method master0_m_wready
assign CAN_FIRE_master0_m_wready = 1'd1 ;
assign WILL_FIRE_master0_m_wready = 1'd1 ;
// action method master0_m_bvalid
assign CAN_FIRE_master0_m_bvalid = 1'd1 ;
assign WILL_FIRE_master0_m_bvalid = 1'd1 ;
// value method master0_m_bready
assign master0_bready =
!llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
// value method master0_m_arvalid
assign master0_arvalid = llc_axi4_adapter_master_xactor_crg_rd_addr_full ;
// value method master0_m_arid
assign master0_arid = llc_axi4_adapter_master_xactor_rg_rd_addr[96:93] ;
// value method master0_m_araddr
assign master0_araddr = llc_axi4_adapter_master_xactor_rg_rd_addr[92:29] ;
// value method master0_m_arlen
assign master0_arlen = llc_axi4_adapter_master_xactor_rg_rd_addr[28:21] ;
// value method master0_m_arsize
assign master0_arsize = llc_axi4_adapter_master_xactor_rg_rd_addr[20:18] ;
// value method master0_m_arburst
assign master0_arburst = llc_axi4_adapter_master_xactor_rg_rd_addr[17:16] ;
// value method master0_m_arlock
assign master0_arlock = llc_axi4_adapter_master_xactor_rg_rd_addr[15] ;
// value method master0_m_arcache
assign master0_arcache = llc_axi4_adapter_master_xactor_rg_rd_addr[14:11] ;
// value method master0_m_arprot
assign master0_arprot = llc_axi4_adapter_master_xactor_rg_rd_addr[10:8] ;
// value method master0_m_arqos
assign master0_arqos = llc_axi4_adapter_master_xactor_rg_rd_addr[7:4] ;
// value method master0_m_arregion
assign master0_arregion = llc_axi4_adapter_master_xactor_rg_rd_addr[3:0] ;
// action method master0_m_arready
assign CAN_FIRE_master0_m_arready = 1'd1 ;
assign WILL_FIRE_master0_m_arready = 1'd1 ;
// action method master0_m_rvalid
assign CAN_FIRE_master0_m_rvalid = 1'd1 ;
assign WILL_FIRE_master0_m_rvalid = 1'd1 ;
// value method master0_m_rready
assign master0_rready =
!llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
// value method master1_m_awvalid
assign master1_awvalid = mmio_axi4_adapter_master_xactor_crg_wr_addr_full ;
// value method master1_m_awid
assign master1_awid = mmio_axi4_adapter_master_xactor_rg_wr_addr[96:93] ;
// value method master1_m_awaddr
assign master1_awaddr = mmio_axi4_adapter_master_xactor_rg_wr_addr[92:29] ;
// value method master1_m_awlen
assign master1_awlen = mmio_axi4_adapter_master_xactor_rg_wr_addr[28:21] ;
// value method master1_m_awsize
assign master1_awsize = mmio_axi4_adapter_master_xactor_rg_wr_addr[20:18] ;
// value method master1_m_awburst
assign master1_awburst = mmio_axi4_adapter_master_xactor_rg_wr_addr[17:16] ;
// value method master1_m_awlock
assign master1_awlock = mmio_axi4_adapter_master_xactor_rg_wr_addr[15] ;
// value method master1_m_awcache
assign master1_awcache = mmio_axi4_adapter_master_xactor_rg_wr_addr[14:11] ;
// value method master1_m_awprot
assign master1_awprot = mmio_axi4_adapter_master_xactor_rg_wr_addr[10:8] ;
// value method master1_m_awqos
assign master1_awqos = mmio_axi4_adapter_master_xactor_rg_wr_addr[7:4] ;
// value method master1_m_awregion
assign master1_awregion = mmio_axi4_adapter_master_xactor_rg_wr_addr[3:0] ;
// action method master1_m_awready
assign CAN_FIRE_master1_m_awready = 1'd1 ;
assign WILL_FIRE_master1_m_awready = 1'd1 ;
// value method master1_m_wvalid
assign master1_wvalid = mmio_axi4_adapter_master_xactor_crg_wr_data_full ;
// value method master1_m_wid
assign master1_wid = mmio_axi4_adapter_master_xactor_rg_wr_data[76:73] ;
// value method master1_m_wdata
assign master1_wdata = mmio_axi4_adapter_master_xactor_rg_wr_data[72:9] ;
// value method master1_m_wstrb
assign master1_wstrb = mmio_axi4_adapter_master_xactor_rg_wr_data[8:1] ;
// value method master1_m_wlast
assign master1_wlast = mmio_axi4_adapter_master_xactor_rg_wr_data[0] ;
// action method master1_m_wready
assign CAN_FIRE_master1_m_wready = 1'd1 ;
assign WILL_FIRE_master1_m_wready = 1'd1 ;
// action method master1_m_bvalid
assign CAN_FIRE_master1_m_bvalid = 1'd1 ;
assign WILL_FIRE_master1_m_bvalid = 1'd1 ;
// value method master1_m_bready
assign master1_bready =
!mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
// value method master1_m_arvalid
assign master1_arvalid = mmio_axi4_adapter_master_xactor_crg_rd_addr_full ;
// value method master1_m_arid
assign master1_arid = mmio_axi4_adapter_master_xactor_rg_rd_addr[96:93] ;
// value method master1_m_araddr
assign master1_araddr = mmio_axi4_adapter_master_xactor_rg_rd_addr[92:29] ;
// value method master1_m_arlen
assign master1_arlen = mmio_axi4_adapter_master_xactor_rg_rd_addr[28:21] ;
// value method master1_m_arsize
assign master1_arsize = mmio_axi4_adapter_master_xactor_rg_rd_addr[20:18] ;
// value method master1_m_arburst
assign master1_arburst = mmio_axi4_adapter_master_xactor_rg_rd_addr[17:16] ;
// value method master1_m_arlock
assign master1_arlock = mmio_axi4_adapter_master_xactor_rg_rd_addr[15] ;
// value method master1_m_arcache
assign master1_arcache = mmio_axi4_adapter_master_xactor_rg_rd_addr[14:11] ;
// value method master1_m_arprot
assign master1_arprot = mmio_axi4_adapter_master_xactor_rg_rd_addr[10:8] ;
// value method master1_m_arqos
assign master1_arqos = mmio_axi4_adapter_master_xactor_rg_rd_addr[7:4] ;
// value method master1_m_arregion
assign master1_arregion = mmio_axi4_adapter_master_xactor_rg_rd_addr[3:0] ;
// action method master1_m_arready
assign CAN_FIRE_master1_m_arready = 1'd1 ;
assign WILL_FIRE_master1_m_arready = 1'd1 ;
// action method master1_m_rvalid
assign CAN_FIRE_master1_m_rvalid = 1'd1 ;
assign WILL_FIRE_master1_m_rvalid = 1'd1 ;
// value method master1_m_rready
assign master1_rready =
!mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method debug_external_interrupt_req
assign CAN_FIRE_debug_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_debug_external_interrupt_req = 1'd1 ;
// action method non_maskable_interrupt_req
assign CAN_FIRE_non_maskable_interrupt_req = 1'd1 ;
assign WILL_FIRE_non_maskable_interrupt_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// actionvalue method trace_data_out_get
assign trace_data_out_get = f_trace_data$D_OUT ;
assign RDY_trace_data_out_get = f_trace_data$EMPTY_N ;
assign CAN_FIRE_trace_data_out_get = f_trace_data$EMPTY_N ;
assign WILL_FIRE_trace_data_out_get = EN_trace_data_out_get ;
// action method hart0_server_run_halt_request_put
assign RDY_hart0_server_run_halt_request_put = f_run_halt_reqs$FULL_N ;
assign CAN_FIRE_hart0_server_run_halt_request_put = f_run_halt_reqs$FULL_N ;
assign WILL_FIRE_hart0_server_run_halt_request_put =
EN_hart0_server_run_halt_request_put ;
// actionvalue method hart0_server_run_halt_response_get
assign hart0_server_run_halt_response_get = f_run_halt_rsps$D_OUT ;
assign RDY_hart0_server_run_halt_response_get = f_run_halt_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_server_run_halt_response_get =
f_run_halt_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_server_run_halt_response_get =
EN_hart0_server_run_halt_response_get ;
// action method hart0_put_other_req_put
assign RDY_hart0_put_other_req_put = 1'd1 ;
assign CAN_FIRE_hart0_put_other_req_put = 1'd1 ;
assign WILL_FIRE_hart0_put_other_req_put = EN_hart0_put_other_req_put ;
// action method hart0_gpr_mem_server_request_put
assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_gpr_mem_server_request_put =
EN_hart0_gpr_mem_server_request_put ;
// actionvalue method hart0_gpr_mem_server_response_get
assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ;
assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_gpr_mem_server_response_get =
EN_hart0_gpr_mem_server_response_get ;
// action method hart0_fpr_mem_server_request_put
assign RDY_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_fpr_mem_server_request_put =
EN_hart0_fpr_mem_server_request_put ;
// actionvalue method hart0_fpr_mem_server_response_get
assign hart0_fpr_mem_server_response_get = f_fpr_rsps$D_OUT ;
assign RDY_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_fpr_mem_server_response_get =
EN_hart0_fpr_mem_server_response_get ;
// action method hart0_csr_mem_server_request_put
assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign WILL_FIRE_hart0_csr_mem_server_request_put =
EN_hart0_csr_mem_server_request_put ;
// actionvalue method hart0_csr_mem_server_response_get
assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ;
assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_csr_mem_server_response_get =
EN_hart0_csr_mem_server_response_get ;
// submodule core_0
mkCore core_0(.CLK(CLK),
.RST_N(RST_N),
.coreReq_perfReq_loc(core_0$coreReq_perfReq_loc),
.coreReq_perfReq_t(core_0$coreReq_perfReq_t),
.coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr),
.coreReq_start_startpc(core_0$coreReq_start_startpc),
.coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr),
.dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x),
.iCacheToParent_fromP_enq_x(core_0$iCacheToParent_fromP_enq_x),
.mmioToPlatform_pRq_enq_x(core_0$mmioToPlatform_pRq_enq_x),
.mmioToPlatform_pRs_enq_x(core_0$mmioToPlatform_pRs_enq_x),
.mmioToPlatform_setTime_t(core_0$mmioToPlatform_setTime_t),
.recvDoStats_x(core_0$recvDoStats_x),
.setDEIP_v(core_0$setDEIP_v),
.setMEIP_v(core_0$setMEIP_v),
.setSEIP_v(core_0$setSEIP_v),
.tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x),
.EN_coreReq_start(core_0$EN_coreReq_start),
.EN_coreReq_perfReq(core_0$EN_coreReq_perfReq),
.EN_coreIndInv_perfResp(core_0$EN_coreIndInv_perfResp),
.EN_coreIndInv_terminate(core_0$EN_coreIndInv_terminate),
.EN_dCacheToParent_rsToP_deq(core_0$EN_dCacheToParent_rsToP_deq),
.EN_dCacheToParent_rqToP_deq(core_0$EN_dCacheToParent_rqToP_deq),
.EN_dCacheToParent_fromP_enq(core_0$EN_dCacheToParent_fromP_enq),
.EN_iCacheToParent_rsToP_deq(core_0$EN_iCacheToParent_rsToP_deq),
.EN_iCacheToParent_rqToP_deq(core_0$EN_iCacheToParent_rqToP_deq),
.EN_iCacheToParent_fromP_enq(core_0$EN_iCacheToParent_fromP_enq),
.EN_tlbToMem_memReq_deq(core_0$EN_tlbToMem_memReq_deq),
.EN_tlbToMem_respLd_enq(core_0$EN_tlbToMem_respLd_enq),
.EN_mmioToPlatform_cRq_deq(core_0$EN_mmioToPlatform_cRq_deq),
.EN_mmioToPlatform_pRs_enq(core_0$EN_mmioToPlatform_pRs_enq),
.EN_mmioToPlatform_pRq_enq(core_0$EN_mmioToPlatform_pRq_enq),
.EN_mmioToPlatform_cRs_deq(core_0$EN_mmioToPlatform_cRs_deq),
.EN_mmioToPlatform_setTime(core_0$EN_mmioToPlatform_setTime),
.EN_sendDoStats(core_0$EN_sendDoStats),
.EN_recvDoStats(core_0$EN_recvDoStats),
.EN_deadlock_dCacheCRqStuck_get(core_0$EN_deadlock_dCacheCRqStuck_get),
.EN_deadlock_dCachePRqStuck_get(core_0$EN_deadlock_dCachePRqStuck_get),
.EN_deadlock_iCacheCRqStuck_get(core_0$EN_deadlock_iCacheCRqStuck_get),
.EN_deadlock_iCachePRqStuck_get(core_0$EN_deadlock_iCachePRqStuck_get),
.EN_deadlock_renameInstStuck_get(core_0$EN_deadlock_renameInstStuck_get),
.EN_deadlock_renameCorrectPathStuck_get(core_0$EN_deadlock_renameCorrectPathStuck_get),
.EN_deadlock_commitInstStuck_get(core_0$EN_deadlock_commitInstStuck_get),
.EN_deadlock_commitUserInstStuck_get(core_0$EN_deadlock_commitUserInstStuck_get),
.EN_deadlock_checkStarted_get(core_0$EN_deadlock_checkStarted_get),
.EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get),
.EN_setMEIP(core_0$EN_setMEIP),
.EN_setSEIP(core_0$EN_setSEIP),
.EN_setDEIP(core_0$EN_setDEIP),
.RDY_coreReq_start(),
.RDY_coreReq_perfReq(),
.coreIndInv_perfResp(),
.RDY_coreIndInv_perfResp(),
.RDY_coreIndInv_terminate(core_0$RDY_coreIndInv_terminate),
.dCacheToParent_rsToP_notEmpty(),
.RDY_dCacheToParent_rsToP_notEmpty(),
.RDY_dCacheToParent_rsToP_deq(core_0$RDY_dCacheToParent_rsToP_deq),
.dCacheToParent_rsToP_first(core_0$dCacheToParent_rsToP_first),
.RDY_dCacheToParent_rsToP_first(core_0$RDY_dCacheToParent_rsToP_first),
.dCacheToParent_rqToP_notEmpty(),
.RDY_dCacheToParent_rqToP_notEmpty(),
.RDY_dCacheToParent_rqToP_deq(core_0$RDY_dCacheToParent_rqToP_deq),
.dCacheToParent_rqToP_first(core_0$dCacheToParent_rqToP_first),
.RDY_dCacheToParent_rqToP_first(core_0$RDY_dCacheToParent_rqToP_first),
.dCacheToParent_fromP_notFull(),
.RDY_dCacheToParent_fromP_notFull(),
.RDY_dCacheToParent_fromP_enq(core_0$RDY_dCacheToParent_fromP_enq),
.iCacheToParent_rsToP_notEmpty(),
.RDY_iCacheToParent_rsToP_notEmpty(),
.RDY_iCacheToParent_rsToP_deq(core_0$RDY_iCacheToParent_rsToP_deq),
.iCacheToParent_rsToP_first(core_0$iCacheToParent_rsToP_first),
.RDY_iCacheToParent_rsToP_first(core_0$RDY_iCacheToParent_rsToP_first),
.iCacheToParent_rqToP_notEmpty(),
.RDY_iCacheToParent_rqToP_notEmpty(),
.RDY_iCacheToParent_rqToP_deq(core_0$RDY_iCacheToParent_rqToP_deq),
.iCacheToParent_rqToP_first(core_0$iCacheToParent_rqToP_first),
.RDY_iCacheToParent_rqToP_first(core_0$RDY_iCacheToParent_rqToP_first),
.iCacheToParent_fromP_notFull(),
.RDY_iCacheToParent_fromP_notFull(),
.RDY_iCacheToParent_fromP_enq(core_0$RDY_iCacheToParent_fromP_enq),
.tlbToMem_memReq_notEmpty(),
.RDY_tlbToMem_memReq_notEmpty(),
.RDY_tlbToMem_memReq_deq(core_0$RDY_tlbToMem_memReq_deq),
.tlbToMem_memReq_first(core_0$tlbToMem_memReq_first),
.RDY_tlbToMem_memReq_first(core_0$RDY_tlbToMem_memReq_first),
.tlbToMem_respLd_notFull(),
.RDY_tlbToMem_respLd_notFull(),
.RDY_tlbToMem_respLd_enq(core_0$RDY_tlbToMem_respLd_enq),
.mmioToPlatform_cRq_notEmpty(core_0$mmioToPlatform_cRq_notEmpty),
.RDY_mmioToPlatform_cRq_notEmpty(),
.RDY_mmioToPlatform_cRq_deq(core_0$RDY_mmioToPlatform_cRq_deq),
.mmioToPlatform_cRq_first(core_0$mmioToPlatform_cRq_first),
.RDY_mmioToPlatform_cRq_first(core_0$RDY_mmioToPlatform_cRq_first),
.mmioToPlatform_pRs_notFull(),
.RDY_mmioToPlatform_pRs_notFull(),
.RDY_mmioToPlatform_pRs_enq(core_0$RDY_mmioToPlatform_pRs_enq),
.mmioToPlatform_pRq_notFull(),
.RDY_mmioToPlatform_pRq_notFull(),
.RDY_mmioToPlatform_pRq_enq(core_0$RDY_mmioToPlatform_pRq_enq),
.mmioToPlatform_cRs_notEmpty(),
.RDY_mmioToPlatform_cRs_notEmpty(),
.RDY_mmioToPlatform_cRs_deq(core_0$RDY_mmioToPlatform_cRs_deq),
.mmioToPlatform_cRs_first(core_0$mmioToPlatform_cRs_first),
.RDY_mmioToPlatform_cRs_first(core_0$RDY_mmioToPlatform_cRs_first),
.RDY_mmioToPlatform_setTime(),
.sendDoStats(core_0$sendDoStats),
.RDY_sendDoStats(core_0$RDY_sendDoStats),
.RDY_recvDoStats(),
.deadlock_dCacheCRqStuck_get(),
.RDY_deadlock_dCacheCRqStuck_get(core_0$RDY_deadlock_dCacheCRqStuck_get),
.deadlock_dCachePRqStuck_get(),
.RDY_deadlock_dCachePRqStuck_get(core_0$RDY_deadlock_dCachePRqStuck_get),
.deadlock_iCacheCRqStuck_get(),
.RDY_deadlock_iCacheCRqStuck_get(core_0$RDY_deadlock_iCacheCRqStuck_get),
.deadlock_iCachePRqStuck_get(),
.RDY_deadlock_iCachePRqStuck_get(core_0$RDY_deadlock_iCachePRqStuck_get),
.deadlock_renameInstStuck_get(),
.RDY_deadlock_renameInstStuck_get(core_0$RDY_deadlock_renameInstStuck_get),
.deadlock_renameCorrectPathStuck_get(),
.RDY_deadlock_renameCorrectPathStuck_get(core_0$RDY_deadlock_renameCorrectPathStuck_get),
.deadlock_commitInstStuck_get(),
.RDY_deadlock_commitInstStuck_get(core_0$RDY_deadlock_commitInstStuck_get),
.deadlock_commitUserInstStuck_get(),
.RDY_deadlock_commitUserInstStuck_get(core_0$RDY_deadlock_commitUserInstStuck_get),
.RDY_deadlock_checkStarted_get(core_0$RDY_deadlock_checkStarted_get),
.renameDebug_renameErr_get(),
.RDY_renameDebug_renameErr_get(core_0$RDY_renameDebug_renameErr_get),
.RDY_setMEIP(),
.RDY_setSEIP(),
.RDY_setDEIP());
// submodule enqDst_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0(.CLK(CLK),
.D_IN(enqDst_0_dummy2_0$D_IN),
.EN(enqDst_0_dummy2_0$EN),
.Q_OUT(enqDst_0_dummy2_0$Q_OUT));
// submodule enqDst_0_dummy2_0_1
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_0_1(.CLK(CLK),
.D_IN(enqDst_0_dummy2_0_1$D_IN),
.EN(enqDst_0_dummy2_0_1$EN),
.Q_OUT(enqDst_0_dummy2_0_1$Q_OUT));
// submodule enqDst_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_1(.CLK(CLK),
.D_IN(enqDst_0_dummy2_1$D_IN),
.EN(enqDst_0_dummy2_1$EN),
.Q_OUT(enqDst_0_dummy2_1$Q_OUT));
// submodule enqDst_0_dummy2_1_1
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_0_dummy2_1_1(.CLK(CLK),
.D_IN(enqDst_0_dummy2_1_1$D_IN),
.EN(enqDst_0_dummy2_1_1$EN),
.Q_OUT(enqDst_0_dummy2_1_1$Q_OUT));
// submodule enqDst_1_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_0(.CLK(CLK),
.D_IN(enqDst_1_0_dummy2_0$D_IN),
.EN(enqDst_1_0_dummy2_0$EN),
.Q_OUT(enqDst_1_0_dummy2_0$Q_OUT));
// submodule enqDst_1_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) enqDst_1_0_dummy2_1(.CLK(CLK),
.D_IN(enqDst_1_0_dummy2_1$D_IN),
.EN(enqDst_1_0_dummy2_1$EN),
.Q_OUT(enqDst_1_0_dummy2_1$Q_OUT));
// submodule f_csr_reqs
FIFO1 #(.width(32'd77), .guarded(32'd1)) f_csr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_reqs$D_IN),
.ENQ(f_csr_reqs$ENQ),
.DEQ(f_csr_reqs$DEQ),
.CLR(f_csr_reqs$CLR),
.D_OUT(),
.FULL_N(f_csr_reqs$FULL_N),
.EMPTY_N());
// submodule f_csr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_csr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_rsps$D_IN),
.ENQ(f_csr_rsps$ENQ),
.DEQ(f_csr_rsps$DEQ),
.CLR(f_csr_rsps$CLR),
.D_OUT(f_csr_rsps$D_OUT),
.FULL_N(),
.EMPTY_N(f_csr_rsps$EMPTY_N));
// submodule f_fpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_fpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_reqs$D_IN),
.ENQ(f_fpr_reqs$ENQ),
.DEQ(f_fpr_reqs$DEQ),
.CLR(f_fpr_reqs$CLR),
.D_OUT(),
.FULL_N(f_fpr_reqs$FULL_N),
.EMPTY_N());
// submodule f_fpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_fpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_rsps$D_IN),
.ENQ(f_fpr_rsps$ENQ),
.DEQ(f_fpr_rsps$DEQ),
.CLR(f_fpr_rsps$CLR),
.D_OUT(f_fpr_rsps$D_OUT),
.FULL_N(),
.EMPTY_N(f_fpr_rsps$EMPTY_N));
// submodule f_gpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_reqs$D_IN),
.ENQ(f_gpr_reqs$ENQ),
.DEQ(f_gpr_reqs$DEQ),
.CLR(f_gpr_reqs$CLR),
.D_OUT(),
.FULL_N(f_gpr_reqs$FULL_N),
.EMPTY_N());
// submodule f_gpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_rsps$D_IN),
.ENQ(f_gpr_rsps$ENQ),
.DEQ(f_gpr_rsps$DEQ),
.CLR(f_gpr_rsps$CLR),
.D_OUT(f_gpr_rsps$D_OUT),
.FULL_N(),
.EMPTY_N(f_gpr_rsps$EMPTY_N));
// submodule f_reset_reqs
FIFO20 #(.guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO20 #(.guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule f_run_halt_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_reqs$D_IN),
.ENQ(f_run_halt_reqs$ENQ),
.DEQ(f_run_halt_reqs$DEQ),
.CLR(f_run_halt_reqs$CLR),
.D_OUT(),
.FULL_N(f_run_halt_reqs$FULL_N),
.EMPTY_N());
// submodule f_run_halt_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_rsps$D_IN),
.ENQ(f_run_halt_rsps$ENQ),
.DEQ(f_run_halt_rsps$DEQ),
.CLR(f_run_halt_rsps$CLR),
.D_OUT(f_run_halt_rsps$D_OUT),
.FULL_N(),
.EMPTY_N(f_run_halt_rsps$EMPTY_N));
// submodule f_trace_data
FIFO2 #(.width(32'd362), .guarded(32'd1)) f_trace_data(.RST(RST_N),
.CLK(CLK),
.D_IN(f_trace_data$D_IN),
.ENQ(f_trace_data$ENQ),
.DEQ(f_trace_data$DEQ),
.CLR(f_trace_data$CLR),
.D_OUT(f_trace_data$D_OUT),
.FULL_N(),
.EMPTY_N(f_trace_data$EMPTY_N));
// submodule llc
mkLLCache llc(.CLK(CLK),
.RST_N(RST_N),
.dma_memReq_enq_x(llc$dma_memReq_enq_x),
.perf_req_r(llc$perf_req_r),
.perf_setStatus_doStats(llc$perf_setStatus_doStats),
.to_child_rqFromC_enq_x(llc$to_child_rqFromC_enq_x),
.to_child_rsFromC_enq_x(llc$to_child_rsFromC_enq_x),
.to_mem_rsFromM_enq_x(llc$to_mem_rsFromM_enq_x),
.EN_to_child_rsFromC_enq(llc$EN_to_child_rsFromC_enq),
.EN_to_child_rqFromC_enq(llc$EN_to_child_rqFromC_enq),
.EN_to_child_toC_deq(llc$EN_to_child_toC_deq),
.EN_dma_memReq_enq(llc$EN_dma_memReq_enq),
.EN_dma_respLd_deq(llc$EN_dma_respLd_deq),
.EN_dma_respSt_deq(llc$EN_dma_respSt_deq),
.EN_to_mem_toM_deq(llc$EN_to_mem_toM_deq),
.EN_to_mem_rsFromM_enq(llc$EN_to_mem_rsFromM_enq),
.EN_cRqStuck_get(llc$EN_cRqStuck_get),
.EN_perf_setStatus(llc$EN_perf_setStatus),
.EN_perf_req(llc$EN_perf_req),
.EN_perf_resp(llc$EN_perf_resp),
.to_child_rsFromC_notFull(),
.RDY_to_child_rsFromC_notFull(),
.RDY_to_child_rsFromC_enq(llc$RDY_to_child_rsFromC_enq),
.to_child_rqFromC_notFull(),
.RDY_to_child_rqFromC_notFull(),
.RDY_to_child_rqFromC_enq(llc$RDY_to_child_rqFromC_enq),
.to_child_toC_notEmpty(),
.RDY_to_child_toC_notEmpty(),
.RDY_to_child_toC_deq(llc$RDY_to_child_toC_deq),
.to_child_toC_first(llc$to_child_toC_first),
.RDY_to_child_toC_first(llc$RDY_to_child_toC_first),
.dma_memReq_notFull(),
.RDY_dma_memReq_notFull(),
.RDY_dma_memReq_enq(llc$RDY_dma_memReq_enq),
.dma_respLd_notEmpty(),
.RDY_dma_respLd_notEmpty(),
.RDY_dma_respLd_deq(llc$RDY_dma_respLd_deq),
.dma_respLd_first(llc$dma_respLd_first),
.RDY_dma_respLd_first(llc$RDY_dma_respLd_first),
.dma_respSt_notEmpty(),
.RDY_dma_respSt_notEmpty(),
.RDY_dma_respSt_deq(llc$RDY_dma_respSt_deq),
.dma_respSt_first(llc$dma_respSt_first),
.RDY_dma_respSt_first(llc$RDY_dma_respSt_first),
.to_mem_toM_notEmpty(),
.RDY_to_mem_toM_notEmpty(),
.RDY_to_mem_toM_deq(llc$RDY_to_mem_toM_deq),
.to_mem_toM_first(llc$to_mem_toM_first),
.RDY_to_mem_toM_first(llc$RDY_to_mem_toM_first),
.to_mem_rsFromM_notFull(),
.RDY_to_mem_rsFromM_notFull(),
.RDY_to_mem_rsFromM_enq(llc$RDY_to_mem_rsFromM_enq),
.cRqStuck_get(),
.RDY_cRqStuck_get(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule llc_axi4_adapter_f_pending_reads
FIFO2 #(.width(32'd69),
.guarded(32'd1)) llc_axi4_adapter_f_pending_reads(.RST(RST_N),
.CLK(CLK),
.D_IN(llc_axi4_adapter_f_pending_reads$D_IN),
.ENQ(llc_axi4_adapter_f_pending_reads$ENQ),
.DEQ(llc_axi4_adapter_f_pending_reads$DEQ),
.CLR(llc_axi4_adapter_f_pending_reads$CLR),
.D_OUT(llc_axi4_adapter_f_pending_reads$D_OUT),
.FULL_N(llc_axi4_adapter_f_pending_reads$FULL_N),
.EMPTY_N(llc_axi4_adapter_f_pending_reads$EMPTY_N));
// submodule llc_axi4_adapter_f_pending_writes
FIFO2 #(.width(32'd640),
.guarded(32'd1)) llc_axi4_adapter_f_pending_writes(.RST(RST_N),
.CLK(CLK),
.D_IN(llc_axi4_adapter_f_pending_writes$D_IN),
.ENQ(llc_axi4_adapter_f_pending_writes$ENQ),
.DEQ(llc_axi4_adapter_f_pending_writes$DEQ),
.CLR(llc_axi4_adapter_f_pending_writes$CLR),
.D_OUT(),
.FULL_N(llc_axi4_adapter_f_pending_writes$FULL_N),
.EMPTY_N(llc_axi4_adapter_f_pending_writes$EMPTY_N));
// submodule mmioPlatform_fromHostQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN),
.EN(mmioPlatform_fromHostQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmioPlatform_fromHostQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN),
.EN(mmioPlatform_fromHostQ_clearReq_dummy2_1$EN),
.Q_OUT(mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT));
// submodule mmioPlatform_fromHostQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN),
.EN(mmioPlatform_fromHostQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmioPlatform_fromHostQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN),
.EN(mmioPlatform_fromHostQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmioPlatform_fromHostQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN),
.EN(mmioPlatform_fromHostQ_deqReq_dummy2_2$EN),
.Q_OUT(mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT));
// submodule mmioPlatform_fromHostQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN),
.EN(mmioPlatform_fromHostQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmioPlatform_fromHostQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN),
.EN(mmioPlatform_fromHostQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmioPlatform_fromHostQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_fromHostQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN),
.EN(mmioPlatform_fromHostQ_enqReq_dummy2_2$EN),
.Q_OUT(mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT));
// submodule mmioPlatform_toHostQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN),
.EN(mmioPlatform_toHostQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmioPlatform_toHostQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN),
.EN(mmioPlatform_toHostQ_clearReq_dummy2_1$EN),
.Q_OUT(mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT));
// submodule mmioPlatform_toHostQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN),
.EN(mmioPlatform_toHostQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmioPlatform_toHostQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN),
.EN(mmioPlatform_toHostQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmioPlatform_toHostQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN),
.EN(mmioPlatform_toHostQ_deqReq_dummy2_2$EN),
.Q_OUT(mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT));
// submodule mmioPlatform_toHostQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN),
.EN(mmioPlatform_toHostQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmioPlatform_toHostQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN),
.EN(mmioPlatform_toHostQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmioPlatform_toHostQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmioPlatform_toHostQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN),
.EN(mmioPlatform_toHostQ_enqReq_dummy2_2$EN),
.Q_OUT(mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_axi4_adapter_f_reqs_from_core
FIFO2 #(.width(32'd142),
.guarded(32'd1)) mmio_axi4_adapter_f_reqs_from_core(.RST(RST_N),
.CLK(CLK),
.D_IN(mmio_axi4_adapter_f_reqs_from_core$D_IN),
.ENQ(mmio_axi4_adapter_f_reqs_from_core$ENQ),
.DEQ(mmio_axi4_adapter_f_reqs_from_core$DEQ),
.CLR(mmio_axi4_adapter_f_reqs_from_core$CLR),
.D_OUT(mmio_axi4_adapter_f_reqs_from_core$D_OUT),
.FULL_N(mmio_axi4_adapter_f_reqs_from_core$FULL_N),
.EMPTY_N(mmio_axi4_adapter_f_reqs_from_core$EMPTY_N));
// submodule mmio_axi4_adapter_f_rsps_to_core
FIFO2 #(.width(32'd65),
.guarded(32'd1)) mmio_axi4_adapter_f_rsps_to_core(.RST(RST_N),
.CLK(CLK),
.D_IN(mmio_axi4_adapter_f_rsps_to_core$D_IN),
.ENQ(mmio_axi4_adapter_f_rsps_to_core$ENQ),
.DEQ(mmio_axi4_adapter_f_rsps_to_core$DEQ),
.CLR(mmio_axi4_adapter_f_rsps_to_core$CLR),
.D_OUT(mmio_axi4_adapter_f_rsps_to_core$D_OUT),
.FULL_N(mmio_axi4_adapter_f_rsps_to_core$FULL_N),
.EMPTY_N(mmio_axi4_adapter_f_rsps_to_core$EMPTY_N));
// submodule propDstData_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_0(.CLK(CLK),
.D_IN(propDstData_0_dummy2_0$D_IN),
.EN(propDstData_0_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_0_dummy2_0_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_0_1(.CLK(CLK),
.D_IN(propDstData_0_dummy2_0_1$D_IN),
.EN(propDstData_0_dummy2_0_1$EN),
.Q_OUT());
// submodule propDstData_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_1(.CLK(CLK),
.D_IN(propDstData_0_dummy2_1$D_IN),
.EN(propDstData_0_dummy2_1$EN),
.Q_OUT(propDstData_0_dummy2_1$Q_OUT));
// submodule propDstData_0_dummy2_1_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_0_dummy2_1_1(.CLK(CLK),
.D_IN(propDstData_0_dummy2_1_1$D_IN),
.EN(propDstData_0_dummy2_1_1$EN),
.Q_OUT(propDstData_0_dummy2_1_1$Q_OUT));
// submodule propDstData_1_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_0(.CLK(CLK),
.D_IN(propDstData_1_0_dummy2_0$D_IN),
.EN(propDstData_1_0_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_1_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_0_dummy2_1(.CLK(CLK),
.D_IN(propDstData_1_0_dummy2_1$D_IN),
.EN(propDstData_1_0_dummy2_1$EN),
.Q_OUT(propDstData_1_0_dummy2_1$Q_OUT));
// submodule propDstData_1_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_0(.CLK(CLK),
.D_IN(propDstData_1_1_dummy2_0$D_IN),
.EN(propDstData_1_1_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_1_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_1_dummy2_1(.CLK(CLK),
.D_IN(propDstData_1_1_dummy2_1$D_IN),
.EN(propDstData_1_1_dummy2_1$EN),
.Q_OUT(propDstData_1_1_dummy2_1$Q_OUT));
// submodule propDstData_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_0(.CLK(CLK),
.D_IN(propDstData_1_dummy2_0$D_IN),
.EN(propDstData_1_dummy2_0$EN),
.Q_OUT());
// submodule propDstData_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstData_1_dummy2_1(.CLK(CLK),
.D_IN(propDstData_1_dummy2_1$D_IN),
.EN(propDstData_1_dummy2_1$EN),
.Q_OUT(propDstData_1_dummy2_1$Q_OUT));
// submodule propDstIdx_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_0_dummy2_0$D_IN),
.EN(propDstIdx_0_dummy2_0$EN),
.Q_OUT(propDstIdx_0_dummy2_0$Q_OUT));
// submodule propDstIdx_0_dummy2_0_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_0_1(.CLK(CLK),
.D_IN(propDstIdx_0_dummy2_0_1$D_IN),
.EN(propDstIdx_0_dummy2_0_1$EN),
.Q_OUT(propDstIdx_0_dummy2_0_1$Q_OUT));
// submodule propDstIdx_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_0_dummy2_1$D_IN),
.EN(propDstIdx_0_dummy2_1$EN),
.Q_OUT(propDstIdx_0_dummy2_1$Q_OUT));
// submodule propDstIdx_0_dummy2_1_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_0_dummy2_1_1(.CLK(CLK),
.D_IN(propDstIdx_0_dummy2_1_1$D_IN),
.EN(propDstIdx_0_dummy2_1_1$EN),
.Q_OUT(propDstIdx_0_dummy2_1_1$Q_OUT));
// submodule propDstIdx_1_0_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_1_0_dummy2_0$D_IN),
.EN(propDstIdx_1_0_dummy2_0$EN),
.Q_OUT(propDstIdx_1_0_dummy2_0$Q_OUT));
// submodule propDstIdx_1_0_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_0_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_1_0_dummy2_1$D_IN),
.EN(propDstIdx_1_0_dummy2_1$EN),
.Q_OUT(propDstIdx_1_0_dummy2_1$Q_OUT));
// submodule propDstIdx_1_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_1_1_dummy2_0$D_IN),
.EN(propDstIdx_1_1_dummy2_0$EN),
.Q_OUT(propDstIdx_1_1_dummy2_0$Q_OUT));
// submodule propDstIdx_1_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_1_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_1_1_dummy2_1$D_IN),
.EN(propDstIdx_1_1_dummy2_1$EN),
.Q_OUT(propDstIdx_1_1_dummy2_1$Q_OUT));
// submodule propDstIdx_1_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_0(.CLK(CLK),
.D_IN(propDstIdx_1_dummy2_0$D_IN),
.EN(propDstIdx_1_dummy2_0$EN),
.Q_OUT(propDstIdx_1_dummy2_0$Q_OUT));
// submodule propDstIdx_1_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) propDstIdx_1_dummy2_1(.CLK(CLK),
.D_IN(propDstIdx_1_dummy2_1$D_IN),
.EN(propDstIdx_1_dummy2_1$EN),
.Q_OUT(propDstIdx_1_dummy2_1$Q_OUT));
// submodule tlbQ
FIFO2 #(.width(32'd65), .guarded(32'd1)) tlbQ(.RST(RST_N),
.CLK(CLK),
.D_IN(tlbQ$D_IN),
.ENQ(tlbQ$ENQ),
.DEQ(tlbQ$DEQ),
.CLR(tlbQ$CLR),
.D_OUT(tlbQ$D_OUT),
.FULL_N(tlbQ$FULL_N),
.EMPTY_N(tlbQ$EMPTY_N));
// rule RL_srcPropose
assign CAN_FIRE_RL_srcPropose =
core_0$RDY_dCacheToParent_rqToP_first &&
core_0$RDY_dCacheToParent_rqToP_deq &&
(!propDstIdx_0_dummy2_0$Q_OUT || !propDstIdx_0_dummy2_1$Q_OUT ||
!propDstIdx_0_rl) ;
assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ;
// rule RL_srcPropose_1
assign CAN_FIRE_RL_srcPropose_1 =
core_0$RDY_iCacheToParent_rqToP_first &&
core_0$RDY_iCacheToParent_rqToP_deq &&
(!propDstIdx_1_dummy2_0$Q_OUT || !propDstIdx_1_dummy2_1$Q_OUT ||
!propDstIdx_1_rl) ;
assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ;
// rule RL_dstSelectSrc
assign CAN_FIRE_RL_dstSelectSrc = 1'd1 ;
assign WILL_FIRE_RL_dstSelectSrc = 1'd1 ;
// rule RL_doEnq
assign CAN_FIRE_RL_doEnq =
llc$RDY_to_child_rqFromC_enq && enqDst_0_dummy2_1$Q_OUT &&
IF_enqDst_0_lat_0_whas__89_THEN_enqDst_0_lat_0_ETC___d994 ;
assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ;
// rule RL_srcPropose_2
assign CAN_FIRE_RL_srcPropose_2 =
core_0$RDY_dCacheToParent_rsToP_first &&
core_0$RDY_dCacheToParent_rsToP_deq &&
(!propDstIdx_1_0_dummy2_0$Q_OUT ||
!propDstIdx_1_0_dummy2_1$Q_OUT ||
!propDstIdx_1_0_rl) ;
assign WILL_FIRE_RL_srcPropose_2 = CAN_FIRE_RL_srcPropose_2 ;
// rule RL_srcPropose_3
assign CAN_FIRE_RL_srcPropose_3 =
core_0$RDY_iCacheToParent_rsToP_first &&
core_0$RDY_iCacheToParent_rsToP_deq &&
(!propDstIdx_1_1_dummy2_0$Q_OUT ||
!propDstIdx_1_1_dummy2_1$Q_OUT ||
!propDstIdx_1_1_rl) ;
assign WILL_FIRE_RL_srcPropose_3 = CAN_FIRE_RL_srcPropose_3 ;
// rule RL_dstSelectSrc_1
assign CAN_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
assign WILL_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
// rule RL_doEnq_1
assign CAN_FIRE_RL_doEnq_1 =
llc$RDY_to_child_rsFromC_enq && enqDst_1_0_dummy2_1$Q_OUT &&
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1225 ;
assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ;
// rule RL_sendPRq
assign CAN_FIRE_RL_sendPRq =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_dCacheToParent_fromP_enq &&
!llc$to_child_toC_first[583] &&
!llc$to_child_toC_first[0] ;
assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ;
// rule RL_sendPRs
assign CAN_FIRE_RL_sendPRs =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_dCacheToParent_fromP_enq &&
llc$to_child_toC_first[583] &&
!llc$to_child_toC_first[516] ;
assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ;
// rule RL_sendPRq_1
assign CAN_FIRE_RL_sendPRq_1 =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_iCacheToParent_fromP_enq &&
!llc$to_child_toC_first[583] &&
llc$to_child_toC_first[0] ;
assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ;
// rule RL_sendPRs_1
assign CAN_FIRE_RL_sendPRs_1 =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_iCacheToParent_fromP_enq &&
llc$to_child_toC_first[583] &&
llc$to_child_toC_first[516] ;
assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ;
// rule RL_srcPropose_4
assign CAN_FIRE_RL_srcPropose_4 =
core_0$RDY_tlbToMem_memReq_first &&
core_0$RDY_tlbToMem_memReq_deq &&
(!propDstIdx_0_dummy2_0_1$Q_OUT ||
!propDstIdx_0_dummy2_1_1$Q_OUT ||
!propDstIdx_0_rl_1) ;
assign WILL_FIRE_RL_srcPropose_4 = CAN_FIRE_RL_srcPropose_4 ;
// rule RL_dstSelectSrc_2
assign CAN_FIRE_RL_dstSelectSrc_2 = 1'd1 ;
assign WILL_FIRE_RL_dstSelectSrc_2 = 1'd1 ;
// rule RL_doEnq_2
assign CAN_FIRE_RL_doEnq_2 =
tlbQ$FULL_N && enqDst_0_dummy2_1_1$Q_OUT &&
IF_enqDst_0_lat_0_1_whas__476_THEN_enqDst_0_la_ETC___d1481 ;
assign WILL_FIRE_RL_doEnq_2 = CAN_FIRE_RL_doEnq_2 ;
// rule RL_sendTlbReqToLLC
assign CAN_FIRE_RL_sendTlbReqToLLC =
llc$RDY_dma_memReq_enq && tlbQ$EMPTY_N ;
assign WILL_FIRE_RL_sendTlbReqToLLC = CAN_FIRE_RL_sendTlbReqToLLC ;
// rule RL_sendLdRespToMemLoader
assign CAN_FIRE_RL_sendLdRespToMemLoader =
llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq &&
!llc$dma_respLd_first[4] ;
assign WILL_FIRE_RL_sendLdRespToMemLoader =
CAN_FIRE_RL_sendLdRespToMemLoader ;
// rule RL_sendLdRespToTlb
assign CAN_FIRE_RL_sendLdRespToTlb =
llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq &&
core_0$RDY_tlbToMem_respLd_enq &&
llc$dma_respLd_first[4] ;
assign WILL_FIRE_RL_sendLdRespToTlb = CAN_FIRE_RL_sendLdRespToTlb ;
// rule RL_sendStRespToMemLoader
assign CAN_FIRE_RL_sendStRespToMemLoader =
llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq &&
!llc$dma_respSt_first[4] ;
assign WILL_FIRE_RL_sendStRespToMemLoader =
CAN_FIRE_RL_sendStRespToMemLoader ;
// rule RL_sendStRespToTlb
assign CAN_FIRE_RL_sendStRespToTlb =
llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq &&
llc$dma_respSt_first[4] ;
assign WILL_FIRE_RL_sendStRespToTlb = CAN_FIRE_RL_sendStRespToTlb ;
// rule RL_broadcastStats
assign CAN_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ;
assign WILL_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ;
// rule RL_rl_dummy1
assign CAN_FIRE_RL_rl_dummy1 = core_0$RDY_deadlock_dCacheCRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy1 = core_0$RDY_deadlock_dCacheCRqStuck_get ;
// rule RL_rl_dummy2
assign CAN_FIRE_RL_rl_dummy2 = core_0$RDY_deadlock_dCachePRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy2 = core_0$RDY_deadlock_dCachePRqStuck_get ;
// rule RL_rl_dummy3
assign CAN_FIRE_RL_rl_dummy3 = core_0$RDY_deadlock_iCacheCRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy3 = core_0$RDY_deadlock_iCacheCRqStuck_get ;
// rule RL_rl_dummy4
assign CAN_FIRE_RL_rl_dummy4 = core_0$RDY_deadlock_iCachePRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy4 = core_0$RDY_deadlock_iCachePRqStuck_get ;
// rule RL_rl_dummy5
assign CAN_FIRE_RL_rl_dummy5 = core_0$RDY_deadlock_renameInstStuck_get ;
assign WILL_FIRE_RL_rl_dummy5 = core_0$RDY_deadlock_renameInstStuck_get ;
// rule RL_rl_dummy6
assign CAN_FIRE_RL_rl_dummy6 =
core_0$RDY_deadlock_renameCorrectPathStuck_get ;
assign WILL_FIRE_RL_rl_dummy6 =
core_0$RDY_deadlock_renameCorrectPathStuck_get ;
// rule RL_rl_dummy7
assign CAN_FIRE_RL_rl_dummy7 = core_0$RDY_deadlock_commitInstStuck_get ;
assign WILL_FIRE_RL_rl_dummy7 = core_0$RDY_deadlock_commitInstStuck_get ;
// rule RL_rl_dummy8
assign CAN_FIRE_RL_rl_dummy8 = core_0$RDY_deadlock_commitUserInstStuck_get ;
assign WILL_FIRE_RL_rl_dummy8 =
core_0$RDY_deadlock_commitUserInstStuck_get ;
// rule RL_rl_dummy9
assign CAN_FIRE_RL_rl_dummy9 = core_0$RDY_deadlock_checkStarted_get ;
assign WILL_FIRE_RL_rl_dummy9 = core_0$RDY_deadlock_checkStarted_get ;
// rule RL_rl_dummy20
assign CAN_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ;
assign WILL_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ;
// rule RL_rl_terminate
assign CAN_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ;
assign WILL_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ;
// rule RL_rl_tohost
assign CAN_FIRE_RL_rl_tohost = !mmioPlatform_toHostQ_empty ;
assign WILL_FIRE_RL_rl_tohost = CAN_FIRE_RL_rl_tohost ;
// rule RL_mmio_axi4_adapter_rl_handle_read_rsps
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps =
mmio_axi4_adapter_master_xactor_crg_rd_data_full &&
mmio_axi4_adapter_f_rsps_to_core$FULL_N ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;
// rule RL_mmio_axi4_adapter_rl_handle_write_req
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req =
!mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read &&
!mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read &&
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd2 ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ;
// rule RL_mmio_axi4_adapter_rl_handle_read_req
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req =
!mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read &&
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd1 &&
b__h3158 == 4'd0 ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
// rule RL_mmio_axi4_adapter_rl_discard_write_rsp
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp =
b__h3158 != 4'd0 &&
mmio_axi4_adapter_master_xactor_crg_wr_resp_full &&
(mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0 ||
mmio_axi4_adapter_f_rsps_to_core$FULL_N) ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp =
CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
!WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;
// rule RL_mmio_axi4_adapter_rl_handle_non_Ld_St
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St =
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd1 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd2 ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ;
// rule RL_mmioPlatform_propagateTime
assign CAN_FIRE_RL_mmioPlatform_propagateTime = mmioPlatform_state != 2'd0 ;
assign WILL_FIRE_RL_mmioPlatform_propagateTime =
CAN_FIRE_RL_mmioPlatform_propagateTime ;
// rule RL_mmioPlatform_incCycle
assign CAN_FIRE_RL_mmioPlatform_incCycle =
mmioPlatform_state != 2'd0 &&
mmioPlatform_cycle_10_ULT_99___d311 ;
assign WILL_FIRE_RL_mmioPlatform_incCycle =
CAN_FIRE_RL_mmioPlatform_incCycle ;
// rule RL_mmioPlatform_incTime
assign CAN_FIRE_RL_mmioPlatform_incTime =
mmioPlatform_state == 2'd1 &&
!mmioPlatform_cycle_10_ULT_99___d311 ;
assign WILL_FIRE_RL_mmioPlatform_incTime =
CAN_FIRE_RL_mmioPlatform_incTime ;
// rule RL_mmioPlatform_selectReq
assign CAN_FIRE_RL_mmioPlatform_selectReq =
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 ||
core_0$RDY_mmioToPlatform_pRq_enq) &&
NOT_mmioPlatform_mtip_0_18_25_AND_mmioPlatform_ETC___d333 &&
mmioPlatform_state == 2'd1 ;
assign WILL_FIRE_RL_mmioPlatform_selectReq =
CAN_FIRE_RL_mmioPlatform_selectReq &&
!WILL_FIRE_RL_mmioPlatform_incTime ;
// rule RL_mmioPlatform_waitTimerInterruptDone
assign CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone =
(!mmioPlatform_waitMTIPCRs ||
core_0$RDY_mmioToPlatform_cRs_deq) &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_curReq[66:64] == 3'd1 ;
assign WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone =
CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone ;
// rule RL_mmioPlatform_processMSIP
assign CAN_FIRE_RL_mmioPlatform_processMSIP =
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d416 &&
mmioPlatform_curReq[66:64] == 3'd2 &&
mmioPlatform_state == 2'd2 ;
assign WILL_FIRE_RL_mmioPlatform_processMSIP =
CAN_FIRE_RL_mmioPlatform_processMSIP ;
// rule RL_mmioPlatform_waitMSIPDone
assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone =
core_0$RDY_mmioToPlatform_pRs_enq &&
IF_mmioPlatform_waitLowerMSIPCRs_51_THEN_core__ETC___d459 &&
mmioPlatform_curReq[66:64] == 3'd2 &&
mmioPlatform_state == 2'd3 ;
assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone =
CAN_FIRE_RL_mmioPlatform_waitMSIPDone ;
// rule RL_mmioPlatform_processMTimeCmp
assign CAN_FIRE_RL_mmioPlatform_processMTimeCmp =
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 &&
mmioPlatform_curReq[66:64] == 3'd3 &&
mmioPlatform_state == 2'd2 ;
assign WILL_FIRE_RL_mmioPlatform_processMTimeCmp =
CAN_FIRE_RL_mmioPlatform_processMTimeCmp ;
// rule RL_mmioPlatform_waitMTimeCmpDone
assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone =
core_0$RDY_mmioToPlatform_cRs_deq &&
core_0$RDY_mmioToPlatform_pRs_enq &&
mmioPlatform_curReq[66:64] == 3'd3 &&
mmioPlatform_state == 2'd3 ;
assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone =
CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
// rule RL_mmioPlatform_processMTime
assign CAN_FIRE_RL_mmioPlatform_processMTime =
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_curReq[66:64] == 3'd4 ;
assign WILL_FIRE_RL_mmioPlatform_processMTime =
CAN_FIRE_RL_mmioPlatform_processMTime ;
// rule RL_mmioPlatform_waitMTimeDone
assign CAN_FIRE_RL_mmioPlatform_waitMTimeDone =
core_0$RDY_mmioToPlatform_pRs_enq &&
(!mmioPlatform_waitMTIPCRs ||
core_0$RDY_mmioToPlatform_cRs_deq) &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_curReq[66:64] == 3'd4 ;
assign WILL_FIRE_RL_mmioPlatform_waitMTimeDone =
CAN_FIRE_RL_mmioPlatform_waitMTimeDone ;
// rule RL_mmioPlatform_processToHost
assign CAN_FIRE_RL_mmioPlatform_processToHost =
core_0$RDY_mmioToPlatform_pRs_enq &&
(mmioPlatform_reqFunc[5:4] != 2'd2 ||
!mmioPlatform_toHostQ_empty ||
x__h41149 == 64'd0 ||
!mmioPlatform_toHostQ_full) &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_curReq[66:64] == 3'd5 ;
assign WILL_FIRE_RL_mmioPlatform_processToHost =
CAN_FIRE_RL_mmioPlatform_processToHost ;
// rule RL_mmioPlatform_processFromHost
assign CAN_FIRE_RL_mmioPlatform_processFromHost =
core_0$RDY_mmioToPlatform_pRs_enq &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_curReq[66:64] == 3'd6 ;
assign WILL_FIRE_RL_mmioPlatform_processFromHost =
CAN_FIRE_RL_mmioPlatform_processFromHost ;
// rule RL_mmioPlatform_rl_mmio_to_fabric_req
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req =
mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d705 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req =
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;
// rule RL_mmioPlatform_rl_mmio_from_fabric_rsp
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp =
core_0$RDY_mmioToPlatform_pRs_enq &&
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d713 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp =
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ;
// rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req =
mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d719 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req =
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ;
// rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp =
core_0$RDY_mmioToPlatform_pRs_enq &&
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
(!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ||
mmio_axi4_adapter_f_reqs_from_core$FULL_N) &&
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d729 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp =
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ;
// rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req =
mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d920 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req =
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ;
// rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp =
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
IF_mmio_axi4_adapter_f_rsps_to_core_first__15__ETC___d930 &&
NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d933 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp =
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ;
// rule RL_mmioPlatform_toHostQ_canonicalize
assign CAN_FIRE_RL_mmioPlatform_toHostQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_canonicalize = 1'd1 ;
// rule RL_mmioPlatform_toHostQ_enqReq_canon
assign CAN_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_toHostQ_deqReq_canon
assign CAN_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_toHostQ_clearReq_canon
assign CAN_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_canonicalize
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_canonicalize = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_enqReq_canon
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_deqReq_canon
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_clearReq_canon
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon = 1'd1 ;
// rule RL_propDstIdx_0_canon
assign CAN_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_canon
assign CAN_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
// rule RL_propDstData_0_canon
assign CAN_FIRE_RL_propDstData_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_0_canon = 1'd1 ;
// rule RL_propDstData_1_canon
assign CAN_FIRE_RL_propDstData_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_canon = 1'd1 ;
// rule RL_enqDst_0_canon
assign CAN_FIRE_RL_enqDst_0_canon = 1'd1 ;
assign WILL_FIRE_RL_enqDst_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_0_canon
assign CAN_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_1_canon
assign CAN_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
// rule RL_propDstData_1_0_canon
assign CAN_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
// rule RL_propDstData_1_1_canon
assign CAN_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
// rule RL_enqDst_1_0_canon
assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
// rule RL_propDstIdx_0_canon_1
assign CAN_FIRE_RL_propDstIdx_0_canon_1 = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_0_canon_1 = 1'd1 ;
// rule RL_propDstData_0_canon_1
assign CAN_FIRE_RL_propDstData_0_canon_1 = 1'd1 ;
assign WILL_FIRE_RL_propDstData_0_canon_1 = 1'd1 ;
// rule RL_enqDst_0_canon_1
assign CAN_FIRE_RL_enqDst_0_canon_1 = 1'd1 ;
assign WILL_FIRE_RL_enqDst_0_canon_1 = 1'd1 ;
// rule RL_llc_axi4_adapter_rl_handle_read_rsps
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
llc_axi4_adapter_master_xactor_crg_rd_data_full &&
(llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 ||
llc$RDY_to_mem_rsFromM_enq &&
llc_axi4_adapter_f_pending_reads$EMPTY_N) ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// rule RL_llc_axi4_adapter_rl_handle_write_req
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
!llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read &&
!llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read &&
llc$RDY_to_mem_toM_first &&
(llc_axi4_adapter_rg_wr_req_beat != 3'd0 ||
llc_axi4_adapter_f_pending_writes$FULL_N) &&
(llc_axi4_adapter_rg_wr_req_beat != 3'd7 ||
llc$RDY_to_mem_toM_deq) &&
llc$to_mem_toM_first[640] ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// rule RL_llc_axi4_adapter_rl_handle_read_req
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
!llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read &&
llc$RDY_to_mem_toM_first &&
(llc_axi4_adapter_rg_rd_req_beat != 3'd0 ||
llc_axi4_adapter_f_pending_reads$FULL_N) &&
(llc_axi4_adapter_rg_rd_req_beat != 3'd7 ||
llc$RDY_to_mem_toM_deq) &&
!llc$to_mem_toM_first[640] &&
b__h111153 == 4'd0 ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
// rule RL_llc_axi4_adapter_rl_discard_write_rsp
assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
b__h111153 != 4'd0 &&
llc_axi4_adapter_master_xactor_crg_wr_resp_full &&
(llc_axi4_adapter_rg_wr_rsp_beat != 3'd7 ||
llc_axi4_adapter_f_pending_writes$EMPTY_N) ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
!mmioPlatform_reqBE[4] &&
mmioPlatform_reqBE[0] ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d544 ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 =
WILL_FIRE_RL_mmioPlatform_processMTime &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d607 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d426 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d530 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 =
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d595 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
(!mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ||
!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 =
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
assign MUX_mmioPlatform_amoResp$write_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ;
assign MUX_mmioPlatform_amoResp$write_1__SEL_2 =
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ;
assign MUX_mmioPlatform_curReq$write_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 ||
core_0$mmioToPlatform_cRq_notEmpty) ;
assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320) &&
core_0$mmioToPlatform_cRq_notEmpty ;
assign MUX_mmioPlatform_state$write_1__SEL_6 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
WILL_FIRE_RL_mmioPlatform_processFromHost ||
WILL_FIRE_RL_mmioPlatform_processToHost ||
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone ||
EN_start ;
assign MUX_mmioPlatform_state$write_1__SEL_7 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ;
assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 =
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] == 2'b0 ;
assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 =
{ 1'd1,
llc$to_child_toC_first[582:517],
llc$to_child_toC_first[515:0] } ;
assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 =
{ 1'd0, llc$to_child_toC_first[582:1] } ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 =
{ 1'd0,
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d440,
(mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
mmioPlatform_reqData[31:0] :
x_data__h28822 } ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 =
{ 7'd106,
(IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
!mmioPlatform_mtip_0) ?
32'd1 :
32'd0 } ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 =
{ 7'd106,
(mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
!mmioPlatform_mtip_0) ?
32'd1 :
32'd0 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1 =
{ mmioPlatform_reqFunc[5:4] != 2'd0,
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
66'h155555554AAAAAAAA :
66'h0AAAAAAAAAAAAAAAA } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2 =
{ mmioPlatform_reqFunc[5:4] != 2'd0,
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
66'h155555554AAAAAAAA :
{ 2'h1,
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_1_ETC___d537 } } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 =
{ mmioPlatform_reqFunc[5:4] != 2'd0,
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
66'h155555554AAAAAAAA :
{ 2'h1,
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_1_ETC___d601 } } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 =
{ !mmio_axi4_adapter_f_rsps_to_core$D_OUT[64],
IF_mmio_axi4_adapter_f_rsps_to_core_first__15__ETC___d947 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 =
{ 3'd5, mmioPlatform_amoResp } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 = { 3'd5, data__h30239 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 =
{ mmioPlatform_reqFunc[5:4] != 2'd0,
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
66'h155555554AAAAAAAA :
DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_99_BIT_ETC___d643 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 =
{ mmioPlatform_reqFunc[5:4] != 2'd0,
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
66'h155555554AAAAAAAA :
{ 1'h0,
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_2_ETC___d682 } } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 =
{ 2'd2, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 =
{ 2'd2,
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
{ 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] } :
mmio_axi4_adapter_f_rsps_to_core$D_OUT } ;
assign MUX_mmioPlatform_amoResp$write_1__VAL_1 =
(mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtimecmp_0 :
IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d536 ;
assign MUX_mmioPlatform_amoResp$write_1__VAL_2 =
(mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtime :
IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d600 ;
assign MUX_mmioPlatform_curReq$write_1__VAL_1 =
(!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320) ?
67'h1AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33554432 &&
core_0$mmioToPlatform_cRq_first[141:81] < 61'd33554433) ?
67'h2AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[141:81] >= 61'd33556480 &&
core_0$mmioToPlatform_cRq_first[141:81] < 61'd33556481) ?
67'h3AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[141:81] ==
61'd33560575) ?
67'h4AAAAAAAAAAAAAAAA :
IF_core_0_mmioToPlatform_cRq_first__41_BITS_14_ETC___d364))) ;
assign MUX_mmioPlatform_curReq$write_1__VAL_2 =
{ 3'd7,
mmioPlatform_instSel ?
mmioPlatform_curReq[63:0] + 64'd8 :
mmioPlatform_curReq[63:0] } ;
assign MUX_mmioPlatform_cycle$write_1__VAL_1 = mmioPlatform_cycle + 7'd1 ;
assign MUX_mmioPlatform_fetchingWay$write_1__VAL_2 =
mmioPlatform_fetchingWay + 1'd1 ;
assign MUX_mmioPlatform_instSel$write_1__VAL_2 =
mmioPlatform_instSel + 1'd1 ;
assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ;
assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 =
IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
!mmioPlatform_mtip_0 ;
assign MUX_mmioPlatform_state$write_1__VAL_1 =
(!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320) ?
2'd3 :
2'd2 ;
assign MUX_mmioPlatform_state$write_1__VAL_2 =
(mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ?
2'd1 :
((mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
(mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) :
2'd3) ;
always@(mmioPlatform_reqFunc or
IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 or
mmioPlatform_mtip_0)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1;
2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4];
default: MUX_mmioPlatform_state$write_1__VAL_3 =
(IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
!mmioPlatform_mtip_0 ||
!IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
mmioPlatform_mtip_0) ?
2'd3 :
2'd1;
endcase
end
always@(mmioPlatform_reqFunc or
mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 or
mmioPlatform_mtip_0)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1;
2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4];
default: MUX_mmioPlatform_state$write_1__VAL_4 =
(mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
mmioPlatform_mtip_0) ?
2'd3 :
2'd1;
endcase
end
assign MUX_mmioPlatform_state$write_1__VAL_5 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
(mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ?
2'd2 :
2'd1) :
2'd1 ;
assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 =
mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
mmioPlatform_mtip_0 ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 =
{ mmioPlatform_curReq[63:0],
6'd42,
mmioPlatform_reqBE,
x__h46145 } ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 =
{ mmioPlatform_curReq[63:0],
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d440,
mmioPlatform_reqBE,
mmioPlatform_reqData } ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 =
{ mmioPlatform_curReq[63:0], 78'h1AAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 =
{ x__h48257, 78'h1AAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 =
{ 1'd1, mmio_axi4_adapter_master_xactor_rg_rd_data[66:3] } ;
// inlined wires
assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h41149 } ;
assign mmioPlatform_toHostQ_enqReq_lat_0$whas =
WILL_FIRE_RL_mmioPlatform_processToHost &&
mmioPlatform_reqFunc[5:4] == 2'd2 &&
mmioPlatform_toHostQ_empty &&
x__h41149 != 64'd0 ;
assign mmioPlatform_fromHostQ_deqReq_lat_0$whas =
WILL_FIRE_RL_mmioPlatform_processFromHost &&
mmioPlatform_reqFunc[5:4] == 2'd2 &&
!mmioPlatform_fromHostQ_empty &&
x__h39129 == 64'd0 ;
assign propDstIdx_0_lat_1$whas =
NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 &&
IF_SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_ETC___d1120 ;
assign propDstIdx_1_lat_1$whas =
NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 &&
x__h59168 ;
assign propDstData_0_lat_0$wget =
{ core_0$dCacheToParent_rqToP_first, 1'd0 } ;
assign propDstData_1_lat_0$wget =
{ core_0$iCacheToParent_rqToP_first, 1'd1 } ;
assign enqDst_0_lat_0$wget =
{ 1'd1,
CASE_x9168_0_n__read_addr9350_1_n__read_addr94_ETC__q15,
SEL_ARR_IF_propDstData_0_dummy2_1_read__051_TH_ETC___d1115 } ;
assign propDstIdx_1_0_lat_1$whas =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 &&
IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_A_ETC___d1417 ;
assign propDstIdx_1_1_lat_1$whas =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 &&
x__h77791 ;
assign propDstData_1_0_lat_0$wget =
{ core_0$dCacheToParent_rsToP_first, 1'd0 } ;
assign propDstData_1_1_lat_0$wget =
{ core_0$iCacheToParent_rsToP_first, 1'd1 } ;
assign enqDst_1_0_lat_0$wget =
{ 1'd1,
CASE_x7791_0_n__read_addr7969_1_n__read_addr80_ETC__q26,
SEL_ARR_IF_propDstData_1_0_dummy2_1_read__320__ETC___d1412 } ;
assign enqDst_0_lat_0_1$wget =
{ 1'd1, n__read_snd_addr__h92140, n__read_snd_id__h92141 } ;
assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write =
mmio_axi4_adapter_master_xactor_crg_wr_addr_full &&
master1_awready ;
assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read =
!mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write &&
mmio_axi4_adapter_master_xactor_crg_wr_addr_full ;
assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ;
assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write =
mmio_axi4_adapter_master_xactor_crg_wr_data_full &&
master1_wready ;
assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read =
!mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write &&
mmio_axi4_adapter_master_xactor_crg_wr_data_full ;
assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
mmio_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ;
assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read =
!WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_crg_wr_resp_full ;
assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write =
master1_bvalid &&
!mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read =
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write ||
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write =
mmio_axi4_adapter_master_xactor_crg_rd_addr_full &&
master1_arready ;
assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read =
!mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write &&
mmio_axi4_adapter_master_xactor_crg_rd_addr_full ;
assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ||
mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ;
assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read =
!CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_crg_rd_data_full ;
assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write =
master1_rvalid &&
!mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read =
mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write ||
mmio_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
b__h3158 - 4'd1 ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ?
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
b__h3158 ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read =
CAN_FIRE_RL_rl_reset ?
4'd0 :
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write =
llc_axi4_adapter_master_xactor_crg_wr_addr_full &&
master0_awready ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read =
!llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN_port1__write &&
llc_axi4_adapter_master_xactor_crg_wr_addr_full ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write =
llc_axi4_adapter_master_xactor_crg_wr_data_full &&
master0_wready ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read =
!llc_axi4_adapter_master_xactor_crg_wr_data_full$EN_port1__write &&
llc_axi4_adapter_master_xactor_crg_wr_data_full ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ||
llc_axi4_adapter_master_xactor_crg_wr_data_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read =
!CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_crg_wr_resp_full ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write =
master0_bvalid &&
!llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read =
llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN_port2__write ||
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write =
llc_axi4_adapter_master_xactor_crg_rd_addr_full &&
master0_arready ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read =
!llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN_port1__write &&
llc_axi4_adapter_master_xactor_crg_rd_addr_full ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ||
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read =
!CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_crg_rd_data_full ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write =
master0_rvalid &&
!llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read =
llc_axi4_adapter_master_xactor_crg_rd_data_full$EN_port2__write ||
llc_axi4_adapter_master_xactor_crg_rd_data_full$port2__read ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
b__h111153 - 4'd1 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ?
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
b__h111153 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read =
CAN_FIRE_RL_rl_reset ?
4'd0 :
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
// register cfg_verbosity
assign cfg_verbosity$D_IN =
EN_hart0_put_other_req_put ?
hart0_put_other_req_put :
set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_hart0_put_other_req_put || EN_set_verbosity ;
// register enqDst_0_rl
assign enqDst_0_rl$D_IN =
{ !CAN_FIRE_RL_doEnq &&
IF_enqDst_0_lat_0_whas__89_THEN_enqDst_0_lat_0_ETC___d994,
CAN_FIRE_RL_doEnq ?
73'h0AAAAAAAAAAAAAAAAAA :
(NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 ?
enqDst_0_lat_0$wget[72:0] :
enqDst_0_rl[72:0]) } ;
assign enqDst_0_rl$EN = 1'd1 ;
// register enqDst_0_rl_1
assign enqDst_0_rl_1$D_IN =
{ !CAN_FIRE_RL_doEnq_2 &&
IF_enqDst_0_lat_0_1_whas__476_THEN_enqDst_0_la_ETC___d1481,
CAN_FIRE_RL_doEnq_2 ?
65'h0AAAAAAAAAAAAAAAA :
(NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514 ?
enqDst_0_lat_0_1$wget[64:0] :
enqDst_0_rl_1[64:0]) } ;
assign enqDst_0_rl_1$EN = 1'd1 ;
// register enqDst_1_0_rl
assign enqDst_1_0_rl$D_IN =
{ !CAN_FIRE_RL_doEnq_1 &&
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1225,
IF_enqDst_1_0_lat_1_whas__217_THEN_enqDst_1_0__ETC___d1264 } ;
assign enqDst_1_0_rl$EN = 1'd1 ;
// register llc_axi4_adapter_cfg_verbosity
assign llc_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ;
assign llc_axi4_adapter_cfg_verbosity$EN = 1'b0 ;
// register llc_axi4_adapter_ctr_wr_rsps_pending_crg
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_rd_addr_full
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN =
llc_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_rd_data_full
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN =
llc_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_wr_addr_full
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN =
llc_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_wr_data_full
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN =
llc_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_crg_wr_resp_full
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN =
llc_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ;
assign llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_rg_rd_addr
assign llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN =
{ 4'd0, mem_req_rd_addr_araddr__h111446, 29'd851968 } ;
assign llc_axi4_adapter_master_xactor_rg_rd_addr$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
// register llc_axi4_adapter_master_xactor_rg_rd_data
assign llc_axi4_adapter_master_xactor_rg_rd_data$D_IN =
{ master0_rid, master0_rdata, master0_rresp, master0_rlast } ;
assign llc_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ;
// register llc_axi4_adapter_master_xactor_rg_wr_addr
assign llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN =
{ 4'd0, mem_req_wr_addr_awaddr__h125370, 29'd851968 } ;
assign llc_axi4_adapter_master_xactor_rg_wr_addr$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// register llc_axi4_adapter_master_xactor_rg_wr_data
assign llc_axi4_adapter_master_xactor_rg_wr_data$D_IN =
{ 4'd0, data64__h125285, strb8__h125286, 1'd1 } ;
assign llc_axi4_adapter_master_xactor_rg_wr_data$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// register llc_axi4_adapter_master_xactor_rg_wr_resp
assign llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN =
{ master0_bid, master0_bresp } ;
assign llc_axi4_adapter_master_xactor_rg_wr_resp$EN =
master0_bvalid &&
!llc_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
// register llc_axi4_adapter_rg_cline
assign llc_axi4_adapter_rg_cline$D_IN = new_cline__h112148 ;
assign llc_axi4_adapter_rg_cline$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// register llc_axi4_adapter_rg_rd_req_beat
assign llc_axi4_adapter_rg_rd_req_beat$D_IN =
llc_axi4_adapter_rg_rd_req_beat + 3'd1 ;
assign llc_axi4_adapter_rg_rd_req_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
// register llc_axi4_adapter_rg_rd_rsp_beat
assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN =
llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ;
assign llc_axi4_adapter_rg_rd_rsp_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// register llc_axi4_adapter_rg_wr_req_beat
assign llc_axi4_adapter_rg_wr_req_beat$D_IN =
llc_axi4_adapter_rg_wr_req_beat + 3'd1 ;
assign llc_axi4_adapter_rg_wr_req_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// register llc_axi4_adapter_rg_wr_rsp_beat
assign llc_axi4_adapter_rg_wr_rsp_beat$D_IN =
llc_axi4_adapter_rg_wr_rsp_beat + 3'd1 ;
assign llc_axi4_adapter_rg_wr_rsp_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;
// register mmioPlatform_amoResp
assign mmioPlatform_amoResp$D_IN =
MUX_mmioPlatform_amoResp$write_1__SEL_1 ?
MUX_mmioPlatform_amoResp$write_1__VAL_1 :
MUX_mmioPlatform_amoResp$write_1__VAL_2 ;
assign mmioPlatform_amoResp$EN =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ;
// register mmioPlatform_curReq
assign mmioPlatform_curReq$D_IN =
MUX_mmioPlatform_curReq$write_1__SEL_1 ?
MUX_mmioPlatform_curReq$write_1__VAL_1 :
MUX_mmioPlatform_curReq$write_1__VAL_2 ;
assign mmioPlatform_curReq$EN =
MUX_mmioPlatform_curReq$write_1__SEL_1 ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ;
// register mmioPlatform_cycle
assign mmioPlatform_cycle$D_IN =
WILL_FIRE_RL_mmioPlatform_incCycle ?
MUX_mmioPlatform_cycle$write_1__VAL_1 :
7'd0 ;
assign mmioPlatform_cycle$EN =
WILL_FIRE_RL_mmioPlatform_incCycle ||
WILL_FIRE_RL_mmioPlatform_incTime ;
// register mmioPlatform_fetchedInsts_0
assign mmioPlatform_fetchedInsts_0$D_IN =
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d942 ;
assign mmioPlatform_fetchedInsts_0$EN =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 &&
!mmioPlatform_fetchingWay ;
// register mmioPlatform_fetchingWay
assign mmioPlatform_fetchingWay$D_IN =
!MUX_mmioPlatform_fetchingWay$write_1__SEL_1 &&
MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ;
assign mmioPlatform_fetchingWay$EN =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320) &&
core_0$mmioToPlatform_cRq_notEmpty ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ;
// register mmioPlatform_fromHostAddr
assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ;
assign mmioPlatform_fromHostAddr$EN = EN_start ;
// register mmioPlatform_fromHostQ_clearReq_rl
assign mmioPlatform_fromHostQ_clearReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_fromHostQ_clearReq_rl$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_data_0
assign mmioPlatform_fromHostQ_data_0$D_IN =
mmioPlatform_fromHostQ_enqReq_rl[63:0] ;
assign mmioPlatform_fromHostQ_data_0$EN =
NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d281 &&
mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT &&
mmioPlatform_fromHostQ_enqReq_rl[64] ;
// register mmioPlatform_fromHostQ_deqReq_rl
assign mmioPlatform_fromHostQ_deqReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_fromHostQ_deqReq_rl$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_empty
assign mmioPlatform_fromHostQ_empty$D_IN =
mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT &&
mmioPlatform_fromHostQ_clearReq_rl ||
NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d302 ;
assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_enqReq_rl
assign mmioPlatform_fromHostQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign mmioPlatform_fromHostQ_enqReq_rl$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_full
assign mmioPlatform_fromHostQ_full$D_IN =
NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d281 &&
mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d294 ;
assign mmioPlatform_fromHostQ_full$EN = 1'd1 ;
// register mmioPlatform_instSel
assign mmioPlatform_instSel$D_IN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ?
core_0$mmioToPlatform_cRq_first[80] :
MUX_mmioPlatform_instSel$write_1__VAL_2 ;
assign mmioPlatform_instSel$EN =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320) &&
core_0$mmioToPlatform_cRq_notEmpty ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] &&
mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ;
// register mmioPlatform_mtime
assign mmioPlatform_mtime$D_IN =
MUX_mmioPlatform_amoResp$write_1__SEL_2 ?
newData__h33250 :
MUX_mmioPlatform_mtime$write_1__VAL_2 ;
assign mmioPlatform_mtime$EN =
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ||
WILL_FIRE_RL_mmioPlatform_incTime ;
// register mmioPlatform_mtimecmp_0
assign mmioPlatform_mtimecmp_0$D_IN = newData__h30320 ;
assign mmioPlatform_mtimecmp_0$EN =
MUX_mmioPlatform_amoResp$write_1__SEL_1 ;
// register mmioPlatform_mtip_0
assign mmioPlatform_mtip_0$D_IN =
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 ||
MUX_mmioPlatform_mtip_0$write_1__VAL_2 ;
assign mmioPlatform_mtip_0$EN =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d544 ;
// register mmioPlatform_reqAmofunc
assign mmioPlatform_reqAmofunc$D_IN =
(core_0$mmioToPlatform_cRq_first[77:76] != 2'd0 &&
core_0$mmioToPlatform_cRq_first[77:76] != 2'd1 &&
core_0$mmioToPlatform_cRq_first[77:76] != 2'd2) ?
core_0$mmioToPlatform_cRq_first[75:72] :
4'd9 ;
assign mmioPlatform_reqAmofunc$EN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqBE
assign mmioPlatform_reqBE$D_IN = core_0$mmioToPlatform_cRq_first[71:64] ;
assign mmioPlatform_reqBE$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqData
assign mmioPlatform_reqData$D_IN = core_0$mmioToPlatform_cRq_first[63:0] ;
assign mmioPlatform_reqData$EN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqFunc
always@(core_0$mmioToPlatform_cRq_first)
begin
case (core_0$mmioToPlatform_cRq_first[77:76])
2'd0, 2'd1, 2'd2:
mmioPlatform_reqFunc$D_IN = core_0$mmioToPlatform_cRq_first[77:72];
2'd3:
mmioPlatform_reqFunc$D_IN =
{ 2'd3, core_0$mmioToPlatform_cRq_first[75:72] };
endcase
end
assign mmioPlatform_reqFunc$EN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqSz
assign mmioPlatform_reqSz$D_IN = 2'b11 ;
assign mmioPlatform_reqSz$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_state
always@(MUX_mmioPlatform_curReq$write_1__SEL_1 or
MUX_mmioPlatform_state$write_1__VAL_1 or
WILL_FIRE_RL_mmioPlatform_processMSIP or
MUX_mmioPlatform_state$write_1__VAL_2 or
WILL_FIRE_RL_mmioPlatform_processMTimeCmp or
MUX_mmioPlatform_state$write_1__VAL_3 or
WILL_FIRE_RL_mmioPlatform_processMTime or
MUX_mmioPlatform_state$write_1__VAL_4 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp or
MUX_mmioPlatform_state$write_1__VAL_5 or
MUX_mmioPlatform_state$write_1__SEL_6 or
MUX_mmioPlatform_state$write_1__SEL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_mmioPlatform_curReq$write_1__SEL_1:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_1;
WILL_FIRE_RL_mmioPlatform_processMSIP:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_2;
WILL_FIRE_RL_mmioPlatform_processMTimeCmp:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_3;
WILL_FIRE_RL_mmioPlatform_processMTime:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_4;
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_5;
MUX_mmioPlatform_state$write_1__SEL_6: mmioPlatform_state$D_IN = 2'd1;
MUX_mmioPlatform_state$write_1__SEL_7: mmioPlatform_state$D_IN = 2'd3;
default: mmioPlatform_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign mmioPlatform_state$EN =
MUX_mmioPlatform_curReq$write_1__SEL_1 ||
WILL_FIRE_RL_mmioPlatform_processMSIP ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp ||
WILL_FIRE_RL_mmioPlatform_processMTime ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
WILL_FIRE_RL_mmioPlatform_processFromHost ||
WILL_FIRE_RL_mmioPlatform_processToHost ||
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone ||
EN_start ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;
// register mmioPlatform_toHostAddr
assign mmioPlatform_toHostAddr$D_IN = start_tohostAddr[63:3] ;
assign mmioPlatform_toHostAddr$EN = EN_start ;
// register mmioPlatform_toHostQ_clearReq_rl
assign mmioPlatform_toHostQ_clearReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_toHostQ_clearReq_rl$EN = 1'd1 ;
// register mmioPlatform_toHostQ_data_0
assign mmioPlatform_toHostQ_data_0$D_IN =
mmioPlatform_toHostQ_enqReq_lat_0$whas ?
mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] :
mmioPlatform_toHostQ_enqReq_rl[63:0] ;
assign mmioPlatform_toHostQ_data_0$EN =
NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d203 &&
mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT &&
IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__54__ETC___d163 ;
// register mmioPlatform_toHostQ_deqReq_rl
assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_toHostQ_deqReq_rl$EN = 1'd1 ;
// register mmioPlatform_toHostQ_empty
assign mmioPlatform_toHostQ_empty$D_IN =
mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT &&
mmioPlatform_toHostQ_clearReq_rl ||
NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d224 ;
assign mmioPlatform_toHostQ_empty$EN = 1'd1 ;
// register mmioPlatform_toHostQ_enqReq_rl
assign mmioPlatform_toHostQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign mmioPlatform_toHostQ_enqReq_rl$EN = 1'd1 ;
// register mmioPlatform_toHostQ_full
assign mmioPlatform_toHostQ_full$D_IN =
NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d203 &&
mmioPlatform_toHostQ_enqReq_dummy2_2_read__04__ETC___d216 ;
assign mmioPlatform_toHostQ_full$EN = 1'd1 ;
// register mmioPlatform_waitLowerMSIPCRs
assign mmioPlatform_waitLowerMSIPCRs$D_IN =
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 ||
mmioPlatform_reqBE[0] ;
assign mmioPlatform_waitLowerMSIPCRs$EN =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d449 ;
// register mmioPlatform_waitMTIPCRs
assign mmioPlatform_waitMTIPCRs$D_IN =
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 ||
MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ;
assign mmioPlatform_waitMTIPCRs$EN =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d607 ;
// register mmioPlatform_waitUpperMSIPCRs
assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ;
assign mmioPlatform_waitUpperMSIPCRs$EN =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d449 ;
// register mmio_axi4_adapter_cfg_verbosity
assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ;
assign mmio_axi4_adapter_cfg_verbosity$EN = 1'b0 ;
// register mmio_axi4_adapter_ctr_wr_rsps_pending_crg
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port3__read ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_crg_rd_addr_full
assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN =
mmio_axi4_adapter_master_xactor_crg_rd_addr_full$port3__read ;
assign mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_crg_rd_data_full
assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN =
mmio_axi4_adapter_master_xactor_crg_rd_data_full$port3__read ;
assign mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_crg_wr_addr_full
assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN =
mmio_axi4_adapter_master_xactor_crg_wr_addr_full$port3__read ;
assign mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_crg_wr_data_full
assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN =
mmio_axi4_adapter_master_xactor_crg_wr_data_full$port3__read ;
assign mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_crg_wr_resp_full
assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN =
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port3__read ;
assign mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_rg_rd_addr
assign mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN =
{ 4'd0,
mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78],
29'd851968 } ;
assign mmio_axi4_adapter_master_xactor_rg_rd_addr$EN =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
// register mmio_axi4_adapter_master_xactor_rg_rd_data
assign mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN =
{ master1_rid, master1_rdata, master1_rresp, master1_rlast } ;
assign mmio_axi4_adapter_master_xactor_rg_rd_data$EN = 1'd1 ;
// register mmio_axi4_adapter_master_xactor_rg_wr_addr
assign mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN =
{ 4'd0,
mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78],
29'd851968 } ;
assign mmio_axi4_adapter_master_xactor_rg_wr_addr$EN =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ;
// register mmio_axi4_adapter_master_xactor_rg_wr_data
assign mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN =
{ 4'd0,
mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0],
mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64],
1'd1 } ;
assign mmio_axi4_adapter_master_xactor_rg_wr_data$EN =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ;
// register mmio_axi4_adapter_master_xactor_rg_wr_resp
assign mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN =
{ master1_bid, master1_bresp } ;
assign mmio_axi4_adapter_master_xactor_rg_wr_resp$EN =
master1_bvalid &&
!mmio_axi4_adapter_master_xactor_crg_wr_resp_full$port2__read ;
// register propDstData_0_rl
assign propDstData_0_rl$D_IN =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget :
propDstData_0_rl ;
assign propDstData_0_rl$EN = 1'd1 ;
// register propDstData_0_rl_1
assign propDstData_0_rl_1$D_IN =
CAN_FIRE_RL_srcPropose_4 ?
core_0$tlbToMem_memReq_first :
propDstData_0_rl_1 ;
assign propDstData_0_rl_1$EN = 1'd1 ;
// register propDstData_1_0_rl
assign propDstData_1_0_rl$D_IN =
{ IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1149,
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1154,
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[513] :
propDstData_1_0_rl[513],
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[512:1] :
propDstData_1_0_rl[512:1],
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1175 } ;
assign propDstData_1_0_rl$EN = 1'd1 ;
// register propDstData_1_1_rl
assign propDstData_1_1_rl$D_IN =
{ IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1187,
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1192,
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[513] :
propDstData_1_1_rl[513],
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[512:1] :
propDstData_1_1_rl[512:1],
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1213 } ;
assign propDstData_1_1_rl$EN = 1'd1 ;
// register propDstData_1_rl
assign propDstData_1_rl$D_IN =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget :
propDstData_1_rl ;
assign propDstData_1_rl$EN = 1'd1 ;
// register propDstIdx_0_rl
assign propDstIdx_0_rl$D_IN =
!propDstIdx_0_lat_1$whas &&
IF_propDstIdx_0_lat_0_whas__60_THEN_propDstIdx_ETC___d963 ;
assign propDstIdx_0_rl$EN = 1'd1 ;
// register propDstIdx_0_rl_1
assign propDstIdx_0_rl_1$D_IN =
!NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514 &&
IF_propDstIdx_0_lat_0_1_whas__461_THEN_propDst_ETC___d1464 ;
assign propDstIdx_0_rl_1$EN = 1'd1 ;
// register propDstIdx_1_0_rl
assign propDstIdx_1_0_rl$D_IN =
!propDstIdx_1_0_lat_1$whas &&
IF_propDstIdx_1_0_lat_0_whas__129_THEN_propDst_ETC___d1132 ;
assign propDstIdx_1_0_rl$EN = 1'd1 ;
// register propDstIdx_1_1_rl
assign propDstIdx_1_1_rl$D_IN =
!propDstIdx_1_1_lat_1$whas &&
IF_propDstIdx_1_1_lat_0_whas__136_THEN_propDst_ETC___d1139 ;
assign propDstIdx_1_1_rl$EN = 1'd1 ;
// register propDstIdx_1_rl
assign propDstIdx_1_rl$D_IN =
!propDstIdx_1_lat_1$whas &&
IF_propDstIdx_1_lat_0_whas__67_THEN_propDstIdx_ETC___d970 ;
assign propDstIdx_1_rl$EN = 1'd1 ;
// register rg_step_count
assign rg_step_count$D_IN = 1'b0 ;
assign rg_step_count$EN = 1'b0 ;
// register rg_stop_req
assign rg_stop_req$D_IN = 1'b0 ;
assign rg_stop_req$EN = 1'b0 ;
// register srcRR_0
assign srcRR_0$D_IN = srcRR_0 + 1'd1 ;
assign srcRR_0$EN =
NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 ;
// register srcRR_1_0
assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ;
assign srcRR_1_0$EN =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ;
// submodule core_0
assign core_0$coreReq_perfReq_loc = 4'h0 ;
assign core_0$coreReq_perfReq_t = 5'h0 ;
assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ;
assign core_0$coreReq_start_startpc = start_startpc ;
assign core_0$coreReq_start_toHostAddr = start_tohostAddr ;
assign core_0$dCacheToParent_fromP_enq_x =
WILL_FIRE_RL_sendPRs ?
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 :
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ;
assign core_0$iCacheToParent_fromP_enq_x =
WILL_FIRE_RL_sendPRs_1 ?
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 :
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ;
always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 or
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 or
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 or
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 or
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 or
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1:
core_0$mmioToPlatform_pRq_enq_x = 39'h6A00000001;
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2:
core_0$mmioToPlatform_pRq_enq_x =
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2;
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3:
core_0$mmioToPlatform_pRq_enq_x =
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3;
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4:
core_0$mmioToPlatform_pRq_enq_x =
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4;
default: core_0$mmioToPlatform_pRq_enq_x =
39'h2AAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or
WILL_FIRE_RL_mmioPlatform_waitMSIPDone or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or
WILL_FIRE_RL_mmioPlatform_processToHost or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or
WILL_FIRE_RL_mmioPlatform_processFromHost or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10)
begin
case (1'b1) // synopsys parallel_case
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5;
WILL_FIRE_RL_mmioPlatform_waitMSIPDone:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6;
WILL_FIRE_RL_mmioPlatform_processToHost:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7;
WILL_FIRE_RL_mmioPlatform_processFromHost:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8;
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9;
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10;
default: core_0$mmioToPlatform_pRs_enq_x =
67'h2AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign core_0$mmioToPlatform_setTime_t = mmioPlatform_mtime ;
assign core_0$recvDoStats_x = core_0$sendDoStats ;
assign core_0$setDEIP_v = debug_external_interrupt_req_set_not_clear ;
assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ;
assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ;
assign core_0$tlbToMem_respLd_enq_x =
{ ld_data__h109019, llc$dma_respLd_first[3] } ;
assign core_0$EN_coreReq_start = EN_start ;
assign core_0$EN_coreReq_perfReq = 1'b0 ;
assign core_0$EN_coreIndInv_perfResp = 1'b0 ;
assign core_0$EN_coreIndInv_terminate = core_0$RDY_coreIndInv_terminate ;
assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ;
assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ;
assign core_0$EN_dCacheToParent_fromP_enq =
WILL_FIRE_RL_sendPRs || WILL_FIRE_RL_sendPRq ;
assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ;
assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ;
assign core_0$EN_iCacheToParent_fromP_enq =
WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ;
assign core_0$EN_tlbToMem_memReq_deq = CAN_FIRE_RL_srcPropose_4 ;
assign core_0$EN_tlbToMem_respLd_enq = CAN_FIRE_RL_sendLdRespToTlb ;
assign core_0$EN_mmioToPlatform_cRq_deq =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
assign core_0$EN_mmioToPlatform_pRs_enq =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d426 ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d530 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d595 ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
(!mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 ||
!mmio_axi4_adapter_f_rsps_to_core$D_OUT[64]) ||
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
WILL_FIRE_RL_mmioPlatform_processToHost ||
WILL_FIRE_RL_mmioPlatform_processFromHost ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ;
assign core_0$EN_mmioToPlatform_pRq_enq =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 ||
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
!mmioPlatform_reqBE[4] &&
mmioPlatform_reqBE[0] ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d544 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d607 ;
assign core_0$EN_mmioToPlatform_cRs_deq =
(WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) &&
mmioPlatform_waitMTIPCRs ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone &&
(mmioPlatform_waitLowerMSIPCRs ||
mmioPlatform_waitUpperMSIPCRs) ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
assign core_0$EN_mmioToPlatform_setTime =
CAN_FIRE_RL_mmioPlatform_propagateTime ;
assign core_0$EN_sendDoStats = core_0$RDY_sendDoStats ;
assign core_0$EN_recvDoStats = core_0$RDY_sendDoStats ;
assign core_0$EN_deadlock_dCacheCRqStuck_get =
core_0$RDY_deadlock_dCacheCRqStuck_get ;
assign core_0$EN_deadlock_dCachePRqStuck_get =
core_0$RDY_deadlock_dCachePRqStuck_get ;
assign core_0$EN_deadlock_iCacheCRqStuck_get =
core_0$RDY_deadlock_iCacheCRqStuck_get ;
assign core_0$EN_deadlock_iCachePRqStuck_get =
core_0$RDY_deadlock_iCachePRqStuck_get ;
assign core_0$EN_deadlock_renameInstStuck_get =
core_0$RDY_deadlock_renameInstStuck_get ;
assign core_0$EN_deadlock_renameCorrectPathStuck_get =
core_0$RDY_deadlock_renameCorrectPathStuck_get ;
assign core_0$EN_deadlock_commitInstStuck_get =
core_0$RDY_deadlock_commitInstStuck_get ;
assign core_0$EN_deadlock_commitUserInstStuck_get =
core_0$RDY_deadlock_commitUserInstStuck_get ;
assign core_0$EN_deadlock_checkStarted_get =
core_0$RDY_deadlock_checkStarted_get ;
assign core_0$EN_renameDebug_renameErr_get =
core_0$RDY_renameDebug_renameErr_get ;
assign core_0$EN_setMEIP = 1'd1 ;
assign core_0$EN_setSEIP = 1'd1 ;
assign core_0$EN_setDEIP = 1'd1 ;
// submodule enqDst_0_dummy2_0
assign enqDst_0_dummy2_0$D_IN = 1'd1 ;
assign enqDst_0_dummy2_0$EN =
NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 ;
// submodule enqDst_0_dummy2_0_1
assign enqDst_0_dummy2_0_1$D_IN = 1'd1 ;
assign enqDst_0_dummy2_0_1$EN =
NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514 ;
// submodule enqDst_0_dummy2_1
assign enqDst_0_dummy2_1$D_IN = 1'd1 ;
assign enqDst_0_dummy2_1$EN = CAN_FIRE_RL_doEnq ;
// submodule enqDst_0_dummy2_1_1
assign enqDst_0_dummy2_1_1$D_IN = 1'd1 ;
assign enqDst_0_dummy2_1_1$EN = CAN_FIRE_RL_doEnq_2 ;
// submodule enqDst_1_0_dummy2_0
assign enqDst_1_0_dummy2_0$D_IN = 1'd1 ;
assign enqDst_1_0_dummy2_0$EN =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ;
// submodule enqDst_1_0_dummy2_1
assign enqDst_1_0_dummy2_1$D_IN = 1'd1 ;
assign enqDst_1_0_dummy2_1$EN = CAN_FIRE_RL_doEnq_1 ;
// submodule f_csr_reqs
assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ;
assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ;
assign f_csr_reqs$DEQ = 1'b0 ;
assign f_csr_reqs$CLR = 1'b0 ;
// submodule f_csr_rsps
assign f_csr_rsps$D_IN = 65'h0 ;
assign f_csr_rsps$ENQ = 1'b0 ;
assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ;
assign f_csr_rsps$CLR = 1'b0 ;
// submodule f_fpr_reqs
assign f_fpr_reqs$D_IN = hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$ENQ = EN_hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$DEQ = 1'b0 ;
assign f_fpr_reqs$CLR = 1'b0 ;
// submodule f_fpr_rsps
assign f_fpr_rsps$D_IN = 65'h0 ;
assign f_fpr_rsps$ENQ = 1'b0 ;
assign f_fpr_rsps$DEQ = EN_hart0_fpr_mem_server_response_get ;
assign f_fpr_rsps$CLR = 1'b0 ;
// submodule f_gpr_reqs
assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$DEQ = 1'b0 ;
assign f_gpr_reqs$CLR = 1'b0 ;
// submodule f_gpr_rsps
assign f_gpr_rsps$D_IN = 65'h0 ;
assign f_gpr_rsps$ENQ = 1'b0 ;
assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ;
assign f_gpr_rsps$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_reset ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_reset ;
assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule f_run_halt_reqs
assign f_run_halt_reqs$D_IN = hart0_server_run_halt_request_put ;
assign f_run_halt_reqs$ENQ = EN_hart0_server_run_halt_request_put ;
assign f_run_halt_reqs$DEQ = 1'b0 ;
assign f_run_halt_reqs$CLR = 1'b0 ;
// submodule f_run_halt_rsps
assign f_run_halt_rsps$D_IN = 1'b0 ;
assign f_run_halt_rsps$ENQ = 1'b0 ;
assign f_run_halt_rsps$DEQ = EN_hart0_server_run_halt_response_get ;
assign f_run_halt_rsps$CLR = 1'b0 ;
// submodule f_trace_data
assign f_trace_data$D_IN = 362'h0 ;
assign f_trace_data$ENQ = 1'b0 ;
assign f_trace_data$DEQ = EN_trace_data_out_get ;
assign f_trace_data$CLR = 1'b0 ;
// submodule llc
assign llc$dma_memReq_enq_x =
{ tlbQ$D_OUT[64:1],
577'h0000000000000000155555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555,
tlbQ$D_OUT[0],
tlbQ$D_OUT[6:4] } ;
assign llc$perf_req_r = 4'h0 ;
assign llc$perf_setStatus_doStats = core_0$sendDoStats ;
assign llc$to_child_rqFromC_enq_x =
NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 ?
enqDst_0_lat_0$wget[72:0] :
enqDst_0_rl[72:0] ;
assign llc$to_child_rsFromC_enq_x =
{ IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1235,
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1240,
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1245,
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1255,
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1261 } ;
assign llc$to_mem_rsFromM_enq_x =
{ new_cline__h112148,
llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ;
assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ;
assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ;
assign llc$EN_to_child_toC_deq =
WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ||
WILL_FIRE_RL_sendPRs ||
WILL_FIRE_RL_sendPRq ;
assign llc$EN_dma_memReq_enq = CAN_FIRE_RL_sendTlbReqToLLC ;
assign llc$EN_dma_respLd_deq =
WILL_FIRE_RL_sendLdRespToTlb ||
WILL_FIRE_RL_sendLdRespToMemLoader ;
assign llc$EN_dma_respSt_deq =
WILL_FIRE_RL_sendStRespToTlb ||
WILL_FIRE_RL_sendStRespToMemLoader ;
assign llc$EN_to_mem_toM_deq =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_rg_rd_req_beat == 3'd7 ||
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd7 ;
assign llc$EN_to_mem_rsFromM_enq =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
assign llc$EN_cRqStuck_get = 1'b0 ;
assign llc$EN_perf_setStatus = core_0$RDY_sendDoStats ;
assign llc$EN_perf_req = 1'b0 ;
assign llc$EN_perf_resp = 1'b0 ;
// submodule llc_axi4_adapter_f_pending_reads
assign llc_axi4_adapter_f_pending_reads$D_IN = llc$to_mem_toM_first[68:0] ;
assign llc_axi4_adapter_f_pending_reads$ENQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0 ;
assign llc_axi4_adapter_f_pending_reads$DEQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ;
// submodule llc_axi4_adapter_f_pending_writes
assign llc_axi4_adapter_f_pending_writes$D_IN =
llc$to_mem_toM_first[639:0] ;
assign llc_axi4_adapter_f_pending_writes$ENQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 ;
assign llc_axi4_adapter_f_pending_writes$DEQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_rg_wr_rsp_beat == 3'd7 ;
assign llc_axi4_adapter_f_pending_writes$CLR = 1'b0 ;
// submodule mmioPlatform_fromHostQ_clearReq_dummy2_0
assign mmioPlatform_fromHostQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmioPlatform_fromHostQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmioPlatform_fromHostQ_clearReq_dummy2_1
assign mmioPlatform_fromHostQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmioPlatform_fromHostQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmioPlatform_fromHostQ_deqReq_dummy2_0
assign mmioPlatform_fromHostQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmioPlatform_fromHostQ_deqReq_dummy2_0$EN =
mmioPlatform_fromHostQ_deqReq_lat_0$whas ;
// submodule mmioPlatform_fromHostQ_deqReq_dummy2_1
assign mmioPlatform_fromHostQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmioPlatform_fromHostQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmioPlatform_fromHostQ_deqReq_dummy2_2
assign mmioPlatform_fromHostQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmioPlatform_fromHostQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmioPlatform_fromHostQ_enqReq_dummy2_0
assign mmioPlatform_fromHostQ_enqReq_dummy2_0$D_IN = 1'b0 ;
assign mmioPlatform_fromHostQ_enqReq_dummy2_0$EN = 1'b0 ;
// submodule mmioPlatform_fromHostQ_enqReq_dummy2_1
assign mmioPlatform_fromHostQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmioPlatform_fromHostQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmioPlatform_fromHostQ_enqReq_dummy2_2
assign mmioPlatform_fromHostQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmioPlatform_fromHostQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmioPlatform_toHostQ_clearReq_dummy2_0
assign mmioPlatform_toHostQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmioPlatform_toHostQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmioPlatform_toHostQ_clearReq_dummy2_1
assign mmioPlatform_toHostQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmioPlatform_toHostQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmioPlatform_toHostQ_deqReq_dummy2_0
assign mmioPlatform_toHostQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmioPlatform_toHostQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_rl_tohost ;
// submodule mmioPlatform_toHostQ_deqReq_dummy2_1
assign mmioPlatform_toHostQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmioPlatform_toHostQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmioPlatform_toHostQ_deqReq_dummy2_2
assign mmioPlatform_toHostQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmioPlatform_toHostQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmioPlatform_toHostQ_enqReq_dummy2_0
assign mmioPlatform_toHostQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmioPlatform_toHostQ_enqReq_dummy2_0$EN =
mmioPlatform_toHostQ_enqReq_lat_0$whas ;
// submodule mmioPlatform_toHostQ_enqReq_dummy2_1
assign mmioPlatform_toHostQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmioPlatform_toHostQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmioPlatform_toHostQ_enqReq_dummy2_2
assign mmioPlatform_toHostQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmioPlatform_toHostQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_axi4_adapter_f_reqs_from_core
always@(MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1;
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2;
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3;
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4;
default: mmio_axi4_adapter_f_reqs_from_core$D_IN =
142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign mmio_axi4_adapter_f_reqs_from_core$ENQ =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ;
assign mmio_axi4_adapter_f_reqs_from_core$DEQ =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ;
// submodule mmio_axi4_adapter_f_rsps_to_core
assign mmio_axi4_adapter_f_rsps_to_core$D_IN =
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 ?
65'h10000000000000000 :
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_2 ;
assign mmio_axi4_adapter_f_rsps_to_core$ENQ =
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] == 2'b0 ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;
assign mmio_axi4_adapter_f_rsps_to_core$DEQ =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ;
assign mmio_axi4_adapter_f_rsps_to_core$CLR = 1'b0 ;
// submodule propDstData_0_dummy2_0
assign propDstData_0_dummy2_0$D_IN = 1'd1 ;
assign propDstData_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;
// submodule propDstData_0_dummy2_0_1
assign propDstData_0_dummy2_0_1$D_IN = 1'd1 ;
assign propDstData_0_dummy2_0_1$EN = CAN_FIRE_RL_srcPropose_4 ;
// submodule propDstData_0_dummy2_1
assign propDstData_0_dummy2_1$D_IN = 1'b0 ;
assign propDstData_0_dummy2_1$EN = 1'b0 ;
// submodule propDstData_0_dummy2_1_1
assign propDstData_0_dummy2_1_1$D_IN = 1'b0 ;
assign propDstData_0_dummy2_1_1$EN = 1'b0 ;
// submodule propDstData_1_0_dummy2_0
assign propDstData_1_0_dummy2_0$D_IN = 1'd1 ;
assign propDstData_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;
// submodule propDstData_1_0_dummy2_1
assign propDstData_1_0_dummy2_1$D_IN = 1'b0 ;
assign propDstData_1_0_dummy2_1$EN = 1'b0 ;
// submodule propDstData_1_1_dummy2_0
assign propDstData_1_1_dummy2_0$D_IN = 1'd1 ;
assign propDstData_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;
// submodule propDstData_1_1_dummy2_1
assign propDstData_1_1_dummy2_1$D_IN = 1'b0 ;
assign propDstData_1_1_dummy2_1$EN = 1'b0 ;
// submodule propDstData_1_dummy2_0
assign propDstData_1_dummy2_0$D_IN = 1'd1 ;
assign propDstData_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;
// submodule propDstData_1_dummy2_1
assign propDstData_1_dummy2_1$D_IN = 1'b0 ;
assign propDstData_1_dummy2_1$EN = 1'b0 ;
// submodule propDstIdx_0_dummy2_0
assign propDstIdx_0_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose ;
// submodule propDstIdx_0_dummy2_0_1
assign propDstIdx_0_dummy2_0_1$D_IN = 1'd1 ;
assign propDstIdx_0_dummy2_0_1$EN = CAN_FIRE_RL_srcPropose_4 ;
// submodule propDstIdx_0_dummy2_1
assign propDstIdx_0_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_0_dummy2_1$EN = propDstIdx_0_lat_1$whas ;
// submodule propDstIdx_0_dummy2_1_1
assign propDstIdx_0_dummy2_1_1$D_IN = 1'd1 ;
assign propDstIdx_0_dummy2_1_1$EN =
NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514 ;
// submodule propDstIdx_1_0_dummy2_0
assign propDstIdx_1_0_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_1_0_dummy2_0$EN = CAN_FIRE_RL_srcPropose_2 ;
// submodule propDstIdx_1_0_dummy2_1
assign propDstIdx_1_0_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_1_0_dummy2_1$EN = propDstIdx_1_0_lat_1$whas ;
// submodule propDstIdx_1_1_dummy2_0
assign propDstIdx_1_1_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_1_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_3 ;
// submodule propDstIdx_1_1_dummy2_1
assign propDstIdx_1_1_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_1_1_dummy2_1$EN = propDstIdx_1_1_lat_1$whas ;
// submodule propDstIdx_1_dummy2_0
assign propDstIdx_1_dummy2_0$D_IN = 1'd1 ;
assign propDstIdx_1_dummy2_0$EN = CAN_FIRE_RL_srcPropose_1 ;
// submodule propDstIdx_1_dummy2_1
assign propDstIdx_1_dummy2_1$D_IN = 1'd1 ;
assign propDstIdx_1_dummy2_1$EN = propDstIdx_1_lat_1$whas ;
// submodule tlbQ
assign tlbQ$D_IN =
NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514 ?
enqDst_0_lat_0_1$wget[64:0] :
enqDst_0_rl_1[64:0] ;
assign tlbQ$ENQ = CAN_FIRE_RL_doEnq_2 ;
assign tlbQ$DEQ = CAN_FIRE_RL_sendTlbReqToLLC ;
assign tlbQ$CLR = 1'b0 ;
// remaining internal signals
module_amoExec instance_amoExec_0(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
mmioPlatform_reqBE_BIT_4___h28407 &&
mmioPlatform_reqBE_BIT_0___h28447,
2'd0 }),
.amoExec_current_data(x__h35701),
.amoExec_in_data(mmioPlatform_reqData__h46741),
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h28407 &&
!mmioPlatform_reqBE_BIT_0___h28447),
.amoExec(x__h30431));
module_amoExec instance_amoExec_1(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
mmioPlatform_reqBE_BIT_4___h28407 &&
mmioPlatform_reqBE_BIT_0___h28447,
2'd0 }),
.amoExec_current_data(mmioPlatform_mtime__h35553),
.amoExec_in_data(mmioPlatform_reqData__h46741),
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h28407 &&
!mmioPlatform_reqBE_BIT_0___h28447),
.amoExec(x__h33341));
module_amoExec instance_amoExec_2(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
mmioPlatform_reqBE_BIT_4___h28407 &&
mmioPlatform_reqBE_BIT_0___h28447,
2'd0 }),
.amoExec_current_data(mmioPlatform_fromHostQ_data_0__h40939),
.amoExec_in_data(mmioPlatform_reqData__h46741),
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h28407 &&
!mmioPlatform_reqBE_BIT_0___h28447),
.amoExec(x__h39140));
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmioPlatform_reqFunc[3:0],
mmioPlatform_reqBE_BIT_4___h28407 &&
mmioPlatform_reqBE_BIT_0___h28447,
2'd0 }),
.amoExec_current_data(64'd0),
.amoExec_in_data(mmioPlatform_reqData__h46741),
.amoExec_upper_32_bits(mmioPlatform_reqBE_BIT_4___h28407 &&
!mmioPlatform_reqBE_BIT_0___h28447),
.amoExec(x__h41160));
assign DONTCARE_CONCAT_IF_mmioPlatform_reqFunc_99_BIT_ETC___d643 =
{ 1'h0,
(mmioPlatform_reqFunc[5:4] == 2'd2) ?
{ mmioPlatform_toHostQ_empty, 64'hAAAAAAAAAAAAAAAA } :
{ mmioPlatform_reqFunc[5:4] == 2'd1,
x1_avValue_data__h38611 } } ;
assign IF_IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4__ETC___d518 =
(IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
!mmioPlatform_mtip_0 ||
!IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
mmioPlatform_mtip_0) ?
core_0$RDY_mmioToPlatform_pRq_enq :
core_0$RDY_mmioToPlatform_pRs_enq ;
assign IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d415 =
(mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
(mmioPlatform_reqBE[0] ?
core_0$RDY_mmioToPlatform_pRq_enq :
core_0$RDY_mmioToPlatform_pRs_enq) :
!mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ;
assign IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 =
newData__h30320 <= mmioPlatform_mtime ;
assign IF_NOT_propDstIdx_0_dummy2_1_read__013_014_OR__ETC___d1048 =
NOT_propDstIdx_0_dummy2_1_read__013_014_OR_IF__ETC___d1047 ?
propDstIdx_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_lat_0_whas__67_THEN_propDstIdx_ETC___d970 :
propDstIdx_0_dummy2_1$Q_OUT &&
IF_propDstIdx_0_lat_0_whas__60_THEN_propDstIdx_ETC___d963 ;
assign IF_NOT_propDstIdx_1_0_dummy2_1_read__272_273_O_ETC___d1317 =
NOT_propDstIdx_1_0_dummy2_1_read__272_273_OR_I_ETC___d1316 ?
propDstIdx_1_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_1_lat_0_whas__136_THEN_propDst_ETC___d1139 :
propDstIdx_1_0_dummy2_1$Q_OUT &&
IF_propDstIdx_1_0_lat_0_whas__129_THEN_propDst_ETC___d1132 ;
assign IF_SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_ETC___d1120 =
SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_IF_ETC___d1044 ?
!srcRR_0 :
propDstIdx_0_dummy2_1$Q_OUT &&
IF_propDstIdx_0_lat_0_whas__60_THEN_propDstIdx_ETC___d963 ;
assign IF_SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_A_ETC___d1417 =
SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_AND__ETC___d1313 ?
!srcRR_1_0 :
propDstIdx_1_0_dummy2_1$Q_OUT &&
IF_propDstIdx_1_0_lat_0_whas__129_THEN_propDst_ETC___d1132 ;
assign IF_core_0_mmioToPlatform_cRq_first__41_BITS_14_ETC___d364 =
(core_0$mmioToPlatform_cRq_first[141:81] ==
mmioPlatform_toHostAddr) ?
67'h5AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[141:81] ==
mmioPlatform_fromHostAddr) ?
67'h6AAAAAAAAAAAAAAAA :
{ 3'd7, core_0$mmioToPlatform_cRq_first[141:78] }) ;
assign IF_enqDst_0_lat_0_1_whas__476_THEN_enqDst_0_la_ETC___d1481 =
NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514 ?
enqDst_0_lat_0_1$wget[65] :
enqDst_0_rl_1[65] ;
assign IF_enqDst_0_lat_0_whas__89_THEN_enqDst_0_lat_0_ETC___d994 =
NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 ?
enqDst_0_lat_0$wget[73] :
enqDst_0_rl[73] ;
assign IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1225 =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ?
enqDst_1_0_lat_0$wget[580] :
enqDst_1_0_rl[580] ;
assign IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1235 =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ?
enqDst_1_0_lat_0$wget[579:516] :
enqDst_1_0_rl[579:516] ;
assign IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1240 =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ?
enqDst_1_0_lat_0$wget[515:514] :
enqDst_1_0_rl[515:514] ;
assign IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1245 =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ?
enqDst_1_0_lat_0$wget[513] :
enqDst_1_0_rl[513] ;
assign IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1255 =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ?
enqDst_1_0_lat_0$wget[512:1] :
enqDst_1_0_rl[512:1] ;
assign IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1261 =
NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 ?
enqDst_1_0_lat_0$wget[0] :
enqDst_1_0_rl[0] ;
assign IF_enqDst_1_0_lat_1_whas__217_THEN_enqDst_1_0__ETC___d1263 =
{ CAN_FIRE_RL_doEnq_1 ||
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1245,
CAN_FIRE_RL_doEnq_1 ?
512'h55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 :
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1255,
x__h72720 } ;
assign IF_enqDst_1_0_lat_1_whas__217_THEN_enqDst_1_0__ETC___d1264 =
{ CAN_FIRE_RL_doEnq_1 ?
64'hAAAAAAAAAAAAAAAA :
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1235,
CAN_FIRE_RL_doEnq_1 ?
2'b10 :
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1240,
IF_enqDst_1_0_lat_1_whas__217_THEN_enqDst_1_0__ETC___d1263 } ;
assign IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785 =
(mmioPlatform_curReq[2:0] == 3'h0) ?
mmioPlatform_reqData :
64'd0 ;
assign IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836 =
(mmioPlatform_curReq[2:0] == 3'h0) ?
mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] :
64'd0 ;
assign IF_mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioP_ETC___d584 =
((mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
!mmioPlatform_mtip_0) ?
core_0$RDY_mmioToPlatform_pRq_enq :
mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 ||
!mmioPlatform_mtip_0 ||
core_0$RDY_mmioToPlatform_pRq_enq) &&
(mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
mmioPlatform_mtip_0 ||
core_0$RDY_mmioToPlatform_pRs_enq) ;
assign IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d536 =
mmioPlatform_reqBE[4] ?
{ {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1[31]}},
mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 } :
{ {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2[31]}},
mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 } ;
assign IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d600 =
mmioPlatform_reqBE[4] ?
{ {32{mmioPlatform_mtime_BITS_63_TO_32__q3[31]}},
mmioPlatform_mtime_BITS_63_TO_32__q3 } :
{ {32{mmioPlatform_mtime_BITS_31_TO_0__q4[31]}},
mmioPlatform_mtime_BITS_31_TO_0__q4 } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d494 =
{ mmioPlatform_reqBE[7] ?
mmioPlatform_reqData[63:56] :
mmioPlatform_mtimecmp_0[63:56],
mmioPlatform_reqBE[6] ?
mmioPlatform_reqData[55:48] :
mmioPlatform_mtimecmp_0[55:48],
mmioPlatform_reqBE[5] ?
mmioPlatform_reqData[47:40] :
mmioPlatform_mtimecmp_0[47:40],
mmioPlatform_reqBE[4] ?
mmioPlatform_reqData[39:32] :
mmioPlatform_mtimecmp_0[39:32] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d503 =
{ IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d494,
mmioPlatform_reqBE[3] ?
mmioPlatform_reqData[31:24] :
mmioPlatform_mtimecmp_0[31:24],
mmioPlatform_reqBE[2] ?
mmioPlatform_reqData[23:16] :
mmioPlatform_mtimecmp_0[23:16] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d511 =
{ IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d503,
mmioPlatform_reqBE[1] ?
mmioPlatform_reqData[15:8] :
mmioPlatform_mtimecmp_0[15:8],
mmioPlatform_reqBE[0] ?
mmioPlatform_reqData[7:0] :
mmioPlatform_mtimecmp_0[7:0] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d563 =
{ mmioPlatform_reqBE[7] ?
mmioPlatform_reqData[63:56] :
mmioPlatform_mtime[63:56],
mmioPlatform_reqBE[6] ?
mmioPlatform_reqData[55:48] :
mmioPlatform_mtime[55:48],
mmioPlatform_reqBE[5] ?
mmioPlatform_reqData[47:40] :
mmioPlatform_mtime[47:40],
mmioPlatform_reqBE[4] ?
mmioPlatform_reqData[39:32] :
mmioPlatform_mtime[39:32] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d568 =
{ IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d563,
mmioPlatform_reqBE[3] ?
mmioPlatform_reqData[31:24] :
mmioPlatform_mtime[31:24],
mmioPlatform_reqBE[2] ?
mmioPlatform_reqData[23:16] :
mmioPlatform_mtime[23:16] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d573 =
{ IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d568,
mmioPlatform_reqBE[1] ?
mmioPlatform_reqData[15:8] :
mmioPlatform_mtime[15:8],
mmioPlatform_reqBE[0] ?
mmioPlatform_reqData[7:0] :
mmioPlatform_mtime[7:0] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d664 =
{ mmioPlatform_reqBE[7] ?
mmioPlatform_reqData[63:56] :
mmioPlatform_fromHostQ_data_0[63:56],
mmioPlatform_reqBE[6] ?
mmioPlatform_reqData[55:48] :
mmioPlatform_fromHostQ_data_0[55:48],
mmioPlatform_reqBE[5] ?
mmioPlatform_reqData[47:40] :
mmioPlatform_fromHostQ_data_0[47:40],
mmioPlatform_reqBE[4] ?
mmioPlatform_reqData[39:32] :
mmioPlatform_fromHostQ_data_0[39:32] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d669 =
{ IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d664,
mmioPlatform_reqBE[3] ?
mmioPlatform_reqData[31:24] :
mmioPlatform_fromHostQ_data_0[31:24],
mmioPlatform_reqBE[2] ?
mmioPlatform_reqData[23:16] :
mmioPlatform_fromHostQ_data_0[23:16] } ;
assign IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d674 =
{ IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d669,
mmioPlatform_reqBE[1] ?
mmioPlatform_reqData[15:8] :
mmioPlatform_fromHostQ_data_0[15:8],
mmioPlatform_reqBE[0] ?
mmioPlatform_reqData[7:0] :
mmioPlatform_fromHostQ_data_0[7:0] } ;
assign IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d416 =
(mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ?
core_0$RDY_mmioToPlatform_pRs_enq :
IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d415 ;
assign IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_1_ETC___d537 =
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtimecmp_0 :
IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d536 ;
assign IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_1_ETC___d601 =
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtime :
IF_mmioPlatform_reqBE_02_BIT_4_03_THEN_SEXT_mm_ETC___d600 ;
assign IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_2_ETC___d682 =
(mmioPlatform_reqFunc[5:4] == 2'd2) ?
{ mmioPlatform_fromHostQ_empty ?
x__h41149 == 64'd0 :
x__h39129 == 64'd0,
64'hAAAAAAAAAAAAAAAA } :
{ mmioPlatform_reqFunc[5:4] == 2'd1,
x1_avValue_data__h43078 } ;
assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__54__ETC___d163 =
mmioPlatform_toHostQ_enqReq_lat_0$whas ?
mmioPlatform_toHostQ_enqReq_lat_0$wget[64] :
mmioPlatform_toHostQ_enqReq_rl[64] ;
assign IF_mmioPlatform_waitLowerMSIPCRs_51_THEN_core__ETC___d459 =
mmioPlatform_waitLowerMSIPCRs ?
core_0$RDY_mmioToPlatform_cRs_first &&
core_0$RDY_mmioToPlatform_cRs_deq :
(!mmioPlatform_waitUpperMSIPCRs ||
core_0$RDY_mmioToPlatform_cRs_first) &&
(!mmioPlatform_waitUpperMSIPCRs ||
core_0$RDY_mmioToPlatform_cRs_deq) ;
assign IF_mmio_axi4_adapter_f_rsps_to_core_first__15__ETC___d930 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
mmioPlatform_fetchingWay <
(mmioPlatform_reqFunc[5:4] == 2'd0 &&
mmioPlatform_reqFunc[0]) ||
core_0$RDY_mmioToPlatform_pRs_enq :
core_0$RDY_mmioToPlatform_pRs_enq ;
assign IF_mmio_axi4_adapter_f_rsps_to_core_first__15__ETC___d947 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[64] ?
{ mmioPlatform_fetchingWay,
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d942,
1'd1,
mmioPlatform_fetchingWay ?
mmioPlatform_fetchedInsts_0 :
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d942 } :
{ 1'h0, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ;
assign IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1067 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[8:7] :
propDstData_0_rl[8:7]) :
2'd0 ;
assign IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1077 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[6:5] :
propDstData_0_rl[6:5]) :
2'd0 ;
assign IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1149 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[579:516] :
propDstData_1_0_rl[579:516] ;
assign IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1154 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[515:514] :
propDstData_1_0_rl[515:514] ;
assign IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1175 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[0] :
propDstData_1_0_rl[0] ;
assign IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1187 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[579:516] :
propDstData_1_1_rl[579:516] ;
assign IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1192 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[515:514] :
propDstData_1_1_rl[515:514] ;
assign IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1213 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[0] :
propDstData_1_1_rl[0] ;
assign IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1071 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[8:7] :
propDstData_1_rl[8:7]) :
2'd0 ;
assign IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1081 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[6:5] :
propDstData_1_rl[6:5]) :
2'd0 ;
assign IF_propDstIdx_0_lat_0_1_whas__461_THEN_propDst_ETC___d1464 =
CAN_FIRE_RL_srcPropose_4 || propDstIdx_0_rl_1 ;
assign IF_propDstIdx_0_lat_0_whas__60_THEN_propDstIdx_ETC___d963 =
CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ;
assign IF_propDstIdx_1_0_lat_0_whas__129_THEN_propDst_ETC___d1132 =
CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ;
assign IF_propDstIdx_1_1_lat_0_whas__136_THEN_propDst_ETC___d1139 =
CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ;
assign IF_propDstIdx_1_lat_0_whas__67_THEN_propDstIdx_ETC___d970 =
CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ;
assign NOT_enqDst_0_dummy2_0_1_read__507_508_OR_NOT_e_ETC___d1514 =
(!enqDst_0_dummy2_0_1$Q_OUT || !enqDst_0_dummy2_1_1$Q_OUT ||
!enqDst_0_rl_1[65]) &&
propDstIdx_0_dummy2_1_1$Q_OUT &&
IF_propDstIdx_0_lat_0_1_whas__461_THEN_propDst_ETC___d1464 ;
assign NOT_enqDst_0_dummy2_0_read__034_035_OR_NOT_enq_ETC___d1050 =
(!enqDst_0_dummy2_0$Q_OUT || !enqDst_0_dummy2_1$Q_OUT ||
!enqDst_0_rl[73]) &&
(SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_IF_ETC___d1044 ||
IF_NOT_propDstIdx_0_dummy2_1_read__013_014_OR__ETC___d1048) ;
assign NOT_enqDst_1_0_dummy2_0_read__303_304_OR_NOT_e_ETC___d1319 =
(!enqDst_1_0_dummy2_0$Q_OUT || !enqDst_1_0_dummy2_1$Q_OUT ||
!enqDst_1_0_rl[580]) &&
(SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_AND__ETC___d1313 ||
IF_NOT_propDstIdx_1_0_dummy2_1_read__272_273_O_ETC___d1317) ;
assign NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610 =
llc_axi4_adapter_cfg_verbosity > 4'd1 ;
assign NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d705 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd2 &&
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqFunc[5:4] == 2'd2) ;
assign NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d713 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd3 &&
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqFunc[5:4] == 2'd2) ;
assign NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d719 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 ;
assign NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d729 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 ;
assign NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d920 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_reqFunc[5:4] == 2'd0 ;
assign NOT_mmioPlatform_curReq_94_BITS_66_TO_64_95_EQ_ETC___d933 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_reqFunc[5:4] == 2'd0 ;
assign NOT_mmioPlatform_fromHostQ_clearReq_dummy2_1_r_ETC___d281 =
!mmioPlatform_fromHostQ_clearReq_dummy2_1$Q_OUT ||
!mmioPlatform_fromHostQ_clearReq_rl ;
assign NOT_mmioPlatform_fromHostQ_enqReq_dummy2_2_rea_ETC___d302 =
(!mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT ||
!mmioPlatform_fromHostQ_enqReq_rl[64]) &&
(mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT &&
(mmioPlatform_fromHostQ_deqReq_lat_0$whas ||
mmioPlatform_fromHostQ_deqReq_rl) ||
mmioPlatform_fromHostQ_empty) ;
assign NOT_mmioPlatform_mtip_0_18_25_AND_mmioPlatform_ETC___d333 =
!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 ||
!core_0$mmioToPlatform_cRq_notEmpty ||
core_0$RDY_mmioToPlatform_cRq_first &&
core_0$RDY_mmioToPlatform_cRq_deq ;
assign NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d449 =
mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] &&
(mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqFunc[5:4] == 2'd2) ;
assign NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d544 =
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
(IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
!mmioPlatform_mtip_0 ||
!IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 &&
mmioPlatform_mtip_0) ;
assign NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ__ETC___d607 =
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
(mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 &&
mmioPlatform_mtip_0) ;
assign NOT_mmioPlatform_toHostQ_clearReq_dummy2_1_rea_ETC___d203 =
!mmioPlatform_toHostQ_clearReq_dummy2_1$Q_OUT ||
!mmioPlatform_toHostQ_clearReq_rl ;
assign NOT_mmioPlatform_toHostQ_enqReq_dummy2_2_read__ETC___d224 =
(!mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT ||
(mmioPlatform_toHostQ_enqReq_lat_0$whas ?
!mmioPlatform_toHostQ_enqReq_lat_0$wget[64] :
!mmioPlatform_toHostQ_enqReq_rl[64])) &&
(mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT &&
(!mmioPlatform_toHostQ_empty ||
mmioPlatform_toHostQ_deqReq_rl) ||
mmioPlatform_toHostQ_empty) ;
assign NOT_propDstData_1_0_dummy2_1_read__320_331_OR__ETC___d1332 =
!propDstData_1_0_dummy2_1$Q_OUT ||
(CAN_FIRE_RL_srcPropose_2 ?
!propDstData_1_0_lat_0$wget[513] :
!propDstData_1_0_rl[513]) ;
assign NOT_propDstData_1_1_dummy2_1_read__322_333_OR__ETC___d1334 =
!propDstData_1_1_dummy2_1$Q_OUT ||
(CAN_FIRE_RL_srcPropose_3 ?
!propDstData_1_1_lat_0$wget[513] :
!propDstData_1_1_rl[513]) ;
assign NOT_propDstIdx_0_dummy2_1_read__013_014_OR_IF__ETC___d1047 =
!propDstIdx_0_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ;
assign NOT_propDstIdx_1_0_dummy2_1_read__272_273_OR_I_ETC___d1316 =
!propDstIdx_1_0_dummy2_1$Q_OUT ||
!CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ;
assign SEL_ARR_IF_propDstData_0_dummy2_1_read__051_TH_ETC___d1115 =
{ CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13,
CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14,
SEL_ARR_propDstData_0_dummy2_1_read__051_AND_I_ETC___d1114 } ;
assign SEL_ARR_IF_propDstData_1_0_dummy2_1_read__320__ETC___d1412 =
{ CASE_x7791_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24,
!CASE_x7791_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1405,
x__h80207 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1354 =
{ CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1371 =
{ SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1354,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1388 =
{ SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1371,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1405 =
{ SEL_ARR_IF_propDstData_1_0_lat_0_whas__144_THE_ETC___d1388,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22,
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 } ;
assign SEL_ARR_propDstData_0_dummy2_1_read__051_AND_I_ETC___d1114 =
{ CASE_x9168_0_propDstData_0_dummy2_1_read__051__ETC__q12,
x__h59482,
x__h59489 } ;
assign b__h111153 =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ?
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
llc_axi4_adapter_ctr_wr_rsps_pending_crg ;
assign b__h3158 =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ?
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
mmio_axi4_adapter_ctr_wr_rsps_pending_crg ;
assign data__h30239 =
mmioPlatform_waitLowerMSIPCRs ?
{ 63'd0, core_0$mmioToPlatform_cRs_first } :
{ v__h30032, 32'd0 } ;
assign failed_testnum__h140054 =
{ 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ;
assign mem_req_rd_addr_araddr__h111446 =
{ llc$to_mem_toM_first[68:11], x__h111481 } ;
assign mem_req_wr_addr_awaddr__h125370 =
{ llc$to_mem_toM_first[639:582], x__h125395 } ;
assign mmioPlatform_cycle_10_ULT_99___d311 = mmioPlatform_cycle < 7'd99 ;
assign mmioPlatform_fetchingWay_25_ULT_mmioPlatform_r_ETC___d935 =
mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ;
assign mmioPlatform_fromHostQ_data_0__h40939 =
mmioPlatform_fromHostQ_data_0 ;
assign mmioPlatform_fromHostQ_enqReq_dummy2_2_read__8_ETC___d294 =
mmioPlatform_fromHostQ_enqReq_dummy2_2$Q_OUT &&
mmioPlatform_fromHostQ_enqReq_rl[64] ||
(!mmioPlatform_fromHostQ_deqReq_dummy2_2$Q_OUT ||
!mmioPlatform_fromHostQ_deqReq_lat_0$whas &&
!mmioPlatform_fromHostQ_deqReq_rl) &&
mmioPlatform_fromHostQ_full ;
assign mmioPlatform_mtime_BITS_31_TO_0__q4 = mmioPlatform_mtime[31:0] ;
assign mmioPlatform_mtime_BITS_63_TO_32__q3 = mmioPlatform_mtime[63:32] ;
assign mmioPlatform_mtime__h35553 = mmioPlatform_mtime ;
assign mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 =
mmioPlatform_mtimecmp_0 <= newData__h33250 ;
assign mmioPlatform_mtimecmp_0_19_ULE_mmioPlatform_mt_ETC___d320 =
mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ;
assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q2 =
mmioPlatform_mtimecmp_0[31:0] ;
assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q1 =
mmioPlatform_mtimecmp_0[63:32] ;
assign mmioPlatform_reqBE_BIT_0___h28447 = mmioPlatform_reqBE[0] ;
assign mmioPlatform_reqBE_BIT_4___h28407 = mmioPlatform_reqBE[4] ;
assign mmioPlatform_reqData__h46741 = mmioPlatform_reqData ;
assign mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d426 =
mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] ||
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 &&
!mmioPlatform_reqBE[0] ;
assign mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d530 =
mmioPlatform_reqFunc[5:4] == 2'd0 ||
mmioPlatform_reqFunc[5:4] == 2'd1 ||
(!IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 ||
mmioPlatform_mtip_0) &&
(IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4_00__ETC___d513 ||
!mmioPlatform_mtip_0) ;
assign mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_01_ETC___d595 =
mmioPlatform_reqFunc[5:4] == 2'd0 ||
mmioPlatform_reqFunc[5:4] == 2'd1 ||
(!mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 ||
mmioPlatform_mtip_0) &&
(mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioPlat_ETC___d575 ||
!mmioPlatform_mtip_0) ;
assign mmioPlatform_toHostQ_enqReq_dummy2_2_read__04__ETC___d216 =
mmioPlatform_toHostQ_enqReq_dummy2_2$Q_OUT &&
IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__54__ETC___d163 ||
(!mmioPlatform_toHostQ_deqReq_dummy2_2$Q_OUT ||
!(!mmioPlatform_toHostQ_empty) &&
!mmioPlatform_toHostQ_deqReq_rl) &&
mmioPlatform_toHostQ_full ;
assign n__read_addr__h59350 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[72:9] :
propDstData_0_rl[72:9]) :
64'd0 ;
assign n__read_addr__h59435 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[72:9] :
propDstData_1_rl[72:9]) :
64'd0 ;
assign n__read_addr__h77969 =
propDstData_1_0_dummy2_1$Q_OUT ?
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1149 :
64'd0 ;
assign n__read_addr__h78048 =
propDstData_1_1_dummy2_1$Q_OUT ?
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1187 :
64'd0 ;
assign n__read_child__h59355 =
propDstData_0_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[0] :
propDstData_0_rl[0]) ;
assign n__read_child__h59440 =
propDstData_1_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[0] :
propDstData_1_rl[0]) ;
assign n__read_child__h77972 =
propDstData_1_0_dummy2_1$Q_OUT &&
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1175 ;
assign n__read_child__h78051 =
propDstData_1_1_dummy2_1$Q_OUT &&
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1213 ;
assign n__read_id__h59354 =
propDstData_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[3:1] :
propDstData_0_rl[3:1]) :
3'd0 ;
assign n__read_id__h59439 =
propDstData_1_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[3:1] :
propDstData_1_rl[3:1]) :
3'd0 ;
assign n__read_snd_addr__h92140 =
propDstData_0_dummy2_1_1$Q_OUT ?
(CAN_FIRE_RL_srcPropose_4 ?
core_0$tlbToMem_memReq_first[64:1] :
propDstData_0_rl_1[64:1]) :
64'd0 ;
assign n__read_snd_id__h92141 =
propDstData_0_dummy2_1_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_4 ?
core_0$tlbToMem_memReq_first[0] :
propDstData_0_rl_1[0]) ;
assign newData__h30320 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
x__h30431 :
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d511 ;
assign newData__h33250 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
x__h33341 :
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d573 ;
assign new_cline__h112148 =
{ llc_axi4_adapter_master_xactor_rg_rd_data[66:3],
llc_axi4_adapter_rg_cline[511:64] } ;
assign op_result__h46757 =
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 +
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ;
assign op_result__h47287 = w1__h46154 ^ w2__h46156 ;
assign op_result__h47292 = w1__h46154 & w2__h46156 ;
assign op_result__h47297 = w1__h46154 | w2__h46156 ;
assign op_result__h47302 =
(w1__h46154 < w2__h46156) ? w1__h46154 : w2__h46156 ;
assign op_result__h47308 =
(w1__h46154 <= w2__h46156) ? w2__h46156 : w1__h46154 ;
assign op_result__h47315 =
((IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 ^
64'h8000000000000000) <
(IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ^
64'h8000000000000000)) ?
w1__h46154 :
w2__h46156 ;
assign op_result__h47321 =
((IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 ^
64'h8000000000000000) <=
(IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 ^
64'h8000000000000000)) ?
w2__h46156 :
w1__h46154 ;
assign propDstData_0_dummy2_1_read__051_AND_IF_propDs_ETC___d1087 =
propDstData_0_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[4] :
propDstData_0_rl[4]) ;
assign propDstData_1_dummy2_1_read__056_AND_IF_propDs_ETC___d1091 =
propDstData_1_dummy2_1$Q_OUT &&
(CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[4] :
propDstData_1_rl[4]) ;
assign result__h46200 =
{ mmioPlatform_reqData[63:8],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0] } ;
assign result__h46324 = { 56'd0, mmioPlatform_reqData[7:0] } ;
assign result__h46352 = { 56'd0, mmioPlatform_reqData[15:8] } ;
assign result__h46380 = { 56'd0, mmioPlatform_reqData[23:16] } ;
assign result__h46408 = { 56'd0, mmioPlatform_reqData[31:24] } ;
assign result__h46436 = { 56'd0, mmioPlatform_reqData[39:32] } ;
assign result__h46464 = { 56'd0, mmioPlatform_reqData[47:40] } ;
assign result__h46492 = { 56'd0, mmioPlatform_reqData[55:48] } ;
assign result__h46520 = { 56'd0, mmioPlatform_reqData[63:56] } ;
assign result__h46565 = { 48'd0, mmioPlatform_reqData[15:0] } ;
assign result__h46593 = { 48'd0, mmioPlatform_reqData[31:16] } ;
assign result__h46621 = { 48'd0, mmioPlatform_reqData[47:32] } ;
assign result__h46649 = { 48'd0, mmioPlatform_reqData[63:48] } ;
assign result__h46690 = { 32'd0, mmioPlatform_reqData[31:0] } ;
assign result__h46718 = { 32'd0, mmioPlatform_reqData[63:32] } ;
assign result__h46844 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ;
assign result__h46871 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ;
assign result__h46898 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ;
assign result__h46925 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ;
assign result__h46952 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ;
assign result__h46979 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ;
assign result__h47006 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ;
assign result__h47033 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ;
assign result__h47077 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ;
assign result__h47104 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ;
assign result__h47131 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ;
assign result__h47158 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ;
assign result__h47198 =
{ 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ;
assign result__h47225 =
{ 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ;
assign result__h47342 =
{ mmioPlatform_reqData[63:16],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0],
mmioPlatform_reqData[7:0] } ;
assign result__h47408 =
{ mmioPlatform_reqData[63:24],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0],
mmioPlatform_reqData[15:0] } ;
assign result__h47474 =
{ mmioPlatform_reqData[63:32],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0],
mmioPlatform_reqData[23:0] } ;
assign result__h47540 =
{ mmioPlatform_reqData[63:40],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0],
mmioPlatform_reqData[31:0] } ;
assign result__h47606 =
{ mmioPlatform_reqData[63:48],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0],
mmioPlatform_reqData[39:0] } ;
assign result__h47672 =
{ mmioPlatform_reqData[63:56],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0],
mmioPlatform_reqData[47:0] } ;
assign result__h47738 =
{ IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[7:0],
mmioPlatform_reqData[55:0] } ;
assign result__h47800 =
{ mmioPlatform_reqData[63:16],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0] } ;
assign result__h47845 =
{ mmioPlatform_reqData[63:32],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0],
mmioPlatform_reqData[15:0] } ;
assign result__h47911 =
{ mmioPlatform_reqData[63:48],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0],
mmioPlatform_reqData[31:0] } ;
assign result__h47977 =
{ IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[15:0],
mmioPlatform_reqData[47:0] } ;
assign result__h48035 =
{ mmioPlatform_reqData[63:32],
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[31:0] } ;
assign result__h48080 =
{ IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875[31:0],
mmioPlatform_reqData[31:0] } ;
assign v__h30032 = mmioPlatform_waitUpperMSIPCRs ? v__h30069 : 32'd0 ;
assign v__h30069 = { 31'd0, core_0$mmioToPlatform_cRs_first } ;
assign w16149_BITS_31_TO_0__q7 = w1__h46149[31:0] ;
assign w1___1__h46259 = { 32'd0, w1__h46149[31:0] } ;
assign w26150_BITS_31_TO_0__q8 = w2__h46150[31:0] ;
assign w2___1__h46260 = { 32'd0, w2__h46150[31:0] } ;
assign x1_avValue_data__h38611 =
mmioPlatform_toHostQ_empty ?
64'd0 :
mmioPlatform_toHostQ_data_0 ;
assign x1_avValue_data__h43078 =
mmioPlatform_fromHostQ_empty ?
64'd0 :
mmioPlatform_fromHostQ_data_0 ;
assign x__h111481 = { llc_axi4_adapter_rg_rd_req_beat, 3'b0 } ;
assign x__h125395 = { llc_axi4_adapter_rg_wr_req_beat, 3'b0 } ;
assign x__h35701 = mmioPlatform_mtimecmp_0 ;
assign x__h39129 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
x__h39140 :
IF_mmioPlatform_reqBE_02_BIT_7_78_THEN_mmioPla_ETC___d674 ;
assign x__h41149 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
x__h41160 :
{ mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0,
mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0,
mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0,
mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : 8'd0,
mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : 8'd0,
mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0,
mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0,
mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ;
assign x__h48257 = { mmioPlatform_curReq[63:3], 3'b0 } ;
assign x__h59168 =
SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_IF_ETC___d1044 ?
srcRR_0 :
NOT_propDstIdx_0_dummy2_1_read__013_014_OR_IF__ETC___d1047 ;
assign x__h72720 =
!CAN_FIRE_RL_doEnq_1 &&
IF_enqDst_1_0_lat_0_whas__220_THEN_enqDst_1_0__ETC___d1261 ;
assign x__h77791 =
SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_AND__ETC___d1313 ?
srcRR_1_0 :
NOT_propDstIdx_1_0_dummy2_1_read__272_273_OR_I_ETC___d1316 ;
assign x_data__h28822 = { 31'd0, mmioPlatform_reqData[0] } ;
always@(llc$dma_respLd_first)
begin
case (llc$dma_respLd_first[2:0])
3'd0: ld_data__h109019 = llc$dma_respLd_first[68:5];
3'd1: ld_data__h109019 = llc$dma_respLd_first[132:69];
3'd2: ld_data__h109019 = llc$dma_respLd_first[196:133];
3'd3: ld_data__h109019 = llc$dma_respLd_first[260:197];
3'd4: ld_data__h109019 = llc$dma_respLd_first[324:261];
3'd5: ld_data__h109019 = llc$dma_respLd_first[388:325];
3'd6: ld_data__h109019 = llc$dma_respLd_first[452:389];
3'd7: ld_data__h109019 = llc$dma_respLd_first[516:453];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat)
3'd0: data64__h125285 = llc$to_mem_toM_first[63:0];
3'd1: data64__h125285 = llc$to_mem_toM_first[127:64];
3'd2: data64__h125285 = llc$to_mem_toM_first[191:128];
3'd3: data64__h125285 = llc$to_mem_toM_first[255:192];
3'd4: data64__h125285 = llc$to_mem_toM_first[319:256];
3'd5: data64__h125285 = llc$to_mem_toM_first[383:320];
3'd6: data64__h125285 = llc$to_mem_toM_first[447:384];
3'd7: data64__h125285 = llc$to_mem_toM_first[511:448];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat)
3'd0: strb8__h125286 = llc$to_mem_toM_first[519:512];
3'd1: strb8__h125286 = llc$to_mem_toM_first[527:520];
3'd2: strb8__h125286 = llc$to_mem_toM_first[535:528];
3'd3: strb8__h125286 = llc$to_mem_toM_first[543:536];
3'd4: strb8__h125286 = llc$to_mem_toM_first[551:544];
3'd5: strb8__h125286 = llc$to_mem_toM_first[559:552];
3'd6: strb8__h125286 = llc$to_mem_toM_first[567:560];
3'd7: strb8__h125286 = llc$to_mem_toM_first[575:568];
endcase
end
always@(mmioPlatform_curReq or
result__h46324 or
result__h46352 or
result__h46380 or
result__h46408 or
result__h46436 or
result__h46464 or result__h46492 or result__h46520)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46324;
3'h1:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46352;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46380;
3'h3:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46408;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46436;
3'h5:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46464;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46492;
3'h7:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 =
result__h46520;
endcase
end
always@(mmioPlatform_curReq or
result__h46565 or
result__h46593 or result__h46621 or result__h46649)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 =
result__h46565;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 =
result__h46593;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 =
result__h46621;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 =
result__h46649;
default: IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or result__h46690 or result__h46718)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 =
result__h46690;
3'h4:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 =
result__h46718;
default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 = 64'd0;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 or
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785)
begin
case (mmioPlatform_reqSz)
2'b0:
w2__h46150 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765;
2'b01:
w2__h46150 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778;
2'b10:
w2__h46150 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q5;
2'b11:
w2__h46150 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 or
w2___1__h46260 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785)
begin
case (mmioPlatform_reqSz)
2'b0:
w2__h46156 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765;
2'b01:
w2__h46156 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778;
2'b10: w2__h46156 = w2___1__h46260;
2'b11:
w2__h46156 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785;
endcase
end
always@(mmioPlatform_curReq or
result__h46844 or
result__h46871 or
result__h46898 or
result__h46925 or
result__h46952 or
result__h46979 or result__h47006 or result__h47033)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h46844;
3'h1:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h46871;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h46898;
3'h3:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h46925;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h46952;
3'h5:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h46979;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h47006;
3'h7:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 =
result__h47033;
endcase
end
always@(mmioPlatform_curReq or
result__h47077 or
result__h47104 or result__h47131 or result__h47158)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 =
result__h47077;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 =
result__h47104;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 =
result__h47131;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 =
result__h47158;
default: IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or result__h47198 or result__h47225)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 =
result__h47198;
3'h4:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 =
result__h47225;
default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 = 64'd0;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 or
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836)
begin
case (mmioPlatform_reqSz)
2'b0:
w1__h46149 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817;
2'b01:
w1__h46149 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829;
2'b10:
w1__h46149 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q6;
2'b11:
w1__h46149 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 or
w1___1__h46259 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836)
begin
case (mmioPlatform_reqSz)
2'b0:
w1__h46154 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817;
2'b01:
w1__h46154 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829;
2'b10: w1__h46154 = w1___1__h46259;
2'b11:
w1__h46154 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829 or
w16149_BITS_31_TO_0__q7 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836)
begin
case (mmioPlatform_reqSz)
2'b0:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d817;
2'b01:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d829;
2'b10:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 =
{ {32{w16149_BITS_31_TO_0__q7[31]}}, w16149_BITS_31_TO_0__q7 };
2'b11:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d843 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d836;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778 or
w26150_BITS_31_TO_0__q8 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785)
begin
case (mmioPlatform_reqSz)
2'b0:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d765;
2'b01:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d778;
2'b10:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 =
{ {32{w26150_BITS_31_TO_0__q8[31]}}, w26150_BITS_31_TO_0__q8 };
2'b11:
IF_mmioPlatform_reqSz_35_EQ_0b10_42_THEN_SEXT__ETC___d845 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785;
endcase
end
always@(mmioPlatform_reqAmofunc or
op_result__h47321 or
w2__h46156 or
op_result__h46757 or
op_result__h47287 or
op_result__h47292 or
op_result__h47297 or
op_result__h47315 or op_result__h47302 or op_result__h47308)
begin
case (mmioPlatform_reqAmofunc)
4'd0:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
w2__h46156;
4'd1:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h46757;
4'd2:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h47287;
4'd3:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h47292;
4'd4:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h47297;
4'd5:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h47315;
4'd7:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h47302;
4'd8:
IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h47308;
default: IF_mmioPlatform_reqAmofunc_40_EQ_0_41_THEN_IF__ETC___d875 =
op_result__h47321;
endcase
end
always@(mmioPlatform_curReq or
result__h47800 or
result__h47845 or result__h47911 or result__h47977)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908 =
result__h47800;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908 =
result__h47845;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908 =
result__h47911;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908 =
result__h47977;
default: IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or
result__h46200 or
result__h47342 or
result__h47408 or
result__h47474 or
result__h47540 or
result__h47606 or result__h47672 or result__h47738)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h46200;
3'h1:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h47342;
3'h2:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h47408;
3'h3:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h47474;
3'h4:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h47540;
3'h5:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h47606;
3'h6:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h47672;
3'h7:
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 =
result__h47738;
endcase
end
always@(mmioPlatform_curReq or result__h48035 or result__h48080)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 =
result__h48035;
3'h4:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 =
result__h48080;
default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908 or
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785)
begin
case (mmioPlatform_reqSz)
2'b0:
x__h46145 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d899;
2'b01:
x__h46145 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d908;
2'b10:
x__h46145 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9;
2'b11:
x__h46145 =
IF_mmioPlatform_curReq_94_BITS_2_TO_0_37_EQ_0x_ETC___d785;
endcase
end
always@(mmioPlatform_reqFunc)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0, 2'd1, 2'd2:
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d440 =
mmioPlatform_reqFunc;
2'd3:
IF_mmioPlatform_reqFunc_99_BITS_5_TO_4_00_EQ_0_ETC___d440 =
{ 2'd3, mmioPlatform_reqFunc[3:0] };
endcase
end
always@(mmioPlatform_instSel or mmio_axi4_adapter_f_rsps_to_core$D_OUT)
begin
case (mmioPlatform_instSel)
1'd0:
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d942 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0];
1'd1:
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d942 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32];
endcase
end
always@(mmioPlatform_reqFunc or
IF_IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4__ETC___d518 or
core_0$RDY_mmioToPlatform_pRs_enq)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0, 2'd1:
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 =
core_0$RDY_mmioToPlatform_pRs_enq;
default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q10 =
IF_IF_NOT_mmioPlatform_reqFunc_99_BITS_5_TO_4__ETC___d518;
endcase
end
always@(mmioPlatform_reqFunc or
IF_mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioP_ETC___d584 or
core_0$RDY_mmioToPlatform_pRs_enq)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0, 2'd1:
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 =
core_0$RDY_mmioToPlatform_pRs_enq;
default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q11 =
IF_mmioPlatform_mtimecmp_0_19_ULE_IF_NOT_mmioP_ETC___d584;
endcase
end
always@(srcRR_0 or
propDstIdx_0_dummy2_1$Q_OUT or
IF_propDstIdx_0_lat_0_whas__60_THEN_propDstIdx_ETC___d963 or
propDstIdx_1_dummy2_1$Q_OUT or
IF_propDstIdx_1_lat_0_whas__67_THEN_propDstIdx_ETC___d970)
begin
case (srcRR_0)
1'd0:
SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_IF_ETC___d1044 =
propDstIdx_0_dummy2_1$Q_OUT &&
IF_propDstIdx_0_lat_0_whas__60_THEN_propDstIdx_ETC___d963;
1'd1:
SEL_ARR_propDstIdx_0_dummy2_1_read__013_AND_IF_ETC___d1044 =
propDstIdx_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_lat_0_whas__67_THEN_propDstIdx_ETC___d970;
endcase
end
always@(srcRR_1_0 or
propDstIdx_1_0_dummy2_1$Q_OUT or
IF_propDstIdx_1_0_lat_0_whas__129_THEN_propDst_ETC___d1132 or
propDstIdx_1_1_dummy2_1$Q_OUT or
IF_propDstIdx_1_1_lat_0_whas__136_THEN_propDst_ETC___d1139)
begin
case (srcRR_1_0)
1'd0:
SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_AND__ETC___d1313 =
propDstIdx_1_0_dummy2_1$Q_OUT &&
IF_propDstIdx_1_0_lat_0_whas__129_THEN_propDst_ETC___d1132;
1'd1:
SEL_ARR_propDstIdx_1_0_dummy2_1_read__272_AND__ETC___d1313 =
propDstIdx_1_1_dummy2_1$Q_OUT &&
IF_propDstIdx_1_1_lat_0_whas__136_THEN_propDst_ETC___d1139;
endcase
end
always@(x__h59168 or n__read_id__h59354 or n__read_id__h59439)
begin
case (x__h59168)
1'd0: x__h59482 = n__read_id__h59354;
1'd1: x__h59482 = n__read_id__h59439;
endcase
end
always@(x__h59168 or n__read_child__h59355 or n__read_child__h59440)
begin
case (x__h59168)
1'd0: x__h59489 = n__read_child__h59355;
1'd1: x__h59489 = n__read_child__h59440;
endcase
end
always@(x__h59168 or
propDstData_0_dummy2_1_read__051_AND_IF_propDs_ETC___d1087 or
propDstData_1_dummy2_1_read__056_AND_IF_propDs_ETC___d1091)
begin
case (x__h59168)
1'd0:
CASE_x9168_0_propDstData_0_dummy2_1_read__051__ETC__q12 =
propDstData_0_dummy2_1_read__051_AND_IF_propDs_ETC___d1087;
1'd1:
CASE_x9168_0_propDstData_0_dummy2_1_read__051__ETC__q12 =
propDstData_1_dummy2_1_read__056_AND_IF_propDs_ETC___d1091;
endcase
end
always@(x__h59168 or
IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1067 or
IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1071)
begin
case (x__h59168)
1'd0:
CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 =
IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1067;
1'd1:
CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q13 =
IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1071;
endcase
end
always@(x__h59168 or
IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1077 or
IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1081)
begin
case (x__h59168)
1'd0:
CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 =
IF_propDstData_0_dummy2_1_read__051_THEN_IF_pr_ETC___d1077;
1'd1:
CASE_x9168_0_IF_propDstData_0_dummy2_1_read__0_ETC__q14 =
IF_propDstData_1_dummy2_1_read__056_THEN_IF_pr_ETC___d1081;
endcase
end
always@(x__h59168 or n__read_addr__h59350 or n__read_addr__h59435)
begin
case (x__h59168)
1'd0:
CASE_x9168_0_n__read_addr9350_1_n__read_addr94_ETC__q15 =
n__read_addr__h59350;
1'd1:
CASE_x9168_0_n__read_addr9350_1_n__read_addr94_ETC__q15 =
n__read_addr__h59435;
endcase
end
always@(x__h77791 or n__read_child__h77972 or n__read_child__h78051)
begin
case (x__h77791)
1'd0: x__h80207 = n__read_child__h77972;
1'd1: x__h80207 = n__read_child__h78051;
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[512:449] :
propDstData_1_0_rl[512:449];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q16 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[512:449] :
propDstData_1_1_rl[512:449];
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[448:385] :
propDstData_1_0_rl[448:385];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q17 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[448:385] :
propDstData_1_1_rl[448:385];
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[384:321] :
propDstData_1_0_rl[384:321];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q18 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[384:321] :
propDstData_1_1_rl[384:321];
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[320:257] :
propDstData_1_0_rl[320:257];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q19 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[320:257] :
propDstData_1_1_rl[320:257];
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[256:193] :
propDstData_1_0_rl[256:193];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q20 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[256:193] :
propDstData_1_1_rl[256:193];
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[192:129] :
propDstData_1_0_rl[192:129];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q21 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[192:129] :
propDstData_1_1_rl[192:129];
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[128:65] :
propDstData_1_0_rl[128:65];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q22 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[128:65] :
propDstData_1_1_rl[128:65];
endcase
end
always@(x__h77791 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[64:1] :
propDstData_1_0_rl[64:1];
1'd1:
CASE_x7791_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[64:1] :
propDstData_1_1_rl[64:1];
endcase
end
always@(x__h77791 or
propDstData_1_0_dummy2_1$Q_OUT or
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1154 or
propDstData_1_1_dummy2_1$Q_OUT or
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1192)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 =
propDstData_1_0_dummy2_1$Q_OUT ?
IF_propDstData_1_0_lat_0_whas__144_THEN_propDs_ETC___d1154 :
2'd0;
1'd1:
CASE_x7791_0_IF_propDstData_1_0_dummy2_1Q_OUT_ETC__q24 =
propDstData_1_1_dummy2_1$Q_OUT ?
IF_propDstData_1_1_lat_0_whas__182_THEN_propDs_ETC___d1192 :
2'd0;
endcase
end
always@(x__h77791 or
NOT_propDstData_1_0_dummy2_1_read__320_331_OR__ETC___d1332 or
NOT_propDstData_1_1_dummy2_1_read__322_333_OR__ETC___d1334)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 =
NOT_propDstData_1_0_dummy2_1_read__320_331_OR__ETC___d1332;
1'd1:
CASE_x7791_0_NOT_propDstData_1_0_dummy2_1_read_ETC__q25 =
NOT_propDstData_1_1_dummy2_1_read__322_333_OR__ETC___d1334;
endcase
end
always@(x__h77791 or n__read_addr__h77969 or n__read_addr__h78048)
begin
case (x__h77791)
1'd0:
CASE_x7791_0_n__read_addr7969_1_n__read_addr80_ETC__q26 =
n__read_addr__h77969;
1'd1:
CASE_x7791_0_n__read_addr7969_1_n__read_addr80_ETC__q26 =
n__read_addr__h78048;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY 74'h0AAAAAAAAAAAAAAAAAA;
enqDst_0_rl_1 <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
4'd0;
llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0;
mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_fromHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_fromHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_fromHostQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmioPlatform_fromHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_toHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_toHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_toHostQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
4'd0;
mmio_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
mmio_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
mmio_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
mmio_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
mmio_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
propDstData_0_rl_1 <= `BSV_ASSIGNMENT_DELAY 65'h0AAAAAAAAAAAAAAAA;
propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_0_rl_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_step_count <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_stop_req <= `BSV_ASSIGNMENT_DELAY 1'd0;
srcRR_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (enqDst_0_rl$EN)
enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl$D_IN;
if (enqDst_0_rl_1$EN)
enqDst_0_rl_1 <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl_1$D_IN;
if (enqDst_1_0_rl$EN)
enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_1_0_rl$D_IN;
if (llc_axi4_adapter_cfg_verbosity$EN)
llc_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_cfg_verbosity$D_IN;
if (llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
if (llc_axi4_adapter_master_xactor_crg_rd_addr_full$EN)
llc_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_rd_data_full$EN)
llc_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_rd_data_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_wr_addr_full$EN)
llc_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_wr_data_full$EN)
llc_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_wr_data_full$D_IN;
if (llc_axi4_adapter_master_xactor_crg_wr_resp_full$EN)
llc_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN;
if (llc_axi4_adapter_rg_rd_req_beat$EN)
llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_rd_req_beat$D_IN;
if (llc_axi4_adapter_rg_rd_rsp_beat$EN)
llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
if (llc_axi4_adapter_rg_wr_req_beat$EN)
llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_wr_req_beat$D_IN;
if (llc_axi4_adapter_rg_wr_rsp_beat$EN)
llc_axi4_adapter_rg_wr_rsp_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_wr_rsp_beat$D_IN;
if (mmioPlatform_cycle$EN)
mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN;
if (mmioPlatform_fromHostAddr$EN)
mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostAddr$D_IN;
if (mmioPlatform_fromHostQ_clearReq_rl$EN)
mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_clearReq_rl$D_IN;
if (mmioPlatform_fromHostQ_data_0$EN)
mmioPlatform_fromHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_data_0$D_IN;
if (mmioPlatform_fromHostQ_deqReq_rl$EN)
mmioPlatform_fromHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_deqReq_rl$D_IN;
if (mmioPlatform_fromHostQ_empty$EN)
mmioPlatform_fromHostQ_empty <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_empty$D_IN;
if (mmioPlatform_fromHostQ_enqReq_rl$EN)
mmioPlatform_fromHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_enqReq_rl$D_IN;
if (mmioPlatform_fromHostQ_full$EN)
mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_full$D_IN;
if (mmioPlatform_mtime$EN)
mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY mmioPlatform_mtime$D_IN;
if (mmioPlatform_mtimecmp_0$EN)
mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_mtimecmp_0$D_IN;
if (mmioPlatform_mtip_0$EN)
mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_mtip_0$D_IN;
if (mmioPlatform_state$EN)
mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY mmioPlatform_state$D_IN;
if (mmioPlatform_toHostAddr$EN)
mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostAddr$D_IN;
if (mmioPlatform_toHostQ_clearReq_rl$EN)
mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_clearReq_rl$D_IN;
if (mmioPlatform_toHostQ_data_0$EN)
mmioPlatform_toHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_data_0$D_IN;
if (mmioPlatform_toHostQ_deqReq_rl$EN)
mmioPlatform_toHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_deqReq_rl$D_IN;
if (mmioPlatform_toHostQ_empty$EN)
mmioPlatform_toHostQ_empty <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_empty$D_IN;
if (mmioPlatform_toHostQ_enqReq_rl$EN)
mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_enqReq_rl$D_IN;
if (mmioPlatform_toHostQ_full$EN)
mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_full$D_IN;
if (mmio_axi4_adapter_cfg_verbosity$EN)
mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_cfg_verbosity$D_IN;
if (mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
if (mmio_axi4_adapter_master_xactor_crg_rd_addr_full$EN)
mmio_axi4_adapter_master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_crg_rd_addr_full$D_IN;
if (mmio_axi4_adapter_master_xactor_crg_rd_data_full$EN)
mmio_axi4_adapter_master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_crg_rd_data_full$D_IN;
if (mmio_axi4_adapter_master_xactor_crg_wr_addr_full$EN)
mmio_axi4_adapter_master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_crg_wr_addr_full$D_IN;
if (mmio_axi4_adapter_master_xactor_crg_wr_data_full$EN)
mmio_axi4_adapter_master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_crg_wr_data_full$D_IN;
if (mmio_axi4_adapter_master_xactor_crg_wr_resp_full$EN)
mmio_axi4_adapter_master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_crg_wr_resp_full$D_IN;
if (propDstData_0_rl$EN)
propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN;
if (propDstData_0_rl_1$EN)
propDstData_0_rl_1 <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl_1$D_IN;
if (propDstData_1_0_rl$EN)
propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_0_rl$D_IN;
if (propDstData_1_1_rl$EN)
propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_1_rl$D_IN;
if (propDstData_1_rl$EN)
propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_rl$D_IN;
if (propDstIdx_0_rl$EN)
propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl$D_IN;
if (propDstIdx_0_rl_1$EN)
propDstIdx_0_rl_1 <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl_1$D_IN;
if (propDstIdx_1_0_rl$EN)
propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_0_rl$D_IN;
if (propDstIdx_1_1_rl$EN)
propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_1_rl$D_IN;
if (propDstIdx_1_rl$EN)
propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_rl$D_IN;
if (rg_step_count$EN)
rg_step_count <= `BSV_ASSIGNMENT_DELAY rg_step_count$D_IN;
if (rg_stop_req$EN)
rg_stop_req <= `BSV_ASSIGNMENT_DELAY rg_stop_req$D_IN;
if (srcRR_0$EN) srcRR_0 <= `BSV_ASSIGNMENT_DELAY srcRR_0$D_IN;
if (srcRR_1_0$EN) srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY srcRR_1_0$D_IN;
end
if (llc_axi4_adapter_master_xactor_rg_rd_addr$EN)
llc_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
if (llc_axi4_adapter_master_xactor_rg_rd_data$EN)
llc_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_rd_data$D_IN;
if (llc_axi4_adapter_master_xactor_rg_wr_addr$EN)
llc_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
if (llc_axi4_adapter_master_xactor_rg_wr_data$EN)
llc_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_wr_data$D_IN;
if (llc_axi4_adapter_master_xactor_rg_wr_resp$EN)
llc_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
if (llc_axi4_adapter_rg_cline$EN)
llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_cline$D_IN;
if (mmioPlatform_amoResp$EN)
mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN;
if (mmioPlatform_curReq$EN)
mmioPlatform_curReq <= `BSV_ASSIGNMENT_DELAY mmioPlatform_curReq$D_IN;
if (mmioPlatform_fetchedInsts_0$EN)
mmioPlatform_fetchedInsts_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fetchedInsts_0$D_IN;
if (mmioPlatform_fetchingWay$EN)
mmioPlatform_fetchingWay <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fetchingWay$D_IN;
if (mmioPlatform_instSel$EN)
mmioPlatform_instSel <= `BSV_ASSIGNMENT_DELAY mmioPlatform_instSel$D_IN;
if (mmioPlatform_reqAmofunc$EN)
mmioPlatform_reqAmofunc <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_reqAmofunc$D_IN;
if (mmioPlatform_reqBE$EN)
mmioPlatform_reqBE <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqBE$D_IN;
if (mmioPlatform_reqData$EN)
mmioPlatform_reqData <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqData$D_IN;
if (mmioPlatform_reqFunc$EN)
mmioPlatform_reqFunc <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqFunc$D_IN;
if (mmioPlatform_reqSz$EN)
mmioPlatform_reqSz <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqSz$D_IN;
if (mmioPlatform_waitLowerMSIPCRs$EN)
mmioPlatform_waitLowerMSIPCRs <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_waitLowerMSIPCRs$D_IN;
if (mmioPlatform_waitMTIPCRs$EN)
mmioPlatform_waitMTIPCRs <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_waitMTIPCRs$D_IN;
if (mmioPlatform_waitUpperMSIPCRs$EN)
mmioPlatform_waitUpperMSIPCRs <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_waitUpperMSIPCRs$D_IN;
if (mmio_axi4_adapter_master_xactor_rg_rd_addr$EN)
mmio_axi4_adapter_master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_rg_rd_addr$D_IN;
if (mmio_axi4_adapter_master_xactor_rg_rd_data$EN)
mmio_axi4_adapter_master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_rg_rd_data$D_IN;
if (mmio_axi4_adapter_master_xactor_rg_wr_addr$EN)
mmio_axi4_adapter_master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_rg_wr_addr$D_IN;
if (mmio_axi4_adapter_master_xactor_rg_wr_data$EN)
mmio_axi4_adapter_master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_rg_wr_data$D_IN;
if (mmio_axi4_adapter_master_xactor_rg_wr_resp$EN)
mmio_axi4_adapter_master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_rg_wr_resp$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
enqDst_0_rl = 74'h2AAAAAAAAAAAAAAAAAA;
enqDst_0_rl_1 = 66'h2AAAAAAAAAAAAAAAA;
enqDst_1_0_rl =
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_cfg_verbosity = 4'hA;
llc_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
llc_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0;
llc_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0;
llc_axi4_adapter_master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A;
llc_axi4_adapter_rg_cline =
512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_rg_rd_req_beat = 3'h2;
llc_axi4_adapter_rg_rd_rsp_beat = 3'h2;
llc_axi4_adapter_rg_wr_req_beat = 3'h2;
llc_axi4_adapter_rg_wr_rsp_beat = 3'h2;
mmioPlatform_amoResp = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA;
mmioPlatform_cycle = 7'h2A;
mmioPlatform_fetchedInsts_0 = 32'hAAAAAAAA;
mmioPlatform_fetchingWay = 1'h0;
mmioPlatform_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_clearReq_rl = 1'h0;
mmioPlatform_fromHostQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_deqReq_rl = 1'h0;
mmioPlatform_fromHostQ_empty = 1'h0;
mmioPlatform_fromHostQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_full = 1'h0;
mmioPlatform_instSel = 1'h0;
mmioPlatform_mtime = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_mtimecmp_0 = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_mtip_0 = 1'h0;
mmioPlatform_reqAmofunc = 4'hA;
mmioPlatform_reqBE = 8'hAA;
mmioPlatform_reqData = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_reqFunc = 6'h2A;
mmioPlatform_reqSz = 2'h2;
mmioPlatform_state = 2'h2;
mmioPlatform_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_clearReq_rl = 1'h0;
mmioPlatform_toHostQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_deqReq_rl = 1'h0;
mmioPlatform_toHostQ_empty = 1'h0;
mmioPlatform_toHostQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_full = 1'h0;
mmioPlatform_waitLowerMSIPCRs = 1'h0;
mmioPlatform_waitMTIPCRs = 1'h0;
mmioPlatform_waitUpperMSIPCRs = 1'h0;
mmio_axi4_adapter_cfg_verbosity = 4'hA;
mmio_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
mmio_axi4_adapter_master_xactor_crg_rd_addr_full = 1'h0;
mmio_axi4_adapter_master_xactor_crg_rd_data_full = 1'h0;
mmio_axi4_adapter_master_xactor_crg_wr_addr_full = 1'h0;
mmio_axi4_adapter_master_xactor_crg_wr_data_full = 1'h0;
mmio_axi4_adapter_master_xactor_crg_wr_resp_full = 1'h0;
mmio_axi4_adapter_master_xactor_rg_rd_addr =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_rg_wr_addr =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_rg_wr_resp = 6'h2A;
propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA;
propDstData_0_rl_1 = 65'h0AAAAAAAAAAAAAAAA;
propDstData_1_0_rl =
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_1_rl =
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_rl = 73'h0AAAAAAAAAAAAAAAAAA;
propDstIdx_0_rl = 1'h0;
propDstIdx_0_rl_1 = 1'h0;
propDstIdx_1_0_rl = 1'h0;
propDstIdx_1_1_rl = 1'h0;
propDstIdx_1_rl = 1'h0;
rg_step_count = 1'h0;
rg_stop_req = 1'h0;
srcRR_0 = 1'h0;
srcRR_1_0 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_start)
$display("MMIOPlatform.start: tohostAddr = 0x%0h, fromhostAddr = %0h",
start_tohostAddr,
start_fromhostAddr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_start)
$display("Proc.start: startpc = 0x%0h, tohostAddr = 0x%0h, fromhostAddr = %0h",
start_startpc,
start_tohostAddr,
start_fromhostAddr);
if (RST_N != `BSV_RESET_VALUE)
if (core_0$RDY_coreIndInv_terminate)
$display("Core %d terminated", $signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost)
$display("mmioPlatform.rl_tohost: 0x%0x (= %0d)",
mmioPlatform_toHostQ_data_0,
mmioPlatform_toHostQ_data_0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 &&
mmioPlatform_toHostQ_data_0[63:1] == 63'd0)
$display("PASS");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 &&
mmioPlatform_toHostQ_data_0[63:1] != 63'd0)
$display("FAIL %0d", failed_testnum__h140054);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h4988 = $stime;
#0;
end
v__h4982 = v__h4988 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsps ", v__h4982);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
begin
v__h5154 = $stime;
#0;
end
v__h5148 = v__h5154 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$display("%0d: MMIO_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit",
v__h5148);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
mmio_axi4_adapter_master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
!mmio_axi4_adapter_master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" Response MMIO to core: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIODataPRs { ", "valid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_rg_rd_data[66:3],
" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h5432 = $stime;
#0;
end
v__h5426 = v__h5432 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%d: MMIO_AXI4_Adapter.rl_handle_write_req: St request:",
v__h5426);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("tagged St ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h7471 = $stime;
#0;
end
v__h7465 = v__h7471 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h7465);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[71:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h3264 = $stime;
#0;
end
v__h3258 = v__h3264 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: MMIO_AXI4_Adapter.rl_handle_read_req: Ld request",
v__h3258);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("tagged Ld ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h7772 = $stime;
#0;
end
v__h7766 = v__h7772 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp", v__h7766);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
begin
v__h8263 = $stime;
#0;
end
v__h8257 = v__h8263 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$display("%0d: MMIO_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit",
v__h8257);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
begin
v__h8426 = $stime;
#0;
end
v__h8420 = v__h8426 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$display("%0d: ERROR: MMIO_AXI4_Adapter.rl_handle_non_Ld_St",
v__h8420);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[141:78]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd0)
$write("tagged Inst ",
"'h%h",
mmio_axi4_adapter_f_reqs_from_core$D_OUT[72]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0)
$write("tagged Amo ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd0)
$write("Swap");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd1)
$write("Add");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd2)
$write("Xor");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd3)
$write("And");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd4)
$write("Or");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd5)
$write("Min");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd6)
$write("Max");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd7)
$write("Minu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] == 4'd8)
$write("Maxu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[77:76] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd1 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd2 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd3 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd4 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd5 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd6 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd7 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[75:72] != 4'd8)
$write("None");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[64])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[65])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[66])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[67])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[68])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[69])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[70])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[71])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
begin
v__h111845 = $stime;
#0;
end
v__h111839 = v__h111845 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ",
v__h111839,
llc_axi4_adapter_rg_rd_rsp_beat);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610 &&
llc_axi4_adapter_master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610 &&
!llc_axi4_adapter_master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
begin
v__h112012 = $stime;
#0;
end
v__h112006 = v__h112012 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit",
v__h112006);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
llc_axi4_adapter_master_xactor_rg_rd_data[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0 &&
!llc_axi4_adapter_master_xactor_rg_rd_data[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_rg_rd_data[2:1] != 2'b0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" Response to LLC: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("MemRsMsg { ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_rg_cline[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_rg_cline[191:128], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_rg_cline[255:192], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_rg_cline[319:256], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_rg_cline[383:320], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_rg_cline[447:384], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_rg_cline[511:448], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_rd_data[66:3], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("LdMemRqId { ", "refill: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610 &&
llc_axi4_adapter_f_pending_reads$D_OUT[4])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610 &&
!llc_axi4_adapter_f_pending_reads$D_OUT[4])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "mshrIdx: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
begin
v__h114115 = $stime;
#0;
end
v__h114109 = v__h114115 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:",
v__h114109);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("WbMemRs { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[639:576]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[512])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[512])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[513])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[513])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[514])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[514])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[515])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[515])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[516])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[516])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[517])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[517])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[518])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[518])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[519])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[519])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[520])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[520])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[521])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[521])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[522])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[522])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[523])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[523])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[524])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[524])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[525])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[525])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[526])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[526])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[527])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[527])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[528])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[528])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[529])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[529])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[530])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[530])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[531])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[531])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[532])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[532])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[533])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[533])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[534])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[534])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[535])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[535])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[536])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[536])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[537])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[537])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[538])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[538])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[539])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[539])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[540])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[540])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[541])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[541])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[542])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[542])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[543])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[543])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[544])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[544])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[545])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[545])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[546])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[546])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[547])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[547])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[548])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[548])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[549])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[549])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[550])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[550])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[551])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[551])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[552])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[552])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[553])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[553])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[554])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[554])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[555])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[555])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[556])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[556])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[557])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[557])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[558])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[558])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[559])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[559])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[560])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[560])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[561])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[561])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[562])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[562])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[563])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[563])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[564])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[564])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[565])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[565])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[566])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[566])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[567])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[567])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[568])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[568])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[569])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[569])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[570])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[570])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[571])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[571])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[572])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[572])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[573])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[573])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[574])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[574])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[575])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[575])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[63:0], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[191:128], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[255:192], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[319:256], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[383:320], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[447:384], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[511:448], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h131461 = $stime;
#0;
end
v__h131455 = v__h131461 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h131455);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", mem_req_wr_addr_awaddr__h125370);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("AXI4_Wr_Data { ", "wid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", data64__h125285);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", strb8__h125286);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
begin
v__h111226 = $stime;
#0;
end
v__h111220 = v__h111226 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d",
v__h111220,
llc_axi4_adapter_rg_rd_req_beat);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("LdMemRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[68:5]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(", ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("LdMemRqId { ", "refill: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0 &&
llc$to_mem_toM_first[4])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0 &&
!llc$to_mem_toM_first[4])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(", ", "mshrIdx: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[3:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", mem_req_rd_addr_araddr__h111446);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
begin
v__h138156 = $stime;
#0;
end
v__h138150 = v__h138156 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: beat %0d ",
v__h138150,
llc_axi4_adapter_rg_wr_rsp_beat);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
NOT_llc_axi4_adapter_cfg_verbosity_read__593_U_ETC___d1610)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
begin
v__h138664 = $stime;
#0;
end
v__h138658 = v__h138664 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit",
v__h138658);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", llc_axi4_adapter_master_xactor_rg_wr_resp[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_rg_wr_resp[1:0] != 2'b0)
$finish(32'd1);
end
// synopsys translate_on
endmodule // mkProc
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