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72175d87dbf736e56e5702f5e57f65824a9ab5ab
Toooba/src_SSITH_P3/Verilog_RTL/mkRobRowSynth.v
rsnikhil 53aacff7c5 Changes to support 'C' extension (compressed instructions). Details follow. 
>----------------
Status and outlook:

    For RV64GC, out of 229 standard ISA tests, 202 PASS, 27 FAIL.
    Below is a list of current failures, current diagnoses, and outlook.

    'C' instructions:
        rv64uc-v-rvc

        Diagnosis: error in saved regs during instruction page fault
            when a 32-bit instruction straddles a page boundary and
            the second 16-bits encounters a page fault.

            Note: the corresponding rv64uc-p-rvc passes, containing
            the same set of tests except for the virtual-memory
            aspect, so we expect this test to pass once this issue is
            fixed.

        Outlook: Target date for fix: 2019-Apr-09 (today)

    System instructions:
        rv64mi-p-access
        rv64mi-p-csr
        rv64si-p-dirty
        rv64mi-p-illegal

        Diagnosis: we do not have accurate diagnoses yet, although
            some symptoms look similar to what we saw with earlier
            processors (these test various corner-cases of system
            instructions).

        Outlook: Target date for fix: 2019-Apr-15

    'F' and 'D' instructions
        rv64uf-p-fadd        rv64uf-v-fadd
        rv64uf-p-fcmp        rv64uf-v-fcmp
        rv64uf-p-fdiv        rv64uf-v-fdiv
        rv64uf-p-fmin        rv64uf-v-fmin

        rv64ud-p-fadd        rv64ud-v-fadd
        rv64ud-p-fcmp        rv64ud-v-fcmp
        rv64ud-p-fdiv        rv64ud-v-fdiv
        rv64ud-p-fmadd       rv64ud-v-fmadd
        rv64ud-p-fmin        rv64ud-v-fmin
        rv64ud-p-ldst        rv64ud-v-ldst
        rv64ud-p-move        rv64ud-v-move

        Diagnosis: These seem to be simulation-only errors. Simulation
            uses some quick-and-dirty floating-point "model" modules
            written by the MIT authors, which are not accurate.  All
            the errors seem to be regarding incomplete treatment of
            NaNs in the models.  These errors should not happen in
            FPGA since those use Xilinx IP modules instead.  MIT has
            been booting Linux with the Xilinx IP modules, lending
            more confidence in the FPGA version.

            The actual number of root-cause failures is likely to be
            smaller than the list.  For example, the 'fadd' test has
            four variants: {uf/ud} x {-p-/-v-}; they all likely need a
            comon fix.

        Outlook: Target date: 2019-Apr-30
            [Lower priority, since FPGA versions should be ok even now.]

>----------------
Detailed comments on file changes

New files:
    Doc/micro2018.pdf
        MIT's paper on RISCY-OOO at IEEE Micro
    src_Core/CPU/CPU_Decode_C.bsv
        Function to expand 'C' instrs to 32-bit counterparts, taken from Piccolo/Flute

Modified files:
    src_Core/CPU/Core.bsv
        Added rob_getOrig_Inst method

    src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
        Added 'orig_inst' stuff, $displays

    src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
        Mostly verbosity stuff, including printing out brief instruction trace similar to Piccolo/Flute.

    src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
        Major changes for 'C', including call to Decode_C function from Piccolo/Flute
        Pass orig_inst to downpipe.

    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        Added 'orig_inst', input from FetchStage and passed on to ROB
        Tweaked PC+4 check to accommodate 'C' instructions.

    src_Core/RISCY_OOO/procs/lib/BrPred.bsv
        Fixed 'decodeBrPred' to accommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/Exec.bsv
        Fixed 'brAddrCalc', 'getControlFlow', 'basicExec' to acommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/MemLoader.bsv
        Switched off 'verbose' by default

    src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
        Added 'C' to MISA, 'getExtensionBits'

    src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
        Added 'orig_inst' register to basic cell, and methods to set/access.

    src_Core/RISCY_OOO/procs/lib/Types.bsv
        Added typedefs for 'C' instructions
>----------------
2019-04-09 13:50:16 -04:00

1582 lines
55 KiB
Verilog
Raw Blame History

//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_write_enq O 1 const
// read_deq O 219
// RDY_read_deq O 1 const
// RDY_setLSQAtCommitNotified O 1 const
// RDY_setExecuted_deqLSQ O 1 const
// RDY_setExecuted_doFinishAlu_0_set O 1 const
// RDY_setExecuted_doFinishAlu_1_set O 1 const
// RDY_setExecuted_doFinishFpuMulDiv_0_set O 1 const
// RDY_setExecuted_doFinishMem O 1 const
// getOrigPC O 64 reg
// RDY_getOrigPC O 1 const
// getOrigPredPC O 64
// RDY_getOrigPredPC O 1 const
// getOrig_Inst O 32 reg
// RDY_getOrig_Inst O 1 const
// dependsOn_wrongSpec O 1
// RDY_dependsOn_wrongSpec O 1 const
// RDY_correctSpeculation O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// write_enq_x I 219
// setExecuted_deqLSQ_cause I 5
// setExecuted_deqLSQ_ld_killed I 3
// setExecuted_doFinishAlu_0_set_csrData I 65
// setExecuted_doFinishAlu_0_set_cf I 130
// setExecuted_doFinishAlu_1_set_csrData I 65
// setExecuted_doFinishAlu_1_set_cf I 130
// setExecuted_doFinishFpuMulDiv_0_set_fflags I 5
// setExecuted_doFinishMem_vaddr I 64
// setExecuted_doFinishMem_access_at_commit I 1
// setExecuted_doFinishMem_non_mmio_st_done I 1
// dependsOn_wrongSpec_tag I 4
// correctSpeculation_mask I 12
// EN_write_enq I 1
// EN_setLSQAtCommitNotified I 1
// EN_setExecuted_deqLSQ I 1
// EN_setExecuted_doFinishAlu_0_set I 1
// EN_setExecuted_doFinishAlu_1_set I 1
// EN_setExecuted_doFinishFpuMulDiv_0_set I 1
// EN_setExecuted_doFinishMem I 1
// EN_correctSpeculation I 1
//
// Combinational paths from inputs to outputs:
// dependsOn_wrongSpec_tag -> dependsOn_wrongSpec
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRobRowSynth(CLK,
RST_N,
write_enq_x,
EN_write_enq,
RDY_write_enq,
read_deq,
RDY_read_deq,
EN_setLSQAtCommitNotified,
RDY_setLSQAtCommitNotified,
setExecuted_deqLSQ_cause,
setExecuted_deqLSQ_ld_killed,
EN_setExecuted_deqLSQ,
RDY_setExecuted_deqLSQ,
setExecuted_doFinishAlu_0_set_csrData,
setExecuted_doFinishAlu_0_set_cf,
EN_setExecuted_doFinishAlu_0_set,
RDY_setExecuted_doFinishAlu_0_set,
setExecuted_doFinishAlu_1_set_csrData,
setExecuted_doFinishAlu_1_set_cf,
EN_setExecuted_doFinishAlu_1_set,
RDY_setExecuted_doFinishAlu_1_set,
setExecuted_doFinishFpuMulDiv_0_set_fflags,
EN_setExecuted_doFinishFpuMulDiv_0_set,
RDY_setExecuted_doFinishFpuMulDiv_0_set,
setExecuted_doFinishMem_vaddr,
setExecuted_doFinishMem_access_at_commit,
setExecuted_doFinishMem_non_mmio_st_done,
EN_setExecuted_doFinishMem,
RDY_setExecuted_doFinishMem,
getOrigPC,
RDY_getOrigPC,
getOrigPredPC,
RDY_getOrigPredPC,
getOrig_Inst,
RDY_getOrig_Inst,
dependsOn_wrongSpec_tag,
dependsOn_wrongSpec,
RDY_dependsOn_wrongSpec,
correctSpeculation_mask,
EN_correctSpeculation,
RDY_correctSpeculation);
input CLK;
input RST_N;
// action method write_enq
input [218 : 0] write_enq_x;
input EN_write_enq;
output RDY_write_enq;
// value method read_deq
output [218 : 0] read_deq;
output RDY_read_deq;
// action method setLSQAtCommitNotified
input EN_setLSQAtCommitNotified;
output RDY_setLSQAtCommitNotified;
// action method setExecuted_deqLSQ
input [4 : 0] setExecuted_deqLSQ_cause;
input [2 : 0] setExecuted_deqLSQ_ld_killed;
input EN_setExecuted_deqLSQ;
output RDY_setExecuted_deqLSQ;
// action method setExecuted_doFinishAlu_0_set
input [64 : 0] setExecuted_doFinishAlu_0_set_csrData;
input [129 : 0] setExecuted_doFinishAlu_0_set_cf;
input EN_setExecuted_doFinishAlu_0_set;
output RDY_setExecuted_doFinishAlu_0_set;
// action method setExecuted_doFinishAlu_1_set
input [64 : 0] setExecuted_doFinishAlu_1_set_csrData;
input [129 : 0] setExecuted_doFinishAlu_1_set_cf;
input EN_setExecuted_doFinishAlu_1_set;
output RDY_setExecuted_doFinishAlu_1_set;
// action method setExecuted_doFinishFpuMulDiv_0_set
input [4 : 0] setExecuted_doFinishFpuMulDiv_0_set_fflags;
input EN_setExecuted_doFinishFpuMulDiv_0_set;
output RDY_setExecuted_doFinishFpuMulDiv_0_set;
// action method setExecuted_doFinishMem
input [63 : 0] setExecuted_doFinishMem_vaddr;
input setExecuted_doFinishMem_access_at_commit;
input setExecuted_doFinishMem_non_mmio_st_done;
input EN_setExecuted_doFinishMem;
output RDY_setExecuted_doFinishMem;
// value method getOrigPC
output [63 : 0] getOrigPC;
output RDY_getOrigPC;
// value method getOrigPredPC
output [63 : 0] getOrigPredPC;
output RDY_getOrigPredPC;
// value method getOrig_Inst
output [31 : 0] getOrig_Inst;
output RDY_getOrig_Inst;
// value method dependsOn_wrongSpec
input [3 : 0] dependsOn_wrongSpec_tag;
output dependsOn_wrongSpec;
output RDY_dependsOn_wrongSpec;
// action method correctSpeculation
input [11 : 0] correctSpeculation_mask;
input EN_correctSpeculation;
output RDY_correctSpeculation;
// signals for module outputs
wire [218 : 0] read_deq;
wire [63 : 0] getOrigPC, getOrigPredPC;
wire [31 : 0] getOrig_Inst;
wire RDY_correctSpeculation,
RDY_dependsOn_wrongSpec,
RDY_getOrigPC,
RDY_getOrigPredPC,
RDY_getOrig_Inst,
RDY_read_deq,
RDY_setExecuted_deqLSQ,
RDY_setExecuted_doFinishAlu_0_set,
RDY_setExecuted_doFinishAlu_1_set,
RDY_setExecuted_doFinishFpuMulDiv_0_set,
RDY_setExecuted_doFinishMem,
RDY_setLSQAtCommitNotified,
RDY_write_enq,
dependsOn_wrongSpec;
// inlined wires
wire [65 : 0] m_ppc_vaddr_csrData_lat_0$wget,
m_ppc_vaddr_csrData_lat_1$wget,
m_ppc_vaddr_csrData_lat_2$wget,
m_ppc_vaddr_csrData_lat_3$wget;
wire [5 : 0] m_trap_lat_0$wget, m_trap_lat_2$wget;
wire m_rob_inst_state_lat_4$whas, m_trap_lat_0$whas;
// register m_claimed_phy_reg
reg m_claimed_phy_reg;
wire m_claimed_phy_reg$D_IN, m_claimed_phy_reg$EN;
// register m_csr
reg [12 : 0] m_csr;
wire [12 : 0] m_csr$D_IN;
wire m_csr$EN;
// register m_epochIncremented
reg m_epochIncremented;
wire m_epochIncremented$D_IN, m_epochIncremented$EN;
// register m_fflags_rl
reg [4 : 0] m_fflags_rl;
wire [4 : 0] m_fflags_rl$D_IN;
wire m_fflags_rl$EN;
// register m_iType
reg [4 : 0] m_iType;
wire [4 : 0] m_iType$D_IN;
wire m_iType$EN;
// register m_ldKilled_rl
reg [2 : 0] m_ldKilled_rl;
wire [2 : 0] m_ldKilled_rl$D_IN;
wire m_ldKilled_rl$EN;
// register m_lsqAtCommitNotified_rl
reg m_lsqAtCommitNotified_rl;
wire m_lsqAtCommitNotified_rl$D_IN, m_lsqAtCommitNotified_rl$EN;
// register m_lsqTag
reg [5 : 0] m_lsqTag;
wire [5 : 0] m_lsqTag$D_IN;
wire m_lsqTag$EN;
// register m_memAccessAtCommit_rl
reg m_memAccessAtCommit_rl;
wire m_memAccessAtCommit_rl$D_IN, m_memAccessAtCommit_rl$EN;
// register m_nonMMIOStDone_rl
reg m_nonMMIOStDone_rl;
wire m_nonMMIOStDone_rl$D_IN, m_nonMMIOStDone_rl$EN;
// register m_orig_inst
reg [31 : 0] m_orig_inst;
wire [31 : 0] m_orig_inst$D_IN;
wire m_orig_inst$EN;
// register m_pc
reg [63 : 0] m_pc;
wire [63 : 0] m_pc$D_IN;
wire m_pc$EN;
// register m_ppc_vaddr_csrData_rl
reg [65 : 0] m_ppc_vaddr_csrData_rl;
wire [65 : 0] m_ppc_vaddr_csrData_rl$D_IN;
wire m_ppc_vaddr_csrData_rl$EN;
// register m_rob_inst_state_rl
reg m_rob_inst_state_rl;
wire m_rob_inst_state_rl$D_IN, m_rob_inst_state_rl$EN;
// register m_spec_bits_rl
reg [11 : 0] m_spec_bits_rl;
wire [11 : 0] m_spec_bits_rl$D_IN;
wire m_spec_bits_rl$EN;
// register m_trap_rl
reg [5 : 0] m_trap_rl;
wire [5 : 0] m_trap_rl$D_IN;
wire m_trap_rl$EN;
// register m_will_dirty_fpu_state
reg m_will_dirty_fpu_state;
wire m_will_dirty_fpu_state$D_IN, m_will_dirty_fpu_state$EN;
// ports of submodule m_fflags_dummy2_0
wire m_fflags_dummy2_0$D_IN, m_fflags_dummy2_0$EN, m_fflags_dummy2_0$Q_OUT;
// ports of submodule m_fflags_dummy2_1
wire m_fflags_dummy2_1$D_IN, m_fflags_dummy2_1$EN, m_fflags_dummy2_1$Q_OUT;
// ports of submodule m_ldKilled_dummy2_0
wire m_ldKilled_dummy2_0$D_IN,
m_ldKilled_dummy2_0$EN,
m_ldKilled_dummy2_0$Q_OUT;
// ports of submodule m_ldKilled_dummy2_1
wire m_ldKilled_dummy2_1$D_IN,
m_ldKilled_dummy2_1$EN,
m_ldKilled_dummy2_1$Q_OUT;
// ports of submodule m_lsqAtCommitNotified_dummy2_0
wire m_lsqAtCommitNotified_dummy2_0$D_IN,
m_lsqAtCommitNotified_dummy2_0$EN,
m_lsqAtCommitNotified_dummy2_0$Q_OUT;
// ports of submodule m_lsqAtCommitNotified_dummy2_1
wire m_lsqAtCommitNotified_dummy2_1$D_IN,
m_lsqAtCommitNotified_dummy2_1$EN,
m_lsqAtCommitNotified_dummy2_1$Q_OUT;
// ports of submodule m_memAccessAtCommit_dummy2_0
wire m_memAccessAtCommit_dummy2_0$D_IN,
m_memAccessAtCommit_dummy2_0$EN,
m_memAccessAtCommit_dummy2_0$Q_OUT;
// ports of submodule m_memAccessAtCommit_dummy2_1
wire m_memAccessAtCommit_dummy2_1$D_IN,
m_memAccessAtCommit_dummy2_1$EN,
m_memAccessAtCommit_dummy2_1$Q_OUT;
// ports of submodule m_memAccessAtCommit_dummy2_2
wire m_memAccessAtCommit_dummy2_2$D_IN,
m_memAccessAtCommit_dummy2_2$EN,
m_memAccessAtCommit_dummy2_2$Q_OUT;
// ports of submodule m_nonMMIOStDone_dummy2_0
wire m_nonMMIOStDone_dummy2_0$D_IN,
m_nonMMIOStDone_dummy2_0$EN,
m_nonMMIOStDone_dummy2_0$Q_OUT;
// ports of submodule m_nonMMIOStDone_dummy2_1
wire m_nonMMIOStDone_dummy2_1$D_IN,
m_nonMMIOStDone_dummy2_1$EN,
m_nonMMIOStDone_dummy2_1$Q_OUT;
// ports of submodule m_ppc_vaddr_csrData_dummy2_0
wire m_ppc_vaddr_csrData_dummy2_0$D_IN,
m_ppc_vaddr_csrData_dummy2_0$EN,
m_ppc_vaddr_csrData_dummy2_0$Q_OUT;
// ports of submodule m_ppc_vaddr_csrData_dummy2_1
wire m_ppc_vaddr_csrData_dummy2_1$D_IN,
m_ppc_vaddr_csrData_dummy2_1$EN,
m_ppc_vaddr_csrData_dummy2_1$Q_OUT;
// ports of submodule m_ppc_vaddr_csrData_dummy2_2
wire m_ppc_vaddr_csrData_dummy2_2$D_IN,
m_ppc_vaddr_csrData_dummy2_2$EN,
m_ppc_vaddr_csrData_dummy2_2$Q_OUT;
// ports of submodule m_ppc_vaddr_csrData_dummy2_3
wire m_ppc_vaddr_csrData_dummy2_3$D_IN,
m_ppc_vaddr_csrData_dummy2_3$EN,
m_ppc_vaddr_csrData_dummy2_3$Q_OUT;
// ports of submodule m_rob_inst_state_dummy2_0
wire m_rob_inst_state_dummy2_0$D_IN,
m_rob_inst_state_dummy2_0$EN,
m_rob_inst_state_dummy2_0$Q_OUT;
// ports of submodule m_rob_inst_state_dummy2_1
wire m_rob_inst_state_dummy2_1$D_IN,
m_rob_inst_state_dummy2_1$EN,
m_rob_inst_state_dummy2_1$Q_OUT;
// ports of submodule m_rob_inst_state_dummy2_2
wire m_rob_inst_state_dummy2_2$D_IN,
m_rob_inst_state_dummy2_2$EN,
m_rob_inst_state_dummy2_2$Q_OUT;
// ports of submodule m_rob_inst_state_dummy2_3
wire m_rob_inst_state_dummy2_3$D_IN,
m_rob_inst_state_dummy2_3$EN,
m_rob_inst_state_dummy2_3$Q_OUT;
// ports of submodule m_rob_inst_state_dummy2_4
wire m_rob_inst_state_dummy2_4$D_IN,
m_rob_inst_state_dummy2_4$EN,
m_rob_inst_state_dummy2_4$Q_OUT;
// ports of submodule m_rob_inst_state_dummy2_5
wire m_rob_inst_state_dummy2_5$D_IN,
m_rob_inst_state_dummy2_5$EN,
m_rob_inst_state_dummy2_5$Q_OUT;
// ports of submodule m_spec_bits_dummy2_0
wire m_spec_bits_dummy2_0$D_IN,
m_spec_bits_dummy2_0$EN,
m_spec_bits_dummy2_0$Q_OUT;
// ports of submodule m_spec_bits_dummy2_1
wire m_spec_bits_dummy2_1$D_IN,
m_spec_bits_dummy2_1$EN,
m_spec_bits_dummy2_1$Q_OUT;
// ports of submodule m_spec_bits_dummy2_2
wire m_spec_bits_dummy2_2$D_IN,
m_spec_bits_dummy2_2$EN,
m_spec_bits_dummy2_2$Q_OUT;
// ports of submodule m_trap_dummy2_0
wire m_trap_dummy2_0$D_IN, m_trap_dummy2_0$EN, m_trap_dummy2_0$Q_OUT;
// ports of submodule m_trap_dummy2_1
wire m_trap_dummy2_1$D_IN, m_trap_dummy2_1$EN, m_trap_dummy2_1$Q_OUT;
// ports of submodule m_trap_dummy2_2
wire m_trap_dummy2_2$D_IN, m_trap_dummy2_2$EN, m_trap_dummy2_2$Q_OUT;
// rule scheduling signals
wire CAN_FIRE_RL_m_fflags_canon,
CAN_FIRE_RL_m_ldKilled_canon,
CAN_FIRE_RL_m_lsqAtCommitNotified_canon,
CAN_FIRE_RL_m_memAccessAtCommit_canon,
CAN_FIRE_RL_m_nonMMIOStDone_canon,
CAN_FIRE_RL_m_ppc_vaddr_csrData_canon,
CAN_FIRE_RL_m_rob_inst_state_canon,
CAN_FIRE_RL_m_setPcWires,
CAN_FIRE_RL_m_spec_bits_canon,
CAN_FIRE_RL_m_trap_canon,
CAN_FIRE_correctSpeculation,
CAN_FIRE_setExecuted_deqLSQ,
CAN_FIRE_setExecuted_doFinishAlu_0_set,
CAN_FIRE_setExecuted_doFinishAlu_1_set,
CAN_FIRE_setExecuted_doFinishFpuMulDiv_0_set,
CAN_FIRE_setExecuted_doFinishMem,
CAN_FIRE_setLSQAtCommitNotified,
CAN_FIRE_write_enq,
WILL_FIRE_RL_m_fflags_canon,
WILL_FIRE_RL_m_ldKilled_canon,
WILL_FIRE_RL_m_lsqAtCommitNotified_canon,
WILL_FIRE_RL_m_memAccessAtCommit_canon,
WILL_FIRE_RL_m_nonMMIOStDone_canon,
WILL_FIRE_RL_m_ppc_vaddr_csrData_canon,
WILL_FIRE_RL_m_rob_inst_state_canon,
WILL_FIRE_RL_m_setPcWires,
WILL_FIRE_RL_m_spec_bits_canon,
WILL_FIRE_RL_m_trap_canon,
WILL_FIRE_correctSpeculation,
WILL_FIRE_setExecuted_deqLSQ,
WILL_FIRE_setExecuted_doFinishAlu_0_set,
WILL_FIRE_setExecuted_doFinishAlu_1_set,
WILL_FIRE_setExecuted_doFinishFpuMulDiv_0_set,
WILL_FIRE_setExecuted_doFinishMem,
WILL_FIRE_setLSQAtCommitNotified,
WILL_FIRE_write_enq;
// remaining internal signals
reg [11 : 0] CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8;
reg [3 : 0] CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q1,
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q2,
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q4,
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5,
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6;
reg [1 : 0] CASE_write_enq_x_BITS_97_TO_96_0_write_enq_x_B_ETC__q7;
wire [122 : 0] m_iType_39_CONCAT_m_csr_40_BIT_12_41_CONCAT_IF_ETC___d615;
wire [104 : 0] m_claimed_phy_reg_17_CONCAT_m_trap_dummy2_0_re_ETC___d614;
wire [65 : 0] IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_8_ETC___d559;
wire [63 : 0] IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298,
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d197,
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d199;
wire [11 : 0] IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281,
bs__h29532,
sb__h29567,
upd__h16390;
wire [4 : 0] IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d154,
x_read_deq_fflags__h23257;
wire [3 : 0] IF_IF_m_trap_lat_2_whas_THEN_NOT_m_trap_lat_2__ETC___d153,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d131,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d132,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d134,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d136,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d137,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d139,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d141,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d143,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d146,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d148,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d150,
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d152;
wire [1 : 0] IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d246;
wire IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d236,
IF_m_memAccessAtCommit_lat_1_whas__51_THEN_m_m_ETC___d257,
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d177,
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d186,
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d179,
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d188,
IF_m_rob_inst_state_lat_3_whas__12_THEN_m_rob__ETC___d224,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d102,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d109,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d116,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d46,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d53,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d67,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d74,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d81,
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d95,
NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293,
m_rob_inst_state_dummy2_0_read__65_AND_m_rob_i_ETC___d576;
// action method write_enq
assign RDY_write_enq = 1'd1 ;
assign CAN_FIRE_write_enq = 1'd1 ;
assign WILL_FIRE_write_enq = EN_write_enq ;
// value method read_deq
assign read_deq =
{ m_pc,
m_orig_inst,
m_iType_39_CONCAT_m_csr_40_BIT_12_41_CONCAT_IF_ETC___d615 } ;
assign RDY_read_deq = 1'd1 ;
// action method setLSQAtCommitNotified
assign RDY_setLSQAtCommitNotified = 1'd1 ;
assign CAN_FIRE_setLSQAtCommitNotified = 1'd1 ;
assign WILL_FIRE_setLSQAtCommitNotified = EN_setLSQAtCommitNotified ;
// action method setExecuted_deqLSQ
assign RDY_setExecuted_deqLSQ = 1'd1 ;
assign CAN_FIRE_setExecuted_deqLSQ = 1'd1 ;
assign WILL_FIRE_setExecuted_deqLSQ = EN_setExecuted_deqLSQ ;
// action method setExecuted_doFinishAlu_0_set
assign RDY_setExecuted_doFinishAlu_0_set = 1'd1 ;
assign CAN_FIRE_setExecuted_doFinishAlu_0_set = 1'd1 ;
assign WILL_FIRE_setExecuted_doFinishAlu_0_set =
EN_setExecuted_doFinishAlu_0_set ;
// action method setExecuted_doFinishAlu_1_set
assign RDY_setExecuted_doFinishAlu_1_set = 1'd1 ;
assign CAN_FIRE_setExecuted_doFinishAlu_1_set = 1'd1 ;
assign WILL_FIRE_setExecuted_doFinishAlu_1_set =
EN_setExecuted_doFinishAlu_1_set ;
// action method setExecuted_doFinishFpuMulDiv_0_set
assign RDY_setExecuted_doFinishFpuMulDiv_0_set = 1'd1 ;
assign CAN_FIRE_setExecuted_doFinishFpuMulDiv_0_set = 1'd1 ;
assign WILL_FIRE_setExecuted_doFinishFpuMulDiv_0_set =
EN_setExecuted_doFinishFpuMulDiv_0_set ;
// action method setExecuted_doFinishMem
assign RDY_setExecuted_doFinishMem = 1'd1 ;
assign CAN_FIRE_setExecuted_doFinishMem = 1'd1 ;
assign WILL_FIRE_setExecuted_doFinishMem = EN_setExecuted_doFinishMem ;
// value method getOrigPC
assign getOrigPC = m_pc ;
assign RDY_getOrigPC = 1'd1 ;
// value method getOrigPredPC
assign getOrigPredPC =
(NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293 ||
m_ppc_vaddr_csrData_rl[65:64] == 2'd0) ?
IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298 :
64'd0 ;
assign RDY_getOrigPredPC = 1'd1 ;
// value method getOrig_Inst
assign getOrig_Inst = m_orig_inst ;
assign RDY_getOrig_Inst = 1'd1 ;
// value method dependsOn_wrongSpec
assign dependsOn_wrongSpec = bs__h29532[dependsOn_wrongSpec_tag] ;
assign RDY_dependsOn_wrongSpec = 1'd1 ;
// action method correctSpeculation
assign RDY_correctSpeculation = 1'd1 ;
assign CAN_FIRE_correctSpeculation = 1'd1 ;
assign WILL_FIRE_correctSpeculation = EN_correctSpeculation ;
// submodule m_fflags_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_fflags_dummy2_0(.CLK(CLK),
.D_IN(m_fflags_dummy2_0$D_IN),
.EN(m_fflags_dummy2_0$EN),
.Q_OUT(m_fflags_dummy2_0$Q_OUT));
// submodule m_fflags_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_fflags_dummy2_1(.CLK(CLK),
.D_IN(m_fflags_dummy2_1$D_IN),
.EN(m_fflags_dummy2_1$EN),
.Q_OUT(m_fflags_dummy2_1$Q_OUT));
// submodule m_ldKilled_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_ldKilled_dummy2_0(.CLK(CLK),
.D_IN(m_ldKilled_dummy2_0$D_IN),
.EN(m_ldKilled_dummy2_0$EN),
.Q_OUT(m_ldKilled_dummy2_0$Q_OUT));
// submodule m_ldKilled_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_ldKilled_dummy2_1(.CLK(CLK),
.D_IN(m_ldKilled_dummy2_1$D_IN),
.EN(m_ldKilled_dummy2_1$EN),
.Q_OUT(m_ldKilled_dummy2_1$Q_OUT));
// submodule m_lsqAtCommitNotified_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_lsqAtCommitNotified_dummy2_0(.CLK(CLK),
.D_IN(m_lsqAtCommitNotified_dummy2_0$D_IN),
.EN(m_lsqAtCommitNotified_dummy2_0$EN),
.Q_OUT(m_lsqAtCommitNotified_dummy2_0$Q_OUT));
// submodule m_lsqAtCommitNotified_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_lsqAtCommitNotified_dummy2_1(.CLK(CLK),
.D_IN(m_lsqAtCommitNotified_dummy2_1$D_IN),
.EN(m_lsqAtCommitNotified_dummy2_1$EN),
.Q_OUT(m_lsqAtCommitNotified_dummy2_1$Q_OUT));
// submodule m_memAccessAtCommit_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_memAccessAtCommit_dummy2_0(.CLK(CLK),
.D_IN(m_memAccessAtCommit_dummy2_0$D_IN),
.EN(m_memAccessAtCommit_dummy2_0$EN),
.Q_OUT(m_memAccessAtCommit_dummy2_0$Q_OUT));
// submodule m_memAccessAtCommit_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_memAccessAtCommit_dummy2_1(.CLK(CLK),
.D_IN(m_memAccessAtCommit_dummy2_1$D_IN),
.EN(m_memAccessAtCommit_dummy2_1$EN),
.Q_OUT(m_memAccessAtCommit_dummy2_1$Q_OUT));
// submodule m_memAccessAtCommit_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_memAccessAtCommit_dummy2_2(.CLK(CLK),
.D_IN(m_memAccessAtCommit_dummy2_2$D_IN),
.EN(m_memAccessAtCommit_dummy2_2$EN),
.Q_OUT(m_memAccessAtCommit_dummy2_2$Q_OUT));
// submodule m_nonMMIOStDone_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_nonMMIOStDone_dummy2_0(.CLK(CLK),
.D_IN(m_nonMMIOStDone_dummy2_0$D_IN),
.EN(m_nonMMIOStDone_dummy2_0$EN),
.Q_OUT(m_nonMMIOStDone_dummy2_0$Q_OUT));
// submodule m_nonMMIOStDone_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_nonMMIOStDone_dummy2_1(.CLK(CLK),
.D_IN(m_nonMMIOStDone_dummy2_1$D_IN),
.EN(m_nonMMIOStDone_dummy2_1$EN),
.Q_OUT(m_nonMMIOStDone_dummy2_1$Q_OUT));
// submodule m_ppc_vaddr_csrData_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) m_ppc_vaddr_csrData_dummy2_0(.CLK(CLK),
.D_IN(m_ppc_vaddr_csrData_dummy2_0$D_IN),
.EN(m_ppc_vaddr_csrData_dummy2_0$EN),
.Q_OUT(m_ppc_vaddr_csrData_dummy2_0$Q_OUT));
// submodule m_ppc_vaddr_csrData_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) m_ppc_vaddr_csrData_dummy2_1(.CLK(CLK),
.D_IN(m_ppc_vaddr_csrData_dummy2_1$D_IN),
.EN(m_ppc_vaddr_csrData_dummy2_1$EN),
.Q_OUT(m_ppc_vaddr_csrData_dummy2_1$Q_OUT));
// submodule m_ppc_vaddr_csrData_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) m_ppc_vaddr_csrData_dummy2_2(.CLK(CLK),
.D_IN(m_ppc_vaddr_csrData_dummy2_2$D_IN),
.EN(m_ppc_vaddr_csrData_dummy2_2$EN),
.Q_OUT(m_ppc_vaddr_csrData_dummy2_2$Q_OUT));
// submodule m_ppc_vaddr_csrData_dummy2_3
RevertReg #(.width(32'd1),
.init(1'd1)) m_ppc_vaddr_csrData_dummy2_3(.CLK(CLK),
.D_IN(m_ppc_vaddr_csrData_dummy2_3$D_IN),
.EN(m_ppc_vaddr_csrData_dummy2_3$EN),
.Q_OUT(m_ppc_vaddr_csrData_dummy2_3$Q_OUT));
// submodule m_rob_inst_state_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_rob_inst_state_dummy2_0(.CLK(CLK),
.D_IN(m_rob_inst_state_dummy2_0$D_IN),
.EN(m_rob_inst_state_dummy2_0$EN),
.Q_OUT(m_rob_inst_state_dummy2_0$Q_OUT));
// submodule m_rob_inst_state_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_rob_inst_state_dummy2_1(.CLK(CLK),
.D_IN(m_rob_inst_state_dummy2_1$D_IN),
.EN(m_rob_inst_state_dummy2_1$EN),
.Q_OUT(m_rob_inst_state_dummy2_1$Q_OUT));
// submodule m_rob_inst_state_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_rob_inst_state_dummy2_2(.CLK(CLK),
.D_IN(m_rob_inst_state_dummy2_2$D_IN),
.EN(m_rob_inst_state_dummy2_2$EN),
.Q_OUT(m_rob_inst_state_dummy2_2$Q_OUT));
// submodule m_rob_inst_state_dummy2_3
RevertReg #(.width(32'd1), .init(1'd1)) m_rob_inst_state_dummy2_3(.CLK(CLK),
.D_IN(m_rob_inst_state_dummy2_3$D_IN),
.EN(m_rob_inst_state_dummy2_3$EN),
.Q_OUT(m_rob_inst_state_dummy2_3$Q_OUT));
// submodule m_rob_inst_state_dummy2_4
RevertReg #(.width(32'd1), .init(1'd1)) m_rob_inst_state_dummy2_4(.CLK(CLK),
.D_IN(m_rob_inst_state_dummy2_4$D_IN),
.EN(m_rob_inst_state_dummy2_4$EN),
.Q_OUT(m_rob_inst_state_dummy2_4$Q_OUT));
// submodule m_rob_inst_state_dummy2_5
RevertReg #(.width(32'd1), .init(1'd1)) m_rob_inst_state_dummy2_5(.CLK(CLK),
.D_IN(m_rob_inst_state_dummy2_5$D_IN),
.EN(m_rob_inst_state_dummy2_5$EN),
.Q_OUT(m_rob_inst_state_dummy2_5$Q_OUT));
// submodule m_spec_bits_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_spec_bits_dummy2_0(.CLK(CLK),
.D_IN(m_spec_bits_dummy2_0$D_IN),
.EN(m_spec_bits_dummy2_0$EN),
.Q_OUT(m_spec_bits_dummy2_0$Q_OUT));
// submodule m_spec_bits_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_spec_bits_dummy2_1(.CLK(CLK),
.D_IN(m_spec_bits_dummy2_1$D_IN),
.EN(m_spec_bits_dummy2_1$EN),
.Q_OUT(m_spec_bits_dummy2_1$Q_OUT));
// submodule m_spec_bits_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_spec_bits_dummy2_2(.CLK(CLK),
.D_IN(m_spec_bits_dummy2_2$D_IN),
.EN(m_spec_bits_dummy2_2$EN),
.Q_OUT(m_spec_bits_dummy2_2$Q_OUT));
// submodule m_trap_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) m_trap_dummy2_0(.CLK(CLK),
.D_IN(m_trap_dummy2_0$D_IN),
.EN(m_trap_dummy2_0$EN),
.Q_OUT(m_trap_dummy2_0$Q_OUT));
// submodule m_trap_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) m_trap_dummy2_1(.CLK(CLK),
.D_IN(m_trap_dummy2_1$D_IN),
.EN(m_trap_dummy2_1$EN),
.Q_OUT(m_trap_dummy2_1$Q_OUT));
// submodule m_trap_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) m_trap_dummy2_2(.CLK(CLK),
.D_IN(m_trap_dummy2_2$D_IN),
.EN(m_trap_dummy2_2$EN),
.Q_OUT(m_trap_dummy2_2$Q_OUT));
// rule RL_m_setPcWires
assign CAN_FIRE_RL_m_setPcWires = 1'd1 ;
assign WILL_FIRE_RL_m_setPcWires = 1'd1 ;
// rule RL_m_trap_canon
assign CAN_FIRE_RL_m_trap_canon = 1'd1 ;
assign WILL_FIRE_RL_m_trap_canon = 1'd1 ;
// rule RL_m_ppc_vaddr_csrData_canon
assign CAN_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
assign WILL_FIRE_RL_m_ppc_vaddr_csrData_canon = 1'd1 ;
// rule RL_m_fflags_canon
assign CAN_FIRE_RL_m_fflags_canon = 1'd1 ;
assign WILL_FIRE_RL_m_fflags_canon = 1'd1 ;
// rule RL_m_rob_inst_state_canon
assign CAN_FIRE_RL_m_rob_inst_state_canon = 1'd1 ;
assign WILL_FIRE_RL_m_rob_inst_state_canon = 1'd1 ;
// rule RL_m_ldKilled_canon
assign CAN_FIRE_RL_m_ldKilled_canon = 1'd1 ;
assign WILL_FIRE_RL_m_ldKilled_canon = 1'd1 ;
// rule RL_m_memAccessAtCommit_canon
assign CAN_FIRE_RL_m_memAccessAtCommit_canon = 1'd1 ;
assign WILL_FIRE_RL_m_memAccessAtCommit_canon = 1'd1 ;
// rule RL_m_lsqAtCommitNotified_canon
assign CAN_FIRE_RL_m_lsqAtCommitNotified_canon = 1'd1 ;
assign WILL_FIRE_RL_m_lsqAtCommitNotified_canon = 1'd1 ;
// rule RL_m_nonMMIOStDone_canon
assign CAN_FIRE_RL_m_nonMMIOStDone_canon = 1'd1 ;
assign WILL_FIRE_RL_m_nonMMIOStDone_canon = 1'd1 ;
// rule RL_m_spec_bits_canon
assign CAN_FIRE_RL_m_spec_bits_canon = 1'd1 ;
assign WILL_FIRE_RL_m_spec_bits_canon = 1'd1 ;
// inlined wires
assign m_trap_lat_0$wget =
{ 2'd2,
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q4 } ;
assign m_trap_lat_0$whas =
EN_setExecuted_deqLSQ && setExecuted_deqLSQ_cause[4] ;
assign m_trap_lat_2$wget =
{ write_enq_x[103:102],
write_enq_x[102] ?
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5 :
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6 } ;
assign m_ppc_vaddr_csrData_lat_0$wget =
setExecuted_doFinishAlu_0_set_csrData[64] ?
{ 2'd2, setExecuted_doFinishAlu_0_set_csrData[63:0] } :
{ 2'd0, setExecuted_doFinishAlu_0_set_cf[65:2] } ;
assign m_ppc_vaddr_csrData_lat_1$wget =
setExecuted_doFinishAlu_1_set_csrData[64] ?
{ 2'd2, setExecuted_doFinishAlu_1_set_csrData[63:0] } :
{ 2'd0, setExecuted_doFinishAlu_1_set_cf[65:2] } ;
assign m_ppc_vaddr_csrData_lat_2$wget =
{ 2'd1, setExecuted_doFinishMem_vaddr } ;
assign m_ppc_vaddr_csrData_lat_3$wget =
{ CASE_write_enq_x_BITS_97_TO_96_0_write_enq_x_B_ETC__q7,
write_enq_x[95:32] } ;
assign m_rob_inst_state_lat_4$whas =
EN_setExecuted_doFinishMem &&
setExecuted_doFinishMem_non_mmio_st_done ;
// register m_claimed_phy_reg
assign m_claimed_phy_reg$D_IN = write_enq_x[104] ;
assign m_claimed_phy_reg$EN = EN_write_enq ;
// register m_csr
assign m_csr$D_IN =
{ write_enq_x[117],
CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8 } ;
assign m_csr$EN = EN_write_enq ;
// register m_epochIncremented
assign m_epochIncremented$D_IN = write_enq_x[12] ;
assign m_epochIncremented$EN = EN_write_enq ;
// register m_fflags_rl
assign m_fflags_rl$D_IN =
EN_write_enq ?
write_enq_x[31:27] :
(EN_setExecuted_doFinishFpuMulDiv_0_set ?
setExecuted_doFinishFpuMulDiv_0_set_fflags :
m_fflags_rl) ;
assign m_fflags_rl$EN = 1'd1 ;
// register m_iType
assign m_iType$D_IN = write_enq_x[122:118] ;
assign m_iType$EN = EN_write_enq ;
// register m_ldKilled_rl
assign m_ldKilled_rl$D_IN =
{ IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d236,
IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d246 } ;
assign m_ldKilled_rl$EN = 1'd1 ;
// register m_lsqAtCommitNotified_rl
assign m_lsqAtCommitNotified_rl$D_IN =
!EN_write_enq &&
(EN_setLSQAtCommitNotified || m_lsqAtCommitNotified_rl) ;
assign m_lsqAtCommitNotified_rl$EN = 1'd1 ;
// register m_lsqTag
assign m_lsqTag$D_IN = write_enq_x[24:19] ;
assign m_lsqTag$EN = EN_write_enq ;
// register m_memAccessAtCommit_rl
assign m_memAccessAtCommit_rl$D_IN =
IF_m_memAccessAtCommit_lat_1_whas__51_THEN_m_m_ETC___d257 ;
assign m_memAccessAtCommit_rl$EN = 1'd1 ;
// register m_nonMMIOStDone_rl
assign m_nonMMIOStDone_rl$D_IN =
!EN_write_enq &&
(EN_setExecuted_doFinishMem ?
setExecuted_doFinishMem_non_mmio_st_done :
m_nonMMIOStDone_rl) ;
assign m_nonMMIOStDone_rl$EN = 1'd1 ;
// register m_orig_inst
assign m_orig_inst$D_IN = write_enq_x[154:123] ;
assign m_orig_inst$EN = EN_write_enq ;
// register m_pc
assign m_pc$D_IN = write_enq_x[218:155] ;
assign m_pc$EN = EN_write_enq ;
// register m_ppc_vaddr_csrData_rl
assign m_ppc_vaddr_csrData_rl$D_IN =
{ IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d179 ?
2'd0 :
(IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d188 ?
2'd1 :
2'd2),
IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d199 } ;
assign m_ppc_vaddr_csrData_rl$EN = 1'd1 ;
// register m_rob_inst_state_rl
assign m_rob_inst_state_rl$D_IN =
EN_write_enq ?
write_enq_x[25] :
m_rob_inst_state_lat_4$whas ||
IF_m_rob_inst_state_lat_3_whas__12_THEN_m_rob__ETC___d224 ;
assign m_rob_inst_state_rl$EN = 1'd1 ;
// register m_spec_bits_rl
assign m_spec_bits_rl$D_IN =
EN_correctSpeculation ?
upd__h16390 :
IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281 ;
assign m_spec_bits_rl$EN = 1'd1 ;
// register m_trap_rl
assign m_trap_rl$D_IN =
{ EN_write_enq ?
m_trap_lat_2$wget[5] :
(m_trap_lat_0$whas ? m_trap_lat_0$wget[5] : m_trap_rl[5]),
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d154 } ;
assign m_trap_rl$EN = 1'd1 ;
// register m_will_dirty_fpu_state
assign m_will_dirty_fpu_state$D_IN = write_enq_x[26] ;
assign m_will_dirty_fpu_state$EN = EN_write_enq ;
// submodule m_fflags_dummy2_0
assign m_fflags_dummy2_0$D_IN = 1'd1 ;
assign m_fflags_dummy2_0$EN = EN_setExecuted_doFinishFpuMulDiv_0_set ;
// submodule m_fflags_dummy2_1
assign m_fflags_dummy2_1$D_IN = 1'd1 ;
assign m_fflags_dummy2_1$EN = EN_write_enq ;
// submodule m_ldKilled_dummy2_0
assign m_ldKilled_dummy2_0$D_IN = 1'd1 ;
assign m_ldKilled_dummy2_0$EN = EN_setExecuted_deqLSQ ;
// submodule m_ldKilled_dummy2_1
assign m_ldKilled_dummy2_1$D_IN = 1'd1 ;
assign m_ldKilled_dummy2_1$EN = EN_write_enq ;
// submodule m_lsqAtCommitNotified_dummy2_0
assign m_lsqAtCommitNotified_dummy2_0$D_IN = 1'd1 ;
assign m_lsqAtCommitNotified_dummy2_0$EN = EN_setLSQAtCommitNotified ;
// submodule m_lsqAtCommitNotified_dummy2_1
assign m_lsqAtCommitNotified_dummy2_1$D_IN = 1'd1 ;
assign m_lsqAtCommitNotified_dummy2_1$EN = EN_write_enq ;
// submodule m_memAccessAtCommit_dummy2_0
assign m_memAccessAtCommit_dummy2_0$D_IN = 1'd1 ;
assign m_memAccessAtCommit_dummy2_0$EN = EN_setExecuted_doFinishMem ;
// submodule m_memAccessAtCommit_dummy2_1
assign m_memAccessAtCommit_dummy2_1$D_IN = 1'd1 ;
assign m_memAccessAtCommit_dummy2_1$EN = EN_write_enq ;
// submodule m_memAccessAtCommit_dummy2_2
assign m_memAccessAtCommit_dummy2_2$D_IN = 1'b0 ;
assign m_memAccessAtCommit_dummy2_2$EN = 1'b0 ;
// submodule m_nonMMIOStDone_dummy2_0
assign m_nonMMIOStDone_dummy2_0$D_IN = 1'd1 ;
assign m_nonMMIOStDone_dummy2_0$EN = EN_setExecuted_doFinishMem ;
// submodule m_nonMMIOStDone_dummy2_1
assign m_nonMMIOStDone_dummy2_1$D_IN = 1'd1 ;
assign m_nonMMIOStDone_dummy2_1$EN = EN_write_enq ;
// submodule m_ppc_vaddr_csrData_dummy2_0
assign m_ppc_vaddr_csrData_dummy2_0$D_IN = 1'd1 ;
assign m_ppc_vaddr_csrData_dummy2_0$EN = EN_setExecuted_doFinishAlu_0_set ;
// submodule m_ppc_vaddr_csrData_dummy2_1
assign m_ppc_vaddr_csrData_dummy2_1$D_IN = 1'd1 ;
assign m_ppc_vaddr_csrData_dummy2_1$EN = EN_setExecuted_doFinishAlu_1_set ;
// submodule m_ppc_vaddr_csrData_dummy2_2
assign m_ppc_vaddr_csrData_dummy2_2$D_IN = 1'd1 ;
assign m_ppc_vaddr_csrData_dummy2_2$EN = EN_setExecuted_doFinishMem ;
// submodule m_ppc_vaddr_csrData_dummy2_3
assign m_ppc_vaddr_csrData_dummy2_3$D_IN = 1'd1 ;
assign m_ppc_vaddr_csrData_dummy2_3$EN = EN_write_enq ;
// submodule m_rob_inst_state_dummy2_0
assign m_rob_inst_state_dummy2_0$D_IN = 1'd1 ;
assign m_rob_inst_state_dummy2_0$EN = EN_setExecuted_doFinishAlu_0_set ;
// submodule m_rob_inst_state_dummy2_1
assign m_rob_inst_state_dummy2_1$D_IN = 1'd1 ;
assign m_rob_inst_state_dummy2_1$EN = EN_setExecuted_doFinishAlu_1_set ;
// submodule m_rob_inst_state_dummy2_2
assign m_rob_inst_state_dummy2_2$D_IN = 1'd1 ;
assign m_rob_inst_state_dummy2_2$EN =
EN_setExecuted_doFinishFpuMulDiv_0_set ;
// submodule m_rob_inst_state_dummy2_3
assign m_rob_inst_state_dummy2_3$D_IN = 1'd1 ;
assign m_rob_inst_state_dummy2_3$EN = EN_setExecuted_deqLSQ ;
// submodule m_rob_inst_state_dummy2_4
assign m_rob_inst_state_dummy2_4$D_IN = 1'd1 ;
assign m_rob_inst_state_dummy2_4$EN = m_rob_inst_state_lat_4$whas ;
// submodule m_rob_inst_state_dummy2_5
assign m_rob_inst_state_dummy2_5$D_IN = 1'd1 ;
assign m_rob_inst_state_dummy2_5$EN = EN_write_enq ;
// submodule m_spec_bits_dummy2_0
assign m_spec_bits_dummy2_0$D_IN = 1'b0 ;
assign m_spec_bits_dummy2_0$EN = 1'b0 ;
// submodule m_spec_bits_dummy2_1
assign m_spec_bits_dummy2_1$D_IN = 1'd1 ;
assign m_spec_bits_dummy2_1$EN = EN_write_enq ;
// submodule m_spec_bits_dummy2_2
assign m_spec_bits_dummy2_2$D_IN = 1'd1 ;
assign m_spec_bits_dummy2_2$EN = EN_correctSpeculation ;
// submodule m_trap_dummy2_0
assign m_trap_dummy2_0$D_IN = 1'd1 ;
assign m_trap_dummy2_0$EN = m_trap_lat_0$whas ;
// submodule m_trap_dummy2_1
assign m_trap_dummy2_1$D_IN = 1'b0 ;
assign m_trap_dummy2_1$EN = 1'b0 ;
// submodule m_trap_dummy2_2
assign m_trap_dummy2_2$D_IN = 1'd1 ;
assign m_trap_dummy2_2$EN = EN_write_enq ;
// remaining internal signals
assign IF_IF_m_trap_lat_2_whas_THEN_NOT_m_trap_lat_2__ETC___d153 =
(EN_write_enq ?
!m_trap_lat_2$wget[4] :
(m_trap_lat_0$whas ? !m_trap_lat_0$wget[4] : !m_trap_rl[4])) ?
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d143 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d152 ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d131 =
(EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd13 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd13 :
m_trap_rl[3:0] == 4'd13)) ?
4'd13 :
4'd15 ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d132 =
(EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd12 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd12 :
m_trap_rl[3:0] == 4'd12)) ?
4'd12 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d131 ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d134 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d109 ?
4'd9 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d116 ?
4'd11 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d132) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d136 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d95 ?
4'd7 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d102 ?
4'd8 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d134) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d137 =
(EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd6 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd6 :
m_trap_rl[3:0] == 4'd6)) ?
4'd6 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d136 ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d139 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d74 ?
4'd4 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d81 ?
4'd5 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d137) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d141 =
(EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd2 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd2 :
m_trap_rl[3:0] == 4'd2)) ?
4'd2 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d67 ?
4'd3 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d139) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d143 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d46 ?
4'd0 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d53 ?
4'd1 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d141) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d146 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d102 ?
4'd8 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d109 ?
4'd9 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d116 ?
4'd11 :
4'd14)) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d148 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d81 ?
4'd5 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d95 ?
4'd7 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d146) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d150 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d67 ?
4'd3 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d74 ?
4'd4 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d148) ;
assign IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d152 =
IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d46 ?
4'd0 :
(IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d53 ?
4'd1 :
IF_IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_ETC___d150) ;
assign IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_8_ETC___d559 =
(NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293 ||
m_ppc_vaddr_csrData_rl[65:64] == 2'd0) ?
{ 2'd0,
IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298 } :
{ (m_ppc_vaddr_csrData_rl[65:64] == 2'd1) ?
m_ppc_vaddr_csrData_rl[65:64] :
2'd2,
m_ppc_vaddr_csrData_rl[63:0] } ;
assign IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d236 =
!EN_write_enq &&
(EN_setExecuted_deqLSQ ?
setExecuted_deqLSQ_ld_killed[2] :
m_ldKilled_rl[2]) ;
assign IF_m_ldKilled_lat_1_whas__27_THEN_m_ldKilled_l_ETC___d246 =
EN_write_enq ?
2'b10 :
(EN_setExecuted_deqLSQ ?
setExecuted_deqLSQ_ld_killed[1:0] :
m_ldKilled_rl[1:0]) ;
assign IF_m_memAccessAtCommit_lat_1_whas__51_THEN_m_m_ETC___d257 =
EN_write_enq ?
write_enq_x[122:118] == 5'd14 :
(EN_setExecuted_doFinishMem ?
setExecuted_doFinishMem_access_at_commit :
m_memAccessAtCommit_rl) ;
assign IF_m_ppc_vaddr_csrData_dummy2_0_read__83_AND_m_ETC___d298 =
(m_ppc_vaddr_csrData_dummy2_0$Q_OUT &&
m_ppc_vaddr_csrData_dummy2_1$Q_OUT &&
m_ppc_vaddr_csrData_dummy2_2$Q_OUT &&
m_ppc_vaddr_csrData_dummy2_3$Q_OUT) ?
m_ppc_vaddr_csrData_rl[63:0] :
64'd0 ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d177 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[65:64] == 2'd0 :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[65:64] == 2'd0 :
m_ppc_vaddr_csrData_rl[65:64] == 2'd0) ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d186 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[65:64] == 2'd1 :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[65:64] == 2'd1 :
m_ppc_vaddr_csrData_rl[65:64] == 2'd1) ;
assign IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d197 =
EN_setExecuted_doFinishAlu_1_set ?
m_ppc_vaddr_csrData_lat_1$wget[63:0] :
(EN_setExecuted_doFinishAlu_0_set ?
m_ppc_vaddr_csrData_lat_0$wget[63:0] :
m_ppc_vaddr_csrData_rl[63:0]) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d179 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[65:64] == 2'd0 :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[65:64] == 2'd0 :
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d177) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d188 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[65:64] == 2'd1 :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[65:64] == 2'd1 :
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d186) ;
assign IF_m_ppc_vaddr_csrData_lat_3_whas__57_THEN_m_p_ETC___d199 =
EN_write_enq ?
m_ppc_vaddr_csrData_lat_3$wget[63:0] :
(EN_setExecuted_doFinishMem ?
m_ppc_vaddr_csrData_lat_2$wget[63:0] :
IF_m_ppc_vaddr_csrData_lat_1_whas__65_THEN_m_p_ETC___d197) ;
assign IF_m_rob_inst_state_lat_3_whas__12_THEN_m_rob__ETC___d224 =
EN_setExecuted_deqLSQ ||
EN_setExecuted_doFinishFpuMulDiv_0_set ||
EN_setExecuted_doFinishAlu_1_set ||
EN_setExecuted_doFinishAlu_0_set ||
m_rob_inst_state_rl ;
assign IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281 =
EN_write_enq ? write_enq_x[11:0] : m_spec_bits_rl ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d102 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd8 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd8 :
m_trap_rl[3:0] == 4'd8) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d109 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd9 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd9 :
m_trap_rl[3:0] == 4'd9) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d116 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd11 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd11 :
m_trap_rl[3:0] == 4'd11) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d154 =
{ EN_write_enq ?
m_trap_lat_2$wget[4] :
(m_trap_lat_0$whas ? m_trap_lat_0$wget[4] : m_trap_rl[4]),
IF_IF_m_trap_lat_2_whas_THEN_NOT_m_trap_lat_2__ETC___d153 } ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d46 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd0 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd0 :
m_trap_rl[3:0] == 4'd0) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d53 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd1 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd1 :
m_trap_rl[3:0] == 4'd1) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d67 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd3 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd3 :
m_trap_rl[3:0] == 4'd3) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d74 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd4 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd4 :
m_trap_rl[3:0] == 4'd4) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d81 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd5 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd5 :
m_trap_rl[3:0] == 4'd5) ;
assign IF_m_trap_lat_2_whas_THEN_m_trap_lat_2_wget_BI_ETC___d95 =
EN_write_enq ?
m_trap_lat_2$wget[3:0] == 4'd7 :
(m_trap_lat_0$whas ?
m_trap_lat_0$wget[3:0] == 4'd7 :
m_trap_rl[3:0] == 4'd7) ;
assign NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_84_O_ETC___d293 =
!m_ppc_vaddr_csrData_dummy2_0$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_1$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_2$Q_OUT ||
!m_ppc_vaddr_csrData_dummy2_3$Q_OUT ;
assign bs__h29532 =
(m_spec_bits_dummy2_0$Q_OUT && m_spec_bits_dummy2_1$Q_OUT &&
m_spec_bits_dummy2_2$Q_OUT) ?
m_spec_bits_rl :
12'd0 ;
assign m_claimed_phy_reg_17_CONCAT_m_trap_dummy2_0_re_ETC___d614 =
{ m_claimed_phy_reg,
m_trap_dummy2_0$Q_OUT && m_trap_dummy2_1$Q_OUT &&
m_trap_dummy2_2$Q_OUT &&
m_trap_rl[5],
m_trap_rl[4],
m_trap_rl[4] ?
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q1 :
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q2,
IF_NOT_m_ppc_vaddr_csrData_dummy2_0_read__83_8_ETC___d559,
x_read_deq_fflags__h23257,
m_will_dirty_fpu_state,
m_rob_inst_state_dummy2_0_read__65_AND_m_rob_i_ETC___d576,
m_lsqTag,
m_ldKilled_dummy2_0$Q_OUT && m_ldKilled_dummy2_1$Q_OUT &&
m_ldKilled_rl[2],
m_ldKilled_rl[1:0],
m_memAccessAtCommit_dummy2_0$Q_OUT &&
m_memAccessAtCommit_dummy2_1$Q_OUT &&
m_memAccessAtCommit_dummy2_2$Q_OUT &&
m_memAccessAtCommit_rl,
m_lsqAtCommitNotified_dummy2_0$Q_OUT &&
m_lsqAtCommitNotified_dummy2_1$Q_OUT &&
m_lsqAtCommitNotified_rl,
m_nonMMIOStDone_dummy2_0$Q_OUT &&
m_nonMMIOStDone_dummy2_1$Q_OUT &&
m_nonMMIOStDone_rl,
m_epochIncremented,
bs__h29532 } ;
assign m_iType_39_CONCAT_m_csr_40_BIT_12_41_CONCAT_IF_ETC___d615 =
{ m_iType,
m_csr[12],
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3,
m_claimed_phy_reg_17_CONCAT_m_trap_dummy2_0_re_ETC___d614 } ;
assign m_rob_inst_state_dummy2_0_read__65_AND_m_rob_i_ETC___d576 =
m_rob_inst_state_dummy2_0$Q_OUT &&
m_rob_inst_state_dummy2_1$Q_OUT &&
m_rob_inst_state_dummy2_2$Q_OUT &&
m_rob_inst_state_dummy2_3$Q_OUT &&
m_rob_inst_state_dummy2_4$Q_OUT &&
m_rob_inst_state_dummy2_5$Q_OUT &&
m_rob_inst_state_rl ;
assign sb__h29567 =
m_spec_bits_dummy2_2$Q_OUT ?
IF_m_spec_bits_lat_1_whas__75_THEN_m_spec_bits_ETC___d281 :
12'd0 ;
assign upd__h16390 = sb__h29567 & correctSpeculation_mask ;
assign x_read_deq_fflags__h23257 =
(m_fflags_dummy2_0$Q_OUT && m_fflags_dummy2_1$Q_OUT) ?
m_fflags_rl :
5'd0 ;
always@(m_trap_rl)
begin
case (m_trap_rl[3:0])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11:
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q1 =
m_trap_rl[3:0];
default: CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q1 = 4'd14;
endcase
end
always@(m_trap_rl)
begin
case (m_trap_rl[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q2 =
m_trap_rl[3:0];
default: CASE_m_trap_rl_BITS_3_TO_0_0_m_trap_rl_BITS_3__ETC__q2 = 4'd15;
endcase
end
always@(m_csr)
begin
case (m_csr[11:0])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3 =
m_csr[11:0];
default: CASE_m_csr_BITS_11_TO_0_1_m_csr_BITS_11_TO_0_2_ETC__q3 =
12'd2303;
endcase
end
always@(setExecuted_deqLSQ_cause)
begin
case (setExecuted_deqLSQ_cause[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q4 =
setExecuted_deqLSQ_cause[3:0];
default: CASE_setExecuted_deqLSQ_cause_BITS_3_TO_0_0_se_ETC__q4 = 4'd15;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[101:98])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11:
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5 =
write_enq_x[101:98];
default: CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q5 = 4'd14;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[101:98])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6 =
write_enq_x[101:98];
default: CASE_write_enq_x_BITS_101_TO_98_0_write_enq_x__ETC__q6 = 4'd15;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[97:96])
2'd0, 2'd1:
CASE_write_enq_x_BITS_97_TO_96_0_write_enq_x_B_ETC__q7 =
write_enq_x[97:96];
default: CASE_write_enq_x_BITS_97_TO_96_0_write_enq_x_B_ETC__q7 = 2'd2;
endcase
end
always@(write_enq_x)
begin
case (write_enq_x[116:105])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8 =
write_enq_x[116:105];
default: CASE_write_enq_x_BITS_116_TO_105_1_write_enq_x_ETC__q8 =
12'd2303;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_fflags_rl <= `BSV_ASSIGNMENT_DELAY 5'h0A;
m_ldKilled_rl <= `BSV_ASSIGNMENT_DELAY 3'h2;
m_lsqAtCommitNotified_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
m_memAccessAtCommit_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
m_nonMMIOStDone_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
m_ppc_vaddr_csrData_rl <= `BSV_ASSIGNMENT_DELAY 66'h2AAAAAAAAAAAAAAAA;
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
m_trap_rl <= `BSV_ASSIGNMENT_DELAY 6'h2A;
end
else
begin
if (m_fflags_rl$EN)
m_fflags_rl <= `BSV_ASSIGNMENT_DELAY m_fflags_rl$D_IN;
if (m_ldKilled_rl$EN)
m_ldKilled_rl <= `BSV_ASSIGNMENT_DELAY m_ldKilled_rl$D_IN;
if (m_lsqAtCommitNotified_rl$EN)
m_lsqAtCommitNotified_rl <= `BSV_ASSIGNMENT_DELAY
m_lsqAtCommitNotified_rl$D_IN;
if (m_memAccessAtCommit_rl$EN)
m_memAccessAtCommit_rl <= `BSV_ASSIGNMENT_DELAY
m_memAccessAtCommit_rl$D_IN;
if (m_nonMMIOStDone_rl$EN)
m_nonMMIOStDone_rl <= `BSV_ASSIGNMENT_DELAY m_nonMMIOStDone_rl$D_IN;
if (m_ppc_vaddr_csrData_rl$EN)
m_ppc_vaddr_csrData_rl <= `BSV_ASSIGNMENT_DELAY
m_ppc_vaddr_csrData_rl$D_IN;
if (m_rob_inst_state_rl$EN)
m_rob_inst_state_rl <= `BSV_ASSIGNMENT_DELAY
m_rob_inst_state_rl$D_IN;
if (m_spec_bits_rl$EN)
m_spec_bits_rl <= `BSV_ASSIGNMENT_DELAY m_spec_bits_rl$D_IN;
if (m_trap_rl$EN) m_trap_rl <= `BSV_ASSIGNMENT_DELAY m_trap_rl$D_IN;
end
if (m_claimed_phy_reg$EN)
m_claimed_phy_reg <= `BSV_ASSIGNMENT_DELAY m_claimed_phy_reg$D_IN;
if (m_csr$EN) m_csr <= `BSV_ASSIGNMENT_DELAY m_csr$D_IN;
if (m_epochIncremented$EN)
m_epochIncremented <= `BSV_ASSIGNMENT_DELAY m_epochIncremented$D_IN;
if (m_iType$EN) m_iType <= `BSV_ASSIGNMENT_DELAY m_iType$D_IN;
if (m_lsqTag$EN) m_lsqTag <= `BSV_ASSIGNMENT_DELAY m_lsqTag$D_IN;
if (m_orig_inst$EN) m_orig_inst <= `BSV_ASSIGNMENT_DELAY m_orig_inst$D_IN;
if (m_pc$EN) m_pc <= `BSV_ASSIGNMENT_DELAY m_pc$D_IN;
if (m_will_dirty_fpu_state$EN)
m_will_dirty_fpu_state <= `BSV_ASSIGNMENT_DELAY
m_will_dirty_fpu_state$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_claimed_phy_reg = 1'h0;
m_csr = 13'h0AAA;
m_epochIncremented = 1'h0;
m_fflags_rl = 5'h0A;
m_iType = 5'h0A;
m_ldKilled_rl = 3'h2;
m_lsqAtCommitNotified_rl = 1'h0;
m_lsqTag = 6'h2A;
m_memAccessAtCommit_rl = 1'h0;
m_nonMMIOStDone_rl = 1'h0;
m_orig_inst = 32'hAAAAAAAA;
m_pc = 64'hAAAAAAAAAAAAAAAA;
m_ppc_vaddr_csrData_rl = 66'h2AAAAAAAAAAAAAAAA;
m_rob_inst_state_rl = 1'h0;
m_spec_bits_rl = 12'hAAA;
m_trap_rl = 6'h2A;
m_will_dirty_fpu_state = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkRobRowSynth
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