Files
Toooba/src_SSITH_P3/Verilog_RTL/module_decode.v
rsnikhil 53aacff7c5 Changes to support 'C' extension (compressed instructions). Details follow.
>----------------
Status and outlook:

    For RV64GC, out of 229 standard ISA tests, 202 PASS, 27 FAIL.
    Below is a list of current failures, current diagnoses, and outlook.

    'C' instructions:
        rv64uc-v-rvc

        Diagnosis: error in saved regs during instruction page fault
            when a 32-bit instruction straddles a page boundary and
            the second 16-bits encounters a page fault.

            Note: the corresponding rv64uc-p-rvc passes, containing
            the same set of tests except for the virtual-memory
            aspect, so we expect this test to pass once this issue is
            fixed.

        Outlook: Target date for fix: 2019-Apr-09 (today)

    System instructions:
        rv64mi-p-access
        rv64mi-p-csr
        rv64si-p-dirty
        rv64mi-p-illegal

        Diagnosis: we do not have accurate diagnoses yet, although
            some symptoms look similar to what we saw with earlier
            processors (these test various corner-cases of system
            instructions).

        Outlook: Target date for fix: 2019-Apr-15

    'F' and 'D' instructions
        rv64uf-p-fadd        rv64uf-v-fadd
        rv64uf-p-fcmp        rv64uf-v-fcmp
        rv64uf-p-fdiv        rv64uf-v-fdiv
        rv64uf-p-fmin        rv64uf-v-fmin

        rv64ud-p-fadd        rv64ud-v-fadd
        rv64ud-p-fcmp        rv64ud-v-fcmp
        rv64ud-p-fdiv        rv64ud-v-fdiv
        rv64ud-p-fmadd       rv64ud-v-fmadd
        rv64ud-p-fmin        rv64ud-v-fmin
        rv64ud-p-ldst        rv64ud-v-ldst
        rv64ud-p-move        rv64ud-v-move

        Diagnosis: These seem to be simulation-only errors. Simulation
            uses some quick-and-dirty floating-point "model" modules
            written by the MIT authors, which are not accurate.  All
            the errors seem to be regarding incomplete treatment of
            NaNs in the models.  These errors should not happen in
            FPGA since those use Xilinx IP modules instead.  MIT has
            been booting Linux with the Xilinx IP modules, lending
            more confidence in the FPGA version.

            The actual number of root-cause failures is likely to be
            smaller than the list.  For example, the 'fadd' test has
            four variants: {uf/ud} x {-p-/-v-}; they all likely need a
            comon fix.

        Outlook: Target date: 2019-Apr-30
            [Lower priority, since FPGA versions should be ok even now.]

>----------------
Detailed comments on file changes

New files:
    Doc/micro2018.pdf
        MIT's paper on RISCY-OOO at IEEE Micro
    src_Core/CPU/CPU_Decode_C.bsv
        Function to expand 'C' instrs to 32-bit counterparts, taken from Piccolo/Flute

Modified files:
    src_Core/CPU/Core.bsv
        Added rob_getOrig_Inst method

    src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
        Added 'orig_inst' stuff, $displays

    src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
        Mostly verbosity stuff, including printing out brief instruction trace similar to Piccolo/Flute.

    src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
        Major changes for 'C', including call to Decode_C function from Piccolo/Flute
        Pass orig_inst to downpipe.

    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        Added 'orig_inst', input from FetchStage and passed on to ROB
        Tweaked PC+4 check to accommodate 'C' instructions.

    src_Core/RISCY_OOO/procs/lib/BrPred.bsv
        Fixed 'decodeBrPred' to accommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/Exec.bsv
        Fixed 'brAddrCalc', 'getControlFlow', 'basicExec' to acommodate 'C' instructions

    src_Core/RISCY_OOO/procs/lib/MemLoader.bsv
        Switched off 'verbose' by default

    src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
        Added 'C' to MISA, 'getExtensionBits'

    src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
        Added 'orig_inst' register to basic cell, and methods to set/access.

    src_Core/RISCY_OOO/procs/lib/Types.bsv
        Added typedefs for 'C' instructions
>----------------
2019-04-09 13:50:16 -04:00

1087 lines
42 KiB
Verilog

//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// decode O 100
// decode_inst I 32
//
// Combinational paths from inputs to outputs:
// decode_inst -> decode
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_decode(decode_inst,
decode);
// value method decode
input [31 : 0] decode_inst;
output [99 : 0] decode;
// signals for module outputs
wire [99 : 0] decode;
// remaining internal signals
reg [31 : 0] IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550;
reg [11 : 0] CASE_immI2_BITS_11_TO_0_0x1_immI2_BITS_11_TO_0_ETC__q30;
reg [7 : 0] CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q12;
reg [4 : 0] CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5,
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7,
CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_14__q8,
CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_IF_ETC__q6,
CASE_decode_inst_BITS_14_TO_12_0b0_21_0b1_20_19__q20,
CASE_decode_inst_BITS_14_TO_12_0b0_5_0b1_6_7__q19,
CASE_decode_inst_BITS_14_TO_12_0b1_15_0b10_16__ETC__q4,
CASE_decode_inst_BITS_24_TO_20_0_11_1_12_2_13_14__q21,
CASE_decode_inst_BITS_24_TO_20_0_15_1_16_2_17_18__q18,
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22,
CASE_decode_inst_BITS_31_TO_27_0b10_6_0b11_7_2__q28,
CASE_decode_inst_BITS_6_TO_0_19_decode_inst_BI_ETC__q31,
CASE_decode_inst_BITS_6_TO_0_35_decode_inst_BI_ETC__q34,
CASE_decode_inst_BITS_6_TO_0_67_25_71_26_75_27_ETC__q23,
CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29,
IF_decode_inst_BITS_14_TO_12_1_EQ_0b1_2_THEN_1_ETC___d53,
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85,
IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137;
reg [3 : 0] CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2,
CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q9,
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d284;
reg [2 : 0] CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q24,
CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26,
CASE_decode_inst_BITS_31_TO_27_0b0_4_0b1_4_0b1_ETC__q3,
CASE_decode_inst_BITS_6_TO_0_103_6_111_6_CASE__ETC__q27,
CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q15,
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d270;
reg [1 : 0] CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_0_0b1_ETC__q17,
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_1_0b1_ETC__q16,
IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d326;
reg CASE_decode_inst_BITS_31_TO_27_0b10_NOT_decode_ETC__q37,
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q10,
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q13,
CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38,
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q11,
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q14,
CASE_decode_inst_BITS_6_TO_0_47_NOT_decode_ins_ETC__q33,
CASE_decode_inst_BITS_6_TO_0_51_decode_inst_BI_ETC__q25,
CASE_decode_inst_BITS_6_TO_0_67_NOT_decode_ins_ETC__q35,
CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q32,
CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q36,
IF_decode_inst_BITS_6_TO_0_EQ_7_1_OR_decode_in_ETC___d197;
wire [31 : 0] immB__h34, immI__h32, immJ__h36, immS__h33, immU__h35;
wire [20 : 0] IF_NOT_decode_inst_BITS_6_TO_0_EQ_51_39_AND_NO_ETC___d406,
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d408,
x__h10144;
wire [14 : 0] IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d328;
wire [12 : 0] x__h10232;
wire [11 : 0] decode_inst_BITS_31_TO_20__q1, x__h10319;
wire [4 : 0] IF_NOT_decode_inst_BITS_26_TO_25_4_EQ_0b0_5_6__ETC___d30,
IF_SEXT_decode_inst_BITS_31_TO_20_7_8_BIT_10_0_ETC___d103;
wire decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46,
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49;
// value method decode
assign decode =
{ IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85,
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d408,
decode_inst[6:0] == 7'd115 && decode_inst[14:12] != 3'b0,
CASE_immI2_BITS_11_TO_0_0x1_immI2_BITS_11_TO_0_ETC__q30,
decode_inst[6:0] == 7'd19 || decode_inst[6:0] == 7'd27 ||
decode_inst[6:0] == 7'd55 ||
decode_inst[6:0] == 7'd23 ||
decode_inst[6:0] == 7'd111 ||
decode_inst[6:0] == 7'd103 ||
decode_inst[6:0] == 7'd99 ||
decode_inst[6:0] == 7'd3 ||
decode_inst[6:0] == 7'd35 ||
decode_inst[6:0] == 7'd47 ||
decode_inst[6:0] == 7'd7 ||
decode_inst[6:0] == 7'd39 ||
decode_inst[6:0] == 7'd115 && decode_inst[14],
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550,
decode_inst[6:0] == 7'd19 || decode_inst[6:0] == 7'd27 ||
decode_inst[6:0] == 7'd51 ||
decode_inst[6:0] == 7'd59 ||
decode_inst[6:0] == 7'd55 ||
decode_inst[6:0] == 7'd103 ||
decode_inst[6:0] == 7'd99 ||
decode_inst[6:0] == 7'd3 ||
decode_inst[6:0] == 7'd35 ||
decode_inst[6:0] == 7'd47 ||
((decode_inst[6:0] == 7'd83) ?
decode_inst[26:25] == 2'b0 || decode_inst[26:25] == 2'b01 :
decode_inst[6:0] == 7'd7 || decode_inst[6:0] == 7'd39 ||
(decode_inst[6:0] == 7'd67 || decode_inst[6:0] == 7'd71 ||
decode_inst[6:0] == 7'd75 ||
decode_inst[6:0] == 7'd79) &&
(decode_inst[26:25] == 2'b0 ||
decode_inst[26:25] == 2'b01)),
decode_inst[6:0] != 7'd19 && decode_inst[6:0] != 7'd27 &&
decode_inst[6:0] != 7'd51 &&
decode_inst[6:0] != 7'd59 &&
decode_inst[6:0] != 7'd55 &&
decode_inst[6:0] != 7'd103 &&
decode_inst[6:0] != 7'd99 &&
decode_inst[6:0] != 7'd3 &&
decode_inst[6:0] != 7'd35 &&
decode_inst[6:0] != 7'd47 &&
((decode_inst[6:0] == 7'd83) ?
decode_inst[31:27] != 5'b11110 &&
decode_inst[31:27] != 5'b11010 :
decode_inst[6:0] != 7'd7 && decode_inst[6:0] != 7'd39),
(decode_inst[6:0] == 7'd19 || decode_inst[6:0] == 7'd27 ||
decode_inst[6:0] == 7'd51 ||
decode_inst[6:0] == 7'd59 ||
decode_inst[6:0] == 7'd55 ||
decode_inst[6:0] == 7'd103 ||
decode_inst[6:0] == 7'd99 ||
decode_inst[6:0] == 7'd3 ||
decode_inst[6:0] == 7'd35 ||
decode_inst[6:0] == 7'd47 ||
((decode_inst[6:0] == 7'd83) ?
decode_inst[31:27] == 5'b11110 ||
decode_inst[31:27] == 5'b11010 :
decode_inst[6:0] == 7'd7 || decode_inst[6:0] == 7'd39)) ?
CASE_decode_inst_BITS_6_TO_0_19_decode_inst_BI_ETC__q31 :
decode_inst[19:15],
decode_inst[6:0] == 7'd51 || decode_inst[6:0] == 7'd59 ||
decode_inst[6:0] == 7'd99 ||
decode_inst[6:0] == 7'd35 ||
CASE_decode_inst_BITS_6_TO_0_47_NOT_decode_ins_ETC__q33,
decode_inst[6:0] == 7'd83 || decode_inst[6:0] == 7'd39 ||
decode_inst[6:0] == 7'd67 ||
decode_inst[6:0] == 7'd71 ||
decode_inst[6:0] == 7'd75 ||
decode_inst[6:0] == 7'd79,
(decode_inst[6:0] != 7'd83 && decode_inst[6:0] != 7'd39 &&
decode_inst[6:0] != 7'd67 &&
decode_inst[6:0] != 7'd71 &&
decode_inst[6:0] != 7'd75 &&
decode_inst[6:0] != 7'd79) ?
CASE_decode_inst_BITS_6_TO_0_35_decode_inst_BI_ETC__q34 :
decode_inst[24:20],
(decode_inst[6:0] == 7'd67 || decode_inst[6:0] == 7'd71 ||
decode_inst[6:0] == 7'd75 ||
decode_inst[6:0] == 7'd79) &&
(decode_inst[26:25] == 2'b0 || decode_inst[26:25] == 2'b01),
decode_inst[31:27],
(decode_inst[6:0] != 7'd19 && decode_inst[6:0] != 7'd27 &&
decode_inst[6:0] != 7'd51 &&
decode_inst[6:0] != 7'd59 &&
decode_inst[6:0] != 7'd55 &&
decode_inst[6:0] != 7'd23 &&
decode_inst[6:0] != 7'd111 &&
decode_inst[6:0] != 7'd103 &&
decode_inst[6:0] != 7'd3 &&
decode_inst[6:0] != 7'd47 &&
((decode_inst[6:0] == 7'd83) ?
decode_inst[26:25] != 2'b0 && decode_inst[26:25] != 2'b01 :
decode_inst[6:0] != 7'd7 &&
CASE_decode_inst_BITS_6_TO_0_67_NOT_decode_ins_ETC__q35) ||
((decode_inst[6:0] == 7'd83) ?
decode_inst[31:27] != 5'b10100 &&
decode_inst[31:27] != 5'b11100 &&
decode_inst[31:27] != 5'b11000 :
decode_inst[6:0] == 7'd7 || decode_inst[6:0] == 7'd67 ||
decode_inst[6:0] == 7'd71 ||
decode_inst[6:0] == 7'd75 ||
decode_inst[6:0] == 7'd79) ||
decode_inst[11:7] != 5'd0) &&
(decode_inst[6:0] == 7'd19 || decode_inst[6:0] == 7'd27 ||
decode_inst[6:0] == 7'd51 ||
decode_inst[6:0] == 7'd59 ||
decode_inst[6:0] == 7'd55 ||
decode_inst[6:0] == 7'd23 ||
decode_inst[6:0] == 7'd111 ||
decode_inst[6:0] == 7'd103 ||
decode_inst[6:0] == 7'd3 ||
decode_inst[6:0] == 7'd47 ||
((decode_inst[6:0] == 7'd83) ?
decode_inst[26:25] == 2'b0 || decode_inst[26:25] == 2'b01 :
decode_inst[6:0] == 7'd7 ||
CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q36)),
(decode_inst[6:0] == 7'd83) ?
decode_inst[31:27] != 5'b10100 &&
decode_inst[31:27] != 5'b11100 &&
decode_inst[31:27] != 5'b11000 :
decode_inst[6:0] == 7'd7 || decode_inst[6:0] == 7'd67 ||
decode_inst[6:0] == 7'd71 ||
decode_inst[6:0] == 7'd75 ||
decode_inst[6:0] == 7'd79,
decode_inst[11:7],
decode_inst[6:0] != 7'd19 && decode_inst[6:0] != 7'd27 &&
decode_inst[6:0] != 7'd51 &&
decode_inst[6:0] != 7'd59 &&
decode_inst[6:0] != 7'd55 &&
decode_inst[6:0] != 7'd23 &&
decode_inst[6:0] != 7'd111 &&
decode_inst[6:0] != 7'd103 &&
decode_inst[6:0] != 7'd99 &&
CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38 } ;
// remaining internal signals
assign IF_NOT_decode_inst_BITS_26_TO_25_4_EQ_0b0_5_6__ETC___d30 =
(decode_inst[26:25] != 2'b0 && decode_inst[26:25] != 2'b01) ?
5'd0 :
5'd12 ;
assign IF_NOT_decode_inst_BITS_6_TO_0_EQ_51_39_AND_NO_ETC___d406 =
(decode_inst[6:0] != 7'd51 && decode_inst[6:0] != 7'd59 &&
decode_inst[6:0] != 7'd55 &&
decode_inst[6:0] != 7'd23 &&
decode_inst[6:0] != 7'd111 &&
decode_inst[6:0] != 7'd103 &&
decode_inst[6:0] != 7'd99 &&
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q14) ?
{ 3'd2,
CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q15,
IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d328 } :
(((decode_inst[6:0] == 7'd51) ?
decode_inst[31:25] == 7'b0000001 :
decode_inst[6:0] == 7'd59 &&
decode_inst[31:25] == 7'b0000001) ?
{ 16'd27306,
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_1_0b1_ETC__q16,
decode_inst[6:0] != 7'd51,
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_0_0b1_ETC__q17 } :
(((decode_inst[6:0] == 7'd83) ?
decode_inst[26:25] == 2'b0 ||
decode_inst[26:25] == 2'b01 :
(decode_inst[6:0] == 7'd67 ||
decode_inst[6:0] == 7'd71 ||
decode_inst[6:0] == 7'd75 ||
decode_inst[6:0] == 7'd79) &&
(decode_inst[26:25] == 2'b0 ||
decode_inst[26:25] == 2'b01)) ?
{ 12'd2218,
CASE_decode_inst_BITS_6_TO_0_67_25_71_26_75_27_ETC__q23,
CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q24,
decode_inst[26:25] != 2'b0 } :
21'd1485482)) ;
assign IF_SEXT_decode_inst_BITS_31_TO_20_7_8_BIT_10_0_ETC___d103 =
immI__h32[10] ? 5'd11 : 5'd13 ;
assign IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d408 =
(decode_inst[6:0] == 7'd19 || decode_inst[6:0] == 7'd27 ||
CASE_decode_inst_BITS_6_TO_0_51_decode_inst_BI_ETC__q25) ?
{ 16'd2730,
IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137 } :
((decode_inst[6:0] == 7'd111 || decode_inst[6:0] == 7'd103 ||
decode_inst[6:0] == 7'd99) ?
{ 18'd43690,
CASE_decode_inst_BITS_6_TO_0_103_6_111_6_CASE__ETC__q27 } :
IF_NOT_decode_inst_BITS_6_TO_0_EQ_51_39_AND_NO_ETC___d406) ;
assign IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d328 =
{ CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q9,
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q11,
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q12,
IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d326 } ;
assign decode_inst_BITS_31_TO_20__q1 = decode_inst[31:20] ;
assign decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46 =
decode_inst[23] | decode_inst[21] ;
assign decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49 =
decode_inst[26] | decode_inst[24] ;
assign immB__h34 = { {19{x__h10232[12]}}, x__h10232 } ;
assign immI__h32 =
{ {20{decode_inst_BITS_31_TO_20__q1[11]}},
decode_inst_BITS_31_TO_20__q1 } ;
assign immJ__h36 = { {11{x__h10144[20]}}, x__h10144 } ;
assign immS__h33 = { {20{x__h10319[11]}}, x__h10319 } ;
assign immU__h35 = { decode_inst[31:12], 12'b0 } ;
assign x__h10144 =
{ decode_inst[31],
decode_inst[19:12],
decode_inst[20],
decode_inst[30:21],
1'b0 } ;
assign x__h10232 =
{ decode_inst[31],
decode_inst[7],
decode_inst[30:25],
decode_inst[11:8],
1'b0 } ;
assign x__h10319 = { decode_inst[31:25], decode_inst[11:7] } ;
always@(decode_inst or
decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46 or
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49)
begin
case (decode_inst[6:0])
7'd7, 7'd39:
IF_decode_inst_BITS_6_TO_0_EQ_7_1_OR_decode_in_ETC___d197 =
decode_inst[14:12] == 3'b0 || decode_inst[14:12] == 3'b001 ||
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b011 ||
decode_inst[14:12] == 3'b100 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110;
default: IF_decode_inst_BITS_6_TO_0_EQ_7_1_OR_decode_in_ETC___d197 =
decode_inst[6:0] == 7'd15 && decode_inst[14:12] == 3'b0 &&
(decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46 ||
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49);
endcase
end
always@(decode_inst or
decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46 or
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49)
begin
case (decode_inst[6:0])
7'd3, 7'd7, 7'd35, 7'd39, 7'd47:
IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d326 =
{ decode_inst[6:0] == 7'd47 && decode_inst[26],
decode_inst[6:0] == 7'd47 && decode_inst[25] };
default: IF_decode_inst_BITS_6_TO_0_EQ_3_5_OR_decode_in_ETC___d326 =
{ decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46,
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49 };
endcase
end
always@(decode_inst)
begin
case (decode_inst[31:27])
5'b0: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd1;
5'b00001: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd0;
5'b00100: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd2;
5'b01000: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd4;
5'b01100: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd3;
5'b10000: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd5;
5'b10100: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd6;
5'b11000: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd7;
5'b11100: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd8;
default: CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2 = 4'd9;
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2)
begin
case (decode_inst[6:0])
7'd3, 7'd7, 7'd35, 7'd39:
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d284 = 4'd9;
7'd47:
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d284 =
CASE_decode_inst_BITS_31_TO_27_0b0_1_0b1_0_0b1_ETC__q2;
default: IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d284 =
4'd9;
endcase
end
always@(decode_inst)
begin
case (decode_inst[31:27])
5'b0,
5'b00001,
5'b00100,
5'b01000,
5'b01100,
5'b10000,
5'b10100,
5'b11000,
5'b11100:
CASE_decode_inst_BITS_31_TO_27_0b0_4_0b1_4_0b1_ETC__q3 = 3'd4;
5'b00010: CASE_decode_inst_BITS_31_TO_27_0b0_4_0b1_4_0b1_ETC__q3 = 3'd2;
5'b00011: CASE_decode_inst_BITS_31_TO_27_0b0_4_0b1_4_0b1_ETC__q3 = 3'd3;
default: CASE_decode_inst_BITS_31_TO_27_0b0_4_0b1_4_0b1_ETC__q3 = 3'd0;
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_31_TO_27_0b0_4_0b1_4_0b1_ETC__q3)
begin
case (decode_inst[6:0])
7'd3, 7'd7:
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d270 = 3'd0;
7'd35, 7'd39:
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d270 = 3'd1;
7'd47:
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d270 =
CASE_decode_inst_BITS_31_TO_27_0b0_4_0b1_4_0b1_ETC__q3;
default: IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d270 =
3'd0;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b001, 3'b101:
CASE_decode_inst_BITS_14_TO_12_0b1_15_0b10_16__ETC__q4 = 5'd15;
3'b010, 3'b110:
CASE_decode_inst_BITS_14_TO_12_0b1_15_0b10_16__ETC__q4 = 5'd16;
default: CASE_decode_inst_BITS_14_TO_12_0b1_15_0b10_16__ETC__q4 = 5'd17;
endcase
end
always@(decode_inst or
IF_SEXT_decode_inst_BITS_31_TO_20_7_8_BIT_10_0_ETC___d103)
begin
case (decode_inst[14:12])
3'b0: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 = 5'd0;
3'b001: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 = 5'd9;
3'b010: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 = 5'd7;
3'b011: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 = 5'd8;
3'b100: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 = 5'd6;
3'd5:
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 =
IF_SEXT_decode_inst_BITS_31_TO_20_7_8_BIT_10_0_ETC___d103;
3'b110: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 = 5'd5;
3'b111: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 = 5'd4;
endcase
end
always@(decode_inst or immI__h32)
begin
case (decode_inst[14:12])
3'b0: CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_IF_ETC__q6 = 5'd1;
3'b001: CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_IF_ETC__q6 = 5'd10;
default: CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_IF_ETC__q6 =
immI__h32[10] ? 5'd12 : 5'd14;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd0;
3'b001: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd9;
3'b010: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd7;
3'b011: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd8;
3'b100: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd6;
3'd5: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd13;
3'b110: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd5;
3'b111: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 = 5'd4;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0: CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_14__q8 = 5'd1;
3'b001: CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_14__q8 = 5'd10;
default: CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_14__q8 = 5'd14;
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_14_TO_12_0b1_15_0b10_16__ETC__q4 or
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5 or
CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_IF_ETC__q6 or
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 or
CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_14__q8)
begin
case (decode_inst[6:0])
7'd19:
IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137 =
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q5;
7'd23, 7'd55:
IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137 = 5'd0;
7'd27:
IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137 =
CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_IF_ETC__q6;
7'd51:
IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137 =
(decode_inst[31:25] == 7'b0) ?
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_9_0b1_ETC__q7 :
((decode_inst[14:12] == 3'b0) ? 5'd2 : 5'd11);
7'd59:
IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137 =
(decode_inst[31:25] == 7'b0) ?
CASE_decode_inst_BITS_14_TO_12_0b0_1_0b1_10_14__q8 :
((decode_inst[14:12] == 3'b0) ? 5'd3 : 5'd12);
default: IF_decode_inst_BITS_6_TO_0_EQ_19_THEN_IF_decod_ETC___d137 =
CASE_decode_inst_BITS_14_TO_12_0b1_15_0b10_16__ETC__q4;
endcase
end
always@(decode_inst or
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d284)
begin
case (decode_inst[6:0])
7'd3, 7'd7, 7'd35, 7'd39, 7'd47:
CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q9 =
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d284;
default: CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q9 = 4'd9;
endcase
end
always@(decode_inst)
begin
case (decode_inst[31:27])
5'b00010, 5'b00011:
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q10 =
decode_inst[14:12] == 3'b100 || decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110;
default: CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q10 =
decode_inst[14:12] == 3'b100 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110;
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q10)
begin
case (decode_inst[6:0])
7'd3, 7'd35:
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q11 =
decode_inst[14:12] == 3'b100 || decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110;
7'd47:
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q11 =
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q10;
default: CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q11 =
decode_inst[6:0] == 7'd7 ||
decode_inst[6:0] == 7'd39 &&
(decode_inst[14:12] == 3'b100 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110);
endcase
end
always@(decode_inst)
begin
case (decode_inst[6:0])
7'd3, 7'd7, 7'd35, 7'd47:
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q12 =
{ decode_inst[14:12] == 3'b011,
decode_inst[14:12] == 3'b011,
decode_inst[14:12] == 3'b011,
decode_inst[14:12] == 3'b011,
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b110 ||
decode_inst[14:12] == 3'b011,
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b110 ||
decode_inst[14:12] == 3'b011,
decode_inst[14:12] == 3'b001 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b110 ||
decode_inst[14:12] == 3'b011,
decode_inst[14:12] == 3'b0 || decode_inst[14:12] == 3'b100 ||
decode_inst[14:12] == 3'b001 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b110 ||
decode_inst[14:12] == 3'b011 };
default: CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q12 =
{ decode_inst[6:0] == 7'd39 &&
decode_inst[14:12] == 3'b011,
decode_inst[6:0] == 7'd39 &&
decode_inst[14:12] == 3'b011,
decode_inst[6:0] == 7'd39 &&
decode_inst[14:12] == 3'b011,
decode_inst[6:0] == 7'd39 &&
decode_inst[14:12] == 3'b011,
decode_inst[6:0] == 7'd39 &&
(decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b110 ||
decode_inst[14:12] == 3'b011),
decode_inst[6:0] == 7'd39 &&
(decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b110 ||
decode_inst[14:12] == 3'b011),
decode_inst[6:0] == 7'd39 &&
(decode_inst[14:12] == 3'b001 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b110 ||
decode_inst[14:12] == 3'b011),
decode_inst[6:0] == 7'd39 };
endcase
end
always@(decode_inst or
immI__h32 or immU__h35 or immS__h33 or immB__h34 or immJ__h36)
begin
case (decode_inst[6:0])
7'd3, 7'd7, 7'd19, 7'd27, 7'd103:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550 =
immI__h32;
7'd23, 7'd55:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550 =
immU__h35;
7'd35, 7'd39:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550 =
immS__h33;
7'd47:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550 = 32'd0;
7'd99:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550 =
immB__h34;
7'd111:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550 =
immJ__h36;
default: IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d550 =
{ 27'd0, decode_inst[19:15] };
endcase
end
always@(decode_inst)
begin
case (decode_inst[31:27])
5'b00010, 5'b00011:
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q13 =
decode_inst[14:12] == 3'b0 || decode_inst[14:12] == 3'b001 ||
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b011 ||
decode_inst[14:12] == 3'b100 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110;
default: CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q13 =
(decode_inst[31:27] == 5'b00001 ||
decode_inst[31:27] == 5'b0 ||
decode_inst[31:27] == 5'b00100 ||
decode_inst[31:27] == 5'b01100 ||
decode_inst[31:27] == 5'b01000 ||
decode_inst[31:27] == 5'b10000 ||
decode_inst[31:27] == 5'b10100 ||
decode_inst[31:27] == 5'b11000 ||
decode_inst[31:27] == 5'b11100) &&
(decode_inst[14:12] == 3'b0 ||
decode_inst[14:12] == 3'b001 ||
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b011 ||
decode_inst[14:12] == 3'b100 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110);
endcase
end
always@(decode_inst or
IF_decode_inst_BITS_6_TO_0_EQ_7_1_OR_decode_in_ETC___d197 or
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q13)
begin
case (decode_inst[6:0])
7'd3, 7'd35:
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q14 =
decode_inst[14:12] == 3'b0 || decode_inst[14:12] == 3'b001 ||
decode_inst[14:12] == 3'b010 ||
decode_inst[14:12] == 3'b011 ||
decode_inst[14:12] == 3'b100 ||
decode_inst[14:12] == 3'b101 ||
decode_inst[14:12] == 3'b110;
7'd47:
CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q14 =
CASE_decode_inst_BITS_31_TO_27_0b10_decode_ins_ETC__q13;
default: CASE_decode_inst_BITS_6_TO_0_3_decode_inst_BIT_ETC__q14 =
decode_inst[6:0] != 7'd83 &&
IF_decode_inst_BITS_6_TO_0_EQ_7_1_OR_decode_in_ETC___d197;
endcase
end
always@(decode_inst or
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d270)
begin
case (decode_inst[6:0])
7'd3, 7'd7, 7'd35, 7'd39, 7'd47:
CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q15 =
IF_NOT_decode_inst_BITS_14_TO_12_1_EQ_0b0_3_0__ETC___d270;
default: CASE_decode_inst_BITS_6_TO_0_3_IF_NOT_decode_i_ETC__q15 = 3'd5;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_1_0b1_ETC__q16 = 2'd0;
3'b001, 3'b010, 3'b011:
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_1_0b1_ETC__q16 = 2'd1;
3'b100, 3'b101:
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_1_0b1_ETC__q16 = 2'd2;
default: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_1_0b1_ETC__q16 = 2'd3;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0, 3'b001, 3'b100, 3'b110:
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_0_0b1_ETC__q17 = 2'd0;
3'b010: CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_0_0b1_ETC__q17 = 2'd2;
3'b011, 3'b101, 3'd7:
CASE_decode_inst_BITS_14_TO_12_0b0_0_0b1_0_0b1_ETC__q17 = 2'd1;
endcase
end
always@(decode_inst)
begin
case (decode_inst[24:20])
5'd0: CASE_decode_inst_BITS_24_TO_20_0_15_1_16_2_17_18__q18 = 5'd15;
5'd1: CASE_decode_inst_BITS_24_TO_20_0_15_1_16_2_17_18__q18 = 5'd16;
5'd2: CASE_decode_inst_BITS_24_TO_20_0_15_1_16_2_17_18__q18 = 5'd17;
default: CASE_decode_inst_BITS_24_TO_20_0_15_1_16_2_17_18__q18 = 5'd18;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0: CASE_decode_inst_BITS_14_TO_12_0b0_5_0b1_6_7__q19 = 5'd5;
3'b001: CASE_decode_inst_BITS_14_TO_12_0b0_5_0b1_6_7__q19 = 5'd6;
default: CASE_decode_inst_BITS_14_TO_12_0b0_5_0b1_6_7__q19 = 5'd7;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0: CASE_decode_inst_BITS_14_TO_12_0b0_21_0b1_20_19__q20 = 5'd21;
3'b001: CASE_decode_inst_BITS_14_TO_12_0b0_21_0b1_20_19__q20 = 5'd20;
default: CASE_decode_inst_BITS_14_TO_12_0b0_21_0b1_20_19__q20 = 5'd19;
endcase
end
always@(decode_inst)
begin
case (decode_inst[24:20])
5'd0: CASE_decode_inst_BITS_24_TO_20_0_11_1_12_2_13_14__q21 = 5'd11;
5'd1: CASE_decode_inst_BITS_24_TO_20_0_11_1_12_2_13_14__q21 = 5'd12;
5'd2: CASE_decode_inst_BITS_24_TO_20_0_11_1_12_2_13_14__q21 = 5'd13;
default: CASE_decode_inst_BITS_24_TO_20_0_11_1_12_2_13_14__q21 = 5'd14;
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_24_TO_20_0_15_1_16_2_17_18__q18 or
CASE_decode_inst_BITS_14_TO_12_0b0_5_0b1_6_7__q19 or
CASE_decode_inst_BITS_14_TO_12_0b0_21_0b1_20_19__q20 or
CASE_decode_inst_BITS_24_TO_20_0_11_1_12_2_13_14__q21)
begin
case (decode_inst[31:27])
5'b0, 5'b00001, 5'b00010, 5'b00011:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 =
decode_inst[31:27];
5'b00100:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 =
CASE_decode_inst_BITS_14_TO_12_0b0_5_0b1_6_7__q19;
5'b00101:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 =
(decode_inst[14:12] == 3'b0) ? 5'd8 : 5'd9;
5'b01000:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 = 5'd10;
5'b01011:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 = 5'd4;
5'b10100:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 =
CASE_decode_inst_BITS_14_TO_12_0b0_21_0b1_20_19__q20;
5'b11000:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 =
CASE_decode_inst_BITS_24_TO_20_0_11_1_12_2_13_14__q21;
5'b11100:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 =
(decode_inst[14:12] == 3'b0) ? 5'd23 : 5'd22;
5'b11110:
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 = 5'd24;
default: CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22 =
CASE_decode_inst_BITS_24_TO_20_0_15_1_16_2_17_18__q18;
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22)
begin
case (decode_inst[6:0])
7'd67: CASE_decode_inst_BITS_6_TO_0_67_25_71_26_75_27_ETC__q23 = 5'd25;
7'd71: CASE_decode_inst_BITS_6_TO_0_67_25_71_26_75_27_ETC__q23 = 5'd26;
7'd75: CASE_decode_inst_BITS_6_TO_0_67_25_71_26_75_27_ETC__q23 = 5'd27;
7'd83:
CASE_decode_inst_BITS_6_TO_0_67_25_71_26_75_27_ETC__q23 =
CASE_decode_inst_BITS_31_TO_27_0b0_decode_inst_ETC__q22;
default: CASE_decode_inst_BITS_6_TO_0_67_25_71_26_75_27_ETC__q23 =
5'd28;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0, 3'b001, 3'b010, 3'b011, 3'b100:
CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q24 =
decode_inst[14:12];
default: CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q24 = 3'd7;
endcase
end
always@(decode_inst)
begin
case (decode_inst[6:0])
7'd51, 7'd59:
CASE_decode_inst_BITS_6_TO_0_51_decode_inst_BI_ETC__q25 =
decode_inst[31:25] == 7'b0 || decode_inst[31:25] == 7'b0100000;
default: CASE_decode_inst_BITS_6_TO_0_51_decode_inst_BI_ETC__q25 =
decode_inst[6:0] == 7'd55 || decode_inst[6:0] == 7'd23 ||
decode_inst[6:0] == 7'd115 && decode_inst[14:12] != 3'b0;
endcase
end
always@(decode_inst)
begin
case (decode_inst[14:12])
3'b0, 3'b001:
CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26 =
decode_inst[14:12];
3'b100: CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26 = 3'd2;
3'b101: CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26 = 3'd4;
3'b110: CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26 = 3'd3;
default: CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26 = 3'd5;
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26)
begin
case (decode_inst[6:0])
7'd103, 7'd111:
CASE_decode_inst_BITS_6_TO_0_103_6_111_6_CASE__ETC__q27 = 3'd6;
default: CASE_decode_inst_BITS_6_TO_0_103_6_111_6_CASE__ETC__q27 =
CASE_decode_inst_BITS_14_TO_12_0b0_decode_inst_ETC__q26;
endcase
end
always@(decode_inst or
decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46 or
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49)
begin
case (decode_inst[14:12])
3'b0:
IF_decode_inst_BITS_14_TO_12_1_EQ_0b1_2_THEN_1_ETC___d53 =
(decode_inst_BIT_23_4_OR_decode_inst_BIT_21_5___d46 ||
decode_inst_BIT_26_7_OR_decode_inst_BIT_24_8___d49) ?
5'd14 :
5'd1;
3'b001:
IF_decode_inst_BITS_14_TO_12_1_EQ_0b1_2_THEN_1_ETC___d53 = 5'd15;
default: IF_decode_inst_BITS_14_TO_12_1_EQ_0b1_2_THEN_1_ETC___d53 =
5'd0;
endcase
end
always@(decode_inst)
begin
case (decode_inst[31:27])
5'b00010: CASE_decode_inst_BITS_31_TO_27_0b10_6_0b11_7_2__q28 = 5'd6;
5'b00011: CASE_decode_inst_BITS_31_TO_27_0b10_6_0b11_7_2__q28 = 5'd7;
default: CASE_decode_inst_BITS_31_TO_27_0b10_6_0b11_7_2__q28 = 5'd2;
endcase
end
always@(immI__h32)
begin
case (immI__h32[11:0])
12'h0: CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29 = 5'd17;
12'h001:
CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29 = 5'd18;
12'h102:
CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29 = 5'd19;
12'h105: CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29 = 5'd1;
12'h302:
CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29 = 5'd20;
default: CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29 = 5'd0;
endcase
end
always@(decode_inst or
IF_decode_inst_BITS_14_TO_12_1_EQ_0b1_2_THEN_1_ETC___d53 or
CASE_decode_inst_BITS_31_TO_27_0b10_6_0b11_7_2__q28 or
IF_NOT_decode_inst_BITS_26_TO_25_4_EQ_0b0_5_6__ETC___d30 or
CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29)
begin
case (decode_inst[6:0])
7'd3, 7'd7:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 = 5'd4;
7'd15:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 =
IF_decode_inst_BITS_14_TO_12_1_EQ_0b1_2_THEN_1_ETC___d53;
7'd19, 7'd27, 7'd51, 7'd55, 7'd59:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 = 5'd3;
7'd23: IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 = 5'd11;
7'd35, 7'd39:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 = 5'd5;
7'd47:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 =
CASE_decode_inst_BITS_31_TO_27_0b10_6_0b11_7_2__q28;
7'd67, 7'd71, 7'd75, 7'd79, 7'd83:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 =
IF_NOT_decode_inst_BITS_26_TO_25_4_EQ_0b0_5_6__ETC___d30;
7'd99: IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 = 5'd10;
7'd103: IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 = 5'd9;
7'd111: IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 = 5'd8;
7'd115:
IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 =
(decode_inst[14:12] == 3'b0) ?
((decode_inst[31:25] == 7'h09) ?
5'd16 :
CASE_immI2_BITS_11_TO_0_0x0_17_0x1_18_0x102_19_ETC__q29) :
5'd13;
default: IF_decode_inst_BITS_6_TO_0_EQ_19_OR_decode_ins_ETC___d85 =
5'd0;
endcase
end
always@(immI__h32)
begin
case (immI__h32[11:0])
12'h001,
12'd2,
12'd3,
12'd256,
12'd260,
12'h105,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'h302,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_immI2_BITS_11_TO_0_0x1_immI2_BITS_11_TO_0_ETC__q30 =
immI__h32[11:0];
default: CASE_immI2_BITS_11_TO_0_0x1_immI2_BITS_11_TO_0_ETC__q30 =
12'd2303;
endcase
end
always@(decode_inst)
begin
case (decode_inst[6:0])
7'd19, 7'd27, 7'd51, 7'd59:
CASE_decode_inst_BITS_6_TO_0_19_decode_inst_BI_ETC__q31 =
decode_inst[19:15];
7'd55: CASE_decode_inst_BITS_6_TO_0_19_decode_inst_BI_ETC__q31 = 5'd0;
default: CASE_decode_inst_BITS_6_TO_0_19_decode_inst_BI_ETC__q31 =
decode_inst[19:15];
endcase
end
always@(decode_inst)
begin
case (decode_inst[6:0])
7'd67, 7'd71, 7'd75, 7'd79:
CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q32 =
decode_inst[26:25] == 2'b0 || decode_inst[26:25] == 2'b01;
default: CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q32 =
decode_inst[6:0] == 7'd115 && decode_inst[14:12] != 3'b0 &&
!decode_inst[14];
endcase
end
always@(decode_inst or
CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q32)
begin
case (decode_inst[6:0])
7'd47:
CASE_decode_inst_BITS_6_TO_0_47_NOT_decode_ins_ETC__q33 =
decode_inst[31:27] != 5'b00010;
7'd83:
CASE_decode_inst_BITS_6_TO_0_47_NOT_decode_ins_ETC__q33 =
(decode_inst[26:25] == 2'b0 || decode_inst[26:25] == 2'b01) &&
decode_inst[31:27] != 5'b01011 &&
decode_inst[31:27] != 5'b11100 &&
decode_inst[31:27] != 5'b11110 &&
decode_inst[31:27] != 5'b01000 &&
decode_inst[31:27] != 5'b11000 &&
decode_inst[31:27] != 5'b11010;
default: CASE_decode_inst_BITS_6_TO_0_47_NOT_decode_ins_ETC__q33 =
decode_inst[6:0] == 7'd39 ||
CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q32;
endcase
end
always@(decode_inst)
begin
case (decode_inst[6:0])
7'd35, 7'd47, 7'd51, 7'd59, 7'd99:
CASE_decode_inst_BITS_6_TO_0_35_decode_inst_BI_ETC__q34 =
decode_inst[24:20];
default: CASE_decode_inst_BITS_6_TO_0_35_decode_inst_BI_ETC__q34 =
decode_inst[19:15];
endcase
end
always@(decode_inst)
begin
case (decode_inst[6:0])
7'd67, 7'd71, 7'd75, 7'd79:
CASE_decode_inst_BITS_6_TO_0_67_NOT_decode_ins_ETC__q35 =
decode_inst[26:25] != 2'b0 && decode_inst[26:25] != 2'b01;
default: CASE_decode_inst_BITS_6_TO_0_67_NOT_decode_ins_ETC__q35 =
decode_inst[6:0] != 7'd115 || decode_inst[14:12] == 3'b0;
endcase
end
always@(decode_inst)
begin
case (decode_inst[6:0])
7'd67, 7'd71, 7'd75, 7'd79:
CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q36 =
decode_inst[26:25] == 2'b0 || decode_inst[26:25] == 2'b01;
default: CASE_decode_inst_BITS_6_TO_0_67_decode_inst_BI_ETC__q36 =
decode_inst[6:0] == 7'd115 && decode_inst[14:12] != 3'b0;
endcase
end
always@(decode_inst)
begin
case (decode_inst[31:27])
5'b00010, 5'b00011:
CASE_decode_inst_BITS_31_TO_27_0b10_NOT_decode_ETC__q37 =
decode_inst[14:12] != 3'b0 && decode_inst[14:12] != 3'b100 &&
decode_inst[14:12] != 3'b001 &&
decode_inst[14:12] != 3'b101 &&
decode_inst[14:12] != 3'b010 &&
decode_inst[14:12] != 3'b110 &&
decode_inst[14:12] != 3'b011;
default: CASE_decode_inst_BITS_31_TO_27_0b10_NOT_decode_ETC__q37 =
decode_inst[31:27] != 5'b00001 &&
decode_inst[31:27] != 5'b0 &&
decode_inst[31:27] != 5'b00100 &&
decode_inst[31:27] != 5'b01100 &&
decode_inst[31:27] != 5'b01000 &&
decode_inst[31:27] != 5'b10000 &&
decode_inst[31:27] != 5'b10100 &&
decode_inst[31:27] != 5'b11000 &&
decode_inst[31:27] != 5'b11100 ||
decode_inst[14:12] != 3'b0 &&
decode_inst[14:12] != 3'b100 &&
decode_inst[14:12] != 3'b001 &&
decode_inst[14:12] != 3'b101 &&
decode_inst[14:12] != 3'b010 &&
decode_inst[14:12] != 3'b110 &&
decode_inst[14:12] != 3'b011;
endcase
end
always@(decode_inst or
immI__h32 or
CASE_decode_inst_BITS_31_TO_27_0b10_NOT_decode_ETC__q37)
begin
case (decode_inst[6:0])
7'd3, 7'd7, 7'd35, 7'd39:
CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38 =
decode_inst[14:12] != 3'b0 && decode_inst[14:12] != 3'b100 &&
decode_inst[14:12] != 3'b001 &&
decode_inst[14:12] != 3'b101 &&
decode_inst[14:12] != 3'b010 &&
decode_inst[14:12] != 3'b110 &&
decode_inst[14:12] != 3'b011;
7'd15:
CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38 =
decode_inst[14:12] != 3'b001 && decode_inst[14:12] != 3'b0;
7'd47:
CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38 =
CASE_decode_inst_BITS_31_TO_27_0b10_NOT_decode_ETC__q37;
7'd67, 7'd71, 7'd75, 7'd79:
CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38 =
decode_inst[26:25] != 2'b0 && decode_inst[26:25] != 2'b01 ||
decode_inst[6:0] != 7'd67 && decode_inst[6:0] != 7'd71 &&
decode_inst[6:0] != 7'd75 &&
decode_inst[6:0] != 7'd79;
7'd83:
CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38 =
decode_inst[26:25] != 2'b0 && decode_inst[26:25] != 2'b01;
default: CASE_decode_inst_BITS_6_TO_0_3_NOT_decode_inst_ETC__q38 =
decode_inst[6:0] != 7'd115 ||
decode_inst[14:12] == 3'b0 &&
decode_inst[31:25] != 7'h09 &&
immI__h32[11:0] != 12'h102 &&
immI__h32[11:0] != 12'h302 &&
immI__h32[11:0] != 12'h0 &&
immI__h32[11:0] != 12'h001 &&
immI__h32[11:0] != 12'h105;
endcase
end
endmodule // module_decode