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Toooba/src_SSITH_P3/xilinx_ip/component.xml
rsnikhil 113f888d37 Added support for 'debug_external_interrupt_req' 
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00

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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>ssith</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>ssith_processor</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>master0</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:master>
<spirit:addressSpaceRef spirit:addressSpaceRef="master0"/>
</spirit:master>
<spirit:portMaps>
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<spirit:logicalPort>
<spirit:name>AWID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>master0_awid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
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<spirit:name>AWADDR</spirit:name>
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<spirit:physicalPort>
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