156 lines
4.3 KiB
Verilog
156 lines
4.3 KiB
Verilog
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// Copyright (c) 2000-2012 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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`ifdef BSV_ASYNC_RESET
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`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
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`else
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`define BSV_ARESET_EDGE_META
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`endif
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`ifdef BSV_RESET_FIFO_HEAD
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`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
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`else
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`define BSV_ARESET_EDGE_HEAD
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`endif
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// Depth 1 FIFO
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// Allows simultaneous ENQ and DEQ (at the expense of potentially
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// causing combinational loops).
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module FIFOL1(CLK,
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RST,
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D_IN,
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ENQ,
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FULL_N,
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D_OUT,
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DEQ,
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EMPTY_N,
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CLR);
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parameter width = 1;
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input CLK;
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input RST;
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input [width - 1 : 0] D_IN;
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input ENQ;
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input DEQ;
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input CLR ;
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output FULL_N;
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output EMPTY_N;
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output [width - 1 : 0] D_OUT;
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reg empty_reg ;
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reg [width - 1 : 0] D_OUT;
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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// synopsys translate_off
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initial
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begin
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D_OUT <= `BSV_ASSIGNMENT_DELAY {((width + 1)/2) {2'b10}} ;
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empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
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end // initial begin
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// synopsys translate_on
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`endif // BSV_NO_INITIAL_BLOCKS
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assign FULL_N = !empty_reg || DEQ;
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assign EMPTY_N = empty_reg ;
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always@(posedge CLK `BSV_ARESET_EDGE_META)
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begin
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if (RST == `BSV_RESET_VALUE)
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begin
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empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
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end
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else
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begin
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if (CLR)
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begin
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empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
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end
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else if (ENQ)
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begin
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empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
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end
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else if (DEQ)
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begin
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empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
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end // if (DEQ)
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end // else: !if(RST == `BSV_RESET_VALUE)
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end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
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always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
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begin
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`ifdef BSV_RESET_FIFO_HEAD
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if (RST == `BSV_RESET_VALUE)
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begin
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D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
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end
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else
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`endif
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begin
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if (ENQ)
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D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
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end // else: !if(RST == `BSV_RESET_VALUE)
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end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
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// synopsys translate_off
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always@(posedge CLK)
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begin: error_checks
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reg deqerror, enqerror ;
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deqerror = 0;
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enqerror = 0;
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if ( ! empty_reg && DEQ )
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begin
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deqerror = 1 ;
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$display( "Warning: FIFOL1: %m -- Dequeuing from empty fifo" ) ;
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end
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if ( ! FULL_N && ENQ && ! DEQ)
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begin
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enqerror = 1 ;
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$display( "Warning: FIFOL1: %m -- Enqueuing to a full fifo" ) ;
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end
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end
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// synopsys translate_on
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endmodule
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