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75df204e31a950cdf67d2931bfde9a890f42e1a9
Toooba/src_SSITH_P3/Verilog_RTL/mkCoreW.v
rsnikhil 75df204e31 Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values) 
MIP/MIE/SIP/SIE fields are WARL (Write-Any/Read-Legal). The CSR
register forces the user-privilege bits ([8,4,0]) to 0 since riscy-ooo
does not support user-level interrupts.  However, function
Csrfile.fv_warl_xform() was not mirroring this correctly.
2020-03-04 09:50:39 -05:00

3753 lines
153 KiB
Verilog
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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_start O 1
// cpu_imem_master_awvalid O 1
// cpu_imem_master_awid O 4 reg
// cpu_imem_master_awaddr O 64 reg
// cpu_imem_master_awlen O 8 reg
// cpu_imem_master_awsize O 3 reg
// cpu_imem_master_awburst O 2 reg
// cpu_imem_master_awlock O 1 reg
// cpu_imem_master_awcache O 4 reg
// cpu_imem_master_awprot O 3 reg
// cpu_imem_master_awqos O 4 reg
// cpu_imem_master_awregion O 4 reg
// cpu_imem_master_wvalid O 1
// cpu_imem_master_wdata O 64 reg
// cpu_imem_master_wstrb O 8 reg
// cpu_imem_master_wlast O 1 reg
// cpu_imem_master_bready O 1
// cpu_imem_master_arvalid O 1
// cpu_imem_master_arid O 4 reg
// cpu_imem_master_araddr O 64 reg
// cpu_imem_master_arlen O 8 reg
// cpu_imem_master_arsize O 3 reg
// cpu_imem_master_arburst O 2 reg
// cpu_imem_master_arlock O 1 reg
// cpu_imem_master_arcache O 4 reg
// cpu_imem_master_arprot O 3 reg
// cpu_imem_master_arqos O 4 reg
// cpu_imem_master_arregion O 4 reg
// cpu_imem_master_rready O 1
// cpu_dmem_master_awvalid O 1 reg
// cpu_dmem_master_awid O 4 reg
// cpu_dmem_master_awaddr O 64 reg
// cpu_dmem_master_awlen O 8 reg
// cpu_dmem_master_awsize O 3 reg
// cpu_dmem_master_awburst O 2 reg
// cpu_dmem_master_awlock O 1 reg
// cpu_dmem_master_awcache O 4 reg
// cpu_dmem_master_awprot O 3 reg
// cpu_dmem_master_awqos O 4 reg
// cpu_dmem_master_awregion O 4 reg
// cpu_dmem_master_wvalid O 1 reg
// cpu_dmem_master_wdata O 64 reg
// cpu_dmem_master_wstrb O 8 reg
// cpu_dmem_master_wlast O 1 reg
// cpu_dmem_master_bready O 1 reg
// cpu_dmem_master_arvalid O 1 reg
// cpu_dmem_master_arid O 4 reg
// cpu_dmem_master_araddr O 64 reg
// cpu_dmem_master_arlen O 8 reg
// cpu_dmem_master_arsize O 3 reg
// cpu_dmem_master_arburst O 2 reg
// cpu_dmem_master_arlock O 1 reg
// cpu_dmem_master_arcache O 4 reg
// cpu_dmem_master_arprot O 3 reg
// cpu_dmem_master_arqos O 4 reg
// cpu_dmem_master_arregion O 4 reg
// cpu_dmem_master_rready O 1 reg
// RDY_dmi_read_addr O 1
// dmi_read_data O 32
// RDY_dmi_read_data O 1
// RDY_dmi_write O 1
// ndm_reset_client_request_get O 1 reg
// RDY_ndm_reset_client_request_get O 1 reg
// RDY_ndm_reset_client_response_put O 1 reg
// tv_verifier_info_get_get O 608 reg
// RDY_tv_verifier_info_get_get O 1 reg
// RST_N_dm_power_on_reset I 1 reset
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4
// set_verbosity_logdelay I 64 unused
// start_tohost_addr I 64
// start_fromhost_addr I 64
// cpu_imem_master_awready I 1
// cpu_imem_master_wready I 1
// cpu_imem_master_bvalid I 1
// cpu_imem_master_bid I 4 reg
// cpu_imem_master_bresp I 2 reg
// cpu_imem_master_arready I 1
// cpu_imem_master_rvalid I 1
// cpu_imem_master_rid I 4 reg
// cpu_imem_master_rdata I 64 reg
// cpu_imem_master_rresp I 2 reg
// cpu_imem_master_rlast I 1 reg
// cpu_dmem_master_awready I 1
// cpu_dmem_master_wready I 1
// cpu_dmem_master_bvalid I 1
// cpu_dmem_master_bid I 4 reg
// cpu_dmem_master_bresp I 2 reg
// cpu_dmem_master_arready I 1
// cpu_dmem_master_rvalid I 1
// cpu_dmem_master_rid I 4 reg
// cpu_dmem_master_rdata I 64 reg
// cpu_dmem_master_rresp I 2 reg
// cpu_dmem_master_rlast I 1 reg
// core_external_interrupt_sources_0_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_1_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_2_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_3_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_4_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_5_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_6_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_7_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_8_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_9_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_10_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_11_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_12_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_13_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_14_m_interrupt_req_set_not_clear I 1
// core_external_interrupt_sources_15_m_interrupt_req_set_not_clear I 1
// nmi_req_set_not_clear I 1 unused
// dmi_read_addr_dm_addr I 7
// dmi_write_dm_addr I 7
// dmi_write_dm_word I 32
// ndm_reset_client_response_put I 1 reg
// EN_set_verbosity I 1
// EN_start I 1
// EN_dmi_read_addr I 1
// EN_dmi_write I 1
// EN_ndm_reset_client_response_put I 1
// EN_dmi_read_data I 1
// EN_ndm_reset_client_request_get I 1
// EN_tv_verifier_info_get_get I 1
//
// Combinational paths from inputs to outputs:
// (cpu_imem_master_awready, cpu_imem_master_wready) -> cpu_imem_master_bready
// (dmi_read_addr_dm_addr, EN_dmi_read_addr) -> RDY_dmi_read_data
// (dmi_read_addr_dm_addr, EN_dmi_read_addr, EN_dmi_read_data) -> dmi_read_data
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCoreW(RST_N_dm_power_on_reset,
CLK,
RST_N,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
start_tohost_addr,
start_fromhost_addr,
EN_start,
RDY_start,
cpu_imem_master_awvalid,
cpu_imem_master_awid,
cpu_imem_master_awaddr,
cpu_imem_master_awlen,
cpu_imem_master_awsize,
cpu_imem_master_awburst,
cpu_imem_master_awlock,
cpu_imem_master_awcache,
cpu_imem_master_awprot,
cpu_imem_master_awqos,
cpu_imem_master_awregion,
cpu_imem_master_awready,
cpu_imem_master_wvalid,
cpu_imem_master_wdata,
cpu_imem_master_wstrb,
cpu_imem_master_wlast,
cpu_imem_master_wready,
cpu_imem_master_bvalid,
cpu_imem_master_bid,
cpu_imem_master_bresp,
cpu_imem_master_bready,
cpu_imem_master_arvalid,
cpu_imem_master_arid,
cpu_imem_master_araddr,
cpu_imem_master_arlen,
cpu_imem_master_arsize,
cpu_imem_master_arburst,
cpu_imem_master_arlock,
cpu_imem_master_arcache,
cpu_imem_master_arprot,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_arready,
cpu_imem_master_rvalid,
cpu_imem_master_rid,
cpu_imem_master_rdata,
cpu_imem_master_rresp,
cpu_imem_master_rlast,
cpu_imem_master_rready,
cpu_dmem_master_awvalid,
cpu_dmem_master_awid,
cpu_dmem_master_awaddr,
cpu_dmem_master_awlen,
cpu_dmem_master_awsize,
cpu_dmem_master_awburst,
cpu_dmem_master_awlock,
cpu_dmem_master_awcache,
cpu_dmem_master_awprot,
cpu_dmem_master_awqos,
cpu_dmem_master_awregion,
cpu_dmem_master_awready,
cpu_dmem_master_wvalid,
cpu_dmem_master_wdata,
cpu_dmem_master_wstrb,
cpu_dmem_master_wlast,
cpu_dmem_master_wready,
cpu_dmem_master_bvalid,
cpu_dmem_master_bid,
cpu_dmem_master_bresp,
cpu_dmem_master_bready,
cpu_dmem_master_arvalid,
cpu_dmem_master_arid,
cpu_dmem_master_araddr,
cpu_dmem_master_arlen,
cpu_dmem_master_arsize,
cpu_dmem_master_arburst,
cpu_dmem_master_arlock,
cpu_dmem_master_arcache,
cpu_dmem_master_arprot,
cpu_dmem_master_arqos,
cpu_dmem_master_arregion,
cpu_dmem_master_arready,
cpu_dmem_master_rvalid,
cpu_dmem_master_rid,
cpu_dmem_master_rdata,
cpu_dmem_master_rresp,
cpu_dmem_master_rlast,
cpu_dmem_master_rready,
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear,
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
dmi_read_addr_dm_addr,
EN_dmi_read_addr,
RDY_dmi_read_addr,
EN_dmi_read_data,
dmi_read_data,
RDY_dmi_read_data,
dmi_write_dm_addr,
dmi_write_dm_word,
EN_dmi_write,
RDY_dmi_write,
EN_ndm_reset_client_request_get,
ndm_reset_client_request_get,
RDY_ndm_reset_client_request_get,
ndm_reset_client_response_put,
EN_ndm_reset_client_response_put,
RDY_ndm_reset_client_response_put,
EN_tv_verifier_info_get_get,
tv_verifier_info_get_get,
RDY_tv_verifier_info_get_get);
input RST_N_dm_power_on_reset;
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method start
input [63 : 0] start_tohost_addr;
input [63 : 0] start_fromhost_addr;
input EN_start;
output RDY_start;
// value method cpu_imem_master_m_awvalid
output cpu_imem_master_awvalid;
// value method cpu_imem_master_m_awid
output [3 : 0] cpu_imem_master_awid;
// value method cpu_imem_master_m_awaddr
output [63 : 0] cpu_imem_master_awaddr;
// value method cpu_imem_master_m_awlen
output [7 : 0] cpu_imem_master_awlen;
// value method cpu_imem_master_m_awsize
output [2 : 0] cpu_imem_master_awsize;
// value method cpu_imem_master_m_awburst
output [1 : 0] cpu_imem_master_awburst;
// value method cpu_imem_master_m_awlock
output cpu_imem_master_awlock;
// value method cpu_imem_master_m_awcache
output [3 : 0] cpu_imem_master_awcache;
// value method cpu_imem_master_m_awprot
output [2 : 0] cpu_imem_master_awprot;
// value method cpu_imem_master_m_awqos
output [3 : 0] cpu_imem_master_awqos;
// value method cpu_imem_master_m_awregion
output [3 : 0] cpu_imem_master_awregion;
// value method cpu_imem_master_m_awuser
// action method cpu_imem_master_m_awready
input cpu_imem_master_awready;
// value method cpu_imem_master_m_wvalid
output cpu_imem_master_wvalid;
// value method cpu_imem_master_m_wdata
output [63 : 0] cpu_imem_master_wdata;
// value method cpu_imem_master_m_wstrb
output [7 : 0] cpu_imem_master_wstrb;
// value method cpu_imem_master_m_wlast
output cpu_imem_master_wlast;
// value method cpu_imem_master_m_wuser
// action method cpu_imem_master_m_wready
input cpu_imem_master_wready;
// action method cpu_imem_master_m_bvalid
input cpu_imem_master_bvalid;
input [3 : 0] cpu_imem_master_bid;
input [1 : 0] cpu_imem_master_bresp;
// value method cpu_imem_master_m_bready
output cpu_imem_master_bready;
// value method cpu_imem_master_m_arvalid
output cpu_imem_master_arvalid;
// value method cpu_imem_master_m_arid
output [3 : 0] cpu_imem_master_arid;
// value method cpu_imem_master_m_araddr
output [63 : 0] cpu_imem_master_araddr;
// value method cpu_imem_master_m_arlen
output [7 : 0] cpu_imem_master_arlen;
// value method cpu_imem_master_m_arsize
output [2 : 0] cpu_imem_master_arsize;
// value method cpu_imem_master_m_arburst
output [1 : 0] cpu_imem_master_arburst;
// value method cpu_imem_master_m_arlock
output cpu_imem_master_arlock;
// value method cpu_imem_master_m_arcache
output [3 : 0] cpu_imem_master_arcache;
// value method cpu_imem_master_m_arprot
output [2 : 0] cpu_imem_master_arprot;
// value method cpu_imem_master_m_arqos
output [3 : 0] cpu_imem_master_arqos;
// value method cpu_imem_master_m_arregion
output [3 : 0] cpu_imem_master_arregion;
// value method cpu_imem_master_m_aruser
// action method cpu_imem_master_m_arready
input cpu_imem_master_arready;
// action method cpu_imem_master_m_rvalid
input cpu_imem_master_rvalid;
input [3 : 0] cpu_imem_master_rid;
input [63 : 0] cpu_imem_master_rdata;
input [1 : 0] cpu_imem_master_rresp;
input cpu_imem_master_rlast;
// value method cpu_imem_master_m_rready
output cpu_imem_master_rready;
// value method cpu_dmem_master_m_awvalid
output cpu_dmem_master_awvalid;
// value method cpu_dmem_master_m_awid
output [3 : 0] cpu_dmem_master_awid;
// value method cpu_dmem_master_m_awaddr
output [63 : 0] cpu_dmem_master_awaddr;
// value method cpu_dmem_master_m_awlen
output [7 : 0] cpu_dmem_master_awlen;
// value method cpu_dmem_master_m_awsize
output [2 : 0] cpu_dmem_master_awsize;
// value method cpu_dmem_master_m_awburst
output [1 : 0] cpu_dmem_master_awburst;
// value method cpu_dmem_master_m_awlock
output cpu_dmem_master_awlock;
// value method cpu_dmem_master_m_awcache
output [3 : 0] cpu_dmem_master_awcache;
// value method cpu_dmem_master_m_awprot
output [2 : 0] cpu_dmem_master_awprot;
// value method cpu_dmem_master_m_awqos
output [3 : 0] cpu_dmem_master_awqos;
// value method cpu_dmem_master_m_awregion
output [3 : 0] cpu_dmem_master_awregion;
// value method cpu_dmem_master_m_awuser
// action method cpu_dmem_master_m_awready
input cpu_dmem_master_awready;
// value method cpu_dmem_master_m_wvalid
output cpu_dmem_master_wvalid;
// value method cpu_dmem_master_m_wdata
output [63 : 0] cpu_dmem_master_wdata;
// value method cpu_dmem_master_m_wstrb
output [7 : 0] cpu_dmem_master_wstrb;
// value method cpu_dmem_master_m_wlast
output cpu_dmem_master_wlast;
// value method cpu_dmem_master_m_wuser
// action method cpu_dmem_master_m_wready
input cpu_dmem_master_wready;
// action method cpu_dmem_master_m_bvalid
input cpu_dmem_master_bvalid;
input [3 : 0] cpu_dmem_master_bid;
input [1 : 0] cpu_dmem_master_bresp;
// value method cpu_dmem_master_m_bready
output cpu_dmem_master_bready;
// value method cpu_dmem_master_m_arvalid
output cpu_dmem_master_arvalid;
// value method cpu_dmem_master_m_arid
output [3 : 0] cpu_dmem_master_arid;
// value method cpu_dmem_master_m_araddr
output [63 : 0] cpu_dmem_master_araddr;
// value method cpu_dmem_master_m_arlen
output [7 : 0] cpu_dmem_master_arlen;
// value method cpu_dmem_master_m_arsize
output [2 : 0] cpu_dmem_master_arsize;
// value method cpu_dmem_master_m_arburst
output [1 : 0] cpu_dmem_master_arburst;
// value method cpu_dmem_master_m_arlock
output cpu_dmem_master_arlock;
// value method cpu_dmem_master_m_arcache
output [3 : 0] cpu_dmem_master_arcache;
// value method cpu_dmem_master_m_arprot
output [2 : 0] cpu_dmem_master_arprot;
// value method cpu_dmem_master_m_arqos
output [3 : 0] cpu_dmem_master_arqos;
// value method cpu_dmem_master_m_arregion
output [3 : 0] cpu_dmem_master_arregion;
// value method cpu_dmem_master_m_aruser
// action method cpu_dmem_master_m_arready
input cpu_dmem_master_arready;
// action method cpu_dmem_master_m_rvalid
input cpu_dmem_master_rvalid;
input [3 : 0] cpu_dmem_master_rid;
input [63 : 0] cpu_dmem_master_rdata;
input [1 : 0] cpu_dmem_master_rresp;
input cpu_dmem_master_rlast;
// value method cpu_dmem_master_m_rready
output cpu_dmem_master_rready;
// action method core_external_interrupt_sources_0_m_interrupt_req
input core_external_interrupt_sources_0_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_1_m_interrupt_req
input core_external_interrupt_sources_1_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_2_m_interrupt_req
input core_external_interrupt_sources_2_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_3_m_interrupt_req
input core_external_interrupt_sources_3_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_4_m_interrupt_req
input core_external_interrupt_sources_4_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_5_m_interrupt_req
input core_external_interrupt_sources_5_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_6_m_interrupt_req
input core_external_interrupt_sources_6_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_7_m_interrupt_req
input core_external_interrupt_sources_7_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_8_m_interrupt_req
input core_external_interrupt_sources_8_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_9_m_interrupt_req
input core_external_interrupt_sources_9_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_10_m_interrupt_req
input core_external_interrupt_sources_10_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_11_m_interrupt_req
input core_external_interrupt_sources_11_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_12_m_interrupt_req
input core_external_interrupt_sources_12_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_13_m_interrupt_req
input core_external_interrupt_sources_13_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_14_m_interrupt_req
input core_external_interrupt_sources_14_m_interrupt_req_set_not_clear;
// action method core_external_interrupt_sources_15_m_interrupt_req
input core_external_interrupt_sources_15_m_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method dmi_read_addr
input [6 : 0] dmi_read_addr_dm_addr;
input EN_dmi_read_addr;
output RDY_dmi_read_addr;
// actionvalue method dmi_read_data
input EN_dmi_read_data;
output [31 : 0] dmi_read_data;
output RDY_dmi_read_data;
// action method dmi_write
input [6 : 0] dmi_write_dm_addr;
input [31 : 0] dmi_write_dm_word;
input EN_dmi_write;
output RDY_dmi_write;
// actionvalue method ndm_reset_client_request_get
input EN_ndm_reset_client_request_get;
output ndm_reset_client_request_get;
output RDY_ndm_reset_client_request_get;
// action method ndm_reset_client_response_put
input ndm_reset_client_response_put;
input EN_ndm_reset_client_response_put;
output RDY_ndm_reset_client_response_put;
// actionvalue method tv_verifier_info_get_get
input EN_tv_verifier_info_get_get;
output [607 : 0] tv_verifier_info_get_get;
output RDY_tv_verifier_info_get_get;
// signals for module outputs
wire [607 : 0] tv_verifier_info_get_get;
wire [63 : 0] cpu_dmem_master_araddr,
cpu_dmem_master_awaddr,
cpu_dmem_master_wdata,
cpu_imem_master_araddr,
cpu_imem_master_awaddr,
cpu_imem_master_wdata;
wire [31 : 0] dmi_read_data;
wire [7 : 0] cpu_dmem_master_arlen,
cpu_dmem_master_awlen,
cpu_dmem_master_wstrb,
cpu_imem_master_arlen,
cpu_imem_master_awlen,
cpu_imem_master_wstrb;
wire [3 : 0] cpu_dmem_master_arcache,
cpu_dmem_master_arid,
cpu_dmem_master_arqos,
cpu_dmem_master_arregion,
cpu_dmem_master_awcache,
cpu_dmem_master_awid,
cpu_dmem_master_awqos,
cpu_dmem_master_awregion,
cpu_imem_master_arcache,
cpu_imem_master_arid,
cpu_imem_master_arqos,
cpu_imem_master_arregion,
cpu_imem_master_awcache,
cpu_imem_master_awid,
cpu_imem_master_awqos,
cpu_imem_master_awregion;
wire [2 : 0] cpu_dmem_master_arprot,
cpu_dmem_master_arsize,
cpu_dmem_master_awprot,
cpu_dmem_master_awsize,
cpu_imem_master_arprot,
cpu_imem_master_arsize,
cpu_imem_master_awprot,
cpu_imem_master_awsize;
wire [1 : 0] cpu_dmem_master_arburst,
cpu_dmem_master_awburst,
cpu_imem_master_arburst,
cpu_imem_master_awburst;
wire RDY_dmi_read_addr,
RDY_dmi_read_data,
RDY_dmi_write,
RDY_ndm_reset_client_request_get,
RDY_ndm_reset_client_response_put,
RDY_set_verbosity,
RDY_start,
RDY_tv_verifier_info_get_get,
cpu_dmem_master_arlock,
cpu_dmem_master_arvalid,
cpu_dmem_master_awlock,
cpu_dmem_master_awvalid,
cpu_dmem_master_bready,
cpu_dmem_master_rready,
cpu_dmem_master_wlast,
cpu_dmem_master_wvalid,
cpu_imem_master_arlock,
cpu_imem_master_arvalid,
cpu_imem_master_awlock,
cpu_imem_master_awvalid,
cpu_imem_master_bready,
cpu_imem_master_rready,
cpu_imem_master_wlast,
cpu_imem_master_wvalid,
ndm_reset_client_request_get;
// register rg_fromhost_addr
reg [63 : 0] rg_fromhost_addr;
wire [63 : 0] rg_fromhost_addr$D_IN;
wire rg_fromhost_addr$EN;
// register rg_hart0_reset_delay
reg [7 : 0] rg_hart0_reset_delay;
wire [7 : 0] rg_hart0_reset_delay$D_IN;
wire rg_hart0_reset_delay$EN;
// register rg_tohost_addr
reg [63 : 0] rg_tohost_addr;
wire [63 : 0] rg_tohost_addr$D_IN;
wire rg_tohost_addr$EN;
// ports of submodule debug_module
wire [76 : 0] debug_module$hart0_csr_mem_client_request_get;
wire [69 : 0] debug_module$hart0_gpr_mem_client_request_get;
wire [64 : 0] debug_module$hart0_csr_mem_client_response_put,
debug_module$hart0_fpr_mem_client_response_put,
debug_module$hart0_gpr_mem_client_response_put;
wire [63 : 0] debug_module$master_araddr,
debug_module$master_awaddr,
debug_module$master_rdata,
debug_module$master_wdata;
wire [31 : 0] debug_module$dmi_read_data, debug_module$dmi_write_dm_word;
wire [7 : 0] debug_module$master_arlen,
debug_module$master_awlen,
debug_module$master_wstrb;
wire [6 : 0] debug_module$dmi_read_addr_dm_addr,
debug_module$dmi_write_dm_addr;
wire [3 : 0] debug_module$hart0_get_other_req_get,
debug_module$master_arcache,
debug_module$master_arid,
debug_module$master_arqos,
debug_module$master_arregion,
debug_module$master_awcache,
debug_module$master_awid,
debug_module$master_awqos,
debug_module$master_awregion,
debug_module$master_bid,
debug_module$master_rid;
wire [2 : 0] debug_module$master_arprot,
debug_module$master_arsize,
debug_module$master_awprot,
debug_module$master_awsize;
wire [1 : 0] debug_module$master_arburst,
debug_module$master_awburst,
debug_module$master_bresp,
debug_module$master_rresp;
wire debug_module$EN_dmi_read_addr,
debug_module$EN_dmi_read_data,
debug_module$EN_dmi_write,
debug_module$EN_hart0_client_run_halt_request_get,
debug_module$EN_hart0_client_run_halt_response_put,
debug_module$EN_hart0_csr_mem_client_request_get,
debug_module$EN_hart0_csr_mem_client_response_put,
debug_module$EN_hart0_fpr_mem_client_request_get,
debug_module$EN_hart0_fpr_mem_client_response_put,
debug_module$EN_hart0_get_other_req_get,
debug_module$EN_hart0_gpr_mem_client_request_get,
debug_module$EN_hart0_gpr_mem_client_response_put,
debug_module$EN_hart0_reset_client_request_get,
debug_module$EN_hart0_reset_client_response_put,
debug_module$EN_ndm_reset_client_request_get,
debug_module$EN_ndm_reset_client_response_put,
debug_module$RDY_dmi_read_addr,
debug_module$RDY_dmi_read_data,
debug_module$RDY_dmi_write,
debug_module$RDY_hart0_client_run_halt_request_get,
debug_module$RDY_hart0_client_run_halt_response_put,
debug_module$RDY_hart0_csr_mem_client_request_get,
debug_module$RDY_hart0_csr_mem_client_response_put,
debug_module$RDY_hart0_get_other_req_get,
debug_module$RDY_hart0_gpr_mem_client_request_get,
debug_module$RDY_hart0_gpr_mem_client_response_put,
debug_module$RDY_hart0_reset_client_request_get,
debug_module$RDY_hart0_reset_client_response_put,
debug_module$RDY_ndm_reset_client_request_get,
debug_module$RDY_ndm_reset_client_response_put,
debug_module$hart0_client_run_halt_request_get,
debug_module$hart0_client_run_halt_response_put,
debug_module$hart0_reset_client_response_put,
debug_module$master_arlock,
debug_module$master_arready,
debug_module$master_arvalid,
debug_module$master_awlock,
debug_module$master_awready,
debug_module$master_awvalid,
debug_module$master_bready,
debug_module$master_bvalid,
debug_module$master_rlast,
debug_module$master_rready,
debug_module$master_rvalid,
debug_module$master_wlast,
debug_module$master_wready,
debug_module$master_wvalid,
debug_module$ndm_reset_client_request_get,
debug_module$ndm_reset_client_response_put;
// ports of submodule dm_csr_tap
wire [426 : 0] dm_csr_tap$trace_data_out_get;
wire [76 : 0] dm_csr_tap$client_request_get, dm_csr_tap$server_request_put;
wire [64 : 0] dm_csr_tap$client_response_put,
dm_csr_tap$server_response_get;
wire dm_csr_tap$EN_client_request_get,
dm_csr_tap$EN_client_response_put,
dm_csr_tap$EN_server_request_put,
dm_csr_tap$EN_server_response_get,
dm_csr_tap$EN_trace_data_out_get,
dm_csr_tap$RDY_client_request_get,
dm_csr_tap$RDY_client_response_put,
dm_csr_tap$RDY_server_request_put,
dm_csr_tap$RDY_server_response_get,
dm_csr_tap$RDY_trace_data_out_get;
// ports of submodule dm_gpr_tap_ifc
wire [426 : 0] dm_gpr_tap_ifc$trace_data_out_get;
wire [69 : 0] dm_gpr_tap_ifc$client_request_get,
dm_gpr_tap_ifc$server_request_put;
wire [64 : 0] dm_gpr_tap_ifc$client_response_put,
dm_gpr_tap_ifc$server_response_get;
wire dm_gpr_tap_ifc$EN_client_request_get,
dm_gpr_tap_ifc$EN_client_response_put,
dm_gpr_tap_ifc$EN_server_request_put,
dm_gpr_tap_ifc$EN_server_response_get,
dm_gpr_tap_ifc$EN_trace_data_out_get,
dm_gpr_tap_ifc$RDY_client_request_get,
dm_gpr_tap_ifc$RDY_client_response_put,
dm_gpr_tap_ifc$RDY_server_request_put,
dm_gpr_tap_ifc$RDY_server_response_get,
dm_gpr_tap_ifc$RDY_trace_data_out_get;
// ports of submodule dm_hart0_reset_controller
wire dm_hart0_reset_controller$ASSERT_IN, dm_hart0_reset_controller$OUT_RST;
// ports of submodule dm_mem_tap
wire [426 : 0] dm_mem_tap$trace_data_out_get;
wire [63 : 0] dm_mem_tap$master_araddr,
dm_mem_tap$master_awaddr,
dm_mem_tap$master_rdata,
dm_mem_tap$master_wdata,
dm_mem_tap$slave_araddr,
dm_mem_tap$slave_awaddr,
dm_mem_tap$slave_rdata,
dm_mem_tap$slave_wdata;
wire [7 : 0] dm_mem_tap$master_arlen,
dm_mem_tap$master_awlen,
dm_mem_tap$master_wstrb,
dm_mem_tap$slave_arlen,
dm_mem_tap$slave_awlen,
dm_mem_tap$slave_wstrb;
wire [3 : 0] dm_mem_tap$master_arcache,
dm_mem_tap$master_arid,
dm_mem_tap$master_arqos,
dm_mem_tap$master_arregion,
dm_mem_tap$master_awcache,
dm_mem_tap$master_awid,
dm_mem_tap$master_awqos,
dm_mem_tap$master_awregion,
dm_mem_tap$master_bid,
dm_mem_tap$master_rid,
dm_mem_tap$slave_arcache,
dm_mem_tap$slave_arid,
dm_mem_tap$slave_arqos,
dm_mem_tap$slave_arregion,
dm_mem_tap$slave_awcache,
dm_mem_tap$slave_awid,
dm_mem_tap$slave_awqos,
dm_mem_tap$slave_awregion,
dm_mem_tap$slave_bid,
dm_mem_tap$slave_rid;
wire [2 : 0] dm_mem_tap$master_arprot,
dm_mem_tap$master_arsize,
dm_mem_tap$master_awprot,
dm_mem_tap$master_awsize,
dm_mem_tap$slave_arprot,
dm_mem_tap$slave_arsize,
dm_mem_tap$slave_awprot,
dm_mem_tap$slave_awsize;
wire [1 : 0] dm_mem_tap$master_arburst,
dm_mem_tap$master_awburst,
dm_mem_tap$master_bresp,
dm_mem_tap$master_rresp,
dm_mem_tap$slave_arburst,
dm_mem_tap$slave_awburst,
dm_mem_tap$slave_bresp,
dm_mem_tap$slave_rresp;
wire dm_mem_tap$EN_trace_data_out_get,
dm_mem_tap$RDY_trace_data_out_get,
dm_mem_tap$master_arlock,
dm_mem_tap$master_arready,
dm_mem_tap$master_arvalid,
dm_mem_tap$master_awlock,
dm_mem_tap$master_awready,
dm_mem_tap$master_awvalid,
dm_mem_tap$master_bready,
dm_mem_tap$master_bvalid,
dm_mem_tap$master_rlast,
dm_mem_tap$master_rready,
dm_mem_tap$master_rvalid,
dm_mem_tap$master_wlast,
dm_mem_tap$master_wready,
dm_mem_tap$master_wvalid,
dm_mem_tap$slave_arlock,
dm_mem_tap$slave_arready,
dm_mem_tap$slave_arvalid,
dm_mem_tap$slave_awlock,
dm_mem_tap$slave_awready,
dm_mem_tap$slave_awvalid,
dm_mem_tap$slave_bready,
dm_mem_tap$slave_bvalid,
dm_mem_tap$slave_rlast,
dm_mem_tap$slave_rready,
dm_mem_tap$slave_rvalid,
dm_mem_tap$slave_wlast,
dm_mem_tap$slave_wready,
dm_mem_tap$slave_wvalid;
// ports of submodule fabric_2x3
wire [63 : 0] fabric_2x3$v_from_masters_0_araddr,
fabric_2x3$v_from_masters_0_awaddr,
fabric_2x3$v_from_masters_0_rdata,
fabric_2x3$v_from_masters_0_wdata,
fabric_2x3$v_from_masters_1_araddr,
fabric_2x3$v_from_masters_1_awaddr,
fabric_2x3$v_from_masters_1_rdata,
fabric_2x3$v_from_masters_1_wdata,
fabric_2x3$v_to_slaves_0_araddr,
fabric_2x3$v_to_slaves_0_awaddr,
fabric_2x3$v_to_slaves_0_rdata,
fabric_2x3$v_to_slaves_0_wdata,
fabric_2x3$v_to_slaves_1_araddr,
fabric_2x3$v_to_slaves_1_awaddr,
fabric_2x3$v_to_slaves_1_rdata,
fabric_2x3$v_to_slaves_1_wdata,
fabric_2x3$v_to_slaves_2_araddr,
fabric_2x3$v_to_slaves_2_awaddr,
fabric_2x3$v_to_slaves_2_rdata,
fabric_2x3$v_to_slaves_2_wdata;
wire [7 : 0] fabric_2x3$v_from_masters_0_arlen,
fabric_2x3$v_from_masters_0_awlen,
fabric_2x3$v_from_masters_0_wstrb,
fabric_2x3$v_from_masters_1_arlen,
fabric_2x3$v_from_masters_1_awlen,
fabric_2x3$v_from_masters_1_wstrb,
fabric_2x3$v_to_slaves_0_arlen,
fabric_2x3$v_to_slaves_0_awlen,
fabric_2x3$v_to_slaves_0_wstrb,
fabric_2x3$v_to_slaves_1_arlen,
fabric_2x3$v_to_slaves_1_awlen,
fabric_2x3$v_to_slaves_1_wstrb,
fabric_2x3$v_to_slaves_2_arlen,
fabric_2x3$v_to_slaves_2_awlen,
fabric_2x3$v_to_slaves_2_wstrb;
wire [3 : 0] fabric_2x3$set_verbosity_verbosity,
fabric_2x3$v_from_masters_0_arcache,
fabric_2x3$v_from_masters_0_arid,
fabric_2x3$v_from_masters_0_arqos,
fabric_2x3$v_from_masters_0_arregion,
fabric_2x3$v_from_masters_0_awcache,
fabric_2x3$v_from_masters_0_awid,
fabric_2x3$v_from_masters_0_awqos,
fabric_2x3$v_from_masters_0_awregion,
fabric_2x3$v_from_masters_0_bid,
fabric_2x3$v_from_masters_0_rid,
fabric_2x3$v_from_masters_1_arcache,
fabric_2x3$v_from_masters_1_arid,
fabric_2x3$v_from_masters_1_arqos,
fabric_2x3$v_from_masters_1_arregion,
fabric_2x3$v_from_masters_1_awcache,
fabric_2x3$v_from_masters_1_awid,
fabric_2x3$v_from_masters_1_awqos,
fabric_2x3$v_from_masters_1_awregion,
fabric_2x3$v_from_masters_1_bid,
fabric_2x3$v_from_masters_1_rid,
fabric_2x3$v_to_slaves_0_arcache,
fabric_2x3$v_to_slaves_0_arid,
fabric_2x3$v_to_slaves_0_arqos,
fabric_2x3$v_to_slaves_0_arregion,
fabric_2x3$v_to_slaves_0_awcache,
fabric_2x3$v_to_slaves_0_awid,
fabric_2x3$v_to_slaves_0_awqos,
fabric_2x3$v_to_slaves_0_awregion,
fabric_2x3$v_to_slaves_0_bid,
fabric_2x3$v_to_slaves_0_rid,
fabric_2x3$v_to_slaves_1_arcache,
fabric_2x3$v_to_slaves_1_arid,
fabric_2x3$v_to_slaves_1_arqos,
fabric_2x3$v_to_slaves_1_arregion,
fabric_2x3$v_to_slaves_1_awcache,
fabric_2x3$v_to_slaves_1_awid,
fabric_2x3$v_to_slaves_1_awqos,
fabric_2x3$v_to_slaves_1_awregion,
fabric_2x3$v_to_slaves_1_bid,
fabric_2x3$v_to_slaves_1_rid,
fabric_2x3$v_to_slaves_2_arcache,
fabric_2x3$v_to_slaves_2_arid,
fabric_2x3$v_to_slaves_2_arqos,
fabric_2x3$v_to_slaves_2_arregion,
fabric_2x3$v_to_slaves_2_awcache,
fabric_2x3$v_to_slaves_2_awid,
fabric_2x3$v_to_slaves_2_awqos,
fabric_2x3$v_to_slaves_2_awregion,
fabric_2x3$v_to_slaves_2_bid,
fabric_2x3$v_to_slaves_2_rid;
wire [2 : 0] fabric_2x3$v_from_masters_0_arprot,
fabric_2x3$v_from_masters_0_arsize,
fabric_2x3$v_from_masters_0_awprot,
fabric_2x3$v_from_masters_0_awsize,
fabric_2x3$v_from_masters_1_arprot,
fabric_2x3$v_from_masters_1_arsize,
fabric_2x3$v_from_masters_1_awprot,
fabric_2x3$v_from_masters_1_awsize,
fabric_2x3$v_to_slaves_0_arprot,
fabric_2x3$v_to_slaves_0_arsize,
fabric_2x3$v_to_slaves_0_awprot,
fabric_2x3$v_to_slaves_0_awsize,
fabric_2x3$v_to_slaves_1_arprot,
fabric_2x3$v_to_slaves_1_arsize,
fabric_2x3$v_to_slaves_1_awprot,
fabric_2x3$v_to_slaves_1_awsize,
fabric_2x3$v_to_slaves_2_arprot,
fabric_2x3$v_to_slaves_2_arsize,
fabric_2x3$v_to_slaves_2_awprot,
fabric_2x3$v_to_slaves_2_awsize;
wire [1 : 0] fabric_2x3$v_from_masters_0_arburst,
fabric_2x3$v_from_masters_0_awburst,
fabric_2x3$v_from_masters_0_bresp,
fabric_2x3$v_from_masters_0_rresp,
fabric_2x3$v_from_masters_1_arburst,
fabric_2x3$v_from_masters_1_awburst,
fabric_2x3$v_from_masters_1_bresp,
fabric_2x3$v_from_masters_1_rresp,
fabric_2x3$v_to_slaves_0_arburst,
fabric_2x3$v_to_slaves_0_awburst,
fabric_2x3$v_to_slaves_0_bresp,
fabric_2x3$v_to_slaves_0_rresp,
fabric_2x3$v_to_slaves_1_arburst,
fabric_2x3$v_to_slaves_1_awburst,
fabric_2x3$v_to_slaves_1_bresp,
fabric_2x3$v_to_slaves_1_rresp,
fabric_2x3$v_to_slaves_2_arburst,
fabric_2x3$v_to_slaves_2_awburst,
fabric_2x3$v_to_slaves_2_bresp,
fabric_2x3$v_to_slaves_2_rresp;
wire fabric_2x3$EN_reset,
fabric_2x3$EN_set_verbosity,
fabric_2x3$v_from_masters_0_arlock,
fabric_2x3$v_from_masters_0_arready,
fabric_2x3$v_from_masters_0_arvalid,
fabric_2x3$v_from_masters_0_awlock,
fabric_2x3$v_from_masters_0_awready,
fabric_2x3$v_from_masters_0_awvalid,
fabric_2x3$v_from_masters_0_bready,
fabric_2x3$v_from_masters_0_bvalid,
fabric_2x3$v_from_masters_0_rlast,
fabric_2x3$v_from_masters_0_rready,
fabric_2x3$v_from_masters_0_rvalid,
fabric_2x3$v_from_masters_0_wlast,
fabric_2x3$v_from_masters_0_wready,
fabric_2x3$v_from_masters_0_wvalid,
fabric_2x3$v_from_masters_1_arlock,
fabric_2x3$v_from_masters_1_arready,
fabric_2x3$v_from_masters_1_arvalid,
fabric_2x3$v_from_masters_1_awlock,
fabric_2x3$v_from_masters_1_awready,
fabric_2x3$v_from_masters_1_awvalid,
fabric_2x3$v_from_masters_1_bready,
fabric_2x3$v_from_masters_1_bvalid,
fabric_2x3$v_from_masters_1_rlast,
fabric_2x3$v_from_masters_1_rready,
fabric_2x3$v_from_masters_1_rvalid,
fabric_2x3$v_from_masters_1_wlast,
fabric_2x3$v_from_masters_1_wready,
fabric_2x3$v_from_masters_1_wvalid,
fabric_2x3$v_to_slaves_0_arlock,
fabric_2x3$v_to_slaves_0_arready,
fabric_2x3$v_to_slaves_0_arvalid,
fabric_2x3$v_to_slaves_0_awlock,
fabric_2x3$v_to_slaves_0_awready,
fabric_2x3$v_to_slaves_0_awvalid,
fabric_2x3$v_to_slaves_0_bready,
fabric_2x3$v_to_slaves_0_bvalid,
fabric_2x3$v_to_slaves_0_rlast,
fabric_2x3$v_to_slaves_0_rready,
fabric_2x3$v_to_slaves_0_rvalid,
fabric_2x3$v_to_slaves_0_wlast,
fabric_2x3$v_to_slaves_0_wready,
fabric_2x3$v_to_slaves_0_wvalid,
fabric_2x3$v_to_slaves_1_arlock,
fabric_2x3$v_to_slaves_1_arready,
fabric_2x3$v_to_slaves_1_arvalid,
fabric_2x3$v_to_slaves_1_awlock,
fabric_2x3$v_to_slaves_1_awready,
fabric_2x3$v_to_slaves_1_awvalid,
fabric_2x3$v_to_slaves_1_bready,
fabric_2x3$v_to_slaves_1_bvalid,
fabric_2x3$v_to_slaves_1_rlast,
fabric_2x3$v_to_slaves_1_rready,
fabric_2x3$v_to_slaves_1_rvalid,
fabric_2x3$v_to_slaves_1_wlast,
fabric_2x3$v_to_slaves_1_wready,
fabric_2x3$v_to_slaves_1_wvalid,
fabric_2x3$v_to_slaves_2_arlock,
fabric_2x3$v_to_slaves_2_arready,
fabric_2x3$v_to_slaves_2_arvalid,
fabric_2x3$v_to_slaves_2_awlock,
fabric_2x3$v_to_slaves_2_awready,
fabric_2x3$v_to_slaves_2_awvalid,
fabric_2x3$v_to_slaves_2_bready,
fabric_2x3$v_to_slaves_2_bvalid,
fabric_2x3$v_to_slaves_2_rlast,
fabric_2x3$v_to_slaves_2_rready,
fabric_2x3$v_to_slaves_2_rvalid,
fabric_2x3$v_to_slaves_2_wlast,
fabric_2x3$v_to_slaves_2_wready,
fabric_2x3$v_to_slaves_2_wvalid;
// ports of submodule hart0_reset
wire hart0_reset$RST_OUT;
// ports of submodule plic
wire [63 : 0] plic$axi4_slave_araddr,
plic$axi4_slave_awaddr,
plic$axi4_slave_rdata,
plic$axi4_slave_wdata,
plic$set_addr_map_addr_base,
plic$set_addr_map_addr_lim;
wire [7 : 0] plic$axi4_slave_arlen,
plic$axi4_slave_awlen,
plic$axi4_slave_wstrb;
wire [3 : 0] plic$axi4_slave_arcache,
plic$axi4_slave_arid,
plic$axi4_slave_arqos,
plic$axi4_slave_arregion,
plic$axi4_slave_awcache,
plic$axi4_slave_awid,
plic$axi4_slave_awqos,
plic$axi4_slave_awregion,
plic$axi4_slave_bid,
plic$axi4_slave_rid,
plic$set_verbosity_verbosity;
wire [2 : 0] plic$axi4_slave_arprot,
plic$axi4_slave_arsize,
plic$axi4_slave_awprot,
plic$axi4_slave_awsize;
wire [1 : 0] plic$axi4_slave_arburst,
plic$axi4_slave_awburst,
plic$axi4_slave_bresp,
plic$axi4_slave_rresp;
wire plic$EN_server_reset_request_put,
plic$EN_server_reset_response_get,
plic$EN_set_addr_map,
plic$EN_set_verbosity,
plic$EN_show_PLIC_state,
plic$axi4_slave_arlock,
plic$axi4_slave_arready,
plic$axi4_slave_arvalid,
plic$axi4_slave_awlock,
plic$axi4_slave_awready,
plic$axi4_slave_awvalid,
plic$axi4_slave_bready,
plic$axi4_slave_bvalid,
plic$axi4_slave_rlast,
plic$axi4_slave_rready,
plic$axi4_slave_rvalid,
plic$axi4_slave_wlast,
plic$axi4_slave_wready,
plic$axi4_slave_wvalid,
plic$v_sources_0_m_interrupt_req_set_not_clear,
plic$v_sources_10_m_interrupt_req_set_not_clear,
plic$v_sources_11_m_interrupt_req_set_not_clear,
plic$v_sources_12_m_interrupt_req_set_not_clear,
plic$v_sources_13_m_interrupt_req_set_not_clear,
plic$v_sources_14_m_interrupt_req_set_not_clear,
plic$v_sources_15_m_interrupt_req_set_not_clear,
plic$v_sources_1_m_interrupt_req_set_not_clear,
plic$v_sources_2_m_interrupt_req_set_not_clear,
plic$v_sources_3_m_interrupt_req_set_not_clear,
plic$v_sources_4_m_interrupt_req_set_not_clear,
plic$v_sources_5_m_interrupt_req_set_not_clear,
plic$v_sources_6_m_interrupt_req_set_not_clear,
plic$v_sources_7_m_interrupt_req_set_not_clear,
plic$v_sources_8_m_interrupt_req_set_not_clear,
plic$v_sources_9_m_interrupt_req_set_not_clear,
plic$v_targets_0_m_eip,
plic$v_targets_1_m_eip;
// ports of submodule proc
wire [861 : 0] proc$v_to_TV_0_get, proc$v_to_TV_1_get;
wire [76 : 0] proc$hart0_csr_mem_server_request_put;
wire [69 : 0] proc$hart0_fpr_mem_server_request_put,
proc$hart0_gpr_mem_server_request_put;
wire [64 : 0] proc$hart0_csr_mem_server_response_get,
proc$hart0_gpr_mem_server_response_get;
wire [63 : 0] proc$debug_module_mem_server_araddr,
proc$debug_module_mem_server_awaddr,
proc$debug_module_mem_server_rdata,
proc$debug_module_mem_server_wdata,
proc$master0_araddr,
proc$master0_awaddr,
proc$master0_rdata,
proc$master0_wdata,
proc$master1_araddr,
proc$master1_awaddr,
proc$master1_rdata,
proc$master1_wdata,
proc$start_fromhostAddr,
proc$start_startpc,
proc$start_tohostAddr;
wire [7 : 0] proc$debug_module_mem_server_arlen,
proc$debug_module_mem_server_awlen,
proc$debug_module_mem_server_wstrb,
proc$master0_arlen,
proc$master0_awlen,
proc$master0_wstrb,
proc$master1_arlen,
proc$master1_awlen,
proc$master1_wstrb;
wire [3 : 0] proc$debug_module_mem_server_arcache,
proc$debug_module_mem_server_arid,
proc$debug_module_mem_server_arqos,
proc$debug_module_mem_server_arregion,
proc$debug_module_mem_server_awcache,
proc$debug_module_mem_server_awid,
proc$debug_module_mem_server_awqos,
proc$debug_module_mem_server_awregion,
proc$debug_module_mem_server_bid,
proc$debug_module_mem_server_rid,
proc$hart0_put_other_req_put,
proc$master0_arcache,
proc$master0_arid,
proc$master0_arqos,
proc$master0_arregion,
proc$master0_awcache,
proc$master0_awid,
proc$master0_awqos,
proc$master0_awregion,
proc$master0_bid,
proc$master0_rid,
proc$master1_arcache,
proc$master1_arid,
proc$master1_arqos,
proc$master1_arregion,
proc$master1_awcache,
proc$master1_awid,
proc$master1_awqos,
proc$master1_awregion,
proc$master1_bid,
proc$master1_rid,
proc$set_verbosity_verbosity;
wire [2 : 0] proc$debug_module_mem_server_arprot,
proc$debug_module_mem_server_arsize,
proc$debug_module_mem_server_awprot,
proc$debug_module_mem_server_awsize,
proc$master0_arprot,
proc$master0_arsize,
proc$master0_awprot,
proc$master0_awsize,
proc$master1_arprot,
proc$master1_arsize,
proc$master1_awprot,
proc$master1_awsize;
wire [1 : 0] proc$debug_module_mem_server_arburst,
proc$debug_module_mem_server_awburst,
proc$debug_module_mem_server_bresp,
proc$debug_module_mem_server_rresp,
proc$master0_arburst,
proc$master0_awburst,
proc$master0_bresp,
proc$master0_rresp,
proc$master1_arburst,
proc$master1_awburst,
proc$master1_bresp,
proc$master1_rresp;
wire proc$EN_hart0_csr_mem_server_request_put,
proc$EN_hart0_csr_mem_server_response_get,
proc$EN_hart0_fpr_mem_server_request_put,
proc$EN_hart0_fpr_mem_server_response_get,
proc$EN_hart0_gpr_mem_server_request_put,
proc$EN_hart0_gpr_mem_server_response_get,
proc$EN_hart0_put_other_req_put,
proc$EN_hart0_run_halt_server_request_put,
proc$EN_hart0_run_halt_server_response_get,
proc$EN_set_verbosity,
proc$EN_start,
proc$EN_v_to_TV_0_get,
proc$EN_v_to_TV_1_get,
proc$RDY_hart0_csr_mem_server_request_put,
proc$RDY_hart0_csr_mem_server_response_get,
proc$RDY_hart0_gpr_mem_server_request_put,
proc$RDY_hart0_gpr_mem_server_response_get,
proc$RDY_hart0_run_halt_server_request_put,
proc$RDY_hart0_run_halt_server_response_get,
proc$RDY_start,
proc$RDY_v_to_TV_0_get,
proc$RDY_v_to_TV_1_get,
proc$debug_module_mem_server_arlock,
proc$debug_module_mem_server_arready,
proc$debug_module_mem_server_arvalid,
proc$debug_module_mem_server_awlock,
proc$debug_module_mem_server_awready,
proc$debug_module_mem_server_awvalid,
proc$debug_module_mem_server_bready,
proc$debug_module_mem_server_bvalid,
proc$debug_module_mem_server_rlast,
proc$debug_module_mem_server_rready,
proc$debug_module_mem_server_rvalid,
proc$debug_module_mem_server_wlast,
proc$debug_module_mem_server_wready,
proc$debug_module_mem_server_wvalid,
proc$hart0_run_halt_server_request_put,
proc$hart0_run_halt_server_response_get,
proc$m_external_interrupt_req_set_not_clear,
proc$master0_arlock,
proc$master0_arready,
proc$master0_arvalid,
proc$master0_awlock,
proc$master0_awready,
proc$master0_awvalid,
proc$master0_bready,
proc$master0_bvalid,
proc$master0_rlast,
proc$master0_rready,
proc$master0_rvalid,
proc$master0_wlast,
proc$master0_wready,
proc$master0_wvalid,
proc$master1_arlock,
proc$master1_arready,
proc$master1_arvalid,
proc$master1_awlock,
proc$master1_awready,
proc$master1_awvalid,
proc$master1_bready,
proc$master1_bvalid,
proc$master1_rlast,
proc$master1_rready,
proc$master1_rvalid,
proc$master1_wlast,
proc$master1_wready,
proc$master1_wvalid,
proc$non_maskable_interrupt_req_set_not_clear,
proc$s_external_interrupt_req_set_not_clear;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// ports of submodule tv_encode
reg [426 : 0] tv_encode$dm_in_put;
wire [607 : 0] tv_encode$out_get;
wire [490 : 0] tv_encode$v_cpu_in_0_put, tv_encode$v_cpu_in_1_put;
wire tv_encode$EN_dm_in_put,
tv_encode$EN_out_get,
tv_encode$EN_v_cpu_in_0_put,
tv_encode$EN_v_cpu_in_1_put,
tv_encode$RDY_dm_in_put,
tv_encode$RDY_out_get,
tv_encode$RDY_v_cpu_in_0_put,
tv_encode$RDY_v_cpu_in_1_put;
// ports of submodule v_td2_to_td_0
wire [861 : 0] v_td2_to_td_0$in_put;
wire [490 : 0] v_td2_to_td_0$out_get;
wire v_td2_to_td_0$EN_in_put,
v_td2_to_td_0$EN_out_get,
v_td2_to_td_0$RDY_in_put,
v_td2_to_td_0$RDY_out_get;
// ports of submodule v_td2_to_td_1
wire [861 : 0] v_td2_to_td_1$in_put;
wire [490 : 0] v_td2_to_td_1$out_get;
wire v_td2_to_td_1$EN_in_put,
v_td2_to_td_1$EN_out_get,
v_td2_to_td_1$RDY_in_put,
v_td2_to_td_1$RDY_out_get;
// rule scheduling signals
wire CAN_FIRE_RL_ClientServerRequest,
CAN_FIRE_RL_ClientServerRequest_1,
CAN_FIRE_RL_ClientServerRequest_2,
CAN_FIRE_RL_ClientServerRequest_3,
CAN_FIRE_RL_ClientServerRequest_4,
CAN_FIRE_RL_ClientServerResponse,
CAN_FIRE_RL_ClientServerResponse_1,
CAN_FIRE_RL_ClientServerResponse_2,
CAN_FIRE_RL_ClientServerResponse_3,
CAN_FIRE_RL_ClientServerResponse_4,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_mkConnectionGetPut_1,
CAN_FIRE_RL_mkConnectionGetPut_2,
CAN_FIRE_RL_mkConnectionGetPut_3,
CAN_FIRE_RL_mkConnectionGetPut_4,
CAN_FIRE_RL_rl_dm_hart0_reset,
CAN_FIRE_RL_rl_dm_hart0_reset_wait,
CAN_FIRE_RL_rl_merge_dm_csr_trace_data,
CAN_FIRE_RL_rl_merge_dm_gpr_trace_data,
CAN_FIRE_RL_rl_merge_dm_mem_trace_data,
CAN_FIRE_RL_rl_rd_addr_channel,
CAN_FIRE_RL_rl_rd_addr_channel_1,
CAN_FIRE_RL_rl_rd_addr_channel_2,
CAN_FIRE_RL_rl_rd_addr_channel_3,
CAN_FIRE_RL_rl_rd_addr_channel_4,
CAN_FIRE_RL_rl_rd_data_channel,
CAN_FIRE_RL_rl_rd_data_channel_1,
CAN_FIRE_RL_rl_rd_data_channel_2,
CAN_FIRE_RL_rl_rd_data_channel_3,
CAN_FIRE_RL_rl_rd_data_channel_4,
CAN_FIRE_RL_rl_relay_external_interrupts,
CAN_FIRE_RL_rl_wr_addr_channel,
CAN_FIRE_RL_rl_wr_addr_channel_1,
CAN_FIRE_RL_rl_wr_addr_channel_2,
CAN_FIRE_RL_rl_wr_addr_channel_3,
CAN_FIRE_RL_rl_wr_addr_channel_4,
CAN_FIRE_RL_rl_wr_data_channel,
CAN_FIRE_RL_rl_wr_data_channel_1,
CAN_FIRE_RL_rl_wr_data_channel_2,
CAN_FIRE_RL_rl_wr_data_channel_3,
CAN_FIRE_RL_rl_wr_data_channel_4,
CAN_FIRE_RL_rl_wr_response_channel,
CAN_FIRE_RL_rl_wr_response_channel_1,
CAN_FIRE_RL_rl_wr_response_channel_2,
CAN_FIRE_RL_rl_wr_response_channel_3,
CAN_FIRE_RL_rl_wr_response_channel_4,
CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
CAN_FIRE_cpu_dmem_master_m_arready,
CAN_FIRE_cpu_dmem_master_m_awready,
CAN_FIRE_cpu_dmem_master_m_bvalid,
CAN_FIRE_cpu_dmem_master_m_rvalid,
CAN_FIRE_cpu_dmem_master_m_wready,
CAN_FIRE_cpu_imem_master_m_arready,
CAN_FIRE_cpu_imem_master_m_awready,
CAN_FIRE_cpu_imem_master_m_bvalid,
CAN_FIRE_cpu_imem_master_m_rvalid,
CAN_FIRE_cpu_imem_master_m_wready,
CAN_FIRE_dmi_read_addr,
CAN_FIRE_dmi_read_data,
CAN_FIRE_dmi_write,
CAN_FIRE_ndm_reset_client_request_get,
CAN_FIRE_ndm_reset_client_response_put,
CAN_FIRE_nmi_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_start,
CAN_FIRE_tv_verifier_info_get_get,
WILL_FIRE_RL_ClientServerRequest,
WILL_FIRE_RL_ClientServerRequest_1,
WILL_FIRE_RL_ClientServerRequest_2,
WILL_FIRE_RL_ClientServerRequest_3,
WILL_FIRE_RL_ClientServerRequest_4,
WILL_FIRE_RL_ClientServerResponse,
WILL_FIRE_RL_ClientServerResponse_1,
WILL_FIRE_RL_ClientServerResponse_2,
WILL_FIRE_RL_ClientServerResponse_3,
WILL_FIRE_RL_ClientServerResponse_4,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_mkConnectionGetPut_1,
WILL_FIRE_RL_mkConnectionGetPut_2,
WILL_FIRE_RL_mkConnectionGetPut_3,
WILL_FIRE_RL_mkConnectionGetPut_4,
WILL_FIRE_RL_rl_dm_hart0_reset,
WILL_FIRE_RL_rl_dm_hart0_reset_wait,
WILL_FIRE_RL_rl_merge_dm_csr_trace_data,
WILL_FIRE_RL_rl_merge_dm_gpr_trace_data,
WILL_FIRE_RL_rl_merge_dm_mem_trace_data,
WILL_FIRE_RL_rl_rd_addr_channel,
WILL_FIRE_RL_rl_rd_addr_channel_1,
WILL_FIRE_RL_rl_rd_addr_channel_2,
WILL_FIRE_RL_rl_rd_addr_channel_3,
WILL_FIRE_RL_rl_rd_addr_channel_4,
WILL_FIRE_RL_rl_rd_data_channel,
WILL_FIRE_RL_rl_rd_data_channel_1,
WILL_FIRE_RL_rl_rd_data_channel_2,
WILL_FIRE_RL_rl_rd_data_channel_3,
WILL_FIRE_RL_rl_rd_data_channel_4,
WILL_FIRE_RL_rl_relay_external_interrupts,
WILL_FIRE_RL_rl_wr_addr_channel,
WILL_FIRE_RL_rl_wr_addr_channel_1,
WILL_FIRE_RL_rl_wr_addr_channel_2,
WILL_FIRE_RL_rl_wr_addr_channel_3,
WILL_FIRE_RL_rl_wr_addr_channel_4,
WILL_FIRE_RL_rl_wr_data_channel,
WILL_FIRE_RL_rl_wr_data_channel_1,
WILL_FIRE_RL_rl_wr_data_channel_2,
WILL_FIRE_RL_rl_wr_data_channel_3,
WILL_FIRE_RL_rl_wr_data_channel_4,
WILL_FIRE_RL_rl_wr_response_channel,
WILL_FIRE_RL_rl_wr_response_channel_1,
WILL_FIRE_RL_rl_wr_response_channel_2,
WILL_FIRE_RL_rl_wr_response_channel_3,
WILL_FIRE_RL_rl_wr_response_channel_4,
WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req,
WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req,
WILL_FIRE_cpu_dmem_master_m_arready,
WILL_FIRE_cpu_dmem_master_m_awready,
WILL_FIRE_cpu_dmem_master_m_bvalid,
WILL_FIRE_cpu_dmem_master_m_rvalid,
WILL_FIRE_cpu_dmem_master_m_wready,
WILL_FIRE_cpu_imem_master_m_arready,
WILL_FIRE_cpu_imem_master_m_awready,
WILL_FIRE_cpu_imem_master_m_bvalid,
WILL_FIRE_cpu_imem_master_m_rvalid,
WILL_FIRE_cpu_imem_master_m_wready,
WILL_FIRE_dmi_read_addr,
WILL_FIRE_dmi_read_data,
WILL_FIRE_dmi_write,
WILL_FIRE_ndm_reset_client_request_get,
WILL_FIRE_ndm_reset_client_response_put,
WILL_FIRE_nmi_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_start,
WILL_FIRE_tv_verifier_info_get_get;
// inputs to muxes for submodule ports
wire [7 : 0] MUX_rg_hart0_reset_delay$write_1__VAL_1;
wire MUX_proc$start_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h5047;
reg [31 : 0] v__h5190;
reg [31 : 0] v__h15930;
reg [31 : 0] v__h5041;
reg [31 : 0] v__h5184;
reg [31 : 0] v__h15924;
// synopsys translate_on
// remaining internal signals
reg [11 : 0] CASE_procv_to_TV_0_get_BITS_475_TO_464_1_proc_ETC__q1,
CASE_procv_to_TV_1_get_BITS_475_TO_464_1_proc_ETC__q5;
reg [3 : 0] CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q2,
CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q3,
CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q6,
CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q7;
reg [1 : 0] CASE_procv_to_TV_0_get_BITS_393_TO_392_0_proc_ETC__q4,
CASE_procv_to_TV_1_get_BITS_393_TO_392_0_proc_ETC__q8;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method start
assign RDY_start = proc$RDY_start ;
assign CAN_FIRE_start = proc$RDY_start ;
assign WILL_FIRE_start = EN_start ;
// value method cpu_imem_master_m_awvalid
assign cpu_imem_master_awvalid = proc$master0_awvalid ;
// value method cpu_imem_master_m_awid
assign cpu_imem_master_awid = proc$master0_awid ;
// value method cpu_imem_master_m_awaddr
assign cpu_imem_master_awaddr = proc$master0_awaddr ;
// value method cpu_imem_master_m_awlen
assign cpu_imem_master_awlen = proc$master0_awlen ;
// value method cpu_imem_master_m_awsize
assign cpu_imem_master_awsize = proc$master0_awsize ;
// value method cpu_imem_master_m_awburst
assign cpu_imem_master_awburst = proc$master0_awburst ;
// value method cpu_imem_master_m_awlock
assign cpu_imem_master_awlock = proc$master0_awlock ;
// value method cpu_imem_master_m_awcache
assign cpu_imem_master_awcache = proc$master0_awcache ;
// value method cpu_imem_master_m_awprot
assign cpu_imem_master_awprot = proc$master0_awprot ;
// value method cpu_imem_master_m_awqos
assign cpu_imem_master_awqos = proc$master0_awqos ;
// value method cpu_imem_master_m_awregion
assign cpu_imem_master_awregion = proc$master0_awregion ;
// action method cpu_imem_master_m_awready
assign CAN_FIRE_cpu_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_awready = 1'd1 ;
// value method cpu_imem_master_m_wvalid
assign cpu_imem_master_wvalid = proc$master0_wvalid ;
// value method cpu_imem_master_m_wdata
assign cpu_imem_master_wdata = proc$master0_wdata ;
// value method cpu_imem_master_m_wstrb
assign cpu_imem_master_wstrb = proc$master0_wstrb ;
// value method cpu_imem_master_m_wlast
assign cpu_imem_master_wlast = proc$master0_wlast ;
// action method cpu_imem_master_m_wready
assign CAN_FIRE_cpu_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_wready = 1'd1 ;
// action method cpu_imem_master_m_bvalid
assign CAN_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_bvalid = 1'd1 ;
// value method cpu_imem_master_m_bready
assign cpu_imem_master_bready = proc$master0_bready ;
// value method cpu_imem_master_m_arvalid
assign cpu_imem_master_arvalid = proc$master0_arvalid ;
// value method cpu_imem_master_m_arid
assign cpu_imem_master_arid = proc$master0_arid ;
// value method cpu_imem_master_m_araddr
assign cpu_imem_master_araddr = proc$master0_araddr ;
// value method cpu_imem_master_m_arlen
assign cpu_imem_master_arlen = proc$master0_arlen ;
// value method cpu_imem_master_m_arsize
assign cpu_imem_master_arsize = proc$master0_arsize ;
// value method cpu_imem_master_m_arburst
assign cpu_imem_master_arburst = proc$master0_arburst ;
// value method cpu_imem_master_m_arlock
assign cpu_imem_master_arlock = proc$master0_arlock ;
// value method cpu_imem_master_m_arcache
assign cpu_imem_master_arcache = proc$master0_arcache ;
// value method cpu_imem_master_m_arprot
assign cpu_imem_master_arprot = proc$master0_arprot ;
// value method cpu_imem_master_m_arqos
assign cpu_imem_master_arqos = proc$master0_arqos ;
// value method cpu_imem_master_m_arregion
assign cpu_imem_master_arregion = proc$master0_arregion ;
// action method cpu_imem_master_m_arready
assign CAN_FIRE_cpu_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_arready = 1'd1 ;
// action method cpu_imem_master_m_rvalid
assign CAN_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_imem_master_m_rvalid = 1'd1 ;
// value method cpu_imem_master_m_rready
assign cpu_imem_master_rready = proc$master0_rready ;
// value method cpu_dmem_master_m_awvalid
assign cpu_dmem_master_awvalid = fabric_2x3$v_to_slaves_0_awvalid ;
// value method cpu_dmem_master_m_awid
assign cpu_dmem_master_awid = fabric_2x3$v_to_slaves_0_awid ;
// value method cpu_dmem_master_m_awaddr
assign cpu_dmem_master_awaddr = fabric_2x3$v_to_slaves_0_awaddr ;
// value method cpu_dmem_master_m_awlen
assign cpu_dmem_master_awlen = fabric_2x3$v_to_slaves_0_awlen ;
// value method cpu_dmem_master_m_awsize
assign cpu_dmem_master_awsize = fabric_2x3$v_to_slaves_0_awsize ;
// value method cpu_dmem_master_m_awburst
assign cpu_dmem_master_awburst = fabric_2x3$v_to_slaves_0_awburst ;
// value method cpu_dmem_master_m_awlock
assign cpu_dmem_master_awlock = fabric_2x3$v_to_slaves_0_awlock ;
// value method cpu_dmem_master_m_awcache
assign cpu_dmem_master_awcache = fabric_2x3$v_to_slaves_0_awcache ;
// value method cpu_dmem_master_m_awprot
assign cpu_dmem_master_awprot = fabric_2x3$v_to_slaves_0_awprot ;
// value method cpu_dmem_master_m_awqos
assign cpu_dmem_master_awqos = fabric_2x3$v_to_slaves_0_awqos ;
// value method cpu_dmem_master_m_awregion
assign cpu_dmem_master_awregion = fabric_2x3$v_to_slaves_0_awregion ;
// action method cpu_dmem_master_m_awready
assign CAN_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_awready = 1'd1 ;
// value method cpu_dmem_master_m_wvalid
assign cpu_dmem_master_wvalid = fabric_2x3$v_to_slaves_0_wvalid ;
// value method cpu_dmem_master_m_wdata
assign cpu_dmem_master_wdata = fabric_2x3$v_to_slaves_0_wdata ;
// value method cpu_dmem_master_m_wstrb
assign cpu_dmem_master_wstrb = fabric_2x3$v_to_slaves_0_wstrb ;
// value method cpu_dmem_master_m_wlast
assign cpu_dmem_master_wlast = fabric_2x3$v_to_slaves_0_wlast ;
// action method cpu_dmem_master_m_wready
assign CAN_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_wready = 1'd1 ;
// action method cpu_dmem_master_m_bvalid
assign CAN_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_bvalid = 1'd1 ;
// value method cpu_dmem_master_m_bready
assign cpu_dmem_master_bready = fabric_2x3$v_to_slaves_0_bready ;
// value method cpu_dmem_master_m_arvalid
assign cpu_dmem_master_arvalid = fabric_2x3$v_to_slaves_0_arvalid ;
// value method cpu_dmem_master_m_arid
assign cpu_dmem_master_arid = fabric_2x3$v_to_slaves_0_arid ;
// value method cpu_dmem_master_m_araddr
assign cpu_dmem_master_araddr = fabric_2x3$v_to_slaves_0_araddr ;
// value method cpu_dmem_master_m_arlen
assign cpu_dmem_master_arlen = fabric_2x3$v_to_slaves_0_arlen ;
// value method cpu_dmem_master_m_arsize
assign cpu_dmem_master_arsize = fabric_2x3$v_to_slaves_0_arsize ;
// value method cpu_dmem_master_m_arburst
assign cpu_dmem_master_arburst = fabric_2x3$v_to_slaves_0_arburst ;
// value method cpu_dmem_master_m_arlock
assign cpu_dmem_master_arlock = fabric_2x3$v_to_slaves_0_arlock ;
// value method cpu_dmem_master_m_arcache
assign cpu_dmem_master_arcache = fabric_2x3$v_to_slaves_0_arcache ;
// value method cpu_dmem_master_m_arprot
assign cpu_dmem_master_arprot = fabric_2x3$v_to_slaves_0_arprot ;
// value method cpu_dmem_master_m_arqos
assign cpu_dmem_master_arqos = fabric_2x3$v_to_slaves_0_arqos ;
// value method cpu_dmem_master_m_arregion
assign cpu_dmem_master_arregion = fabric_2x3$v_to_slaves_0_arregion ;
// action method cpu_dmem_master_m_arready
assign CAN_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_arready = 1'd1 ;
// action method cpu_dmem_master_m_rvalid
assign CAN_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_cpu_dmem_master_m_rvalid = 1'd1 ;
// value method cpu_dmem_master_m_rready
assign cpu_dmem_master_rready = fabric_2x3$v_to_slaves_0_rready ;
// action method core_external_interrupt_sources_0_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_0_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_1_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_1_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_2_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_2_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_3_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_3_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_4_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_4_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_5_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_5_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_6_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_6_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_7_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_7_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_8_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_8_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_9_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_9_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_10_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_10_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_11_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_11_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_12_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_12_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_13_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_13_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_14_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_14_m_interrupt_req = 1'd1 ;
// action method core_external_interrupt_sources_15_m_interrupt_req
assign CAN_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
assign WILL_FIRE_core_external_interrupt_sources_15_m_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method dmi_read_addr
assign RDY_dmi_read_addr = debug_module$RDY_dmi_read_addr ;
assign CAN_FIRE_dmi_read_addr = debug_module$RDY_dmi_read_addr ;
assign WILL_FIRE_dmi_read_addr = EN_dmi_read_addr ;
// actionvalue method dmi_read_data
assign dmi_read_data = debug_module$dmi_read_data ;
assign RDY_dmi_read_data = debug_module$RDY_dmi_read_data ;
assign CAN_FIRE_dmi_read_data = debug_module$RDY_dmi_read_data ;
assign WILL_FIRE_dmi_read_data = EN_dmi_read_data ;
// action method dmi_write
assign RDY_dmi_write = debug_module$RDY_dmi_write ;
assign CAN_FIRE_dmi_write = debug_module$RDY_dmi_write ;
assign WILL_FIRE_dmi_write = EN_dmi_write ;
// actionvalue method ndm_reset_client_request_get
assign ndm_reset_client_request_get =
debug_module$ndm_reset_client_request_get ;
assign RDY_ndm_reset_client_request_get =
debug_module$RDY_ndm_reset_client_request_get ;
assign CAN_FIRE_ndm_reset_client_request_get =
debug_module$RDY_ndm_reset_client_request_get ;
assign WILL_FIRE_ndm_reset_client_request_get =
EN_ndm_reset_client_request_get ;
// action method ndm_reset_client_response_put
assign RDY_ndm_reset_client_response_put =
debug_module$RDY_ndm_reset_client_response_put ;
assign CAN_FIRE_ndm_reset_client_response_put =
debug_module$RDY_ndm_reset_client_response_put ;
assign WILL_FIRE_ndm_reset_client_response_put =
EN_ndm_reset_client_response_put ;
// actionvalue method tv_verifier_info_get_get
assign tv_verifier_info_get_get = tv_encode$out_get ;
assign RDY_tv_verifier_info_get_get = tv_encode$RDY_out_get ;
assign CAN_FIRE_tv_verifier_info_get_get = tv_encode$RDY_out_get ;
assign WILL_FIRE_tv_verifier_info_get_get = EN_tv_verifier_info_get_get ;
// submodule debug_module
mkDebug_Module debug_module(.CLK(CLK),
.RST_N(RST_N_dm_power_on_reset),
.dmi_read_addr_dm_addr(debug_module$dmi_read_addr_dm_addr),
.dmi_write_dm_addr(debug_module$dmi_write_dm_addr),
.dmi_write_dm_word(debug_module$dmi_write_dm_word),
.hart0_client_run_halt_response_put(debug_module$hart0_client_run_halt_response_put),
.hart0_csr_mem_client_response_put(debug_module$hart0_csr_mem_client_response_put),
.hart0_fpr_mem_client_response_put(debug_module$hart0_fpr_mem_client_response_put),
.hart0_gpr_mem_client_response_put(debug_module$hart0_gpr_mem_client_response_put),
.hart0_reset_client_response_put(debug_module$hart0_reset_client_response_put),
.master_arready(debug_module$master_arready),
.master_awready(debug_module$master_awready),
.master_bid(debug_module$master_bid),
.master_bresp(debug_module$master_bresp),
.master_bvalid(debug_module$master_bvalid),
.master_rdata(debug_module$master_rdata),
.master_rid(debug_module$master_rid),
.master_rlast(debug_module$master_rlast),
.master_rresp(debug_module$master_rresp),
.master_rvalid(debug_module$master_rvalid),
.master_wready(debug_module$master_wready),
.ndm_reset_client_response_put(debug_module$ndm_reset_client_response_put),
.EN_dmi_read_addr(debug_module$EN_dmi_read_addr),
.EN_dmi_read_data(debug_module$EN_dmi_read_data),
.EN_dmi_write(debug_module$EN_dmi_write),
.EN_hart0_reset_client_request_get(debug_module$EN_hart0_reset_client_request_get),
.EN_hart0_reset_client_response_put(debug_module$EN_hart0_reset_client_response_put),
.EN_hart0_client_run_halt_request_get(debug_module$EN_hart0_client_run_halt_request_get),
.EN_hart0_client_run_halt_response_put(debug_module$EN_hart0_client_run_halt_response_put),
.EN_hart0_get_other_req_get(debug_module$EN_hart0_get_other_req_get),
.EN_hart0_gpr_mem_client_request_get(debug_module$EN_hart0_gpr_mem_client_request_get),
.EN_hart0_gpr_mem_client_response_put(debug_module$EN_hart0_gpr_mem_client_response_put),
.EN_hart0_fpr_mem_client_request_get(debug_module$EN_hart0_fpr_mem_client_request_get),
.EN_hart0_fpr_mem_client_response_put(debug_module$EN_hart0_fpr_mem_client_response_put),
.EN_hart0_csr_mem_client_request_get(debug_module$EN_hart0_csr_mem_client_request_get),
.EN_hart0_csr_mem_client_response_put(debug_module$EN_hart0_csr_mem_client_response_put),
.EN_ndm_reset_client_request_get(debug_module$EN_ndm_reset_client_request_get),
.EN_ndm_reset_client_response_put(debug_module$EN_ndm_reset_client_response_put),
.RDY_dmi_read_addr(debug_module$RDY_dmi_read_addr),
.dmi_read_data(debug_module$dmi_read_data),
.RDY_dmi_read_data(debug_module$RDY_dmi_read_data),
.RDY_dmi_write(debug_module$RDY_dmi_write),
.hart0_reset_client_request_get(),
.RDY_hart0_reset_client_request_get(debug_module$RDY_hart0_reset_client_request_get),
.RDY_hart0_reset_client_response_put(debug_module$RDY_hart0_reset_client_response_put),
.hart0_client_run_halt_request_get(debug_module$hart0_client_run_halt_request_get),
.RDY_hart0_client_run_halt_request_get(debug_module$RDY_hart0_client_run_halt_request_get),
.RDY_hart0_client_run_halt_response_put(debug_module$RDY_hart0_client_run_halt_response_put),
.hart0_get_other_req_get(debug_module$hart0_get_other_req_get),
.RDY_hart0_get_other_req_get(debug_module$RDY_hart0_get_other_req_get),
.hart0_gpr_mem_client_request_get(debug_module$hart0_gpr_mem_client_request_get),
.RDY_hart0_gpr_mem_client_request_get(debug_module$RDY_hart0_gpr_mem_client_request_get),
.RDY_hart0_gpr_mem_client_response_put(debug_module$RDY_hart0_gpr_mem_client_response_put),
.hart0_fpr_mem_client_request_get(),
.RDY_hart0_fpr_mem_client_request_get(),
.RDY_hart0_fpr_mem_client_response_put(),
.hart0_csr_mem_client_request_get(debug_module$hart0_csr_mem_client_request_get),
.RDY_hart0_csr_mem_client_request_get(debug_module$RDY_hart0_csr_mem_client_request_get),
.RDY_hart0_csr_mem_client_response_put(debug_module$RDY_hart0_csr_mem_client_response_put),
.ndm_reset_client_request_get(debug_module$ndm_reset_client_request_get),
.RDY_ndm_reset_client_request_get(debug_module$RDY_ndm_reset_client_request_get),
.RDY_ndm_reset_client_response_put(debug_module$RDY_ndm_reset_client_response_put),
.master_awvalid(debug_module$master_awvalid),
.master_awid(debug_module$master_awid),
.master_awaddr(debug_module$master_awaddr),
.master_awlen(debug_module$master_awlen),
.master_awsize(debug_module$master_awsize),
.master_awburst(debug_module$master_awburst),
.master_awlock(debug_module$master_awlock),
.master_awcache(debug_module$master_awcache),
.master_awprot(debug_module$master_awprot),
.master_awqos(debug_module$master_awqos),
.master_awregion(debug_module$master_awregion),
.master_wvalid(debug_module$master_wvalid),
.master_wdata(debug_module$master_wdata),
.master_wstrb(debug_module$master_wstrb),
.master_wlast(debug_module$master_wlast),
.master_bready(debug_module$master_bready),
.master_arvalid(debug_module$master_arvalid),
.master_arid(debug_module$master_arid),
.master_araddr(debug_module$master_araddr),
.master_arlen(debug_module$master_arlen),
.master_arsize(debug_module$master_arsize),
.master_arburst(debug_module$master_arburst),
.master_arlock(debug_module$master_arlock),
.master_arcache(debug_module$master_arcache),
.master_arprot(debug_module$master_arprot),
.master_arqos(debug_module$master_arqos),
.master_arregion(debug_module$master_arregion),
.master_rready(debug_module$master_rready));
// submodule dm_csr_tap
mkDM_CSR_Tap dm_csr_tap(.CLK(CLK),
.RST_N(RST_N),
.client_response_put(dm_csr_tap$client_response_put),
.server_request_put(dm_csr_tap$server_request_put),
.EN_client_request_get(dm_csr_tap$EN_client_request_get),
.EN_client_response_put(dm_csr_tap$EN_client_response_put),
.EN_server_request_put(dm_csr_tap$EN_server_request_put),
.EN_server_response_get(dm_csr_tap$EN_server_response_get),
.EN_trace_data_out_get(dm_csr_tap$EN_trace_data_out_get),
.client_request_get(dm_csr_tap$client_request_get),
.RDY_client_request_get(dm_csr_tap$RDY_client_request_get),
.RDY_client_response_put(dm_csr_tap$RDY_client_response_put),
.RDY_server_request_put(dm_csr_tap$RDY_server_request_put),
.server_response_get(dm_csr_tap$server_response_get),
.RDY_server_response_get(dm_csr_tap$RDY_server_response_get),
.trace_data_out_get(dm_csr_tap$trace_data_out_get),
.RDY_trace_data_out_get(dm_csr_tap$RDY_trace_data_out_get));
// submodule dm_gpr_tap_ifc
mkDM_GPR_Tap dm_gpr_tap_ifc(.CLK(CLK),
.RST_N(RST_N),
.client_response_put(dm_gpr_tap_ifc$client_response_put),
.server_request_put(dm_gpr_tap_ifc$server_request_put),
.EN_client_request_get(dm_gpr_tap_ifc$EN_client_request_get),
.EN_client_response_put(dm_gpr_tap_ifc$EN_client_response_put),
.EN_server_request_put(dm_gpr_tap_ifc$EN_server_request_put),
.EN_server_response_get(dm_gpr_tap_ifc$EN_server_response_get),
.EN_trace_data_out_get(dm_gpr_tap_ifc$EN_trace_data_out_get),
.client_request_get(dm_gpr_tap_ifc$client_request_get),
.RDY_client_request_get(dm_gpr_tap_ifc$RDY_client_request_get),
.RDY_client_response_put(dm_gpr_tap_ifc$RDY_client_response_put),
.RDY_server_request_put(dm_gpr_tap_ifc$RDY_server_request_put),
.server_response_get(dm_gpr_tap_ifc$server_response_get),
.RDY_server_response_get(dm_gpr_tap_ifc$RDY_server_response_get),
.trace_data_out_get(dm_gpr_tap_ifc$trace_data_out_get),
.RDY_trace_data_out_get(dm_gpr_tap_ifc$RDY_trace_data_out_get));
// submodule dm_hart0_reset_controller
MakeResetA #(.RSTDELAY(32'd10),
.init(1'd1)) dm_hart0_reset_controller(.CLK(CLK),
.RST(RST_N),
.DST_CLK(CLK),
.ASSERT_IN(dm_hart0_reset_controller$ASSERT_IN),
.ASSERT_OUT(),
.OUT_RST(dm_hart0_reset_controller$OUT_RST));
// submodule dm_mem_tap
mkDM_Mem_Tap dm_mem_tap(.CLK(CLK),
.RST_N(RST_N),
.master_arready(dm_mem_tap$master_arready),
.master_awready(dm_mem_tap$master_awready),
.master_bid(dm_mem_tap$master_bid),
.master_bresp(dm_mem_tap$master_bresp),
.master_bvalid(dm_mem_tap$master_bvalid),
.master_rdata(dm_mem_tap$master_rdata),
.master_rid(dm_mem_tap$master_rid),
.master_rlast(dm_mem_tap$master_rlast),
.master_rresp(dm_mem_tap$master_rresp),
.master_rvalid(dm_mem_tap$master_rvalid),
.master_wready(dm_mem_tap$master_wready),
.slave_araddr(dm_mem_tap$slave_araddr),
.slave_arburst(dm_mem_tap$slave_arburst),
.slave_arcache(dm_mem_tap$slave_arcache),
.slave_arid(dm_mem_tap$slave_arid),
.slave_arlen(dm_mem_tap$slave_arlen),
.slave_arlock(dm_mem_tap$slave_arlock),
.slave_arprot(dm_mem_tap$slave_arprot),
.slave_arqos(dm_mem_tap$slave_arqos),
.slave_arregion(dm_mem_tap$slave_arregion),
.slave_arsize(dm_mem_tap$slave_arsize),
.slave_arvalid(dm_mem_tap$slave_arvalid),
.slave_awaddr(dm_mem_tap$slave_awaddr),
.slave_awburst(dm_mem_tap$slave_awburst),
.slave_awcache(dm_mem_tap$slave_awcache),
.slave_awid(dm_mem_tap$slave_awid),
.slave_awlen(dm_mem_tap$slave_awlen),
.slave_awlock(dm_mem_tap$slave_awlock),
.slave_awprot(dm_mem_tap$slave_awprot),
.slave_awqos(dm_mem_tap$slave_awqos),
.slave_awregion(dm_mem_tap$slave_awregion),
.slave_awsize(dm_mem_tap$slave_awsize),
.slave_awvalid(dm_mem_tap$slave_awvalid),
.slave_bready(dm_mem_tap$slave_bready),
.slave_rready(dm_mem_tap$slave_rready),
.slave_wdata(dm_mem_tap$slave_wdata),
.slave_wlast(dm_mem_tap$slave_wlast),
.slave_wstrb(dm_mem_tap$slave_wstrb),
.slave_wvalid(dm_mem_tap$slave_wvalid),
.EN_trace_data_out_get(dm_mem_tap$EN_trace_data_out_get),
.slave_awready(dm_mem_tap$slave_awready),
.slave_wready(dm_mem_tap$slave_wready),
.slave_bvalid(dm_mem_tap$slave_bvalid),
.slave_bid(dm_mem_tap$slave_bid),
.slave_bresp(dm_mem_tap$slave_bresp),
.slave_arready(dm_mem_tap$slave_arready),
.slave_rvalid(dm_mem_tap$slave_rvalid),
.slave_rid(dm_mem_tap$slave_rid),
.slave_rdata(dm_mem_tap$slave_rdata),
.slave_rresp(dm_mem_tap$slave_rresp),
.slave_rlast(dm_mem_tap$slave_rlast),
.master_awvalid(dm_mem_tap$master_awvalid),
.master_awid(dm_mem_tap$master_awid),
.master_awaddr(dm_mem_tap$master_awaddr),
.master_awlen(dm_mem_tap$master_awlen),
.master_awsize(dm_mem_tap$master_awsize),
.master_awburst(dm_mem_tap$master_awburst),
.master_awlock(dm_mem_tap$master_awlock),
.master_awcache(dm_mem_tap$master_awcache),
.master_awprot(dm_mem_tap$master_awprot),
.master_awqos(dm_mem_tap$master_awqos),
.master_awregion(dm_mem_tap$master_awregion),
.master_wvalid(dm_mem_tap$master_wvalid),
.master_wdata(dm_mem_tap$master_wdata),
.master_wstrb(dm_mem_tap$master_wstrb),
.master_wlast(dm_mem_tap$master_wlast),
.master_bready(dm_mem_tap$master_bready),
.master_arvalid(dm_mem_tap$master_arvalid),
.master_arid(dm_mem_tap$master_arid),
.master_araddr(dm_mem_tap$master_araddr),
.master_arlen(dm_mem_tap$master_arlen),
.master_arsize(dm_mem_tap$master_arsize),
.master_arburst(dm_mem_tap$master_arburst),
.master_arlock(dm_mem_tap$master_arlock),
.master_arcache(dm_mem_tap$master_arcache),
.master_arprot(dm_mem_tap$master_arprot),
.master_arqos(dm_mem_tap$master_arqos),
.master_arregion(dm_mem_tap$master_arregion),
.master_rready(dm_mem_tap$master_rready),
.trace_data_out_get(dm_mem_tap$trace_data_out_get),
.RDY_trace_data_out_get(dm_mem_tap$RDY_trace_data_out_get));
// submodule fabric_2x3
mkFabric_2x3 fabric_2x3(.CLK(CLK),
.RST_N(RST_N),
.set_verbosity_verbosity(fabric_2x3$set_verbosity_verbosity),
.v_from_masters_0_araddr(fabric_2x3$v_from_masters_0_araddr),
.v_from_masters_0_arburst(fabric_2x3$v_from_masters_0_arburst),
.v_from_masters_0_arcache(fabric_2x3$v_from_masters_0_arcache),
.v_from_masters_0_arid(fabric_2x3$v_from_masters_0_arid),
.v_from_masters_0_arlen(fabric_2x3$v_from_masters_0_arlen),
.v_from_masters_0_arlock(fabric_2x3$v_from_masters_0_arlock),
.v_from_masters_0_arprot(fabric_2x3$v_from_masters_0_arprot),
.v_from_masters_0_arqos(fabric_2x3$v_from_masters_0_arqos),
.v_from_masters_0_arregion(fabric_2x3$v_from_masters_0_arregion),
.v_from_masters_0_arsize(fabric_2x3$v_from_masters_0_arsize),
.v_from_masters_0_arvalid(fabric_2x3$v_from_masters_0_arvalid),
.v_from_masters_0_awaddr(fabric_2x3$v_from_masters_0_awaddr),
.v_from_masters_0_awburst(fabric_2x3$v_from_masters_0_awburst),
.v_from_masters_0_awcache(fabric_2x3$v_from_masters_0_awcache),
.v_from_masters_0_awid(fabric_2x3$v_from_masters_0_awid),
.v_from_masters_0_awlen(fabric_2x3$v_from_masters_0_awlen),
.v_from_masters_0_awlock(fabric_2x3$v_from_masters_0_awlock),
.v_from_masters_0_awprot(fabric_2x3$v_from_masters_0_awprot),
.v_from_masters_0_awqos(fabric_2x3$v_from_masters_0_awqos),
.v_from_masters_0_awregion(fabric_2x3$v_from_masters_0_awregion),
.v_from_masters_0_awsize(fabric_2x3$v_from_masters_0_awsize),
.v_from_masters_0_awvalid(fabric_2x3$v_from_masters_0_awvalid),
.v_from_masters_0_bready(fabric_2x3$v_from_masters_0_bready),
.v_from_masters_0_rready(fabric_2x3$v_from_masters_0_rready),
.v_from_masters_0_wdata(fabric_2x3$v_from_masters_0_wdata),
.v_from_masters_0_wlast(fabric_2x3$v_from_masters_0_wlast),
.v_from_masters_0_wstrb(fabric_2x3$v_from_masters_0_wstrb),
.v_from_masters_0_wvalid(fabric_2x3$v_from_masters_0_wvalid),
.v_from_masters_1_araddr(fabric_2x3$v_from_masters_1_araddr),
.v_from_masters_1_arburst(fabric_2x3$v_from_masters_1_arburst),
.v_from_masters_1_arcache(fabric_2x3$v_from_masters_1_arcache),
.v_from_masters_1_arid(fabric_2x3$v_from_masters_1_arid),
.v_from_masters_1_arlen(fabric_2x3$v_from_masters_1_arlen),
.v_from_masters_1_arlock(fabric_2x3$v_from_masters_1_arlock),
.v_from_masters_1_arprot(fabric_2x3$v_from_masters_1_arprot),
.v_from_masters_1_arqos(fabric_2x3$v_from_masters_1_arqos),
.v_from_masters_1_arregion(fabric_2x3$v_from_masters_1_arregion),
.v_from_masters_1_arsize(fabric_2x3$v_from_masters_1_arsize),
.v_from_masters_1_arvalid(fabric_2x3$v_from_masters_1_arvalid),
.v_from_masters_1_awaddr(fabric_2x3$v_from_masters_1_awaddr),
.v_from_masters_1_awburst(fabric_2x3$v_from_masters_1_awburst),
.v_from_masters_1_awcache(fabric_2x3$v_from_masters_1_awcache),
.v_from_masters_1_awid(fabric_2x3$v_from_masters_1_awid),
.v_from_masters_1_awlen(fabric_2x3$v_from_masters_1_awlen),
.v_from_masters_1_awlock(fabric_2x3$v_from_masters_1_awlock),
.v_from_masters_1_awprot(fabric_2x3$v_from_masters_1_awprot),
.v_from_masters_1_awqos(fabric_2x3$v_from_masters_1_awqos),
.v_from_masters_1_awregion(fabric_2x3$v_from_masters_1_awregion),
.v_from_masters_1_awsize(fabric_2x3$v_from_masters_1_awsize),
.v_from_masters_1_awvalid(fabric_2x3$v_from_masters_1_awvalid),
.v_from_masters_1_bready(fabric_2x3$v_from_masters_1_bready),
.v_from_masters_1_rready(fabric_2x3$v_from_masters_1_rready),
.v_from_masters_1_wdata(fabric_2x3$v_from_masters_1_wdata),
.v_from_masters_1_wlast(fabric_2x3$v_from_masters_1_wlast),
.v_from_masters_1_wstrb(fabric_2x3$v_from_masters_1_wstrb),
.v_from_masters_1_wvalid(fabric_2x3$v_from_masters_1_wvalid),
.v_to_slaves_0_arready(fabric_2x3$v_to_slaves_0_arready),
.v_to_slaves_0_awready(fabric_2x3$v_to_slaves_0_awready),
.v_to_slaves_0_bid(fabric_2x3$v_to_slaves_0_bid),
.v_to_slaves_0_bresp(fabric_2x3$v_to_slaves_0_bresp),
.v_to_slaves_0_bvalid(fabric_2x3$v_to_slaves_0_bvalid),
.v_to_slaves_0_rdata(fabric_2x3$v_to_slaves_0_rdata),
.v_to_slaves_0_rid(fabric_2x3$v_to_slaves_0_rid),
.v_to_slaves_0_rlast(fabric_2x3$v_to_slaves_0_rlast),
.v_to_slaves_0_rresp(fabric_2x3$v_to_slaves_0_rresp),
.v_to_slaves_0_rvalid(fabric_2x3$v_to_slaves_0_rvalid),
.v_to_slaves_0_wready(fabric_2x3$v_to_slaves_0_wready),
.v_to_slaves_1_arready(fabric_2x3$v_to_slaves_1_arready),
.v_to_slaves_1_awready(fabric_2x3$v_to_slaves_1_awready),
.v_to_slaves_1_bid(fabric_2x3$v_to_slaves_1_bid),
.v_to_slaves_1_bresp(fabric_2x3$v_to_slaves_1_bresp),
.v_to_slaves_1_bvalid(fabric_2x3$v_to_slaves_1_bvalid),
.v_to_slaves_1_rdata(fabric_2x3$v_to_slaves_1_rdata),
.v_to_slaves_1_rid(fabric_2x3$v_to_slaves_1_rid),
.v_to_slaves_1_rlast(fabric_2x3$v_to_slaves_1_rlast),
.v_to_slaves_1_rresp(fabric_2x3$v_to_slaves_1_rresp),
.v_to_slaves_1_rvalid(fabric_2x3$v_to_slaves_1_rvalid),
.v_to_slaves_1_wready(fabric_2x3$v_to_slaves_1_wready),
.v_to_slaves_2_arready(fabric_2x3$v_to_slaves_2_arready),
.v_to_slaves_2_awready(fabric_2x3$v_to_slaves_2_awready),
.v_to_slaves_2_bid(fabric_2x3$v_to_slaves_2_bid),
.v_to_slaves_2_bresp(fabric_2x3$v_to_slaves_2_bresp),
.v_to_slaves_2_bvalid(fabric_2x3$v_to_slaves_2_bvalid),
.v_to_slaves_2_rdata(fabric_2x3$v_to_slaves_2_rdata),
.v_to_slaves_2_rid(fabric_2x3$v_to_slaves_2_rid),
.v_to_slaves_2_rlast(fabric_2x3$v_to_slaves_2_rlast),
.v_to_slaves_2_rresp(fabric_2x3$v_to_slaves_2_rresp),
.v_to_slaves_2_rvalid(fabric_2x3$v_to_slaves_2_rvalid),
.v_to_slaves_2_wready(fabric_2x3$v_to_slaves_2_wready),
.EN_reset(fabric_2x3$EN_reset),
.EN_set_verbosity(fabric_2x3$EN_set_verbosity),
.RDY_reset(),
.RDY_set_verbosity(),
.v_from_masters_0_awready(fabric_2x3$v_from_masters_0_awready),
.v_from_masters_0_wready(fabric_2x3$v_from_masters_0_wready),
.v_from_masters_0_bvalid(fabric_2x3$v_from_masters_0_bvalid),
.v_from_masters_0_bid(fabric_2x3$v_from_masters_0_bid),
.v_from_masters_0_bresp(fabric_2x3$v_from_masters_0_bresp),
.v_from_masters_0_arready(fabric_2x3$v_from_masters_0_arready),
.v_from_masters_0_rvalid(fabric_2x3$v_from_masters_0_rvalid),
.v_from_masters_0_rid(fabric_2x3$v_from_masters_0_rid),
.v_from_masters_0_rdata(fabric_2x3$v_from_masters_0_rdata),
.v_from_masters_0_rresp(fabric_2x3$v_from_masters_0_rresp),
.v_from_masters_0_rlast(fabric_2x3$v_from_masters_0_rlast),
.v_from_masters_1_awready(fabric_2x3$v_from_masters_1_awready),
.v_from_masters_1_wready(fabric_2x3$v_from_masters_1_wready),
.v_from_masters_1_bvalid(fabric_2x3$v_from_masters_1_bvalid),
.v_from_masters_1_bid(fabric_2x3$v_from_masters_1_bid),
.v_from_masters_1_bresp(fabric_2x3$v_from_masters_1_bresp),
.v_from_masters_1_arready(fabric_2x3$v_from_masters_1_arready),
.v_from_masters_1_rvalid(fabric_2x3$v_from_masters_1_rvalid),
.v_from_masters_1_rid(fabric_2x3$v_from_masters_1_rid),
.v_from_masters_1_rdata(fabric_2x3$v_from_masters_1_rdata),
.v_from_masters_1_rresp(fabric_2x3$v_from_masters_1_rresp),
.v_from_masters_1_rlast(fabric_2x3$v_from_masters_1_rlast),
.v_to_slaves_0_awvalid(fabric_2x3$v_to_slaves_0_awvalid),
.v_to_slaves_0_awid(fabric_2x3$v_to_slaves_0_awid),
.v_to_slaves_0_awaddr(fabric_2x3$v_to_slaves_0_awaddr),
.v_to_slaves_0_awlen(fabric_2x3$v_to_slaves_0_awlen),
.v_to_slaves_0_awsize(fabric_2x3$v_to_slaves_0_awsize),
.v_to_slaves_0_awburst(fabric_2x3$v_to_slaves_0_awburst),
.v_to_slaves_0_awlock(fabric_2x3$v_to_slaves_0_awlock),
.v_to_slaves_0_awcache(fabric_2x3$v_to_slaves_0_awcache),
.v_to_slaves_0_awprot(fabric_2x3$v_to_slaves_0_awprot),
.v_to_slaves_0_awqos(fabric_2x3$v_to_slaves_0_awqos),
.v_to_slaves_0_awregion(fabric_2x3$v_to_slaves_0_awregion),
.v_to_slaves_0_wvalid(fabric_2x3$v_to_slaves_0_wvalid),
.v_to_slaves_0_wdata(fabric_2x3$v_to_slaves_0_wdata),
.v_to_slaves_0_wstrb(fabric_2x3$v_to_slaves_0_wstrb),
.v_to_slaves_0_wlast(fabric_2x3$v_to_slaves_0_wlast),
.v_to_slaves_0_bready(fabric_2x3$v_to_slaves_0_bready),
.v_to_slaves_0_arvalid(fabric_2x3$v_to_slaves_0_arvalid),
.v_to_slaves_0_arid(fabric_2x3$v_to_slaves_0_arid),
.v_to_slaves_0_araddr(fabric_2x3$v_to_slaves_0_araddr),
.v_to_slaves_0_arlen(fabric_2x3$v_to_slaves_0_arlen),
.v_to_slaves_0_arsize(fabric_2x3$v_to_slaves_0_arsize),
.v_to_slaves_0_arburst(fabric_2x3$v_to_slaves_0_arburst),
.v_to_slaves_0_arlock(fabric_2x3$v_to_slaves_0_arlock),
.v_to_slaves_0_arcache(fabric_2x3$v_to_slaves_0_arcache),
.v_to_slaves_0_arprot(fabric_2x3$v_to_slaves_0_arprot),
.v_to_slaves_0_arqos(fabric_2x3$v_to_slaves_0_arqos),
.v_to_slaves_0_arregion(fabric_2x3$v_to_slaves_0_arregion),
.v_to_slaves_0_rready(fabric_2x3$v_to_slaves_0_rready),
.v_to_slaves_1_awvalid(fabric_2x3$v_to_slaves_1_awvalid),
.v_to_slaves_1_awid(fabric_2x3$v_to_slaves_1_awid),
.v_to_slaves_1_awaddr(fabric_2x3$v_to_slaves_1_awaddr),
.v_to_slaves_1_awlen(fabric_2x3$v_to_slaves_1_awlen),
.v_to_slaves_1_awsize(fabric_2x3$v_to_slaves_1_awsize),
.v_to_slaves_1_awburst(fabric_2x3$v_to_slaves_1_awburst),
.v_to_slaves_1_awlock(fabric_2x3$v_to_slaves_1_awlock),
.v_to_slaves_1_awcache(fabric_2x3$v_to_slaves_1_awcache),
.v_to_slaves_1_awprot(fabric_2x3$v_to_slaves_1_awprot),
.v_to_slaves_1_awqos(fabric_2x3$v_to_slaves_1_awqos),
.v_to_slaves_1_awregion(fabric_2x3$v_to_slaves_1_awregion),
.v_to_slaves_1_wvalid(fabric_2x3$v_to_slaves_1_wvalid),
.v_to_slaves_1_wdata(fabric_2x3$v_to_slaves_1_wdata),
.v_to_slaves_1_wstrb(fabric_2x3$v_to_slaves_1_wstrb),
.v_to_slaves_1_wlast(fabric_2x3$v_to_slaves_1_wlast),
.v_to_slaves_1_bready(fabric_2x3$v_to_slaves_1_bready),
.v_to_slaves_1_arvalid(fabric_2x3$v_to_slaves_1_arvalid),
.v_to_slaves_1_arid(fabric_2x3$v_to_slaves_1_arid),
.v_to_slaves_1_araddr(fabric_2x3$v_to_slaves_1_araddr),
.v_to_slaves_1_arlen(fabric_2x3$v_to_slaves_1_arlen),
.v_to_slaves_1_arsize(fabric_2x3$v_to_slaves_1_arsize),
.v_to_slaves_1_arburst(fabric_2x3$v_to_slaves_1_arburst),
.v_to_slaves_1_arlock(fabric_2x3$v_to_slaves_1_arlock),
.v_to_slaves_1_arcache(fabric_2x3$v_to_slaves_1_arcache),
.v_to_slaves_1_arprot(fabric_2x3$v_to_slaves_1_arprot),
.v_to_slaves_1_arqos(fabric_2x3$v_to_slaves_1_arqos),
.v_to_slaves_1_arregion(fabric_2x3$v_to_slaves_1_arregion),
.v_to_slaves_1_rready(fabric_2x3$v_to_slaves_1_rready),
.v_to_slaves_2_awvalid(fabric_2x3$v_to_slaves_2_awvalid),
.v_to_slaves_2_awid(fabric_2x3$v_to_slaves_2_awid),
.v_to_slaves_2_awaddr(fabric_2x3$v_to_slaves_2_awaddr),
.v_to_slaves_2_awlen(fabric_2x3$v_to_slaves_2_awlen),
.v_to_slaves_2_awsize(fabric_2x3$v_to_slaves_2_awsize),
.v_to_slaves_2_awburst(fabric_2x3$v_to_slaves_2_awburst),
.v_to_slaves_2_awlock(fabric_2x3$v_to_slaves_2_awlock),
.v_to_slaves_2_awcache(fabric_2x3$v_to_slaves_2_awcache),
.v_to_slaves_2_awprot(fabric_2x3$v_to_slaves_2_awprot),
.v_to_slaves_2_awqos(fabric_2x3$v_to_slaves_2_awqos),
.v_to_slaves_2_awregion(fabric_2x3$v_to_slaves_2_awregion),
.v_to_slaves_2_wvalid(fabric_2x3$v_to_slaves_2_wvalid),
.v_to_slaves_2_wdata(fabric_2x3$v_to_slaves_2_wdata),
.v_to_slaves_2_wstrb(fabric_2x3$v_to_slaves_2_wstrb),
.v_to_slaves_2_wlast(fabric_2x3$v_to_slaves_2_wlast),
.v_to_slaves_2_bready(fabric_2x3$v_to_slaves_2_bready),
.v_to_slaves_2_arvalid(fabric_2x3$v_to_slaves_2_arvalid),
.v_to_slaves_2_arid(fabric_2x3$v_to_slaves_2_arid),
.v_to_slaves_2_araddr(fabric_2x3$v_to_slaves_2_araddr),
.v_to_slaves_2_arlen(fabric_2x3$v_to_slaves_2_arlen),
.v_to_slaves_2_arsize(fabric_2x3$v_to_slaves_2_arsize),
.v_to_slaves_2_arburst(fabric_2x3$v_to_slaves_2_arburst),
.v_to_slaves_2_arlock(fabric_2x3$v_to_slaves_2_arlock),
.v_to_slaves_2_arcache(fabric_2x3$v_to_slaves_2_arcache),
.v_to_slaves_2_arprot(fabric_2x3$v_to_slaves_2_arprot),
.v_to_slaves_2_arqos(fabric_2x3$v_to_slaves_2_arqos),
.v_to_slaves_2_arregion(fabric_2x3$v_to_slaves_2_arregion),
.v_to_slaves_2_rready(fabric_2x3$v_to_slaves_2_rready));
// submodule hart0_reset
ResetEither hart0_reset(.A_RST(RST_N),
.B_RST(dm_hart0_reset_controller$OUT_RST),
.RST_OUT(hart0_reset$RST_OUT));
// submodule plic
mkPLIC_16_2_7 plic(.CLK(CLK),
.RST_N(RST_N),
.axi4_slave_araddr(plic$axi4_slave_araddr),
.axi4_slave_arburst(plic$axi4_slave_arburst),
.axi4_slave_arcache(plic$axi4_slave_arcache),
.axi4_slave_arid(plic$axi4_slave_arid),
.axi4_slave_arlen(plic$axi4_slave_arlen),
.axi4_slave_arlock(plic$axi4_slave_arlock),
.axi4_slave_arprot(plic$axi4_slave_arprot),
.axi4_slave_arqos(plic$axi4_slave_arqos),
.axi4_slave_arregion(plic$axi4_slave_arregion),
.axi4_slave_arsize(plic$axi4_slave_arsize),
.axi4_slave_arvalid(plic$axi4_slave_arvalid),
.axi4_slave_awaddr(plic$axi4_slave_awaddr),
.axi4_slave_awburst(plic$axi4_slave_awburst),
.axi4_slave_awcache(plic$axi4_slave_awcache),
.axi4_slave_awid(plic$axi4_slave_awid),
.axi4_slave_awlen(plic$axi4_slave_awlen),
.axi4_slave_awlock(plic$axi4_slave_awlock),
.axi4_slave_awprot(plic$axi4_slave_awprot),
.axi4_slave_awqos(plic$axi4_slave_awqos),
.axi4_slave_awregion(plic$axi4_slave_awregion),
.axi4_slave_awsize(plic$axi4_slave_awsize),
.axi4_slave_awvalid(plic$axi4_slave_awvalid),
.axi4_slave_bready(plic$axi4_slave_bready),
.axi4_slave_rready(plic$axi4_slave_rready),
.axi4_slave_wdata(plic$axi4_slave_wdata),
.axi4_slave_wlast(plic$axi4_slave_wlast),
.axi4_slave_wstrb(plic$axi4_slave_wstrb),
.axi4_slave_wvalid(plic$axi4_slave_wvalid),
.set_addr_map_addr_base(plic$set_addr_map_addr_base),
.set_addr_map_addr_lim(plic$set_addr_map_addr_lim),
.set_verbosity_verbosity(plic$set_verbosity_verbosity),
.v_sources_0_m_interrupt_req_set_not_clear(plic$v_sources_0_m_interrupt_req_set_not_clear),
.v_sources_10_m_interrupt_req_set_not_clear(plic$v_sources_10_m_interrupt_req_set_not_clear),
.v_sources_11_m_interrupt_req_set_not_clear(plic$v_sources_11_m_interrupt_req_set_not_clear),
.v_sources_12_m_interrupt_req_set_not_clear(plic$v_sources_12_m_interrupt_req_set_not_clear),
.v_sources_13_m_interrupt_req_set_not_clear(plic$v_sources_13_m_interrupt_req_set_not_clear),
.v_sources_14_m_interrupt_req_set_not_clear(plic$v_sources_14_m_interrupt_req_set_not_clear),
.v_sources_15_m_interrupt_req_set_not_clear(plic$v_sources_15_m_interrupt_req_set_not_clear),
.v_sources_1_m_interrupt_req_set_not_clear(plic$v_sources_1_m_interrupt_req_set_not_clear),
.v_sources_2_m_interrupt_req_set_not_clear(plic$v_sources_2_m_interrupt_req_set_not_clear),
.v_sources_3_m_interrupt_req_set_not_clear(plic$v_sources_3_m_interrupt_req_set_not_clear),
.v_sources_4_m_interrupt_req_set_not_clear(plic$v_sources_4_m_interrupt_req_set_not_clear),
.v_sources_5_m_interrupt_req_set_not_clear(plic$v_sources_5_m_interrupt_req_set_not_clear),
.v_sources_6_m_interrupt_req_set_not_clear(plic$v_sources_6_m_interrupt_req_set_not_clear),
.v_sources_7_m_interrupt_req_set_not_clear(plic$v_sources_7_m_interrupt_req_set_not_clear),
.v_sources_8_m_interrupt_req_set_not_clear(plic$v_sources_8_m_interrupt_req_set_not_clear),
.v_sources_9_m_interrupt_req_set_not_clear(plic$v_sources_9_m_interrupt_req_set_not_clear),
.EN_set_verbosity(plic$EN_set_verbosity),
.EN_show_PLIC_state(plic$EN_show_PLIC_state),
.EN_server_reset_request_put(plic$EN_server_reset_request_put),
.EN_server_reset_response_get(plic$EN_server_reset_response_get),
.EN_set_addr_map(plic$EN_set_addr_map),
.RDY_set_verbosity(),
.RDY_show_PLIC_state(),
.RDY_server_reset_request_put(),
.RDY_server_reset_response_get(),
.RDY_set_addr_map(),
.axi4_slave_awready(plic$axi4_slave_awready),
.axi4_slave_wready(plic$axi4_slave_wready),
.axi4_slave_bvalid(plic$axi4_slave_bvalid),
.axi4_slave_bid(plic$axi4_slave_bid),
.axi4_slave_bresp(plic$axi4_slave_bresp),
.axi4_slave_arready(plic$axi4_slave_arready),
.axi4_slave_rvalid(plic$axi4_slave_rvalid),
.axi4_slave_rid(plic$axi4_slave_rid),
.axi4_slave_rdata(plic$axi4_slave_rdata),
.axi4_slave_rresp(plic$axi4_slave_rresp),
.axi4_slave_rlast(plic$axi4_slave_rlast),
.v_targets_0_m_eip(plic$v_targets_0_m_eip),
.v_targets_1_m_eip(plic$v_targets_1_m_eip));
// submodule proc
mkProc proc(.CLK(CLK),
.RST_N(hart0_reset$RST_OUT),
.debug_module_mem_server_araddr(proc$debug_module_mem_server_araddr),
.debug_module_mem_server_arburst(proc$debug_module_mem_server_arburst),
.debug_module_mem_server_arcache(proc$debug_module_mem_server_arcache),
.debug_module_mem_server_arid(proc$debug_module_mem_server_arid),
.debug_module_mem_server_arlen(proc$debug_module_mem_server_arlen),
.debug_module_mem_server_arlock(proc$debug_module_mem_server_arlock),
.debug_module_mem_server_arprot(proc$debug_module_mem_server_arprot),
.debug_module_mem_server_arqos(proc$debug_module_mem_server_arqos),
.debug_module_mem_server_arregion(proc$debug_module_mem_server_arregion),
.debug_module_mem_server_arsize(proc$debug_module_mem_server_arsize),
.debug_module_mem_server_arvalid(proc$debug_module_mem_server_arvalid),
.debug_module_mem_server_awaddr(proc$debug_module_mem_server_awaddr),
.debug_module_mem_server_awburst(proc$debug_module_mem_server_awburst),
.debug_module_mem_server_awcache(proc$debug_module_mem_server_awcache),
.debug_module_mem_server_awid(proc$debug_module_mem_server_awid),
.debug_module_mem_server_awlen(proc$debug_module_mem_server_awlen),
.debug_module_mem_server_awlock(proc$debug_module_mem_server_awlock),
.debug_module_mem_server_awprot(proc$debug_module_mem_server_awprot),
.debug_module_mem_server_awqos(proc$debug_module_mem_server_awqos),
.debug_module_mem_server_awregion(proc$debug_module_mem_server_awregion),
.debug_module_mem_server_awsize(proc$debug_module_mem_server_awsize),
.debug_module_mem_server_awvalid(proc$debug_module_mem_server_awvalid),
.debug_module_mem_server_bready(proc$debug_module_mem_server_bready),
.debug_module_mem_server_rready(proc$debug_module_mem_server_rready),
.debug_module_mem_server_wdata(proc$debug_module_mem_server_wdata),
.debug_module_mem_server_wlast(proc$debug_module_mem_server_wlast),
.debug_module_mem_server_wstrb(proc$debug_module_mem_server_wstrb),
.debug_module_mem_server_wvalid(proc$debug_module_mem_server_wvalid),
.hart0_csr_mem_server_request_put(proc$hart0_csr_mem_server_request_put),
.hart0_fpr_mem_server_request_put(proc$hart0_fpr_mem_server_request_put),
.hart0_gpr_mem_server_request_put(proc$hart0_gpr_mem_server_request_put),
.hart0_put_other_req_put(proc$hart0_put_other_req_put),
.hart0_run_halt_server_request_put(proc$hart0_run_halt_server_request_put),
.m_external_interrupt_req_set_not_clear(proc$m_external_interrupt_req_set_not_clear),
.master0_arready(proc$master0_arready),
.master0_awready(proc$master0_awready),
.master0_bid(proc$master0_bid),
.master0_bresp(proc$master0_bresp),
.master0_bvalid(proc$master0_bvalid),
.master0_rdata(proc$master0_rdata),
.master0_rid(proc$master0_rid),
.master0_rlast(proc$master0_rlast),
.master0_rresp(proc$master0_rresp),
.master0_rvalid(proc$master0_rvalid),
.master0_wready(proc$master0_wready),
.master1_arready(proc$master1_arready),
.master1_awready(proc$master1_awready),
.master1_bid(proc$master1_bid),
.master1_bresp(proc$master1_bresp),
.master1_bvalid(proc$master1_bvalid),
.master1_rdata(proc$master1_rdata),
.master1_rid(proc$master1_rid),
.master1_rlast(proc$master1_rlast),
.master1_rresp(proc$master1_rresp),
.master1_rvalid(proc$master1_rvalid),
.master1_wready(proc$master1_wready),
.non_maskable_interrupt_req_set_not_clear(proc$non_maskable_interrupt_req_set_not_clear),
.s_external_interrupt_req_set_not_clear(proc$s_external_interrupt_req_set_not_clear),
.set_verbosity_verbosity(proc$set_verbosity_verbosity),
.start_fromhostAddr(proc$start_fromhostAddr),
.start_startpc(proc$start_startpc),
.start_tohostAddr(proc$start_tohostAddr),
.EN_start(proc$EN_start),
.EN_set_verbosity(proc$EN_set_verbosity),
.EN_hart0_run_halt_server_request_put(proc$EN_hart0_run_halt_server_request_put),
.EN_hart0_run_halt_server_response_get(proc$EN_hart0_run_halt_server_response_get),
.EN_hart0_gpr_mem_server_request_put(proc$EN_hart0_gpr_mem_server_request_put),
.EN_hart0_gpr_mem_server_response_get(proc$EN_hart0_gpr_mem_server_response_get),
.EN_hart0_fpr_mem_server_request_put(proc$EN_hart0_fpr_mem_server_request_put),
.EN_hart0_fpr_mem_server_response_get(proc$EN_hart0_fpr_mem_server_response_get),
.EN_hart0_csr_mem_server_request_put(proc$EN_hart0_csr_mem_server_request_put),
.EN_hart0_csr_mem_server_response_get(proc$EN_hart0_csr_mem_server_response_get),
.EN_hart0_put_other_req_put(proc$EN_hart0_put_other_req_put),
.EN_v_to_TV_0_get(proc$EN_v_to_TV_0_get),
.EN_v_to_TV_1_get(proc$EN_v_to_TV_1_get),
.RDY_start(proc$RDY_start),
.master0_awvalid(proc$master0_awvalid),
.master0_awid(proc$master0_awid),
.master0_awaddr(proc$master0_awaddr),
.master0_awlen(proc$master0_awlen),
.master0_awsize(proc$master0_awsize),
.master0_awburst(proc$master0_awburst),
.master0_awlock(proc$master0_awlock),
.master0_awcache(proc$master0_awcache),
.master0_awprot(proc$master0_awprot),
.master0_awqos(proc$master0_awqos),
.master0_awregion(proc$master0_awregion),
.master0_wvalid(proc$master0_wvalid),
.master0_wdata(proc$master0_wdata),
.master0_wstrb(proc$master0_wstrb),
.master0_wlast(proc$master0_wlast),
.master0_bready(proc$master0_bready),
.master0_arvalid(proc$master0_arvalid),
.master0_arid(proc$master0_arid),
.master0_araddr(proc$master0_araddr),
.master0_arlen(proc$master0_arlen),
.master0_arsize(proc$master0_arsize),
.master0_arburst(proc$master0_arburst),
.master0_arlock(proc$master0_arlock),
.master0_arcache(proc$master0_arcache),
.master0_arprot(proc$master0_arprot),
.master0_arqos(proc$master0_arqos),
.master0_arregion(proc$master0_arregion),
.master0_rready(proc$master0_rready),
.master1_awvalid(proc$master1_awvalid),
.master1_awid(proc$master1_awid),
.master1_awaddr(proc$master1_awaddr),
.master1_awlen(proc$master1_awlen),
.master1_awsize(proc$master1_awsize),
.master1_awburst(proc$master1_awburst),
.master1_awlock(proc$master1_awlock),
.master1_awcache(proc$master1_awcache),
.master1_awprot(proc$master1_awprot),
.master1_awqos(proc$master1_awqos),
.master1_awregion(proc$master1_awregion),
.master1_wvalid(proc$master1_wvalid),
.master1_wdata(proc$master1_wdata),
.master1_wstrb(proc$master1_wstrb),
.master1_wlast(proc$master1_wlast),
.master1_bready(proc$master1_bready),
.master1_arvalid(proc$master1_arvalid),
.master1_arid(proc$master1_arid),
.master1_araddr(proc$master1_araddr),
.master1_arlen(proc$master1_arlen),
.master1_arsize(proc$master1_arsize),
.master1_arburst(proc$master1_arburst),
.master1_arlock(proc$master1_arlock),
.master1_arcache(proc$master1_arcache),
.master1_arprot(proc$master1_arprot),
.master1_arqos(proc$master1_arqos),
.master1_arregion(proc$master1_arregion),
.master1_rready(proc$master1_rready),
.RDY_set_verbosity(),
.debug_module_mem_server_awready(proc$debug_module_mem_server_awready),
.debug_module_mem_server_wready(proc$debug_module_mem_server_wready),
.debug_module_mem_server_bvalid(proc$debug_module_mem_server_bvalid),
.debug_module_mem_server_bid(proc$debug_module_mem_server_bid),
.debug_module_mem_server_bresp(proc$debug_module_mem_server_bresp),
.debug_module_mem_server_arready(proc$debug_module_mem_server_arready),
.debug_module_mem_server_rvalid(proc$debug_module_mem_server_rvalid),
.debug_module_mem_server_rid(proc$debug_module_mem_server_rid),
.debug_module_mem_server_rdata(proc$debug_module_mem_server_rdata),
.debug_module_mem_server_rresp(proc$debug_module_mem_server_rresp),
.debug_module_mem_server_rlast(proc$debug_module_mem_server_rlast),
.RDY_hart0_run_halt_server_request_put(proc$RDY_hart0_run_halt_server_request_put),
.hart0_run_halt_server_response_get(proc$hart0_run_halt_server_response_get),
.RDY_hart0_run_halt_server_response_get(proc$RDY_hart0_run_halt_server_response_get),
.RDY_hart0_gpr_mem_server_request_put(proc$RDY_hart0_gpr_mem_server_request_put),
.hart0_gpr_mem_server_response_get(proc$hart0_gpr_mem_server_response_get),
.RDY_hart0_gpr_mem_server_response_get(proc$RDY_hart0_gpr_mem_server_response_get),
.RDY_hart0_fpr_mem_server_request_put(),
.hart0_fpr_mem_server_response_get(),
.RDY_hart0_fpr_mem_server_response_get(),
.RDY_hart0_csr_mem_server_request_put(proc$RDY_hart0_csr_mem_server_request_put),
.hart0_csr_mem_server_response_get(proc$hart0_csr_mem_server_response_get),
.RDY_hart0_csr_mem_server_response_get(proc$RDY_hart0_csr_mem_server_response_get),
.RDY_hart0_put_other_req_put(),
.v_to_TV_0_get(proc$v_to_TV_0_get),
.RDY_v_to_TV_0_get(proc$RDY_v_to_TV_0_get),
.v_to_TV_1_get(proc$v_to_TV_1_get),
.RDY_v_to_TV_1_get(proc$RDY_v_to_TV_1_get));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_flash_mem_addr_base(),
.m_flash_mem_addr_size(),
.m_flash_mem_addr_lim(),
.m_ethernet_0_addr_base(),
.m_ethernet_0_addr_size(),
.m_ethernet_0_addr_lim(),
.m_dma_0_addr_base(),
.m_dma_0_addr_size(),
.m_dma_0_addr_lim(),
.m_uart16550_0_addr_base(),
.m_uart16550_0_addr_size(),
.m_uart16550_0_addr_lim(),
.m_gpio_0_addr_base(),
.m_gpio_0_addr_size(),
.m_gpio_0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_ddr4_0_uncached_addr_base(),
.m_ddr4_0_uncached_addr_size(),
.m_ddr4_0_uncached_addr_lim(),
.m_ddr4_0_cached_addr_base(),
.m_ddr4_0_cached_addr_size(),
.m_ddr4_0_cached_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule tv_encode
mkTV_Encode tv_encode(.CLK(CLK),
.RST_N(RST_N),
.dm_in_put(tv_encode$dm_in_put),
.v_cpu_in_0_put(tv_encode$v_cpu_in_0_put),
.v_cpu_in_1_put(tv_encode$v_cpu_in_1_put),
.EN_v_cpu_in_0_put(tv_encode$EN_v_cpu_in_0_put),
.EN_v_cpu_in_1_put(tv_encode$EN_v_cpu_in_1_put),
.EN_dm_in_put(tv_encode$EN_dm_in_put),
.EN_out_get(tv_encode$EN_out_get),
.RDY_v_cpu_in_0_put(tv_encode$RDY_v_cpu_in_0_put),
.RDY_v_cpu_in_1_put(tv_encode$RDY_v_cpu_in_1_put),
.RDY_dm_in_put(tv_encode$RDY_dm_in_put),
.out_get(tv_encode$out_get),
.RDY_out_get(tv_encode$RDY_out_get));
// submodule v_td2_to_td_0
mkTrace_Data2_to_Trace_Data v_td2_to_td_0(.CLK(CLK),
.RST_N(RST_N),
.in_put(v_td2_to_td_0$in_put),
.EN_in_put(v_td2_to_td_0$EN_in_put),
.EN_out_get(v_td2_to_td_0$EN_out_get),
.RDY_in_put(v_td2_to_td_0$RDY_in_put),
.out_get(v_td2_to_td_0$out_get),
.RDY_out_get(v_td2_to_td_0$RDY_out_get));
// submodule v_td2_to_td_1
mkTrace_Data2_to_Trace_Data v_td2_to_td_1(.CLK(CLK),
.RST_N(RST_N),
.in_put(v_td2_to_td_1$in_put),
.EN_in_put(v_td2_to_td_1$EN_in_put),
.EN_out_get(v_td2_to_td_1$EN_out_get),
.RDY_in_put(v_td2_to_td_1$RDY_in_put),
.out_get(v_td2_to_td_1$out_get),
.RDY_out_get(v_td2_to_td_1$RDY_out_get));
// rule RL_rl_dm_hart0_reset
assign CAN_FIRE_RL_rl_dm_hart0_reset =
debug_module$RDY_hart0_reset_client_request_get &&
rg_hart0_reset_delay == 8'd0 ;
assign WILL_FIRE_RL_rl_dm_hart0_reset = CAN_FIRE_RL_rl_dm_hart0_reset ;
// rule RL_rl_dm_hart0_reset_wait
assign CAN_FIRE_RL_rl_dm_hart0_reset_wait =
(rg_hart0_reset_delay != 8'd1 ||
proc$RDY_start &&
debug_module$RDY_hart0_reset_client_response_put) &&
rg_hart0_reset_delay != 8'd0 ;
assign WILL_FIRE_RL_rl_dm_hart0_reset_wait =
CAN_FIRE_RL_rl_dm_hart0_reset_wait && !EN_start ;
// rule RL_ClientServerRequest
assign CAN_FIRE_RL_ClientServerRequest =
proc$RDY_hart0_run_halt_server_request_put &&
debug_module$RDY_hart0_client_run_halt_request_get ;
assign WILL_FIRE_RL_ClientServerRequest = CAN_FIRE_RL_ClientServerRequest ;
// rule RL_ClientServerResponse
assign CAN_FIRE_RL_ClientServerResponse =
proc$RDY_hart0_run_halt_server_response_get &&
debug_module$RDY_hart0_client_run_halt_response_put ;
assign WILL_FIRE_RL_ClientServerResponse =
CAN_FIRE_RL_ClientServerResponse ;
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
debug_module$RDY_hart0_get_other_req_get ;
assign WILL_FIRE_RL_mkConnectionGetPut =
debug_module$RDY_hart0_get_other_req_get ;
// rule RL_mkConnectionGetPut_1
assign CAN_FIRE_RL_mkConnectionGetPut_1 =
proc$RDY_v_to_TV_0_get && v_td2_to_td_0$RDY_in_put ;
assign WILL_FIRE_RL_mkConnectionGetPut_1 =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
// rule RL_mkConnectionGetPut_2
assign CAN_FIRE_RL_mkConnectionGetPut_2 =
tv_encode$RDY_v_cpu_in_0_put && v_td2_to_td_0$RDY_out_get ;
assign WILL_FIRE_RL_mkConnectionGetPut_2 =
CAN_FIRE_RL_mkConnectionGetPut_2 ;
// rule RL_mkConnectionGetPut_3
assign CAN_FIRE_RL_mkConnectionGetPut_3 =
proc$RDY_v_to_TV_1_get && v_td2_to_td_1$RDY_in_put ;
assign WILL_FIRE_RL_mkConnectionGetPut_3 =
CAN_FIRE_RL_mkConnectionGetPut_3 ;
// rule RL_mkConnectionGetPut_4
assign CAN_FIRE_RL_mkConnectionGetPut_4 =
tv_encode$RDY_v_cpu_in_1_put && v_td2_to_td_1$RDY_out_get ;
assign WILL_FIRE_RL_mkConnectionGetPut_4 =
CAN_FIRE_RL_mkConnectionGetPut_4 ;
// rule RL_rl_wr_addr_channel
assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
// rule RL_rl_wr_data_channel
assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ;
// rule RL_rl_wr_response_channel
assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ;
// rule RL_rl_rd_addr_channel
assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
// rule RL_rl_rd_data_channel
assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ;
// rule RL_ClientServerRequest_1
assign CAN_FIRE_RL_ClientServerRequest_1 =
debug_module$RDY_hart0_gpr_mem_client_request_get &&
dm_gpr_tap_ifc$RDY_server_request_put ;
assign WILL_FIRE_RL_ClientServerRequest_1 =
CAN_FIRE_RL_ClientServerRequest_1 ;
// rule RL_ClientServerResponse_1
assign CAN_FIRE_RL_ClientServerResponse_1 =
debug_module$RDY_hart0_gpr_mem_client_response_put &&
dm_gpr_tap_ifc$RDY_server_response_get ;
assign WILL_FIRE_RL_ClientServerResponse_1 =
CAN_FIRE_RL_ClientServerResponse_1 ;
// rule RL_ClientServerResponse_2
assign CAN_FIRE_RL_ClientServerResponse_2 =
proc$RDY_hart0_gpr_mem_server_response_get &&
dm_gpr_tap_ifc$RDY_client_response_put ;
assign WILL_FIRE_RL_ClientServerResponse_2 =
CAN_FIRE_RL_ClientServerResponse_2 ;
// rule RL_rl_merge_dm_gpr_trace_data
assign CAN_FIRE_RL_rl_merge_dm_gpr_trace_data =
tv_encode$RDY_dm_in_put &&
dm_gpr_tap_ifc$RDY_trace_data_out_get ;
assign WILL_FIRE_RL_rl_merge_dm_gpr_trace_data =
CAN_FIRE_RL_rl_merge_dm_gpr_trace_data ;
// rule RL_ClientServerRequest_3
assign CAN_FIRE_RL_ClientServerRequest_3 =
debug_module$RDY_hart0_csr_mem_client_request_get &&
dm_csr_tap$RDY_server_request_put ;
assign WILL_FIRE_RL_ClientServerRequest_3 =
CAN_FIRE_RL_ClientServerRequest_3 ;
// rule RL_ClientServerResponse_3
assign CAN_FIRE_RL_ClientServerResponse_3 =
debug_module$RDY_hart0_csr_mem_client_response_put &&
dm_csr_tap$RDY_server_response_get ;
assign WILL_FIRE_RL_ClientServerResponse_3 =
CAN_FIRE_RL_ClientServerResponse_3 ;
// rule RL_ClientServerResponse_4
assign CAN_FIRE_RL_ClientServerResponse_4 =
proc$RDY_hart0_csr_mem_server_response_get &&
dm_csr_tap$RDY_client_response_put ;
assign WILL_FIRE_RL_ClientServerResponse_4 =
CAN_FIRE_RL_ClientServerResponse_4 ;
// rule RL_rl_merge_dm_mem_trace_data
assign CAN_FIRE_RL_rl_merge_dm_mem_trace_data =
tv_encode$RDY_dm_in_put && dm_mem_tap$RDY_trace_data_out_get ;
assign WILL_FIRE_RL_rl_merge_dm_mem_trace_data =
CAN_FIRE_RL_rl_merge_dm_mem_trace_data &&
!WILL_FIRE_RL_rl_merge_dm_csr_trace_data &&
!WILL_FIRE_RL_rl_merge_dm_gpr_trace_data ;
// rule RL_rl_merge_dm_csr_trace_data
assign CAN_FIRE_RL_rl_merge_dm_csr_trace_data =
tv_encode$RDY_dm_in_put && dm_csr_tap$RDY_trace_data_out_get ;
assign WILL_FIRE_RL_rl_merge_dm_csr_trace_data =
CAN_FIRE_RL_rl_merge_dm_csr_trace_data &&
!WILL_FIRE_RL_rl_merge_dm_gpr_trace_data ;
// rule RL_rl_wr_addr_channel_1
assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
// rule RL_rl_wr_data_channel_1
assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_response_channel_1
assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
// rule RL_rl_rd_addr_channel_1
assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
// rule RL_rl_rd_data_channel_1
assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_addr_channel_2
assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
// rule RL_rl_wr_data_channel_2
assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_response_channel_2
assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
// rule RL_rl_rd_addr_channel_2
assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
// rule RL_rl_rd_data_channel_2
assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_addr_channel_3
assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
// rule RL_rl_wr_data_channel_3
assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_response_channel_3
assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
// rule RL_rl_rd_addr_channel_3
assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
// rule RL_rl_rd_data_channel_3
assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_addr_channel_4
assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ;
// rule RL_rl_wr_data_channel_4
assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ;
// rule RL_rl_wr_response_channel_4
assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ;
// rule RL_rl_rd_addr_channel_4
assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ;
// rule RL_rl_rd_data_channel_4
assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ;
// rule RL_rl_relay_external_interrupts
assign CAN_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
assign WILL_FIRE_RL_rl_relay_external_interrupts = 1'd1 ;
// rule RL_ClientServerRequest_2
assign CAN_FIRE_RL_ClientServerRequest_2 =
proc$RDY_hart0_gpr_mem_server_request_put &&
dm_gpr_tap_ifc$RDY_client_request_get ;
assign WILL_FIRE_RL_ClientServerRequest_2 =
CAN_FIRE_RL_ClientServerRequest_2 ;
// rule RL_ClientServerRequest_4
assign CAN_FIRE_RL_ClientServerRequest_4 =
proc$RDY_hart0_csr_mem_server_request_put &&
dm_csr_tap$RDY_client_request_get ;
assign WILL_FIRE_RL_ClientServerRequest_4 =
CAN_FIRE_RL_ClientServerRequest_4 ;
// inputs to muxes for submodule ports
assign MUX_proc$start_1__SEL_1 =
WILL_FIRE_RL_rl_dm_hart0_reset_wait &&
rg_hart0_reset_delay == 8'd1 ;
assign MUX_rg_hart0_reset_delay$write_1__VAL_1 =
rg_hart0_reset_delay - 8'd1 ;
// register rg_fromhost_addr
assign rg_fromhost_addr$D_IN = start_fromhost_addr ;
assign rg_fromhost_addr$EN = EN_start ;
// register rg_hart0_reset_delay
assign rg_hart0_reset_delay$D_IN =
WILL_FIRE_RL_rl_dm_hart0_reset_wait ?
MUX_rg_hart0_reset_delay$write_1__VAL_1 :
8'd210 ;
assign rg_hart0_reset_delay$EN =
WILL_FIRE_RL_rl_dm_hart0_reset_wait ||
WILL_FIRE_RL_rl_dm_hart0_reset ;
// register rg_tohost_addr
assign rg_tohost_addr$D_IN = start_tohost_addr ;
assign rg_tohost_addr$EN = EN_start ;
// submodule debug_module
assign debug_module$dmi_read_addr_dm_addr = dmi_read_addr_dm_addr ;
assign debug_module$dmi_write_dm_addr = dmi_write_dm_addr ;
assign debug_module$dmi_write_dm_word = dmi_write_dm_word ;
assign debug_module$hart0_client_run_halt_response_put =
proc$hart0_run_halt_server_response_get ;
assign debug_module$hart0_csr_mem_client_response_put =
dm_csr_tap$server_response_get ;
assign debug_module$hart0_fpr_mem_client_response_put = 65'h0 ;
assign debug_module$hart0_gpr_mem_client_response_put =
dm_gpr_tap_ifc$server_response_get ;
assign debug_module$hart0_reset_client_response_put = 1'd1 ;
assign debug_module$master_arready = dm_mem_tap$slave_arready ;
assign debug_module$master_awready = dm_mem_tap$slave_awready ;
assign debug_module$master_bid = dm_mem_tap$slave_bid ;
assign debug_module$master_bresp = dm_mem_tap$slave_bresp ;
assign debug_module$master_bvalid = dm_mem_tap$slave_bvalid ;
assign debug_module$master_rdata = dm_mem_tap$slave_rdata ;
assign debug_module$master_rid = dm_mem_tap$slave_rid ;
assign debug_module$master_rlast = dm_mem_tap$slave_rlast ;
assign debug_module$master_rresp = dm_mem_tap$slave_rresp ;
assign debug_module$master_rvalid = dm_mem_tap$slave_rvalid ;
assign debug_module$master_wready = dm_mem_tap$slave_wready ;
assign debug_module$ndm_reset_client_response_put =
ndm_reset_client_response_put ;
assign debug_module$EN_dmi_read_addr = EN_dmi_read_addr ;
assign debug_module$EN_dmi_read_data = EN_dmi_read_data ;
assign debug_module$EN_dmi_write = EN_dmi_write ;
assign debug_module$EN_hart0_reset_client_request_get =
CAN_FIRE_RL_rl_dm_hart0_reset ;
assign debug_module$EN_hart0_reset_client_response_put =
MUX_proc$start_1__SEL_1 ;
assign debug_module$EN_hart0_client_run_halt_request_get =
CAN_FIRE_RL_ClientServerRequest ;
assign debug_module$EN_hart0_client_run_halt_response_put =
CAN_FIRE_RL_ClientServerResponse ;
assign debug_module$EN_hart0_get_other_req_get =
debug_module$RDY_hart0_get_other_req_get ;
assign debug_module$EN_hart0_gpr_mem_client_request_get =
CAN_FIRE_RL_ClientServerRequest_1 ;
assign debug_module$EN_hart0_gpr_mem_client_response_put =
CAN_FIRE_RL_ClientServerResponse_1 ;
assign debug_module$EN_hart0_fpr_mem_client_request_get = 1'b0 ;
assign debug_module$EN_hart0_fpr_mem_client_response_put = 1'b0 ;
assign debug_module$EN_hart0_csr_mem_client_request_get =
CAN_FIRE_RL_ClientServerRequest_3 ;
assign debug_module$EN_hart0_csr_mem_client_response_put =
CAN_FIRE_RL_ClientServerResponse_3 ;
assign debug_module$EN_ndm_reset_client_request_get =
EN_ndm_reset_client_request_get ;
assign debug_module$EN_ndm_reset_client_response_put =
EN_ndm_reset_client_response_put ;
// submodule dm_csr_tap
assign dm_csr_tap$client_response_put =
proc$hart0_csr_mem_server_response_get ;
assign dm_csr_tap$server_request_put =
debug_module$hart0_csr_mem_client_request_get ;
assign dm_csr_tap$EN_client_request_get =
CAN_FIRE_RL_ClientServerRequest_4 ;
assign dm_csr_tap$EN_client_response_put =
CAN_FIRE_RL_ClientServerResponse_4 ;
assign dm_csr_tap$EN_server_request_put =
CAN_FIRE_RL_ClientServerRequest_3 ;
assign dm_csr_tap$EN_server_response_get =
CAN_FIRE_RL_ClientServerResponse_3 ;
assign dm_csr_tap$EN_trace_data_out_get =
WILL_FIRE_RL_rl_merge_dm_csr_trace_data ;
// submodule dm_gpr_tap_ifc
assign dm_gpr_tap_ifc$client_response_put =
proc$hart0_gpr_mem_server_response_get ;
assign dm_gpr_tap_ifc$server_request_put =
debug_module$hart0_gpr_mem_client_request_get ;
assign dm_gpr_tap_ifc$EN_client_request_get =
CAN_FIRE_RL_ClientServerRequest_2 ;
assign dm_gpr_tap_ifc$EN_client_response_put =
CAN_FIRE_RL_ClientServerResponse_2 ;
assign dm_gpr_tap_ifc$EN_server_request_put =
CAN_FIRE_RL_ClientServerRequest_1 ;
assign dm_gpr_tap_ifc$EN_server_response_get =
CAN_FIRE_RL_ClientServerResponse_1 ;
assign dm_gpr_tap_ifc$EN_trace_data_out_get =
CAN_FIRE_RL_rl_merge_dm_gpr_trace_data ;
// submodule dm_hart0_reset_controller
assign dm_hart0_reset_controller$ASSERT_IN = CAN_FIRE_RL_rl_dm_hart0_reset ;
// submodule dm_mem_tap
assign dm_mem_tap$master_arready = fabric_2x3$v_from_masters_1_arready ;
assign dm_mem_tap$master_awready = fabric_2x3$v_from_masters_1_awready ;
assign dm_mem_tap$master_bid = fabric_2x3$v_from_masters_1_bid ;
assign dm_mem_tap$master_bresp = fabric_2x3$v_from_masters_1_bresp ;
assign dm_mem_tap$master_bvalid = fabric_2x3$v_from_masters_1_bvalid ;
assign dm_mem_tap$master_rdata = fabric_2x3$v_from_masters_1_rdata ;
assign dm_mem_tap$master_rid = fabric_2x3$v_from_masters_1_rid ;
assign dm_mem_tap$master_rlast = fabric_2x3$v_from_masters_1_rlast ;
assign dm_mem_tap$master_rresp = fabric_2x3$v_from_masters_1_rresp ;
assign dm_mem_tap$master_rvalid = fabric_2x3$v_from_masters_1_rvalid ;
assign dm_mem_tap$master_wready = fabric_2x3$v_from_masters_1_wready ;
assign dm_mem_tap$slave_araddr = debug_module$master_araddr ;
assign dm_mem_tap$slave_arburst = debug_module$master_arburst ;
assign dm_mem_tap$slave_arcache = debug_module$master_arcache ;
assign dm_mem_tap$slave_arid = debug_module$master_arid ;
assign dm_mem_tap$slave_arlen = debug_module$master_arlen ;
assign dm_mem_tap$slave_arlock = debug_module$master_arlock ;
assign dm_mem_tap$slave_arprot = debug_module$master_arprot ;
assign dm_mem_tap$slave_arqos = debug_module$master_arqos ;
assign dm_mem_tap$slave_arregion = debug_module$master_arregion ;
assign dm_mem_tap$slave_arsize = debug_module$master_arsize ;
assign dm_mem_tap$slave_arvalid = debug_module$master_arvalid ;
assign dm_mem_tap$slave_awaddr = debug_module$master_awaddr ;
assign dm_mem_tap$slave_awburst = debug_module$master_awburst ;
assign dm_mem_tap$slave_awcache = debug_module$master_awcache ;
assign dm_mem_tap$slave_awid = debug_module$master_awid ;
assign dm_mem_tap$slave_awlen = debug_module$master_awlen ;
assign dm_mem_tap$slave_awlock = debug_module$master_awlock ;
assign dm_mem_tap$slave_awprot = debug_module$master_awprot ;
assign dm_mem_tap$slave_awqos = debug_module$master_awqos ;
assign dm_mem_tap$slave_awregion = debug_module$master_awregion ;
assign dm_mem_tap$slave_awsize = debug_module$master_awsize ;
assign dm_mem_tap$slave_awvalid = debug_module$master_awvalid ;
assign dm_mem_tap$slave_bready = debug_module$master_bready ;
assign dm_mem_tap$slave_rready = debug_module$master_rready ;
assign dm_mem_tap$slave_wdata = debug_module$master_wdata ;
assign dm_mem_tap$slave_wlast = debug_module$master_wlast ;
assign dm_mem_tap$slave_wstrb = debug_module$master_wstrb ;
assign dm_mem_tap$slave_wvalid = debug_module$master_wvalid ;
assign dm_mem_tap$EN_trace_data_out_get =
WILL_FIRE_RL_rl_merge_dm_mem_trace_data ;
// submodule fabric_2x3
assign fabric_2x3$set_verbosity_verbosity = 4'h0 ;
assign fabric_2x3$v_from_masters_0_araddr = proc$master1_araddr ;
assign fabric_2x3$v_from_masters_0_arburst = proc$master1_arburst ;
assign fabric_2x3$v_from_masters_0_arcache = proc$master1_arcache ;
assign fabric_2x3$v_from_masters_0_arid = proc$master1_arid ;
assign fabric_2x3$v_from_masters_0_arlen = proc$master1_arlen ;
assign fabric_2x3$v_from_masters_0_arlock = proc$master1_arlock ;
assign fabric_2x3$v_from_masters_0_arprot = proc$master1_arprot ;
assign fabric_2x3$v_from_masters_0_arqos = proc$master1_arqos ;
assign fabric_2x3$v_from_masters_0_arregion = proc$master1_arregion ;
assign fabric_2x3$v_from_masters_0_arsize = proc$master1_arsize ;
assign fabric_2x3$v_from_masters_0_arvalid = proc$master1_arvalid ;
assign fabric_2x3$v_from_masters_0_awaddr = proc$master1_awaddr ;
assign fabric_2x3$v_from_masters_0_awburst = proc$master1_awburst ;
assign fabric_2x3$v_from_masters_0_awcache = proc$master1_awcache ;
assign fabric_2x3$v_from_masters_0_awid = proc$master1_awid ;
assign fabric_2x3$v_from_masters_0_awlen = proc$master1_awlen ;
assign fabric_2x3$v_from_masters_0_awlock = proc$master1_awlock ;
assign fabric_2x3$v_from_masters_0_awprot = proc$master1_awprot ;
assign fabric_2x3$v_from_masters_0_awqos = proc$master1_awqos ;
assign fabric_2x3$v_from_masters_0_awregion = proc$master1_awregion ;
assign fabric_2x3$v_from_masters_0_awsize = proc$master1_awsize ;
assign fabric_2x3$v_from_masters_0_awvalid = proc$master1_awvalid ;
assign fabric_2x3$v_from_masters_0_bready = proc$master1_bready ;
assign fabric_2x3$v_from_masters_0_rready = proc$master1_rready ;
assign fabric_2x3$v_from_masters_0_wdata = proc$master1_wdata ;
assign fabric_2x3$v_from_masters_0_wlast = proc$master1_wlast ;
assign fabric_2x3$v_from_masters_0_wstrb = proc$master1_wstrb ;
assign fabric_2x3$v_from_masters_0_wvalid = proc$master1_wvalid ;
assign fabric_2x3$v_from_masters_1_araddr = dm_mem_tap$master_araddr ;
assign fabric_2x3$v_from_masters_1_arburst = dm_mem_tap$master_arburst ;
assign fabric_2x3$v_from_masters_1_arcache = dm_mem_tap$master_arcache ;
assign fabric_2x3$v_from_masters_1_arid = dm_mem_tap$master_arid ;
assign fabric_2x3$v_from_masters_1_arlen = dm_mem_tap$master_arlen ;
assign fabric_2x3$v_from_masters_1_arlock = dm_mem_tap$master_arlock ;
assign fabric_2x3$v_from_masters_1_arprot = dm_mem_tap$master_arprot ;
assign fabric_2x3$v_from_masters_1_arqos = dm_mem_tap$master_arqos ;
assign fabric_2x3$v_from_masters_1_arregion = dm_mem_tap$master_arregion ;
assign fabric_2x3$v_from_masters_1_arsize = dm_mem_tap$master_arsize ;
assign fabric_2x3$v_from_masters_1_arvalid = dm_mem_tap$master_arvalid ;
assign fabric_2x3$v_from_masters_1_awaddr = dm_mem_tap$master_awaddr ;
assign fabric_2x3$v_from_masters_1_awburst = dm_mem_tap$master_awburst ;
assign fabric_2x3$v_from_masters_1_awcache = dm_mem_tap$master_awcache ;
assign fabric_2x3$v_from_masters_1_awid = dm_mem_tap$master_awid ;
assign fabric_2x3$v_from_masters_1_awlen = dm_mem_tap$master_awlen ;
assign fabric_2x3$v_from_masters_1_awlock = dm_mem_tap$master_awlock ;
assign fabric_2x3$v_from_masters_1_awprot = dm_mem_tap$master_awprot ;
assign fabric_2x3$v_from_masters_1_awqos = dm_mem_tap$master_awqos ;
assign fabric_2x3$v_from_masters_1_awregion = dm_mem_tap$master_awregion ;
assign fabric_2x3$v_from_masters_1_awsize = dm_mem_tap$master_awsize ;
assign fabric_2x3$v_from_masters_1_awvalid = dm_mem_tap$master_awvalid ;
assign fabric_2x3$v_from_masters_1_bready = dm_mem_tap$master_bready ;
assign fabric_2x3$v_from_masters_1_rready = dm_mem_tap$master_rready ;
assign fabric_2x3$v_from_masters_1_wdata = dm_mem_tap$master_wdata ;
assign fabric_2x3$v_from_masters_1_wlast = dm_mem_tap$master_wlast ;
assign fabric_2x3$v_from_masters_1_wstrb = dm_mem_tap$master_wstrb ;
assign fabric_2x3$v_from_masters_1_wvalid = dm_mem_tap$master_wvalid ;
assign fabric_2x3$v_to_slaves_0_arready = cpu_dmem_master_arready ;
assign fabric_2x3$v_to_slaves_0_awready = cpu_dmem_master_awready ;
assign fabric_2x3$v_to_slaves_0_bid = cpu_dmem_master_bid ;
assign fabric_2x3$v_to_slaves_0_bresp = cpu_dmem_master_bresp ;
assign fabric_2x3$v_to_slaves_0_bvalid = cpu_dmem_master_bvalid ;
assign fabric_2x3$v_to_slaves_0_rdata = cpu_dmem_master_rdata ;
assign fabric_2x3$v_to_slaves_0_rid = cpu_dmem_master_rid ;
assign fabric_2x3$v_to_slaves_0_rlast = cpu_dmem_master_rlast ;
assign fabric_2x3$v_to_slaves_0_rresp = cpu_dmem_master_rresp ;
assign fabric_2x3$v_to_slaves_0_rvalid = cpu_dmem_master_rvalid ;
assign fabric_2x3$v_to_slaves_0_wready = cpu_dmem_master_wready ;
assign fabric_2x3$v_to_slaves_1_arready = plic$axi4_slave_arready ;
assign fabric_2x3$v_to_slaves_1_awready = plic$axi4_slave_awready ;
assign fabric_2x3$v_to_slaves_1_bid = plic$axi4_slave_bid ;
assign fabric_2x3$v_to_slaves_1_bresp = plic$axi4_slave_bresp ;
assign fabric_2x3$v_to_slaves_1_bvalid = plic$axi4_slave_bvalid ;
assign fabric_2x3$v_to_slaves_1_rdata = plic$axi4_slave_rdata ;
assign fabric_2x3$v_to_slaves_1_rid = plic$axi4_slave_rid ;
assign fabric_2x3$v_to_slaves_1_rlast = plic$axi4_slave_rlast ;
assign fabric_2x3$v_to_slaves_1_rresp = plic$axi4_slave_rresp ;
assign fabric_2x3$v_to_slaves_1_rvalid = plic$axi4_slave_rvalid ;
assign fabric_2x3$v_to_slaves_1_wready = plic$axi4_slave_wready ;
assign fabric_2x3$v_to_slaves_2_arready =
proc$debug_module_mem_server_arready ;
assign fabric_2x3$v_to_slaves_2_awready =
proc$debug_module_mem_server_awready ;
assign fabric_2x3$v_to_slaves_2_bid = proc$debug_module_mem_server_bid ;
assign fabric_2x3$v_to_slaves_2_bresp = proc$debug_module_mem_server_bresp ;
assign fabric_2x3$v_to_slaves_2_bvalid =
proc$debug_module_mem_server_bvalid ;
assign fabric_2x3$v_to_slaves_2_rdata = proc$debug_module_mem_server_rdata ;
assign fabric_2x3$v_to_slaves_2_rid = proc$debug_module_mem_server_rid ;
assign fabric_2x3$v_to_slaves_2_rlast = proc$debug_module_mem_server_rlast ;
assign fabric_2x3$v_to_slaves_2_rresp = proc$debug_module_mem_server_rresp ;
assign fabric_2x3$v_to_slaves_2_rvalid =
proc$debug_module_mem_server_rvalid ;
assign fabric_2x3$v_to_slaves_2_wready =
proc$debug_module_mem_server_wready ;
assign fabric_2x3$EN_reset = 1'b0 ;
assign fabric_2x3$EN_set_verbosity = 1'b0 ;
// submodule plic
assign plic$axi4_slave_araddr = fabric_2x3$v_to_slaves_1_araddr ;
assign plic$axi4_slave_arburst = fabric_2x3$v_to_slaves_1_arburst ;
assign plic$axi4_slave_arcache = fabric_2x3$v_to_slaves_1_arcache ;
assign plic$axi4_slave_arid = fabric_2x3$v_to_slaves_1_arid ;
assign plic$axi4_slave_arlen = fabric_2x3$v_to_slaves_1_arlen ;
assign plic$axi4_slave_arlock = fabric_2x3$v_to_slaves_1_arlock ;
assign plic$axi4_slave_arprot = fabric_2x3$v_to_slaves_1_arprot ;
assign plic$axi4_slave_arqos = fabric_2x3$v_to_slaves_1_arqos ;
assign plic$axi4_slave_arregion = fabric_2x3$v_to_slaves_1_arregion ;
assign plic$axi4_slave_arsize = fabric_2x3$v_to_slaves_1_arsize ;
assign plic$axi4_slave_arvalid = fabric_2x3$v_to_slaves_1_arvalid ;
assign plic$axi4_slave_awaddr = fabric_2x3$v_to_slaves_1_awaddr ;
assign plic$axi4_slave_awburst = fabric_2x3$v_to_slaves_1_awburst ;
assign plic$axi4_slave_awcache = fabric_2x3$v_to_slaves_1_awcache ;
assign plic$axi4_slave_awid = fabric_2x3$v_to_slaves_1_awid ;
assign plic$axi4_slave_awlen = fabric_2x3$v_to_slaves_1_awlen ;
assign plic$axi4_slave_awlock = fabric_2x3$v_to_slaves_1_awlock ;
assign plic$axi4_slave_awprot = fabric_2x3$v_to_slaves_1_awprot ;
assign plic$axi4_slave_awqos = fabric_2x3$v_to_slaves_1_awqos ;
assign plic$axi4_slave_awregion = fabric_2x3$v_to_slaves_1_awregion ;
assign plic$axi4_slave_awsize = fabric_2x3$v_to_slaves_1_awsize ;
assign plic$axi4_slave_awvalid = fabric_2x3$v_to_slaves_1_awvalid ;
assign plic$axi4_slave_bready = fabric_2x3$v_to_slaves_1_bready ;
assign plic$axi4_slave_rready = fabric_2x3$v_to_slaves_1_rready ;
assign plic$axi4_slave_wdata = fabric_2x3$v_to_slaves_1_wdata ;
assign plic$axi4_slave_wlast = fabric_2x3$v_to_slaves_1_wlast ;
assign plic$axi4_slave_wstrb = fabric_2x3$v_to_slaves_1_wstrb ;
assign plic$axi4_slave_wvalid = fabric_2x3$v_to_slaves_1_wvalid ;
assign plic$set_addr_map_addr_base = soc_map$m_plic_addr_base ;
assign plic$set_addr_map_addr_lim = soc_map$m_plic_addr_lim ;
assign plic$set_verbosity_verbosity = 4'h0 ;
assign plic$v_sources_0_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_0_m_interrupt_req_set_not_clear ;
assign plic$v_sources_10_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_10_m_interrupt_req_set_not_clear ;
assign plic$v_sources_11_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_11_m_interrupt_req_set_not_clear ;
assign plic$v_sources_12_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_12_m_interrupt_req_set_not_clear ;
assign plic$v_sources_13_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_13_m_interrupt_req_set_not_clear ;
assign plic$v_sources_14_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_14_m_interrupt_req_set_not_clear ;
assign plic$v_sources_15_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_15_m_interrupt_req_set_not_clear ;
assign plic$v_sources_1_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_1_m_interrupt_req_set_not_clear ;
assign plic$v_sources_2_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_2_m_interrupt_req_set_not_clear ;
assign plic$v_sources_3_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_3_m_interrupt_req_set_not_clear ;
assign plic$v_sources_4_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_4_m_interrupt_req_set_not_clear ;
assign plic$v_sources_5_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_5_m_interrupt_req_set_not_clear ;
assign plic$v_sources_6_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_6_m_interrupt_req_set_not_clear ;
assign plic$v_sources_7_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_7_m_interrupt_req_set_not_clear ;
assign plic$v_sources_8_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_8_m_interrupt_req_set_not_clear ;
assign plic$v_sources_9_m_interrupt_req_set_not_clear =
core_external_interrupt_sources_9_m_interrupt_req_set_not_clear ;
assign plic$EN_set_verbosity = 1'b0 ;
assign plic$EN_show_PLIC_state = 1'b0 ;
assign plic$EN_server_reset_request_put = 1'b0 ;
assign plic$EN_server_reset_response_get = 1'b0 ;
assign plic$EN_set_addr_map = EN_start ;
// submodule proc
assign proc$debug_module_mem_server_araddr =
fabric_2x3$v_to_slaves_2_araddr ;
assign proc$debug_module_mem_server_arburst =
fabric_2x3$v_to_slaves_2_arburst ;
assign proc$debug_module_mem_server_arcache =
fabric_2x3$v_to_slaves_2_arcache ;
assign proc$debug_module_mem_server_arid = fabric_2x3$v_to_slaves_2_arid ;
assign proc$debug_module_mem_server_arlen = fabric_2x3$v_to_slaves_2_arlen ;
assign proc$debug_module_mem_server_arlock =
fabric_2x3$v_to_slaves_2_arlock ;
assign proc$debug_module_mem_server_arprot =
fabric_2x3$v_to_slaves_2_arprot ;
assign proc$debug_module_mem_server_arqos = fabric_2x3$v_to_slaves_2_arqos ;
assign proc$debug_module_mem_server_arregion =
fabric_2x3$v_to_slaves_2_arregion ;
assign proc$debug_module_mem_server_arsize =
fabric_2x3$v_to_slaves_2_arsize ;
assign proc$debug_module_mem_server_arvalid =
fabric_2x3$v_to_slaves_2_arvalid ;
assign proc$debug_module_mem_server_awaddr =
fabric_2x3$v_to_slaves_2_awaddr ;
assign proc$debug_module_mem_server_awburst =
fabric_2x3$v_to_slaves_2_awburst ;
assign proc$debug_module_mem_server_awcache =
fabric_2x3$v_to_slaves_2_awcache ;
assign proc$debug_module_mem_server_awid = fabric_2x3$v_to_slaves_2_awid ;
assign proc$debug_module_mem_server_awlen = fabric_2x3$v_to_slaves_2_awlen ;
assign proc$debug_module_mem_server_awlock =
fabric_2x3$v_to_slaves_2_awlock ;
assign proc$debug_module_mem_server_awprot =
fabric_2x3$v_to_slaves_2_awprot ;
assign proc$debug_module_mem_server_awqos = fabric_2x3$v_to_slaves_2_awqos ;
assign proc$debug_module_mem_server_awregion =
fabric_2x3$v_to_slaves_2_awregion ;
assign proc$debug_module_mem_server_awsize =
fabric_2x3$v_to_slaves_2_awsize ;
assign proc$debug_module_mem_server_awvalid =
fabric_2x3$v_to_slaves_2_awvalid ;
assign proc$debug_module_mem_server_bready =
fabric_2x3$v_to_slaves_2_bready ;
assign proc$debug_module_mem_server_rready =
fabric_2x3$v_to_slaves_2_rready ;
assign proc$debug_module_mem_server_wdata = fabric_2x3$v_to_slaves_2_wdata ;
assign proc$debug_module_mem_server_wlast = fabric_2x3$v_to_slaves_2_wlast ;
assign proc$debug_module_mem_server_wstrb = fabric_2x3$v_to_slaves_2_wstrb ;
assign proc$debug_module_mem_server_wvalid =
fabric_2x3$v_to_slaves_2_wvalid ;
assign proc$hart0_csr_mem_server_request_put =
dm_csr_tap$client_request_get ;
assign proc$hart0_fpr_mem_server_request_put = 70'h0 ;
assign proc$hart0_gpr_mem_server_request_put =
dm_gpr_tap_ifc$client_request_get ;
assign proc$hart0_put_other_req_put = debug_module$hart0_get_other_req_get ;
assign proc$hart0_run_halt_server_request_put =
debug_module$hart0_client_run_halt_request_get ;
assign proc$m_external_interrupt_req_set_not_clear =
plic$v_targets_0_m_eip ;
assign proc$master0_arready = cpu_imem_master_arready ;
assign proc$master0_awready = cpu_imem_master_awready ;
assign proc$master0_bid = cpu_imem_master_bid ;
assign proc$master0_bresp = cpu_imem_master_bresp ;
assign proc$master0_bvalid = cpu_imem_master_bvalid ;
assign proc$master0_rdata = cpu_imem_master_rdata ;
assign proc$master0_rid = cpu_imem_master_rid ;
assign proc$master0_rlast = cpu_imem_master_rlast ;
assign proc$master0_rresp = cpu_imem_master_rresp ;
assign proc$master0_rvalid = cpu_imem_master_rvalid ;
assign proc$master0_wready = cpu_imem_master_wready ;
assign proc$master1_arready = fabric_2x3$v_from_masters_0_arready ;
assign proc$master1_awready = fabric_2x3$v_from_masters_0_awready ;
assign proc$master1_bid = fabric_2x3$v_from_masters_0_bid ;
assign proc$master1_bresp = fabric_2x3$v_from_masters_0_bresp ;
assign proc$master1_bvalid = fabric_2x3$v_from_masters_0_bvalid ;
assign proc$master1_rdata = fabric_2x3$v_from_masters_0_rdata ;
assign proc$master1_rid = fabric_2x3$v_from_masters_0_rid ;
assign proc$master1_rlast = fabric_2x3$v_from_masters_0_rlast ;
assign proc$master1_rresp = fabric_2x3$v_from_masters_0_rresp ;
assign proc$master1_rvalid = fabric_2x3$v_from_masters_0_rvalid ;
assign proc$master1_wready = fabric_2x3$v_from_masters_0_wready ;
assign proc$non_maskable_interrupt_req_set_not_clear = 1'd0 ;
assign proc$s_external_interrupt_req_set_not_clear =
plic$v_targets_1_m_eip ;
assign proc$set_verbosity_verbosity = set_verbosity_verbosity ;
assign proc$start_fromhostAddr =
MUX_proc$start_1__SEL_1 ?
rg_fromhost_addr :
start_fromhost_addr ;
assign proc$start_startpc = 64'h0000000070000000 ;
assign proc$start_tohostAddr =
MUX_proc$start_1__SEL_1 ? rg_tohost_addr : start_tohost_addr ;
assign proc$EN_start =
WILL_FIRE_RL_rl_dm_hart0_reset_wait &&
rg_hart0_reset_delay == 8'd1 ||
EN_start ;
assign proc$EN_set_verbosity = EN_set_verbosity ;
assign proc$EN_hart0_run_halt_server_request_put =
CAN_FIRE_RL_ClientServerRequest ;
assign proc$EN_hart0_run_halt_server_response_get =
CAN_FIRE_RL_ClientServerResponse ;
assign proc$EN_hart0_gpr_mem_server_request_put =
CAN_FIRE_RL_ClientServerRequest_2 ;
assign proc$EN_hart0_gpr_mem_server_response_get =
CAN_FIRE_RL_ClientServerResponse_2 ;
assign proc$EN_hart0_fpr_mem_server_request_put = 1'b0 ;
assign proc$EN_hart0_fpr_mem_server_response_get = 1'b0 ;
assign proc$EN_hart0_csr_mem_server_request_put =
CAN_FIRE_RL_ClientServerRequest_4 ;
assign proc$EN_hart0_csr_mem_server_response_get =
CAN_FIRE_RL_ClientServerResponse_4 ;
assign proc$EN_hart0_put_other_req_put =
debug_module$RDY_hart0_get_other_req_get ;
assign proc$EN_v_to_TV_0_get = CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign proc$EN_v_to_TV_1_get = CAN_FIRE_RL_mkConnectionGetPut_3 ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule tv_encode
always@(WILL_FIRE_RL_rl_merge_dm_mem_trace_data or
dm_mem_tap$trace_data_out_get or
WILL_FIRE_RL_rl_merge_dm_gpr_trace_data or
dm_gpr_tap_ifc$trace_data_out_get or
WILL_FIRE_RL_rl_merge_dm_csr_trace_data or
dm_csr_tap$trace_data_out_get)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_merge_dm_mem_trace_data:
tv_encode$dm_in_put = dm_mem_tap$trace_data_out_get;
WILL_FIRE_RL_rl_merge_dm_gpr_trace_data:
tv_encode$dm_in_put = dm_gpr_tap_ifc$trace_data_out_get;
WILL_FIRE_RL_rl_merge_dm_csr_trace_data:
tv_encode$dm_in_put = dm_csr_tap$trace_data_out_get;
default: tv_encode$dm_in_put =
427'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign tv_encode$v_cpu_in_0_put = v_td2_to_td_0$out_get ;
assign tv_encode$v_cpu_in_1_put = v_td2_to_td_1$out_get ;
assign tv_encode$EN_v_cpu_in_0_put = CAN_FIRE_RL_mkConnectionGetPut_2 ;
assign tv_encode$EN_v_cpu_in_1_put = CAN_FIRE_RL_mkConnectionGetPut_4 ;
assign tv_encode$EN_dm_in_put =
WILL_FIRE_RL_rl_merge_dm_mem_trace_data ||
WILL_FIRE_RL_rl_merge_dm_gpr_trace_data ||
WILL_FIRE_RL_rl_merge_dm_csr_trace_data ;
assign tv_encode$EN_out_get = EN_tv_verifier_info_get_get ;
// submodule v_td2_to_td_0
assign v_td2_to_td_0$in_put =
{ proc$v_to_TV_0_get[861:797],
proc$v_to_TV_0_get[797] ?
proc$v_to_TV_0_get[796:721] :
76'hAAAAAAAAAAAAAAAAAAA,
proc$v_to_TV_0_get[720:619],
proc$v_to_TV_0_get[619] ? proc$v_to_TV_0_get[618:613] : 6'h2A,
proc$v_to_TV_0_get[612:476],
proc$v_to_TV_0_get[476] ?
CASE_procv_to_TV_0_get_BITS_475_TO_464_1_proc_ETC__q1 :
12'hAAA,
proc$v_to_TV_0_get[463],
proc$v_to_TV_0_get[463] ?
{ proc$v_to_TV_0_get[462],
proc$v_to_TV_0_get[462] ?
CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q2 :
CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q3 } :
5'h0A,
proc$v_to_TV_0_get[457:394],
CASE_procv_to_TV_0_get_BITS_393_TO_392_0_proc_ETC__q4,
proc$v_to_TV_0_get[391:0] } ;
assign v_td2_to_td_0$EN_in_put = CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign v_td2_to_td_0$EN_out_get = CAN_FIRE_RL_mkConnectionGetPut_2 ;
// submodule v_td2_to_td_1
assign v_td2_to_td_1$in_put =
{ proc$v_to_TV_1_get[861:797],
proc$v_to_TV_1_get[797] ?
proc$v_to_TV_1_get[796:721] :
76'hAAAAAAAAAAAAAAAAAAA,
proc$v_to_TV_1_get[720:619],
proc$v_to_TV_1_get[619] ? proc$v_to_TV_1_get[618:613] : 6'h2A,
proc$v_to_TV_1_get[612:476],
proc$v_to_TV_1_get[476] ?
CASE_procv_to_TV_1_get_BITS_475_TO_464_1_proc_ETC__q5 :
12'hAAA,
proc$v_to_TV_1_get[463],
proc$v_to_TV_1_get[463] ?
{ proc$v_to_TV_1_get[462],
proc$v_to_TV_1_get[462] ?
CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q6 :
CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q7 } :
5'h0A,
proc$v_to_TV_1_get[457:394],
CASE_procv_to_TV_1_get_BITS_393_TO_392_0_proc_ETC__q8,
proc$v_to_TV_1_get[391:0] } ;
assign v_td2_to_td_1$EN_in_put = CAN_FIRE_RL_mkConnectionGetPut_3 ;
assign v_td2_to_td_1$EN_out_get = CAN_FIRE_RL_mkConnectionGetPut_4 ;
// remaining internal signals
always@(proc$v_to_TV_0_get)
begin
case (proc$v_to_TV_0_get[475:464])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_procv_to_TV_0_get_BITS_475_TO_464_1_proc_ETC__q1 =
proc$v_to_TV_0_get[475:464];
default: CASE_procv_to_TV_0_get_BITS_475_TO_464_1_proc_ETC__q1 =
12'd2303;
endcase
end
always@(proc$v_to_TV_0_get)
begin
case (proc$v_to_TV_0_get[461:458])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q2 =
proc$v_to_TV_0_get[461:458];
default: CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q2 = 4'd15;
endcase
end
always@(proc$v_to_TV_0_get)
begin
case (proc$v_to_TV_0_get[461:458])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q3 =
proc$v_to_TV_0_get[461:458];
default: CASE_procv_to_TV_0_get_BITS_461_TO_458_0_proc_ETC__q3 = 4'd15;
endcase
end
always@(proc$v_to_TV_0_get)
begin
case (proc$v_to_TV_0_get[393:392])
2'd0, 2'd1:
CASE_procv_to_TV_0_get_BITS_393_TO_392_0_proc_ETC__q4 =
proc$v_to_TV_0_get[393:392];
default: CASE_procv_to_TV_0_get_BITS_393_TO_392_0_proc_ETC__q4 = 2'd2;
endcase
end
always@(proc$v_to_TV_1_get)
begin
case (proc$v_to_TV_1_get[475:464])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_procv_to_TV_1_get_BITS_475_TO_464_1_proc_ETC__q5 =
proc$v_to_TV_1_get[475:464];
default: CASE_procv_to_TV_1_get_BITS_475_TO_464_1_proc_ETC__q5 =
12'd2303;
endcase
end
always@(proc$v_to_TV_1_get)
begin
case (proc$v_to_TV_1_get[461:458])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q6 =
proc$v_to_TV_1_get[461:458];
default: CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q6 = 4'd15;
endcase
end
always@(proc$v_to_TV_1_get)
begin
case (proc$v_to_TV_1_get[461:458])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q7 =
proc$v_to_TV_1_get[461:458];
default: CASE_procv_to_TV_1_get_BITS_461_TO_458_0_proc_ETC__q7 = 4'd15;
endcase
end
always@(proc$v_to_TV_1_get)
begin
case (proc$v_to_TV_1_get[393:392])
2'd0, 2'd1:
CASE_procv_to_TV_1_get_BITS_393_TO_392_0_proc_ETC__q8 =
proc$v_to_TV_1_get[393:392];
default: CASE_procv_to_TV_1_get_BITS_393_TO_392_0_proc_ETC__q8 = 2'd2;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'd0;
end
else
begin
if (rg_fromhost_addr$EN)
rg_fromhost_addr <= `BSV_ASSIGNMENT_DELAY rg_fromhost_addr$D_IN;
if (rg_hart0_reset_delay$EN)
rg_hart0_reset_delay <= `BSV_ASSIGNMENT_DELAY
rg_hart0_reset_delay$D_IN;
if (rg_tohost_addr$EN)
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_fromhost_addr = 64'hAAAAAAAAAAAAAAAA;
rg_hart0_reset_delay = 8'hAA;
rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_dm_hart0_reset)
begin
v__h5047 = $stime;
#0;
end
v__h5041 = v__h5047 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_dm_hart0_reset)
$display("%0d: %m.rl_dm_hart0_reset: asserting hart0 reset for %0d cycles",
v__h5041,
$signed(32'd10));
if (RST_N != `BSV_RESET_VALUE)
if (hart0_reset$RST_OUT != `BSV_RESET_VALUE)
if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_dm_hart0_reset_wait &&
rg_hart0_reset_delay == 8'd1)
begin
v__h5190 = $stime;
#0;
end
v__h5184 = v__h5190 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (hart0_reset$RST_OUT != `BSV_RESET_VALUE)
if (RST_N_dm_power_on_reset != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_dm_hart0_reset_wait &&
rg_hart0_reset_delay == 8'd1)
$display("%0d: %m.rl_dm_hart0_reset_wait: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h",
v__h5184,
64'h0000000070000000,
rg_tohost_addr,
rg_fromhost_addr);
if (RST_N != `BSV_RESET_VALUE)
if (hart0_reset$RST_OUT != `BSV_RESET_VALUE)
if (EN_start)
begin
v__h15930 = $stime;
#0;
end
v__h15924 = v__h15930 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (hart0_reset$RST_OUT != `BSV_RESET_VALUE)
if (EN_start)
$display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)",
v__h15924,
64'h0000000070000000,
start_tohost_addr,
start_fromhost_addr);
end
// synopsys translate_on
endmodule // mkCoreW
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