94 lines
2.5 KiB
Verilog
94 lines
2.5 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// brAddrCalc O 64
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// brAddrCalc_pc I 64
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// brAddrCalc_val I 64
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// brAddrCalc_iType I 5
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// brAddrCalc_imm I 64
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// brAddrCalc_taken I 1
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// brAddrCalc_orig_inst I 32
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//
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// Combinational paths from inputs to outputs:
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// (brAddrCalc_pc,
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// brAddrCalc_val,
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// brAddrCalc_iType,
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// brAddrCalc_imm,
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// brAddrCalc_taken,
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// brAddrCalc_orig_inst) -> brAddrCalc
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_brAddrCalc(brAddrCalc_pc,
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brAddrCalc_val,
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brAddrCalc_iType,
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brAddrCalc_imm,
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brAddrCalc_taken,
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brAddrCalc_orig_inst,
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brAddrCalc);
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// value method brAddrCalc
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input [63 : 0] brAddrCalc_pc;
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input [63 : 0] brAddrCalc_val;
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input [4 : 0] brAddrCalc_iType;
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input [63 : 0] brAddrCalc_imm;
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input brAddrCalc_taken;
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input [31 : 0] brAddrCalc_orig_inst;
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output [63 : 0] brAddrCalc;
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// signals for module outputs
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reg [63 : 0] brAddrCalc;
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// remaining internal signals
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wire [63 : 0] brAddrCalc_pc_PLUS_brAddrCalc_imm___d2,
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brAddrCalc_val_PLUS_brAddrCalc_imm__q1,
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fallthrough_incr__h28,
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pcPlusN__h29;
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// value method brAddrCalc
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always@(brAddrCalc_iType or
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pcPlusN__h29 or
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brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 or
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brAddrCalc_val_PLUS_brAddrCalc_imm__q1 or brAddrCalc_taken)
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begin
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case (brAddrCalc_iType)
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5'd8: brAddrCalc = brAddrCalc_pc_PLUS_brAddrCalc_imm___d2;
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5'd9:
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brAddrCalc = { brAddrCalc_val_PLUS_brAddrCalc_imm__q1[63:1], 1'b0 };
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5'd10:
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brAddrCalc =
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brAddrCalc_taken ?
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brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 :
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pcPlusN__h29;
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default: brAddrCalc = pcPlusN__h29;
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endcase
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end
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// remaining internal signals
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assign brAddrCalc_pc_PLUS_brAddrCalc_imm___d2 =
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brAddrCalc_pc + brAddrCalc_imm ;
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assign brAddrCalc_val_PLUS_brAddrCalc_imm__q1 =
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brAddrCalc_val + brAddrCalc_imm ;
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assign fallthrough_incr__h28 =
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(brAddrCalc_orig_inst[1:0] == 2'b11) ? 64'd4 : 64'd2 ;
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assign pcPlusN__h29 = brAddrCalc_pc + fallthrough_incr__h28 ;
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endmodule // module_brAddrCalc
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