867 lines
38 KiB
Verilog
867 lines
38 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Wed Jun 17 12:21:08 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// checkForException O 14
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// checkForException_dInst I 144
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// checkForException_regs I 27
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// checkForException_csrState I 15
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// checkForException_pcc I 129
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// checkForException_fourByteInst I 1
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//
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// Combinational paths from inputs to outputs:
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// (checkForException_dInst,
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// checkForException_regs,
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// checkForException_csrState,
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// checkForException_pcc,
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// checkForException_fourByteInst) -> checkForException
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_checkForException(checkForException_dInst,
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checkForException_regs,
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checkForException_csrState,
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checkForException_pcc,
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checkForException_fourByteInst,
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checkForException);
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// value method checkForException
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input [143 : 0] checkForException_dInst;
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input [26 : 0] checkForException_regs;
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input [14 : 0] checkForException_csrState;
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input [128 : 0] checkForException_pcc;
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input checkForException_fourByteInst;
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output [13 : 0] checkForException;
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// signals for module outputs
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wire [13 : 0] checkForException;
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// remaining internal signals
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reg [5 : 0] CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4;
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reg [4 : 0] CASE_checkForException_dInst_BITS_37_TO_33_0_c_ETC__q2;
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reg [2 : 0] CASE_checkForException_csrState_BITS_14_TO_12__ETC__q3;
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reg CASE_checkForException_dInst_BITS_143_TO_139_2_ETC__q5,
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IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d566;
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wire [63 : 0] memCap_address__h637, x__h443, x__h997;
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wire [31 : 0] imm__h1512;
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wire [18 : 0] INV_checkForException_pcc_BITS_108_TO_90__q1;
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wire [13 : 0] b_base__h929,
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cr_addrBits__h111,
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cr_addrBits__h561,
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x__h960,
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y__h1054;
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wire [12 : 0] IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d719;
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wire [11 : 0] IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18,
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b_top__h928,
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csr__h1509,
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inc__h652;
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wire [5 : 0] x__h1035;
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wire [4 : 0] IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d702,
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d704,
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d705,
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rs1__h1511;
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wire [2 : 0] IF_NOT_checkForException_dInst_BITS_112_TO_110_ETC___d545,
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repBound__h535,
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tb__h532,
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tmp_expBotHalf__h991,
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tmp_expTopHalf__h989;
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wire [1 : 0] carry_out__h594,
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impliedTopBits__h596,
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len_correction__h595,
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x__h617;
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wire IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d51,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d573,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d577,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d69,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d695,
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d80,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d40,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d42,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d47,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d48,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d61,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d62,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d65,
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d66,
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IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d681,
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IF_checkForException_dInst_BIT_38_70_THEN_chec_ETC___d562,
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NOT_checkForException_dInst_BITS_138_TO_136_02_ETC___d594,
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NOT_checkForException_dInst_BITS_138_TO_136_02_ETC___d678,
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NOT_checkForException_dInst_BIT_51_22_68_OR_NO_ETC___d417,
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NOT_checkForException_pcc_BIT_122_8_9_AND_NOT__ETC___d468,
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d266,
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d493,
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d515,
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checkForException_dInst_BITS_138_TO_136_02_EQ__ETC___d264,
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checkForException_dInst_BITS_138_TO_136_02_EQ__ETC___d406;
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// value method checkForException
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assign checkForException =
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{ IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d80 ||
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checkForException_dInst[143:139] == 5'd22 ||
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checkForException_dInst[143:139] == 5'd23 ||
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IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d566,
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d719 } ;
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// remaining internal signals
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assign IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d702 =
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(IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d573 &&
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d577 &&
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!checkForException_pcc[113]) ?
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5'd17 :
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((IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d573 &&
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d577 &&
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checkForException_pcc[113] &&
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INV_checkForException_pcc_BITS_108_TO_90__q1[18:1] ==
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18'd262143 &&
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checkForException_pcc[128]) ?
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5'd24 :
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5'd27) ;
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assign IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d704 =
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d695 ?
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5'd2 :
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((IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d573 &&
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d577 &&
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checkForException_pcc[113] &&
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INV_checkForException_pcc_BITS_108_TO_90__q1[18:1] !=
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18'd262143) ?
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5'd3 :
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d702) ;
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assign IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d705 =
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(IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d80 &&
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(IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d51 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d69)) ?
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5'd1 :
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d704 ;
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assign IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d719 =
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(IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d80 ||
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checkForException_dInst[143:139] != 5'd22 &&
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checkForException_dInst[143:139] != 5'd23 &&
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CASE_checkForException_dInst_BITS_143_TO_139_2_ETC__q5) ?
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{ 8'd32,
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IF_IF_IF_INV_checkForException_pcc_BITS_108_TO_ETC___d705 } :
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{ 8'd106,
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((checkForException_dInst[143:139] == 5'd22) ?
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checkForException_csrState[10:9] != 2'd0 &&
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checkForException_csrState[10:9] != 2'd1 &&
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checkForException_csrState[10:9] != 2'd3 :
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checkForException_dInst[143:139] != 5'd23) ?
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5'd2 :
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((checkForException_dInst[143:139] == 5'd23) ?
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5'd3 :
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((checkForException_dInst[143:139] == 5'd22 &&
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checkForException_csrState[10:9] == 2'd0) ?
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5'd8 :
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((checkForException_dInst[143:139] == 5'd22 &&
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checkForException_csrState[10:9] == 2'd1) ?
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5'd9 :
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((checkForException_dInst[143:139] == 5'd22 &&
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checkForException_csrState[10:9] == 2'd3) ?
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5'd11 :
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5'd28)))) } ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d51 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d40 ?
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d42 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29) ||
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d47 ?
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d48 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39) ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d573 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d40 ?
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d42 :
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29) &&
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d47 ?
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d48 :
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39) ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d577 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d61 ?
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d62 :
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29) &&
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d65 ?
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d66 :
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60) ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d69 =
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d61 ?
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d62 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29) ||
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(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d65 ?
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d66 :
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!IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60) ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d695 =
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(IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d51 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d69 ||
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!checkForException_pcc[128]) &&
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d573 &&
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d577 &&
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checkForException_pcc[113] &&
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INV_checkForException_pcc_BITS_108_TO_90__q1[18:1] ==
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18'd262143 ;
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assign IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d80 =
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d51 ||
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IF_IF_INV_checkForException_pcc_BITS_108_TO_90_ETC___d69 ||
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!checkForException_pcc[113] ||
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INV_checkForException_pcc_BITS_108_TO_90__q1[18:1] !=
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18'd262143 ||
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!checkForException_pcc[128] ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18 =
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INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
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{ checkForException_pcc[89:81], 3'd0 } :
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b_top__h928 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 =
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tb__h532 < repBound__h535 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39 =
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cr_addrBits__h111[13:11] < repBound__h535 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d40 =
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d42 =
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cr_addrBits__h111 <= y__h1054 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46 =
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x__h960[13:11] < repBound__h535 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d47 =
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d39 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d48 =
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cr_addrBits__h111 < x__h960 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60 =
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cr_addrBits__h561[13:11] < repBound__h535 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d61 =
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d29 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d62 =
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cr_addrBits__h561 <= y__h1054 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d65 =
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d46 ==
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IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d60 ;
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assign IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d66 =
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cr_addrBits__h561 < x__h960 ;
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assign IF_NOT_checkForException_dInst_BITS_112_TO_110_ETC___d545 =
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(checkForException_dInst[112:110] != 3'd0 &&
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checkForException_dInst[112:110] != 3'd1 &&
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checkForException_dInst[112:110] != 3'd2 &&
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checkForException_dInst[112:110] != 3'd3 &&
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checkForException_dInst[112:110] != 3'd4) ?
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CASE_checkForException_csrState_BITS_14_TO_12__ETC__q3 :
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checkForException_dInst[112:110] ;
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assign IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d681 =
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(checkForException_dInst[143:139] == 5'd17) ?
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NOT_checkForException_dInst_BITS_138_TO_136_02_ETC___d678 &&
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!checkForException_pcc[122] &&
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NOT_checkForException_dInst_BIT_51_22_68_OR_NO_ETC___d417 :
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checkForException_dInst[38] &&
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!checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d493 &&
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(checkForException_dInst[37:33] == 5'd0 ||
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checkForException_dInst[37:33] == 5'd1 ||
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checkForException_dInst[37:33] == 5'd12 ||
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checkForException_dInst[37:33] == 5'd13 ||
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checkForException_dInst[37:33] == 5'd14 ||
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checkForException_dInst[37:33] == 5'd15 ||
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checkForException_dInst[37:33] == 5'd28 ||
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checkForException_dInst[37:33] == 5'd29 ||
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checkForException_dInst[37:33] == 5'd30 ||
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checkForException_dInst[37:33] == 5'd31) ;
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assign IF_checkForException_dInst_BIT_38_70_THEN_chec_ETC___d562 =
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checkForException_dInst[38] ?
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checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d515 :
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checkForException_dInst[143:139] == 5'd16 &&
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(checkForException_dInst[138:136] != 3'd4 ||
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IF_NOT_checkForException_dInst_BITS_112_TO_110_ETC___d545 !=
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3'd0 &&
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IF_NOT_checkForException_dInst_BITS_112_TO_110_ETC___d545 !=
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3'd1 &&
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IF_NOT_checkForException_dInst_BITS_112_TO_110_ETC___d545 !=
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3'd2 &&
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IF_NOT_checkForException_dInst_BITS_112_TO_110_ETC___d545 !=
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3'd3 &&
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IF_NOT_checkForException_dInst_BITS_112_TO_110_ETC___d545 !=
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3'd4) ;
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assign INV_checkForException_pcc_BITS_108_TO_90__q1 =
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~checkForException_pcc[108:90] ;
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assign NOT_checkForException_dInst_BITS_138_TO_136_02_ETC___d594 =
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(checkForException_dInst[138:136] != 3'd0 ||
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checkForException_dInst[113:109] != 5'd15) &&
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rs1__h1511 == 5'd0 &&
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imm__h1512 == 32'd0 ||
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csr__h1509[11:10] != 2'b11 ;
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assign NOT_checkForException_dInst_BITS_138_TO_136_02_ETC___d678 =
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NOT_checkForException_dInst_BITS_138_TO_136_02_ETC___d594 &&
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!checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d266 &&
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checkForException_dInst[51] &&
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(checkForException_dInst[50:39] == 12'd3072 ||
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checkForException_dInst[50:39] == 12'd3073 ||
|
|
checkForException_dInst[50:39] == 12'd3074 ||
|
|
checkForException_dInst[50:39] == 12'd2048 ||
|
|
checkForException_dInst[50:39] == 12'd2049 ||
|
|
checkForException_dInst[50:39] == 12'd256 ||
|
|
checkForException_dInst[50:39] == 12'd260 ||
|
|
checkForException_dInst[50:39] == 12'd261 ||
|
|
checkForException_dInst[50:39] == 12'd262 ||
|
|
checkForException_dInst[50:39] == 12'd320 ||
|
|
checkForException_dInst[50:39] == 12'd321 ||
|
|
checkForException_dInst[50:39] == 12'd322 ||
|
|
checkForException_dInst[50:39] == 12'd323 ||
|
|
checkForException_dInst[50:39] == 12'd324 ||
|
|
checkForException_dInst[50:39] == 12'd384 ||
|
|
checkForException_dInst[50:39] == 12'd2496 ||
|
|
checkForException_dInst[50:39] == 12'd768 ||
|
|
checkForException_dInst[50:39] == 12'd769 ||
|
|
checkForException_dInst[50:39] == 12'd770 ||
|
|
checkForException_dInst[50:39] == 12'd771 ||
|
|
checkForException_dInst[50:39] == 12'd772 ||
|
|
checkForException_dInst[50:39] == 12'd773 ||
|
|
checkForException_dInst[50:39] == 12'd774 ||
|
|
checkForException_dInst[50:39] == 12'd832 ||
|
|
checkForException_dInst[50:39] == 12'd833 ||
|
|
checkForException_dInst[50:39] == 12'd834 ||
|
|
checkForException_dInst[50:39] == 12'd835 ||
|
|
checkForException_dInst[50:39] == 12'd836 ||
|
|
checkForException_dInst[50:39] == 12'd2816 ||
|
|
checkForException_dInst[50:39] == 12'd2818 ||
|
|
checkForException_dInst[50:39] == 12'd3857 ||
|
|
checkForException_dInst[50:39] == 12'd3858 ||
|
|
checkForException_dInst[50:39] == 12'd3859 ||
|
|
checkForException_dInst[50:39] == 12'd3860 ||
|
|
checkForException_dInst[50:39] == 12'd3008 ||
|
|
checkForException_dInst[50:39] == 12'd1952 ||
|
|
checkForException_dInst[50:39] == 12'd1953 ||
|
|
checkForException_dInst[50:39] == 12'd1954 ||
|
|
checkForException_dInst[50:39] == 12'd1955 ||
|
|
checkForException_dInst[50:39] == 12'd1968 ||
|
|
checkForException_dInst[50:39] == 12'd1969 ||
|
|
checkForException_dInst[50:39] == 12'd1970 ||
|
|
checkForException_dInst[50:39] == 12'd1971) ;
|
|
assign NOT_checkForException_dInst_BIT_51_22_68_OR_NO_ETC___d417 =
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd2) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3072 ||
|
|
(checkForException_dInst[138:136] != 3'd0 ||
|
|
checkForException_dInst[113:109] != 5'd15) &&
|
|
rs1__h1511 == 5'd0 &&
|
|
imm__h1512 == 32'd0) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3074 ||
|
|
(checkForException_dInst[138:136] != 3'd0 ||
|
|
checkForException_dInst[113:109] != 5'd15) &&
|
|
rs1__h1511 == 5'd0 &&
|
|
imm__h1512 == 32'd0) ;
|
|
assign NOT_checkForException_pcc_BIT_122_8_9_AND_NOT__ETC___d468 =
|
|
!checkForException_pcc[122] &&
|
|
NOT_checkForException_dInst_BIT_51_22_68_OR_NO_ETC___d417 ||
|
|
checkForException_csrState[10:9] == 2'd1 &&
|
|
checkForException_csrState[8] &&
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 == 6'd17 ;
|
|
assign b_base__h929 =
|
|
{ checkForException_pcc[77:67],
|
|
~checkForException_pcc[66],
|
|
checkForException_pcc[65:64] } ;
|
|
assign b_top__h928 =
|
|
{ checkForException_pcc[89:81],
|
|
~checkForException_pcc[80:79],
|
|
checkForException_pcc[78] } ;
|
|
assign carry_out__h594 =
|
|
(IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18 <
|
|
x__h960[11:0]) ?
|
|
2'b01 :
|
|
2'b0 ;
|
|
assign checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d266 =
|
|
checkForException_csrState[10:9] < csr__h1509[9:8] ;
|
|
assign checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d493 =
|
|
checkForException_csrState[10:9] <
|
|
CASE_checkForException_dInst_BITS_37_TO_33_0_c_ETC__q2[4:3] ;
|
|
assign checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d515 =
|
|
checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d493 ||
|
|
checkForException_dInst[37:33] != 5'd0 &&
|
|
checkForException_dInst[37:33] != 5'd1 &&
|
|
checkForException_dInst[37:33] != 5'd12 &&
|
|
checkForException_dInst[37:33] != 5'd13 &&
|
|
checkForException_dInst[37:33] != 5'd14 &&
|
|
checkForException_dInst[37:33] != 5'd15 &&
|
|
checkForException_dInst[37:33] != 5'd28 &&
|
|
checkForException_dInst[37:33] != 5'd29 &&
|
|
checkForException_dInst[37:33] != 5'd30 &&
|
|
checkForException_dInst[37:33] != 5'd31 ||
|
|
!checkForException_pcc[122] &&
|
|
checkForException_dInst[37:33] != 5'd1 ;
|
|
assign checkForException_dInst_BITS_138_TO_136_02_EQ__ETC___d264 =
|
|
(checkForException_dInst[138:136] == 3'd0 &&
|
|
checkForException_dInst[113:109] == 5'd15 ||
|
|
rs1__h1511 != 5'd0 ||
|
|
imm__h1512 != 32'd0) &&
|
|
csr__h1509[11:10] == 2'b11 ;
|
|
assign checkForException_dInst_BITS_138_TO_136_02_EQ__ETC___d406 =
|
|
checkForException_dInst_BITS_138_TO_136_02_EQ__ETC___d264 ||
|
|
checkForException_csrState_BITS_10_TO_9_5_ULT__ETC___d266 ||
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd2) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3072) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3073) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3074) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd2048) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd2049) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd256) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd260) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd261) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd262) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd320) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd321) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd322) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd323) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd324) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd384) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd2496) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd768) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd769) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd770) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd771) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd772) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd773) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd774) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd832) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd833) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd834) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd835) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd836) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd2816) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd2818) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3857) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3858) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3859) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3860) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd3008) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1952) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1953) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1954) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1955) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1968) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1969) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1970) &&
|
|
(!checkForException_dInst[51] ||
|
|
checkForException_dInst[50:39] != 12'd1971) ;
|
|
assign cr_addrBits__h111 =
|
|
INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
|
|
x__h443[13:0] :
|
|
checkForException_pcc[13:0] ;
|
|
assign cr_addrBits__h561 =
|
|
INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
|
|
x__h997[13:0] :
|
|
memCap_address__h637[13:0] ;
|
|
assign csr__h1509 =
|
|
(checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] == 12'd1) ?
|
|
12'd1 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] == 12'd2) ?
|
|
12'd2 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] == 12'd3) ?
|
|
12'd3 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] == 12'd3072) ?
|
|
12'd3072 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] == 12'd3073) ?
|
|
12'd3073 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] == 12'd3074) ?
|
|
12'd3074 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] == 12'd2048) ?
|
|
12'd2048 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd2049) ?
|
|
12'd2049 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd256) ?
|
|
12'd256 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd260) ?
|
|
12'd260 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd261) ?
|
|
12'd261 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd262) ?
|
|
12'd262 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd320) ?
|
|
12'd320 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd321) ?
|
|
12'd321 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd322) ?
|
|
12'd322 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd323) ?
|
|
12'd323 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd324) ?
|
|
12'd324 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd384) ?
|
|
12'd384 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd2496) ?
|
|
12'd2496 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd768) ?
|
|
12'd768 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd769) ?
|
|
12'd769 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd770) ?
|
|
12'd770 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd771) ?
|
|
12'd771 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd772) ?
|
|
12'd772 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd773) ?
|
|
12'd773 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd774) ?
|
|
12'd774 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd832) ?
|
|
12'd832 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd833) ?
|
|
12'd833 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd834) ?
|
|
12'd834 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd835) ?
|
|
12'd835 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd836) ?
|
|
12'd836 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd2816) ?
|
|
12'd2816 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd2818) ?
|
|
12'd2818 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd3857) ?
|
|
12'd3857 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd3858) ?
|
|
12'd3858 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd3859) ?
|
|
12'd3859 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd3860) ?
|
|
12'd3860 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd3008) ?
|
|
12'd3008 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1952) ?
|
|
12'd1952 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1953) ?
|
|
12'd1953 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1954) ?
|
|
12'd1954 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1955) ?
|
|
12'd1955 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1968) ?
|
|
12'd1968 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1969) ?
|
|
12'd1969 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1970) ?
|
|
12'd1970 :
|
|
((checkForException_dInst[51] &&
|
|
checkForException_dInst[50:39] ==
|
|
12'd1971) ?
|
|
12'd1971 :
|
|
12'd2303))))))))))))))))))))))))))))))))))))))))))))) ;
|
|
assign imm__h1512 =
|
|
checkForException_dInst[32] ?
|
|
checkForException_dInst[31:0] :
|
|
32'd0 ;
|
|
assign impliedTopBits__h596 = x__h617 + len_correction__h595 ;
|
|
assign inc__h652 = checkForException_fourByteInst ? 12'd4 : 12'd2 ;
|
|
assign len_correction__h595 =
|
|
INV_checkForException_pcc_BITS_108_TO_90__q1[0] ? 2'b01 : 2'b0 ;
|
|
assign memCap_address__h637 =
|
|
checkForException_pcc[63:0] +
|
|
{ {52{inc__h652[11]}}, inc__h652 } ;
|
|
assign repBound__h535 = x__h960[13:11] - 3'b001 ;
|
|
assign rs1__h1511 =
|
|
(checkForException_regs[19] && !checkForException_regs[18]) ?
|
|
checkForException_regs[17:13] :
|
|
5'd0 ;
|
|
assign tb__h532 =
|
|
{ impliedTopBits__h596,
|
|
IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18[11] } ;
|
|
assign tmp_expBotHalf__h991 =
|
|
{ ~checkForException_pcc[66], checkForException_pcc[65:64] } ;
|
|
assign tmp_expTopHalf__h989 =
|
|
{ ~checkForException_pcc[80:79], checkForException_pcc[78] } ;
|
|
assign x__h1035 = { tmp_expTopHalf__h989, tmp_expBotHalf__h991 } ;
|
|
assign x__h443 = checkForException_pcc[63:0] >> x__h1035 ;
|
|
assign x__h617 = x__h960[13:12] + carry_out__h594 ;
|
|
assign x__h960 =
|
|
INV_checkForException_pcc_BITS_108_TO_90__q1[0] ?
|
|
{ checkForException_pcc[77:67], 3'd0 } :
|
|
b_base__h929 ;
|
|
assign x__h997 = memCap_address__h637 >> x__h1035 ;
|
|
assign y__h1054 =
|
|
{ impliedTopBits__h596,
|
|
IF_INV_checkForException_pcc_BITS_108_TO_90_BI_ETC___d18 } ;
|
|
always@(checkForException_dInst)
|
|
begin
|
|
case (checkForException_dInst[37:33])
|
|
5'd0, 5'd1, 5'd12, 5'd13, 5'd14, 5'd15, 5'd28, 5'd29, 5'd30, 5'd31:
|
|
CASE_checkForException_dInst_BITS_37_TO_33_0_c_ETC__q2 =
|
|
checkForException_dInst[37:33];
|
|
default: CASE_checkForException_dInst_BITS_37_TO_33_0_c_ETC__q2 = 5'd10;
|
|
endcase
|
|
end
|
|
always@(checkForException_csrState)
|
|
begin
|
|
case (checkForException_csrState[14:12])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_checkForException_csrState_BITS_14_TO_12__ETC__q3 =
|
|
checkForException_csrState[14:12];
|
|
default: CASE_checkForException_csrState_BITS_14_TO_12__ETC__q3 = 3'd5;
|
|
endcase
|
|
end
|
|
always@(checkForException_dInst)
|
|
begin
|
|
case (checkForException_dInst[50:39])
|
|
12'd1: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd0;
|
|
12'd2: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd1;
|
|
12'd3: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd2;
|
|
12'd256: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd8;
|
|
12'd260: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd9;
|
|
12'd261: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd10;
|
|
12'd262: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd11;
|
|
12'd320: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd12;
|
|
12'd321: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd13;
|
|
12'd322: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd14;
|
|
12'd323: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd15;
|
|
12'd324: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd16;
|
|
12'd384: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd17;
|
|
12'd768: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd19;
|
|
12'd769: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd20;
|
|
12'd770: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd21;
|
|
12'd771: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd22;
|
|
12'd772: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd23;
|
|
12'd773: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd24;
|
|
12'd774: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd25;
|
|
12'd832: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd26;
|
|
12'd833: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd27;
|
|
12'd834: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd28;
|
|
12'd835: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd29;
|
|
12'd836: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd30;
|
|
12'd1952:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd38;
|
|
12'd1953:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd39;
|
|
12'd1954:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd40;
|
|
12'd1955:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd41;
|
|
12'd1968:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd42;
|
|
12'd1969:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd43;
|
|
12'd1970:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd44;
|
|
12'd1971:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd45;
|
|
12'd2048: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd6;
|
|
12'd2049: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd7;
|
|
12'd2496:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd18;
|
|
12'd2816:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd31;
|
|
12'd2818:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd32;
|
|
12'd3008:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd37;
|
|
12'd3072: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd3;
|
|
12'd3073: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd4;
|
|
12'd3074: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd5;
|
|
12'd3857:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd33;
|
|
12'd3858:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd34;
|
|
12'd3859:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd35;
|
|
12'd3860:
|
|
CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd36;
|
|
default: CASE_checkForException_dInst_BITS_50_TO_39_1_0_ETC__q4 = 6'd46;
|
|
endcase
|
|
end
|
|
always@(checkForException_dInst or
|
|
IF_checkForException_dInst_BIT_38_70_THEN_chec_ETC___d562 or
|
|
checkForException_dInst_BITS_138_TO_136_02_EQ__ETC___d406 or
|
|
NOT_checkForException_pcc_BIT_122_8_9_AND_NOT__ETC___d468 or
|
|
checkForException_csrState or checkForException_pcc)
|
|
begin
|
|
case (checkForException_dInst[143:139])
|
|
5'd17:
|
|
IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d566 =
|
|
checkForException_dInst_BITS_138_TO_136_02_EQ__ETC___d406 ||
|
|
NOT_checkForException_pcc_BIT_122_8_9_AND_NOT__ETC___d468;
|
|
5'd21:
|
|
IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d566 =
|
|
checkForException_csrState[10:9] == 2'd1 &&
|
|
checkForException_csrState[8];
|
|
5'd24:
|
|
IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d566 =
|
|
checkForException_csrState[10:9] == 2'd0 ||
|
|
checkForException_csrState[10:9] == 2'd1 &&
|
|
checkForException_csrState[6] ||
|
|
!checkForException_pcc[122];
|
|
5'd25:
|
|
IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d566 =
|
|
checkForException_csrState[10:9] != 2'd3 ||
|
|
!checkForException_pcc[122];
|
|
default: IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d566 =
|
|
IF_checkForException_dInst_BIT_38_70_THEN_chec_ETC___d562;
|
|
endcase
|
|
end
|
|
always@(checkForException_dInst or
|
|
IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d681 or
|
|
checkForException_csrState)
|
|
begin
|
|
case (checkForException_dInst[143:139])
|
|
5'd24:
|
|
CASE_checkForException_dInst_BITS_143_TO_139_2_ETC__q5 =
|
|
checkForException_csrState[10:9] != 2'd0 &&
|
|
(checkForException_csrState[10:9] != 2'd1 ||
|
|
!checkForException_csrState[6]);
|
|
5'd25:
|
|
CASE_checkForException_dInst_BITS_143_TO_139_2_ETC__q5 =
|
|
checkForException_csrState[10:9] == 2'd3;
|
|
default: CASE_checkForException_dInst_BITS_143_TO_139_2_ETC__q5 =
|
|
checkForException_dInst[143:139] != 5'd21 &&
|
|
IF_checkForException_dInst_BITS_143_TO_139_1_E_ETC___d681;
|
|
endcase
|
|
end
|
|
endmodule // module_checkForException
|
|
|