Toooba

Files

rsnikhil 83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load

2020-02-04 16:02:53 -05:00

src_BSV

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Verilog_RTL

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

xilinx_ip

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Makefile

Removed -D EXTERNAL_DEBUG_MODULE in src_SSITH_P3 Makefile, and added an undef in src_Core/Core/CoreW.bsv

2020-01-23 12:25:21 -05:00

README.txt

Added src_SSITH_P3_sim directory

2020-01-30 20:16:08 +05:30

README.txt

Copyright (c) 2019 Bluespec, Inc.  All Rights Reserved.

This directory is intended for DARPA SSITH users; others may safely ignore it.

This directory contains a wrapper and other resources that package up
MIT's RISCY-OOO to fit into the "standard" core socket in the SSITH GFE
("Government Furnished Equipment").

>================================================================
Context:

The SSITH system is an SoC with a "socket" (placeholder) for a "Core"
module (a RISC-V CPU).  Various implementations are/will be plugged
into this socket:

 - "P1"
    - Baseline Piccolo (BSV) based core
    - Baseline Rocket (Chisel) based core
    - Variations/alternatives by various SSITH project teams

 - "P2"
    - Baseline Flute (BSV) based core
    - Baseline Rocket (Chisel) based core
    - Variations/alternatives by various SSITH project teams

 - "P3"
    - Baseline Tooba (BSV) based core
    - Baseline BOOM (Chisel) based core
    - Variations/alternatives by various SSITH project teams

>================================================================
Whenever there are changes to the Toooba core, rerun:

  $ make compile for a synthesizable (on Xilinx) version
      (which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)

The synthesis version uses Xilinx IP for the integer divider.

>================================================================