8a07e18439
I couldn't quite use the implementation from Flute as the register was too wide for verilator. This one uses wide memories instead, which is way complicated, but I think it works. The width of the memory can be traded off for reset speed. The width at the moment is 8192 bits, which seems to be fast enough.
159 lines
6.4 KiB
Plaintext
159 lines
6.4 KiB
Plaintext
// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved
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//-
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// RVFI_DII modifications:
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// Copyright (c) 2018 Peter Rugg
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//-
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package Mem_Model;
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// ================================================================
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// A simulation model of external DRAM memory.
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// Uses a register file to model memory.
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// ================================================================
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// BSV library imports
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import RegFile :: *;
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import Vector :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Memory :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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// ================================================================
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// Project imports
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import Mem_Controller :: *;
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`ifdef RVFI_DII
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import RVFI_DII :: *;
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`endif
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// ================================================================
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// Mem Model interface
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interface Mem_Model_IFC;
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// The read/write interface
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interface MemoryServer #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) mem_server;
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endinterface
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typedef 'h4000_0000 Bytes_Per_Mem;
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`ifdef RVFI_DII
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typedef 'h0000_0000 Zeroed_0_start;
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typedef RVFI_DII_Mem_Size Zeroed_0_end;
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typedef TLog#(TDiv#(Bits_per_Raw_Mem_Word,8)) ByteOffsetInWord;
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typedef 8192 ZeroMemWidth;
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typedef TLog#(ZeroMemWidth) LogZMWidth;
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Integer wordOffsetWidth = valueOf(ByteOffsetInWord);
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Integer lineInZeroesOffsetWidth = valueOf(LogZMWidth) + valueOf(ByteOffsetInWord);
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typedef Bit#(TSub#(TLog#(TSub#(Zeroed_0_end, Zeroed_0_start)), TAdd#(LogZMWidth,ByteOffsetInWord))) Offset_Zeroes_0;
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typedef Bit#(TSub#(TLog#(TSub#(Zeroed_1_end, Zeroed_1_start)), TAdd#(LogZMWidth,ByteOffsetInWord))) Offset_Zeroes_1;
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typedef 'h3f00_0000 Zeroed_1_start;
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typedef 'h3fff_ff00 Zeroed_1_end;
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`endif
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// ================================================================
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// Mem Model implementation
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(* synthesize *)
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module mkMem_Model (Mem_Model_IFC);
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Integer verbosity = 0; // 0 = quiet; 1 = verbose
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Raw_Mem_Addr alloc_size = fromInteger(valueOf(TDiv#(TMul#(Bytes_Per_Mem,8), Bits_per_Raw_Mem_Word))); //(raw mem words)
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`ifdef RVFI_DII
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Raw_Mem_Addr zeroed_0_start = fromInteger(valueOf(TDiv#(Zeroed_0_start, TDiv#(Bits_per_Raw_Mem_Word, 8))));
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Raw_Mem_Addr zeroed_0_end = fromInteger(valueOf(TDiv#(Zeroed_0_end, TDiv#(Bits_per_Raw_Mem_Word, 8))));
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Raw_Mem_Addr zeroed_1_start = fromInteger(valueOf(TDiv#(Zeroed_1_start, TDiv#(Bits_per_Raw_Mem_Word, 8))));
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Raw_Mem_Addr zeroed_1_end = fromInteger(valueOf(TDiv#(Zeroed_1_end, TDiv#(Bits_per_Raw_Mem_Word, 8))));
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RegFile #(Raw_Mem_Addr, Bit #(Bits_per_Raw_Mem_Word)) rf <- mkRegFile (0, alloc_size - 1);
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//zeroes register allows quick resetting of memory. If bit of zeroes is 0 then corresponding entry of rf is 0.
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RegFile #(Offset_Zeroes_0, Bit #(ZeroMemWidth)) zeroes_0 <- mkRegFileFull;
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RegFile #(Offset_Zeroes_1, Bit #(ZeroMemWidth)) zeroes_1 <- mkRegFileFull;
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Reg#(Bool) reset_done <- mkReg(False);
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Reg#(Offset_Zeroes_0) reset_count_0 <- mkReg(~0);
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Reg#(Offset_Zeroes_1) reset_count_1 <- mkReg(~0);
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rule doZeroesReset(!reset_done);
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zeroes_0.upd(reset_count_0, 0);
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reset_count_0 <= reset_count_0 - 1;
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zeroes_1.upd(reset_count_1, 0);
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reset_count_1 <= reset_count_1 - 1;
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if (reset_count_0 == 0 && reset_count_1 == 0) reset_done <= True;
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endrule
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`else
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RegFile #(Raw_Mem_Addr, Bit #(Bits_per_Raw_Mem_Word)) rf <- mkRegFileLoad ("Mem.hex", 0, alloc_size - 1);
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Reg#(Bool) reset_done <- mkReg(True);
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`endif
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FIFOF #(MemoryResponse #(Bits_per_Raw_Mem_Word)) f_raw_mem_rsps <- mkFIFOF;
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// ----------------------------------------------------------------
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// INTERFACE
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interface MemoryServer mem_server;
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interface Put request;
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method Action put (MemoryRequest #(Bits_per_Raw_Mem_Addr, Bits_per_Raw_Mem_Word) req) if (reset_done);
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`ifdef RVFI_DII
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Bit#(LogZMWidth) offsetLo = truncate((req.address - zeroed_0_start)>>wordOffsetWidth);
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Offset_Zeroes_0 word0 = truncate((req.address - zeroed_0_start)>>lineInZeroesOffsetWidth);
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Bit#(ZeroMemWidth) zeroes_0_word = zeroes_0.sub(word0);
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Offset_Zeroes_1 word1 = truncate((req.address - zeroed_1_start)>>lineInZeroesOffsetWidth);
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Bit#(ZeroMemWidth) zeroes_1_word = zeroes_1.sub(word1);
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`endif
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if (req.address >= alloc_size) begin
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$display ("%0d: ERROR: Mem_Model.request.put: addr 0x%0h >= size 0x%0h (num raw-mem words)",
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cur_cycle, req.address, alloc_size);
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$finish (1); // Assertion failure: address out of bounds
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end
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else if (req.write) begin
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`ifdef RVFI_DII
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if (req.address >= zeroed_0_start && req.address < zeroed_0_end && zeroes_0_word[offsetLo] == 0) begin
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zeroes_0_word[offsetLo] = 1;
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zeroes_0.upd(word0, zeroes_0_word);
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end
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if (req.address >= zeroed_1_start && req.address < zeroed_1_end && zeroes_1_word[offsetLo] == 0) begin
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zeroes_1_word[offsetLo] = 1;
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zeroes_1.upd(word1, zeroes_1_word);
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end
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`endif
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rf.upd (req.address, req.data);
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if (verbosity != 0)
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$display ("%0d: Mem_Model write [0x%0h] <= 0x%0h", cur_cycle, req.address, req.data);
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end
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else begin
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let x = rf.sub (req.address);
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`ifdef RVFI_DII
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$display("req addr: ", fshow(req.address), ", zeroed_0_start: ", fshow(zeroed_0_start), ", zeroed_1_start: ", fshow(zeroed_1_start));
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if (req.address < zeroed_0_end && req.address >= zeroed_0_start && zeroes_0.sub(word0)[offsetLo] == 0) x = 0;
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if (req.address < zeroed_1_end && req.address >= zeroed_1_start && zeroes_1.sub(word1)[offsetLo] == 0) x = 0;
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`endif
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let rsp = MemoryResponse {data: x};
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f_raw_mem_rsps.enq (rsp);
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if (verbosity != 0)
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$display ("%0d: Mem_Model read [0x%0h] => 0x%0h", cur_cycle, req.address, x);
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end
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endmethod
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endinterface
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interface Get response = toGet (f_raw_mem_rsps);
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endinterface
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endmodule
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// ================================================================
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endpackage
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