Peter Rugg 8ef44b0a6c Workaround single step wedges by not waiting for flush before halting

2021-09-24 10:33:58 +00:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Use type EventsCacheCore instead of Vector#(7, Bit#(1))

2021-09-02 16:10:55 +01:00

CPU

Workaround single step wedges by not waiting for flush before halting

2021-09-24 10:33:58 +00:00

Debug_Module

Multicore debug cleanups

2021-01-21 20:51:02 +00:00

ISA

Fix CHERI Exception numbering to match spec.

2021-08-02 12:15:05 +01:00

PLIC

Adapt the PLIC instantiation and wiring to support multiple cores

2021-01-31 17:54:43 +00:00

RISCY_OOO

performed corrections for CONTRACTS_VERIFY

2021-09-07 08:15:03 +01:00