7eff218288
BSC does not play nicely with enums whose labels do not start at 0 and increase linearly. Instead, in such cases, it generates a whole bunch of conditions to "legalise" any read values, which causes an explosion of logic in places like the ROB. Thus, use this ugly (but still typed) alternative that, other than naming conventions enforced by BSC, looks almost the same as an enum.
1345 lines
53 KiB
Plaintext
1345 lines
53 KiB
Plaintext
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// Copyright (c) 2017 Massachusetts Institute of Technology
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// Portions Copyright (c) 2019-2020 Bluespec, Inc.
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Jessica Clarke
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// Copyright (c) 2020 Peter Rugg
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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//
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// Permission is hereby granted, free of charge, to any person
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// obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without
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// restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies
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// of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be
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// included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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`include "ProcConfig.bsv"
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import Types::*;
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import ProcTypes::*;
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import DefaultValue::*;
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import ConcatReg::*;
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import ConfigReg::*;
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import Ehr::*;
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import Fifos::*;
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import Vector::*;
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import FIFO::*;
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import GetPut::*;
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import BuildVector::*;
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import CHERICap::*;
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import CHERICC_Fat::*;
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import ISA_Decls_CHERI::*;
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// ================================================================
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// BSV additional libs
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import Cur_Cycle :: *;
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// ================================================================
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// Project imports from Toooba
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import SoC_Map :: *;
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// ================================================================
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// Information returned on traps and mret/sret/uret
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typedef Bit#(SizeOf#(Exception)) Cause;
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typedef struct {
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CapPipe new_pcc;
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`ifdef INCLUDE_TANDEM_VERIF
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// The fields below are for tandem verification only
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Bit #(2) prv;
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Data status;
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Data cause;
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CapPipe epcc;
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Data tval;
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`endif
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} Trap_Updates
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deriving (Bits, FShow);
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typedef struct {
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CapPipe new_pcc;
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`ifdef INCLUDE_TANDEM_VERIF
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// The fields below are for tandem verification only
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Bit #(2) prv;
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Data status;
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`endif
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} RET_Updates
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deriving (Bits, FShow);
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// ================================================================
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interface CsrFile;
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// Read
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method Data rd(CSR csr);
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method CapReg scrRd(SCR csr);
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// normal write by CSRXXX inst to any CSR
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method Action csrInstWr(CSR csr, Data x);
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// normal write by RWSpecialCap inst to any SCR
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method Action scrInstWr(SCR csr, CapReg x);
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// normal write by FPU inst to FPU CSR
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method Bool fpuInstNeedWr(Bit#(5) fflags, Bool fpu_dirty);
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method Action fpuInstWr(Bit#(5) fflags); // FPU must become dirty
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`ifdef INCLUDE_TANDEM_VERIF
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// Returns new fcsr and mstatus (pure function)
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method Tuple2 #(Bit #(5), Data) fpuInst_csr_updates (Bit #(5) fflags,
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Bool init_for_way0,
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Bit #(5) old_fflags,
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Data old_mstatus);
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method Data getMIP;
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`endif
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// The WARL transform performed during CSRRx writes to a CSR
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method Data warl_xform (CSR csr, Data x);
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// Methods for handling traps
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method Maybe#(Interrupt) pending_interrupt;
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method ActionValue#(Trap_Updates) trap(Trap t, CapPipe pcc, Addr faultAddr, Bit #(32) orig_inst);
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method ActionValue#(RET_Updates) sret;
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method ActionValue#(RET_Updates) mret;
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// Outputs for CSRs that the rest of the processor needs to know about
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method VMInfo vmI;
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method VMInfo vmD;
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method CsrDecodeInfo decodeInfo;
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// Updating minstret CSR outside of normal CSR write instructions. This
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// increment will see the effect of normal CSR write.
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method Action incInstret(SupCnt x);
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// update copy of mtime
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method Action setTime(Data t);
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// MSIP/MTIP bits for external world (e.g., for MMIO and timer interrupt).
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// XXX These methods should only be called when the processor backend
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// pipeline does not contain any CSRXXX inst or corresponding interrupt
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// inst (the inst which is turned into an interrupt). This ensures that
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// CSRXXX and interrupt are handled atomically. MSIP/MTIP should not
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// affect other insts (e.g., address translation of loads/stores),
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// synchronous exceptions and other types of interrupts.
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method Bit#(1) getMSIP;
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method Action setMSIP(Bit#(1) v);
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method Action setMTIP(Bit#(1) v);
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// Bluespec: external interrupts targeting machine and supervisor modes
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method Action setMEIP (Bit #(1) v);
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method Action setSEIP (Bit #(1) v);
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// performance stats is collected or not
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method Bool doPerfStats;
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// send/recv updates on stats CSR globally
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method ActionValue#(Bool) sendDoStats;
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method Action recvDoStats(Bool s);
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// terminate
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method ActionValue#(void) terminate;
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`ifdef INCLUDE_GDB_CONTROL
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// Read dpc
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method CapReg dpc_read ();
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// Update dpc
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method Action dpc_write (CapReg pc);
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// Check whether to enter Debug Mode based on dcsr.{ebreakm, ebreaks, ebreaku}
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method Bit #(1) dcsr_break_bit;
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// Read dcsr[2], the step bit
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method Bit #(1) dcsr_step_bit;
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// Update 'cause' in DCSR
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// Is invoked by logic that stops a hart, to enter Debug Mode
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(* always_ready *)
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method Action dcsr_cause_write (Bit #(3) dcsr_cause);
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`endif
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endinterface
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// Fancy Reg functions
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function Reg#(Bit#(n)) truncateReg(Reg#(Bit#(m)) r) provisos (Add#(a__,n,m));
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return (interface Reg;
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method Bit#(n) _read = truncate(r._read);
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method Action _write(Bit#(n) x) = r._write({truncateLSB(r._read), x});
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endinterface);
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endfunction
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function Reg#(Bit#(n)) truncateRegLSB(Reg#(Bit#(m)) r) provisos (Add#(a__,n,m));
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return (interface Reg;
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method Bit#(n) _read = truncateLSB(r._read);
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method Action _write(Bit#(n) x) = r._write({x, truncate(r._read)});
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endinterface);
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endfunction
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function Reg#(Bit#(n)) zeroExtendReg(Reg#(Bit#(m)) r) provisos (Add#(a__,m,n));
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return (interface Reg;
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method Bit#(n) _read = zeroExtend(r._read);
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method Action _write(Bit#(n) x) = r._write(truncate(x));
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endinterface);
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endfunction
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function Reg#(t) readOnlyReg(t r);
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return (interface Reg;
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method t _read = r;
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method Action _write(t x) = noAction;
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endinterface);
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endfunction
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// module version of readOnlyReg for convenience
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module mkReadOnlyReg#(t x)(Reg#(t));
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return readOnlyReg(x);
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endmodule
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function Reg#(t) regFromReadOnly(ReadOnly#(t) r);
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return (interface Reg;
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method t _read = r._read;
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method Action _write(t x);
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noAction;
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endmethod
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endinterface);
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endfunction
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function Reg#(t) addWriteSideEffect(Reg#(t) r, Action a);
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return (interface Reg;
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method t _read = r._read;
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method Action _write(t x);
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r._write(x);
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a;
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endmethod
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endinterface);
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endfunction
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function Bool has_csr_permission(CSR csr, Bit#(2) prv, Bool write);
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Bit#(12) csr_index = pack(csr);
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return ((prv >= csr_index[9:8]) && (!write || (csr_index[11:10] != 2'b11)));
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endfunction
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// non-standard terminate CSR
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interface Terminate;
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interface Reg#(Data) reg_ifc;
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method ActionValue#(void) terminate;
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endinterface
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module mkTerminate(Terminate);
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FIFO#(void) terminateQ <- mkFIFO1;
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interface Reg reg_ifc;
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method Action _write(Data x);
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terminateQ.enq(?);
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$display(
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"[Terminate CSR] being written (val = %x), ",
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"send terminate signal to host", x
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);
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endmethod
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method Data _read = 0;
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endinterface
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method terminate = toGet(terminateQ).get;
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endmodule
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// stats CSR: there is only one copy in the whole multiprocessor, so any write
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// to stats CSR will be broadcasted
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interface StatsCsr;
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interface Reg#(Data) reg_ifc;
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method Bool doPerfStats;
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// send/recv updates on stats CSR globally
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method ActionValue#(Bool) sendDoStats;
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method Action recvDoStats(Bool s);
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endinterface
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module mkStatsCsr(StatsCsr);
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Reg#(Bool) doStats <- mkConfigReg(False);
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FIFO#(Bool) writeQ <- mkFIFO1;
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interface Reg reg_ifc;
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method Data _read = zeroExtend(pack(doStats));
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method Action _write(Data x);
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writeQ.enq(unpack(truncate(x)));
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endmethod
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endinterface
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method Bool doPerfStats = doStats;
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method ActionValue#(Bool) sendDoStats;
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writeQ.deq;
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return writeQ.first;
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endmethod
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method Action recvDoStats(Bool s);
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doStats <= s;
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endmethod
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endmodule
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function Reg#(Data) scrToCsr(Reg#(CapReg) scr) = interface Reg
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method _write (x) = action CapPipe scr_pipe = cast(scr); scr <= cast(setOffset(scr_pipe, x).value); endaction;
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method Data _read;
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CapPipe scr_pipe = cast(scr);
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return getOffset(scr_pipe);
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endmethod
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endinterface;
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// same as EHR except that read port 0 is not ordered with other methods. Read
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// port 1 will still get bypassing from write port 0.
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module mkConfigEhr#(t init)(Ehr#(n, t)) provisos(Bits#(t, w));
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Ehr#(n, t) data <- mkEhr(init);
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Wire#(t) read <- mkBypassWire;
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(* fire_when_enabled, no_implicit_conditions *)
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rule setRead;
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read <= data[0];
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endrule
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Ehr#(n, t) ifc = ?;
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ifc[0] = (interface Reg;
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method _read = read._read;
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method _write = data[0]._write;
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endinterface);
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for(Integer i = 1; i < valueOf(n); i = i+1) begin
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ifc[i] = (interface Reg;
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method _read = data[i]._read;
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method _write = data[i]._write;
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endinterface);
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end
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return ifc;
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endmodule
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module mkCsrFile #(Data hartid)(CsrFile);
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RiscVISASubset isa = defaultValue;
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// To save from bypassing logic, CSR reads will get stale value
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let mkCsrReg = mkConfigReg;
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let mkCsrEhr = mkConfigEhr;
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// current prv level (this is not a csr...)
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Reg#(Bit#(2)) prv_reg <- mkCsrReg(prvM);
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// Machine level CSRs
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// mstatus
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Reg#(Bit#(2)) xs_reg <- mkReadOnlyReg(0); // XXX no extension
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Reg#(Bit#(2)) fs_reg <- (isa.f || isa.d) ? mkCsrReg(2'b00) : mkReadOnlyReg(0);
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Reg#(Bit#(1)) sd_reg = readOnlyReg(
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((xs_reg == 2'b11) || (fs_reg == 2'b11)) ? 1 : 0
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);
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function Bit #(1) fn_sd_val (Bit #(2) xs_val, Bit #(2) fs_val);
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return (((xs_val == 2'b11) || (fs_val == 2'b11)) ? 1 : 0);
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endfunction
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Reg#(Bit#(2)) sxl_reg = readOnlyReg(getXLBits);
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Reg#(Bit#(2)) uxl_reg = readOnlyReg(getXLBits);
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Reg#(Bit#(1)) tsr_reg <- mkCsrReg(0);
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Reg#(Bit#(1)) tw_reg <- mkCsrReg(0);
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Reg#(Bit#(1)) tvm_reg <- mkCsrReg(0);
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Reg#(Bit#(1)) mxr_reg <- mkCsrReg(0);
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Reg#(Bit#(1)) sum_reg <- mkCsrReg(0);
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Reg#(Bit#(1)) mprv_reg <- mkCsrReg(0);
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Reg#(Bit#(2)) mpp_reg <- mkCsrReg(0);
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Reg#(Bit#(1)) spp_reg <- mkCsrReg(0);
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Vector#(4, Reg#(Bit#(2))) prev_prv_vec = vec(
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// prev_prv_vec[x]: privilege mode before trapping into mode x
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readOnlyReg(prvU), // upp
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concatReg2(readOnlyReg(1'b0), spp_reg), // spp
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readOnlyReg(2'b0), // reserved
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mpp_reg
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);
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Vector#(4, Reg#(Bit#(1))) ie_vec = replicate(
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readOnlyReg(0) // ie_vec[x]: interrupt enable for mode x
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);
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ie_vec[prvU] <- mkCsrReg(0);
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ie_vec[prvS] <- mkCsrReg(0);
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ie_vec[prvM] <- mkCsrReg(0);
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Vector#(4, Reg#(Bit#(1))) prev_ie_vec = replicate(
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readOnlyReg(0) // prev_ie_vec[x]: ie_vec[x] before trapping into mode x
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);
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prev_ie_vec[prvU] <- mkCsrReg(0);
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prev_ie_vec[prvS] <- mkCsrReg(0);
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prev_ie_vec[prvM] <- mkCsrReg(0);
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Reg#(Data) mstatus_csr = concatReg24(
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sd_reg, readOnlyReg(27'b0), sxl_reg, uxl_reg, readOnlyReg(9'b0),
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tsr_reg, tw_reg, tvm_reg, mxr_reg, sum_reg, mprv_reg, xs_reg, fs_reg,
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mpp_reg, readOnlyReg(2'b0), spp_reg,
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prev_ie_vec[prvM], readOnlyReg(1'b0),
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prev_ie_vec[prvS], prev_ie_vec[prvU],
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ie_vec[prvM], readOnlyReg(1'b0),
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ie_vec[prvS], ie_vec[prvU]
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);
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function Data fn_mstatus_val (Bit #(2) sxl_val, Bit #(2) uxl_val,
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Bit #(1) tsr_val, Bit #(1) tw_val, Bit #(1) tvm_val,
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Bit #(1) mxr_val, Bit #(1) sum_val, Bit #(1) mprv_val,
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Bit #(2) xs_val, Bit #(2) fs_val,
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Bit #(2) mpp_val, Bit #(1) spp_val,
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Bit #(1) prev_ie_vec_prvM_val,
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Bit #(1) prev_ie_vec_prvS_val, Bit #(1) prev_ie_vec_prvU_val,
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Bit #(1) ie_vec_prvM_val,
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Bit #(1) ie_vec_prvS_val, Bit #(1) ie_vec_prvU_val);
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return {fn_sd_val (xs_val, fs_val),
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27'b0, sxl_val, uxl_val, 9'b0,
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tsr_val, tw_val, tvm_val, mxr_val, sum_val, mprv_val, xs_val, fs_val,
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mpp_val, 2'b0, spp_val,
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prev_ie_vec_prvM_val, 1'b0,
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prev_ie_vec_prvS_val, prev_ie_vec_prvU_val,
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ie_vec_prvM_val, 1'b0,
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ie_vec_prvS_val, ie_vec_prvU_val};
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endfunction
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// misa
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Reg#(Data) misa_csr = readOnlyReg({getXLBits, 36'b0, getExtensionBits(isa)});
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// medeleg: some exceptions don't exist, fix corresponding bits to 0
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Reg#(Bit#(3)) medeleg_28_26_reg <- mkCsrReg(0); // CHERI causes 0x1a-0x1c
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Reg#(Bit#(1)) medeleg_15_reg <- mkCsrReg(0); // cause 15
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Reg#(Bit#(3)) medeleg_13_11_reg <- mkCsrReg(0); // case 13-11
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Reg#(Bit#(10)) medeleg_9_0_reg <- mkCsrReg(0); // cause 9-0
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Reg#(Data) medeleg_csr = concatReg8(
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readOnlyReg(35'b0), medeleg_28_26_reg,
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readOnlyReg(10'b0), medeleg_15_reg,
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readOnlyReg(1'b0), medeleg_13_11_reg,
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readOnlyReg(1'b0), medeleg_9_0_reg
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);
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// mideleg: some interrupts don't exist, fix corresponding bits to 0
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Reg#(Bit#(1)) mideleg_11_reg <- mkCsrReg(0);
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Reg#(Bit#(3)) mideleg_9_7_reg <- mkCsrReg(0);
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Reg#(Bit#(3)) mideleg_5_3_reg <- mkCsrReg(0);
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Reg#(Bit#(2)) mideleg_1_0_reg <- mkCsrReg(0);
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Reg#(Data) mideleg_csr = concatReg8(
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readOnlyReg(52'b0), mideleg_11_reg,
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readOnlyReg(1'b0), mideleg_9_7_reg,
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readOnlyReg(1'b0), mideleg_5_3_reg,
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readOnlyReg(1'b0), mideleg_1_0_reg
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);
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// mie
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Vector#(4, Reg#(Bit#(1))) external_int_en_vec = replicate(readOnlyReg(0));
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external_int_en_vec[prvU] <- mkCsrReg(0);
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external_int_en_vec[prvS] <- mkCsrReg(0);
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external_int_en_vec[prvM] <- mkCsrReg(0);
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Vector#(4, Reg#(Bit#(1))) timer_int_en_vec = replicate(readOnlyReg(0));
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timer_int_en_vec[prvU] <- mkCsrReg(0);
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timer_int_en_vec[prvS] <- mkCsrReg(0);
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timer_int_en_vec[prvM] <- mkCsrReg(0);
|
|
Vector#(4, Reg#(Bit#(1))) software_int_en_vec = replicate(readOnlyReg(0));
|
|
software_int_en_vec[prvU] <- mkCsrReg(0);
|
|
software_int_en_vec[prvS] <- mkCsrReg(0);
|
|
software_int_en_vec[prvM] <- mkCsrReg(0);
|
|
Reg#(Data) mie_csr = concatReg13(
|
|
readOnlyReg(52'b0),
|
|
external_int_en_vec[prvM], readOnlyReg(1'b0),
|
|
external_int_en_vec[prvS], readOnlyReg(1'b0), // only if misa.N: external_int_en_vec[prvU],
|
|
timer_int_en_vec[prvM], readOnlyReg(1'b0),
|
|
timer_int_en_vec[prvS], readOnlyReg(1'b0), // only if misa.N: timer_int_en_vec[prvU],
|
|
software_int_en_vec[prvM], readOnlyReg(1'b0),
|
|
software_int_en_vec[prvS], readOnlyReg(1'b0) // only if misa.N: software_int_en_vec[prvU]
|
|
);
|
|
// mcounteren
|
|
Reg#(Bit#(1)) mcounteren_ir_reg <- mkCsrReg(0);
|
|
Reg#(Bit#(1)) mcounteren_tm_reg <- mkCsrReg(0);
|
|
Reg#(Bit#(1)) mcounteren_cy_reg <- mkCsrReg(0);
|
|
Reg#(Data) mcounteren_csr = concatReg5(
|
|
readOnlyReg(32'b0),
|
|
readOnlyReg(29'b0), // hpmcounter 3-31 not accessible in S mode
|
|
mcounteren_ir_reg, mcounteren_tm_reg, mcounteren_cy_reg
|
|
);
|
|
// mscratch
|
|
Reg#(Data) mscratch_csr <- mkCsrReg(0);
|
|
// mcause
|
|
Reg#(Bit#(1)) mcause_interrupt_reg <- mkCsrReg(0);
|
|
Reg#(Cause) mcause_code_reg <- mkCsrReg(0);
|
|
Reg#(Data) mcause_csr = concatReg3(
|
|
mcause_interrupt_reg, readOnlyReg(0), mcause_code_reg
|
|
);
|
|
function Data fn_mcause_val (Bit #(1) mcause_interrupt_val, Cause mcause_code_val);
|
|
return { mcause_interrupt_val, 'b0, mcause_code_val };
|
|
endfunction
|
|
|
|
// mtval (mbadaddr in spike)
|
|
Reg#(Data) mtval_csr <- mkCsrReg(0);
|
|
// mip
|
|
Vector#(4, Reg#(Bit#(1))) external_int_pend_vec = replicate(readOnlyReg(0));
|
|
external_int_pend_vec[prvU] <- mkCsrReg(0);
|
|
external_int_pend_vec[prvS] <- mkCsrReg(0);
|
|
external_int_pend_vec[prvM] <- mkCsrReg(0); // TODO: bug (writeable by CSRRx)?
|
|
Vector#(4, Reg#(Bit#(1))) timer_int_pend_vec = replicate(readOnlyReg(0));
|
|
timer_int_pend_vec[prvU] <- mkCsrReg(0);
|
|
timer_int_pend_vec[prvS] <- mkCsrReg(0);
|
|
timer_int_pend_vec[prvM] <- mkCsrReg(0); // TODO: bug (writeable by CSRRx)?
|
|
Vector#(4, Reg#(Bit#(1))) software_int_pend_vec = replicate(readOnlyReg(0));
|
|
software_int_pend_vec[prvU] <- mkCsrReg(0);
|
|
software_int_pend_vec[prvS] <- mkCsrReg(0);
|
|
software_int_pend_vec[prvM] <- mkCsrReg(0); // TODO: bug (writeable by CSRRx)?
|
|
Reg#(Data) mip_csr = concatReg13(
|
|
readOnlyReg(52'b0),
|
|
// External interrupts
|
|
readOnlyReg(external_int_pend_vec[prvM]), // MEIP is read-only to software
|
|
readOnlyReg(1'b0),
|
|
external_int_pend_vec[prvS],
|
|
readOnlyReg(1'b0), // only if misa.N: external_int_pend_vec[prvU],
|
|
// Timer interrupts
|
|
readOnlyReg(timer_int_pend_vec[prvM]), // MTIP is read-only to software
|
|
readOnlyReg(1'b0),
|
|
timer_int_pend_vec[prvS],
|
|
readOnlyReg(1'b0), // only if misa.N: timer_int_pend_vec[prvU],
|
|
// Software interrupts
|
|
readOnlyReg(software_int_pend_vec[prvM]), // MSIP is read-only to software
|
|
readOnlyReg(1'b0),
|
|
software_int_pend_vec[prvS],
|
|
readOnlyReg(1'b0) // only if misa.N: software_int_pend_vec[prvU]
|
|
);
|
|
// MIP and MIE fields are WARL (Write Any Read Legal)
|
|
// We support M-privilege and S-privilege bits only;
|
|
// this mask allows only those bits through.
|
|
Data mip_mie_warl_mask = zeroExtend (12'h_222);
|
|
|
|
// minstret
|
|
Ehr#(2, Data) minstret_ehr <- mkCsrEhr(0);
|
|
Reg#(Data) minstret_csr = minstret_ehr[0];
|
|
// mcycle
|
|
Ehr#(2, Data) mcycle_ehr <- mkCsrEhr(0);
|
|
Reg#(Data) mcycle_csr = mcycle_ehr[0];
|
|
// mvendorid
|
|
Reg#(Data) mvendorid_csr = readOnlyReg(0);
|
|
// marchid
|
|
Reg#(Data) marchid_csr = readOnlyReg(0);
|
|
// mimpid
|
|
Reg#(Data) mimpid_csr = readOnlyReg(0);
|
|
// mhartid
|
|
Reg#(Data) mhartid_csr = readOnlyReg(hartid);
|
|
|
|
// Supervisor level CSRs
|
|
// sstatus: restricted view of mstatus
|
|
Reg#(Data) sstatus_csr = concatReg17(
|
|
sd_reg, readOnlyReg(29'b0), uxl_reg, readOnlyReg(12'b0),
|
|
mxr_reg, sum_reg, readOnlyReg(1'b0), xs_reg, fs_reg,
|
|
readOnlyReg(4'b0), spp_reg,
|
|
readOnlyReg(2'b0), prev_ie_vec[prvS], prev_ie_vec[prvU],
|
|
readOnlyReg(2'b0), ie_vec[prvS], ie_vec[prvU]
|
|
);
|
|
function Data fn_sstatus_val (Bit #(2) uxl_val,
|
|
Bit #(1) mxr_val, Bit #(1) sum_val,
|
|
Bit #(2) xs_val, Bit #(2) fs_val,
|
|
Bit #(1) spp_val,
|
|
Bit #(1) prev_ie_vec_prvS_val,
|
|
Bit #(1) prev_ie_vec_prvU_val,
|
|
Bit #(1) ie_vec_prvS_val,
|
|
Bit #(1) ie_vec_prvU_val);
|
|
return {fn_sd_val (xs_val, fs_val),
|
|
27'b0, 2'b0, uxl_val, 12'b0,
|
|
mxr_val, sum_val, 1'b0, xs_val, fs_val,
|
|
4'b0, spp_val,
|
|
2'b0,
|
|
prev_ie_vec_prvS_val, prev_ie_vec_prvU_val,
|
|
2'b0,
|
|
ie_vec_prvS_val, ie_vec_prvU_val};
|
|
endfunction
|
|
|
|
// sie: restricted view of mie
|
|
Reg#(Data) sie_csr = concatReg9(
|
|
readOnlyReg(54'b0),
|
|
external_int_en_vec[prvS], readOnlyReg(1'b0), // only if misa.N: external_int_en_vec[prvU],
|
|
readOnlyReg(2'b0),
|
|
timer_int_en_vec[prvS], readOnlyReg(1'b0), // only if misa.N: timer_int_en_vec[prvU],
|
|
readOnlyReg(2'b0),
|
|
software_int_en_vec[prvS], readOnlyReg(1'b0) // only if misa.N: software_int_en_vec[prvU]
|
|
);
|
|
// scounteren
|
|
Reg#(Bit#(1)) scounteren_ir_reg <- mkCsrReg(0);
|
|
Reg#(Bit#(1)) scounteren_tm_reg <- mkCsrReg(0);
|
|
Reg#(Bit#(1)) scounteren_cy_reg <- mkCsrReg(0);
|
|
Reg#(Data) scounteren_csr = concatReg5(
|
|
readOnlyReg(32'b0),
|
|
readOnlyReg(29'b0), // hpmcounter 3-31 not accessible in U mode
|
|
scounteren_ir_reg, scounteren_tm_reg, scounteren_cy_reg
|
|
);
|
|
// sscratch
|
|
Reg#(Data) sscratch_csr <- mkCsrReg(0);
|
|
// scause
|
|
Reg#(Bit#(1)) scause_interrupt_reg <- mkCsrReg(0);
|
|
Reg#(Cause) scause_code_reg <- mkCsrReg(0);
|
|
Reg#(Data) scause_csr = concatReg3(
|
|
scause_interrupt_reg, readOnlyReg('b0), scause_code_reg
|
|
);
|
|
function Data fn_scause_val (Bit #(1) scause_interrupt_val, Cause scause_code_val);
|
|
return { scause_interrupt_val, 0, scause_code_val };
|
|
endfunction
|
|
|
|
// stval (sbadaddr in spike)
|
|
Reg#(Data) stval_csr <- mkCsrReg(0);
|
|
// sip: restricted view of mip
|
|
Reg#(Data) sip_csr = concatReg9(
|
|
readOnlyReg(54'b0),
|
|
external_int_pend_vec[prvS], readOnlyReg(1'b0), // only if misa.N: external_int_pend_vec[prvU],
|
|
readOnlyReg(2'b0),
|
|
timer_int_pend_vec[prvS], readOnlyReg(1'b0), // only if misa.N: timer_int_pend_vec[prvU],
|
|
readOnlyReg(2'b0),
|
|
software_int_pend_vec[prvS], readOnlyReg(1'b0) // only if misa.N: software_int_pend_vec[prvU]
|
|
);
|
|
|
|
// SIP and SIE fields are WARL (Write Any Read Legal)
|
|
// We support S-privilege bits only;
|
|
// this mask allows only those bits through.
|
|
Data sip_sie_warl_mask = zeroExtend (12'h_222);
|
|
|
|
// satp (sptbr in spike): FIXME we only support Bare and Sv39, so we hack
|
|
// the encoding of mode[3:0] field. Only mode[3] is relevant, other bits
|
|
// are always 0
|
|
Reg#(Bit#(1)) vm_mode_sv39_reg <- mkCsrReg(0);
|
|
Reg#(Bit#(4)) vm_mode_reg = concatReg2(vm_mode_sv39_reg, readOnlyReg(3'b0));
|
|
Reg#(Asid) asid_reg <- mkCsrReg(0);
|
|
Reg#(Bit#(16)) full_asid_reg = zeroExtendReg(asid_reg);
|
|
Reg#(Bit#(44)) ppn_reg <- mkCsrReg(0);
|
|
Reg#(Data) satp_csr = concatReg3(vm_mode_reg, full_asid_reg, ppn_reg);
|
|
|
|
// User level CSRs
|
|
// According to spike, any write to fflags/frm/fcsr will set fs_reg as
|
|
// dirty, regardless of whether the write truly changes value or not.
|
|
// Besides, any non-zero FP exception flags will also make fs_reg dirty.
|
|
// fflags: if we directly change fflags_reg (instead of fflags_csr), then
|
|
// we must set fs_reg manually
|
|
Reg#(Bit#(5)) fflags_reg <- mkCsrReg(0);
|
|
Reg#(Data) fflags_csr = addWriteSideEffect(
|
|
zeroExtendReg(fflags_reg), fs_reg._write(2'b11)
|
|
);
|
|
// frm: if we directly change frm_reg (instead of frm_csr), then we must
|
|
// set fs_reg manually
|
|
Reg#(Bit#(3)) frm_reg <- mkCsrReg(0);
|
|
Reg#(Data) frm_csr = addWriteSideEffect(
|
|
zeroExtendReg(frm_reg), fs_reg._write(2'b11)
|
|
);
|
|
// fcsr
|
|
Reg#(Data) fcsr_csr = addWriteSideEffect(
|
|
zeroExtendReg(concatReg2(frm_reg, fflags_reg)), fs_reg._write(2'b11)
|
|
);
|
|
// cycle
|
|
Reg#(Data) cycle_csr = readOnlyReg(mcycle_csr);
|
|
// time
|
|
Reg#(Data) time_reg <- mkCsrReg(0);
|
|
Reg#(Data) time_csr = readOnlyReg(time_reg);
|
|
// instret
|
|
Reg#(Data) instret_csr = readOnlyReg(minstret_csr);
|
|
// terminate (non-standard)
|
|
Terminate terminate_module <- mkTerminate;
|
|
Reg#(Data) terminate_csr = terminate_module.reg_ifc;
|
|
// whether performance stats is collected
|
|
StatsCsr stats_module <- mkStatsCsr;
|
|
Reg#(Data) stats_csr = stats_module.reg_ifc;
|
|
|
|
Reg #(Data) rg_tselect <- mkConfigReg (0);
|
|
// Note: ISA test rv64mi-p-breakpoint assumes tdata1's reset value == 0
|
|
// Until we implement trigger functionality,
|
|
// force 'tdata1.type' field ([xlen-1:xlen-4]) to zero
|
|
// meaning: 'There is no trigger at this tselect'
|
|
Reg #(Bit #(4)) rg_tdata1_type <- mkReadOnlyReg (0);
|
|
Reg #(Bit #(1)) rg_tdata1_dmode <- mkCsrReg (0);
|
|
Reg #(Bit #(59)) rg_tdata1_data <- mkCsrReg (0);
|
|
Reg #(Data) rg_tdata1 = concatReg3 (rg_tdata1_type, rg_tdata1_dmode, rg_tdata1_data);
|
|
Reg #(Data) rg_tdata2 <- mkConfigRegU;
|
|
Reg #(Data) rg_tdata3 <- mkConfigRegU;
|
|
// Capability cause register
|
|
Reg #(CapException) mccsr_reg <- mkCsrReg(unpack(0));
|
|
|
|
`ifdef INCLUDE_GDB_CONTROL
|
|
// DCSR is 32b even in RV64
|
|
Bit #(32) dcsr_reset_value = {4'h4, // [31:28] xdebugver
|
|
12'h0, // [27:16] reserved
|
|
1'h0, // [15] ebreakm
|
|
1'h0, // [14] reserved
|
|
1'h0, // [13] ebreaks
|
|
1'h0, // [12] ebreaku
|
|
1'h0, // [11] stepie
|
|
1'h0, // [10] stopcount
|
|
1'h0, // [9] stoptime
|
|
3'h0, // [8:6] cause // WARNING: 0 is non-standard
|
|
1'h0, // [5] reserved
|
|
1'h1, // [4] mprven
|
|
1'h0, // [3] nmip // non-maskable interrupt pending
|
|
1'h0, // [2] step
|
|
2'h3}; // [1:0] prv (machine mode)
|
|
|
|
// RV64: dcsr's upper 32b zeroExtended/ignored
|
|
Reg #(Data) rg_dcsr <- mkConfigReg (zeroExtend (dcsr_reset_value));
|
|
Reg #(CapReg) rg_dpc <- mkConfigReg (setAddrUnsafe(almightyCap,soc_map_struct.pc_reset_value));
|
|
Reg #(Data) rg_dscratch0 <- mkConfigRegU;
|
|
Reg #(Data) rg_dscratch1 <- mkConfigRegU;
|
|
`endif
|
|
|
|
`ifdef SECURITY
|
|
// sanctum machine CSRs
|
|
|
|
// ### Enclave virtual base and mask
|
|
// (per-core) registers
|
|
// ( defines a virtual region for which enclave page tables are used in
|
|
// place of OS-controlled page tables)
|
|
// (machine-mode non-standard read/write)
|
|
Reg#(Data) mevbase_csr <- mkCsrReg(maxBound); // impossible base & mask,
|
|
Reg#(Data) mevmask_csr <- mkCsrReg(0); // so no enclave accesses are possible
|
|
|
|
// ### Enclave page table base
|
|
// (per core) register
|
|
// ( pointer to a separate page table data structure used to translate enclave
|
|
// virtual addresses)
|
|
// (machine-mode non-standard read/write)
|
|
Reg#(Bit#(44)) eppn_reg <- mkCsrReg(0);
|
|
Reg#(Data) meatp_csr = zeroExtendReg(eppn_reg);
|
|
|
|
// ### DRAM bitmap
|
|
// (per core) registers (OS and Enclave)
|
|
// ( white-lists the DRAM regions the core is allowed to access via OS and
|
|
// enclave virtual addresses)
|
|
// (machine-mode non-standard read/write)
|
|
Reg#(Data) mmrbm_csr <- mkCsrReg(maxBound);
|
|
Reg#(Data) memrbm_csr <- mkCsrReg(0);
|
|
|
|
// ### Protected region base and mask
|
|
// (per core) registers (OS and Enclave)
|
|
// ( these are used to prevent address translation into a specific range of
|
|
// physical addresses, for example to protect the security monitor from all software)
|
|
// (machine-mode non-standard read/write)
|
|
Reg#(Data) mparbase_csr <- mkCsrReg(maxBound);
|
|
Reg#(Data) mparmask_csr <- mkCsrReg(0);
|
|
Reg#(Data) meparbase_csr <- mkCsrReg(0);
|
|
Reg#(Data) meparmask_csr <- mkCsrReg(0);
|
|
|
|
// ### Turn on/off speculation
|
|
Reg#(Bit#(2)) mspec_reg <- mkCsrReg(mSpecAll);
|
|
Reg#(Data) mspec_csr = zeroExtendReg(mspec_reg);
|
|
|
|
// sanctum user CSR
|
|
// ### true random number
|
|
// For now, we skip secure boot, keep TRNG = 0
|
|
Reg#(Data) trng_csr <- mkReadOnlyReg(0); //mkTRNG;
|
|
`endif
|
|
|
|
//SCRs
|
|
Reg#(CapReg) ddc_reg <- mkCsrReg(defaultValue);
|
|
|
|
// User level SCRs with accessSysRegs
|
|
// Reg#(CapReg) utcc_reg <- mkCsrReg(defaultValue);
|
|
// Reg#(CapReg) utdc_reg <- mkCsrReg(nullCap);
|
|
// Reg#(CapReg) uScratchC_reg <- mkCsrReg(nullCap);
|
|
// Reg#(CapReg) uepcc_reg <- mkCsrReg(defaultValue);
|
|
|
|
// System level SCRs with accessSysRegs
|
|
Reg#(CapReg) stcc_reg <- mkCsrReg(defaultValue);
|
|
Reg#(CapReg) stdc_reg <- mkCsrReg(nullCap);
|
|
Reg#(CapReg) sScratchC_reg <- mkCsrReg(nullCap);
|
|
Ehr#(2, CapReg) sepcc_reg <- mkConfigEhr(defaultValue);
|
|
|
|
// Machine level SCRs with accessSysRegs
|
|
Reg#(CapReg) mtcc_reg <- mkCsrReg(defaultValue);
|
|
Reg#(CapReg) mtdc_reg <- mkCsrReg(nullCap);
|
|
Reg#(CapReg) mScratchC_reg <- mkCsrReg(nullCap);
|
|
Ehr#(2, CapReg) mepcc_reg <- mkConfigEhr(defaultValue);
|
|
|
|
rule incCycle;
|
|
mcycle_ehr[1] <= mcycle_ehr[1] + 1;
|
|
endrule
|
|
|
|
// Function for getting a csr given an index
|
|
function Reg#(Data) get_csr(CSR csr);
|
|
return (case (csr)
|
|
// User CSRs
|
|
csrAddrFFLAGS: fflags_csr;
|
|
csrAddrFRM: frm_csr;
|
|
csrAddrFCSR: fcsr_csr;
|
|
csrAddrCYCLE: cycle_csr;
|
|
csrAddrTIME: time_csr;
|
|
csrAddrINSTRET: instret_csr;
|
|
csrAddrTERMINATE: terminate_csr;
|
|
csrAddrSTATS: stats_csr;
|
|
// Supervisor CSRs
|
|
csrAddrSSTATUS: sstatus_csr;
|
|
csrAddrSIE: sie_csr;
|
|
csrAddrSTVEC: scrToCsr(stcc_reg); // Only accessed by debugger. CPU accesses decoded into cspecialrw
|
|
csrAddrSCOUNTEREN: scounteren_csr;
|
|
csrAddrSSCRATCH: sscratch_csr;
|
|
csrAddrSEPC: scrToCsr(sepcc_reg[1]); // Only accessed by debugger. CPU accesses decoded into cspecialrw
|
|
csrAddrSCAUSE: scause_csr;
|
|
csrAddrSTVAL: stval_csr;
|
|
csrAddrSIP: sip_csr;
|
|
csrAddrSATP: satp_csr;
|
|
// Machine CSRs
|
|
csrAddrMSTATUS: mstatus_csr;
|
|
csrAddrMISA: misa_csr;
|
|
csrAddrMEDELEG: medeleg_csr;
|
|
csrAddrMIDELEG: mideleg_csr;
|
|
csrAddrMIE: mie_csr;
|
|
csrAddrMTVEC: scrToCsr(mtcc_reg); // Only accessed by debugger. CPU accesses decoded into cspecialrw
|
|
csrAddrMCOUNTEREN: mcounteren_csr;
|
|
csrAddrMSCRATCH: mscratch_csr;
|
|
csrAddrMEPC: scrToCsr(mepcc_reg[1]); // Only accessed by debugger. CPU accesses decoded into cspecialrw
|
|
csrAddrMCAUSE: mcause_csr;
|
|
csrAddrMTVAL: mtval_csr;
|
|
csrAddrMIP: mip_csr;
|
|
csrAddrMCYCLE: mcycle_csr;
|
|
csrAddrMINSTRET: minstret_csr;
|
|
csrAddrMVENDORID: mvendorid_csr;
|
|
csrAddrMARCHID: marchid_csr;
|
|
csrAddrMIMPID: mimpid_csr;
|
|
csrAddrMHARTID: mhartid_csr;
|
|
csrAddrMCCSR: csr_capcause(mccsr_reg);
|
|
`ifdef SECURITY
|
|
csrAddrMEVBASE: mevbase_csr;
|
|
csrAddrMEVMASK: mevmask_csr;
|
|
csrAddrMEATP: meatp_csr;
|
|
csrAddrMMRBM: mmrbm_csr;
|
|
csrAddrMEMRBM: memrbm_csr;
|
|
csrAddrMPARBASE: mparbase_csr;
|
|
csrAddrMPARMASK: mparmask_csr;
|
|
csrAddrMEPARBASE: meparbase_csr;
|
|
csrAddrMEPARMASK: meparmask_csr;
|
|
csrAddrMSPEC: mspec_csr;
|
|
csrAddrTRNG: trng_csr;
|
|
`endif
|
|
|
|
csrAddrTSELECT: rg_tselect;
|
|
csrAddrTDATA1: rg_tdata1;
|
|
csrAddrTDATA2: rg_tdata2;
|
|
csrAddrTDATA3: rg_tdata3;
|
|
|
|
`ifdef INCLUDE_GDB_CONTROL
|
|
csrAddrDCSR: rg_dcsr; // TODO: take NMI into account (cf. Piccolo/Flute)
|
|
csrAddrDPC: scrToCsr(rg_dpc);
|
|
csrAddrDSCRATCH0: rg_dscratch0;
|
|
csrAddrDSCRATCH1: rg_dscratch1;
|
|
`endif
|
|
|
|
default: readOnlyReg(64'b0);
|
|
endcase);
|
|
endfunction
|
|
|
|
// Function for getting a csr given an index
|
|
function Reg#(CapReg) get_scr(SCR scr);
|
|
return (case (scr)
|
|
// User SCRs
|
|
scrAddrDDC: ddc_reg;
|
|
// User CSRs with accessSysRegs
|
|
// scrAddrUTCC: utcc_reg;
|
|
// scrAddrUTDC: utdc_reg;
|
|
// scrAddrUScratchC: uScratchC_reg;
|
|
// scrAddrUEPCC: uepcc_reg;
|
|
// System CSRs with accessSysRegs
|
|
scrAddrSTCC: stcc_reg;
|
|
scrAddrSTDC: stdc_reg;
|
|
scrAddrSScratchC: sScratchC_reg;
|
|
scrAddrSEPCC: sepcc_reg[1];
|
|
// Machine CSRs with accessSysRegs
|
|
scrAddrMTCC: mtcc_reg;
|
|
scrAddrMTDC: mtdc_reg;
|
|
scrAddrMScratchC: mScratchC_reg;
|
|
scrAddrMEPCC: mepcc_reg[1];
|
|
endcase);
|
|
endfunction
|
|
|
|
// ================================================================
|
|
// This function is the WARL (Write Any Read Legal) transform
|
|
// performed during CSR writes. Currently it duplicates the logic
|
|
// in the _write method of CSRs; ideally this function should be
|
|
// separate from the _write method, which should remain as an
|
|
// ordinary _write. The WARL'd value is needed for Tandem
|
|
// Verification.
|
|
|
|
function Data fv_warl_xform (CSR csr, Data x);
|
|
Asid x_asid = truncate (x [59:44]);
|
|
Bit #(16) asid = zeroExtend (x_asid);
|
|
return (
|
|
case (csr)
|
|
// Machine CSRs
|
|
csrAddrMISA: {getXLBits, 36'b0, getExtensionBits(isa)};
|
|
csrAddrMVENDORID: 0;
|
|
csrAddrMARCHID: 0;
|
|
csrAddrMIMPID: 0;
|
|
csrAddrMHARTID: hartid;
|
|
csrAddrMSTATUS: fn_mstatus_val (getXLBits, // sxl
|
|
getXLBits, // uxl
|
|
x [22], // tsr
|
|
x [21], // tw
|
|
x [20], // tvm
|
|
x [19], // mxr
|
|
x [18], // sum
|
|
x [17], // mprv
|
|
2'b0, // xs
|
|
((isa.f || isa.d) ? x [14:13] : 2'b0), // fs
|
|
x [12:11], // mpp
|
|
x [8], // spp
|
|
x [7], // prev_ie_vec[prvM]
|
|
x [5], // prev_ie_vec[prvS]
|
|
x [4], // prev_ie_vec[prvU]
|
|
x [3], // ie_vec[prvM]
|
|
x [1], // ie_vec[prvS]
|
|
x [0]); // ie_vec[prvU]
|
|
csrAddrMEDELEG: { 35'b0, x[28:26], 10'b0, x[15], 1'b0, x[13:12], x[11], 1'b0, x[9:0]};
|
|
csrAddrMIDELEG: { 52'b0, x[11], 1'b0, x[9:8], x[7], 1'b0, x[5:4], x[3], 1'b0, x[1:0]};
|
|
csrAddrMIP: ((mip_csr & (~ mip_mie_warl_mask)) | (x & mip_mie_warl_mask));
|
|
csrAddrMIE: (x & mip_mie_warl_mask);
|
|
csrAddrMCOUNTEREN: { 61'b0, x[2:0]};
|
|
csrAddrMCAUSE: { x[63], 59'b0, x[3:0] };
|
|
|
|
csrAddrTDATA1: { 4'b0, x [59:0] }; // Force tdata.type == 0 ("no trigger at this tselect")
|
|
|
|
// Supervisor level CSRs
|
|
csrAddrSSTATUS: fn_sstatus_val (getXLBits, // uxl
|
|
x [19], // mxr
|
|
x [18], // sum
|
|
2'b0, // xs
|
|
((isa.f || isa.d) ? x [14:13] : 2'b0), // fs
|
|
x [8], // spp
|
|
x [5], // prev_ie_vec[prvS]
|
|
x [4], // prev_ie_vec[prvU]
|
|
x [1], // ie_vec[prvS]
|
|
x [0]); // ie_vec[prvU]
|
|
csrAddrSIP: ((sip_csr & (~ sip_sie_warl_mask)) | (x & sip_sie_warl_mask));
|
|
csrAddrSIE: (x & sip_sie_warl_mask);
|
|
csrAddrSCOUNTEREN: { 61'b0, x[2:0]};
|
|
csrAddrSCAUSE: { x[63], 59'b0, x[3:0] };
|
|
csrAddrSATP: { x[63], 3'b0, asid, x [43:0] };
|
|
|
|
// User level CSRs
|
|
csrAddrFFLAGS: { 59'b0, x [4:0] };
|
|
csrAddrFRM: { 61'b0, x [2:0] };
|
|
csrAddrFCSR: { 56'b0, x [7:0] };
|
|
|
|
`ifdef INCLUDE_GDB_CONTROL
|
|
// Debug Mode CSRs
|
|
csrAddrDCSR: { 32'b0, x[31:28], 12'b0, x[14], 1'b0, x[13:6], 1'b0, x[4:0] };
|
|
`endif
|
|
|
|
default: x;
|
|
endcase);
|
|
endfunction
|
|
|
|
// ================================================================
|
|
// INTERFACE
|
|
|
|
method Data rd(CSR csr);
|
|
return get_csr(csr)._read;
|
|
endmethod
|
|
|
|
method CapReg scrRd(SCR scr);
|
|
return get_scr(scr)._read;
|
|
endmethod
|
|
|
|
method Action csrInstWr(CSR csr, Data x);
|
|
get_csr(csr)._write(x);
|
|
`ifdef INCLUDE_GDB_CONTROL
|
|
if (csr == csrAddrDCSR) begin
|
|
let prv = x [1:0];
|
|
prv_reg <= prv;
|
|
end
|
|
`endif
|
|
endmethod
|
|
|
|
method Action scrInstWr(SCR csr, CapReg x);
|
|
get_scr(csr)._write(x);
|
|
endmethod
|
|
|
|
method Bool fpuInstNeedWr(Bit#(5) fflags, Bool fpu_dirty);
|
|
Bool fflags_change = (fflags & fflags_reg) != fflags;
|
|
// we need to set fs_reg as dirty in two cases
|
|
// 1. FP reg is written (i.e., fpu_dirty)
|
|
// 2. FP exception (i.e., fflags) is non-zero (try to match spike)
|
|
Bool need_set_dirty = fs_reg != 2'b11 && (fpu_dirty || fflags != 0);
|
|
return fflags_change || need_set_dirty;
|
|
endmethod
|
|
|
|
method Action fpuInstWr(Bit#(5) fflags);
|
|
fs_reg <= 2'b11; // FPU must be dirty
|
|
fflags_reg <= fflags_reg | fflags;
|
|
endmethod
|
|
|
|
`ifdef INCLUDE_TANDEM_VERIF
|
|
method Tuple2 #(Bit #(5), Data) fpuInst_csr_updates (Bit #(5) fflags,
|
|
Bool init_for_way0,
|
|
Bit #(5) old_fflags,
|
|
Data old_mstatus);
|
|
|
|
// Note: old_fflags and old_mstatus are accumulated in
|
|
// sequential program order, and so may differ from fflags_reg
|
|
// and mstatus_csr, which only change after superscalar-wide
|
|
// retirement.
|
|
|
|
Bit #(5) old_fflags1 = (init_for_way0 ? fflags_reg : old_fflags);
|
|
Data old_mstatus1 = (init_for_way0 ? mstatus_csr : old_mstatus);
|
|
|
|
Bit #(5) new_fflags = (old_fflags1 | fflags);
|
|
Data new_mstatus = { 1'b1, old_mstatus1 [62:15], 2'b11, old_mstatus1 [12:0] };
|
|
|
|
return tuple2 (new_fflags, new_mstatus);
|
|
endmethod
|
|
|
|
method Data getMIP;
|
|
return mip_csr;
|
|
endmethod
|
|
`endif
|
|
|
|
method Data warl_xform (CSR csr, Data x);
|
|
return fv_warl_xform (csr, x);
|
|
endmethod
|
|
|
|
method Maybe#(Interrupt) pending_interrupt;
|
|
// first get all the pending interrupts
|
|
Bit#(InterruptNum) pend_ints = truncate(mie_csr & mip_csr);
|
|
// now find out all the truly enabled interrupts (that needs handling)
|
|
Bit#(InterruptNum) enabled_ints = 0;
|
|
// check interrupts that needs to be handled at M mode: all interrupts
|
|
// are by default handled at M mode unless it is delegated in
|
|
// mideleg_csr, we just need to ignore those interrupts
|
|
if(prv_reg < prvM || (prv_reg == prvM && ie_vec[prvM] == 1)) begin
|
|
enabled_ints = pend_ints & ~truncate(mideleg_csr);
|
|
end
|
|
// check interrupts that needs to be handled at S mode only if no
|
|
// interrupt needs to be handled at M mode: interrupts handled at S
|
|
// mode must be delegated in mideleg_csr
|
|
if (enabled_ints == 0 &&
|
|
(prv_reg < prvS || (prv_reg == prvS && ie_vec[prvS] == 1))) begin
|
|
enabled_ints = pend_ints & truncate(mideleg_csr);
|
|
end
|
|
// According to spike, return the interrupt bit at LSB
|
|
function Bool isEnabled(Integer i) = (enabled_ints[i] == 1);
|
|
Vector#(InterruptNum, Integer) idxVec = genVector;
|
|
if(find(isEnabled, idxVec) matches tagged Valid .i) begin
|
|
return Valid (unpack(fromInteger(i)));
|
|
end
|
|
else begin
|
|
return Invalid;
|
|
end
|
|
endmethod
|
|
|
|
method ActionValue#(Trap_Updates) trap(Trap t, CapPipe pcc, Addr addr, Bit #(32) orig_inst);
|
|
// figure out trap cause & trap val
|
|
Bit#(1) cause_interrupt = 0;
|
|
Cause cause_code = 0;
|
|
Data trap_val = 0;
|
|
case(t) matches
|
|
tagged Exception .e: begin
|
|
cause_code = pack(e);
|
|
trap_val = (case(e)
|
|
excIllegalInst: zeroExtend (orig_inst);
|
|
excInstAddrMisaligned, excBreakpoint: return getOffset(pcc); // TODO do we want getAddr?
|
|
|
|
excInstAccessFault, excInstPageFault,
|
|
excLoadAddrMisaligned, excLoadAccessFault,
|
|
excStoreAddrMisaligned, excStoreAccessFault,
|
|
excLoadPageFault, excStorePageFault: return addr;
|
|
|
|
default: return 0;
|
|
endcase);
|
|
end
|
|
tagged CapException .ce: begin
|
|
cause_code = pack(excCHERIFault);
|
|
trap_val = zeroExtend({pack(ce.cheri_exc_reg), pack(ce.cheri_exc_code)});
|
|
end
|
|
tagged Interrupt .i: begin
|
|
cause_code = zeroExtend(pack(i));
|
|
cause_interrupt = 1;
|
|
end
|
|
endcase
|
|
// function to figure out next PC
|
|
function CapPipe getNextPcc(CapPipe tcc);
|
|
let tvec = getAddr(tcc); // Note this is not actually mtcc: addr rather than offset
|
|
let mode_low = tvec[0]; // Valid because bottom 2 bits of base must be zero (enforced on write)
|
|
// tvec[1] must be 1 here.
|
|
let base_hi = tvec[63:2];
|
|
Addr base = {base_hi, 2'b0};
|
|
if(mode_low == 1 && cause_interrupt == 1) begin
|
|
// vector jump: only for interrupt
|
|
return setAddr(tcc, base + zeroExtend({cause_code, 2'b0})).value;
|
|
end
|
|
else begin // direct jump
|
|
return setAddr(tcc, base).value;
|
|
end
|
|
endfunction
|
|
// check if trap is delegated
|
|
Bool deleg = prv_reg <= prvS && (case(t) matches
|
|
tagged Exception .e: return medeleg_csr[pack(e)] == 1;
|
|
tagged CapException .ce: return medeleg_csr[pack(excCHERIFault)] == 1;
|
|
tagged Interrupt .i: return mideleg_csr[pack(i)] == 1;
|
|
endcase);
|
|
// handle the trap
|
|
if(deleg) begin // handle in S mode
|
|
// ie/prv stack
|
|
prev_prv_vec[prvS] <= prv_reg;
|
|
prv_reg <= prvS;
|
|
prev_ie_vec[prvS] <= ie_vec[prvS];
|
|
ie_vec[prvS] <= 0;
|
|
// record trap info
|
|
sepcc_reg[0] <= cast(pcc);
|
|
scause_interrupt_reg <= cause_interrupt;
|
|
scause_code_reg <= cause_code;
|
|
stval_csr <= trap_val;
|
|
// return next pc
|
|
Data sstatus_val = fn_sstatus_val (uxl_reg,
|
|
mxr_reg, sum_reg,
|
|
xs_reg, fs_reg,
|
|
/* spp_reg */ prv_reg [0],
|
|
/* prev_ie_vec_[prvS] */ ie_vec[prvS],
|
|
prev_ie_vec [prvU],
|
|
/* ie_vec [prvS] */ 0,
|
|
ie_vec [prvU]);
|
|
Data scause_val = fn_scause_val (cause_interrupt, cause_code);
|
|
return Trap_Updates {new_pcc: getNextPcc(cast(stcc_reg))
|
|
`ifdef INCLUDE_TANDEM_VERIF
|
|
, prv: prvS,
|
|
status: sstatus_val,
|
|
cause: scause_val,
|
|
epcc: pcc,
|
|
tval: trap_val
|
|
`endif
|
|
};
|
|
end
|
|
else begin
|
|
// ie/prv stack
|
|
prev_prv_vec[prvM] <= prv_reg;
|
|
prv_reg <= prvM;
|
|
prev_ie_vec[prvM] <= ie_vec[prvM];
|
|
ie_vec[prvM] <= 0;
|
|
// record trap info
|
|
mepcc_reg[0] <= cast(pcc);
|
|
mcause_interrupt_reg <= cause_interrupt;
|
|
mcause_code_reg <= cause_code;
|
|
mtval_csr <= trap_val;
|
|
// return next pc
|
|
Data mstatus_val = fn_mstatus_val (sxl_reg, uxl_reg,
|
|
tsr_reg, tw_reg, tvm_reg,
|
|
mxr_reg, sum_reg, mprv_reg,
|
|
xs_reg, fs_reg,
|
|
/* mpp */ prv_reg, spp_reg,
|
|
/* prev_ie_vec [prvM] */ ie_vec [prvM],
|
|
prev_ie_vec [prvS],
|
|
prev_ie_vec [prvU],
|
|
/* ie_vec [prvM] */ 0,
|
|
ie_vec [prvS],
|
|
ie_vec [prvU]);
|
|
Data mcause_val = fn_mcause_val (cause_interrupt, cause_code);
|
|
return Trap_Updates {new_pcc: getNextPcc(cast(mtcc_reg))
|
|
`ifdef INCLUDE_TANDEM_VERIF
|
|
, prv: prvM,
|
|
status: mstatus_val,
|
|
cause: mcause_val,
|
|
epcc: pcc,
|
|
tval: trap_val
|
|
`endif
|
|
};
|
|
end
|
|
// XXX yield load reservation should be done outside this method
|
|
endmethod
|
|
|
|
method ActionValue#(RET_Updates) mret;
|
|
prv_reg <= prev_prv_vec[prvM];
|
|
prev_prv_vec[prvM] <= prvU;
|
|
ie_vec[prvM] <= prev_ie_vec[prvM];
|
|
prev_ie_vec[prvM] <= 1;
|
|
|
|
Data mstatus_val = fn_mstatus_val(sxl_reg, uxl_reg,
|
|
tsr_reg, tw_reg, tvm_reg,
|
|
mxr_reg, sum_reg, mprv_reg,
|
|
xs_reg, fs_reg,
|
|
/* mpp */ prvU,
|
|
spp_reg,
|
|
/* prev_ie_vec [prvM] */ 1,
|
|
prev_ie_vec [prvS],
|
|
prev_ie_vec [prvU],
|
|
/* ie_vec [prvM] */ prev_ie_vec[prvM],
|
|
ie_vec [prvS],
|
|
ie_vec [prvU]);
|
|
return RET_Updates {new_pcc: cast(setKind(mepcc_reg[0], getKind(mepcc_reg[0]) == SENTRY ? UNSEALED : getKind(mepcc_reg[0])))
|
|
`ifdef INCLUDE_TANDEM_VERIF
|
|
, prv: prev_prv_vec[prvM],
|
|
status: mstatus_val
|
|
`endif
|
|
};
|
|
endmethod
|
|
|
|
method ActionValue#(RET_Updates) sret;
|
|
prv_reg <= prev_prv_vec[prvS];
|
|
prev_prv_vec[prvS] <= prvU;
|
|
ie_vec[prvS] <= prev_ie_vec[prvS];
|
|
prev_ie_vec[prvS] <= 1;
|
|
|
|
// For Tandem Verification, we return the full underlying MSTATUS register
|
|
Data mstatus_val = fn_mstatus_val(sxl_reg, uxl_reg,
|
|
tsr_reg, tw_reg, tvm_reg,
|
|
mxr_reg, sum_reg, mprv_reg,
|
|
xs_reg, fs_reg,
|
|
mpp_reg,
|
|
/* spp_reg */ prvU [0],
|
|
|
|
prev_ie_vec [prvM],
|
|
/* prev_ie_vec_[prvS] */ 1,
|
|
prev_ie_vec [prvU],
|
|
|
|
ie_vec [prvM],
|
|
/* ie_vec [prvS] */ prev_ie_vec[prvS],
|
|
ie_vec [prvU]);
|
|
return RET_Updates {new_pcc: cast(setKind(sepcc_reg[0], getKind(sepcc_reg[0]) == SENTRY ? UNSEALED : getKind(sepcc_reg[0])))
|
|
`ifdef INCLUDE_TANDEM_VERIF
|
|
, prv: prev_prv_vec[prvS],
|
|
status: mstatus_val
|
|
`endif
|
|
};
|
|
endmethod
|
|
|
|
method VMInfo vmI;
|
|
// for inst fetch, NO need to consider MPRV
|
|
Bit#(2) prv = prv_reg;
|
|
return VMInfo {
|
|
prv: prv,
|
|
asid: asid_reg,
|
|
sv39: prv < prvM && vm_mode_sv39_reg == 1,
|
|
exeReadable: mxr_reg == 1,
|
|
userAccessibleByS: sum_reg == 1,
|
|
basePPN: ppn_reg
|
|
`ifdef SECURITY
|
|
, sanctum_evbase: mevbase_csr,
|
|
sanctum_evmask: mevmask_csr,
|
|
sanctum_ebasePPN: eppn_reg,
|
|
sanctum_mrbm: mmrbm_csr,
|
|
sanctum_emrbm: memrbm_csr,
|
|
sanctum_parbase: mparbase_csr,
|
|
sanctum_parmask: mparmask_csr,
|
|
sanctum_eparbase: meparbase_csr,
|
|
sanctum_eparmask: meparmask_csr,
|
|
// enclave / security monitor should never execute instructions
|
|
// from untrusted shared region
|
|
sanctum_authShared: False
|
|
`endif
|
|
};
|
|
endmethod
|
|
|
|
method VMInfo vmD;
|
|
// for load/store, need to consider MPRV
|
|
Bit#(2) prv = (mprv_reg == 1) ? prev_prv_vec[prvM] : prv_reg;
|
|
return VMInfo {
|
|
prv: prv,
|
|
asid: asid_reg,
|
|
sv39: prv < prvM && vm_mode_sv39_reg == 1,
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exeReadable: mxr_reg == 1,
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userAccessibleByS: sum_reg == 1,
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|
basePPN: ppn_reg
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|
`ifdef SECURITY
|
|
, sanctum_evbase: mevbase_csr,
|
|
sanctum_evmask: mevmask_csr,
|
|
sanctum_ebasePPN: eppn_reg,
|
|
sanctum_mrbm: mmrbm_csr,
|
|
sanctum_emrbm: memrbm_csr,
|
|
sanctum_parbase: mparbase_csr,
|
|
sanctum_parmask: mparmask_csr,
|
|
sanctum_eparbase: meparbase_csr,
|
|
sanctum_eparmask: meparmask_csr,
|
|
// enclave / security monitor can read/write untrusted shared
|
|
// region when speculation is off (either by mspec CSR or in M
|
|
// mode)
|
|
// XXX Because of the effects of mprv, we have to use prv_reg here
|
|
// instead of prv. Otherwise, we may be in M mode, but prv=S, and
|
|
// still forbid shared accesses
|
|
sanctum_authShared: mspec_reg != mSpecAll || prv_reg == prvM
|
|
`endif
|
|
};
|
|
endmethod
|
|
|
|
method CsrDecodeInfo decodeInfo = CsrDecodeInfo {
|
|
frm: frm_reg,
|
|
fEnabled: fs_reg != 0,
|
|
prv: prv_reg,
|
|
trapVM: tvm_reg == 1,
|
|
timeoutWait: tw_reg == 1,
|
|
trapSret: tsr_reg == 1,
|
|
cycleReadableByS: mcounteren_cy_reg == 1,
|
|
cycleReadableByU: mcounteren_cy_reg == 1 && scounteren_cy_reg == 1,
|
|
instretReadableByS: mcounteren_ir_reg == 1,
|
|
instretReadableByU: mcounteren_ir_reg == 1 && scounteren_ir_reg == 1,
|
|
timeReadableByS: mcounteren_tm_reg == 1,
|
|
timeReadableByU: mcounteren_tm_reg == 1 && scounteren_tm_reg == 1
|
|
};
|
|
|
|
method Action incInstret(SupCnt x);
|
|
minstret_ehr[1] <= minstret_ehr[1] + zeroExtend(x);
|
|
endmethod
|
|
|
|
method Action setTime(Data t);
|
|
time_reg <= t;
|
|
endmethod
|
|
|
|
method getMSIP = software_int_pend_vec[prvM]._read;
|
|
method setMSIP = software_int_pend_vec[prvM]._write;
|
|
method setMTIP = timer_int_pend_vec[prvM]._write;
|
|
|
|
// Bluespec: external interrupts targeting machine and supervisor modes
|
|
method Action setMEIP (Bit #(1) v);
|
|
external_int_pend_vec[prvM] <= v;
|
|
endmethod
|
|
|
|
method Action setSEIP (Bit #(1) v);
|
|
external_int_pend_vec[prvS] <= v;
|
|
endmethod
|
|
|
|
method terminate = terminate_module.terminate;
|
|
|
|
// performance stats
|
|
method doPerfStats = stats_module.doPerfStats;
|
|
method sendDoStats = stats_module.sendDoStats;
|
|
method recvDoStats = stats_module.recvDoStats;
|
|
|
|
// ----------------
|
|
// Bluespec:
|
|
// Methods when Debug Module is present
|
|
|
|
`ifdef INCLUDE_GDB_CONTROL
|
|
// Read dpc
|
|
method CapReg dpc_read ();
|
|
return rg_dpc;
|
|
endmethod
|
|
|
|
// Update dpc
|
|
method Action dpc_write (CapReg pc);
|
|
rg_dpc <= pc;
|
|
endmethod
|
|
|
|
// Check whether to enter Debug Mode based on dcsr.{ebreakm, ebreaks, ebreaku}
|
|
method Bit #(1) dcsr_break_bit;
|
|
return case (prv_reg)
|
|
prvM: rg_dcsr [15];
|
|
prvS: rg_dcsr [13];
|
|
prvU: rg_dcsr [12];
|
|
endcase;
|
|
endmethod
|
|
|
|
// Check whether to enter Debug Mode based on dcsr.step
|
|
method Bit #(1) dcsr_step_bit;
|
|
return rg_dcsr [2];
|
|
endmethod
|
|
|
|
// Update 'cause' in DCSR
|
|
// Is invoked by logic that stops a hart, to enter Debug Mode
|
|
method Action dcsr_cause_write (Bit #(3) dcsr_cause);
|
|
rg_dcsr <= { 32'b0, rg_dcsr [31:9], dcsr_cause, rg_dcsr [5:2], prv_reg };
|
|
|
|
/*
|
|
$display ("%0d: %m mkCsrFile.method-dcsr_cause_write: cause %0d, prv %0d",
|
|
cur_cycle, dcsr_cause, prv_reg);
|
|
*/
|
|
endmethod
|
|
|
|
`endif
|
|
|
|
endmodule
|