Files
Toooba/src_SSITH_P3/Verilog_RTL_sim/module_capChecks.v
2020-07-16 19:35:51 +01:00

304 lines
13 KiB
Verilog

//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Thu Jul 16 18:14:59 BST 2020
//
//
// Ports:
// Name I/O size props
// capChecks O 12
// capChecks_a I 163
// capChecks_b I 163
// capChecks_ddc I 163
// capChecks_toCheck I 47
// capChecks_cap_exact I 1
//
// Combinational paths from inputs to outputs:
// (capChecks_a,
// capChecks_b,
// capChecks_ddc,
// capChecks_toCheck,
// capChecks_cap_exact) -> capChecks
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_capChecks(capChecks_a,
capChecks_b,
capChecks_ddc,
capChecks_toCheck,
capChecks_cap_exact,
capChecks);
// value method capChecks
input [162 : 0] capChecks_a;
input [162 : 0] capChecks_b;
input [162 : 0] capChecks_ddc;
input [46 : 0] capChecks_toCheck;
input capChecks_cap_exact;
output [11 : 0] capChecks;
// signals for module outputs
wire [11 : 0] capChecks;
// remaining internal signals
wire [10 : 0] IF_capChecks_toCheck_BIT_46_AND_NOT_capChecks__ETC___d296;
wire [5 : 0] IF_capChecks_toCheck_BIT_34_9_AND_NOT_capCheck_ETC___d263,
IF_capChecks_toCheck_BIT_41_3_AND_capChecks_dd_ETC___d270,
IF_capChecks_toCheck_BIT_42_4_AND_capChecks_b__ETC___d266,
IF_capChecks_toCheck_BIT_43_7_AND_capChecks_a__ETC___d267,
IF_capChecks_toCheck_BIT_45_AND_NOT_capChecks__ETC___d272;
wire [4 : 0] IF_capChecks_toCheck_BIT_29_9_AND_NOT_capCheck_ETC___d287,
IF_capChecks_toCheck_BIT_30_4_AND_NOT_capCheck_ETC___d288,
IF_capChecks_toCheck_BIT_32_6_AND_NOT_capCheck_ETC___d290,
IF_capChecks_toCheck_BIT_34_9_AND_NOT_capCheck_ETC___d291,
IF_capChecks_toCheck_BIT_36_1_AND_NOT_capCheck_ETC___d292,
IF_capChecks_toCheck_BIT_41_3_AND_capChecks_dd_ETC___d294;
wire _0_CONCAT_capChecks_a_BITS_81_TO_78_4_AND_capCh_ETC___d102,
capChecks_toCheck_BIT_26_05_AND_NOT_capChecks__ETC___d125,
capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d146,
capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d254,
capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d281,
capChecks_toCheck_BIT_29_9_AND_NOT_capChecks_b_ETC___d137,
capChecks_toCheck_BIT_30_4_AND_NOT_capChecks_b_ETC___d138,
capChecks_toCheck_BIT_30_4_AND_NOT_capChecks_b_ETC___d256,
capChecks_toCheck_BIT_35_5_AND_NOT_capChecks_b_ETC___d143,
capChecks_toCheck_BIT_37_7_AND_NOT_capChecks_a_ETC___d145,
capChecks_toCheck_BIT_39_5_AND_capChecks_a_BIT_ETC___d150,
capChecks_toCheck_BIT_39_5_AND_capChecks_a_BIT_ETC___d278,
capChecks_toCheck_BIT_41_3_AND_capChecks_ddc_B_ETC___d152,
capChecks_toCheck_BIT_41_3_AND_capChecks_ddc_B_ETC___d280,
capChecks_toCheck_BIT_43_7_AND_capChecks_a_BIT_ETC___d148,
capChecks_toCheck_BIT_43_7_AND_capChecks_a_BIT_ETC___d276;
// value method capChecks
assign capChecks =
{ capChecks_toCheck[46] && !capChecks_ddc[162] ||
capChecks_toCheck[45] && !capChecks_a[162] ||
capChecks_toCheck[44] && !capChecks_b[162] ||
capChecks_toCheck_BIT_41_3_AND_capChecks_ddc_B_ETC___d152,
IF_capChecks_toCheck_BIT_46_AND_NOT_capChecks__ETC___d296 } ;
// remaining internal signals
assign IF_capChecks_toCheck_BIT_29_9_AND_NOT_capCheck_ETC___d287 =
(capChecks_toCheck[29] && capChecks_b[159:96] > 64'd262139) ?
5'd1 :
((capChecks_toCheck[27] &&
!_0_CONCAT_capChecks_a_BITS_81_TO_78_4_AND_capCh_ETC___d102) ?
5'd8 :
(capChecks_toCheck_BIT_26_05_AND_NOT_capChecks__ETC___d125 ?
5'd1 :
((capChecks_toCheck[25] &&
capChecks_toCheck[11:6] != 6'd0) ?
5'd24 :
5'd10))) ;
assign IF_capChecks_toCheck_BIT_30_4_AND_NOT_capCheck_ETC___d288 =
(capChecks_toCheck[30] &&
capChecks_b[159:96] != { 46'd0, capChecks_a[62:45] }) ?
5'd4 :
IF_capChecks_toCheck_BIT_29_9_AND_NOT_capCheck_ETC___d287 ;
assign IF_capChecks_toCheck_BIT_32_6_AND_NOT_capCheck_ETC___d290 =
(capChecks_toCheck[32] && !capChecks_b[75]) ?
5'd26 :
((capChecks_toCheck[31] && !capChecks_b[73]) ?
5'd23 :
IF_capChecks_toCheck_BIT_30_4_AND_NOT_capCheck_ETC___d288) ;
assign IF_capChecks_toCheck_BIT_34_9_AND_NOT_capCheck_ETC___d263 =
(capChecks_toCheck[34] && !capChecks_a[67]) ?
capChecks_toCheck[11:6] :
((capChecks_toCheck[33] && capChecks_b[67] ||
capChecks_toCheck[32] && !capChecks_b[75] ||
capChecks_toCheck[31] && !capChecks_b[73] ||
capChecks_toCheck_BIT_30_4_AND_NOT_capChecks_b_ETC___d256) ?
capChecks_toCheck[5:0] :
(capChecks_toCheck_BIT_26_05_AND_NOT_capChecks__ETC___d125 ?
capChecks_toCheck[11:6] :
((capChecks_toCheck[25] &&
capChecks_toCheck[11:6] != 6'd0) ?
6'd32 :
capChecks_toCheck[11:6]))) ;
assign IF_capChecks_toCheck_BIT_34_9_AND_NOT_capCheck_ETC___d291 =
(capChecks_toCheck[34] && !capChecks_a[67] ||
capChecks_toCheck[33] && capChecks_b[67]) ?
5'd17 :
IF_capChecks_toCheck_BIT_32_6_AND_NOT_capCheck_ETC___d290 ;
assign IF_capChecks_toCheck_BIT_36_1_AND_NOT_capCheck_ETC___d292 =
(capChecks_toCheck[36] && !capChecks_a[74] ||
capChecks_toCheck[35] && !capChecks_b[74]) ?
5'd25 :
IF_capChecks_toCheck_BIT_34_9_AND_NOT_capCheck_ETC___d291 ;
assign IF_capChecks_toCheck_BIT_41_3_AND_capChecks_dd_ETC___d270 =
(capChecks_toCheck[41] && capChecks_ddc[162] &&
capChecks_ddc[62:45] != 18'd262143) ?
6'b100001 :
((capChecks_toCheck[40] && capChecks_a[162] &&
capChecks_a[62:45] != 18'd262143 ||
capChecks_toCheck[39] && capChecks_a[162] &&
capChecks_a[62:45] != 18'd262143 &&
capChecks_a[62:45] != 18'd262142) ?
capChecks_toCheck[11:6] :
((capChecks_toCheck[38] && capChecks_b[162] &&
capChecks_b[62:45] != 18'd262143) ?
capChecks_toCheck[5:0] :
IF_capChecks_toCheck_BIT_43_7_AND_capChecks_a__ETC___d267)) ;
assign IF_capChecks_toCheck_BIT_41_3_AND_capChecks_dd_ETC___d294 =
capChecks_toCheck_BIT_41_3_AND_capChecks_ddc_B_ETC___d280 ?
5'd3 :
(capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d281 ?
5'd4 :
IF_capChecks_toCheck_BIT_36_1_AND_NOT_capCheck_ETC___d292) ;
assign IF_capChecks_toCheck_BIT_42_4_AND_capChecks_b__ETC___d266 =
(capChecks_toCheck[42] &&
(capChecks_b[62:45] == 18'd262143 ||
capChecks_b[62:45] == 18'd262142 ||
capChecks_b[62:45] == 18'd262141 ||
capChecks_b[62:45] == 18'd262140)) ?
capChecks_toCheck[5:0] :
(capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d254 ?
capChecks_toCheck[11:6] :
((capChecks_toCheck[35] && !capChecks_b[74]) ?
capChecks_toCheck[5:0] :
IF_capChecks_toCheck_BIT_34_9_AND_NOT_capCheck_ETC___d263)) ;
assign IF_capChecks_toCheck_BIT_43_7_AND_capChecks_a__ETC___d267 =
(capChecks_toCheck[43] &&
(capChecks_a[62:45] == 18'd262143 ||
capChecks_a[62:45] == 18'd262142 ||
capChecks_a[62:45] == 18'd262141 ||
capChecks_a[62:45] == 18'd262140)) ?
capChecks_toCheck[11:6] :
IF_capChecks_toCheck_BIT_42_4_AND_capChecks_b__ETC___d266 ;
assign IF_capChecks_toCheck_BIT_45_AND_NOT_capChecks__ETC___d272 =
(capChecks_toCheck[45] && !capChecks_a[162]) ?
capChecks_toCheck[11:6] :
((capChecks_toCheck[44] && !capChecks_b[162]) ?
capChecks_toCheck[5:0] :
IF_capChecks_toCheck_BIT_41_3_AND_capChecks_dd_ETC___d270) ;
assign IF_capChecks_toCheck_BIT_46_AND_NOT_capChecks__ETC___d296 =
{ (capChecks_toCheck[46] && !capChecks_ddc[162]) ?
6'b100001 :
IF_capChecks_toCheck_BIT_45_AND_NOT_capChecks__ETC___d272,
(capChecks_toCheck[46] && !capChecks_ddc[162] ||
capChecks_toCheck[45] && !capChecks_a[162] ||
capChecks_toCheck[44] && !capChecks_b[162]) ?
5'd2 :
IF_capChecks_toCheck_BIT_41_3_AND_capChecks_dd_ETC___d294 } ;
assign _0_CONCAT_capChecks_a_BITS_81_TO_78_4_AND_capCh_ETC___d102 =
{ 12'd0,
capChecks_a[81:78] & capChecks_b[81:78],
3'd0,
capChecks_a[77:66] & capChecks_b[77:66] } ==
{ 12'd0, capChecks_a[81:78], 3'h0, capChecks_a[77:66] } ;
assign capChecks_toCheck_BIT_26_05_AND_NOT_capChecks__ETC___d125 =
capChecks_toCheck[26] &&
(capChecks_a[43:38] > 6'd52 ||
capChecks_a[43:38] == 6'd52 &&
(capChecks_a[37] || capChecks_a[23:22] != 2'b0) ||
capChecks_a[43:38] == 6'd51 && capChecks_a[23] ||
capChecks_a[64:63] != 2'd0) ;
assign capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d146 =
capChecks_toCheck[28] &&
{ 46'd0, capChecks_a[62:45] } > 64'd262139 ||
capChecks_toCheck_BIT_37_7_AND_NOT_capChecks_a_ETC___d145 ;
assign capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d254 =
capChecks_toCheck[28] &&
{ 46'd0, capChecks_a[62:45] } > 64'd262139 ||
capChecks_toCheck[37] &&
capChecks_a[62:45] != capChecks_b[62:45] ||
capChecks_toCheck[36] && !capChecks_a[74] ;
assign capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d281 =
capChecks_toCheck[28] &&
{ 46'd0, capChecks_a[62:45] } > 64'd262139 ||
capChecks_toCheck[37] &&
capChecks_a[62:45] != capChecks_b[62:45] ;
assign capChecks_toCheck_BIT_29_9_AND_NOT_capChecks_b_ETC___d137 =
capChecks_toCheck[29] && capChecks_b[159:96] > 64'd262139 ||
capChecks_toCheck[27] &&
!_0_CONCAT_capChecks_a_BITS_81_TO_78_4_AND_capCh_ETC___d102 ||
capChecks_toCheck_BIT_26_05_AND_NOT_capChecks__ETC___d125 ||
capChecks_toCheck[25] && capChecks_toCheck[11:6] != 6'd0 ||
capChecks_toCheck[22] && !capChecks_cap_exact ;
assign capChecks_toCheck_BIT_30_4_AND_NOT_capChecks_b_ETC___d138 =
capChecks_toCheck[30] &&
capChecks_b[159:96] != { 46'd0, capChecks_a[62:45] } ||
capChecks_toCheck_BIT_29_9_AND_NOT_capChecks_b_ETC___d137 ;
assign capChecks_toCheck_BIT_30_4_AND_NOT_capChecks_b_ETC___d256 =
capChecks_toCheck[30] &&
capChecks_b[159:96] != { 46'd0, capChecks_a[62:45] } ||
capChecks_toCheck[29] && capChecks_b[159:96] > 64'd262139 ||
capChecks_toCheck[27] &&
!_0_CONCAT_capChecks_a_BITS_81_TO_78_4_AND_capCh_ETC___d102 ;
assign capChecks_toCheck_BIT_35_5_AND_NOT_capChecks_b_ETC___d143 =
capChecks_toCheck[35] && !capChecks_b[74] ||
capChecks_toCheck[34] && !capChecks_a[67] ||
capChecks_toCheck[33] && capChecks_b[67] ||
capChecks_toCheck[32] && !capChecks_b[75] ||
capChecks_toCheck[31] && !capChecks_b[73] ||
capChecks_toCheck_BIT_30_4_AND_NOT_capChecks_b_ETC___d138 ;
assign capChecks_toCheck_BIT_37_7_AND_NOT_capChecks_a_ETC___d145 =
capChecks_toCheck[37] &&
capChecks_a[62:45] != capChecks_b[62:45] ||
capChecks_toCheck[36] && !capChecks_a[74] ||
capChecks_toCheck_BIT_35_5_AND_NOT_capChecks_b_ETC___d143 ;
assign capChecks_toCheck_BIT_39_5_AND_capChecks_a_BIT_ETC___d150 =
capChecks_toCheck[39] && capChecks_a[162] &&
capChecks_a[62:45] != 18'd262143 &&
capChecks_a[62:45] != 18'd262142 ||
capChecks_toCheck[38] && capChecks_b[162] &&
capChecks_b[62:45] != 18'd262143 ||
capChecks_toCheck_BIT_43_7_AND_capChecks_a_BIT_ETC___d148 ;
assign capChecks_toCheck_BIT_39_5_AND_capChecks_a_BIT_ETC___d278 =
capChecks_toCheck[39] && capChecks_a[162] &&
capChecks_a[62:45] != 18'd262143 &&
capChecks_a[62:45] != 18'd262142 ||
capChecks_toCheck[38] && capChecks_b[162] &&
capChecks_b[62:45] != 18'd262143 ||
capChecks_toCheck_BIT_43_7_AND_capChecks_a_BIT_ETC___d276 ;
assign capChecks_toCheck_BIT_41_3_AND_capChecks_ddc_B_ETC___d152 =
capChecks_toCheck[41] && capChecks_ddc[162] &&
capChecks_ddc[62:45] != 18'd262143 ||
capChecks_toCheck[40] && capChecks_a[162] &&
capChecks_a[62:45] != 18'd262143 ||
capChecks_toCheck_BIT_39_5_AND_capChecks_a_BIT_ETC___d150 ;
assign capChecks_toCheck_BIT_41_3_AND_capChecks_ddc_B_ETC___d280 =
capChecks_toCheck[41] && capChecks_ddc[162] &&
capChecks_ddc[62:45] != 18'd262143 ||
capChecks_toCheck[40] && capChecks_a[162] &&
capChecks_a[62:45] != 18'd262143 ||
capChecks_toCheck_BIT_39_5_AND_capChecks_a_BIT_ETC___d278 ;
assign capChecks_toCheck_BIT_43_7_AND_capChecks_a_BIT_ETC___d148 =
capChecks_toCheck[43] &&
(capChecks_a[62:45] == 18'd262143 ||
capChecks_a[62:45] == 18'd262142 ||
capChecks_a[62:45] == 18'd262141 ||
capChecks_a[62:45] == 18'd262140) ||
capChecks_toCheck[42] &&
(capChecks_b[62:45] == 18'd262143 ||
capChecks_b[62:45] == 18'd262142 ||
capChecks_b[62:45] == 18'd262141 ||
capChecks_b[62:45] == 18'd262140) ||
capChecks_toCheck_BIT_28_2_AND_NOT_0_CONCAT_ca_ETC___d146 ;
assign capChecks_toCheck_BIT_43_7_AND_capChecks_a_BIT_ETC___d276 =
capChecks_toCheck[43] &&
(capChecks_a[62:45] == 18'd262143 ||
capChecks_a[62:45] == 18'd262142 ||
capChecks_a[62:45] == 18'd262141 ||
capChecks_a[62:45] == 18'd262140) ||
capChecks_toCheck[42] &&
(capChecks_b[62:45] == 18'd262143 ||
capChecks_b[62:45] == 18'd262142 ||
capChecks_b[62:45] == 18'd262141 ||
capChecks_b[62:45] == 18'd262140) ;
endmodule // module_capChecks