36938 lines
1.6 MiB
36938 lines
1.6 MiB
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_coreReq_start O 1 const
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// RDY_coreReq_perfReq O 1 reg
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// coreIndInv_perfResp O 73
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// RDY_coreIndInv_perfResp O 1 reg
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// RDY_coreIndInv_terminate O 1 reg
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// dCacheToParent_rsToP_notEmpty O 1
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// RDY_dCacheToParent_rsToP_notEmpty O 1 const
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// RDY_dCacheToParent_rsToP_deq O 1
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// dCacheToParent_rsToP_first O 579
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// RDY_dCacheToParent_rsToP_first O 1
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// dCacheToParent_rqToP_notEmpty O 1
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// RDY_dCacheToParent_rqToP_notEmpty O 1 const
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// RDY_dCacheToParent_rqToP_deq O 1
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// dCacheToParent_rqToP_first O 72
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// RDY_dCacheToParent_rqToP_first O 1
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// dCacheToParent_fromP_notFull O 1
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// RDY_dCacheToParent_fromP_notFull O 1 const
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// RDY_dCacheToParent_fromP_enq O 1
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// iCacheToParent_rsToP_notEmpty O 1
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// RDY_iCacheToParent_rsToP_notEmpty O 1 const
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// RDY_iCacheToParent_rsToP_deq O 1
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// iCacheToParent_rsToP_first O 579
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// RDY_iCacheToParent_rsToP_first O 1
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// iCacheToParent_rqToP_notEmpty O 1
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// RDY_iCacheToParent_rqToP_notEmpty O 1 const
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// RDY_iCacheToParent_rqToP_deq O 1
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// iCacheToParent_rqToP_first O 72
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// RDY_iCacheToParent_rqToP_first O 1
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// iCacheToParent_fromP_notFull O 1
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// RDY_iCacheToParent_fromP_notFull O 1 const
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// RDY_iCacheToParent_fromP_enq O 1
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// tlbToMem_memReq_notEmpty O 1
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// RDY_tlbToMem_memReq_notEmpty O 1 const
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// RDY_tlbToMem_memReq_deq O 1
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// tlbToMem_memReq_first O 65
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// RDY_tlbToMem_memReq_first O 1
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// tlbToMem_respLd_notFull O 1
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// RDY_tlbToMem_respLd_notFull O 1 const
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// RDY_tlbToMem_respLd_enq O 1
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// mmioToPlatform_cRq_notEmpty O 1
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// RDY_mmioToPlatform_cRq_notEmpty O 1 const
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// RDY_mmioToPlatform_cRq_deq O 1
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// mmioToPlatform_cRq_first O 142
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// RDY_mmioToPlatform_cRq_first O 1
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// mmioToPlatform_pRs_notFull O 1
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// RDY_mmioToPlatform_pRs_notFull O 1 const
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// RDY_mmioToPlatform_pRs_enq O 1
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// mmioToPlatform_pRq_notFull O 1
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// RDY_mmioToPlatform_pRq_notFull O 1 const
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// RDY_mmioToPlatform_pRq_enq O 1
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// mmioToPlatform_cRs_notEmpty O 1
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// RDY_mmioToPlatform_cRs_notEmpty O 1 const
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// RDY_mmioToPlatform_cRs_deq O 1
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// mmioToPlatform_cRs_first O 1 reg
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// RDY_mmioToPlatform_cRs_first O 1
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// RDY_mmioToPlatform_setTime O 1 const
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// sendDoStats O 1 reg
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// RDY_sendDoStats O 1 reg
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// RDY_recvDoStats O 1 const
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// deadlock_dCacheCRqStuck_get O 73 const
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// RDY_deadlock_dCacheCRqStuck_get O 1 const
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// deadlock_dCachePRqStuck_get O 68 const
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// RDY_deadlock_dCachePRqStuck_get O 1 const
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// deadlock_iCacheCRqStuck_get O 68 const
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// RDY_deadlock_iCacheCRqStuck_get O 1 const
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// deadlock_iCachePRqStuck_get O 68 const
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// RDY_deadlock_iCachePRqStuck_get O 1 const
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// deadlock_renameInstStuck_get O 78 const
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// RDY_deadlock_renameInstStuck_get O 1 const
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// deadlock_renameCorrectPathStuck_get O 78 const
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// RDY_deadlock_renameCorrectPathStuck_get O 1 const
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// deadlock_commitInstStuck_get O 163 const
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// RDY_deadlock_commitInstStuck_get O 1 const
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// deadlock_commitUserInstStuck_get O 163 const
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// RDY_deadlock_commitUserInstStuck_get O 1 const
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// RDY_deadlock_checkStarted_get O 1 const
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// renameDebug_renameErr_get O 89 const
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// RDY_renameDebug_renameErr_get O 1 const
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// RDY_setMEIP O 1 const
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// RDY_setSEIP O 1 const
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// RDY_setDEIP O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// coreReq_start_startpc I 64
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// coreReq_start_toHostAddr I 64 reg
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// coreReq_start_fromHostAddr I 64 reg
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// coreReq_perfReq_loc I 4 reg
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// coreReq_perfReq_t I 5 reg
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// dCacheToParent_fromP_enq_x I 583
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// iCacheToParent_fromP_enq_x I 583
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// tlbToMem_respLd_enq_x I 65
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// mmioToPlatform_pRs_enq_x I 67
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// mmioToPlatform_pRq_enq_x I 39
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// mmioToPlatform_setTime_t I 64 reg
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// recvDoStats_x I 1 reg
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// setMEIP_v I 1
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// setSEIP_v I 1
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// setDEIP_v I 1
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// EN_coreReq_start I 1
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// EN_coreReq_perfReq I 1
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// EN_coreIndInv_terminate I 1
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// EN_dCacheToParent_rsToP_deq I 1
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// EN_dCacheToParent_rqToP_deq I 1
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// EN_dCacheToParent_fromP_enq I 1
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// EN_iCacheToParent_rsToP_deq I 1
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// EN_iCacheToParent_rqToP_deq I 1
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// EN_iCacheToParent_fromP_enq I 1
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// EN_tlbToMem_memReq_deq I 1
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// EN_tlbToMem_respLd_enq I 1
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// EN_mmioToPlatform_cRq_deq I 1
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// EN_mmioToPlatform_pRs_enq I 1
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// EN_mmioToPlatform_pRq_enq I 1
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// EN_mmioToPlatform_cRs_deq I 1
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// EN_mmioToPlatform_setTime I 1
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// EN_recvDoStats I 1
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// EN_deadlock_checkStarted_get I 1 unused
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// EN_setMEIP I 1
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// EN_setSEIP I 1
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// EN_setDEIP I 1
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// EN_coreIndInv_perfResp I 1
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// EN_sendDoStats I 1
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// EN_deadlock_dCacheCRqStuck_get I 1 unused
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// EN_deadlock_dCachePRqStuck_get I 1 unused
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// EN_deadlock_iCacheCRqStuck_get I 1 unused
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// EN_deadlock_iCachePRqStuck_get I 1 unused
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// EN_deadlock_renameInstStuck_get I 1 unused
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// EN_deadlock_renameCorrectPathStuck_get I 1 unused
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// EN_deadlock_commitInstStuck_get I 1 unused
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// EN_deadlock_commitUserInstStuck_get I 1 unused
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// EN_renameDebug_renameErr_get I 1 unused
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkCore(CLK,
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RST_N,
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coreReq_start_startpc,
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coreReq_start_toHostAddr,
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coreReq_start_fromHostAddr,
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EN_coreReq_start,
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RDY_coreReq_start,
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coreReq_perfReq_loc,
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coreReq_perfReq_t,
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EN_coreReq_perfReq,
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RDY_coreReq_perfReq,
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EN_coreIndInv_perfResp,
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coreIndInv_perfResp,
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RDY_coreIndInv_perfResp,
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EN_coreIndInv_terminate,
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RDY_coreIndInv_terminate,
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dCacheToParent_rsToP_notEmpty,
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RDY_dCacheToParent_rsToP_notEmpty,
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EN_dCacheToParent_rsToP_deq,
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RDY_dCacheToParent_rsToP_deq,
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dCacheToParent_rsToP_first,
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RDY_dCacheToParent_rsToP_first,
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dCacheToParent_rqToP_notEmpty,
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RDY_dCacheToParent_rqToP_notEmpty,
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EN_dCacheToParent_rqToP_deq,
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RDY_dCacheToParent_rqToP_deq,
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dCacheToParent_rqToP_first,
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RDY_dCacheToParent_rqToP_first,
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dCacheToParent_fromP_notFull,
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RDY_dCacheToParent_fromP_notFull,
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dCacheToParent_fromP_enq_x,
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EN_dCacheToParent_fromP_enq,
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RDY_dCacheToParent_fromP_enq,
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iCacheToParent_rsToP_notEmpty,
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RDY_iCacheToParent_rsToP_notEmpty,
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EN_iCacheToParent_rsToP_deq,
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RDY_iCacheToParent_rsToP_deq,
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iCacheToParent_rsToP_first,
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RDY_iCacheToParent_rsToP_first,
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iCacheToParent_rqToP_notEmpty,
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RDY_iCacheToParent_rqToP_notEmpty,
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EN_iCacheToParent_rqToP_deq,
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RDY_iCacheToParent_rqToP_deq,
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iCacheToParent_rqToP_first,
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RDY_iCacheToParent_rqToP_first,
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iCacheToParent_fromP_notFull,
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RDY_iCacheToParent_fromP_notFull,
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iCacheToParent_fromP_enq_x,
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EN_iCacheToParent_fromP_enq,
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RDY_iCacheToParent_fromP_enq,
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tlbToMem_memReq_notEmpty,
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RDY_tlbToMem_memReq_notEmpty,
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EN_tlbToMem_memReq_deq,
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RDY_tlbToMem_memReq_deq,
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tlbToMem_memReq_first,
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RDY_tlbToMem_memReq_first,
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tlbToMem_respLd_notFull,
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RDY_tlbToMem_respLd_notFull,
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tlbToMem_respLd_enq_x,
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EN_tlbToMem_respLd_enq,
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RDY_tlbToMem_respLd_enq,
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mmioToPlatform_cRq_notEmpty,
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RDY_mmioToPlatform_cRq_notEmpty,
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EN_mmioToPlatform_cRq_deq,
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RDY_mmioToPlatform_cRq_deq,
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mmioToPlatform_cRq_first,
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RDY_mmioToPlatform_cRq_first,
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mmioToPlatform_pRs_notFull,
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RDY_mmioToPlatform_pRs_notFull,
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mmioToPlatform_pRs_enq_x,
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EN_mmioToPlatform_pRs_enq,
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RDY_mmioToPlatform_pRs_enq,
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mmioToPlatform_pRq_notFull,
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RDY_mmioToPlatform_pRq_notFull,
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mmioToPlatform_pRq_enq_x,
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EN_mmioToPlatform_pRq_enq,
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RDY_mmioToPlatform_pRq_enq,
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mmioToPlatform_cRs_notEmpty,
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RDY_mmioToPlatform_cRs_notEmpty,
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EN_mmioToPlatform_cRs_deq,
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RDY_mmioToPlatform_cRs_deq,
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mmioToPlatform_cRs_first,
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RDY_mmioToPlatform_cRs_first,
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mmioToPlatform_setTime_t,
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EN_mmioToPlatform_setTime,
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RDY_mmioToPlatform_setTime,
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EN_sendDoStats,
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sendDoStats,
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RDY_sendDoStats,
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recvDoStats_x,
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EN_recvDoStats,
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RDY_recvDoStats,
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EN_deadlock_dCacheCRqStuck_get,
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deadlock_dCacheCRqStuck_get,
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RDY_deadlock_dCacheCRqStuck_get,
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EN_deadlock_dCachePRqStuck_get,
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deadlock_dCachePRqStuck_get,
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RDY_deadlock_dCachePRqStuck_get,
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EN_deadlock_iCacheCRqStuck_get,
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deadlock_iCacheCRqStuck_get,
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RDY_deadlock_iCacheCRqStuck_get,
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EN_deadlock_iCachePRqStuck_get,
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deadlock_iCachePRqStuck_get,
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RDY_deadlock_iCachePRqStuck_get,
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EN_deadlock_renameInstStuck_get,
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deadlock_renameInstStuck_get,
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RDY_deadlock_renameInstStuck_get,
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EN_deadlock_renameCorrectPathStuck_get,
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deadlock_renameCorrectPathStuck_get,
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RDY_deadlock_renameCorrectPathStuck_get,
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EN_deadlock_commitInstStuck_get,
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deadlock_commitInstStuck_get,
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RDY_deadlock_commitInstStuck_get,
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EN_deadlock_commitUserInstStuck_get,
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deadlock_commitUserInstStuck_get,
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RDY_deadlock_commitUserInstStuck_get,
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EN_deadlock_checkStarted_get,
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RDY_deadlock_checkStarted_get,
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EN_renameDebug_renameErr_get,
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renameDebug_renameErr_get,
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RDY_renameDebug_renameErr_get,
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setMEIP_v,
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EN_setMEIP,
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RDY_setMEIP,
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setSEIP_v,
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EN_setSEIP,
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RDY_setSEIP,
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setDEIP_v,
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EN_setDEIP,
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RDY_setDEIP);
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input CLK;
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input RST_N;
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// action method coreReq_start
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input [63 : 0] coreReq_start_startpc;
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input [63 : 0] coreReq_start_toHostAddr;
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input [63 : 0] coreReq_start_fromHostAddr;
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input EN_coreReq_start;
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output RDY_coreReq_start;
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// action method coreReq_perfReq
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input [3 : 0] coreReq_perfReq_loc;
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input [4 : 0] coreReq_perfReq_t;
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input EN_coreReq_perfReq;
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output RDY_coreReq_perfReq;
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// actionvalue method coreIndInv_perfResp
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input EN_coreIndInv_perfResp;
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output [72 : 0] coreIndInv_perfResp;
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output RDY_coreIndInv_perfResp;
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// action method coreIndInv_terminate
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input EN_coreIndInv_terminate;
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output RDY_coreIndInv_terminate;
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// value method dCacheToParent_rsToP_notEmpty
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output dCacheToParent_rsToP_notEmpty;
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output RDY_dCacheToParent_rsToP_notEmpty;
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// action method dCacheToParent_rsToP_deq
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input EN_dCacheToParent_rsToP_deq;
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output RDY_dCacheToParent_rsToP_deq;
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// value method dCacheToParent_rsToP_first
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output [578 : 0] dCacheToParent_rsToP_first;
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output RDY_dCacheToParent_rsToP_first;
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// value method dCacheToParent_rqToP_notEmpty
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output dCacheToParent_rqToP_notEmpty;
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output RDY_dCacheToParent_rqToP_notEmpty;
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// action method dCacheToParent_rqToP_deq
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input EN_dCacheToParent_rqToP_deq;
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output RDY_dCacheToParent_rqToP_deq;
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// value method dCacheToParent_rqToP_first
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output [71 : 0] dCacheToParent_rqToP_first;
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output RDY_dCacheToParent_rqToP_first;
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// value method dCacheToParent_fromP_notFull
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output dCacheToParent_fromP_notFull;
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output RDY_dCacheToParent_fromP_notFull;
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// action method dCacheToParent_fromP_enq
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input [582 : 0] dCacheToParent_fromP_enq_x;
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input EN_dCacheToParent_fromP_enq;
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output RDY_dCacheToParent_fromP_enq;
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// value method iCacheToParent_rsToP_notEmpty
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output iCacheToParent_rsToP_notEmpty;
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output RDY_iCacheToParent_rsToP_notEmpty;
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// action method iCacheToParent_rsToP_deq
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input EN_iCacheToParent_rsToP_deq;
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output RDY_iCacheToParent_rsToP_deq;
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// value method iCacheToParent_rsToP_first
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output [578 : 0] iCacheToParent_rsToP_first;
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output RDY_iCacheToParent_rsToP_first;
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// value method iCacheToParent_rqToP_notEmpty
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output iCacheToParent_rqToP_notEmpty;
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output RDY_iCacheToParent_rqToP_notEmpty;
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// action method iCacheToParent_rqToP_deq
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input EN_iCacheToParent_rqToP_deq;
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output RDY_iCacheToParent_rqToP_deq;
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// value method iCacheToParent_rqToP_first
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output [71 : 0] iCacheToParent_rqToP_first;
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output RDY_iCacheToParent_rqToP_first;
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// value method iCacheToParent_fromP_notFull
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output iCacheToParent_fromP_notFull;
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output RDY_iCacheToParent_fromP_notFull;
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// action method iCacheToParent_fromP_enq
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input [582 : 0] iCacheToParent_fromP_enq_x;
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input EN_iCacheToParent_fromP_enq;
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output RDY_iCacheToParent_fromP_enq;
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// value method tlbToMem_memReq_notEmpty
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output tlbToMem_memReq_notEmpty;
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output RDY_tlbToMem_memReq_notEmpty;
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// action method tlbToMem_memReq_deq
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input EN_tlbToMem_memReq_deq;
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output RDY_tlbToMem_memReq_deq;
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// value method tlbToMem_memReq_first
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output [64 : 0] tlbToMem_memReq_first;
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output RDY_tlbToMem_memReq_first;
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// value method tlbToMem_respLd_notFull
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output tlbToMem_respLd_notFull;
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output RDY_tlbToMem_respLd_notFull;
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// action method tlbToMem_respLd_enq
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input [64 : 0] tlbToMem_respLd_enq_x;
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input EN_tlbToMem_respLd_enq;
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output RDY_tlbToMem_respLd_enq;
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// value method mmioToPlatform_cRq_notEmpty
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output mmioToPlatform_cRq_notEmpty;
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output RDY_mmioToPlatform_cRq_notEmpty;
|
|
|
|
// action method mmioToPlatform_cRq_deq
|
|
input EN_mmioToPlatform_cRq_deq;
|
|
output RDY_mmioToPlatform_cRq_deq;
|
|
|
|
// value method mmioToPlatform_cRq_first
|
|
output [141 : 0] mmioToPlatform_cRq_first;
|
|
output RDY_mmioToPlatform_cRq_first;
|
|
|
|
// value method mmioToPlatform_pRs_notFull
|
|
output mmioToPlatform_pRs_notFull;
|
|
output RDY_mmioToPlatform_pRs_notFull;
|
|
|
|
// action method mmioToPlatform_pRs_enq
|
|
input [66 : 0] mmioToPlatform_pRs_enq_x;
|
|
input EN_mmioToPlatform_pRs_enq;
|
|
output RDY_mmioToPlatform_pRs_enq;
|
|
|
|
// value method mmioToPlatform_pRq_notFull
|
|
output mmioToPlatform_pRq_notFull;
|
|
output RDY_mmioToPlatform_pRq_notFull;
|
|
|
|
// action method mmioToPlatform_pRq_enq
|
|
input [38 : 0] mmioToPlatform_pRq_enq_x;
|
|
input EN_mmioToPlatform_pRq_enq;
|
|
output RDY_mmioToPlatform_pRq_enq;
|
|
|
|
// value method mmioToPlatform_cRs_notEmpty
|
|
output mmioToPlatform_cRs_notEmpty;
|
|
output RDY_mmioToPlatform_cRs_notEmpty;
|
|
|
|
// action method mmioToPlatform_cRs_deq
|
|
input EN_mmioToPlatform_cRs_deq;
|
|
output RDY_mmioToPlatform_cRs_deq;
|
|
|
|
// value method mmioToPlatform_cRs_first
|
|
output mmioToPlatform_cRs_first;
|
|
output RDY_mmioToPlatform_cRs_first;
|
|
|
|
// action method mmioToPlatform_setTime
|
|
input [63 : 0] mmioToPlatform_setTime_t;
|
|
input EN_mmioToPlatform_setTime;
|
|
output RDY_mmioToPlatform_setTime;
|
|
|
|
// actionvalue method sendDoStats
|
|
input EN_sendDoStats;
|
|
output sendDoStats;
|
|
output RDY_sendDoStats;
|
|
|
|
// action method recvDoStats
|
|
input recvDoStats_x;
|
|
input EN_recvDoStats;
|
|
output RDY_recvDoStats;
|
|
|
|
// actionvalue method deadlock_dCacheCRqStuck_get
|
|
input EN_deadlock_dCacheCRqStuck_get;
|
|
output [72 : 0] deadlock_dCacheCRqStuck_get;
|
|
output RDY_deadlock_dCacheCRqStuck_get;
|
|
|
|
// actionvalue method deadlock_dCachePRqStuck_get
|
|
input EN_deadlock_dCachePRqStuck_get;
|
|
output [67 : 0] deadlock_dCachePRqStuck_get;
|
|
output RDY_deadlock_dCachePRqStuck_get;
|
|
|
|
// actionvalue method deadlock_iCacheCRqStuck_get
|
|
input EN_deadlock_iCacheCRqStuck_get;
|
|
output [67 : 0] deadlock_iCacheCRqStuck_get;
|
|
output RDY_deadlock_iCacheCRqStuck_get;
|
|
|
|
// actionvalue method deadlock_iCachePRqStuck_get
|
|
input EN_deadlock_iCachePRqStuck_get;
|
|
output [67 : 0] deadlock_iCachePRqStuck_get;
|
|
output RDY_deadlock_iCachePRqStuck_get;
|
|
|
|
// actionvalue method deadlock_renameInstStuck_get
|
|
input EN_deadlock_renameInstStuck_get;
|
|
output [77 : 0] deadlock_renameInstStuck_get;
|
|
output RDY_deadlock_renameInstStuck_get;
|
|
|
|
// actionvalue method deadlock_renameCorrectPathStuck_get
|
|
input EN_deadlock_renameCorrectPathStuck_get;
|
|
output [77 : 0] deadlock_renameCorrectPathStuck_get;
|
|
output RDY_deadlock_renameCorrectPathStuck_get;
|
|
|
|
// actionvalue method deadlock_commitInstStuck_get
|
|
input EN_deadlock_commitInstStuck_get;
|
|
output [162 : 0] deadlock_commitInstStuck_get;
|
|
output RDY_deadlock_commitInstStuck_get;
|
|
|
|
// actionvalue method deadlock_commitUserInstStuck_get
|
|
input EN_deadlock_commitUserInstStuck_get;
|
|
output [162 : 0] deadlock_commitUserInstStuck_get;
|
|
output RDY_deadlock_commitUserInstStuck_get;
|
|
|
|
// action method deadlock_checkStarted_get
|
|
input EN_deadlock_checkStarted_get;
|
|
output RDY_deadlock_checkStarted_get;
|
|
|
|
// actionvalue method renameDebug_renameErr_get
|
|
input EN_renameDebug_renameErr_get;
|
|
output [88 : 0] renameDebug_renameErr_get;
|
|
output RDY_renameDebug_renameErr_get;
|
|
|
|
// action method setMEIP
|
|
input setMEIP_v;
|
|
input EN_setMEIP;
|
|
output RDY_setMEIP;
|
|
|
|
// action method setSEIP
|
|
input setSEIP_v;
|
|
input EN_setSEIP;
|
|
output RDY_setSEIP;
|
|
|
|
// action method setDEIP
|
|
input setDEIP_v;
|
|
input EN_setDEIP;
|
|
output RDY_setDEIP;
|
|
|
|
// signals for module outputs
|
|
wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first;
|
|
wire [162 : 0] deadlock_commitInstStuck_get,
|
|
deadlock_commitUserInstStuck_get;
|
|
wire [141 : 0] mmioToPlatform_cRq_first;
|
|
wire [88 : 0] renameDebug_renameErr_get;
|
|
wire [77 : 0] deadlock_renameCorrectPathStuck_get,
|
|
deadlock_renameInstStuck_get;
|
|
wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get;
|
|
wire [71 : 0] dCacheToParent_rqToP_first, iCacheToParent_rqToP_first;
|
|
wire [67 : 0] deadlock_dCachePRqStuck_get,
|
|
deadlock_iCacheCRqStuck_get,
|
|
deadlock_iCachePRqStuck_get;
|
|
wire [64 : 0] tlbToMem_memReq_first;
|
|
wire RDY_coreIndInv_perfResp,
|
|
RDY_coreIndInv_terminate,
|
|
RDY_coreReq_perfReq,
|
|
RDY_coreReq_start,
|
|
RDY_dCacheToParent_fromP_enq,
|
|
RDY_dCacheToParent_fromP_notFull,
|
|
RDY_dCacheToParent_rqToP_deq,
|
|
RDY_dCacheToParent_rqToP_first,
|
|
RDY_dCacheToParent_rqToP_notEmpty,
|
|
RDY_dCacheToParent_rsToP_deq,
|
|
RDY_dCacheToParent_rsToP_first,
|
|
RDY_dCacheToParent_rsToP_notEmpty,
|
|
RDY_deadlock_checkStarted_get,
|
|
RDY_deadlock_commitInstStuck_get,
|
|
RDY_deadlock_commitUserInstStuck_get,
|
|
RDY_deadlock_dCacheCRqStuck_get,
|
|
RDY_deadlock_dCachePRqStuck_get,
|
|
RDY_deadlock_iCacheCRqStuck_get,
|
|
RDY_deadlock_iCachePRqStuck_get,
|
|
RDY_deadlock_renameCorrectPathStuck_get,
|
|
RDY_deadlock_renameInstStuck_get,
|
|
RDY_iCacheToParent_fromP_enq,
|
|
RDY_iCacheToParent_fromP_notFull,
|
|
RDY_iCacheToParent_rqToP_deq,
|
|
RDY_iCacheToParent_rqToP_first,
|
|
RDY_iCacheToParent_rqToP_notEmpty,
|
|
RDY_iCacheToParent_rsToP_deq,
|
|
RDY_iCacheToParent_rsToP_first,
|
|
RDY_iCacheToParent_rsToP_notEmpty,
|
|
RDY_mmioToPlatform_cRq_deq,
|
|
RDY_mmioToPlatform_cRq_first,
|
|
RDY_mmioToPlatform_cRq_notEmpty,
|
|
RDY_mmioToPlatform_cRs_deq,
|
|
RDY_mmioToPlatform_cRs_first,
|
|
RDY_mmioToPlatform_cRs_notEmpty,
|
|
RDY_mmioToPlatform_pRq_enq,
|
|
RDY_mmioToPlatform_pRq_notFull,
|
|
RDY_mmioToPlatform_pRs_enq,
|
|
RDY_mmioToPlatform_pRs_notFull,
|
|
RDY_mmioToPlatform_setTime,
|
|
RDY_recvDoStats,
|
|
RDY_renameDebug_renameErr_get,
|
|
RDY_sendDoStats,
|
|
RDY_setDEIP,
|
|
RDY_setMEIP,
|
|
RDY_setSEIP,
|
|
RDY_tlbToMem_memReq_deq,
|
|
RDY_tlbToMem_memReq_first,
|
|
RDY_tlbToMem_memReq_notEmpty,
|
|
RDY_tlbToMem_respLd_enq,
|
|
RDY_tlbToMem_respLd_notFull,
|
|
dCacheToParent_fromP_notFull,
|
|
dCacheToParent_rqToP_notEmpty,
|
|
dCacheToParent_rsToP_notEmpty,
|
|
iCacheToParent_fromP_notFull,
|
|
iCacheToParent_rqToP_notEmpty,
|
|
iCacheToParent_rsToP_notEmpty,
|
|
mmioToPlatform_cRq_notEmpty,
|
|
mmioToPlatform_cRs_first,
|
|
mmioToPlatform_cRs_notEmpty,
|
|
mmioToPlatform_pRq_notFull,
|
|
mmioToPlatform_pRs_notFull,
|
|
sendDoStats,
|
|
tlbToMem_memReq_notEmpty,
|
|
tlbToMem_respLd_notFull;
|
|
|
|
// inlined wires
|
|
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget;
|
|
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget;
|
|
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget;
|
|
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget;
|
|
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget;
|
|
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget;
|
|
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget;
|
|
wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget;
|
|
wire [76 : 0] coreFix_memExe_issueLd$wget;
|
|
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget;
|
|
wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget,
|
|
coreFix_aluExe_0_bypassWire_1$wget,
|
|
coreFix_aluExe_0_bypassWire_2$wget,
|
|
coreFix_aluExe_0_bypassWire_3$wget;
|
|
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget,
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget;
|
|
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget;
|
|
wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget;
|
|
wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget,
|
|
mmio_dataRespQ_enqReq_lat_0$wget;
|
|
wire [63 : 0] csrf_mcycle_ehr_data_lat_0$wget;
|
|
wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget;
|
|
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget;
|
|
wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget;
|
|
wire coreFix_aluExe_0_bypassWire_0$whas,
|
|
coreFix_aluExe_0_bypassWire_1$whas,
|
|
coreFix_aluExe_0_bypassWire_2$whas,
|
|
coreFix_aluExe_0_bypassWire_3$whas,
|
|
coreFix_aluExe_1_bypassWire_2$whas,
|
|
coreFix_aluExe_1_bypassWire_3$whas,
|
|
coreFix_fpuMulDivExe_0_bypassWire_2$whas,
|
|
coreFix_fpuMulDivExe_0_bypassWire_3$whas,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
|
|
coreFix_globalSpecUpdate_correctSpecTag_0$whas,
|
|
coreFix_globalSpecUpdate_correctSpecTag_1$whas,
|
|
coreFix_memExe_bypassWire_2$whas,
|
|
coreFix_memExe_bypassWire_3$whas,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas,
|
|
coreFix_memExe_forwardQ_enqReq_lat_0$whas,
|
|
coreFix_memExe_issueLd$whas,
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas,
|
|
coreFix_memExe_reqLdQ_data_0_lat_0$whas,
|
|
coreFix_memExe_reqLdQ_empty_lat_0$whas,
|
|
coreFix_memExe_reqLdQ_full_lat_0$whas,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas,
|
|
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas,
|
|
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas,
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas,
|
|
csrInstOrInterruptInflight_lat_1$whas,
|
|
csrf_mcycle_ehr_data_lat_0$whas,
|
|
csrf_minstret_ehr_data_dummy_1_0$whas,
|
|
csrf_minstret_ehr_data_lat_0$whas,
|
|
csrf_minstret_ehr_data_lat_1$whas,
|
|
mmio_cRqQ_enqReq_lat_0$whas,
|
|
mmio_dataPendQ_enqReq_lat_0$whas,
|
|
mmio_dataReqQ_enqReq_lat_0$whas,
|
|
mmio_dataRespQ_deqReq_lat_0$whas,
|
|
mmio_pRsQ_deqReq_dummy_2_0$wget;
|
|
|
|
// register commitStage_commitTrap
|
|
reg [133 : 0] commitStage_commitTrap;
|
|
wire [133 : 0] commitStage_commitTrap$D_IN;
|
|
wire commitStage_commitTrap$EN;
|
|
|
|
// register coreFix_doStatsReg
|
|
reg coreFix_doStatsReg;
|
|
wire coreFix_doStatsReg$D_IN, coreFix_doStatsReg$EN;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt;
|
|
wire [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
|
|
reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
|
|
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit;
|
|
wire [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
|
|
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0;
|
|
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
|
|
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1;
|
|
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
|
|
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl;
|
|
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
|
|
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0;
|
|
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
|
|
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1;
|
|
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
|
|
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl;
|
|
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
|
|
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl;
|
|
wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
|
|
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo;
|
|
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
|
|
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl;
|
|
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
|
|
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0;
|
|
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
|
|
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1;
|
|
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
|
|
reg [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl;
|
|
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
|
|
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0;
|
|
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
|
|
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1;
|
|
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
|
|
reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl;
|
|
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
|
|
reg coreFix_memExe_dMem_perfReqQ_clearReq_rl;
|
|
wire coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_data_0
|
|
reg [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0;
|
|
wire [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
|
|
wire coreFix_memExe_dMem_perfReqQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
|
|
reg coreFix_memExe_dMem_perfReqQ_deqReq_rl;
|
|
wire coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_empty
|
|
reg coreFix_memExe_dMem_perfReqQ_empty;
|
|
wire coreFix_memExe_dMem_perfReqQ_empty$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_empty$EN;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
|
|
reg [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl;
|
|
wire [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_full
|
|
reg coreFix_memExe_dMem_perfReqQ_full;
|
|
wire coreFix_memExe_dMem_perfReqQ_full$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_full$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_clearReq_rl
|
|
reg coreFix_memExe_forwardQ_clearReq_rl;
|
|
wire coreFix_memExe_forwardQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_forwardQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_data_0
|
|
reg [68 : 0] coreFix_memExe_forwardQ_data_0;
|
|
wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN;
|
|
wire coreFix_memExe_forwardQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_data_1
|
|
reg [68 : 0] coreFix_memExe_forwardQ_data_1;
|
|
wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN;
|
|
wire coreFix_memExe_forwardQ_data_1$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_deqP
|
|
reg coreFix_memExe_forwardQ_deqP;
|
|
wire coreFix_memExe_forwardQ_deqP$D_IN, coreFix_memExe_forwardQ_deqP$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_deqReq_rl
|
|
reg coreFix_memExe_forwardQ_deqReq_rl;
|
|
wire coreFix_memExe_forwardQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_forwardQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_empty
|
|
reg coreFix_memExe_forwardQ_empty;
|
|
wire coreFix_memExe_forwardQ_empty$D_IN, coreFix_memExe_forwardQ_empty$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_enqP
|
|
reg coreFix_memExe_forwardQ_enqP;
|
|
wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_enqReq_rl
|
|
reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl;
|
|
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_forwardQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_forwardQ_full
|
|
reg coreFix_memExe_forwardQ_full;
|
|
wire coreFix_memExe_forwardQ_full$D_IN, coreFix_memExe_forwardQ_full$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_clearReq_rl
|
|
reg coreFix_memExe_memRespLdQ_clearReq_rl;
|
|
wire coreFix_memExe_memRespLdQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_memRespLdQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_data_0
|
|
reg [68 : 0] coreFix_memExe_memRespLdQ_data_0;
|
|
wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN;
|
|
wire coreFix_memExe_memRespLdQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_data_1
|
|
reg [68 : 0] coreFix_memExe_memRespLdQ_data_1;
|
|
wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN;
|
|
wire coreFix_memExe_memRespLdQ_data_1$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_deqP
|
|
reg coreFix_memExe_memRespLdQ_deqP;
|
|
wire coreFix_memExe_memRespLdQ_deqP$D_IN, coreFix_memExe_memRespLdQ_deqP$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_deqReq_rl
|
|
reg coreFix_memExe_memRespLdQ_deqReq_rl;
|
|
wire coreFix_memExe_memRespLdQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_memRespLdQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_empty
|
|
reg coreFix_memExe_memRespLdQ_empty;
|
|
wire coreFix_memExe_memRespLdQ_empty$D_IN,
|
|
coreFix_memExe_memRespLdQ_empty$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_enqP
|
|
reg coreFix_memExe_memRespLdQ_enqP;
|
|
wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_enqReq_rl
|
|
reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl;
|
|
wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_memRespLdQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_memRespLdQ_full
|
|
reg coreFix_memExe_memRespLdQ_full;
|
|
wire coreFix_memExe_memRespLdQ_full$D_IN, coreFix_memExe_memRespLdQ_full$EN;
|
|
|
|
// register coreFix_memExe_reqLdQ_data_0_rl
|
|
reg [68 : 0] coreFix_memExe_reqLdQ_data_0_rl;
|
|
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_rl$D_IN;
|
|
wire coreFix_memExe_reqLdQ_data_0_rl$EN;
|
|
|
|
// register coreFix_memExe_reqLdQ_empty_rl
|
|
reg coreFix_memExe_reqLdQ_empty_rl;
|
|
wire coreFix_memExe_reqLdQ_empty_rl$D_IN, coreFix_memExe_reqLdQ_empty_rl$EN;
|
|
|
|
// register coreFix_memExe_reqLdQ_full_rl
|
|
reg coreFix_memExe_reqLdQ_full_rl;
|
|
wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN;
|
|
|
|
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
|
|
reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl;
|
|
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
|
|
wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN;
|
|
|
|
// register coreFix_memExe_reqLrScAmoQ_empty_rl
|
|
reg coreFix_memExe_reqLrScAmoQ_empty_rl;
|
|
wire coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_empty_rl$EN;
|
|
|
|
// register coreFix_memExe_reqLrScAmoQ_full_rl
|
|
reg coreFix_memExe_reqLrScAmoQ_full_rl;
|
|
wire coreFix_memExe_reqLrScAmoQ_full_rl$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_full_rl$EN;
|
|
|
|
// register coreFix_memExe_reqStQ_data_0_rl
|
|
reg [65 : 0] coreFix_memExe_reqStQ_data_0_rl;
|
|
wire [65 : 0] coreFix_memExe_reqStQ_data_0_rl$D_IN;
|
|
wire coreFix_memExe_reqStQ_data_0_rl$EN;
|
|
|
|
// register coreFix_memExe_reqStQ_empty_rl
|
|
reg coreFix_memExe_reqStQ_empty_rl;
|
|
wire coreFix_memExe_reqStQ_empty_rl$D_IN, coreFix_memExe_reqStQ_empty_rl$EN;
|
|
|
|
// register coreFix_memExe_reqStQ_full_rl
|
|
reg coreFix_memExe_reqStQ_full_rl;
|
|
wire coreFix_memExe_reqStQ_full_rl$D_IN, coreFix_memExe_reqStQ_full_rl$EN;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
|
|
reg coreFix_memExe_respLrScAmoQ_clearReq_rl;
|
|
wire coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_clearReq_rl$EN;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_data_0
|
|
reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0;
|
|
wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN;
|
|
wire coreFix_memExe_respLrScAmoQ_data_0$EN;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
|
|
reg coreFix_memExe_respLrScAmoQ_deqReq_rl;
|
|
wire coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_deqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_empty
|
|
reg coreFix_memExe_respLrScAmoQ_empty;
|
|
wire coreFix_memExe_respLrScAmoQ_empty$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_empty$EN;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
|
|
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl;
|
|
wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
|
|
wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_full
|
|
reg coreFix_memExe_respLrScAmoQ_full;
|
|
wire coreFix_memExe_respLrScAmoQ_full$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_full$EN;
|
|
|
|
// register coreFix_memExe_waitLrScAmoMMIOResp
|
|
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp;
|
|
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
|
|
wire coreFix_memExe_waitLrScAmoMMIOResp$EN;
|
|
|
|
// register csrInstOrInterruptInflight_rl
|
|
reg csrInstOrInterruptInflight_rl;
|
|
wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN;
|
|
|
|
// register csrf_debug_int_pend
|
|
reg csrf_debug_int_pend;
|
|
wire csrf_debug_int_pend$D_IN, csrf_debug_int_pend$EN;
|
|
|
|
// register csrf_external_int_en_vec_0
|
|
reg csrf_external_int_en_vec_0;
|
|
wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN;
|
|
|
|
// register csrf_external_int_en_vec_1
|
|
reg csrf_external_int_en_vec_1;
|
|
wire csrf_external_int_en_vec_1$D_IN, csrf_external_int_en_vec_1$EN;
|
|
|
|
// register csrf_external_int_en_vec_3
|
|
reg csrf_external_int_en_vec_3;
|
|
wire csrf_external_int_en_vec_3$D_IN, csrf_external_int_en_vec_3$EN;
|
|
|
|
// register csrf_external_int_pend_vec_0
|
|
reg csrf_external_int_pend_vec_0;
|
|
wire csrf_external_int_pend_vec_0$D_IN, csrf_external_int_pend_vec_0$EN;
|
|
|
|
// register csrf_external_int_pend_vec_1
|
|
reg csrf_external_int_pend_vec_1;
|
|
wire csrf_external_int_pend_vec_1$D_IN, csrf_external_int_pend_vec_1$EN;
|
|
|
|
// register csrf_external_int_pend_vec_3
|
|
reg csrf_external_int_pend_vec_3;
|
|
wire csrf_external_int_pend_vec_3$D_IN, csrf_external_int_pend_vec_3$EN;
|
|
|
|
// register csrf_fflags_reg
|
|
reg [4 : 0] csrf_fflags_reg;
|
|
wire [4 : 0] csrf_fflags_reg$D_IN;
|
|
wire csrf_fflags_reg$EN;
|
|
|
|
// register csrf_frm_reg
|
|
reg [2 : 0] csrf_frm_reg;
|
|
wire [2 : 0] csrf_frm_reg$D_IN;
|
|
wire csrf_frm_reg$EN;
|
|
|
|
// register csrf_fs_reg
|
|
reg [1 : 0] csrf_fs_reg;
|
|
wire [1 : 0] csrf_fs_reg$D_IN;
|
|
wire csrf_fs_reg$EN;
|
|
|
|
// register csrf_ie_vec_0
|
|
reg csrf_ie_vec_0;
|
|
wire csrf_ie_vec_0$D_IN, csrf_ie_vec_0$EN;
|
|
|
|
// register csrf_ie_vec_1
|
|
reg csrf_ie_vec_1;
|
|
wire csrf_ie_vec_1$D_IN, csrf_ie_vec_1$EN;
|
|
|
|
// register csrf_ie_vec_3
|
|
reg csrf_ie_vec_3;
|
|
wire csrf_ie_vec_3$D_IN, csrf_ie_vec_3$EN;
|
|
|
|
// register csrf_mcause_code_reg
|
|
reg [3 : 0] csrf_mcause_code_reg;
|
|
wire [3 : 0] csrf_mcause_code_reg$D_IN;
|
|
wire csrf_mcause_code_reg$EN;
|
|
|
|
// register csrf_mcause_interrupt_reg
|
|
reg csrf_mcause_interrupt_reg;
|
|
wire csrf_mcause_interrupt_reg$D_IN, csrf_mcause_interrupt_reg$EN;
|
|
|
|
// register csrf_mcounteren_cy_reg
|
|
reg csrf_mcounteren_cy_reg;
|
|
wire csrf_mcounteren_cy_reg$D_IN, csrf_mcounteren_cy_reg$EN;
|
|
|
|
// register csrf_mcounteren_ir_reg
|
|
reg csrf_mcounteren_ir_reg;
|
|
wire csrf_mcounteren_ir_reg$D_IN, csrf_mcounteren_ir_reg$EN;
|
|
|
|
// register csrf_mcounteren_tm_reg
|
|
reg csrf_mcounteren_tm_reg;
|
|
wire csrf_mcounteren_tm_reg$D_IN, csrf_mcounteren_tm_reg$EN;
|
|
|
|
// register csrf_mcycle_ehr_data_rl
|
|
reg [63 : 0] csrf_mcycle_ehr_data_rl;
|
|
wire [63 : 0] csrf_mcycle_ehr_data_rl$D_IN;
|
|
wire csrf_mcycle_ehr_data_rl$EN;
|
|
|
|
// register csrf_medeleg_13_11_reg
|
|
reg [2 : 0] csrf_medeleg_13_11_reg;
|
|
wire [2 : 0] csrf_medeleg_13_11_reg$D_IN;
|
|
wire csrf_medeleg_13_11_reg$EN;
|
|
|
|
// register csrf_medeleg_15_reg
|
|
reg csrf_medeleg_15_reg;
|
|
wire csrf_medeleg_15_reg$D_IN, csrf_medeleg_15_reg$EN;
|
|
|
|
// register csrf_medeleg_9_0_reg
|
|
reg [9 : 0] csrf_medeleg_9_0_reg;
|
|
wire [9 : 0] csrf_medeleg_9_0_reg$D_IN;
|
|
wire csrf_medeleg_9_0_reg$EN;
|
|
|
|
// register csrf_mepc_csr
|
|
reg [63 : 0] csrf_mepc_csr;
|
|
wire [63 : 0] csrf_mepc_csr$D_IN;
|
|
wire csrf_mepc_csr$EN;
|
|
|
|
// register csrf_mideleg_11_reg
|
|
reg csrf_mideleg_11_reg;
|
|
wire csrf_mideleg_11_reg$D_IN, csrf_mideleg_11_reg$EN;
|
|
|
|
// register csrf_mideleg_1_0_reg
|
|
reg [1 : 0] csrf_mideleg_1_0_reg;
|
|
wire [1 : 0] csrf_mideleg_1_0_reg$D_IN;
|
|
wire csrf_mideleg_1_0_reg$EN;
|
|
|
|
// register csrf_mideleg_5_3_reg
|
|
reg [2 : 0] csrf_mideleg_5_3_reg;
|
|
wire [2 : 0] csrf_mideleg_5_3_reg$D_IN;
|
|
wire csrf_mideleg_5_3_reg$EN;
|
|
|
|
// register csrf_mideleg_9_7_reg
|
|
reg [2 : 0] csrf_mideleg_9_7_reg;
|
|
wire [2 : 0] csrf_mideleg_9_7_reg$D_IN;
|
|
wire csrf_mideleg_9_7_reg$EN;
|
|
|
|
// register csrf_minstret_ehr_data_rl
|
|
reg [63 : 0] csrf_minstret_ehr_data_rl;
|
|
wire [63 : 0] csrf_minstret_ehr_data_rl$D_IN;
|
|
wire csrf_minstret_ehr_data_rl$EN;
|
|
|
|
// register csrf_mpp_reg
|
|
reg [1 : 0] csrf_mpp_reg;
|
|
wire [1 : 0] csrf_mpp_reg$D_IN;
|
|
wire csrf_mpp_reg$EN;
|
|
|
|
// register csrf_mprv_reg
|
|
reg csrf_mprv_reg;
|
|
wire csrf_mprv_reg$D_IN, csrf_mprv_reg$EN;
|
|
|
|
// register csrf_mscratch_csr
|
|
reg [63 : 0] csrf_mscratch_csr;
|
|
wire [63 : 0] csrf_mscratch_csr$D_IN;
|
|
wire csrf_mscratch_csr$EN;
|
|
|
|
// register csrf_mtval_csr
|
|
reg [63 : 0] csrf_mtval_csr;
|
|
wire [63 : 0] csrf_mtval_csr$D_IN;
|
|
wire csrf_mtval_csr$EN;
|
|
|
|
// register csrf_mtvec_base_hi_reg
|
|
reg [61 : 0] csrf_mtvec_base_hi_reg;
|
|
wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN;
|
|
wire csrf_mtvec_base_hi_reg$EN;
|
|
|
|
// register csrf_mtvec_mode_low_reg
|
|
reg csrf_mtvec_mode_low_reg;
|
|
wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN;
|
|
|
|
// register csrf_mxr_reg
|
|
reg csrf_mxr_reg;
|
|
wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN;
|
|
|
|
// register csrf_ppn_reg
|
|
reg [43 : 0] csrf_ppn_reg;
|
|
wire [43 : 0] csrf_ppn_reg$D_IN;
|
|
wire csrf_ppn_reg$EN;
|
|
|
|
// register csrf_prev_ie_vec_0
|
|
reg csrf_prev_ie_vec_0;
|
|
wire csrf_prev_ie_vec_0$D_IN, csrf_prev_ie_vec_0$EN;
|
|
|
|
// register csrf_prev_ie_vec_1
|
|
reg csrf_prev_ie_vec_1;
|
|
wire csrf_prev_ie_vec_1$D_IN, csrf_prev_ie_vec_1$EN;
|
|
|
|
// register csrf_prev_ie_vec_3
|
|
reg csrf_prev_ie_vec_3;
|
|
wire csrf_prev_ie_vec_3$D_IN, csrf_prev_ie_vec_3$EN;
|
|
|
|
// register csrf_prv_reg
|
|
reg [1 : 0] csrf_prv_reg;
|
|
wire [1 : 0] csrf_prv_reg$D_IN;
|
|
wire csrf_prv_reg$EN;
|
|
|
|
// register csrf_scause_code_reg
|
|
reg [3 : 0] csrf_scause_code_reg;
|
|
wire [3 : 0] csrf_scause_code_reg$D_IN;
|
|
wire csrf_scause_code_reg$EN;
|
|
|
|
// register csrf_scause_interrupt_reg
|
|
reg csrf_scause_interrupt_reg;
|
|
wire csrf_scause_interrupt_reg$D_IN, csrf_scause_interrupt_reg$EN;
|
|
|
|
// register csrf_scounteren_cy_reg
|
|
reg csrf_scounteren_cy_reg;
|
|
wire csrf_scounteren_cy_reg$D_IN, csrf_scounteren_cy_reg$EN;
|
|
|
|
// register csrf_scounteren_ir_reg
|
|
reg csrf_scounteren_ir_reg;
|
|
wire csrf_scounteren_ir_reg$D_IN, csrf_scounteren_ir_reg$EN;
|
|
|
|
// register csrf_scounteren_tm_reg
|
|
reg csrf_scounteren_tm_reg;
|
|
wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN;
|
|
|
|
// register csrf_sepc_csr
|
|
reg [63 : 0] csrf_sepc_csr;
|
|
wire [63 : 0] csrf_sepc_csr$D_IN;
|
|
wire csrf_sepc_csr$EN;
|
|
|
|
// register csrf_software_int_en_vec_0
|
|
reg csrf_software_int_en_vec_0;
|
|
wire csrf_software_int_en_vec_0$D_IN, csrf_software_int_en_vec_0$EN;
|
|
|
|
// register csrf_software_int_en_vec_1
|
|
reg csrf_software_int_en_vec_1;
|
|
wire csrf_software_int_en_vec_1$D_IN, csrf_software_int_en_vec_1$EN;
|
|
|
|
// register csrf_software_int_en_vec_3
|
|
reg csrf_software_int_en_vec_3;
|
|
wire csrf_software_int_en_vec_3$D_IN, csrf_software_int_en_vec_3$EN;
|
|
|
|
// register csrf_software_int_pend_vec_0
|
|
reg csrf_software_int_pend_vec_0;
|
|
wire csrf_software_int_pend_vec_0$D_IN, csrf_software_int_pend_vec_0$EN;
|
|
|
|
// register csrf_software_int_pend_vec_1
|
|
reg csrf_software_int_pend_vec_1;
|
|
wire csrf_software_int_pend_vec_1$D_IN, csrf_software_int_pend_vec_1$EN;
|
|
|
|
// register csrf_software_int_pend_vec_3
|
|
reg csrf_software_int_pend_vec_3;
|
|
wire csrf_software_int_pend_vec_3$D_IN, csrf_software_int_pend_vec_3$EN;
|
|
|
|
// register csrf_spp_reg
|
|
reg csrf_spp_reg;
|
|
wire csrf_spp_reg$D_IN, csrf_spp_reg$EN;
|
|
|
|
// register csrf_sscratch_csr
|
|
reg [63 : 0] csrf_sscratch_csr;
|
|
wire [63 : 0] csrf_sscratch_csr$D_IN;
|
|
wire csrf_sscratch_csr$EN;
|
|
|
|
// register csrf_stats_module_doStats
|
|
reg csrf_stats_module_doStats;
|
|
wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN;
|
|
|
|
// register csrf_stval_csr
|
|
reg [63 : 0] csrf_stval_csr;
|
|
wire [63 : 0] csrf_stval_csr$D_IN;
|
|
wire csrf_stval_csr$EN;
|
|
|
|
// register csrf_stvec_base_hi_reg
|
|
reg [61 : 0] csrf_stvec_base_hi_reg;
|
|
wire [61 : 0] csrf_stvec_base_hi_reg$D_IN;
|
|
wire csrf_stvec_base_hi_reg$EN;
|
|
|
|
// register csrf_stvec_mode_low_reg
|
|
reg csrf_stvec_mode_low_reg;
|
|
wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN;
|
|
|
|
// register csrf_sum_reg
|
|
reg csrf_sum_reg;
|
|
wire csrf_sum_reg$D_IN, csrf_sum_reg$EN;
|
|
|
|
// register csrf_time_reg
|
|
reg [63 : 0] csrf_time_reg;
|
|
wire [63 : 0] csrf_time_reg$D_IN;
|
|
wire csrf_time_reg$EN;
|
|
|
|
// register csrf_timer_int_en_vec_0
|
|
reg csrf_timer_int_en_vec_0;
|
|
wire csrf_timer_int_en_vec_0$D_IN, csrf_timer_int_en_vec_0$EN;
|
|
|
|
// register csrf_timer_int_en_vec_1
|
|
reg csrf_timer_int_en_vec_1;
|
|
wire csrf_timer_int_en_vec_1$D_IN, csrf_timer_int_en_vec_1$EN;
|
|
|
|
// register csrf_timer_int_en_vec_3
|
|
reg csrf_timer_int_en_vec_3;
|
|
wire csrf_timer_int_en_vec_3$D_IN, csrf_timer_int_en_vec_3$EN;
|
|
|
|
// register csrf_timer_int_pend_vec_0
|
|
reg csrf_timer_int_pend_vec_0;
|
|
wire csrf_timer_int_pend_vec_0$D_IN, csrf_timer_int_pend_vec_0$EN;
|
|
|
|
// register csrf_timer_int_pend_vec_1
|
|
reg csrf_timer_int_pend_vec_1;
|
|
wire csrf_timer_int_pend_vec_1$D_IN, csrf_timer_int_pend_vec_1$EN;
|
|
|
|
// register csrf_timer_int_pend_vec_3
|
|
reg csrf_timer_int_pend_vec_3;
|
|
wire csrf_timer_int_pend_vec_3$D_IN, csrf_timer_int_pend_vec_3$EN;
|
|
|
|
// register csrf_tsr_reg
|
|
reg csrf_tsr_reg;
|
|
wire csrf_tsr_reg$D_IN, csrf_tsr_reg$EN;
|
|
|
|
// register csrf_tvm_reg
|
|
reg csrf_tvm_reg;
|
|
wire csrf_tvm_reg$D_IN, csrf_tvm_reg$EN;
|
|
|
|
// register csrf_tw_reg
|
|
reg csrf_tw_reg;
|
|
wire csrf_tw_reg$D_IN, csrf_tw_reg$EN;
|
|
|
|
// register csrf_vm_mode_sv39_reg
|
|
reg csrf_vm_mode_sv39_reg;
|
|
wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN;
|
|
|
|
// register flush_reservation
|
|
reg flush_reservation;
|
|
wire flush_reservation$D_IN, flush_reservation$EN;
|
|
|
|
// register flush_tlbs
|
|
reg flush_tlbs;
|
|
wire flush_tlbs$D_IN, flush_tlbs$EN;
|
|
|
|
// register mmio_cRqQ_clearReq_rl
|
|
reg mmio_cRqQ_clearReq_rl;
|
|
wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN;
|
|
|
|
// register mmio_cRqQ_data_0
|
|
reg [141 : 0] mmio_cRqQ_data_0;
|
|
wire [141 : 0] mmio_cRqQ_data_0$D_IN;
|
|
wire mmio_cRqQ_data_0$EN;
|
|
|
|
// register mmio_cRqQ_deqReq_rl
|
|
reg mmio_cRqQ_deqReq_rl;
|
|
wire mmio_cRqQ_deqReq_rl$D_IN, mmio_cRqQ_deqReq_rl$EN;
|
|
|
|
// register mmio_cRqQ_empty
|
|
reg mmio_cRqQ_empty;
|
|
wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN;
|
|
|
|
// register mmio_cRqQ_enqReq_rl
|
|
reg [142 : 0] mmio_cRqQ_enqReq_rl;
|
|
wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN;
|
|
wire mmio_cRqQ_enqReq_rl$EN;
|
|
|
|
// register mmio_cRqQ_full
|
|
reg mmio_cRqQ_full;
|
|
wire mmio_cRqQ_full$D_IN, mmio_cRqQ_full$EN;
|
|
|
|
// register mmio_cRsQ_clearReq_rl
|
|
reg mmio_cRsQ_clearReq_rl;
|
|
wire mmio_cRsQ_clearReq_rl$D_IN, mmio_cRsQ_clearReq_rl$EN;
|
|
|
|
// register mmio_cRsQ_data_0
|
|
reg mmio_cRsQ_data_0;
|
|
wire mmio_cRsQ_data_0$D_IN, mmio_cRsQ_data_0$EN;
|
|
|
|
// register mmio_cRsQ_deqReq_rl
|
|
reg mmio_cRsQ_deqReq_rl;
|
|
wire mmio_cRsQ_deqReq_rl$D_IN, mmio_cRsQ_deqReq_rl$EN;
|
|
|
|
// register mmio_cRsQ_empty
|
|
reg mmio_cRsQ_empty;
|
|
wire mmio_cRsQ_empty$D_IN, mmio_cRsQ_empty$EN;
|
|
|
|
// register mmio_cRsQ_enqReq_rl
|
|
reg [1 : 0] mmio_cRsQ_enqReq_rl;
|
|
wire [1 : 0] mmio_cRsQ_enqReq_rl$D_IN;
|
|
wire mmio_cRsQ_enqReq_rl$EN;
|
|
|
|
// register mmio_cRsQ_full
|
|
reg mmio_cRsQ_full;
|
|
wire mmio_cRsQ_full$D_IN, mmio_cRsQ_full$EN;
|
|
|
|
// register mmio_dataPendQ_clearReq_rl
|
|
reg mmio_dataPendQ_clearReq_rl;
|
|
wire mmio_dataPendQ_clearReq_rl$D_IN, mmio_dataPendQ_clearReq_rl$EN;
|
|
|
|
// register mmio_dataPendQ_deqReq_rl
|
|
reg mmio_dataPendQ_deqReq_rl;
|
|
wire mmio_dataPendQ_deqReq_rl$D_IN, mmio_dataPendQ_deqReq_rl$EN;
|
|
|
|
// register mmio_dataPendQ_empty
|
|
reg mmio_dataPendQ_empty;
|
|
wire mmio_dataPendQ_empty$D_IN, mmio_dataPendQ_empty$EN;
|
|
|
|
// register mmio_dataPendQ_enqReq_rl
|
|
reg mmio_dataPendQ_enqReq_rl;
|
|
wire mmio_dataPendQ_enqReq_rl$D_IN, mmio_dataPendQ_enqReq_rl$EN;
|
|
|
|
// register mmio_dataPendQ_full
|
|
reg mmio_dataPendQ_full;
|
|
wire mmio_dataPendQ_full$D_IN, mmio_dataPendQ_full$EN;
|
|
|
|
// register mmio_dataReqQ_clearReq_rl
|
|
reg mmio_dataReqQ_clearReq_rl;
|
|
wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN;
|
|
|
|
// register mmio_dataReqQ_data_0
|
|
reg [141 : 0] mmio_dataReqQ_data_0;
|
|
wire [141 : 0] mmio_dataReqQ_data_0$D_IN;
|
|
wire mmio_dataReqQ_data_0$EN;
|
|
|
|
// register mmio_dataReqQ_deqReq_rl
|
|
reg mmio_dataReqQ_deqReq_rl;
|
|
wire mmio_dataReqQ_deqReq_rl$D_IN, mmio_dataReqQ_deqReq_rl$EN;
|
|
|
|
// register mmio_dataReqQ_empty
|
|
reg mmio_dataReqQ_empty;
|
|
wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN;
|
|
|
|
// register mmio_dataReqQ_enqReq_rl
|
|
reg [142 : 0] mmio_dataReqQ_enqReq_rl;
|
|
wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN;
|
|
wire mmio_dataReqQ_enqReq_rl$EN;
|
|
|
|
// register mmio_dataReqQ_full
|
|
reg mmio_dataReqQ_full;
|
|
wire mmio_dataReqQ_full$D_IN, mmio_dataReqQ_full$EN;
|
|
|
|
// register mmio_dataRespQ_clearReq_rl
|
|
reg mmio_dataRespQ_clearReq_rl;
|
|
wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN;
|
|
|
|
// register mmio_dataRespQ_data_0
|
|
reg [64 : 0] mmio_dataRespQ_data_0;
|
|
wire [64 : 0] mmio_dataRespQ_data_0$D_IN;
|
|
wire mmio_dataRespQ_data_0$EN;
|
|
|
|
// register mmio_dataRespQ_deqReq_rl
|
|
reg mmio_dataRespQ_deqReq_rl;
|
|
wire mmio_dataRespQ_deqReq_rl$D_IN, mmio_dataRespQ_deqReq_rl$EN;
|
|
|
|
// register mmio_dataRespQ_empty
|
|
reg mmio_dataRespQ_empty;
|
|
wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN;
|
|
|
|
// register mmio_dataRespQ_enqReq_rl
|
|
reg [65 : 0] mmio_dataRespQ_enqReq_rl;
|
|
wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN;
|
|
wire mmio_dataRespQ_enqReq_rl$EN;
|
|
|
|
// register mmio_dataRespQ_full
|
|
reg mmio_dataRespQ_full;
|
|
wire mmio_dataRespQ_full$D_IN, mmio_dataRespQ_full$EN;
|
|
|
|
// register mmio_fromHostAddr
|
|
reg [60 : 0] mmio_fromHostAddr;
|
|
wire [60 : 0] mmio_fromHostAddr$D_IN;
|
|
wire mmio_fromHostAddr$EN;
|
|
|
|
// register mmio_pRqQ_clearReq_rl
|
|
reg mmio_pRqQ_clearReq_rl;
|
|
wire mmio_pRqQ_clearReq_rl$D_IN, mmio_pRqQ_clearReq_rl$EN;
|
|
|
|
// register mmio_pRqQ_data_0
|
|
reg [38 : 0] mmio_pRqQ_data_0;
|
|
wire [38 : 0] mmio_pRqQ_data_0$D_IN;
|
|
wire mmio_pRqQ_data_0$EN;
|
|
|
|
// register mmio_pRqQ_deqReq_rl
|
|
reg mmio_pRqQ_deqReq_rl;
|
|
wire mmio_pRqQ_deqReq_rl$D_IN, mmio_pRqQ_deqReq_rl$EN;
|
|
|
|
// register mmio_pRqQ_empty
|
|
reg mmio_pRqQ_empty;
|
|
wire mmio_pRqQ_empty$D_IN, mmio_pRqQ_empty$EN;
|
|
|
|
// register mmio_pRqQ_enqReq_rl
|
|
reg [39 : 0] mmio_pRqQ_enqReq_rl;
|
|
wire [39 : 0] mmio_pRqQ_enqReq_rl$D_IN;
|
|
wire mmio_pRqQ_enqReq_rl$EN;
|
|
|
|
// register mmio_pRqQ_full
|
|
reg mmio_pRqQ_full;
|
|
wire mmio_pRqQ_full$D_IN, mmio_pRqQ_full$EN;
|
|
|
|
// register mmio_pRsQ_clearReq_rl
|
|
reg mmio_pRsQ_clearReq_rl;
|
|
wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN;
|
|
|
|
// register mmio_pRsQ_data_0
|
|
reg [66 : 0] mmio_pRsQ_data_0;
|
|
wire [66 : 0] mmio_pRsQ_data_0$D_IN;
|
|
wire mmio_pRsQ_data_0$EN;
|
|
|
|
// register mmio_pRsQ_deqReq_rl
|
|
reg mmio_pRsQ_deqReq_rl;
|
|
wire mmio_pRsQ_deqReq_rl$D_IN, mmio_pRsQ_deqReq_rl$EN;
|
|
|
|
// register mmio_pRsQ_empty
|
|
reg mmio_pRsQ_empty;
|
|
wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN;
|
|
|
|
// register mmio_pRsQ_enqReq_rl
|
|
reg [67 : 0] mmio_pRsQ_enqReq_rl;
|
|
wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN;
|
|
wire mmio_pRsQ_enqReq_rl$EN;
|
|
|
|
// register mmio_pRsQ_full
|
|
reg mmio_pRsQ_full;
|
|
wire mmio_pRsQ_full$D_IN, mmio_pRsQ_full$EN;
|
|
|
|
// register mmio_toHostAddr
|
|
reg [60 : 0] mmio_toHostAddr;
|
|
wire [60 : 0] mmio_toHostAddr$D_IN;
|
|
wire mmio_toHostAddr$EN;
|
|
|
|
// register outOfReset
|
|
reg outOfReset;
|
|
wire outOfReset$D_IN, outOfReset$EN;
|
|
|
|
// register started
|
|
reg started;
|
|
wire started$D_IN, started$EN;
|
|
|
|
// register update_vm_info
|
|
reg update_vm_info;
|
|
wire update_vm_info$D_IN, update_vm_info$EN;
|
|
|
|
// ports of submodule coreFix_aluExe_0_dispToRegQ
|
|
reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x,
|
|
coreFix_aluExe_0_dispToRegQ$first;
|
|
wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_aluExe_0_dispToRegQ$EN_deq,
|
|
coreFix_aluExe_0_dispToRegQ$EN_enq,
|
|
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_0_dispToRegQ$RDY_deq,
|
|
coreFix_aluExe_0_dispToRegQ$RDY_enq,
|
|
coreFix_aluExe_0_dispToRegQ$RDY_first,
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_aluExe_0_exeToFinQ
|
|
reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [325 : 0] coreFix_aluExe_0_exeToFinQ$enq_x,
|
|
coreFix_aluExe_0_exeToFinQ$first;
|
|
wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_aluExe_0_exeToFinQ$EN_deq,
|
|
coreFix_aluExe_0_exeToFinQ$EN_enq,
|
|
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_0_exeToFinQ$RDY_deq,
|
|
coreFix_aluExe_0_exeToFinQ$RDY_enq,
|
|
coreFix_aluExe_0_exeToFinQ$RDY_first,
|
|
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_aluExe_0_regToExeQ
|
|
reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [389 : 0] coreFix_aluExe_0_regToExeQ$enq_x,
|
|
coreFix_aluExe_0_regToExeQ$first;
|
|
wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_aluExe_0_regToExeQ$EN_deq,
|
|
coreFix_aluExe_0_regToExeQ$EN_enq,
|
|
coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_0_regToExeQ$RDY_deq,
|
|
coreFix_aluExe_0_regToExeQ$RDY_enq,
|
|
coreFix_aluExe_0_regToExeQ$RDY_first,
|
|
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_aluExe_0_rsAlu
|
|
reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put,
|
|
coreFix_aluExe_0_rsAlu$setRegReady_4_put;
|
|
reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData,
|
|
coreFix_aluExe_0_rsAlu$enq_x;
|
|
wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask;
|
|
wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put,
|
|
coreFix_aluExe_0_rsAlu$setRegReady_1_put,
|
|
coreFix_aluExe_0_rsAlu$setRegReady_3_put;
|
|
wire [5 : 0] coreFix_aluExe_0_rsAlu$setRobEnqTime_t;
|
|
wire [4 : 0] coreFix_aluExe_0_rsAlu$approximateCount;
|
|
wire coreFix_aluExe_0_rsAlu$EN_doDispatch,
|
|
coreFix_aluExe_0_rsAlu$EN_enq,
|
|
coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put,
|
|
coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put,
|
|
coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put,
|
|
coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
|
|
coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put,
|
|
coreFix_aluExe_0_rsAlu$EN_setRobEnqTime,
|
|
coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_0_rsAlu$RDY_dispatchData,
|
|
coreFix_aluExe_0_rsAlu$RDY_doDispatch,
|
|
coreFix_aluExe_0_rsAlu$RDY_enq,
|
|
coreFix_aluExe_0_rsAlu$canEnq,
|
|
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_aluExe_1_dispToRegQ
|
|
reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x,
|
|
coreFix_aluExe_1_dispToRegQ$first;
|
|
wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_aluExe_1_dispToRegQ$EN_deq,
|
|
coreFix_aluExe_1_dispToRegQ$EN_enq,
|
|
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_1_dispToRegQ$RDY_deq,
|
|
coreFix_aluExe_1_dispToRegQ$RDY_enq,
|
|
coreFix_aluExe_1_dispToRegQ$RDY_first,
|
|
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_aluExe_1_exeToFinQ
|
|
reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [325 : 0] coreFix_aluExe_1_exeToFinQ$enq_x,
|
|
coreFix_aluExe_1_exeToFinQ$first;
|
|
wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_aluExe_1_exeToFinQ$EN_deq,
|
|
coreFix_aluExe_1_exeToFinQ$EN_enq,
|
|
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_1_exeToFinQ$RDY_deq,
|
|
coreFix_aluExe_1_exeToFinQ$RDY_enq,
|
|
coreFix_aluExe_1_exeToFinQ$RDY_first,
|
|
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_aluExe_1_regToExeQ
|
|
reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [389 : 0] coreFix_aluExe_1_regToExeQ$enq_x,
|
|
coreFix_aluExe_1_regToExeQ$first;
|
|
wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_aluExe_1_regToExeQ$EN_deq,
|
|
coreFix_aluExe_1_regToExeQ$EN_enq,
|
|
coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_1_regToExeQ$RDY_deq,
|
|
coreFix_aluExe_1_regToExeQ$RDY_enq,
|
|
coreFix_aluExe_1_regToExeQ$RDY_first,
|
|
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_aluExe_1_rsAlu
|
|
reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put,
|
|
coreFix_aluExe_1_rsAlu$setRegReady_4_put;
|
|
reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData,
|
|
coreFix_aluExe_1_rsAlu$enq_x;
|
|
wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask;
|
|
wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put,
|
|
coreFix_aluExe_1_rsAlu$setRegReady_1_put,
|
|
coreFix_aluExe_1_rsAlu$setRegReady_3_put;
|
|
wire [5 : 0] coreFix_aluExe_1_rsAlu$setRobEnqTime_t;
|
|
wire [4 : 0] coreFix_aluExe_1_rsAlu$approximateCount;
|
|
wire coreFix_aluExe_1_rsAlu$EN_doDispatch,
|
|
coreFix_aluExe_1_rsAlu$EN_enq,
|
|
coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put,
|
|
coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put,
|
|
coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put,
|
|
coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
|
|
coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put,
|
|
coreFix_aluExe_1_rsAlu$EN_setRobEnqTime,
|
|
coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation,
|
|
coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_aluExe_1_rsAlu$RDY_dispatchData,
|
|
coreFix_aluExe_1_rsAlu$RDY_doDispatch,
|
|
coreFix_aluExe_1_rsAlu$RDY_enq,
|
|
coreFix_aluExe_1_rsAlu$canEnq,
|
|
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
|
|
wire [130 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put;
|
|
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get;
|
|
wire coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
|
|
wire [195 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put;
|
|
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get;
|
|
wire coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
|
|
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get;
|
|
wire [66 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put;
|
|
wire coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [101 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first,
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
|
|
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata;
|
|
wire [75 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser;
|
|
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
|
|
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
|
|
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
|
|
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
|
|
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
|
|
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
|
|
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
|
|
reg [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN;
|
|
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT;
|
|
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_regToExeQ
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$EN_enq,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
|
|
reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put;
|
|
reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x;
|
|
wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask;
|
|
wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put;
|
|
wire [5 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t;
|
|
wire coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
|
|
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n;
|
|
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData;
|
|
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq;
|
|
wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr;
|
|
wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
|
|
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ;
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
|
|
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData;
|
|
wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq;
|
|
wire [1 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
|
|
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r;
|
|
reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam;
|
|
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq;
|
|
reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep;
|
|
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N;
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|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
|
|
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N;
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|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
|
|
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT;
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_dTlb
|
|
reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [174 : 0] coreFix_memExe_dTlb$procResp;
|
|
wire [105 : 0] coreFix_memExe_dTlb$procReq_req;
|
|
wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x;
|
|
wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm;
|
|
wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first;
|
|
wire [11 : 0] coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask;
|
|
wire [2 : 0] coreFix_memExe_dTlb$perf_req_r;
|
|
wire coreFix_memExe_dTlb$EN_deqProcResp,
|
|
coreFix_memExe_dTlb$EN_flush,
|
|
coreFix_memExe_dTlb$EN_perf_req,
|
|
coreFix_memExe_dTlb$EN_perf_resp,
|
|
coreFix_memExe_dTlb$EN_perf_setStatus,
|
|
coreFix_memExe_dTlb$EN_procReq,
|
|
coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation,
|
|
coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_memExe_dTlb$EN_toParent_flush_request_get,
|
|
coreFix_memExe_dTlb$EN_toParent_flush_response_put,
|
|
coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq,
|
|
coreFix_memExe_dTlb$EN_toParent_rqToP_deq,
|
|
coreFix_memExe_dTlb$EN_updateVMInfo,
|
|
coreFix_memExe_dTlb$RDY_deqProcResp,
|
|
coreFix_memExe_dTlb$RDY_flush,
|
|
coreFix_memExe_dTlb$RDY_procReq,
|
|
coreFix_memExe_dTlb$RDY_procResp,
|
|
coreFix_memExe_dTlb$RDY_toParent_flush_request_get,
|
|
coreFix_memExe_dTlb$RDY_toParent_flush_response_put,
|
|
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq,
|
|
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq,
|
|
coreFix_memExe_dTlb$RDY_toParent_rqToP_first,
|
|
coreFix_memExe_dTlb$flush_done,
|
|
coreFix_memExe_dTlb$noPendingReq,
|
|
coreFix_memExe_dTlb$perf_setStatus_doStats,
|
|
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_memExe_dispToRegQ
|
|
reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x,
|
|
coreFix_memExe_dispToRegQ$first;
|
|
wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_memExe_dispToRegQ$EN_deq,
|
|
coreFix_memExe_dispToRegQ$EN_enq,
|
|
coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_memExe_dispToRegQ$RDY_deq,
|
|
coreFix_memExe_dispToRegQ$RDY_enq,
|
|
coreFix_memExe_dispToRegQ$RDY_first,
|
|
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_forwardQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_forwardQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_forwardQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_forwardQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_forwardQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_lsq
|
|
reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [170 : 0] coreFix_memExe_lsq$firstSt;
|
|
wire [113 : 0] coreFix_memExe_lsq$firstLd;
|
|
wire [76 : 0] coreFix_memExe_lsq$getIssueLd;
|
|
wire [74 : 0] coreFix_memExe_lsq$issueLd;
|
|
wire [73 : 0] coreFix_memExe_lsq$respLd;
|
|
wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes;
|
|
wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr,
|
|
coreFix_memExe_lsq$respLd_alignedData,
|
|
coreFix_memExe_lsq$updateAddr_paddr,
|
|
coreFix_memExe_lsq$updateData_d;
|
|
wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst,
|
|
coreFix_memExe_lsq$enqSt_mem_inst;
|
|
wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag,
|
|
coreFix_memExe_lsq$enqLd_spec_bits,
|
|
coreFix_memExe_lsq$enqSt_inst_tag,
|
|
coreFix_memExe_lsq$enqSt_spec_bits,
|
|
coreFix_memExe_lsq$specUpdate_correctSpeculation_mask;
|
|
wire [9 : 0] coreFix_memExe_lsq$getHit;
|
|
wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst;
|
|
wire [7 : 0] coreFix_memExe_lsq$getOrigBE,
|
|
coreFix_memExe_lsq$issueLd_shiftedBE,
|
|
coreFix_memExe_lsq$updateAddr_shiftedBE;
|
|
wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag;
|
|
wire [5 : 0] coreFix_memExe_lsq$getHit_t,
|
|
coreFix_memExe_lsq$getOrigBE_t,
|
|
coreFix_memExe_lsq$setAtCommit_0_put,
|
|
coreFix_memExe_lsq$setAtCommit_1_put,
|
|
coreFix_memExe_lsq$updateAddr_lsqTag;
|
|
wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag,
|
|
coreFix_memExe_lsq$respLd_t,
|
|
coreFix_memExe_lsq$updateAddr_fault;
|
|
wire [3 : 0] coreFix_memExe_lsq$updateData_t;
|
|
wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx;
|
|
wire coreFix_memExe_lsq$EN_deqLd,
|
|
coreFix_memExe_lsq$EN_deqSt,
|
|
coreFix_memExe_lsq$EN_enqLd,
|
|
coreFix_memExe_lsq$EN_enqSt,
|
|
coreFix_memExe_lsq$EN_getHit,
|
|
coreFix_memExe_lsq$EN_getIssueLd,
|
|
coreFix_memExe_lsq$EN_issueLd,
|
|
coreFix_memExe_lsq$EN_respLd,
|
|
coreFix_memExe_lsq$EN_setAtCommit_0_put,
|
|
coreFix_memExe_lsq$EN_setAtCommit_1_put,
|
|
coreFix_memExe_lsq$EN_specUpdate_correctSpeculation,
|
|
coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_memExe_lsq$EN_updateAddr,
|
|
coreFix_memExe_lsq$EN_updateData,
|
|
coreFix_memExe_lsq$EN_wakeupLdStalledBySB,
|
|
coreFix_memExe_lsq$RDY_deqLd,
|
|
coreFix_memExe_lsq$RDY_deqSt,
|
|
coreFix_memExe_lsq$RDY_enqLd,
|
|
coreFix_memExe_lsq$RDY_enqSt,
|
|
coreFix_memExe_lsq$RDY_firstLd,
|
|
coreFix_memExe_lsq$RDY_firstSt,
|
|
coreFix_memExe_lsq$RDY_getIssueLd,
|
|
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all,
|
|
coreFix_memExe_lsq$stqEmpty,
|
|
coreFix_memExe_lsq$updateAddr,
|
|
coreFix_memExe_lsq$updateAddr_isMMIO;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_regToExeQ
|
|
reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [192 : 0] coreFix_memExe_regToExeQ$enq_x,
|
|
coreFix_memExe_regToExeQ$first;
|
|
wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask;
|
|
wire coreFix_memExe_regToExeQ$EN_deq,
|
|
coreFix_memExe_regToExeQ$EN_enq,
|
|
coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation,
|
|
coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_memExe_regToExeQ$RDY_deq,
|
|
coreFix_memExe_regToExeQ$RDY_enq,
|
|
coreFix_memExe_regToExeQ$RDY_first,
|
|
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
|
|
wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLdQ_data_0_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
|
|
wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLdQ_data_0_dummy2_1$EN,
|
|
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
|
|
wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLdQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
|
|
wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLdQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0
|
|
wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLdQ_empty_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1
|
|
wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLdQ_empty_dummy2_1$EN,
|
|
coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2
|
|
wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN,
|
|
coreFix_memExe_reqLdQ_empty_dummy2_2$EN,
|
|
coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
|
|
wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLdQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
|
|
wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLdQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0
|
|
wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLdQ_full_dummy2_0$EN,
|
|
coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1
|
|
wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLdQ_full_dummy2_1$EN,
|
|
coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2
|
|
wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN,
|
|
coreFix_memExe_reqLdQ_full_dummy2_2$EN,
|
|
coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
|
|
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
|
|
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
|
|
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
|
|
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
|
|
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
|
|
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN,
|
|
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
|
|
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN,
|
|
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
|
|
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
|
|
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
|
|
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN,
|
|
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
|
|
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN,
|
|
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
|
|
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN,
|
|
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN,
|
|
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0
|
|
wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN,
|
|
coreFix_memExe_reqStQ_data_0_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1
|
|
wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN,
|
|
coreFix_memExe_reqStQ_data_0_dummy2_1$EN,
|
|
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0
|
|
wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN,
|
|
coreFix_memExe_reqStQ_deqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1
|
|
wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN,
|
|
coreFix_memExe_reqStQ_deqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0
|
|
wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN,
|
|
coreFix_memExe_reqStQ_empty_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1
|
|
wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN,
|
|
coreFix_memExe_reqStQ_empty_dummy2_1$EN,
|
|
coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2
|
|
wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN,
|
|
coreFix_memExe_reqStQ_empty_dummy2_2$EN,
|
|
coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0
|
|
wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN,
|
|
coreFix_memExe_reqStQ_enqP_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1
|
|
wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN,
|
|
coreFix_memExe_reqStQ_enqP_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_0
|
|
wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN,
|
|
coreFix_memExe_reqStQ_full_dummy2_0$EN,
|
|
coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_1
|
|
wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN,
|
|
coreFix_memExe_reqStQ_full_dummy2_1$EN,
|
|
coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_2
|
|
wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN,
|
|
coreFix_memExe_reqStQ_full_dummy2_2$EN,
|
|
coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
|
|
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
|
|
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN,
|
|
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
|
|
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
|
|
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
|
|
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN,
|
|
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
|
|
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
|
|
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
|
|
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN,
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN,
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule coreFix_memExe_rsMem
|
|
reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put,
|
|
coreFix_memExe_rsMem$setRegReady_4_put;
|
|
reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [106 : 0] coreFix_memExe_rsMem$dispatchData,
|
|
coreFix_memExe_rsMem$enq_x;
|
|
wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask;
|
|
wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put,
|
|
coreFix_memExe_rsMem$setRegReady_1_put,
|
|
coreFix_memExe_rsMem$setRegReady_3_put;
|
|
wire [5 : 0] coreFix_memExe_rsMem$setRobEnqTime_t;
|
|
wire coreFix_memExe_rsMem$EN_doDispatch,
|
|
coreFix_memExe_rsMem$EN_enq,
|
|
coreFix_memExe_rsMem$EN_setRegReady_0_put,
|
|
coreFix_memExe_rsMem$EN_setRegReady_1_put,
|
|
coreFix_memExe_rsMem$EN_setRegReady_2_put,
|
|
coreFix_memExe_rsMem$EN_setRegReady_3_put,
|
|
coreFix_memExe_rsMem$EN_setRegReady_4_put,
|
|
coreFix_memExe_rsMem$EN_setRobEnqTime,
|
|
coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation,
|
|
coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation,
|
|
coreFix_memExe_rsMem$RDY_dispatchData,
|
|
coreFix_memExe_rsMem$RDY_doDispatch,
|
|
coreFix_memExe_rsMem$RDY_enq,
|
|
coreFix_memExe_rsMem$canEnq,
|
|
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule coreFix_memExe_stb
|
|
wire [635 : 0] coreFix_memExe_stb$issue;
|
|
wire [633 : 0] coreFix_memExe_stb$deq;
|
|
wire [67 : 0] coreFix_memExe_stb$search;
|
|
wire [63 : 0] coreFix_memExe_stb$enq_data,
|
|
coreFix_memExe_stb$enq_paddr,
|
|
coreFix_memExe_stb$getEnqIndex_paddr,
|
|
coreFix_memExe_stb$noMatchLdQ_paddr,
|
|
coreFix_memExe_stb$noMatchStQ_paddr,
|
|
coreFix_memExe_stb$search_paddr;
|
|
wire [7 : 0] coreFix_memExe_stb$enq_be,
|
|
coreFix_memExe_stb$noMatchLdQ_be,
|
|
coreFix_memExe_stb$noMatchStQ_be,
|
|
coreFix_memExe_stb$search_be;
|
|
wire [2 : 0] coreFix_memExe_stb$getEnqIndex;
|
|
wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx;
|
|
wire coreFix_memExe_stb$EN_deq,
|
|
coreFix_memExe_stb$EN_enq,
|
|
coreFix_memExe_stb$EN_issue,
|
|
coreFix_memExe_stb$RDY_deq,
|
|
coreFix_memExe_stb$RDY_enq,
|
|
coreFix_memExe_stb$RDY_issue,
|
|
coreFix_memExe_stb$isEmpty,
|
|
coreFix_memExe_stb$noMatchLdQ,
|
|
coreFix_memExe_stb$noMatchStQ;
|
|
|
|
// ports of submodule coreFix_trainBPQ_0
|
|
wire [158 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT;
|
|
wire coreFix_trainBPQ_0$CLR,
|
|
coreFix_trainBPQ_0$DEQ,
|
|
coreFix_trainBPQ_0$EMPTY_N,
|
|
coreFix_trainBPQ_0$ENQ,
|
|
coreFix_trainBPQ_0$FULL_N;
|
|
|
|
// ports of submodule coreFix_trainBPQ_1
|
|
wire [158 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT;
|
|
wire coreFix_trainBPQ_1$CLR,
|
|
coreFix_trainBPQ_1$DEQ,
|
|
coreFix_trainBPQ_1$EMPTY_N,
|
|
coreFix_trainBPQ_1$ENQ,
|
|
coreFix_trainBPQ_1$FULL_N;
|
|
|
|
// ports of submodule csrInstOrInterruptInflight_dummy2_0
|
|
wire csrInstOrInterruptInflight_dummy2_0$D_IN,
|
|
csrInstOrInterruptInflight_dummy2_0$EN,
|
|
csrInstOrInterruptInflight_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule csrInstOrInterruptInflight_dummy2_1
|
|
wire csrInstOrInterruptInflight_dummy2_1$D_IN,
|
|
csrInstOrInterruptInflight_dummy2_1$EN,
|
|
csrInstOrInterruptInflight_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule csrf_mcycle_ehr_data_dummy2_0
|
|
wire csrf_mcycle_ehr_data_dummy2_0$D_IN,
|
|
csrf_mcycle_ehr_data_dummy2_0$EN,
|
|
csrf_mcycle_ehr_data_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule csrf_mcycle_ehr_data_dummy2_1
|
|
wire csrf_mcycle_ehr_data_dummy2_1$D_IN,
|
|
csrf_mcycle_ehr_data_dummy2_1$EN,
|
|
csrf_mcycle_ehr_data_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule csrf_minstret_ehr_data_dummy2_0
|
|
wire csrf_minstret_ehr_data_dummy2_0$D_IN,
|
|
csrf_minstret_ehr_data_dummy2_0$EN,
|
|
csrf_minstret_ehr_data_dummy2_0$Q_OUT;
|
|
|
|
// ports of submodule csrf_minstret_ehr_data_dummy2_1
|
|
wire csrf_minstret_ehr_data_dummy2_1$D_IN,
|
|
csrf_minstret_ehr_data_dummy2_1$EN,
|
|
csrf_minstret_ehr_data_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule csrf_stats_module_writeQ
|
|
wire csrf_stats_module_writeQ$CLR,
|
|
csrf_stats_module_writeQ$DEQ,
|
|
csrf_stats_module_writeQ$D_IN,
|
|
csrf_stats_module_writeQ$D_OUT,
|
|
csrf_stats_module_writeQ$EMPTY_N,
|
|
csrf_stats_module_writeQ$ENQ,
|
|
csrf_stats_module_writeQ$FULL_N;
|
|
|
|
// ports of submodule csrf_terminate_module_terminateQ
|
|
wire csrf_terminate_module_terminateQ$CLR,
|
|
csrf_terminate_module_terminateQ$DEQ,
|
|
csrf_terminate_module_terminateQ$EMPTY_N,
|
|
csrf_terminate_module_terminateQ$ENQ,
|
|
csrf_terminate_module_terminateQ$FULL_N;
|
|
|
|
// ports of submodule epochManager
|
|
wire [3 : 0] epochManager$checkEpoch_0_check_e,
|
|
epochManager$checkEpoch_1_check_e,
|
|
epochManager$updatePrevEpoch_0_update_e,
|
|
epochManager$updatePrevEpoch_1_update_e;
|
|
wire epochManager$EN_incrementEpoch,
|
|
epochManager$EN_updatePrevEpoch_0_update,
|
|
epochManager$EN_updatePrevEpoch_1_update,
|
|
epochManager$RDY_incrementEpoch,
|
|
epochManager$checkEpoch_0_check,
|
|
epochManager$checkEpoch_1_check;
|
|
|
|
// ports of submodule fetchStage
|
|
reg [63 : 0] fetchStage$redirect_pc;
|
|
wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x;
|
|
wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first;
|
|
wire [291 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first;
|
|
wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x;
|
|
wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first;
|
|
wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get,
|
|
fetchStage$iMemIfc_pRqStuck_get;
|
|
wire [65 : 0] fetchStage$mmioIfc_instResp_enq_x;
|
|
wire [63 : 0] fetchStage$iMemIfc_to_proc_request_put,
|
|
fetchStage$iTlbIfc_to_proc_request_put,
|
|
fetchStage$mmioIfc_instReq_first_fst,
|
|
fetchStage$mmioIfc_setHtifAddrs_fromHost,
|
|
fetchStage$mmioIfc_setHtifAddrs_toHost,
|
|
fetchStage$start_pc,
|
|
fetchStage$train_predictors_next_pc,
|
|
fetchStage$train_predictors_pc;
|
|
wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm;
|
|
wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first;
|
|
wire [23 : 0] fetchStage$train_predictors_dpTrain;
|
|
wire [4 : 0] fetchStage$train_predictors_iType;
|
|
wire [2 : 0] fetchStage$iTlbIfc_perf_req_r;
|
|
wire [1 : 0] fetchStage$iMemIfc_perf_req_r, fetchStage$perf_req_r;
|
|
wire fetchStage$EN_done_flushing,
|
|
fetchStage$EN_flush_predictors,
|
|
fetchStage$EN_iMemIfc_cRqStuck_get,
|
|
fetchStage$EN_iMemIfc_flush,
|
|
fetchStage$EN_iMemIfc_pRqStuck_get,
|
|
fetchStage$EN_iMemIfc_perf_req,
|
|
fetchStage$EN_iMemIfc_perf_resp,
|
|
fetchStage$EN_iMemIfc_perf_setStatus,
|
|
fetchStage$EN_iMemIfc_to_parent_fromP_enq,
|
|
fetchStage$EN_iMemIfc_to_parent_rqToP_deq,
|
|
fetchStage$EN_iMemIfc_to_parent_rsToP_deq,
|
|
fetchStage$EN_iMemIfc_to_proc_request_put,
|
|
fetchStage$EN_iMemIfc_to_proc_response_get,
|
|
fetchStage$EN_iTlbIfc_flush,
|
|
fetchStage$EN_iTlbIfc_perf_req,
|
|
fetchStage$EN_iTlbIfc_perf_resp,
|
|
fetchStage$EN_iTlbIfc_perf_setStatus,
|
|
fetchStage$EN_iTlbIfc_toParent_flush_request_get,
|
|
fetchStage$EN_iTlbIfc_toParent_flush_response_put,
|
|
fetchStage$EN_iTlbIfc_toParent_rqToP_deq,
|
|
fetchStage$EN_iTlbIfc_toParent_rsFromP_enq,
|
|
fetchStage$EN_iTlbIfc_to_proc_request_put,
|
|
fetchStage$EN_iTlbIfc_to_proc_response_get,
|
|
fetchStage$EN_iTlbIfc_updateVMInfo,
|
|
fetchStage$EN_mmioIfc_instReq_deq,
|
|
fetchStage$EN_mmioIfc_instResp_enq,
|
|
fetchStage$EN_mmioIfc_setHtifAddrs,
|
|
fetchStage$EN_perf_req,
|
|
fetchStage$EN_perf_resp,
|
|
fetchStage$EN_perf_setStatus,
|
|
fetchStage$EN_pipelines_0_deq,
|
|
fetchStage$EN_pipelines_1_deq,
|
|
fetchStage$EN_redirect,
|
|
fetchStage$EN_setWaitRedirect,
|
|
fetchStage$EN_start,
|
|
fetchStage$EN_stop,
|
|
fetchStage$EN_train_predictors,
|
|
fetchStage$RDY_done_flushing,
|
|
fetchStage$RDY_iMemIfc_cRqStuck_get,
|
|
fetchStage$RDY_iMemIfc_pRqStuck_get,
|
|
fetchStage$RDY_iMemIfc_to_parent_fromP_enq,
|
|
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq,
|
|
fetchStage$RDY_iMemIfc_to_parent_rqToP_first,
|
|
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq,
|
|
fetchStage$RDY_iMemIfc_to_parent_rsToP_first,
|
|
fetchStage$RDY_iTlbIfc_flush,
|
|
fetchStage$RDY_iTlbIfc_toParent_flush_request_get,
|
|
fetchStage$RDY_iTlbIfc_toParent_flush_response_put,
|
|
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq,
|
|
fetchStage$RDY_iTlbIfc_toParent_rqToP_first,
|
|
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq,
|
|
fetchStage$RDY_mmioIfc_instReq_deq,
|
|
fetchStage$RDY_mmioIfc_instReq_first_fst,
|
|
fetchStage$RDY_mmioIfc_instReq_first_snd,
|
|
fetchStage$RDY_mmioIfc_instResp_enq,
|
|
fetchStage$RDY_pipelines_0_deq,
|
|
fetchStage$RDY_pipelines_0_first,
|
|
fetchStage$RDY_pipelines_1_deq,
|
|
fetchStage$RDY_pipelines_1_first,
|
|
fetchStage$iMemIfc_perf_setStatus_doStats,
|
|
fetchStage$iMemIfc_to_parent_fromP_notFull,
|
|
fetchStage$iMemIfc_to_parent_rqToP_notEmpty,
|
|
fetchStage$iMemIfc_to_parent_rsToP_notEmpty,
|
|
fetchStage$iTlbIfc_flush_done,
|
|
fetchStage$iTlbIfc_noPendingReq,
|
|
fetchStage$iTlbIfc_perf_setStatus_doStats,
|
|
fetchStage$mmioIfc_instReq_first_snd,
|
|
fetchStage$perf_setStatus_doStats,
|
|
fetchStage$pipelines_0_canDeq,
|
|
fetchStage$pipelines_1_canDeq,
|
|
fetchStage$train_predictors_mispred,
|
|
fetchStage$train_predictors_taken;
|
|
|
|
// ports of submodule l2Tlb
|
|
wire [83 : 0] l2Tlb$toChildren_rsToC_first;
|
|
wire [64 : 0] l2Tlb$toMem_memReq_first, l2Tlb$toMem_respLd_enq_x;
|
|
wire [48 : 0] l2Tlb$updateVMInfo_vmD, l2Tlb$updateVMInfo_vmI;
|
|
wire [29 : 0] l2Tlb$toChildren_rqFromC_put;
|
|
wire [3 : 0] l2Tlb$perf_req_r;
|
|
wire l2Tlb$EN_perf_req,
|
|
l2Tlb$EN_perf_resp,
|
|
l2Tlb$EN_perf_setStatus,
|
|
l2Tlb$EN_toChildren_dTlbReqFlush_put,
|
|
l2Tlb$EN_toChildren_flushDone_get,
|
|
l2Tlb$EN_toChildren_iTlbReqFlush_put,
|
|
l2Tlb$EN_toChildren_rqFromC_put,
|
|
l2Tlb$EN_toChildren_rsToC_deq,
|
|
l2Tlb$EN_toMem_memReq_deq,
|
|
l2Tlb$EN_toMem_respLd_enq,
|
|
l2Tlb$EN_updateVMInfo,
|
|
l2Tlb$RDY_toChildren_dTlbReqFlush_put,
|
|
l2Tlb$RDY_toChildren_flushDone_get,
|
|
l2Tlb$RDY_toChildren_iTlbReqFlush_put,
|
|
l2Tlb$RDY_toChildren_rqFromC_put,
|
|
l2Tlb$RDY_toChildren_rsToC_deq,
|
|
l2Tlb$RDY_toChildren_rsToC_first,
|
|
l2Tlb$RDY_toMem_memReq_deq,
|
|
l2Tlb$RDY_toMem_memReq_first,
|
|
l2Tlb$RDY_toMem_respLd_enq,
|
|
l2Tlb$perf_setStatus_doStats,
|
|
l2Tlb$toMem_memReq_notEmpty,
|
|
l2Tlb$toMem_respLd_notFull;
|
|
|
|
// ports of submodule mmio_cRqQ_clearReq_dummy2_0
|
|
wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_cRqQ_clearReq_dummy2_1
|
|
wire mmio_cRqQ_clearReq_dummy2_1$D_IN,
|
|
mmio_cRqQ_clearReq_dummy2_1$EN,
|
|
mmio_cRqQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule mmio_cRqQ_deqReq_dummy2_0
|
|
wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_cRqQ_deqReq_dummy2_1
|
|
wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule mmio_cRqQ_deqReq_dummy2_2
|
|
wire mmio_cRqQ_deqReq_dummy2_2$D_IN,
|
|
mmio_cRqQ_deqReq_dummy2_2$EN,
|
|
mmio_cRqQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule mmio_cRqQ_enqReq_dummy2_0
|
|
wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_cRqQ_enqReq_dummy2_1
|
|
wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule mmio_cRqQ_enqReq_dummy2_2
|
|
wire mmio_cRqQ_enqReq_dummy2_2$D_IN,
|
|
mmio_cRqQ_enqReq_dummy2_2$EN,
|
|
mmio_cRqQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule mmio_cRsQ_clearReq_dummy2_0
|
|
wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_cRsQ_clearReq_dummy2_1
|
|
wire mmio_cRsQ_clearReq_dummy2_1$D_IN,
|
|
mmio_cRsQ_clearReq_dummy2_1$EN,
|
|
mmio_cRsQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule mmio_cRsQ_deqReq_dummy2_0
|
|
wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_cRsQ_deqReq_dummy2_1
|
|
wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule mmio_cRsQ_deqReq_dummy2_2
|
|
wire mmio_cRsQ_deqReq_dummy2_2$D_IN,
|
|
mmio_cRsQ_deqReq_dummy2_2$EN,
|
|
mmio_cRsQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule mmio_cRsQ_enqReq_dummy2_0
|
|
wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_cRsQ_enqReq_dummy2_1
|
|
wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule mmio_cRsQ_enqReq_dummy2_2
|
|
wire mmio_cRsQ_enqReq_dummy2_2$D_IN,
|
|
mmio_cRsQ_enqReq_dummy2_2$EN,
|
|
mmio_cRsQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule mmio_dataPendQ_clearReq_dummy2_0
|
|
wire mmio_dataPendQ_clearReq_dummy2_0$D_IN,
|
|
mmio_dataPendQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_dataPendQ_clearReq_dummy2_1
|
|
wire mmio_dataPendQ_clearReq_dummy2_1$D_IN,
|
|
mmio_dataPendQ_clearReq_dummy2_1$EN,
|
|
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule mmio_dataPendQ_deqReq_dummy2_0
|
|
wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_dataPendQ_deqReq_dummy2_1
|
|
wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule mmio_dataPendQ_deqReq_dummy2_2
|
|
wire mmio_dataPendQ_deqReq_dummy2_2$D_IN,
|
|
mmio_dataPendQ_deqReq_dummy2_2$EN,
|
|
mmio_dataPendQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule mmio_dataPendQ_enqReq_dummy2_0
|
|
wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_dataPendQ_enqReq_dummy2_1
|
|
wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule mmio_dataPendQ_enqReq_dummy2_2
|
|
wire mmio_dataPendQ_enqReq_dummy2_2$D_IN,
|
|
mmio_dataPendQ_enqReq_dummy2_2$EN,
|
|
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule mmio_dataReqQ_clearReq_dummy2_0
|
|
wire mmio_dataReqQ_clearReq_dummy2_0$D_IN,
|
|
mmio_dataReqQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_dataReqQ_clearReq_dummy2_1
|
|
wire mmio_dataReqQ_clearReq_dummy2_1$D_IN,
|
|
mmio_dataReqQ_clearReq_dummy2_1$EN,
|
|
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule mmio_dataReqQ_deqReq_dummy2_0
|
|
wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_dataReqQ_deqReq_dummy2_1
|
|
wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule mmio_dataReqQ_deqReq_dummy2_2
|
|
wire mmio_dataReqQ_deqReq_dummy2_2$D_IN,
|
|
mmio_dataReqQ_deqReq_dummy2_2$EN,
|
|
mmio_dataReqQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule mmio_dataReqQ_enqReq_dummy2_0
|
|
wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule mmio_dataReqQ_enqReq_dummy2_1
|
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wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN;
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// ports of submodule mmio_dataReqQ_enqReq_dummy2_2
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wire mmio_dataReqQ_enqReq_dummy2_2$D_IN,
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mmio_dataReqQ_enqReq_dummy2_2$EN,
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mmio_dataReqQ_enqReq_dummy2_2$Q_OUT;
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// ports of submodule mmio_dataRespQ_clearReq_dummy2_0
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wire mmio_dataRespQ_clearReq_dummy2_0$D_IN,
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mmio_dataRespQ_clearReq_dummy2_0$EN;
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// ports of submodule mmio_dataRespQ_clearReq_dummy2_1
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wire mmio_dataRespQ_clearReq_dummy2_1$D_IN,
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mmio_dataRespQ_clearReq_dummy2_1$EN,
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mmio_dataRespQ_clearReq_dummy2_1$Q_OUT;
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// ports of submodule mmio_dataRespQ_deqReq_dummy2_0
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wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN;
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// ports of submodule mmio_dataRespQ_deqReq_dummy2_1
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wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN;
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// ports of submodule mmio_dataRespQ_deqReq_dummy2_2
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wire mmio_dataRespQ_deqReq_dummy2_2$D_IN,
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mmio_dataRespQ_deqReq_dummy2_2$EN,
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mmio_dataRespQ_deqReq_dummy2_2$Q_OUT;
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// ports of submodule mmio_dataRespQ_enqReq_dummy2_0
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wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN;
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// ports of submodule mmio_dataRespQ_enqReq_dummy2_1
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wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN;
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// ports of submodule mmio_dataRespQ_enqReq_dummy2_2
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wire mmio_dataRespQ_enqReq_dummy2_2$D_IN,
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mmio_dataRespQ_enqReq_dummy2_2$EN,
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mmio_dataRespQ_enqReq_dummy2_2$Q_OUT;
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// ports of submodule mmio_pRqQ_clearReq_dummy2_0
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wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN;
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// ports of submodule mmio_pRqQ_clearReq_dummy2_1
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wire mmio_pRqQ_clearReq_dummy2_1$D_IN,
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mmio_pRqQ_clearReq_dummy2_1$EN,
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mmio_pRqQ_clearReq_dummy2_1$Q_OUT;
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// ports of submodule mmio_pRqQ_deqReq_dummy2_0
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wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN;
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// ports of submodule mmio_pRqQ_deqReq_dummy2_1
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wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN;
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// ports of submodule mmio_pRqQ_deqReq_dummy2_2
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wire mmio_pRqQ_deqReq_dummy2_2$D_IN,
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mmio_pRqQ_deqReq_dummy2_2$EN,
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mmio_pRqQ_deqReq_dummy2_2$Q_OUT;
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// ports of submodule mmio_pRqQ_enqReq_dummy2_0
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wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN;
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// ports of submodule mmio_pRqQ_enqReq_dummy2_1
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wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN;
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// ports of submodule mmio_pRqQ_enqReq_dummy2_2
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wire mmio_pRqQ_enqReq_dummy2_2$D_IN,
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mmio_pRqQ_enqReq_dummy2_2$EN,
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mmio_pRqQ_enqReq_dummy2_2$Q_OUT;
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// ports of submodule mmio_pRsQ_clearReq_dummy2_0
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wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN;
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// ports of submodule mmio_pRsQ_clearReq_dummy2_1
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wire mmio_pRsQ_clearReq_dummy2_1$D_IN,
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mmio_pRsQ_clearReq_dummy2_1$EN,
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mmio_pRsQ_clearReq_dummy2_1$Q_OUT;
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// ports of submodule mmio_pRsQ_deqReq_dummy2_0
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wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN;
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// ports of submodule mmio_pRsQ_deqReq_dummy2_1
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wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN;
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// ports of submodule mmio_pRsQ_deqReq_dummy2_2
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wire mmio_pRsQ_deqReq_dummy2_2$D_IN,
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mmio_pRsQ_deqReq_dummy2_2$EN,
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mmio_pRsQ_deqReq_dummy2_2$Q_OUT;
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// ports of submodule mmio_pRsQ_enqReq_dummy2_0
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wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN;
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// ports of submodule mmio_pRsQ_enqReq_dummy2_1
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wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN;
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// ports of submodule mmio_pRsQ_enqReq_dummy2_2
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wire mmio_pRsQ_enqReq_dummy2_2$D_IN,
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mmio_pRsQ_enqReq_dummy2_2$EN,
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mmio_pRsQ_enqReq_dummy2_2$Q_OUT;
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// ports of submodule perfReqQ
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wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT;
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wire perfReqQ$CLR,
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perfReqQ$DEQ,
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perfReqQ$EMPTY_N,
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perfReqQ$ENQ,
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perfReqQ$FULL_N;
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// ports of submodule regRenamingTable
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reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag;
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wire [32 : 0] regRenamingTable$rename_0_getRename,
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regRenamingTable$rename_1_getRename;
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wire [26 : 0] regRenamingTable$rename_0_claimRename_r,
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regRenamingTable$rename_0_getRename_r,
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regRenamingTable$rename_1_claimRename_r,
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regRenamingTable$rename_1_getRename_r;
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wire [11 : 0] regRenamingTable$rename_0_claimRename_sb,
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regRenamingTable$rename_1_claimRename_sb,
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regRenamingTable$specUpdate_correctSpeculation_mask;
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wire regRenamingTable$EN_commit_0_commit,
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regRenamingTable$EN_commit_1_commit,
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regRenamingTable$EN_rename_0_claimRename,
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regRenamingTable$EN_rename_1_claimRename,
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regRenamingTable$EN_specUpdate_correctSpeculation,
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regRenamingTable$EN_specUpdate_incorrectSpeculation,
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regRenamingTable$RDY_commit_0_commit,
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regRenamingTable$RDY_commit_1_commit,
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regRenamingTable$RDY_rename_0_claimRename,
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regRenamingTable$RDY_rename_0_getRename,
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regRenamingTable$RDY_rename_1_claimRename,
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regRenamingTable$RDY_rename_1_getRename,
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regRenamingTable$rename_0_canRename,
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regRenamingTable$rename_1_canRename,
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regRenamingTable$specUpdate_incorrectSpeculation_kill_all;
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// ports of submodule rf
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reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data;
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reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx;
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wire [63 : 0] rf$read_0_rd1,
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rf$read_0_rd2,
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rf$read_1_rd1,
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rf$read_1_rd2,
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rf$read_2_rd1,
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rf$read_2_rd2,
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rf$read_2_rd3,
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rf$read_3_rd1,
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rf$read_3_rd2,
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rf$write_0_wr_data,
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rf$write_1_wr_data;
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wire [6 : 0] rf$read_0_rd1_rindx,
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rf$read_0_rd2_rindx,
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rf$read_0_rd3_rindx,
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rf$read_1_rd1_rindx,
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rf$read_1_rd2_rindx,
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rf$read_1_rd3_rindx,
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rf$read_2_rd1_rindx,
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rf$read_2_rd2_rindx,
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rf$read_2_rd3_rindx,
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rf$read_3_rd1_rindx,
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rf$read_3_rd2_rindx,
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rf$read_3_rd3_rindx,
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rf$write_0_wr_rindx,
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rf$write_1_wr_rindx;
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wire rf$EN_write_0_wr, rf$EN_write_1_wr, rf$EN_write_2_wr, rf$EN_write_3_wr;
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// ports of submodule rob
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reg [186 : 0] rob$enqPort_0_enq_x;
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reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x,
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rob$specUpdate_incorrectSpeculation_inst_tag;
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reg [4 : 0] rob$setExecuted_deqLSQ_cause,
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rob$setExecuted_doFinishFpuMulDiv_0_set_fflags;
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reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag;
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wire [186 : 0] rob$deqPort_0_deq_data,
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rob$deqPort_1_deq_data,
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rob$enqPort_1_enq_x;
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wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf,
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rob$setExecuted_doFinishAlu_1_set_cf;
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wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData,
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rob$setExecuted_doFinishAlu_1_set_csrData;
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wire [63 : 0] rob$getOrigPC_0_get,
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rob$getOrigPC_1_get,
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rob$getOrigPredPC_0_get,
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rob$getOrigPredPC_1_get,
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rob$setExecuted_doFinishMem_vaddr;
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wire [11 : 0] rob$deqPort_0_getDeqInstTag,
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rob$enqPort_0_getEnqInstTag,
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rob$enqPort_1_getEnqInstTag,
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rob$getOrigPC_0_get_x,
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rob$getOrigPC_1_get_x,
|
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rob$getOrigPC_2_get_x,
|
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rob$getOrigPredPC_0_get_x,
|
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rob$getOrigPredPC_1_get_x,
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rob$setExecuted_deqLSQ_x,
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rob$setExecuted_doFinishAlu_0_set_x,
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rob$setExecuted_doFinishAlu_1_set_x,
|
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rob$setExecuted_doFinishMem_x,
|
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rob$setLSQAtCommitNotified_x,
|
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rob$specUpdate_correctSpeculation_mask;
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wire [5 : 0] rob$getEnqTime;
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wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed;
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wire rob$EN_deqPort_0_deq,
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rob$EN_deqPort_1_deq,
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rob$EN_enqPort_0_enq,
|
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rob$EN_enqPort_1_enq,
|
|
rob$EN_setExecuted_deqLSQ,
|
|
rob$EN_setExecuted_doFinishAlu_0_set,
|
|
rob$EN_setExecuted_doFinishAlu_1_set,
|
|
rob$EN_setExecuted_doFinishFpuMulDiv_0_set,
|
|
rob$EN_setExecuted_doFinishMem,
|
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rob$EN_setLSQAtCommitNotified,
|
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rob$EN_specUpdate_correctSpeculation,
|
|
rob$EN_specUpdate_incorrectSpeculation,
|
|
rob$RDY_deqPort_0_deq,
|
|
rob$RDY_deqPort_0_deq_data,
|
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rob$RDY_deqPort_1_deq,
|
|
rob$RDY_deqPort_1_deq_data,
|
|
rob$RDY_enqPort_0_enq,
|
|
rob$RDY_enqPort_1_enq,
|
|
rob$RDY_setExecuted_deqLSQ,
|
|
rob$RDY_setExecuted_doFinishAlu_0_set,
|
|
rob$RDY_setExecuted_doFinishAlu_1_set,
|
|
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set,
|
|
rob$RDY_setExecuted_doFinishMem,
|
|
rob$RDY_setLSQAtCommitNotified,
|
|
rob$deqPort_0_canDeq,
|
|
rob$deqPort_1_canDeq,
|
|
rob$enqPort_0_canEnq,
|
|
rob$enqPort_1_canEnq,
|
|
rob$isEmpty,
|
|
rob$setExecuted_doFinishMem_access_at_commit,
|
|
rob$setExecuted_doFinishMem_non_mmio_st_done,
|
|
rob$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// ports of submodule sbAggr
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reg [6 : 0] sbAggr$setReady_2_put, sbAggr$setReady_4_put;
|
|
wire [32 : 0] sbAggr$eagerLookup_0_get_r, sbAggr$eagerLookup_1_get_r;
|
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wire [8 : 0] sbAggr$setBusy_0_set_dst, sbAggr$setBusy_1_set_dst;
|
|
wire [6 : 0] sbAggr$setReady_0_put,
|
|
sbAggr$setReady_1_put,
|
|
sbAggr$setReady_3_put;
|
|
wire [3 : 0] sbAggr$eagerLookup_0_get, sbAggr$eagerLookup_1_get;
|
|
wire sbAggr$EN_setBusy_0_set,
|
|
sbAggr$EN_setBusy_1_set,
|
|
sbAggr$EN_setReady_0_put,
|
|
sbAggr$EN_setReady_1_put,
|
|
sbAggr$EN_setReady_2_put,
|
|
sbAggr$EN_setReady_3_put,
|
|
sbAggr$EN_setReady_4_put;
|
|
|
|
// ports of submodule sbCons
|
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reg [6 : 0] sbCons$setReady_2_put, sbCons$setReady_3_put;
|
|
wire [32 : 0] sbCons$eagerLookup_0_get_r,
|
|
sbCons$eagerLookup_1_get_r,
|
|
sbCons$lazyLookup_0_get_r,
|
|
sbCons$lazyLookup_1_get_r,
|
|
sbCons$lazyLookup_2_get_r,
|
|
sbCons$lazyLookup_3_get_r;
|
|
wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst;
|
|
wire [6 : 0] sbCons$setReady_0_put, sbCons$setReady_1_put;
|
|
wire [3 : 0] sbCons$lazyLookup_0_get,
|
|
sbCons$lazyLookup_1_get,
|
|
sbCons$lazyLookup_2_get,
|
|
sbCons$lazyLookup_3_get;
|
|
wire sbCons$EN_setBusy_0_set,
|
|
sbCons$EN_setBusy_1_set,
|
|
sbCons$EN_setReady_0_put,
|
|
sbCons$EN_setReady_1_put,
|
|
sbCons$EN_setReady_2_put,
|
|
sbCons$EN_setReady_3_put;
|
|
|
|
// ports of submodule specTagManager
|
|
reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag;
|
|
wire [11 : 0] specTagManager$currentSpecBits,
|
|
specTagManager$specUpdate_correctSpeculation_mask;
|
|
wire [3 : 0] specTagManager$nextSpecTag;
|
|
wire specTagManager$EN_claimSpecTag,
|
|
specTagManager$EN_specUpdate_correctSpeculation,
|
|
specTagManager$EN_specUpdate_incorrectSpeculation,
|
|
specTagManager$RDY_claimSpecTag,
|
|
specTagManager$RDY_nextSpecTag,
|
|
specTagManager$canClaim,
|
|
specTagManager$specUpdate_incorrectSpeculation_kill_all;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_commitStage_doCommitKilledLd,
|
|
CAN_FIRE_RL_commitStage_doCommitNormalInst,
|
|
CAN_FIRE_RL_commitStage_doCommitSystemInst,
|
|
CAN_FIRE_RL_commitStage_doCommitTrap_flush,
|
|
CAN_FIRE_RL_commitStage_doCommitTrap_handle,
|
|
CAN_FIRE_RL_commitStage_doSetLSQAtCommit,
|
|
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1,
|
|
CAN_FIRE_RL_commitStage_notifyLSQCommit,
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu,
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu,
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
|
|
CAN_FIRE_RL_coreFix_doFetchTrainBP,
|
|
CAN_FIRE_RL_coreFix_doFetchTrainBP_1,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
|
|
CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
|
|
CAN_FIRE_RL_coreFix_memExe_doDispatchMem,
|
|
CAN_FIRE_RL_coreFix_memExe_doExeMem,
|
|
CAN_FIRE_RL_coreFix_memExe_doFinishMem,
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB,
|
|
CAN_FIRE_RL_coreFix_memExe_doRegReadMem,
|
|
CAN_FIRE_RL_coreFix_memExe_doRespLdForward,
|
|
CAN_FIRE_RL_coreFix_memExe_doRespLdMem,
|
|
CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
|
|
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
|
|
CAN_FIRE_RL_coreFix_memExe_sendLdToMem,
|
|
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
|
|
CAN_FIRE_RL_coreFix_memExe_sendStToMem,
|
|
CAN_FIRE_RL_csrInstOrInterruptInflight_canon,
|
|
CAN_FIRE_RL_csrf_incCycle,
|
|
CAN_FIRE_RL_csrf_mcycle_ehr_data_canon,
|
|
CAN_FIRE_RL_csrf_mcycle_ehr_setRead,
|
|
CAN_FIRE_RL_csrf_minstret_ehr_data_canon,
|
|
CAN_FIRE_RL_csrf_minstret_ehr_setRead,
|
|
CAN_FIRE_RL_mkConnectionGetPut,
|
|
CAN_FIRE_RL_mkConnectionGetPut_1,
|
|
CAN_FIRE_RL_mmio_cRqQ_canonicalize,
|
|
CAN_FIRE_RL_mmio_cRqQ_clearReq_canon,
|
|
CAN_FIRE_RL_mmio_cRqQ_deqReq_canon,
|
|
CAN_FIRE_RL_mmio_cRqQ_enqReq_canon,
|
|
CAN_FIRE_RL_mmio_cRsQ_canonicalize,
|
|
CAN_FIRE_RL_mmio_cRsQ_clearReq_canon,
|
|
CAN_FIRE_RL_mmio_cRsQ_deqReq_canon,
|
|
CAN_FIRE_RL_mmio_cRsQ_enqReq_canon,
|
|
CAN_FIRE_RL_mmio_dataPendQ_canonicalize,
|
|
CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon,
|
|
CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon,
|
|
CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon,
|
|
CAN_FIRE_RL_mmio_dataReqQ_canonicalize,
|
|
CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_mmio_dataRespQ_canonicalize,
|
|
CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon,
|
|
CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon,
|
|
CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon,
|
|
CAN_FIRE_RL_mmio_handlePRq,
|
|
CAN_FIRE_RL_mmio_pRqQ_canonicalize,
|
|
CAN_FIRE_RL_mmio_pRqQ_clearReq_canon,
|
|
CAN_FIRE_RL_mmio_pRqQ_deqReq_canon,
|
|
CAN_FIRE_RL_mmio_pRqQ_enqReq_canon,
|
|
CAN_FIRE_RL_mmio_pRsQ_canonicalize,
|
|
CAN_FIRE_RL_mmio_pRsQ_clearReq_canon,
|
|
CAN_FIRE_RL_mmio_pRsQ_deqReq_canon,
|
|
CAN_FIRE_RL_mmio_pRsQ_enqReq_canon,
|
|
CAN_FIRE_RL_mmio_sendDataReq,
|
|
CAN_FIRE_RL_mmio_sendDataResp,
|
|
CAN_FIRE_RL_mmio_sendInstReq,
|
|
CAN_FIRE_RL_mmio_sendInstResp,
|
|
CAN_FIRE_RL_prepareCachesAndTlbs,
|
|
CAN_FIRE_RL_readyToFetch,
|
|
CAN_FIRE_RL_renameStage_doRenaming,
|
|
CAN_FIRE_RL_renameStage_doRenaming_SystemInst,
|
|
CAN_FIRE_RL_renameStage_doRenaming_Trap,
|
|
CAN_FIRE_RL_renameStage_doRenaming_wrongPath,
|
|
CAN_FIRE_RL_rl_outOfReset,
|
|
CAN_FIRE_RL_sendDTlbReq,
|
|
CAN_FIRE_RL_sendFlushDone,
|
|
CAN_FIRE_RL_sendITlbReq,
|
|
CAN_FIRE_RL_sendRobEnqTime,
|
|
CAN_FIRE_RL_sendRsToDTlb,
|
|
CAN_FIRE_RL_sendRsToITlb,
|
|
CAN_FIRE_coreIndInv_perfResp,
|
|
CAN_FIRE_coreIndInv_terminate,
|
|
CAN_FIRE_coreReq_perfReq,
|
|
CAN_FIRE_coreReq_start,
|
|
CAN_FIRE_dCacheToParent_fromP_enq,
|
|
CAN_FIRE_dCacheToParent_rqToP_deq,
|
|
CAN_FIRE_dCacheToParent_rsToP_deq,
|
|
CAN_FIRE_deadlock_checkStarted_get,
|
|
CAN_FIRE_deadlock_commitInstStuck_get,
|
|
CAN_FIRE_deadlock_commitUserInstStuck_get,
|
|
CAN_FIRE_deadlock_dCacheCRqStuck_get,
|
|
CAN_FIRE_deadlock_dCachePRqStuck_get,
|
|
CAN_FIRE_deadlock_iCacheCRqStuck_get,
|
|
CAN_FIRE_deadlock_iCachePRqStuck_get,
|
|
CAN_FIRE_deadlock_renameCorrectPathStuck_get,
|
|
CAN_FIRE_deadlock_renameInstStuck_get,
|
|
CAN_FIRE_iCacheToParent_fromP_enq,
|
|
CAN_FIRE_iCacheToParent_rqToP_deq,
|
|
CAN_FIRE_iCacheToParent_rsToP_deq,
|
|
CAN_FIRE_mmioToPlatform_cRq_deq,
|
|
CAN_FIRE_mmioToPlatform_cRs_deq,
|
|
CAN_FIRE_mmioToPlatform_pRq_enq,
|
|
CAN_FIRE_mmioToPlatform_pRs_enq,
|
|
CAN_FIRE_mmioToPlatform_setTime,
|
|
CAN_FIRE_recvDoStats,
|
|
CAN_FIRE_renameDebug_renameErr_get,
|
|
CAN_FIRE_sendDoStats,
|
|
CAN_FIRE_setDEIP,
|
|
CAN_FIRE_setMEIP,
|
|
CAN_FIRE_setSEIP,
|
|
CAN_FIRE_tlbToMem_memReq_deq,
|
|
CAN_FIRE_tlbToMem_respLd_enq,
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd,
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst,
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst,
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush,
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle,
|
|
WILL_FIRE_RL_commitStage_doSetLSQAtCommit,
|
|
WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1,
|
|
WILL_FIRE_RL_commitStage_notifyLSQCommit,
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu,
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu,
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
|
|
WILL_FIRE_RL_coreFix_doFetchTrainBP,
|
|
WILL_FIRE_RL_coreFix_doFetchTrainBP_1,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
|
|
WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
|
|
WILL_FIRE_RL_coreFix_memExe_doDispatchMem,
|
|
WILL_FIRE_RL_coreFix_memExe_doExeMem,
|
|
WILL_FIRE_RL_coreFix_memExe_doFinishMem,
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueSB,
|
|
WILL_FIRE_RL_coreFix_memExe_doRegReadMem,
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdForward,
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem,
|
|
WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
|
|
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem,
|
|
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem,
|
|
WILL_FIRE_RL_csrInstOrInterruptInflight_canon,
|
|
WILL_FIRE_RL_csrf_incCycle,
|
|
WILL_FIRE_RL_csrf_mcycle_ehr_data_canon,
|
|
WILL_FIRE_RL_csrf_mcycle_ehr_setRead,
|
|
WILL_FIRE_RL_csrf_minstret_ehr_data_canon,
|
|
WILL_FIRE_RL_csrf_minstret_ehr_setRead,
|
|
WILL_FIRE_RL_mkConnectionGetPut,
|
|
WILL_FIRE_RL_mkConnectionGetPut_1,
|
|
WILL_FIRE_RL_mmio_cRqQ_canonicalize,
|
|
WILL_FIRE_RL_mmio_cRqQ_clearReq_canon,
|
|
WILL_FIRE_RL_mmio_cRqQ_deqReq_canon,
|
|
WILL_FIRE_RL_mmio_cRqQ_enqReq_canon,
|
|
WILL_FIRE_RL_mmio_cRsQ_canonicalize,
|
|
WILL_FIRE_RL_mmio_cRsQ_clearReq_canon,
|
|
WILL_FIRE_RL_mmio_cRsQ_deqReq_canon,
|
|
WILL_FIRE_RL_mmio_cRsQ_enqReq_canon,
|
|
WILL_FIRE_RL_mmio_dataPendQ_canonicalize,
|
|
WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon,
|
|
WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon,
|
|
WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon,
|
|
WILL_FIRE_RL_mmio_dataReqQ_canonicalize,
|
|
WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_mmio_dataRespQ_canonicalize,
|
|
WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon,
|
|
WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon,
|
|
WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon,
|
|
WILL_FIRE_RL_mmio_handlePRq,
|
|
WILL_FIRE_RL_mmio_pRqQ_canonicalize,
|
|
WILL_FIRE_RL_mmio_pRqQ_clearReq_canon,
|
|
WILL_FIRE_RL_mmio_pRqQ_deqReq_canon,
|
|
WILL_FIRE_RL_mmio_pRqQ_enqReq_canon,
|
|
WILL_FIRE_RL_mmio_pRsQ_canonicalize,
|
|
WILL_FIRE_RL_mmio_pRsQ_clearReq_canon,
|
|
WILL_FIRE_RL_mmio_pRsQ_deqReq_canon,
|
|
WILL_FIRE_RL_mmio_pRsQ_enqReq_canon,
|
|
WILL_FIRE_RL_mmio_sendDataReq,
|
|
WILL_FIRE_RL_mmio_sendDataResp,
|
|
WILL_FIRE_RL_mmio_sendInstReq,
|
|
WILL_FIRE_RL_mmio_sendInstResp,
|
|
WILL_FIRE_RL_prepareCachesAndTlbs,
|
|
WILL_FIRE_RL_readyToFetch,
|
|
WILL_FIRE_RL_renameStage_doRenaming,
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst,
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap,
|
|
WILL_FIRE_RL_renameStage_doRenaming_wrongPath,
|
|
WILL_FIRE_RL_rl_outOfReset,
|
|
WILL_FIRE_RL_sendDTlbReq,
|
|
WILL_FIRE_RL_sendFlushDone,
|
|
WILL_FIRE_RL_sendITlbReq,
|
|
WILL_FIRE_RL_sendRobEnqTime,
|
|
WILL_FIRE_RL_sendRsToDTlb,
|
|
WILL_FIRE_RL_sendRsToITlb,
|
|
WILL_FIRE_coreIndInv_perfResp,
|
|
WILL_FIRE_coreIndInv_terminate,
|
|
WILL_FIRE_coreReq_perfReq,
|
|
WILL_FIRE_coreReq_start,
|
|
WILL_FIRE_dCacheToParent_fromP_enq,
|
|
WILL_FIRE_dCacheToParent_rqToP_deq,
|
|
WILL_FIRE_dCacheToParent_rsToP_deq,
|
|
WILL_FIRE_deadlock_checkStarted_get,
|
|
WILL_FIRE_deadlock_commitInstStuck_get,
|
|
WILL_FIRE_deadlock_commitUserInstStuck_get,
|
|
WILL_FIRE_deadlock_dCacheCRqStuck_get,
|
|
WILL_FIRE_deadlock_dCachePRqStuck_get,
|
|
WILL_FIRE_deadlock_iCacheCRqStuck_get,
|
|
WILL_FIRE_deadlock_iCachePRqStuck_get,
|
|
WILL_FIRE_deadlock_renameCorrectPathStuck_get,
|
|
WILL_FIRE_deadlock_renameInstStuck_get,
|
|
WILL_FIRE_iCacheToParent_fromP_enq,
|
|
WILL_FIRE_iCacheToParent_rqToP_deq,
|
|
WILL_FIRE_iCacheToParent_rsToP_deq,
|
|
WILL_FIRE_mmioToPlatform_cRq_deq,
|
|
WILL_FIRE_mmioToPlatform_cRs_deq,
|
|
WILL_FIRE_mmioToPlatform_pRq_enq,
|
|
WILL_FIRE_mmioToPlatform_pRs_enq,
|
|
WILL_FIRE_mmioToPlatform_setTime,
|
|
WILL_FIRE_recvDoStats,
|
|
WILL_FIRE_renameDebug_renameErr_get,
|
|
WILL_FIRE_sendDoStats,
|
|
WILL_FIRE_setDEIP,
|
|
WILL_FIRE_setMEIP,
|
|
WILL_FIRE_setSEIP,
|
|
WILL_FIRE_tlbToMem_memReq_deq,
|
|
WILL_FIRE_tlbToMem_respLd_enq;
|
|
|
|
// inputs to muxes for submodule ports
|
|
reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1,
|
|
MUX_coreFix_memExe_lsq$respLd_2__VAL_2,
|
|
MUX_fetchStage$redirect_1__VAL_5;
|
|
reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1,
|
|
MUX_coreFix_memExe_lsq$respLd_1__VAL_2;
|
|
reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_1;
|
|
wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
|
|
wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
|
|
wire [186 : 0] MUX_rob$enqPort_0_enq_1__VAL_1,
|
|
MUX_rob$enqPort_0_enq_1__VAL_2,
|
|
MUX_rob$enqPort_0_enq_1__VAL_3;
|
|
wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1,
|
|
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2;
|
|
wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
|
|
wire [158 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1,
|
|
MUX_coreFix_trainBPQ_0$enq_1__VAL_2,
|
|
MUX_coreFix_trainBPQ_1$enq_1__VAL_1,
|
|
MUX_coreFix_trainBPQ_1$enq_1__VAL_2;
|
|
wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3,
|
|
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1,
|
|
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2;
|
|
wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2,
|
|
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2;
|
|
wire [133 : 0] MUX_commitStage_commitTrap$write_1__VAL_2;
|
|
wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2,
|
|
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1;
|
|
wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1;
|
|
wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1,
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2,
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
|
|
wire [63 : 0] MUX_csrf_mepc_csr$write_1__VAL_2,
|
|
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1,
|
|
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2,
|
|
MUX_csrf_mtval_csr$write_1__VAL_1,
|
|
MUX_csrf_mtval_csr$write_1__VAL_2,
|
|
MUX_csrf_sepc_csr$write_1__VAL_2,
|
|
MUX_fetchStage$redirect_1__VAL_4,
|
|
MUX_rf$write_2_wr_2__VAL_1,
|
|
MUX_rf$write_2_wr_2__VAL_3,
|
|
MUX_rf$write_2_wr_2__VAL_4,
|
|
MUX_rf$write_2_wr_2__VAL_5,
|
|
MUX_rf$write_2_wr_2__VAL_6,
|
|
MUX_rf$write_3_wr_2__VAL_3,
|
|
MUX_rf$write_3_wr_2__VAL_4;
|
|
wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
|
|
wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
|
|
wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1,
|
|
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2;
|
|
wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_2;
|
|
wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_2,
|
|
MUX_rob$setExecuted_deqLSQ_2__VAL_3,
|
|
MUX_rob$setExecuted_deqLSQ_2__VAL_6,
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2,
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3,
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4;
|
|
wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2;
|
|
wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1;
|
|
wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1,
|
|
MUX_csrf_prv_reg$write_1__VAL_1,
|
|
MUX_csrf_prv_reg$write_1__VAL_2;
|
|
wire MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1,
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3,
|
|
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3,
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4,
|
|
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1,
|
|
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2,
|
|
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1,
|
|
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1,
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2,
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1,
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2,
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_1,
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_2,
|
|
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1,
|
|
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1,
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1,
|
|
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1,
|
|
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2,
|
|
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1,
|
|
MUX_coreFix_trainBPQ_0$enq_1__SEL_1,
|
|
MUX_coreFix_trainBPQ_1$enq_1__SEL_1,
|
|
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1,
|
|
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2,
|
|
MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2,
|
|
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1,
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1,
|
|
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1,
|
|
MUX_csrf_fflags_reg$write_1__SEL_1,
|
|
MUX_csrf_fs_reg$write_1__SEL_1,
|
|
MUX_csrf_ie_vec_1$write_1__SEL_1,
|
|
MUX_csrf_ie_vec_1$write_1__SEL_2,
|
|
MUX_csrf_ie_vec_1$write_1__VAL_1,
|
|
MUX_csrf_ie_vec_3$write_1__SEL_1,
|
|
MUX_csrf_ie_vec_3$write_1__SEL_2,
|
|
MUX_csrf_ie_vec_3$write_1__VAL_1,
|
|
MUX_csrf_mpp_reg$write_1__SEL_1,
|
|
MUX_csrf_prev_ie_vec_1$write_1__SEL_1,
|
|
MUX_csrf_prev_ie_vec_1$write_1__VAL_1,
|
|
MUX_csrf_prev_ie_vec_3$write_1__SEL_1,
|
|
MUX_csrf_prev_ie_vec_3$write_1__VAL_1,
|
|
MUX_csrf_prv_reg$write_1__SEL_1,
|
|
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2,
|
|
MUX_csrf_spp_reg$write_1__SEL_1,
|
|
MUX_csrf_spp_reg$write_1__VAL_1,
|
|
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2,
|
|
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2,
|
|
MUX_flush_reservation$write_1__SEL_1,
|
|
MUX_flush_tlbs$write_1__SEL_1,
|
|
MUX_rf$write_3_wr_1__PSEL_5,
|
|
MUX_rf$write_3_wr_1__SEL_1,
|
|
MUX_rf$write_3_wr_1__SEL_2,
|
|
MUX_rf$write_3_wr_1__SEL_3,
|
|
MUX_rf$write_3_wr_1__SEL_4,
|
|
MUX_rf$write_3_wr_1__SEL_5,
|
|
MUX_rf$write_3_wr_2__SEL_5,
|
|
MUX_rob$setExecuted_deqLSQ_1__SEL_5,
|
|
MUX_sbAggr$setReady_4_put_1__SEL_1,
|
|
MUX_sbAggr$setReady_4_put_1__SEL_2,
|
|
MUX_sbCons$setReady_3_put_1__SEL_1,
|
|
MUX_sbCons$setReady_3_put_1__SEL_2,
|
|
MUX_sbCons$setReady_3_put_1__SEL_3,
|
|
MUX_update_vm_info$write_1__SEL_1;
|
|
|
|
// remaining internal signals
|
|
reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492;
|
|
reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9925,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2867,
|
|
addr__h287234,
|
|
curData__h190083,
|
|
rVal1__h605816,
|
|
rVal1__h629196,
|
|
trap_val__h690161,
|
|
x__h194294;
|
|
reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9,
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q211,
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q212,
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q197,
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q198,
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q201,
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q202,
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q199,
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q200,
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q213,
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q214,
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q215,
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q216,
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q217,
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q218,
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q207,
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q208,
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q209,
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q210,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10575,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10601,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10620,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9107,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9134,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9153,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9812,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9838,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9857;
|
|
reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348,
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398;
|
|
reg [22 : 0] CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q78,
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q79,
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q80,
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q81,
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q111,
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q112,
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q41,
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q42,
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q109,
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q110,
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q39,
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q40,
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q113,
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q114,
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q43,
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q44,
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q115,
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q116,
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q45,
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q46,
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q76,
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q77,
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q74,
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q75,
|
|
_theResult___fst_sfd__h343232,
|
|
_theResult___fst_sfd__h351955,
|
|
_theResult___fst_sfd__h360537,
|
|
_theResult___fst_sfd__h369721,
|
|
_theResult___fst_sfd__h378357,
|
|
_theResult___fst_sfd__h388924,
|
|
_theResult___fst_sfd__h397645,
|
|
_theResult___fst_sfd__h406227,
|
|
_theResult___fst_sfd__h415411,
|
|
_theResult___fst_sfd__h424047,
|
|
_theResult___fst_sfd__h434612,
|
|
_theResult___fst_sfd__h443333,
|
|
_theResult___fst_sfd__h451915,
|
|
_theResult___fst_sfd__h461099,
|
|
_theResult___fst_sfd__h469735;
|
|
reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270,
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_384_ETC__q220,
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267,
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276,
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_384_ETC__q223,
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273,
|
|
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283,
|
|
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275;
|
|
reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359,
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407;
|
|
reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271,
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_362_ETC__q221,
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268,
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277,
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_362_ETC__q224,
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274,
|
|
CASE_fetchStagepipelines_0_first_BITS_76_TO_6_ETC__q225,
|
|
CASE_fetchStagepipelines_1_first_BITS_76_TO_6_ETC__q228;
|
|
reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8,
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q205,
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q206,
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q175,
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q176,
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q177,
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q178,
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q181,
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q182,
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q152,
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q153,
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q179,
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q180,
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q183,
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q184,
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q135,
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q136,
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q203,
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q204,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10480,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10518,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10549,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9007,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9050,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9081,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9717,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9755,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9786;
|
|
reg [7 : 0] CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q67,
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q68,
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q72,
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q73,
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q96,
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q97,
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q26,
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q27,
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q94,
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q95,
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q24,
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q25,
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q102,
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q103,
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q32,
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q33,
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q107,
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q108,
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q37,
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q38,
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q61,
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q62,
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q59,
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q60,
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373,
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420,
|
|
_theResult___fst_exp__h343231,
|
|
_theResult___fst_exp__h351954,
|
|
_theResult___fst_exp__h360536,
|
|
_theResult___fst_exp__h369720,
|
|
_theResult___fst_exp__h378356,
|
|
_theResult___fst_exp__h388923,
|
|
_theResult___fst_exp__h397644,
|
|
_theResult___fst_exp__h406226,
|
|
_theResult___fst_exp__h415410,
|
|
_theResult___fst_exp__h424046,
|
|
_theResult___fst_exp__h434611,
|
|
_theResult___fst_exp__h443332,
|
|
_theResult___fst_exp__h451914,
|
|
_theResult___fst_exp__h461098,
|
|
_theResult___fst_exp__h469734;
|
|
reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265,
|
|
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1,
|
|
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262,
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152;
|
|
reg [4 : 0] IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13738,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13863;
|
|
reg [3 : 0] CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227,
|
|
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12,
|
|
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13,
|
|
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263,
|
|
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264,
|
|
CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q259,
|
|
CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q260,
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13741,
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13864,
|
|
i__h689145,
|
|
i__h689305;
|
|
reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269,
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_367_ETC__q219,
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266,
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275,
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_367_ETC__q222,
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272,
|
|
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242,
|
|
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254,
|
|
CASE_fetchStagepipelines_0_first_BITS_81_TO_7_ETC__q226,
|
|
CASE_fetchStagepipelines_1_first_BITS_81_TO_7_ETC__q229,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691,
|
|
x__h283013,
|
|
x__h288783;
|
|
reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248;
|
|
reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
|
|
CASE_fetchStagepipelines_0_canDeq_AND_NOT_fet_ETC__q234,
|
|
CASE_fetchStagepipelines_0_first_BITS_95_TO_9_ETC__q233,
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q230,
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q231,
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q235,
|
|
CASE_guard06588_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87,
|
|
CASE_guard06588_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86,
|
|
CASE_guard09043_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139,
|
|
CASE_guard15424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89,
|
|
CASE_guard15424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88,
|
|
CASE_guard29463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193,
|
|
CASE_guard29463_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187,
|
|
CASE_guard34639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118,
|
|
CASE_guard34639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117,
|
|
CASE_guard38775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191,
|
|
CASE_guard38775_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185,
|
|
CASE_guard43259_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48,
|
|
CASE_guard43259_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47,
|
|
CASE_guard43346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120,
|
|
CASE_guard43346_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119,
|
|
CASE_guard47844_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195,
|
|
CASE_guard47844_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189,
|
|
CASE_guard51968_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50,
|
|
CASE_guard51968_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49,
|
|
CASE_guard52276_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122,
|
|
CASE_guard52276_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121,
|
|
CASE_guard60898_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53,
|
|
CASE_guard60898_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52,
|
|
CASE_guard61112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124,
|
|
CASE_guard61112_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123,
|
|
CASE_guard68664_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162,
|
|
CASE_guard68664_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154,
|
|
CASE_guard69734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51,
|
|
CASE_guard69734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54,
|
|
CASE_guard77976_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160,
|
|
CASE_guard77976_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156,
|
|
CASE_guard87045_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164,
|
|
CASE_guard87045_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158,
|
|
CASE_guard88951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q82,
|
|
CASE_guard88951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83,
|
|
CASE_guard90662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137,
|
|
CASE_guard97658_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85,
|
|
CASE_guard97658_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84,
|
|
CASE_guard99974_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141,
|
|
CASE_k59336_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6438,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6451,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6468,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6481,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6494,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6501,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6504,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6511,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6518,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5046,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5059,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5076,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5089,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5102,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5109,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5112,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5119,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5126,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7830,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7843,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7860,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7873,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7886,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7893,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7896,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7903,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7910,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10828,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10864,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10912,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10954,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10996,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8389,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8402,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8421,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13732,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13735,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13160,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13215,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13476,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13497,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13514,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13566,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13568,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13582,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13589,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13658,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13669,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13861,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13862,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13655,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13680,
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177,
|
|
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__259_ETC___d13616,
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143,
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416;
|
|
wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3239;
|
|
wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2502,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2513,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2515,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2514;
|
|
wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2937;
|
|
wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2200,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2930,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14575;
|
|
wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2000;
|
|
wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2195,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2921,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14566;
|
|
wire [321 : 0] basicExec___d11852, basicExec___d12459;
|
|
wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1995;
|
|
wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2190,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2912,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14557;
|
|
wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1990;
|
|
wire [68 : 0] execFpuSimple___d11030;
|
|
wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627;
|
|
wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2562;
|
|
wire [63 : 0] IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12308,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12309,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12320,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12321,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11701,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11702,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11713,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11714,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8329,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8330,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8340,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8341,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8351,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8352,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659,
|
|
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8062,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10630,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9161,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9867,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9921,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2559,
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377,
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424,
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378,
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425,
|
|
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8,
|
|
_theResult___fst__h600208,
|
|
_theResult___snd__h600209,
|
|
a___1__h599927,
|
|
a___1__h600213,
|
|
a__h599786,
|
|
amoExec___d880,
|
|
b___1__h599928,
|
|
b___1__h600258,
|
|
b__h599787,
|
|
base__h691735,
|
|
base__h691938,
|
|
data___1__h472154,
|
|
data___1__h472962,
|
|
data__h472428,
|
|
fcsr_csr__read__h606094,
|
|
fflags_csr__read__h606069,
|
|
frm_csr__read__h606080,
|
|
mcause_csr__read__h607741,
|
|
mcounteren_csr__read__h607486,
|
|
medeleg_csr__read__h607086,
|
|
mideleg_csr__read__h607181,
|
|
mie_csr__read__h607312,
|
|
mip_csr__read__h607981,
|
|
mstatus_csr__read__h606938,
|
|
mtvec_csr__read__h607394,
|
|
n___1__h195697,
|
|
n__h191621,
|
|
n__read__h608085,
|
|
n__read__h608276,
|
|
n__read__h6133,
|
|
n__read__h699967,
|
|
next_pc__h699310,
|
|
q___1__h473027,
|
|
rVal1__h478908,
|
|
rVal2__h478909,
|
|
r___1__h473053,
|
|
res_data__h335036,
|
|
res_data__h335041,
|
|
res_data__h380731,
|
|
res_data__h380736,
|
|
res_data__h426419,
|
|
res_data__h426424,
|
|
resp_addr__h289138,
|
|
robdeqPort_0_deq_data_BITS_95_TO_32__q261,
|
|
satp_csr__read__h606795,
|
|
scause_csr__read__h606593,
|
|
scounteren_csr__read__h606455,
|
|
shiftData__h180478,
|
|
sie_csr__read__h606359,
|
|
sip_csr__read__h606732,
|
|
sstatus_csr__read__h606290,
|
|
stvec_csr__read__h606402,
|
|
upd__h3638,
|
|
upd__h4955,
|
|
v__h604700,
|
|
v__h628235,
|
|
vaddr__h180473,
|
|
x__h152854,
|
|
x__h156401,
|
|
x__h159215,
|
|
x__h161063,
|
|
x__h17638,
|
|
x__h180387,
|
|
x__h180388,
|
|
x__h20176,
|
|
x__h284458,
|
|
x__h286312,
|
|
x__h45545,
|
|
x__h478817,
|
|
x__h478818,
|
|
x__h478819,
|
|
x__h48081,
|
|
x__h612962,
|
|
x__h612963,
|
|
x__h634046,
|
|
x__h634047,
|
|
x_addr__h311242,
|
|
x_quotient__h472342,
|
|
x_reg_ifc__read__h606199,
|
|
x_remainder__h472343,
|
|
y_avValue__h179475,
|
|
y_avValue__h180081,
|
|
y_avValue__h475953,
|
|
y_avValue__h476561,
|
|
y_avValue__h477163,
|
|
y_avValue__h605606,
|
|
y_avValue__h610852,
|
|
y_avValue__h628988,
|
|
y_avValue__h631946,
|
|
y_avValue__h690008,
|
|
y_avValue__h691772;
|
|
wire [62 : 0] IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10628,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9865,
|
|
r1__read__h608783,
|
|
r1__read__h609187,
|
|
r1__read__h609717,
|
|
r1__read__h609722,
|
|
r1__read__h609741,
|
|
r1__read__h609994,
|
|
r1__read__h610156,
|
|
r1__read__h610274,
|
|
r1__read__h610279,
|
|
r1__read__h610298;
|
|
wire [61 : 0] r1__read__h608785,
|
|
r1__read__h609189,
|
|
r1__read__h609724,
|
|
r1__read__h609743,
|
|
r1__read__h609996,
|
|
r1__read__h610132,
|
|
r1__read__h610158,
|
|
r1__read__h610281,
|
|
r1__read__h610300;
|
|
wire [60 : 0] r1__read__h609998,
|
|
r1__read__h610134,
|
|
r1__read__h610160,
|
|
r1__read__h610302;
|
|
wire [59 : 0] r1__read__h608787,
|
|
r1__read__h609191,
|
|
r1__read__h609735,
|
|
r1__read__h609745,
|
|
r1__read__h610000,
|
|
r1__read__h610162,
|
|
r1__read__h610292,
|
|
r1__read__h610304;
|
|
wire [58 : 0] r1__read__h608789,
|
|
r1__read__h609193,
|
|
r1__read__h609747,
|
|
r1__read__h610002,
|
|
r1__read__h610164,
|
|
r1__read__h610306;
|
|
wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2542,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2705,
|
|
r1__read__h608791,
|
|
r1__read__h609195,
|
|
r1__read__h609749,
|
|
r1__read__h610004,
|
|
r1__read__h610136,
|
|
r1__read__h610166,
|
|
r1__read__h610308,
|
|
y__h251971;
|
|
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20,
|
|
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55,
|
|
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90,
|
|
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130,
|
|
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147,
|
|
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170,
|
|
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100,
|
|
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30,
|
|
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166,
|
|
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173,
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4550,
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5942,
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7334,
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10114,
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8641,
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9351,
|
|
_theResult____h343249,
|
|
_theResult____h360888,
|
|
_theResult____h388941,
|
|
_theResult____h406578,
|
|
_theResult____h434629,
|
|
_theResult____h452266,
|
|
_theResult____h499964,
|
|
_theResult____h538765,
|
|
_theResult____h577966,
|
|
_theResult___snd__h351371,
|
|
_theResult___snd__h351382,
|
|
_theResult___snd__h351384,
|
|
_theResult___snd__h351394,
|
|
_theResult___snd__h351400,
|
|
_theResult___snd__h351423,
|
|
_theResult___snd__h359967,
|
|
_theResult___snd__h359969,
|
|
_theResult___snd__h359976,
|
|
_theResult___snd__h359982,
|
|
_theResult___snd__h360005,
|
|
_theResult___snd__h369137,
|
|
_theResult___snd__h369148,
|
|
_theResult___snd__h369150,
|
|
_theResult___snd__h369160,
|
|
_theResult___snd__h369166,
|
|
_theResult___snd__h369189,
|
|
_theResult___snd__h377757,
|
|
_theResult___snd__h377771,
|
|
_theResult___snd__h377777,
|
|
_theResult___snd__h377795,
|
|
_theResult___snd__h397061,
|
|
_theResult___snd__h397072,
|
|
_theResult___snd__h397074,
|
|
_theResult___snd__h397084,
|
|
_theResult___snd__h397090,
|
|
_theResult___snd__h397113,
|
|
_theResult___snd__h405657,
|
|
_theResult___snd__h405659,
|
|
_theResult___snd__h405666,
|
|
_theResult___snd__h405672,
|
|
_theResult___snd__h405695,
|
|
_theResult___snd__h414827,
|
|
_theResult___snd__h414838,
|
|
_theResult___snd__h414840,
|
|
_theResult___snd__h414850,
|
|
_theResult___snd__h414856,
|
|
_theResult___snd__h414879,
|
|
_theResult___snd__h423447,
|
|
_theResult___snd__h423461,
|
|
_theResult___snd__h423467,
|
|
_theResult___snd__h423485,
|
|
_theResult___snd__h442749,
|
|
_theResult___snd__h442760,
|
|
_theResult___snd__h442762,
|
|
_theResult___snd__h442772,
|
|
_theResult___snd__h442778,
|
|
_theResult___snd__h442801,
|
|
_theResult___snd__h451345,
|
|
_theResult___snd__h451347,
|
|
_theResult___snd__h451354,
|
|
_theResult___snd__h451360,
|
|
_theResult___snd__h451383,
|
|
_theResult___snd__h460515,
|
|
_theResult___snd__h460526,
|
|
_theResult___snd__h460528,
|
|
_theResult___snd__h460538,
|
|
_theResult___snd__h460544,
|
|
_theResult___snd__h460567,
|
|
_theResult___snd__h469135,
|
|
_theResult___snd__h469149,
|
|
_theResult___snd__h469155,
|
|
_theResult___snd__h469173,
|
|
_theResult___snd__h498574,
|
|
_theResult___snd__h498576,
|
|
_theResult___snd__h498583,
|
|
_theResult___snd__h498589,
|
|
_theResult___snd__h498612,
|
|
_theResult___snd__h508211,
|
|
_theResult___snd__h508222,
|
|
_theResult___snd__h508224,
|
|
_theResult___snd__h508234,
|
|
_theResult___snd__h508240,
|
|
_theResult___snd__h508263,
|
|
_theResult___snd__h516979,
|
|
_theResult___snd__h516993,
|
|
_theResult___snd__h516999,
|
|
_theResult___snd__h517017,
|
|
_theResult___snd__h537375,
|
|
_theResult___snd__h537377,
|
|
_theResult___snd__h537384,
|
|
_theResult___snd__h537390,
|
|
_theResult___snd__h537413,
|
|
_theResult___snd__h547012,
|
|
_theResult___snd__h547023,
|
|
_theResult___snd__h547025,
|
|
_theResult___snd__h547035,
|
|
_theResult___snd__h547041,
|
|
_theResult___snd__h547064,
|
|
_theResult___snd__h555780,
|
|
_theResult___snd__h555794,
|
|
_theResult___snd__h555800,
|
|
_theResult___snd__h555818,
|
|
_theResult___snd__h576576,
|
|
_theResult___snd__h576578,
|
|
_theResult___snd__h576585,
|
|
_theResult___snd__h576591,
|
|
_theResult___snd__h576614,
|
|
_theResult___snd__h586213,
|
|
_theResult___snd__h586224,
|
|
_theResult___snd__h586226,
|
|
_theResult___snd__h586236,
|
|
_theResult___snd__h586242,
|
|
_theResult___snd__h586265,
|
|
_theResult___snd__h594981,
|
|
_theResult___snd__h594995,
|
|
_theResult___snd__h595001,
|
|
_theResult___snd__h595019,
|
|
r1__read__h610006,
|
|
r1__read__h610138,
|
|
r1__read__h610168,
|
|
r1__read__h610310,
|
|
result__h361501,
|
|
result__h407191,
|
|
result__h452879,
|
|
result__h500577,
|
|
result__h539378,
|
|
result__h578579,
|
|
sfd__h335644,
|
|
sfd__h381339,
|
|
sfd__h427027,
|
|
sfd__h479622,
|
|
sfd__h518564,
|
|
sfd__h557765,
|
|
sfdin__h351354,
|
|
sfdin__h369120,
|
|
sfdin__h397044,
|
|
sfdin__h414810,
|
|
sfdin__h442732,
|
|
sfdin__h460498,
|
|
sfdin__h508194,
|
|
sfdin__h546995,
|
|
sfdin__h586196,
|
|
x__h361598,
|
|
x__h407288,
|
|
x__h452976,
|
|
x__h500672,
|
|
x__h539473,
|
|
x__h578674;
|
|
wire [55 : 0] r1__read__h608793,
|
|
r1__read__h609197,
|
|
r1__read__h609751,
|
|
r1__read__h610008,
|
|
r1__read__h610170,
|
|
r1__read__h610312;
|
|
wire [54 : 0] r1__read__h608795,
|
|
r1__read__h609199,
|
|
r1__read__h609753,
|
|
r1__read__h610010,
|
|
r1__read__h610172,
|
|
r1__read__h610314;
|
|
wire [53 : 0] r1__read__h610115,
|
|
r1__read__h610140,
|
|
r1__read__h610174,
|
|
r1__read__h610316,
|
|
sfd__h498641,
|
|
sfd__h508292,
|
|
sfd__h517052,
|
|
sfd__h537442,
|
|
sfd__h547093,
|
|
sfd__h555853,
|
|
sfd__h576643,
|
|
sfd__h586294,
|
|
sfd__h595054,
|
|
value__h343871,
|
|
value__h389561,
|
|
value__h435249;
|
|
wire [52 : 0] r1__read__h610012,
|
|
r1__read__h610117,
|
|
r1__read__h610142,
|
|
r1__read__h610176,
|
|
r1__read__h610318;
|
|
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10595,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10597,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9130,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9832,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9834,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10569,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10571,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10614,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10616,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9101,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9103,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9147,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9149,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9806,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9808,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9851,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9853,
|
|
_theResult___fst_sfd__h483551,
|
|
_theResult___fst_sfd__h499379,
|
|
_theResult___fst_sfd__h499382,
|
|
_theResult___fst_sfd__h509030,
|
|
_theResult___fst_sfd__h509033,
|
|
_theResult___fst_sfd__h517814,
|
|
_theResult___fst_sfd__h517817,
|
|
_theResult___fst_sfd__h517826,
|
|
_theResult___fst_sfd__h517832,
|
|
_theResult___fst_sfd__h522352,
|
|
_theResult___fst_sfd__h538180,
|
|
_theResult___fst_sfd__h538183,
|
|
_theResult___fst_sfd__h547831,
|
|
_theResult___fst_sfd__h547834,
|
|
_theResult___fst_sfd__h556615,
|
|
_theResult___fst_sfd__h556618,
|
|
_theResult___fst_sfd__h556627,
|
|
_theResult___fst_sfd__h556633,
|
|
_theResult___fst_sfd__h561553,
|
|
_theResult___fst_sfd__h577381,
|
|
_theResult___fst_sfd__h577384,
|
|
_theResult___fst_sfd__h587032,
|
|
_theResult___fst_sfd__h587035,
|
|
_theResult___fst_sfd__h595816,
|
|
_theResult___fst_sfd__h595819,
|
|
_theResult___fst_sfd__h595828,
|
|
_theResult___fst_sfd__h595834,
|
|
_theResult___sfd__h499279,
|
|
_theResult___sfd__h508930,
|
|
_theResult___sfd__h517714,
|
|
_theResult___sfd__h538080,
|
|
_theResult___sfd__h547731,
|
|
_theResult___sfd__h556515,
|
|
_theResult___sfd__h577281,
|
|
_theResult___sfd__h586932,
|
|
_theResult___sfd__h595716,
|
|
_theResult___snd_fst_sfd__h479576,
|
|
_theResult___snd_fst_sfd__h499385,
|
|
_theResult___snd_fst_sfd__h517820,
|
|
_theResult___snd_fst_sfd__h518518,
|
|
_theResult___snd_fst_sfd__h538186,
|
|
_theResult___snd_fst_sfd__h556621,
|
|
_theResult___snd_fst_sfd__h557719,
|
|
_theResult___snd_fst_sfd__h577387,
|
|
_theResult___snd_fst_sfd__h595822,
|
|
out___1_sfd__h479325,
|
|
out___1_sfd__h518267,
|
|
out___1_sfd__h557468,
|
|
out_sfd__h499282,
|
|
out_sfd__h508933,
|
|
out_sfd__h517717,
|
|
out_sfd__h538083,
|
|
out_sfd__h547734,
|
|
out_sfd__h556518,
|
|
out_sfd__h577284,
|
|
out_sfd__h586935,
|
|
out_sfd__h595719,
|
|
r1__read__h610320;
|
|
wire [50 : 0] r1__read__h608797, r1__read__h610014;
|
|
wire [49 : 0] r1__read__h610119, r1__read__h610322;
|
|
wire [48 : 0] r1__read__h608799, r1__read__h610016, r1__read__h610121;
|
|
wire [46 : 0] r1__read__h608801, r1__read__h610018;
|
|
wire [45 : 0] r1__read__h608803, r1__read__h610020;
|
|
wire [44 : 0] r1__read__h608805, r1__read__h610022;
|
|
wire [43 : 0] r1__read__h608807, r1__read__h610024;
|
|
wire [42 : 0] r1__read__h610026;
|
|
wire [41 : 0] r1__read__h610028;
|
|
wire [40 : 0] r1__read__h610030;
|
|
wire [37 : 0] IF_fetchStage_pipelines_0_first__2595_BIT_64_2_ETC___d13744,
|
|
IF_fetchStage_pipelines_1_first__2604_BIT_64_3_ETC___d13867;
|
|
wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125,
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3,
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2,
|
|
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4,
|
|
data72428_BITS_31_TO_0__q5,
|
|
r1__read__h608809,
|
|
r1__read__h610032,
|
|
x__h190846,
|
|
x__h335048,
|
|
x__h380743,
|
|
x__h426431,
|
|
x__h75490,
|
|
x_data__h65339,
|
|
x_data_imm__h666240,
|
|
x_data_imm__h680279;
|
|
wire [29 : 0] r1__read__h608811, r1__read__h610034;
|
|
wire [27 : 0] r1__read__h610036;
|
|
wire [24 : 0] NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13776,
|
|
sfd__h351452,
|
|
sfd__h360034,
|
|
sfd__h369218,
|
|
sfd__h377830,
|
|
sfd__h397142,
|
|
sfd__h405724,
|
|
sfd__h414908,
|
|
sfd__h423520,
|
|
sfd__h442830,
|
|
sfd__h451412,
|
|
sfd__h460596,
|
|
sfd__h469208,
|
|
value__h484180,
|
|
value__h522981,
|
|
value__h562182;
|
|
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4949,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4951,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6341,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6343,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7733,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7735,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4995,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4997,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6387,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6389,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7779,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7781,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4968,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4970,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5014,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5016,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6360,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6362,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6406,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6408,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7752,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7754,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7798,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7800,
|
|
_theResult___fst_sfd__h351958,
|
|
_theResult___fst_sfd__h360540,
|
|
_theResult___fst_sfd__h369724,
|
|
_theResult___fst_sfd__h378360,
|
|
_theResult___fst_sfd__h378369,
|
|
_theResult___fst_sfd__h378375,
|
|
_theResult___fst_sfd__h397648,
|
|
_theResult___fst_sfd__h406230,
|
|
_theResult___fst_sfd__h415414,
|
|
_theResult___fst_sfd__h424050,
|
|
_theResult___fst_sfd__h424059,
|
|
_theResult___fst_sfd__h424065,
|
|
_theResult___fst_sfd__h443336,
|
|
_theResult___fst_sfd__h451918,
|
|
_theResult___fst_sfd__h461102,
|
|
_theResult___fst_sfd__h469738,
|
|
_theResult___fst_sfd__h469747,
|
|
_theResult___fst_sfd__h469753,
|
|
_theResult___sfd__h351877,
|
|
_theResult___sfd__h360459,
|
|
_theResult___sfd__h369643,
|
|
_theResult___sfd__h378279,
|
|
_theResult___sfd__h378381,
|
|
_theResult___sfd__h397567,
|
|
_theResult___sfd__h406149,
|
|
_theResult___sfd__h415333,
|
|
_theResult___sfd__h423969,
|
|
_theResult___sfd__h424071,
|
|
_theResult___sfd__h443255,
|
|
_theResult___sfd__h451837,
|
|
_theResult___sfd__h461021,
|
|
_theResult___sfd__h469657,
|
|
_theResult___sfd__h469759,
|
|
_theResult___snd_fst_sfd__h335594,
|
|
_theResult___snd_fst_sfd__h360543,
|
|
_theResult___snd_fst_sfd__h378363,
|
|
_theResult___snd_fst_sfd__h381289,
|
|
_theResult___snd_fst_sfd__h406233,
|
|
_theResult___snd_fst_sfd__h424053,
|
|
_theResult___snd_fst_sfd__h426977,
|
|
_theResult___snd_fst_sfd__h451921,
|
|
_theResult___snd_fst_sfd__h469741,
|
|
out_f_sfd__h378658,
|
|
out_f_sfd__h424348,
|
|
out_f_sfd__h470036,
|
|
out_sfd__h351880,
|
|
out_sfd__h360462,
|
|
out_sfd__h369646,
|
|
out_sfd__h378282,
|
|
out_sfd__h397570,
|
|
out_sfd__h406152,
|
|
out_sfd__h415336,
|
|
out_sfd__h423972,
|
|
out_sfd__h443258,
|
|
out_sfd__h451840,
|
|
out_sfd__h461024,
|
|
out_sfd__h469660;
|
|
wire [19 : 0] r1__read__h609971;
|
|
wire [14 : 0] IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664,
|
|
_theResult____h645120,
|
|
enabled_ints___1__h645617,
|
|
enabled_ints__h645664,
|
|
pend_ints__h645118,
|
|
y__h645629;
|
|
wire [12 : 0] fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
fetchStage_pipelines_1_first__2604_BIT_77_3276_ETC___d13351,
|
|
r1__read_BITS_12_TO_0___h645640;
|
|
wire [11 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10407,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8934,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9644,
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5935,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4543,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7327,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10107,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8634,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9344,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4003,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5395,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6787,
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10110,
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8637,
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9347,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8497,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9222,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9985,
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4546,
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5938,
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7330,
|
|
renaming_spec_bits__h672935,
|
|
result__h640846,
|
|
result__h640897,
|
|
spec_bits__h676030,
|
|
w__h640841,
|
|
x__h361631,
|
|
x__h407321,
|
|
x__h453009,
|
|
x__h500705,
|
|
x__h539506,
|
|
x__h578707,
|
|
x__h640845,
|
|
x__h640896,
|
|
y__h640875,
|
|
y__h676043,
|
|
y_avValue_fst__h670126,
|
|
y_avValue_snd_fst__h670400,
|
|
y_avValue_snd_fst__h670435;
|
|
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10512,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10514,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9044,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9046,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9749,
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9751,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10474,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10476,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10543,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10545,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9001,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9003,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9075,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9077,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9711,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9713,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9780,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9782,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172,
|
|
_theResult___exp__h499278,
|
|
_theResult___exp__h508929,
|
|
_theResult___exp__h517713,
|
|
_theResult___exp__h538079,
|
|
_theResult___exp__h547730,
|
|
_theResult___exp__h556514,
|
|
_theResult___exp__h577280,
|
|
_theResult___exp__h586931,
|
|
_theResult___exp__h595715,
|
|
_theResult___fst_exp__h483550,
|
|
_theResult___fst_exp__h498614,
|
|
_theResult___fst_exp__h498620,
|
|
_theResult___fst_exp__h498623,
|
|
_theResult___fst_exp__h499378,
|
|
_theResult___fst_exp__h499381,
|
|
_theResult___fst_exp__h508200,
|
|
_theResult___fst_exp__h508265,
|
|
_theResult___fst_exp__h508271,
|
|
_theResult___fst_exp__h508274,
|
|
_theResult___fst_exp__h509029,
|
|
_theResult___fst_exp__h509032,
|
|
_theResult___fst_exp__h516985,
|
|
_theResult___fst_exp__h517024,
|
|
_theResult___fst_exp__h517030,
|
|
_theResult___fst_exp__h517033,
|
|
_theResult___fst_exp__h517813,
|
|
_theResult___fst_exp__h517816,
|
|
_theResult___fst_exp__h517825,
|
|
_theResult___fst_exp__h517828,
|
|
_theResult___fst_exp__h522351,
|
|
_theResult___fst_exp__h537415,
|
|
_theResult___fst_exp__h537421,
|
|
_theResult___fst_exp__h537424,
|
|
_theResult___fst_exp__h538179,
|
|
_theResult___fst_exp__h538182,
|
|
_theResult___fst_exp__h547001,
|
|
_theResult___fst_exp__h547066,
|
|
_theResult___fst_exp__h547072,
|
|
_theResult___fst_exp__h547075,
|
|
_theResult___fst_exp__h547830,
|
|
_theResult___fst_exp__h547833,
|
|
_theResult___fst_exp__h555786,
|
|
_theResult___fst_exp__h555825,
|
|
_theResult___fst_exp__h555831,
|
|
_theResult___fst_exp__h555834,
|
|
_theResult___fst_exp__h556614,
|
|
_theResult___fst_exp__h556617,
|
|
_theResult___fst_exp__h556626,
|
|
_theResult___fst_exp__h556629,
|
|
_theResult___fst_exp__h561552,
|
|
_theResult___fst_exp__h576616,
|
|
_theResult___fst_exp__h576622,
|
|
_theResult___fst_exp__h576625,
|
|
_theResult___fst_exp__h577380,
|
|
_theResult___fst_exp__h577383,
|
|
_theResult___fst_exp__h586202,
|
|
_theResult___fst_exp__h586267,
|
|
_theResult___fst_exp__h586273,
|
|
_theResult___fst_exp__h586276,
|
|
_theResult___fst_exp__h587031,
|
|
_theResult___fst_exp__h587034,
|
|
_theResult___fst_exp__h594987,
|
|
_theResult___fst_exp__h595026,
|
|
_theResult___fst_exp__h595032,
|
|
_theResult___fst_exp__h595035,
|
|
_theResult___fst_exp__h595815,
|
|
_theResult___fst_exp__h595818,
|
|
_theResult___fst_exp__h595827,
|
|
_theResult___fst_exp__h595830,
|
|
_theResult___snd_fst_exp__h499384,
|
|
_theResult___snd_fst_exp__h517819,
|
|
_theResult___snd_fst_exp__h538185,
|
|
_theResult___snd_fst_exp__h556620,
|
|
_theResult___snd_fst_exp__h577386,
|
|
_theResult___snd_fst_exp__h595821,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98,
|
|
csrf_debug_int_pend_read__1643_CONCAT_0b0_2627_ETC___d12637,
|
|
din_inc___2_exp__h517873,
|
|
din_inc___2_exp__h517908,
|
|
din_inc___2_exp__h517934,
|
|
din_inc___2_exp__h556674,
|
|
din_inc___2_exp__h556709,
|
|
din_inc___2_exp__h556735,
|
|
din_inc___2_exp__h595875,
|
|
din_inc___2_exp__h595910,
|
|
din_inc___2_exp__h595936,
|
|
out_exp__h499281,
|
|
out_exp__h508932,
|
|
out_exp__h517716,
|
|
out_exp__h538082,
|
|
out_exp__h547733,
|
|
out_exp__h556517,
|
|
out_exp__h577283,
|
|
out_exp__h586934,
|
|
out_exp__h595718;
|
|
wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4864,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6256,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7648;
|
|
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4302,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4305,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5694,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5697,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7086,
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7089,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4849,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4851,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6241,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6243,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7633,
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7635,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4524,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4526,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4918,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4920,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5916,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5918,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6310,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6312,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7308,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7310,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7702,
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7704,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104,
|
|
_theResult___exp__h351876,
|
|
_theResult___exp__h360458,
|
|
_theResult___exp__h369642,
|
|
_theResult___exp__h378278,
|
|
_theResult___exp__h378380,
|
|
_theResult___exp__h397566,
|
|
_theResult___exp__h406148,
|
|
_theResult___exp__h415332,
|
|
_theResult___exp__h423968,
|
|
_theResult___exp__h424070,
|
|
_theResult___exp__h443254,
|
|
_theResult___exp__h451836,
|
|
_theResult___exp__h461020,
|
|
_theResult___exp__h469656,
|
|
_theResult___exp__h469758,
|
|
_theResult___fst_exp__h351360,
|
|
_theResult___fst_exp__h351425,
|
|
_theResult___fst_exp__h351431,
|
|
_theResult___fst_exp__h351434,
|
|
_theResult___fst_exp__h351957,
|
|
_theResult___fst_exp__h360007,
|
|
_theResult___fst_exp__h360013,
|
|
_theResult___fst_exp__h360016,
|
|
_theResult___fst_exp__h360539,
|
|
_theResult___fst_exp__h369126,
|
|
_theResult___fst_exp__h369191,
|
|
_theResult___fst_exp__h369197,
|
|
_theResult___fst_exp__h369200,
|
|
_theResult___fst_exp__h369723,
|
|
_theResult___fst_exp__h377763,
|
|
_theResult___fst_exp__h377802,
|
|
_theResult___fst_exp__h377808,
|
|
_theResult___fst_exp__h377811,
|
|
_theResult___fst_exp__h378359,
|
|
_theResult___fst_exp__h378368,
|
|
_theResult___fst_exp__h378371,
|
|
_theResult___fst_exp__h397050,
|
|
_theResult___fst_exp__h397115,
|
|
_theResult___fst_exp__h397121,
|
|
_theResult___fst_exp__h397124,
|
|
_theResult___fst_exp__h397647,
|
|
_theResult___fst_exp__h405697,
|
|
_theResult___fst_exp__h405703,
|
|
_theResult___fst_exp__h405706,
|
|
_theResult___fst_exp__h406229,
|
|
_theResult___fst_exp__h414816,
|
|
_theResult___fst_exp__h414881,
|
|
_theResult___fst_exp__h414887,
|
|
_theResult___fst_exp__h414890,
|
|
_theResult___fst_exp__h415413,
|
|
_theResult___fst_exp__h423453,
|
|
_theResult___fst_exp__h423492,
|
|
_theResult___fst_exp__h423498,
|
|
_theResult___fst_exp__h423501,
|
|
_theResult___fst_exp__h424049,
|
|
_theResult___fst_exp__h424058,
|
|
_theResult___fst_exp__h424061,
|
|
_theResult___fst_exp__h442738,
|
|
_theResult___fst_exp__h442803,
|
|
_theResult___fst_exp__h442809,
|
|
_theResult___fst_exp__h442812,
|
|
_theResult___fst_exp__h443335,
|
|
_theResult___fst_exp__h451385,
|
|
_theResult___fst_exp__h451391,
|
|
_theResult___fst_exp__h451394,
|
|
_theResult___fst_exp__h451917,
|
|
_theResult___fst_exp__h460504,
|
|
_theResult___fst_exp__h460569,
|
|
_theResult___fst_exp__h460575,
|
|
_theResult___fst_exp__h460578,
|
|
_theResult___fst_exp__h461101,
|
|
_theResult___fst_exp__h469141,
|
|
_theResult___fst_exp__h469180,
|
|
_theResult___fst_exp__h469186,
|
|
_theResult___fst_exp__h469189,
|
|
_theResult___fst_exp__h469737,
|
|
_theResult___fst_exp__h469746,
|
|
_theResult___fst_exp__h469749,
|
|
_theResult___snd_fst_exp__h360542,
|
|
_theResult___snd_fst_exp__h378362,
|
|
_theResult___snd_fst_exp__h406232,
|
|
_theResult___snd_fst_exp__h424052,
|
|
_theResult___snd_fst_exp__h451920,
|
|
_theResult___snd_fst_exp__h469740,
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168,
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128,
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145,
|
|
din_inc___2_exp__h378393,
|
|
din_inc___2_exp__h378417,
|
|
din_inc___2_exp__h378447,
|
|
din_inc___2_exp__h378471,
|
|
din_inc___2_exp__h424083,
|
|
din_inc___2_exp__h424107,
|
|
din_inc___2_exp__h424137,
|
|
din_inc___2_exp__h424161,
|
|
din_inc___2_exp__h469771,
|
|
din_inc___2_exp__h469795,
|
|
din_inc___2_exp__h469825,
|
|
din_inc___2_exp__h469849,
|
|
out_exp__h351879,
|
|
out_exp__h360461,
|
|
out_exp__h369645,
|
|
out_exp__h378281,
|
|
out_exp__h397569,
|
|
out_exp__h406151,
|
|
out_exp__h415335,
|
|
out_exp__h423971,
|
|
out_exp__h443257,
|
|
out_exp__h451839,
|
|
out_exp__h461023,
|
|
out_exp__h469659,
|
|
out_f_exp__h378657,
|
|
out_f_exp__h424347,
|
|
out_f_exp__h470035,
|
|
x__h608768;
|
|
wire [6 : 0] csrf_debug_int_pend_read__1643_CONCAT_0b0_2627_ETC___d12632;
|
|
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4239,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5631,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7023,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10356,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8883,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9593,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4790,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6182,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7574,
|
|
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
|
|
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
|
|
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5862,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4470,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7254,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10059,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8571,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9296,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14601,
|
|
x__h180610,
|
|
x__h691750;
|
|
wire [4 : 0] IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13908,
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14460,
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5161,
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6553,
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7945,
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10732,
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10773,
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10817,
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5190,
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6582,
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7974,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5173,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6565,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7957,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10715,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10756,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10800,
|
|
checkForException___d12829,
|
|
checkForException___d13372,
|
|
fflags__h702055,
|
|
res_fflags__h335037,
|
|
res_fflags__h380732,
|
|
res_fflags__h426420,
|
|
x__h152848,
|
|
x__h156395,
|
|
x__h159211,
|
|
x__h284446,
|
|
y_avValue_snd_fst__h702081,
|
|
y_avValue_snd_fst__h702089,
|
|
y_avValue_snd_fst__h702097;
|
|
wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1843,
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1845,
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847,
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849,
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851,
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12966,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12967,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12968,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12969,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12970,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12971,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12972,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12973,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12974,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12975,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12976,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12977,
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12978,
|
|
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3__ETC___d13004,
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2828,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788,
|
|
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d13023,
|
|
cause_code__h689130,
|
|
vm_mode_reg__read__h609977;
|
|
wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2531,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785,
|
|
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
|
|
_theResult_____2__h293689,
|
|
next_deqP___1__h293968,
|
|
v__h293109,
|
|
v__h293340,
|
|
x__h299319,
|
|
x_decodeInfo_frm__h648859;
|
|
wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2781,
|
|
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14482,
|
|
IF_sfdin08194_BIT_4_THEN_2_ELSE_0__q131,
|
|
IF_sfdin14810_BIT_33_THEN_2_ELSE_0__q66,
|
|
IF_sfdin42732_BIT_33_THEN_2_ELSE_0__q91,
|
|
IF_sfdin46995_BIT_4_THEN_2_ELSE_0__q171,
|
|
IF_sfdin51354_BIT_33_THEN_2_ELSE_0__q21,
|
|
IF_sfdin60498_BIT_33_THEN_2_ELSE_0__q101,
|
|
IF_sfdin69120_BIT_33_THEN_2_ELSE_0__q31,
|
|
IF_sfdin86196_BIT_4_THEN_2_ELSE_0__q148,
|
|
IF_sfdin97044_BIT_33_THEN_2_ELSE_0__q56,
|
|
IF_theResult___snd05657_BIT_33_THEN_2_ELSE_0__q58,
|
|
IF_theResult___snd16979_BIT_4_THEN_2_ELSE_0__q134,
|
|
IF_theResult___snd23447_BIT_33_THEN_2_ELSE_0__q71,
|
|
IF_theResult___snd37375_BIT_4_THEN_2_ELSE_0__q167,
|
|
IF_theResult___snd51345_BIT_33_THEN_2_ELSE_0__q93,
|
|
IF_theResult___snd55780_BIT_4_THEN_2_ELSE_0__q174,
|
|
IF_theResult___snd59967_BIT_33_THEN_2_ELSE_0__q23,
|
|
IF_theResult___snd69135_BIT_33_THEN_2_ELSE_0__q106,
|
|
IF_theResult___snd76576_BIT_4_THEN_2_ELSE_0__q144,
|
|
IF_theResult___snd77757_BIT_33_THEN_2_ELSE_0__q36,
|
|
IF_theResult___snd94981_BIT_4_THEN_2_ELSE_0__q151,
|
|
IF_theResult___snd98574_BIT_4_THEN_2_ELSE_0__q127,
|
|
guard__h343259,
|
|
guard__h351968,
|
|
guard__h360898,
|
|
guard__h369734,
|
|
guard__h388951,
|
|
guard__h397658,
|
|
guard__h406588,
|
|
guard__h415424,
|
|
guard__h434639,
|
|
guard__h443346,
|
|
guard__h452276,
|
|
guard__h461112,
|
|
guard__h490662,
|
|
guard__h499974,
|
|
guard__h509043,
|
|
guard__h529463,
|
|
guard__h538775,
|
|
guard__h547844,
|
|
guard__h568664,
|
|
guard__h577976,
|
|
guard__h587045,
|
|
prv__h703535,
|
|
prv__h703579,
|
|
sbIdx__h156274,
|
|
v__h600721,
|
|
v__h600731,
|
|
v__h601366,
|
|
x__h608823,
|
|
x__h699370,
|
|
x__h702270,
|
|
y_avValue_snd_snd_snd_fst__h702327,
|
|
y_avValue_snd_snd_snd_fst__h702335,
|
|
y_avValue_snd_snd_snd_fst__h702343;
|
|
wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5061,
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5111,
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6453,
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6503,
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7845,
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7895,
|
|
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10653,
|
|
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9891,
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10400,
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10665,
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8927,
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9637,
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9903,
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10446,
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10650,
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10677,
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8973,
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9683,
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9888,
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9915,
|
|
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10105,
|
|
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8632,
|
|
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9342,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12125,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12126,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12127,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12150,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12151,
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12152,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11334,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11335,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11336,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11359,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11360,
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11361,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8234,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8235,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8236,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8258,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8259,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8260,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8282,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8283,
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8284,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627,
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628,
|
|
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2078,
|
|
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2095,
|
|
IF_NOT_fetchStage_pipelines_0_canDeq__2593_259_ETC___d13531,
|
|
IF_NOT_fetchStage_pipelines_0_canDeq__2593_259_ETC___d13539,
|
|
IF_NOT_fetchStage_pipelines_1_first__2604_BITS_ETC___d13463,
|
|
IF_NOT_fetchStage_pipelines_1_first__2604_BITS_ETC___d13538,
|
|
IF_NOT_rob_deqPort_1_deq_data__4369_BIT_25_437_ETC___d14473,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5091,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5128,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5219,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5245,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6483,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6520,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6611,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6637,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7875,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7912,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8003,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8029,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10448,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10679,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10874,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10888,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10903,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10920,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10932,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10945,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10962,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10974,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10987,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8975,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9685,
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9917,
|
|
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2069_ETC___d12101,
|
|
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2069_ETC___d12135,
|
|
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1278_ETC___d11310,
|
|
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1278_ETC___d11344,
|
|
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8210,
|
|
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8243,
|
|
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8267,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6524,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6485,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6522,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6586,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6597,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6613,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6626,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6639,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5093,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5130,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5194,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5205,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5221,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5234,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5247,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7877,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7914,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7978,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7989,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8005,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8018,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8031,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5132,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7916,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10450,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10681,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10736,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10777,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10821,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10836,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10846,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10857,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10876,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10890,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10905,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10922,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10934,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10947,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10964,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10976,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10989,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8423,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8977,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9687,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9919,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2076,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2096,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2099,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3038,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3050,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3130,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3145,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3152,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3172,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2996,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2039,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2041,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2042,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2098,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2100,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2696,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3301,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3316,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3397,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3412,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3439,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1737,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1792,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836,
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840,
|
|
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578,
|
|
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611,
|
|
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3742,
|
|
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3735,
|
|
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3720,
|
|
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3648,
|
|
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3641,
|
|
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3626,
|
|
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3550,
|
|
IF_fetchStage_RDY_pipelines_0_first__2592_AND__ETC___d13130,
|
|
IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13465,
|
|
IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13528,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13575,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13696,
|
|
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339,
|
|
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783,
|
|
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46,
|
|
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201,
|
|
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642,
|
|
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491,
|
|
IF_rob_deqPort_1_canDeq__4366_THEN_IF_NOT_rob__ETC___d14474,
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5213,
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5241,
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6605,
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6633,
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d7997,
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8025,
|
|
NOT_IF_NOT_rob_deqPort_0_canDeq__4362_4363_OR__ETC___d14479,
|
|
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13179,
|
|
NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12117,
|
|
NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12145,
|
|
NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11326,
|
|
NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11354,
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8226,
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8253,
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8277,
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5807,
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4415,
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7199,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10032,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10739,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10781,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10839,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10850,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10879,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10894,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10925,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10938,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10967,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10980,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8544,
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9269,
|
|
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594,
|
|
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2518,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2658,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3070,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3119,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3175,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2115,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2525,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2527,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2549,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2556,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2570,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2573,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2584,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2590,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2597,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2622,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2647,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2669,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3290,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3347,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3386,
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3443,
|
|
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1875,
|
|
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1919,
|
|
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3709,
|
|
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3764,
|
|
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3615,
|
|
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3670,
|
|
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473,
|
|
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024,
|
|
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3539,
|
|
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3581,
|
|
NOT_coreFix_memExe_respLrScAmoQ_full_944_945_A_ETC___d2074,
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13218,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13446,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13457,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13479,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13494,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13508,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13511,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13631,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13650,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13702,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13792,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13799,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13810,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13855,
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13885,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13161,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13379,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13393,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13399,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13498,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13515,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13533,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13536,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13624,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707,
|
|
NOT_fetchStage_pipelines_0_first__2595_BIT_4_2_ETC___d13046,
|
|
NOT_fetchStage_pipelines_1_canDeq__2601_2602_O_ETC___d12610,
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13384,
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13503,
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13520,
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805,
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13386,
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13482,
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13807,
|
|
NOT_fetchStage_pipelines_1_first__2604_BIT_4_3_ETC___d13376,
|
|
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431,
|
|
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452,
|
|
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823,
|
|
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844,
|
|
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091,
|
|
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390,
|
|
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325,
|
|
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140,
|
|
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161,
|
|
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241,
|
|
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262,
|
|
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734,
|
|
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755,
|
|
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593,
|
|
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614,
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13488,
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542,
|
|
NOT_rob_deqPort_0_canDeq__4362_4363_OR_rob_RDY_ETC___d14401,
|
|
NOT_rob_deqPort_0_canDeq__4362_4363_OR_rob_deq_ETC___d14454,
|
|
NOT_rob_deqPort_0_deq_data__3921_BITS_122_TO_1_ETC___d14162,
|
|
NOT_rob_deqPort_1_deq_data__4369_BIT_25_4370_4_ETC___d14398,
|
|
NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13621,
|
|
NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13686,
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13435,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328,
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345,
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346,
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4241,
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5633,
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7025,
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10358,
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8885,
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9595,
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4792,
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6184,
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7576,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4472,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4865,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5864,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6257,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7256,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7649,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10061,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10408,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8573,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8935,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9298,
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9645,
|
|
_0_OR_NOT_fetchStage_pipelines_0_first__2595_BI_ETC___d13549,
|
|
_0_OR_NOT_fetchStage_pipelines_1_first__2604_BI_ETC___d13634,
|
|
_0_OR_fetchStage_RDY_pipelines_0_first__2592_34_ETC___d13460,
|
|
_0b0_CONCAT_csrf_medeleg_15_reg_read__1592_1593_ETC___d14025,
|
|
_0b0_CONCAT_csrf_mideleg_11_reg_read__1600_1601_ETC___d14007,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5176,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5201,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5228,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6568,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6593,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6620,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7960,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7985,
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8012,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986,
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988,
|
|
_dfoo12,
|
|
_dfoo16,
|
|
_dfoo18,
|
|
_dfoo2,
|
|
_dfoo20,
|
|
_dfoo28,
|
|
_dfoo7,
|
|
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset,
|
|
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset,
|
|
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
|
|
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset,
|
|
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset,
|
|
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
|
|
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset,
|
|
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset,
|
|
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
|
|
_dor1coreFix_memExe_bypassWire_2$EN_wset,
|
|
_dor1coreFix_memExe_bypassWire_3$EN_wset,
|
|
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write,
|
|
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write,
|
|
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write,
|
|
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset,
|
|
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write,
|
|
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write,
|
|
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset,
|
|
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put,
|
|
_dor1rf$EN_write_0_wr,
|
|
_dor1rf$EN_write_1_wr,
|
|
_dor1sbAggr$EN_setReady_3_put,
|
|
_dor1sbCons$EN_setReady_0_put,
|
|
_dor1sbCons$EN_setReady_1_put,
|
|
_theResult_____2__h301685,
|
|
_theResult_____2__h307679,
|
|
_theResult_____2__h315533,
|
|
_theResult_____2__h325877,
|
|
_theResult_____2__h329102,
|
|
coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093,
|
|
coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132,
|
|
coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12106,
|
|
coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12138,
|
|
coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12114,
|
|
coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12142,
|
|
coreFix_aluExe_0_dispToRegQ_first__2070_BIT_13_ETC___d12155,
|
|
coreFix_aluExe_0_exeToFinQ_RDY_first__2480_AND_ETC___d12518,
|
|
coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139,
|
|
coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302,
|
|
coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341,
|
|
coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11315,
|
|
coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11347,
|
|
coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11323,
|
|
coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11351,
|
|
coreFix_aluExe_1_dispToRegQ_first__1279_BIT_13_ETC___d11364,
|
|
coreFix_aluExe_1_exeToFinQ_RDY_first__1873_AND_ETC___d11912,
|
|
coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202,
|
|
coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240,
|
|
coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264,
|
|
coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8215,
|
|
coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8246,
|
|
coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8270,
|
|
coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8223,
|
|
coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8250,
|
|
coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8274,
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5264,
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3872,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6656,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8094,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8097,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8048,
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10826,
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10862,
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10910,
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10952,
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10994,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__35_ETC___d13641,
|
|
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570,
|
|
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608,
|
|
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583,
|
|
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614,
|
|
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591,
|
|
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2569,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3059,
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3162,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2062,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142,
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2719,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2523,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2552,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2557,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2574,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2591,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2611,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2635,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2641,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2789,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2802,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2811,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2820,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2832,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3333,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3429,
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1903,
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722,
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1724,
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727,
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729,
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3751,
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3657,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3566,
|
|
coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14167,
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027,
|
|
csrf_prv_reg_read__2623_ULE_1___d13987,
|
|
fetchStage_RDY_pipelines_0_first__2592_AND_NOT_ETC___d13126,
|
|
fetchStage_RDY_pipelines_0_first__2592_AND_fet_ETC___d13193,
|
|
fetchStage_RDY_pipelines_1_deq__2607_AND_NOT_f_ETC___d13690,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13710,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13783,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_fetchS_ETC___d13700,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13638,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13644,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13645,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13666,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13898,
|
|
fetchStage_pipelines_0_canDeq__2593_AND_specTa_ETC___d13762,
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13200,
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13404,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13392,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13411,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13470,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13577,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13583,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13605,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13612,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13659,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13670,
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13789,
|
|
fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832,
|
|
fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13432,
|
|
fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13599,
|
|
fetchStage_pipelines_1_first__2604_BITS_98_TO__ETC___d13594,
|
|
fetchStage_pipelines_1_first__2604_BIT_4_3249__ETC___d13427,
|
|
guard__h361496,
|
|
guard__h407186,
|
|
guard__h452874,
|
|
guard__h500572,
|
|
guard__h539373,
|
|
guard__h578574,
|
|
idx__h673066,
|
|
k__h659336,
|
|
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444,
|
|
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836,
|
|
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312,
|
|
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153,
|
|
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254,
|
|
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13065,
|
|
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13704,
|
|
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747,
|
|
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606,
|
|
msip__h75375,
|
|
next_deqP___1__h301964,
|
|
next_deqP___1__h308245,
|
|
next_deqP___1__h316099,
|
|
next_deqP___1__h326156,
|
|
next_deqP___1__h329381,
|
|
r__h608815,
|
|
regRenamingTable_RDY_rename_0_getRename__3034__ETC___d13562,
|
|
regRenamingTable_RDY_rename_1_getRename__3618__ETC___d13636,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13188,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13443,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13455,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13591,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13722,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13728,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13748,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13756,
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13896,
|
|
regRenamingTable_rename_1_canRename__3221_AND__ETC___d13850,
|
|
rob_RDY_enqPort_0_enq__2617_AND_regRenamingTab_ETC___d13042,
|
|
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8287,
|
|
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8288,
|
|
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631,
|
|
v__h296454,
|
|
v__h296972,
|
|
v__h306968,
|
|
v__h307199,
|
|
v__h310844,
|
|
v__h311075,
|
|
v__h325445,
|
|
v__h325676,
|
|
v__h328670,
|
|
v__h328901,
|
|
x__h600222;
|
|
|
|
// action method coreReq_start
|
|
assign RDY_coreReq_start = 1'd1 ;
|
|
assign CAN_FIRE_coreReq_start = 1'd1 ;
|
|
assign WILL_FIRE_coreReq_start = EN_coreReq_start ;
|
|
|
|
// action method coreReq_perfReq
|
|
assign RDY_coreReq_perfReq = perfReqQ$FULL_N ;
|
|
assign CAN_FIRE_coreReq_perfReq = perfReqQ$FULL_N ;
|
|
assign WILL_FIRE_coreReq_perfReq = EN_coreReq_perfReq ;
|
|
|
|
// actionvalue method coreIndInv_perfResp
|
|
assign coreIndInv_perfResp = { perfReqQ$D_OUT, 64'd0 } ;
|
|
assign RDY_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
|
|
assign CAN_FIRE_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
|
|
assign WILL_FIRE_coreIndInv_perfResp = EN_coreIndInv_perfResp ;
|
|
|
|
// action method coreIndInv_terminate
|
|
assign RDY_coreIndInv_terminate = csrf_terminate_module_terminateQ$EMPTY_N ;
|
|
assign CAN_FIRE_coreIndInv_terminate =
|
|
csrf_terminate_module_terminateQ$EMPTY_N ;
|
|
assign WILL_FIRE_coreIndInv_terminate = EN_coreIndInv_terminate ;
|
|
|
|
// value method dCacheToParent_rsToP_notEmpty
|
|
assign dCacheToParent_rsToP_notEmpty =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
|
|
assign RDY_dCacheToParent_rsToP_notEmpty = 1'd1 ;
|
|
|
|
// action method dCacheToParent_rsToP_deq
|
|
assign RDY_dCacheToParent_rsToP_deq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
|
|
assign CAN_FIRE_dCacheToParent_rsToP_deq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
|
|
assign WILL_FIRE_dCacheToParent_rsToP_deq = EN_dCacheToParent_rsToP_deq ;
|
|
|
|
// value method dCacheToParent_rsToP_first
|
|
assign dCacheToParent_rsToP_first =
|
|
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248,
|
|
!CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14575 } ;
|
|
assign RDY_dCacheToParent_rsToP_first =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
|
|
|
|
// value method dCacheToParent_rqToP_notEmpty
|
|
assign dCacheToParent_rqToP_notEmpty =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
|
|
assign RDY_dCacheToParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method dCacheToParent_rqToP_deq
|
|
assign RDY_dCacheToParent_rqToP_deq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
|
|
assign CAN_FIRE_dCacheToParent_rqToP_deq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
|
|
assign WILL_FIRE_dCacheToParent_rqToP_deq = EN_dCacheToParent_rqToP_deq ;
|
|
|
|
// value method dCacheToParent_rqToP_first
|
|
assign dCacheToParent_rqToP_first =
|
|
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14601 } ;
|
|
assign RDY_dCacheToParent_rqToP_first =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
|
|
|
|
// value method dCacheToParent_fromP_notFull
|
|
assign dCacheToParent_fromP_notFull =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
|
|
assign RDY_dCacheToParent_fromP_notFull = 1'd1 ;
|
|
|
|
// action method dCacheToParent_fromP_enq
|
|
assign RDY_dCacheToParent_fromP_enq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
|
|
assign CAN_FIRE_dCacheToParent_fromP_enq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
|
|
assign WILL_FIRE_dCacheToParent_fromP_enq = EN_dCacheToParent_fromP_enq ;
|
|
|
|
// value method iCacheToParent_rsToP_notEmpty
|
|
assign iCacheToParent_rsToP_notEmpty =
|
|
fetchStage$iMemIfc_to_parent_rsToP_notEmpty ;
|
|
assign RDY_iCacheToParent_rsToP_notEmpty = 1'd1 ;
|
|
|
|
// action method iCacheToParent_rsToP_deq
|
|
assign RDY_iCacheToParent_rsToP_deq =
|
|
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
|
|
assign CAN_FIRE_iCacheToParent_rsToP_deq =
|
|
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
|
|
assign WILL_FIRE_iCacheToParent_rsToP_deq = EN_iCacheToParent_rsToP_deq ;
|
|
|
|
// value method iCacheToParent_rsToP_first
|
|
assign iCacheToParent_rsToP_first =
|
|
fetchStage$iMemIfc_to_parent_rsToP_first ;
|
|
assign RDY_iCacheToParent_rsToP_first =
|
|
fetchStage$RDY_iMemIfc_to_parent_rsToP_first ;
|
|
|
|
// value method iCacheToParent_rqToP_notEmpty
|
|
assign iCacheToParent_rqToP_notEmpty =
|
|
fetchStage$iMemIfc_to_parent_rqToP_notEmpty ;
|
|
assign RDY_iCacheToParent_rqToP_notEmpty = 1'd1 ;
|
|
|
|
// action method iCacheToParent_rqToP_deq
|
|
assign RDY_iCacheToParent_rqToP_deq =
|
|
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
|
|
assign CAN_FIRE_iCacheToParent_rqToP_deq =
|
|
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
|
|
assign WILL_FIRE_iCacheToParent_rqToP_deq = EN_iCacheToParent_rqToP_deq ;
|
|
|
|
// value method iCacheToParent_rqToP_first
|
|
assign iCacheToParent_rqToP_first =
|
|
fetchStage$iMemIfc_to_parent_rqToP_first ;
|
|
assign RDY_iCacheToParent_rqToP_first =
|
|
fetchStage$RDY_iMemIfc_to_parent_rqToP_first ;
|
|
|
|
// value method iCacheToParent_fromP_notFull
|
|
assign iCacheToParent_fromP_notFull =
|
|
fetchStage$iMemIfc_to_parent_fromP_notFull ;
|
|
assign RDY_iCacheToParent_fromP_notFull = 1'd1 ;
|
|
|
|
// action method iCacheToParent_fromP_enq
|
|
assign RDY_iCacheToParent_fromP_enq =
|
|
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
|
|
assign CAN_FIRE_iCacheToParent_fromP_enq =
|
|
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
|
|
assign WILL_FIRE_iCacheToParent_fromP_enq = EN_iCacheToParent_fromP_enq ;
|
|
|
|
// value method tlbToMem_memReq_notEmpty
|
|
assign tlbToMem_memReq_notEmpty = l2Tlb$toMem_memReq_notEmpty ;
|
|
assign RDY_tlbToMem_memReq_notEmpty = 1'd1 ;
|
|
|
|
// action method tlbToMem_memReq_deq
|
|
assign RDY_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
|
|
assign CAN_FIRE_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
|
|
assign WILL_FIRE_tlbToMem_memReq_deq = EN_tlbToMem_memReq_deq ;
|
|
|
|
// value method tlbToMem_memReq_first
|
|
assign tlbToMem_memReq_first = l2Tlb$toMem_memReq_first ;
|
|
assign RDY_tlbToMem_memReq_first = l2Tlb$RDY_toMem_memReq_first ;
|
|
|
|
// value method tlbToMem_respLd_notFull
|
|
assign tlbToMem_respLd_notFull = l2Tlb$toMem_respLd_notFull ;
|
|
assign RDY_tlbToMem_respLd_notFull = 1'd1 ;
|
|
|
|
// action method tlbToMem_respLd_enq
|
|
assign RDY_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
|
|
assign CAN_FIRE_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
|
|
assign WILL_FIRE_tlbToMem_respLd_enq = EN_tlbToMem_respLd_enq ;
|
|
|
|
// value method mmioToPlatform_cRq_notEmpty
|
|
assign mmioToPlatform_cRq_notEmpty = !mmio_cRqQ_empty ;
|
|
assign RDY_mmioToPlatform_cRq_notEmpty = 1'd1 ;
|
|
|
|
// action method mmioToPlatform_cRq_deq
|
|
assign RDY_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
|
|
assign CAN_FIRE_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
|
|
assign WILL_FIRE_mmioToPlatform_cRq_deq = EN_mmioToPlatform_cRq_deq ;
|
|
|
|
// value method mmioToPlatform_cRq_first
|
|
assign mmioToPlatform_cRq_first =
|
|
{ mmio_cRqQ_data_0[141:78],
|
|
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1,
|
|
mmio_cRqQ_data_0[71:0] } ;
|
|
assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ;
|
|
|
|
// value method mmioToPlatform_pRs_notFull
|
|
assign mmioToPlatform_pRs_notFull = !mmio_pRsQ_full ;
|
|
assign RDY_mmioToPlatform_pRs_notFull = 1'd1 ;
|
|
|
|
// action method mmioToPlatform_pRs_enq
|
|
assign RDY_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
|
|
assign CAN_FIRE_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
|
|
assign WILL_FIRE_mmioToPlatform_pRs_enq = EN_mmioToPlatform_pRs_enq ;
|
|
|
|
// value method mmioToPlatform_pRq_notFull
|
|
assign mmioToPlatform_pRq_notFull = !mmio_pRqQ_full ;
|
|
assign RDY_mmioToPlatform_pRq_notFull = 1'd1 ;
|
|
|
|
// action method mmioToPlatform_pRq_enq
|
|
assign RDY_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
|
|
assign CAN_FIRE_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
|
|
assign WILL_FIRE_mmioToPlatform_pRq_enq = EN_mmioToPlatform_pRq_enq ;
|
|
|
|
// value method mmioToPlatform_cRs_notEmpty
|
|
assign mmioToPlatform_cRs_notEmpty = !mmio_cRsQ_empty ;
|
|
assign RDY_mmioToPlatform_cRs_notEmpty = 1'd1 ;
|
|
|
|
// action method mmioToPlatform_cRs_deq
|
|
assign RDY_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
|
|
assign CAN_FIRE_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
|
|
assign WILL_FIRE_mmioToPlatform_cRs_deq = EN_mmioToPlatform_cRs_deq ;
|
|
|
|
// value method mmioToPlatform_cRs_first
|
|
assign mmioToPlatform_cRs_first = mmio_cRsQ_data_0 ;
|
|
assign RDY_mmioToPlatform_cRs_first = !mmio_cRsQ_empty ;
|
|
|
|
// action method mmioToPlatform_setTime
|
|
assign RDY_mmioToPlatform_setTime = 1'd1 ;
|
|
assign CAN_FIRE_mmioToPlatform_setTime = 1'd1 ;
|
|
assign WILL_FIRE_mmioToPlatform_setTime = EN_mmioToPlatform_setTime ;
|
|
|
|
// actionvalue method sendDoStats
|
|
assign sendDoStats = csrf_stats_module_writeQ$D_OUT ;
|
|
assign RDY_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
|
|
assign CAN_FIRE_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
|
|
assign WILL_FIRE_sendDoStats = EN_sendDoStats ;
|
|
|
|
// action method recvDoStats
|
|
assign RDY_recvDoStats = 1'd1 ;
|
|
assign CAN_FIRE_recvDoStats = 1'd1 ;
|
|
assign WILL_FIRE_recvDoStats = EN_recvDoStats ;
|
|
|
|
// actionvalue method deadlock_dCacheCRqStuck_get
|
|
assign deadlock_dCacheCRqStuck_get = 73'h0AAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_deadlock_dCacheCRqStuck_get = 1'd0 ;
|
|
assign CAN_FIRE_deadlock_dCacheCRqStuck_get = 1'd0 ;
|
|
assign WILL_FIRE_deadlock_dCacheCRqStuck_get =
|
|
EN_deadlock_dCacheCRqStuck_get ;
|
|
|
|
// actionvalue method deadlock_dCachePRqStuck_get
|
|
assign deadlock_dCachePRqStuck_get = 68'hAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_deadlock_dCachePRqStuck_get = 1'd0 ;
|
|
assign CAN_FIRE_deadlock_dCachePRqStuck_get = 1'd0 ;
|
|
assign WILL_FIRE_deadlock_dCachePRqStuck_get =
|
|
EN_deadlock_dCachePRqStuck_get ;
|
|
|
|
// actionvalue method deadlock_iCacheCRqStuck_get
|
|
assign deadlock_iCacheCRqStuck_get = fetchStage$iMemIfc_cRqStuck_get ;
|
|
assign RDY_deadlock_iCacheCRqStuck_get =
|
|
fetchStage$RDY_iMemIfc_cRqStuck_get ;
|
|
assign CAN_FIRE_deadlock_iCacheCRqStuck_get =
|
|
fetchStage$RDY_iMemIfc_cRqStuck_get ;
|
|
assign WILL_FIRE_deadlock_iCacheCRqStuck_get =
|
|
EN_deadlock_iCacheCRqStuck_get ;
|
|
|
|
// actionvalue method deadlock_iCachePRqStuck_get
|
|
assign deadlock_iCachePRqStuck_get = fetchStage$iMemIfc_pRqStuck_get ;
|
|
assign RDY_deadlock_iCachePRqStuck_get =
|
|
fetchStage$RDY_iMemIfc_pRqStuck_get ;
|
|
assign CAN_FIRE_deadlock_iCachePRqStuck_get =
|
|
fetchStage$RDY_iMemIfc_pRqStuck_get ;
|
|
assign WILL_FIRE_deadlock_iCachePRqStuck_get =
|
|
EN_deadlock_iCachePRqStuck_get ;
|
|
|
|
// actionvalue method deadlock_renameInstStuck_get
|
|
assign deadlock_renameInstStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_deadlock_renameInstStuck_get = 1'd0 ;
|
|
assign CAN_FIRE_deadlock_renameInstStuck_get = 1'd0 ;
|
|
assign WILL_FIRE_deadlock_renameInstStuck_get =
|
|
EN_deadlock_renameInstStuck_get ;
|
|
|
|
// actionvalue method deadlock_renameCorrectPathStuck_get
|
|
assign deadlock_renameCorrectPathStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_deadlock_renameCorrectPathStuck_get = 1'd0 ;
|
|
assign CAN_FIRE_deadlock_renameCorrectPathStuck_get = 1'd0 ;
|
|
assign WILL_FIRE_deadlock_renameCorrectPathStuck_get =
|
|
EN_deadlock_renameCorrectPathStuck_get ;
|
|
|
|
// actionvalue method deadlock_commitInstStuck_get
|
|
assign deadlock_commitInstStuck_get =
|
|
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_deadlock_commitInstStuck_get = 1'd0 ;
|
|
assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ;
|
|
assign WILL_FIRE_deadlock_commitInstStuck_get =
|
|
EN_deadlock_commitInstStuck_get ;
|
|
|
|
// actionvalue method deadlock_commitUserInstStuck_get
|
|
assign deadlock_commitUserInstStuck_get =
|
|
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ;
|
|
assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ;
|
|
assign WILL_FIRE_deadlock_commitUserInstStuck_get =
|
|
EN_deadlock_commitUserInstStuck_get ;
|
|
|
|
// action method deadlock_checkStarted_get
|
|
assign RDY_deadlock_checkStarted_get = 1'd0 ;
|
|
assign CAN_FIRE_deadlock_checkStarted_get = 1'd0 ;
|
|
assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ;
|
|
|
|
// actionvalue method renameDebug_renameErr_get
|
|
assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign RDY_renameDebug_renameErr_get = 1'd0 ;
|
|
assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ;
|
|
assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ;
|
|
|
|
// action method setMEIP
|
|
assign RDY_setMEIP = 1'd1 ;
|
|
assign CAN_FIRE_setMEIP = 1'd1 ;
|
|
assign WILL_FIRE_setMEIP = EN_setMEIP ;
|
|
|
|
// action method setSEIP
|
|
assign RDY_setSEIP = 1'd1 ;
|
|
assign CAN_FIRE_setSEIP = 1'd1 ;
|
|
assign WILL_FIRE_setSEIP = EN_setSEIP ;
|
|
|
|
// action method setDEIP
|
|
assign RDY_setDEIP = 1'd1 ;
|
|
assign CAN_FIRE_setDEIP = 1'd1 ;
|
|
assign WILL_FIRE_setDEIP = EN_setDEIP ;
|
|
|
|
// submodule coreFix_aluExe_0_dispToRegQ
|
|
mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_0_dispToRegQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_0_dispToRegQ$EN_enq),
|
|
.EN_deq(coreFix_aluExe_0_dispToRegQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_0_dispToRegQ$RDY_enq),
|
|
.RDY_deq(coreFix_aluExe_0_dispToRegQ$RDY_deq),
|
|
.first(coreFix_aluExe_0_dispToRegQ$first),
|
|
.RDY_first(coreFix_aluExe_0_dispToRegQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_aluExe_0_exeToFinQ
|
|
mkAluExeToFinFifo coreFix_aluExe_0_exeToFinQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_0_exeToFinQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_0_exeToFinQ$EN_enq),
|
|
.EN_deq(coreFix_aluExe_0_exeToFinQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_0_exeToFinQ$RDY_enq),
|
|
.RDY_deq(coreFix_aluExe_0_exeToFinQ$RDY_deq),
|
|
.first(coreFix_aluExe_0_exeToFinQ$first),
|
|
.RDY_first(coreFix_aluExe_0_exeToFinQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_aluExe_0_regToExeQ
|
|
mkAluRegToExeFifo coreFix_aluExe_0_regToExeQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_0_regToExeQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_0_regToExeQ$EN_enq),
|
|
.EN_deq(coreFix_aluExe_0_regToExeQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_0_regToExeQ$RDY_enq),
|
|
.RDY_deq(coreFix_aluExe_0_regToExeQ$RDY_deq),
|
|
.first(coreFix_aluExe_0_regToExeQ$first),
|
|
.RDY_first(coreFix_aluExe_0_regToExeQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_aluExe_0_rsAlu
|
|
mkReservationStationAlu coreFix_aluExe_0_rsAlu(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_0_rsAlu$enq_x),
|
|
.setRegReady_0_put(coreFix_aluExe_0_rsAlu$setRegReady_0_put),
|
|
.setRegReady_1_put(coreFix_aluExe_0_rsAlu$setRegReady_1_put),
|
|
.setRegReady_2_put(coreFix_aluExe_0_rsAlu$setRegReady_2_put),
|
|
.setRegReady_3_put(coreFix_aluExe_0_rsAlu$setRegReady_3_put),
|
|
.setRegReady_4_put(coreFix_aluExe_0_rsAlu$setRegReady_4_put),
|
|
.setRobEnqTime_t(coreFix_aluExe_0_rsAlu$setRobEnqTime_t),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_0_rsAlu$EN_enq),
|
|
.EN_setRobEnqTime(coreFix_aluExe_0_rsAlu$EN_setRobEnqTime),
|
|
.EN_doDispatch(coreFix_aluExe_0_rsAlu$EN_doDispatch),
|
|
.EN_setRegReady_0_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put),
|
|
.EN_setRegReady_1_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put),
|
|
.EN_setRegReady_2_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put),
|
|
.EN_setRegReady_3_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put),
|
|
.EN_setRegReady_4_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_0_rsAlu$RDY_enq),
|
|
.canEnq(coreFix_aluExe_0_rsAlu$canEnq),
|
|
.RDY_canEnq(),
|
|
.RDY_setRobEnqTime(),
|
|
.dispatchData(coreFix_aluExe_0_rsAlu$dispatchData),
|
|
.RDY_dispatchData(coreFix_aluExe_0_rsAlu$RDY_dispatchData),
|
|
.RDY_doDispatch(coreFix_aluExe_0_rsAlu$RDY_doDispatch),
|
|
.RDY_setRegReady_0_put(),
|
|
.RDY_setRegReady_1_put(),
|
|
.RDY_setRegReady_2_put(),
|
|
.RDY_setRegReady_3_put(),
|
|
.RDY_setRegReady_4_put(),
|
|
.approximateCount(coreFix_aluExe_0_rsAlu$approximateCount),
|
|
.RDY_approximateCount(),
|
|
.isFull_ehrPort0(),
|
|
.RDY_isFull_ehrPort0(),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_aluExe_1_dispToRegQ
|
|
mkAluDispToRegFifo coreFix_aluExe_1_dispToRegQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_1_dispToRegQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_1_dispToRegQ$EN_enq),
|
|
.EN_deq(coreFix_aluExe_1_dispToRegQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_1_dispToRegQ$RDY_enq),
|
|
.RDY_deq(coreFix_aluExe_1_dispToRegQ$RDY_deq),
|
|
.first(coreFix_aluExe_1_dispToRegQ$first),
|
|
.RDY_first(coreFix_aluExe_1_dispToRegQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_aluExe_1_exeToFinQ
|
|
mkAluExeToFinFifo coreFix_aluExe_1_exeToFinQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_1_exeToFinQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_1_exeToFinQ$EN_enq),
|
|
.EN_deq(coreFix_aluExe_1_exeToFinQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_1_exeToFinQ$RDY_enq),
|
|
.RDY_deq(coreFix_aluExe_1_exeToFinQ$RDY_deq),
|
|
.first(coreFix_aluExe_1_exeToFinQ$first),
|
|
.RDY_first(coreFix_aluExe_1_exeToFinQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_aluExe_1_regToExeQ
|
|
mkAluRegToExeFifo coreFix_aluExe_1_regToExeQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_1_regToExeQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_1_regToExeQ$EN_enq),
|
|
.EN_deq(coreFix_aluExe_1_regToExeQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_1_regToExeQ$RDY_enq),
|
|
.RDY_deq(coreFix_aluExe_1_regToExeQ$RDY_deq),
|
|
.first(coreFix_aluExe_1_regToExeQ$first),
|
|
.RDY_first(coreFix_aluExe_1_regToExeQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_aluExe_1_rsAlu
|
|
mkReservationStationAlu coreFix_aluExe_1_rsAlu(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_aluExe_1_rsAlu$enq_x),
|
|
.setRegReady_0_put(coreFix_aluExe_1_rsAlu$setRegReady_0_put),
|
|
.setRegReady_1_put(coreFix_aluExe_1_rsAlu$setRegReady_1_put),
|
|
.setRegReady_2_put(coreFix_aluExe_1_rsAlu$setRegReady_2_put),
|
|
.setRegReady_3_put(coreFix_aluExe_1_rsAlu$setRegReady_3_put),
|
|
.setRegReady_4_put(coreFix_aluExe_1_rsAlu$setRegReady_4_put),
|
|
.setRobEnqTime_t(coreFix_aluExe_1_rsAlu$setRobEnqTime_t),
|
|
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_aluExe_1_rsAlu$EN_enq),
|
|
.EN_setRobEnqTime(coreFix_aluExe_1_rsAlu$EN_setRobEnqTime),
|
|
.EN_doDispatch(coreFix_aluExe_1_rsAlu$EN_doDispatch),
|
|
.EN_setRegReady_0_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put),
|
|
.EN_setRegReady_1_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put),
|
|
.EN_setRegReady_2_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put),
|
|
.EN_setRegReady_3_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put),
|
|
.EN_setRegReady_4_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_aluExe_1_rsAlu$RDY_enq),
|
|
.canEnq(coreFix_aluExe_1_rsAlu$canEnq),
|
|
.RDY_canEnq(),
|
|
.RDY_setRobEnqTime(),
|
|
.dispatchData(coreFix_aluExe_1_rsAlu$dispatchData),
|
|
.RDY_dispatchData(coreFix_aluExe_1_rsAlu$RDY_dispatchData),
|
|
.RDY_doDispatch(coreFix_aluExe_1_rsAlu$RDY_doDispatch),
|
|
.RDY_setRegReady_0_put(),
|
|
.RDY_setRegReady_1_put(),
|
|
.RDY_setRegReady_2_put(),
|
|
.RDY_setRegReady_3_put(),
|
|
.RDY_setRegReady_4_put(),
|
|
.approximateCount(coreFix_aluExe_1_rsAlu$approximateCount),
|
|
.RDY_approximateCount(),
|
|
.isFull_ehrPort0(),
|
|
.RDY_isFull_ehrPort0(),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
|
|
mkFpuMulDivDispToRegFifo coreFix_fpuMulDivExe_0_dispToRegQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_dispToRegQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq),
|
|
.first(coreFix_fpuMulDivExe_0_dispToRegQ$first),
|
|
.RDY_first(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
|
|
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_divQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq),
|
|
.first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data),
|
|
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data),
|
|
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned),
|
|
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
|
|
mkDoubleDiv coreFix_fpuMulDivExe_0_fpuExec_double_div(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put),
|
|
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put),
|
|
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get),
|
|
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put),
|
|
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get),
|
|
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
|
|
mkDoubleFMA coreFix_fpuMulDivExe_0_fpuExec_double_fma(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put),
|
|
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put),
|
|
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get),
|
|
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put),
|
|
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get),
|
|
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
|
|
mkDoubleSqrt coreFix_fpuMulDivExe_0_fpuExec_double_sqrt(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put),
|
|
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put),
|
|
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get),
|
|
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put),
|
|
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get),
|
|
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
|
|
mkFmaExecQ coreFix_fpuMulDivExe_0_fpuExec_fmaQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq),
|
|
.first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data),
|
|
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data),
|
|
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned),
|
|
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
|
|
mkSimpleRespQ coreFix_fpuMulDivExe_0_fpuExec_simpleQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq),
|
|
.first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first),
|
|
.RDY_first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
|
|
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_sqrtQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq),
|
|
.first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data),
|
|
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data),
|
|
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned),
|
|
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
|
|
mkDivExecQ coreFix_fpuMulDivExe_0_mulDivExec_divQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq),
|
|
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data),
|
|
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data),
|
|
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned),
|
|
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
|
|
int_div_unsigned coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc(.aclk(CLK),
|
|
.s_axis_dividend_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata),
|
|
.s_axis_dividend_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser),
|
|
.s_axis_divisor_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata),
|
|
.s_axis_dividend_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid),
|
|
.s_axis_divisor_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid),
|
|
.m_axis_dout_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready),
|
|
.s_axis_dividend_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready),
|
|
.s_axis_divisor_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready),
|
|
.m_axis_dout_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid),
|
|
.m_axis_dout_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata),
|
|
.m_axis_dout_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
|
|
reset_guard coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg(.CLK(CLK),
|
|
.RST(RST_N),
|
|
.IS_READY(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
|
|
mkMulExecQ coreFix_fpuMulDivExe_0_mulDivExec_mulQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq),
|
|
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data),
|
|
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data),
|
|
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned),
|
|
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
|
|
int_mul_signed coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned(.CLK(CLK),
|
|
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A),
|
|
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B),
|
|
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
|
|
int_mul_signed_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned(.CLK(CLK),
|
|
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A),
|
|
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B),
|
|
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
|
|
int_mul_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned(.CLK(CLK),
|
|
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A),
|
|
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B),
|
|
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
|
|
SizedFIFO #(.p1width(32'd128),
|
|
.p2depth(32'd3),
|
|
.p3cntr_width(32'd1),
|
|
.guarded(32'd0)) coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN),
|
|
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ),
|
|
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ),
|
|
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR),
|
|
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT),
|
|
.FULL_N(),
|
|
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N));
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_regToExeQ
|
|
mkFpuMulDivRegToExeFifo coreFix_fpuMulDivExe_0_regToExeQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_regToExeQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_regToExeQ$EN_enq),
|
|
.EN_deq(coreFix_fpuMulDivExe_0_regToExeQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq),
|
|
.RDY_deq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq),
|
|
.first(coreFix_fpuMulDivExe_0_regToExeQ$first),
|
|
.RDY_first(coreFix_fpuMulDivExe_0_regToExeQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
|
|
mkReservationStationFpuMulDiv coreFix_fpuMulDivExe_0_rsFpuMulDiv(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x),
|
|
.setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put),
|
|
.setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put),
|
|
.setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put),
|
|
.setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put),
|
|
.setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put),
|
|
.setRobEnqTime_t(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t),
|
|
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq),
|
|
.EN_setRobEnqTime(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime),
|
|
.EN_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch),
|
|
.EN_setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put),
|
|
.EN_setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put),
|
|
.EN_setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put),
|
|
.EN_setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put),
|
|
.EN_setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq),
|
|
.canEnq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq),
|
|
.RDY_canEnq(),
|
|
.RDY_setRobEnqTime(),
|
|
.dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData),
|
|
.RDY_dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData),
|
|
.RDY_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch),
|
|
.RDY_setRegReady_0_put(),
|
|
.RDY_setRegReady_1_put(),
|
|
.RDY_setRegReady_2_put(),
|
|
.RDY_setRegReady_3_put(),
|
|
.RDY_setRegReady_4_put(),
|
|
.approximateCount(),
|
|
.RDY_approximateCount(),
|
|
.isFull_ehrPort0(),
|
|
.RDY_isFull_ehrPort0(),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
|
|
mkDCRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_cRqMshr(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.cRqTransfer_getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r),
|
|
.cRqTransfer_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n),
|
|
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n),
|
|
.pipelineResp_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n),
|
|
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n),
|
|
.pipelineResp_getSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n),
|
|
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n),
|
|
.pipelineResp_searchEndOfChain_addr(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr),
|
|
.pipelineResp_setData_d(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d),
|
|
.pipelineResp_setData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n),
|
|
.pipelineResp_setStateSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n),
|
|
.pipelineResp_setStateSlot_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot),
|
|
.pipelineResp_setStateSlot_state(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state),
|
|
.pipelineResp_setSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n),
|
|
.pipelineResp_setSucc_succ(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ),
|
|
.sendRqToP_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n),
|
|
.sendRqToP_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n),
|
|
.sendRsToP_cRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n),
|
|
.sendRsToP_cRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n),
|
|
.sendRsToP_cRq_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n),
|
|
.sendRsToP_cRq_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n),
|
|
.sendRsToP_cRq_setWaitSt_setSlot_clearData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n),
|
|
.sendRsToP_cRq_setWaitSt_setSlot_clearData_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot),
|
|
.EN_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit),
|
|
.EN_sendRsToP_cRq_setWaitSt_setSlot_clearData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData),
|
|
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry),
|
|
.EN_pipelineResp_setData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData),
|
|
.EN_pipelineResp_setStateSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot),
|
|
.EN_pipelineResp_setSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc),
|
|
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get),
|
|
.cRqTransfer_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq),
|
|
.RDY_cRqTransfer_getRq(),
|
|
.cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit),
|
|
.RDY_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit),
|
|
.sendRsToP_cRq_getState(),
|
|
.RDY_sendRsToP_cRq_getState(),
|
|
.sendRsToP_cRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq),
|
|
.RDY_sendRsToP_cRq_getRq(),
|
|
.sendRsToP_cRq_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot),
|
|
.RDY_sendRsToP_cRq_getSlot(),
|
|
.sendRsToP_cRq_getData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData),
|
|
.RDY_sendRsToP_cRq_getData(),
|
|
.RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData(),
|
|
.sendRqToP_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq),
|
|
.RDY_sendRqToP_getRq(),
|
|
.sendRqToP_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot),
|
|
.RDY_sendRqToP_getSlot(),
|
|
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry),
|
|
.pipelineResp_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState),
|
|
.RDY_pipelineResp_getState(),
|
|
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq),
|
|
.RDY_pipelineResp_getRq(),
|
|
.pipelineResp_getSlot(),
|
|
.RDY_pipelineResp_getSlot(),
|
|
.RDY_pipelineResp_setData(),
|
|
.RDY_pipelineResp_setStateSlot(),
|
|
.pipelineResp_getSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc),
|
|
.RDY_pipelineResp_getSucc(),
|
|
.RDY_pipelineResp_setSucc(),
|
|
.pipelineResp_searchEndOfChain(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain),
|
|
.RDY_pipelineResp_searchEndOfChain(),
|
|
.emptyForFlush(),
|
|
.RDY_emptyForFlush(),
|
|
.stuck_get(),
|
|
.RDY_stuck_get());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
|
|
mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r),
|
|
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n),
|
|
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n),
|
|
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n),
|
|
.pipelineResp_setDone_setData_d(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d),
|
|
.pipelineResp_setDone_setData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n),
|
|
.sendRsToP_pRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n),
|
|
.sendRsToP_pRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n),
|
|
.sendRsToP_pRq_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n),
|
|
.EN_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit),
|
|
.EN_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
|
|
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry),
|
|
.EN_pipelineResp_setDone_setData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData),
|
|
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get),
|
|
.getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit),
|
|
.RDY_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit),
|
|
.sendRsToP_pRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq),
|
|
.RDY_sendRsToP_pRq_getRq(),
|
|
.sendRsToP_pRq_getData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData),
|
|
.RDY_sendRsToP_pRq_getData(),
|
|
.RDY_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
|
|
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq),
|
|
.RDY_pipelineResp_getRq(),
|
|
.pipelineResp_getState(),
|
|
.RDY_pipelineResp_getState(),
|
|
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry),
|
|
.RDY_pipelineResp_setDone_setData(),
|
|
.stuck_get(),
|
|
.RDY_stuck_get());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
|
|
mkDPipeline coreFix_memExe_dMem_cache_m_banks_0_pipeline(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.deqWrite_swapRq(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq),
|
|
.deqWrite_updateRep(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep),
|
|
.deqWrite_wrRam(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam),
|
|
.send_r(coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r),
|
|
.EN_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send),
|
|
.EN_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite),
|
|
.RDY_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send),
|
|
.first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first),
|
|
.RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first),
|
|
.RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
|
|
SizedFIFO #(.p1width(32'd3),
|
|
.p2depth(32'd8),
|
|
.p3cntr_width(32'd3),
|
|
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN),
|
|
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ),
|
|
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ),
|
|
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR),
|
|
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT),
|
|
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N),
|
|
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
|
|
FIFO2 #(.width(32'd3),
|
|
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN),
|
|
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ),
|
|
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ),
|
|
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR),
|
|
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT),
|
|
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N),
|
|
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
|
|
FIFO2 #(.width(32'd3),
|
|
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN),
|
|
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ),
|
|
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ),
|
|
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR),
|
|
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT),
|
|
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N),
|
|
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
|
|
SizedFIFO #(.p1width(32'd4),
|
|
.p2depth(32'd12),
|
|
.p3cntr_width(32'd4),
|
|
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN),
|
|
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ),
|
|
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ),
|
|
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR),
|
|
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT),
|
|
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N),
|
|
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_dTlb
|
|
mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.perf_req_r(coreFix_memExe_dTlb$perf_req_r),
|
|
.perf_setStatus_doStats(coreFix_memExe_dTlb$perf_setStatus_doStats),
|
|
.procReq_req(coreFix_memExe_dTlb$procReq_req),
|
|
.specUpdate_correctSpeculation_mask(coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag),
|
|
.toParent_ldTransRsFromP_enq_x(coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x),
|
|
.updateVMInfo_vm(coreFix_memExe_dTlb$updateVMInfo_vm),
|
|
.EN_flush(coreFix_memExe_dTlb$EN_flush),
|
|
.EN_updateVMInfo(coreFix_memExe_dTlb$EN_updateVMInfo),
|
|
.EN_procReq(coreFix_memExe_dTlb$EN_procReq),
|
|
.EN_deqProcResp(coreFix_memExe_dTlb$EN_deqProcResp),
|
|
.EN_toParent_rqToP_deq(coreFix_memExe_dTlb$EN_toParent_rqToP_deq),
|
|
.EN_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq),
|
|
.EN_toParent_flush_request_get(coreFix_memExe_dTlb$EN_toParent_flush_request_get),
|
|
.EN_toParent_flush_response_put(coreFix_memExe_dTlb$EN_toParent_flush_response_put),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation),
|
|
.EN_perf_setStatus(coreFix_memExe_dTlb$EN_perf_setStatus),
|
|
.EN_perf_req(coreFix_memExe_dTlb$EN_perf_req),
|
|
.EN_perf_resp(coreFix_memExe_dTlb$EN_perf_resp),
|
|
.flush_done(coreFix_memExe_dTlb$flush_done),
|
|
.RDY_flush_done(),
|
|
.RDY_flush(coreFix_memExe_dTlb$RDY_flush),
|
|
.RDY_updateVMInfo(),
|
|
.noPendingReq(coreFix_memExe_dTlb$noPendingReq),
|
|
.RDY_noPendingReq(),
|
|
.RDY_procReq(coreFix_memExe_dTlb$RDY_procReq),
|
|
.procResp(coreFix_memExe_dTlb$procResp),
|
|
.RDY_procResp(coreFix_memExe_dTlb$RDY_procResp),
|
|
.RDY_deqProcResp(coreFix_memExe_dTlb$RDY_deqProcResp),
|
|
.toParent_rqToP_notEmpty(),
|
|
.RDY_toParent_rqToP_notEmpty(),
|
|
.RDY_toParent_rqToP_deq(coreFix_memExe_dTlb$RDY_toParent_rqToP_deq),
|
|
.toParent_rqToP_first(coreFix_memExe_dTlb$toParent_rqToP_first),
|
|
.RDY_toParent_rqToP_first(coreFix_memExe_dTlb$RDY_toParent_rqToP_first),
|
|
.toParent_ldTransRsFromP_notFull(),
|
|
.RDY_toParent_ldTransRsFromP_notFull(),
|
|
.RDY_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq),
|
|
.RDY_toParent_flush_request_get(coreFix_memExe_dTlb$RDY_toParent_flush_request_get),
|
|
.RDY_toParent_flush_response_put(coreFix_memExe_dTlb$RDY_toParent_flush_response_put),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation(),
|
|
.RDY_perf_setStatus(),
|
|
.RDY_perf_req(),
|
|
.perf_resp(),
|
|
.RDY_perf_resp(),
|
|
.perf_respValid(),
|
|
.RDY_perf_respValid());
|
|
|
|
// submodule coreFix_memExe_dispToRegQ
|
|
mkMemDispToRegFifo coreFix_memExe_dispToRegQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_memExe_dispToRegQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_memExe_dispToRegQ$EN_enq),
|
|
.EN_deq(coreFix_memExe_dispToRegQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_memExe_dispToRegQ$RDY_enq),
|
|
.RDY_deq(coreFix_memExe_dispToRegQ$RDY_deq),
|
|
.first(coreFix_memExe_dispToRegQ$first),
|
|
.RDY_first(coreFix_memExe_dispToRegQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_lsq
|
|
mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enqLd_dst(coreFix_memExe_lsq$enqLd_dst),
|
|
.enqLd_inst_tag(coreFix_memExe_lsq$enqLd_inst_tag),
|
|
.enqLd_mem_inst(coreFix_memExe_lsq$enqLd_mem_inst),
|
|
.enqLd_spec_bits(coreFix_memExe_lsq$enqLd_spec_bits),
|
|
.enqSt_dst(coreFix_memExe_lsq$enqSt_dst),
|
|
.enqSt_inst_tag(coreFix_memExe_lsq$enqSt_inst_tag),
|
|
.enqSt_mem_inst(coreFix_memExe_lsq$enqSt_mem_inst),
|
|
.enqSt_spec_bits(coreFix_memExe_lsq$enqSt_spec_bits),
|
|
.getHit_t(coreFix_memExe_lsq$getHit_t),
|
|
.getOrigBE_t(coreFix_memExe_lsq$getOrigBE_t),
|
|
.issueLd_lsqTag(coreFix_memExe_lsq$issueLd_lsqTag),
|
|
.issueLd_paddr(coreFix_memExe_lsq$issueLd_paddr),
|
|
.issueLd_sbRes(coreFix_memExe_lsq$issueLd_sbRes),
|
|
.issueLd_shiftedBE(coreFix_memExe_lsq$issueLd_shiftedBE),
|
|
.respLd_alignedData(coreFix_memExe_lsq$respLd_alignedData),
|
|
.respLd_t(coreFix_memExe_lsq$respLd_t),
|
|
.setAtCommit_0_put(coreFix_memExe_lsq$setAtCommit_0_put),
|
|
.setAtCommit_1_put(coreFix_memExe_lsq$setAtCommit_1_put),
|
|
.specUpdate_correctSpeculation_mask(coreFix_memExe_lsq$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag),
|
|
.updateAddr_fault(coreFix_memExe_lsq$updateAddr_fault),
|
|
.updateAddr_isMMIO(coreFix_memExe_lsq$updateAddr_isMMIO),
|
|
.updateAddr_lsqTag(coreFix_memExe_lsq$updateAddr_lsqTag),
|
|
.updateAddr_paddr(coreFix_memExe_lsq$updateAddr_paddr),
|
|
.updateAddr_shiftedBE(coreFix_memExe_lsq$updateAddr_shiftedBE),
|
|
.updateData_d(coreFix_memExe_lsq$updateData_d),
|
|
.updateData_t(coreFix_memExe_lsq$updateData_t),
|
|
.wakeupLdStalledBySB_sbIdx(coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx),
|
|
.EN_enqLd(coreFix_memExe_lsq$EN_enqLd),
|
|
.EN_enqSt(coreFix_memExe_lsq$EN_enqSt),
|
|
.EN_getHit(coreFix_memExe_lsq$EN_getHit),
|
|
.EN_updateData(coreFix_memExe_lsq$EN_updateData),
|
|
.EN_updateAddr(coreFix_memExe_lsq$EN_updateAddr),
|
|
.EN_issueLd(coreFix_memExe_lsq$EN_issueLd),
|
|
.EN_getIssueLd(coreFix_memExe_lsq$EN_getIssueLd),
|
|
.EN_respLd(coreFix_memExe_lsq$EN_respLd),
|
|
.EN_deqLd(coreFix_memExe_lsq$EN_deqLd),
|
|
.EN_deqSt(coreFix_memExe_lsq$EN_deqSt),
|
|
.EN_wakeupLdStalledBySB(coreFix_memExe_lsq$EN_wakeupLdStalledBySB),
|
|
.EN_setAtCommit_0_put(coreFix_memExe_lsq$EN_setAtCommit_0_put),
|
|
.EN_setAtCommit_1_put(coreFix_memExe_lsq$EN_setAtCommit_1_put),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_memExe_lsq$EN_specUpdate_correctSpeculation),
|
|
.enqLdTag(coreFix_memExe_lsq$enqLdTag),
|
|
.RDY_enqLdTag(),
|
|
.enqStTag(coreFix_memExe_lsq$enqStTag),
|
|
.RDY_enqStTag(),
|
|
.RDY_enqLd(coreFix_memExe_lsq$RDY_enqLd),
|
|
.RDY_enqSt(coreFix_memExe_lsq$RDY_enqSt),
|
|
.getOrigBE(coreFix_memExe_lsq$getOrigBE),
|
|
.RDY_getOrigBE(),
|
|
.getHit(coreFix_memExe_lsq$getHit),
|
|
.RDY_getHit(),
|
|
.RDY_updateData(),
|
|
.updateAddr(coreFix_memExe_lsq$updateAddr),
|
|
.RDY_updateAddr(),
|
|
.issueLd(coreFix_memExe_lsq$issueLd),
|
|
.RDY_issueLd(),
|
|
.getIssueLd(coreFix_memExe_lsq$getIssueLd),
|
|
.RDY_getIssueLd(coreFix_memExe_lsq$RDY_getIssueLd),
|
|
.respLd(coreFix_memExe_lsq$respLd),
|
|
.RDY_respLd(),
|
|
.firstLd(coreFix_memExe_lsq$firstLd),
|
|
.RDY_firstLd(coreFix_memExe_lsq$RDY_firstLd),
|
|
.RDY_deqLd(coreFix_memExe_lsq$RDY_deqLd),
|
|
.firstSt(coreFix_memExe_lsq$firstSt),
|
|
.RDY_firstSt(coreFix_memExe_lsq$RDY_firstSt),
|
|
.RDY_deqSt(coreFix_memExe_lsq$RDY_deqSt),
|
|
.RDY_wakeupLdStalledBySB(),
|
|
.stqEmpty(coreFix_memExe_lsq$stqEmpty),
|
|
.RDY_stqEmpty(),
|
|
.RDY_setAtCommit_0_put(),
|
|
.RDY_setAtCommit_1_put(),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation(),
|
|
.stqFull_ehrPort0(),
|
|
.RDY_stqFull_ehrPort0(),
|
|
.ldqFull_ehrPort0(),
|
|
.RDY_ldqFull_ehrPort0(),
|
|
.noWrongPathLoads(),
|
|
.RDY_noWrongPathLoads());
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_regToExeQ
|
|
mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_memExe_regToExeQ$enq_x),
|
|
.specUpdate_correctSpeculation_mask(coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_memExe_regToExeQ$EN_enq),
|
|
.EN_deq(coreFix_memExe_regToExeQ$EN_deq),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_memExe_regToExeQ$RDY_enq),
|
|
.RDY_deq(coreFix_memExe_regToExeQ$RDY_deq),
|
|
.first(coreFix_memExe_regToExeQ$first),
|
|
.RDY_first(coreFix_memExe_regToExeQ$RDY_first),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN),
|
|
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN),
|
|
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_reqStQ_full_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_full_dummy2_0$EN),
|
|
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqStQ_full_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_full_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_reqStQ_full_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_reqStQ_full_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN),
|
|
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule coreFix_memExe_rsMem
|
|
mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.enq_x(coreFix_memExe_rsMem$enq_x),
|
|
.setRegReady_0_put(coreFix_memExe_rsMem$setRegReady_0_put),
|
|
.setRegReady_1_put(coreFix_memExe_rsMem$setRegReady_1_put),
|
|
.setRegReady_2_put(coreFix_memExe_rsMem$setRegReady_2_put),
|
|
.setRegReady_3_put(coreFix_memExe_rsMem$setRegReady_3_put),
|
|
.setRegReady_4_put(coreFix_memExe_rsMem$setRegReady_4_put),
|
|
.setRobEnqTime_t(coreFix_memExe_rsMem$setRobEnqTime_t),
|
|
.specUpdate_correctSpeculation_mask(coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_enq(coreFix_memExe_rsMem$EN_enq),
|
|
.EN_setRobEnqTime(coreFix_memExe_rsMem$EN_setRobEnqTime),
|
|
.EN_doDispatch(coreFix_memExe_rsMem$EN_doDispatch),
|
|
.EN_setRegReady_0_put(coreFix_memExe_rsMem$EN_setRegReady_0_put),
|
|
.EN_setRegReady_1_put(coreFix_memExe_rsMem$EN_setRegReady_1_put),
|
|
.EN_setRegReady_2_put(coreFix_memExe_rsMem$EN_setRegReady_2_put),
|
|
.EN_setRegReady_3_put(coreFix_memExe_rsMem$EN_setRegReady_3_put),
|
|
.EN_setRegReady_4_put(coreFix_memExe_rsMem$EN_setRegReady_4_put),
|
|
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation),
|
|
.RDY_enq(coreFix_memExe_rsMem$RDY_enq),
|
|
.canEnq(coreFix_memExe_rsMem$canEnq),
|
|
.RDY_canEnq(),
|
|
.RDY_setRobEnqTime(),
|
|
.dispatchData(coreFix_memExe_rsMem$dispatchData),
|
|
.RDY_dispatchData(coreFix_memExe_rsMem$RDY_dispatchData),
|
|
.RDY_doDispatch(coreFix_memExe_rsMem$RDY_doDispatch),
|
|
.RDY_setRegReady_0_put(),
|
|
.RDY_setRegReady_1_put(),
|
|
.RDY_setRegReady_2_put(),
|
|
.RDY_setRegReady_3_put(),
|
|
.RDY_setRegReady_4_put(),
|
|
.approximateCount(),
|
|
.RDY_approximateCount(),
|
|
.isFull_ehrPort0(),
|
|
.RDY_isFull_ehrPort0(),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule coreFix_memExe_stb
|
|
mkStoreBufferEhr coreFix_memExe_stb(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.deq_idx(coreFix_memExe_stb$deq_idx),
|
|
.enq_be(coreFix_memExe_stb$enq_be),
|
|
.enq_data(coreFix_memExe_stb$enq_data),
|
|
.enq_idx(coreFix_memExe_stb$enq_idx),
|
|
.enq_paddr(coreFix_memExe_stb$enq_paddr),
|
|
.getEnqIndex_paddr(coreFix_memExe_stb$getEnqIndex_paddr),
|
|
.noMatchLdQ_be(coreFix_memExe_stb$noMatchLdQ_be),
|
|
.noMatchLdQ_paddr(coreFix_memExe_stb$noMatchLdQ_paddr),
|
|
.noMatchStQ_be(coreFix_memExe_stb$noMatchStQ_be),
|
|
.noMatchStQ_paddr(coreFix_memExe_stb$noMatchStQ_paddr),
|
|
.search_be(coreFix_memExe_stb$search_be),
|
|
.search_paddr(coreFix_memExe_stb$search_paddr),
|
|
.EN_enq(coreFix_memExe_stb$EN_enq),
|
|
.EN_deq(coreFix_memExe_stb$EN_deq),
|
|
.EN_issue(coreFix_memExe_stb$EN_issue),
|
|
.isEmpty(coreFix_memExe_stb$isEmpty),
|
|
.RDY_isEmpty(),
|
|
.getEnqIndex(coreFix_memExe_stb$getEnqIndex),
|
|
.RDY_getEnqIndex(),
|
|
.RDY_enq(coreFix_memExe_stb$RDY_enq),
|
|
.deq(coreFix_memExe_stb$deq),
|
|
.RDY_deq(coreFix_memExe_stb$RDY_deq),
|
|
.issue(coreFix_memExe_stb$issue),
|
|
.RDY_issue(coreFix_memExe_stb$RDY_issue),
|
|
.search(coreFix_memExe_stb$search),
|
|
.RDY_search(),
|
|
.noMatchLdQ(coreFix_memExe_stb$noMatchLdQ),
|
|
.RDY_noMatchLdQ(),
|
|
.noMatchStQ(coreFix_memExe_stb$noMatchStQ),
|
|
.RDY_noMatchStQ());
|
|
|
|
// submodule coreFix_trainBPQ_0
|
|
FIFO2 #(.width(32'd159), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(coreFix_trainBPQ_0$D_IN),
|
|
.ENQ(coreFix_trainBPQ_0$ENQ),
|
|
.DEQ(coreFix_trainBPQ_0$DEQ),
|
|
.CLR(coreFix_trainBPQ_0$CLR),
|
|
.D_OUT(coreFix_trainBPQ_0$D_OUT),
|
|
.FULL_N(coreFix_trainBPQ_0$FULL_N),
|
|
.EMPTY_N(coreFix_trainBPQ_0$EMPTY_N));
|
|
|
|
// submodule coreFix_trainBPQ_1
|
|
FIFO2 #(.width(32'd159), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(coreFix_trainBPQ_1$D_IN),
|
|
.ENQ(coreFix_trainBPQ_1$ENQ),
|
|
.DEQ(coreFix_trainBPQ_1$DEQ),
|
|
.CLR(coreFix_trainBPQ_1$CLR),
|
|
.D_OUT(coreFix_trainBPQ_1$D_OUT),
|
|
.FULL_N(coreFix_trainBPQ_1$FULL_N),
|
|
.EMPTY_N(coreFix_trainBPQ_1$EMPTY_N));
|
|
|
|
// submodule csrInstOrInterruptInflight_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK),
|
|
.D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN),
|
|
.EN(csrInstOrInterruptInflight_dummy2_0$EN),
|
|
.Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT));
|
|
|
|
// submodule csrInstOrInterruptInflight_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK),
|
|
.D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN),
|
|
.EN(csrInstOrInterruptInflight_dummy2_1$EN),
|
|
.Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT));
|
|
|
|
// submodule csrf_mcycle_ehr_data_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK),
|
|
.D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN),
|
|
.EN(csrf_mcycle_ehr_data_dummy2_0$EN),
|
|
.Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT));
|
|
|
|
// submodule csrf_mcycle_ehr_data_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK),
|
|
.D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN),
|
|
.EN(csrf_mcycle_ehr_data_dummy2_1$EN),
|
|
.Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT));
|
|
|
|
// submodule csrf_minstret_ehr_data_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK),
|
|
.D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN),
|
|
.EN(csrf_minstret_ehr_data_dummy2_0$EN),
|
|
.Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT));
|
|
|
|
// submodule csrf_minstret_ehr_data_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK),
|
|
.D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN),
|
|
.EN(csrf_minstret_ehr_data_dummy2_1$EN),
|
|
.Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT));
|
|
|
|
// submodule csrf_stats_module_writeQ
|
|
FIFO1 #(.width(32'd1),
|
|
.guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(csrf_stats_module_writeQ$D_IN),
|
|
.ENQ(csrf_stats_module_writeQ$ENQ),
|
|
.DEQ(csrf_stats_module_writeQ$DEQ),
|
|
.CLR(csrf_stats_module_writeQ$CLR),
|
|
.D_OUT(csrf_stats_module_writeQ$D_OUT),
|
|
.FULL_N(csrf_stats_module_writeQ$FULL_N),
|
|
.EMPTY_N(csrf_stats_module_writeQ$EMPTY_N));
|
|
|
|
// submodule csrf_terminate_module_terminateQ
|
|
FIFO10 #(.guarded(32'd1)) csrf_terminate_module_terminateQ(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.ENQ(csrf_terminate_module_terminateQ$ENQ),
|
|
.DEQ(csrf_terminate_module_terminateQ$DEQ),
|
|
.CLR(csrf_terminate_module_terminateQ$CLR),
|
|
.FULL_N(csrf_terminate_module_terminateQ$FULL_N),
|
|
.EMPTY_N(csrf_terminate_module_terminateQ$EMPTY_N));
|
|
|
|
// submodule epochManager
|
|
mkEpochManager epochManager(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.checkEpoch_0_check_e(epochManager$checkEpoch_0_check_e),
|
|
.checkEpoch_1_check_e(epochManager$checkEpoch_1_check_e),
|
|
.updatePrevEpoch_0_update_e(epochManager$updatePrevEpoch_0_update_e),
|
|
.updatePrevEpoch_1_update_e(epochManager$updatePrevEpoch_1_update_e),
|
|
.EN_updatePrevEpoch_0_update(epochManager$EN_updatePrevEpoch_0_update),
|
|
.EN_updatePrevEpoch_1_update(epochManager$EN_updatePrevEpoch_1_update),
|
|
.EN_incrementEpoch(epochManager$EN_incrementEpoch),
|
|
.checkEpoch_0_check(epochManager$checkEpoch_0_check),
|
|
.RDY_checkEpoch_0_check(),
|
|
.checkEpoch_1_check(epochManager$checkEpoch_1_check),
|
|
.RDY_checkEpoch_1_check(),
|
|
.RDY_updatePrevEpoch_0_update(),
|
|
.RDY_updatePrevEpoch_1_update(),
|
|
.getEpoch(),
|
|
.RDY_getEpoch(),
|
|
.RDY_incrementEpoch(epochManager$RDY_incrementEpoch),
|
|
.getEpochState(),
|
|
.RDY_getEpochState(),
|
|
.isFull_ehrPort0(),
|
|
.RDY_isFull_ehrPort0());
|
|
|
|
// submodule fetchStage
|
|
mkFetchStage fetchStage(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.iMemIfc_perf_req_r(fetchStage$iMemIfc_perf_req_r),
|
|
.iMemIfc_perf_setStatus_doStats(fetchStage$iMemIfc_perf_setStatus_doStats),
|
|
.iMemIfc_to_parent_fromP_enq_x(fetchStage$iMemIfc_to_parent_fromP_enq_x),
|
|
.iMemIfc_to_proc_request_put(fetchStage$iMemIfc_to_proc_request_put),
|
|
.iTlbIfc_perf_req_r(fetchStage$iTlbIfc_perf_req_r),
|
|
.iTlbIfc_perf_setStatus_doStats(fetchStage$iTlbIfc_perf_setStatus_doStats),
|
|
.iTlbIfc_toParent_rsFromP_enq_x(fetchStage$iTlbIfc_toParent_rsFromP_enq_x),
|
|
.iTlbIfc_to_proc_request_put(fetchStage$iTlbIfc_to_proc_request_put),
|
|
.iTlbIfc_updateVMInfo_vm(fetchStage$iTlbIfc_updateVMInfo_vm),
|
|
.mmioIfc_instResp_enq_x(fetchStage$mmioIfc_instResp_enq_x),
|
|
.mmioIfc_setHtifAddrs_fromHost(fetchStage$mmioIfc_setHtifAddrs_fromHost),
|
|
.mmioIfc_setHtifAddrs_toHost(fetchStage$mmioIfc_setHtifAddrs_toHost),
|
|
.perf_req_r(fetchStage$perf_req_r),
|
|
.perf_setStatus_doStats(fetchStage$perf_setStatus_doStats),
|
|
.redirect_pc(fetchStage$redirect_pc),
|
|
.start_pc(fetchStage$start_pc),
|
|
.train_predictors_dpTrain(fetchStage$train_predictors_dpTrain),
|
|
.train_predictors_iType(fetchStage$train_predictors_iType),
|
|
.train_predictors_mispred(fetchStage$train_predictors_mispred),
|
|
.train_predictors_next_pc(fetchStage$train_predictors_next_pc),
|
|
.train_predictors_pc(fetchStage$train_predictors_pc),
|
|
.train_predictors_taken(fetchStage$train_predictors_taken),
|
|
.EN_pipelines_0_deq(fetchStage$EN_pipelines_0_deq),
|
|
.EN_pipelines_1_deq(fetchStage$EN_pipelines_1_deq),
|
|
.EN_iTlbIfc_flush(fetchStage$EN_iTlbIfc_flush),
|
|
.EN_iTlbIfc_updateVMInfo(fetchStage$EN_iTlbIfc_updateVMInfo),
|
|
.EN_iTlbIfc_to_proc_request_put(fetchStage$EN_iTlbIfc_to_proc_request_put),
|
|
.EN_iTlbIfc_to_proc_response_get(fetchStage$EN_iTlbIfc_to_proc_response_get),
|
|
.EN_iTlbIfc_toParent_rqToP_deq(fetchStage$EN_iTlbIfc_toParent_rqToP_deq),
|
|
.EN_iTlbIfc_toParent_rsFromP_enq(fetchStage$EN_iTlbIfc_toParent_rsFromP_enq),
|
|
.EN_iTlbIfc_toParent_flush_request_get(fetchStage$EN_iTlbIfc_toParent_flush_request_get),
|
|
.EN_iTlbIfc_toParent_flush_response_put(fetchStage$EN_iTlbIfc_toParent_flush_response_put),
|
|
.EN_iTlbIfc_perf_setStatus(fetchStage$EN_iTlbIfc_perf_setStatus),
|
|
.EN_iTlbIfc_perf_req(fetchStage$EN_iTlbIfc_perf_req),
|
|
.EN_iTlbIfc_perf_resp(fetchStage$EN_iTlbIfc_perf_resp),
|
|
.EN_iMemIfc_to_proc_request_put(fetchStage$EN_iMemIfc_to_proc_request_put),
|
|
.EN_iMemIfc_to_proc_response_get(fetchStage$EN_iMemIfc_to_proc_response_get),
|
|
.EN_iMemIfc_flush(fetchStage$EN_iMemIfc_flush),
|
|
.EN_iMemIfc_perf_setStatus(fetchStage$EN_iMemIfc_perf_setStatus),
|
|
.EN_iMemIfc_perf_req(fetchStage$EN_iMemIfc_perf_req),
|
|
.EN_iMemIfc_perf_resp(fetchStage$EN_iMemIfc_perf_resp),
|
|
.EN_iMemIfc_to_parent_rsToP_deq(fetchStage$EN_iMemIfc_to_parent_rsToP_deq),
|
|
.EN_iMemIfc_to_parent_rqToP_deq(fetchStage$EN_iMemIfc_to_parent_rqToP_deq),
|
|
.EN_iMemIfc_to_parent_fromP_enq(fetchStage$EN_iMemIfc_to_parent_fromP_enq),
|
|
.EN_iMemIfc_cRqStuck_get(fetchStage$EN_iMemIfc_cRqStuck_get),
|
|
.EN_iMemIfc_pRqStuck_get(fetchStage$EN_iMemIfc_pRqStuck_get),
|
|
.EN_mmioIfc_instReq_deq(fetchStage$EN_mmioIfc_instReq_deq),
|
|
.EN_mmioIfc_instResp_enq(fetchStage$EN_mmioIfc_instResp_enq),
|
|
.EN_mmioIfc_setHtifAddrs(fetchStage$EN_mmioIfc_setHtifAddrs),
|
|
.EN_start(fetchStage$EN_start),
|
|
.EN_stop(fetchStage$EN_stop),
|
|
.EN_setWaitRedirect(fetchStage$EN_setWaitRedirect),
|
|
.EN_redirect(fetchStage$EN_redirect),
|
|
.EN_done_flushing(fetchStage$EN_done_flushing),
|
|
.EN_train_predictors(fetchStage$EN_train_predictors),
|
|
.EN_flush_predictors(fetchStage$EN_flush_predictors),
|
|
.EN_perf_setStatus(fetchStage$EN_perf_setStatus),
|
|
.EN_perf_req(fetchStage$EN_perf_req),
|
|
.EN_perf_resp(fetchStage$EN_perf_resp),
|
|
.pipelines_0_canDeq(fetchStage$pipelines_0_canDeq),
|
|
.RDY_pipelines_0_canDeq(),
|
|
.RDY_pipelines_0_deq(fetchStage$RDY_pipelines_0_deq),
|
|
.pipelines_0_first(fetchStage$pipelines_0_first),
|
|
.RDY_pipelines_0_first(fetchStage$RDY_pipelines_0_first),
|
|
.pipelines_1_canDeq(fetchStage$pipelines_1_canDeq),
|
|
.RDY_pipelines_1_canDeq(),
|
|
.RDY_pipelines_1_deq(fetchStage$RDY_pipelines_1_deq),
|
|
.pipelines_1_first(fetchStage$pipelines_1_first),
|
|
.RDY_pipelines_1_first(fetchStage$RDY_pipelines_1_first),
|
|
.iTlbIfc_flush_done(fetchStage$iTlbIfc_flush_done),
|
|
.RDY_iTlbIfc_flush_done(),
|
|
.RDY_iTlbIfc_flush(fetchStage$RDY_iTlbIfc_flush),
|
|
.RDY_iTlbIfc_updateVMInfo(),
|
|
.iTlbIfc_noPendingReq(fetchStage$iTlbIfc_noPendingReq),
|
|
.RDY_iTlbIfc_noPendingReq(),
|
|
.RDY_iTlbIfc_to_proc_request_put(),
|
|
.iTlbIfc_to_proc_response_get(),
|
|
.RDY_iTlbIfc_to_proc_response_get(),
|
|
.iTlbIfc_toParent_rqToP_notEmpty(),
|
|
.RDY_iTlbIfc_toParent_rqToP_notEmpty(),
|
|
.RDY_iTlbIfc_toParent_rqToP_deq(fetchStage$RDY_iTlbIfc_toParent_rqToP_deq),
|
|
.iTlbIfc_toParent_rqToP_first(fetchStage$iTlbIfc_toParent_rqToP_first),
|
|
.RDY_iTlbIfc_toParent_rqToP_first(fetchStage$RDY_iTlbIfc_toParent_rqToP_first),
|
|
.iTlbIfc_toParent_rsFromP_notFull(),
|
|
.RDY_iTlbIfc_toParent_rsFromP_notFull(),
|
|
.RDY_iTlbIfc_toParent_rsFromP_enq(fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq),
|
|
.RDY_iTlbIfc_toParent_flush_request_get(fetchStage$RDY_iTlbIfc_toParent_flush_request_get),
|
|
.RDY_iTlbIfc_toParent_flush_response_put(fetchStage$RDY_iTlbIfc_toParent_flush_response_put),
|
|
.RDY_iTlbIfc_perf_setStatus(),
|
|
.RDY_iTlbIfc_perf_req(),
|
|
.iTlbIfc_perf_resp(),
|
|
.RDY_iTlbIfc_perf_resp(),
|
|
.iTlbIfc_perf_respValid(),
|
|
.RDY_iTlbIfc_perf_respValid(),
|
|
.RDY_iMemIfc_to_proc_request_put(),
|
|
.iMemIfc_to_proc_response_get(),
|
|
.RDY_iMemIfc_to_proc_response_get(),
|
|
.RDY_iMemIfc_flush(),
|
|
.iMemIfc_flush_done(),
|
|
.RDY_iMemIfc_flush_done(),
|
|
.RDY_iMemIfc_perf_setStatus(),
|
|
.RDY_iMemIfc_perf_req(),
|
|
.iMemIfc_perf_resp(),
|
|
.RDY_iMemIfc_perf_resp(),
|
|
.iMemIfc_perf_respValid(),
|
|
.RDY_iMemIfc_perf_respValid(),
|
|
.iMemIfc_to_parent_rsToP_notEmpty(fetchStage$iMemIfc_to_parent_rsToP_notEmpty),
|
|
.RDY_iMemIfc_to_parent_rsToP_notEmpty(),
|
|
.RDY_iMemIfc_to_parent_rsToP_deq(fetchStage$RDY_iMemIfc_to_parent_rsToP_deq),
|
|
.iMemIfc_to_parent_rsToP_first(fetchStage$iMemIfc_to_parent_rsToP_first),
|
|
.RDY_iMemIfc_to_parent_rsToP_first(fetchStage$RDY_iMemIfc_to_parent_rsToP_first),
|
|
.iMemIfc_to_parent_rqToP_notEmpty(fetchStage$iMemIfc_to_parent_rqToP_notEmpty),
|
|
.RDY_iMemIfc_to_parent_rqToP_notEmpty(),
|
|
.RDY_iMemIfc_to_parent_rqToP_deq(fetchStage$RDY_iMemIfc_to_parent_rqToP_deq),
|
|
.iMemIfc_to_parent_rqToP_first(fetchStage$iMemIfc_to_parent_rqToP_first),
|
|
.RDY_iMemIfc_to_parent_rqToP_first(fetchStage$RDY_iMemIfc_to_parent_rqToP_first),
|
|
.iMemIfc_to_parent_fromP_notFull(fetchStage$iMemIfc_to_parent_fromP_notFull),
|
|
.RDY_iMemIfc_to_parent_fromP_notFull(),
|
|
.RDY_iMemIfc_to_parent_fromP_enq(fetchStage$RDY_iMemIfc_to_parent_fromP_enq),
|
|
.iMemIfc_cRqStuck_get(fetchStage$iMemIfc_cRqStuck_get),
|
|
.RDY_iMemIfc_cRqStuck_get(fetchStage$RDY_iMemIfc_cRqStuck_get),
|
|
.iMemIfc_pRqStuck_get(fetchStage$iMemIfc_pRqStuck_get),
|
|
.RDY_iMemIfc_pRqStuck_get(fetchStage$RDY_iMemIfc_pRqStuck_get),
|
|
.mmioIfc_instReq_notEmpty(),
|
|
.RDY_mmioIfc_instReq_notEmpty(),
|
|
.RDY_mmioIfc_instReq_deq(fetchStage$RDY_mmioIfc_instReq_deq),
|
|
.mmioIfc_instReq_first_fst(fetchStage$mmioIfc_instReq_first_fst),
|
|
.RDY_mmioIfc_instReq_first_fst(fetchStage$RDY_mmioIfc_instReq_first_fst),
|
|
.mmioIfc_instReq_first_snd(fetchStage$mmioIfc_instReq_first_snd),
|
|
.RDY_mmioIfc_instReq_first_snd(fetchStage$RDY_mmioIfc_instReq_first_snd),
|
|
.mmioIfc_instResp_notFull(),
|
|
.RDY_mmioIfc_instResp_notFull(),
|
|
.RDY_mmioIfc_instResp_enq(fetchStage$RDY_mmioIfc_instResp_enq),
|
|
.RDY_mmioIfc_setHtifAddrs(),
|
|
.RDY_start(),
|
|
.RDY_stop(),
|
|
.RDY_setWaitRedirect(),
|
|
.RDY_redirect(),
|
|
.RDY_done_flushing(fetchStage$RDY_done_flushing),
|
|
.RDY_train_predictors(),
|
|
.emptyForFlush(),
|
|
.RDY_emptyForFlush(),
|
|
.RDY_flush_predictors(),
|
|
.flush_predictors_done(),
|
|
.RDY_flush_predictors_done(),
|
|
.getFetchState(),
|
|
.RDY_getFetchState(),
|
|
.RDY_perf_setStatus(),
|
|
.RDY_perf_req(),
|
|
.perf_resp(),
|
|
.RDY_perf_resp(),
|
|
.perf_respValid(),
|
|
.RDY_perf_respValid());
|
|
|
|
// submodule l2Tlb
|
|
mkL2Tlb l2Tlb(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.perf_req_r(l2Tlb$perf_req_r),
|
|
.perf_setStatus_doStats(l2Tlb$perf_setStatus_doStats),
|
|
.toChildren_rqFromC_put(l2Tlb$toChildren_rqFromC_put),
|
|
.toMem_respLd_enq_x(l2Tlb$toMem_respLd_enq_x),
|
|
.updateVMInfo_vmD(l2Tlb$updateVMInfo_vmD),
|
|
.updateVMInfo_vmI(l2Tlb$updateVMInfo_vmI),
|
|
.EN_updateVMInfo(l2Tlb$EN_updateVMInfo),
|
|
.EN_toChildren_rqFromC_put(l2Tlb$EN_toChildren_rqFromC_put),
|
|
.EN_toChildren_rsToC_deq(l2Tlb$EN_toChildren_rsToC_deq),
|
|
.EN_toChildren_iTlbReqFlush_put(l2Tlb$EN_toChildren_iTlbReqFlush_put),
|
|
.EN_toChildren_dTlbReqFlush_put(l2Tlb$EN_toChildren_dTlbReqFlush_put),
|
|
.EN_toChildren_flushDone_get(l2Tlb$EN_toChildren_flushDone_get),
|
|
.EN_toMem_memReq_deq(l2Tlb$EN_toMem_memReq_deq),
|
|
.EN_toMem_respLd_enq(l2Tlb$EN_toMem_respLd_enq),
|
|
.EN_perf_setStatus(l2Tlb$EN_perf_setStatus),
|
|
.EN_perf_req(l2Tlb$EN_perf_req),
|
|
.EN_perf_resp(l2Tlb$EN_perf_resp),
|
|
.RDY_updateVMInfo(),
|
|
.RDY_toChildren_rqFromC_put(l2Tlb$RDY_toChildren_rqFromC_put),
|
|
.toChildren_rsToC_notEmpty(),
|
|
.RDY_toChildren_rsToC_notEmpty(),
|
|
.RDY_toChildren_rsToC_deq(l2Tlb$RDY_toChildren_rsToC_deq),
|
|
.toChildren_rsToC_first(l2Tlb$toChildren_rsToC_first),
|
|
.RDY_toChildren_rsToC_first(l2Tlb$RDY_toChildren_rsToC_first),
|
|
.RDY_toChildren_iTlbReqFlush_put(l2Tlb$RDY_toChildren_iTlbReqFlush_put),
|
|
.RDY_toChildren_dTlbReqFlush_put(l2Tlb$RDY_toChildren_dTlbReqFlush_put),
|
|
.RDY_toChildren_flushDone_get(l2Tlb$RDY_toChildren_flushDone_get),
|
|
.toMem_memReq_notEmpty(l2Tlb$toMem_memReq_notEmpty),
|
|
.RDY_toMem_memReq_notEmpty(),
|
|
.RDY_toMem_memReq_deq(l2Tlb$RDY_toMem_memReq_deq),
|
|
.toMem_memReq_first(l2Tlb$toMem_memReq_first),
|
|
.RDY_toMem_memReq_first(l2Tlb$RDY_toMem_memReq_first),
|
|
.toMem_respLd_notFull(l2Tlb$toMem_respLd_notFull),
|
|
.RDY_toMem_respLd_notFull(),
|
|
.RDY_toMem_respLd_enq(l2Tlb$RDY_toMem_respLd_enq),
|
|
.RDY_perf_setStatus(),
|
|
.RDY_perf_req(),
|
|
.perf_resp(),
|
|
.RDY_perf_resp(),
|
|
.perf_respValid(),
|
|
.RDY_perf_respValid());
|
|
|
|
// submodule mmio_cRqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(mmio_cRqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(mmio_cRqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule mmio_cRqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(mmio_cRqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(mmio_cRqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(mmio_cRqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_cRqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(mmio_cRqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(mmio_cRqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(mmio_cRqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_cRsQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN),
|
|
.EN(mmio_cRsQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRsQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN),
|
|
.EN(mmio_cRsQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule mmio_cRsQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN),
|
|
.EN(mmio_cRsQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRsQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN),
|
|
.EN(mmio_cRsQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRsQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN),
|
|
.EN(mmio_cRsQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_cRsQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN),
|
|
.EN(mmio_cRsQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRsQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN),
|
|
.EN(mmio_cRsQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_cRsQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN),
|
|
.EN(mmio_cRsQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_dataPendQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN),
|
|
.EN(mmio_dataPendQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataPendQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN),
|
|
.EN(mmio_dataPendQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule mmio_dataPendQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN),
|
|
.EN(mmio_dataPendQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataPendQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN),
|
|
.EN(mmio_dataPendQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataPendQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN),
|
|
.EN(mmio_dataPendQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_dataPendQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN),
|
|
.EN(mmio_dataPendQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataPendQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN),
|
|
.EN(mmio_dataPendQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataPendQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN),
|
|
.EN(mmio_dataPendQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_dataReqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(mmio_dataReqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataReqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(mmio_dataReqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule mmio_dataReqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(mmio_dataReqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataReqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(mmio_dataReqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataReqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(mmio_dataReqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_dataReqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(mmio_dataReqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataReqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(mmio_dataReqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule mmio_dataReqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1),
|
|
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(mmio_dataReqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule mmio_dataRespQ_clearReq_dummy2_0
|
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN),
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.EN(mmio_dataRespQ_clearReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_dataRespQ_clearReq_dummy2_1
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN),
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.EN(mmio_dataRespQ_clearReq_dummy2_1$EN),
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.Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT));
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// submodule mmio_dataRespQ_deqReq_dummy2_0
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN),
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.EN(mmio_dataRespQ_deqReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_dataRespQ_deqReq_dummy2_1
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN),
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.EN(mmio_dataRespQ_deqReq_dummy2_1$EN),
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.Q_OUT());
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// submodule mmio_dataRespQ_deqReq_dummy2_2
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK),
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.D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN),
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.EN(mmio_dataRespQ_deqReq_dummy2_2$EN),
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.Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT));
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// submodule mmio_dataRespQ_enqReq_dummy2_0
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN),
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.EN(mmio_dataRespQ_enqReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_dataRespQ_enqReq_dummy2_1
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN),
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.EN(mmio_dataRespQ_enqReq_dummy2_1$EN),
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.Q_OUT());
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// submodule mmio_dataRespQ_enqReq_dummy2_2
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK),
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.D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN),
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.EN(mmio_dataRespQ_enqReq_dummy2_2$EN),
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.Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT));
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// submodule mmio_pRqQ_clearReq_dummy2_0
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN),
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.EN(mmio_pRqQ_clearReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_pRqQ_clearReq_dummy2_1
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN),
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.EN(mmio_pRqQ_clearReq_dummy2_1$EN),
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.Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT));
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// submodule mmio_pRqQ_deqReq_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN),
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.EN(mmio_pRqQ_deqReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_pRqQ_deqReq_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN),
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.EN(mmio_pRqQ_deqReq_dummy2_1$EN),
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.Q_OUT());
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// submodule mmio_pRqQ_deqReq_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK),
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.D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN),
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.EN(mmio_pRqQ_deqReq_dummy2_2$EN),
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.Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT));
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// submodule mmio_pRqQ_enqReq_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN),
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.EN(mmio_pRqQ_enqReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_pRqQ_enqReq_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN),
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.EN(mmio_pRqQ_enqReq_dummy2_1$EN),
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.Q_OUT());
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// submodule mmio_pRqQ_enqReq_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK),
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.D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN),
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.EN(mmio_pRqQ_enqReq_dummy2_2$EN),
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.Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT));
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// submodule mmio_pRsQ_clearReq_dummy2_0
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN),
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.EN(mmio_pRsQ_clearReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_pRsQ_clearReq_dummy2_1
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RevertReg #(.width(32'd1),
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.init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN),
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.EN(mmio_pRsQ_clearReq_dummy2_1$EN),
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.Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT));
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// submodule mmio_pRsQ_deqReq_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN),
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.EN(mmio_pRsQ_deqReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_pRsQ_deqReq_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN),
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.EN(mmio_pRsQ_deqReq_dummy2_1$EN),
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.Q_OUT());
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// submodule mmio_pRsQ_deqReq_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK),
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.D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN),
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.EN(mmio_pRsQ_deqReq_dummy2_2$EN),
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.Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT));
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// submodule mmio_pRsQ_enqReq_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK),
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.D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN),
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.EN(mmio_pRsQ_enqReq_dummy2_0$EN),
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.Q_OUT());
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// submodule mmio_pRsQ_enqReq_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK),
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.D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN),
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.EN(mmio_pRsQ_enqReq_dummy2_1$EN),
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.Q_OUT());
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// submodule mmio_pRsQ_enqReq_dummy2_2
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RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK),
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.D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN),
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.EN(mmio_pRsQ_enqReq_dummy2_2$EN),
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.Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT));
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// submodule perfReqQ
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FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N),
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.CLK(CLK),
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.D_IN(perfReqQ$D_IN),
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.ENQ(perfReqQ$ENQ),
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.DEQ(perfReqQ$DEQ),
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.CLR(perfReqQ$CLR),
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.D_OUT(perfReqQ$D_OUT),
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.FULL_N(perfReqQ$FULL_N),
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.EMPTY_N(perfReqQ$EMPTY_N));
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// submodule regRenamingTable
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mkRegRenamingTable regRenamingTable(.CLK(CLK),
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.RST_N(RST_N),
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.rename_0_claimRename_r(regRenamingTable$rename_0_claimRename_r),
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.rename_0_claimRename_sb(regRenamingTable$rename_0_claimRename_sb),
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.rename_0_getRename_r(regRenamingTable$rename_0_getRename_r),
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.rename_1_claimRename_r(regRenamingTable$rename_1_claimRename_r),
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.rename_1_claimRename_sb(regRenamingTable$rename_1_claimRename_sb),
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.rename_1_getRename_r(regRenamingTable$rename_1_getRename_r),
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.specUpdate_correctSpeculation_mask(regRenamingTable$specUpdate_correctSpeculation_mask),
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.specUpdate_incorrectSpeculation_kill_all(regRenamingTable$specUpdate_incorrectSpeculation_kill_all),
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.specUpdate_incorrectSpeculation_kill_tag(regRenamingTable$specUpdate_incorrectSpeculation_kill_tag),
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.EN_rename_0_claimRename(regRenamingTable$EN_rename_0_claimRename),
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.EN_rename_1_claimRename(regRenamingTable$EN_rename_1_claimRename),
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.EN_commit_0_commit(regRenamingTable$EN_commit_0_commit),
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.EN_commit_1_commit(regRenamingTable$EN_commit_1_commit),
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.EN_specUpdate_incorrectSpeculation(regRenamingTable$EN_specUpdate_incorrectSpeculation),
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.EN_specUpdate_correctSpeculation(regRenamingTable$EN_specUpdate_correctSpeculation),
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.rename_0_getRename(regRenamingTable$rename_0_getRename),
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.RDY_rename_0_getRename(regRenamingTable$RDY_rename_0_getRename),
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.RDY_rename_0_claimRename(regRenamingTable$RDY_rename_0_claimRename),
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.rename_0_canRename(regRenamingTable$rename_0_canRename),
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.RDY_rename_0_canRename(),
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.rename_1_getRename(regRenamingTable$rename_1_getRename),
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.RDY_rename_1_getRename(regRenamingTable$RDY_rename_1_getRename),
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.RDY_rename_1_claimRename(regRenamingTable$RDY_rename_1_claimRename),
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.rename_1_canRename(regRenamingTable$rename_1_canRename),
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.RDY_rename_1_canRename(),
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.RDY_commit_0_commit(regRenamingTable$RDY_commit_0_commit),
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.commit_0_canCommit(),
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.RDY_commit_0_canCommit(),
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.RDY_commit_1_commit(regRenamingTable$RDY_commit_1_commit),
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.commit_1_canCommit(),
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.RDY_commit_1_canCommit(),
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.RDY_specUpdate_incorrectSpeculation(),
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.RDY_specUpdate_correctSpeculation());
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// submodule rf
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mkRFileSynth rf(.CLK(CLK),
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.RST_N(RST_N),
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.read_0_rd1_rindx(rf$read_0_rd1_rindx),
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.read_0_rd2_rindx(rf$read_0_rd2_rindx),
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.read_0_rd3_rindx(rf$read_0_rd3_rindx),
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.read_1_rd1_rindx(rf$read_1_rd1_rindx),
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.read_1_rd2_rindx(rf$read_1_rd2_rindx),
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.read_1_rd3_rindx(rf$read_1_rd3_rindx),
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.read_2_rd1_rindx(rf$read_2_rd1_rindx),
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.read_2_rd2_rindx(rf$read_2_rd2_rindx),
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.read_2_rd3_rindx(rf$read_2_rd3_rindx),
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.read_3_rd1_rindx(rf$read_3_rd1_rindx),
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.read_3_rd2_rindx(rf$read_3_rd2_rindx),
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.read_3_rd3_rindx(rf$read_3_rd3_rindx),
|
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.write_0_wr_data(rf$write_0_wr_data),
|
|
.write_0_wr_rindx(rf$write_0_wr_rindx),
|
|
.write_1_wr_data(rf$write_1_wr_data),
|
|
.write_1_wr_rindx(rf$write_1_wr_rindx),
|
|
.write_2_wr_data(rf$write_2_wr_data),
|
|
.write_2_wr_rindx(rf$write_2_wr_rindx),
|
|
.write_3_wr_data(rf$write_3_wr_data),
|
|
.write_3_wr_rindx(rf$write_3_wr_rindx),
|
|
.EN_write_0_wr(rf$EN_write_0_wr),
|
|
.EN_write_1_wr(rf$EN_write_1_wr),
|
|
.EN_write_2_wr(rf$EN_write_2_wr),
|
|
.EN_write_3_wr(rf$EN_write_3_wr),
|
|
.RDY_write_0_wr(),
|
|
.RDY_write_1_wr(),
|
|
.RDY_write_2_wr(),
|
|
.RDY_write_3_wr(),
|
|
.read_0_rd1(rf$read_0_rd1),
|
|
.RDY_read_0_rd1(),
|
|
.read_0_rd2(rf$read_0_rd2),
|
|
.RDY_read_0_rd2(),
|
|
.read_0_rd3(),
|
|
.RDY_read_0_rd3(),
|
|
.read_1_rd1(rf$read_1_rd1),
|
|
.RDY_read_1_rd1(),
|
|
.read_1_rd2(rf$read_1_rd2),
|
|
.RDY_read_1_rd2(),
|
|
.read_1_rd3(),
|
|
.RDY_read_1_rd3(),
|
|
.read_2_rd1(rf$read_2_rd1),
|
|
.RDY_read_2_rd1(),
|
|
.read_2_rd2(rf$read_2_rd2),
|
|
.RDY_read_2_rd2(),
|
|
.read_2_rd3(rf$read_2_rd3),
|
|
.RDY_read_2_rd3(),
|
|
.read_3_rd1(rf$read_3_rd1),
|
|
.RDY_read_3_rd1(),
|
|
.read_3_rd2(rf$read_3_rd2),
|
|
.RDY_read_3_rd2(),
|
|
.read_3_rd3(),
|
|
.RDY_read_3_rd3());
|
|
|
|
// submodule rob
|
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mkReorderBufferSynth rob(.CLK(CLK),
|
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.RST_N(RST_N),
|
|
.enqPort_0_enq_x(rob$enqPort_0_enq_x),
|
|
.enqPort_1_enq_x(rob$enqPort_1_enq_x),
|
|
.getOrigPC_0_get_x(rob$getOrigPC_0_get_x),
|
|
.getOrigPC_1_get_x(rob$getOrigPC_1_get_x),
|
|
.getOrigPC_2_get_x(rob$getOrigPC_2_get_x),
|
|
.getOrigPredPC_0_get_x(rob$getOrigPredPC_0_get_x),
|
|
.getOrigPredPC_1_get_x(rob$getOrigPredPC_1_get_x),
|
|
.setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause),
|
|
.setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed),
|
|
.setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x),
|
|
.setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf),
|
|
.setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData),
|
|
.setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x),
|
|
.setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf),
|
|
.setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData),
|
|
.setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x),
|
|
.setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags),
|
|
.setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x),
|
|
.setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit),
|
|
.setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done),
|
|
.setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr),
|
|
.setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x),
|
|
.setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x),
|
|
.specUpdate_correctSpeculation_mask(rob$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_inst_tag(rob$specUpdate_incorrectSpeculation_inst_tag),
|
|
.specUpdate_incorrectSpeculation_kill_all(rob$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_spec_tag(rob$specUpdate_incorrectSpeculation_spec_tag),
|
|
.EN_enqPort_0_enq(rob$EN_enqPort_0_enq),
|
|
.EN_enqPort_1_enq(rob$EN_enqPort_1_enq),
|
|
.EN_deqPort_0_deq(rob$EN_deqPort_0_deq),
|
|
.EN_deqPort_1_deq(rob$EN_deqPort_1_deq),
|
|
.EN_setLSQAtCommitNotified(rob$EN_setLSQAtCommitNotified),
|
|
.EN_setExecuted_deqLSQ(rob$EN_setExecuted_deqLSQ),
|
|
.EN_setExecuted_doFinishAlu_0_set(rob$EN_setExecuted_doFinishAlu_0_set),
|
|
.EN_setExecuted_doFinishAlu_1_set(rob$EN_setExecuted_doFinishAlu_1_set),
|
|
.EN_setExecuted_doFinishFpuMulDiv_0_set(rob$EN_setExecuted_doFinishFpuMulDiv_0_set),
|
|
.EN_setExecuted_doFinishMem(rob$EN_setExecuted_doFinishMem),
|
|
.EN_specUpdate_incorrectSpeculation(rob$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(rob$EN_specUpdate_correctSpeculation),
|
|
.enqPort_0_canEnq(rob$enqPort_0_canEnq),
|
|
.RDY_enqPort_0_canEnq(),
|
|
.RDY_enqPort_0_enq(rob$RDY_enqPort_0_enq),
|
|
.enqPort_0_getEnqInstTag(rob$enqPort_0_getEnqInstTag),
|
|
.RDY_enqPort_0_getEnqInstTag(),
|
|
.enqPort_1_canEnq(rob$enqPort_1_canEnq),
|
|
.RDY_enqPort_1_canEnq(),
|
|
.RDY_enqPort_1_enq(rob$RDY_enqPort_1_enq),
|
|
.enqPort_1_getEnqInstTag(rob$enqPort_1_getEnqInstTag),
|
|
.RDY_enqPort_1_getEnqInstTag(),
|
|
.isEmpty(rob$isEmpty),
|
|
.RDY_isEmpty(),
|
|
.deqPort_0_canDeq(rob$deqPort_0_canDeq),
|
|
.RDY_deqPort_0_canDeq(),
|
|
.RDY_deqPort_0_deq(rob$RDY_deqPort_0_deq),
|
|
.deqPort_0_getDeqInstTag(rob$deqPort_0_getDeqInstTag),
|
|
.RDY_deqPort_0_getDeqInstTag(),
|
|
.deqPort_0_deq_data(rob$deqPort_0_deq_data),
|
|
.RDY_deqPort_0_deq_data(rob$RDY_deqPort_0_deq_data),
|
|
.deqPort_1_canDeq(rob$deqPort_1_canDeq),
|
|
.RDY_deqPort_1_canDeq(),
|
|
.RDY_deqPort_1_deq(rob$RDY_deqPort_1_deq),
|
|
.deqPort_1_getDeqInstTag(),
|
|
.RDY_deqPort_1_getDeqInstTag(),
|
|
.deqPort_1_deq_data(rob$deqPort_1_deq_data),
|
|
.RDY_deqPort_1_deq_data(rob$RDY_deqPort_1_deq_data),
|
|
.RDY_setLSQAtCommitNotified(rob$RDY_setLSQAtCommitNotified),
|
|
.RDY_setExecuted_deqLSQ(rob$RDY_setExecuted_deqLSQ),
|
|
.RDY_setExecuted_doFinishAlu_0_set(rob$RDY_setExecuted_doFinishAlu_0_set),
|
|
.RDY_setExecuted_doFinishAlu_1_set(rob$RDY_setExecuted_doFinishAlu_1_set),
|
|
.RDY_setExecuted_doFinishFpuMulDiv_0_set(rob$RDY_setExecuted_doFinishFpuMulDiv_0_set),
|
|
.RDY_setExecuted_doFinishMem(rob$RDY_setExecuted_doFinishMem),
|
|
.getOrigPC_0_get(rob$getOrigPC_0_get),
|
|
.RDY_getOrigPC_0_get(),
|
|
.getOrigPC_1_get(rob$getOrigPC_1_get),
|
|
.RDY_getOrigPC_1_get(),
|
|
.getOrigPC_2_get(),
|
|
.RDY_getOrigPC_2_get(),
|
|
.getOrigPredPC_0_get(rob$getOrigPredPC_0_get),
|
|
.RDY_getOrigPredPC_0_get(),
|
|
.getOrigPredPC_1_get(rob$getOrigPredPC_1_get),
|
|
.RDY_getOrigPredPC_1_get(),
|
|
.getEnqTime(rob$getEnqTime),
|
|
.RDY_getEnqTime(),
|
|
.isEmpty_ehrPort0(),
|
|
.RDY_isEmpty_ehrPort0(),
|
|
.isFull_ehrPort0(),
|
|
.RDY_isFull_ehrPort0(),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation());
|
|
|
|
// submodule sbAggr
|
|
mkScoreboardAggr sbAggr(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.eagerLookup_0_get_r(sbAggr$eagerLookup_0_get_r),
|
|
.eagerLookup_1_get_r(sbAggr$eagerLookup_1_get_r),
|
|
.setBusy_0_set_dst(sbAggr$setBusy_0_set_dst),
|
|
.setBusy_1_set_dst(sbAggr$setBusy_1_set_dst),
|
|
.setReady_0_put(sbAggr$setReady_0_put),
|
|
.setReady_1_put(sbAggr$setReady_1_put),
|
|
.setReady_2_put(sbAggr$setReady_2_put),
|
|
.setReady_3_put(sbAggr$setReady_3_put),
|
|
.setReady_4_put(sbAggr$setReady_4_put),
|
|
.EN_setBusy_0_set(sbAggr$EN_setBusy_0_set),
|
|
.EN_setBusy_1_set(sbAggr$EN_setBusy_1_set),
|
|
.EN_setReady_0_put(sbAggr$EN_setReady_0_put),
|
|
.EN_setReady_1_put(sbAggr$EN_setReady_1_put),
|
|
.EN_setReady_2_put(sbAggr$EN_setReady_2_put),
|
|
.EN_setReady_3_put(sbAggr$EN_setReady_3_put),
|
|
.EN_setReady_4_put(sbAggr$EN_setReady_4_put),
|
|
.eagerLookup_0_get(sbAggr$eagerLookup_0_get),
|
|
.RDY_eagerLookup_0_get(),
|
|
.eagerLookup_1_get(sbAggr$eagerLookup_1_get),
|
|
.RDY_eagerLookup_1_get(),
|
|
.RDY_setBusy_0_set(),
|
|
.RDY_setBusy_1_set(),
|
|
.RDY_setReady_0_put(),
|
|
.RDY_setReady_1_put(),
|
|
.RDY_setReady_2_put(),
|
|
.RDY_setReady_3_put(),
|
|
.RDY_setReady_4_put());
|
|
|
|
// submodule sbCons
|
|
mkScoreboardCons sbCons(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.eagerLookup_0_get_r(sbCons$eagerLookup_0_get_r),
|
|
.eagerLookup_1_get_r(sbCons$eagerLookup_1_get_r),
|
|
.lazyLookup_0_get_r(sbCons$lazyLookup_0_get_r),
|
|
.lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r),
|
|
.lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r),
|
|
.lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r),
|
|
.setBusy_0_set_dst(sbCons$setBusy_0_set_dst),
|
|
.setBusy_1_set_dst(sbCons$setBusy_1_set_dst),
|
|
.setReady_0_put(sbCons$setReady_0_put),
|
|
.setReady_1_put(sbCons$setReady_1_put),
|
|
.setReady_2_put(sbCons$setReady_2_put),
|
|
.setReady_3_put(sbCons$setReady_3_put),
|
|
.EN_setBusy_0_set(sbCons$EN_setBusy_0_set),
|
|
.EN_setBusy_1_set(sbCons$EN_setBusy_1_set),
|
|
.EN_setReady_0_put(sbCons$EN_setReady_0_put),
|
|
.EN_setReady_1_put(sbCons$EN_setReady_1_put),
|
|
.EN_setReady_2_put(sbCons$EN_setReady_2_put),
|
|
.EN_setReady_3_put(sbCons$EN_setReady_3_put),
|
|
.eagerLookup_0_get(),
|
|
.RDY_eagerLookup_0_get(),
|
|
.eagerLookup_1_get(),
|
|
.RDY_eagerLookup_1_get(),
|
|
.RDY_setBusy_0_set(),
|
|
.RDY_setBusy_1_set(),
|
|
.RDY_setReady_0_put(),
|
|
.RDY_setReady_1_put(),
|
|
.RDY_setReady_2_put(),
|
|
.RDY_setReady_3_put(),
|
|
.lazyLookup_0_get(sbCons$lazyLookup_0_get),
|
|
.RDY_lazyLookup_0_get(),
|
|
.lazyLookup_1_get(sbCons$lazyLookup_1_get),
|
|
.RDY_lazyLookup_1_get(),
|
|
.lazyLookup_2_get(sbCons$lazyLookup_2_get),
|
|
.RDY_lazyLookup_2_get(),
|
|
.lazyLookup_3_get(sbCons$lazyLookup_3_get),
|
|
.RDY_lazyLookup_3_get());
|
|
|
|
// submodule specTagManager
|
|
mkSpecTagManager specTagManager(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.specUpdate_correctSpeculation_mask(specTagManager$specUpdate_correctSpeculation_mask),
|
|
.specUpdate_incorrectSpeculation_kill_all(specTagManager$specUpdate_incorrectSpeculation_kill_all),
|
|
.specUpdate_incorrectSpeculation_kill_tag(specTagManager$specUpdate_incorrectSpeculation_kill_tag),
|
|
.EN_claimSpecTag(specTagManager$EN_claimSpecTag),
|
|
.EN_specUpdate_incorrectSpeculation(specTagManager$EN_specUpdate_incorrectSpeculation),
|
|
.EN_specUpdate_correctSpeculation(specTagManager$EN_specUpdate_correctSpeculation),
|
|
.currentSpecBits(specTagManager$currentSpecBits),
|
|
.RDY_currentSpecBits(),
|
|
.nextSpecTag(specTagManager$nextSpecTag),
|
|
.RDY_nextSpecTag(specTagManager$RDY_nextSpecTag),
|
|
.RDY_claimSpecTag(specTagManager$RDY_claimSpecTag),
|
|
.canClaim(specTagManager$canClaim),
|
|
.RDY_canClaim(),
|
|
.RDY_specUpdate_incorrectSpeculation(),
|
|
.RDY_specUpdate_correctSpeculation(),
|
|
.isFull_ehrPort0(),
|
|
.RDY_isFull_ehrPort0());
|
|
|
|
// rule RL_rl_outOfReset
|
|
assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ;
|
|
assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ;
|
|
|
|
// rule RL_sendDTlbReq
|
|
assign CAN_FIRE_RL_sendDTlbReq =
|
|
coreFix_memExe_dTlb$RDY_toParent_rqToP_first &&
|
|
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq &&
|
|
l2Tlb$RDY_toChildren_rqFromC_put ;
|
|
assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ;
|
|
|
|
// rule RL_sendITlbReq
|
|
assign CAN_FIRE_RL_sendITlbReq =
|
|
l2Tlb$RDY_toChildren_rqFromC_put &&
|
|
fetchStage$RDY_iTlbIfc_toParent_rqToP_first &&
|
|
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ;
|
|
assign WILL_FIRE_RL_sendITlbReq =
|
|
CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ;
|
|
|
|
// rule RL_sendRsToDTlb
|
|
assign CAN_FIRE_RL_sendRsToDTlb =
|
|
l2Tlb$RDY_toChildren_rsToC_first &&
|
|
l2Tlb$RDY_toChildren_rsToC_deq &&
|
|
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq &&
|
|
l2Tlb$toChildren_rsToC_first[83] ;
|
|
assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ;
|
|
|
|
// rule RL_sendRsToITlb
|
|
assign CAN_FIRE_RL_sendRsToITlb =
|
|
l2Tlb$RDY_toChildren_rsToC_first &&
|
|
l2Tlb$RDY_toChildren_rsToC_deq &&
|
|
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq &&
|
|
!l2Tlb$toChildren_rsToC_first[83] ;
|
|
assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ;
|
|
|
|
// rule RL_mkConnectionGetPut
|
|
assign CAN_FIRE_RL_mkConnectionGetPut =
|
|
coreFix_memExe_dTlb$RDY_toParent_flush_request_get &&
|
|
l2Tlb$RDY_toChildren_dTlbReqFlush_put ;
|
|
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
|
|
|
|
// rule RL_mkConnectionGetPut_1
|
|
assign CAN_FIRE_RL_mkConnectionGetPut_1 =
|
|
l2Tlb$RDY_toChildren_iTlbReqFlush_put &&
|
|
fetchStage$RDY_iTlbIfc_toParent_flush_request_get ;
|
|
assign WILL_FIRE_RL_mkConnectionGetPut_1 =
|
|
CAN_FIRE_RL_mkConnectionGetPut_1 ;
|
|
|
|
// rule RL_sendFlushDone
|
|
assign CAN_FIRE_RL_sendFlushDone =
|
|
coreFix_memExe_dTlb$RDY_toParent_flush_response_put &&
|
|
l2Tlb$RDY_toChildren_flushDone_get &&
|
|
fetchStage$RDY_iTlbIfc_toParent_flush_response_put ;
|
|
assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ;
|
|
|
|
// rule RL_sendRobEnqTime
|
|
assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ;
|
|
assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ;
|
|
|
|
// rule RL_readyToFetch
|
|
assign CAN_FIRE_RL_readyToFetch =
|
|
fetchStage$RDY_done_flushing && !flush_reservation &&
|
|
!flush_tlbs &&
|
|
!update_vm_info &&
|
|
fetchStage$iTlbIfc_flush_done &&
|
|
coreFix_memExe_dTlb$flush_done ;
|
|
assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ;
|
|
|
|
// rule RL_csrf_minstret_ehr_setRead
|
|
assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
|
|
assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
|
|
|
|
// rule RL_csrf_mcycle_ehr_setRead
|
|
assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
|
|
assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
|
|
|
|
// rule RL_mmio_handlePRq
|
|
assign CAN_FIRE_RL_mmio_handlePRq =
|
|
!mmio_pRqQ_empty && !mmio_cRsQ_full &&
|
|
(!csrInstOrInterruptInflight_dummy2_0$Q_OUT ||
|
|
!csrInstOrInterruptInflight_dummy2_1$Q_OUT ||
|
|
!csrInstOrInterruptInflight_rl) ;
|
|
assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ;
|
|
|
|
// rule RL_mmio_sendDataReq
|
|
assign CAN_FIRE_RL_mmio_sendDataReq =
|
|
!mmio_dataReqQ_empty && !mmio_cRqQ_full ;
|
|
assign WILL_FIRE_RL_mmio_sendDataReq = CAN_FIRE_RL_mmio_sendDataReq ;
|
|
|
|
// rule RL_mmio_sendInstReq
|
|
assign CAN_FIRE_RL_mmio_sendInstReq =
|
|
!mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd &&
|
|
fetchStage$RDY_mmioIfc_instReq_first_fst &&
|
|
fetchStage$RDY_mmioIfc_instReq_deq ;
|
|
assign WILL_FIRE_RL_mmio_sendInstReq =
|
|
CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ;
|
|
|
|
// rule RL_mmio_sendDataResp
|
|
assign CAN_FIRE_RL_mmio_sendDataResp =
|
|
!mmio_dataRespQ_full && !mmio_pRsQ_empty &&
|
|
mmio_pRsQ_data_0[66] ;
|
|
assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ;
|
|
|
|
// rule RL_mmio_sendInstResp
|
|
assign CAN_FIRE_RL_mmio_sendInstResp =
|
|
!mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq &&
|
|
!mmio_pRsQ_data_0[66] ;
|
|
assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ;
|
|
|
|
// rule RL_mmio_cRqQ_canonicalize
|
|
assign CAN_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_mmio_cRqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_cRqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_cRqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_pRsQ_canonicalize
|
|
assign CAN_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_mmio_pRsQ_enqReq_canon
|
|
assign CAN_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_pRsQ_deqReq_canon
|
|
assign CAN_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_pRsQ_clearReq_canon
|
|
assign CAN_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_cRsQ_canonicalize
|
|
assign CAN_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_mmio_cRsQ_enqReq_canon
|
|
assign CAN_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_cRsQ_deqReq_canon
|
|
assign CAN_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_cRsQ_clearReq_canon
|
|
assign CAN_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_doFetchTrainBP
|
|
assign CAN_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
|
|
assign WILL_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
|
|
|
|
// rule RL_coreFix_doFetchTrainBP_1
|
|
assign CAN_FIRE_RL_coreFix_doFetchTrainBP_1 = coreFix_trainBPQ_0$EMPTY_N ;
|
|
assign WILL_FIRE_RL_coreFix_doFetchTrainBP_1 =
|
|
coreFix_trainBPQ_0$EMPTY_N && !coreFix_trainBPQ_1$EMPTY_N ;
|
|
|
|
// rule RL_coreFix_memExe_doIssueSB
|
|
assign CAN_FIRE_RL_coreFix_memExe_doIssueSB =
|
|
(!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT ||
|
|
!coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_reqStQ_full_rl) &&
|
|
coreFix_memExe_stb$RDY_issue ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doIssueSB =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqLdQ_Lr_issue
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
|
|
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
|
|
coreFix_memExe_lsq$RDY_firstLd &&
|
|
!coreFix_memExe_lsq$firstLd[7] &&
|
|
!coreFix_memExe_lsq$firstLd[16] &&
|
|
coreFix_memExe_lsq$firstLd[101] &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
|
|
coreFix_memExe_stb$noMatchLdQ &&
|
|
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_issue
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
|
|
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
|
|
coreFix_memExe_lsq$RDY_firstLd &&
|
|
!coreFix_memExe_lsq$firstLd[7] &&
|
|
coreFix_memExe_lsq$firstLd[16] &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
|
|
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
|
|
!coreFix_memExe_respLrScAmoQ_full &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2696 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
|
|
2'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ;
|
|
|
|
// rule RL_renameStage_doRenaming_wrongPath
|
|
assign CAN_FIRE_RL_renameStage_doRenaming_wrongPath =
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
epochManager$checkEpoch_0_check ||
|
|
fetchStage$RDY_pipelines_0_deq) &&
|
|
NOT_fetchStage_pipelines_1_canDeq__2601_2602_O_ETC___d12610 &&
|
|
!epochManager$checkEpoch_0_check ;
|
|
assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath =
|
|
CAN_FIRE_RL_renameStage_doRenaming_wrongPath ;
|
|
|
|
// rule RL_commitStage_doCommitTrap_flush
|
|
assign CAN_FIRE_RL_commitStage_doCommitTrap_flush =
|
|
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
|
|
(rob$deqPort_0_deq_data[12] ||
|
|
epochManager$RDY_incrementEpoch) &&
|
|
!commitStage_commitTrap[133] &&
|
|
rob$deqPort_0_deq_data[103] ;
|
|
assign WILL_FIRE_RL_commitStage_doCommitTrap_flush =
|
|
CAN_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_commitStage_doCommitTrap_handle
|
|
assign CAN_FIRE_RL_commitStage_doCommitTrap_handle =
|
|
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
|
|
fetchStage$iTlbIfc_noPendingReq &&
|
|
coreFix_memExe_dTlb$noPendingReq &&
|
|
commitStage_commitTrap[133] ;
|
|
assign WILL_FIRE_RL_commitStage_doCommitTrap_handle =
|
|
CAN_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_prepareCachesAndTlbs ;
|
|
|
|
// rule RL_commitStage_doCommitKilledLd
|
|
assign CAN_FIRE_RL_commitStage_doCommitKilledLd =
|
|
epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data &&
|
|
rob$RDY_deqPort_0_deq &&
|
|
!commitStage_commitTrap[133] &&
|
|
!rob$deqPort_0_deq_data[103] &&
|
|
rob$deqPort_0_deq_data[18] ;
|
|
assign WILL_FIRE_RL_commitStage_doCommitKilledLd =
|
|
CAN_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_commitStage_doCommitSystemInst
|
|
assign CAN_FIRE_RL_commitStage_doCommitSystemInst =
|
|
coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14167 &&
|
|
!commitStage_commitTrap[133] &&
|
|
!rob$deqPort_0_deq_data[103] &&
|
|
!rob$deqPort_0_deq_data[18] &&
|
|
rob$deqPort_0_deq_data[25] &&
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd0 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd21 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd17 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd18 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd15 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd20) ;
|
|
assign WILL_FIRE_RL_commitStage_doCommitSystemInst =
|
|
CAN_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
|
|
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_prepareCachesAndTlbs ;
|
|
|
|
// rule RL_csrf_incCycle
|
|
assign CAN_FIRE_RL_csrf_incCycle = 1'd1 ;
|
|
assign WILL_FIRE_RL_csrf_incCycle = 1'd1 ;
|
|
|
|
// rule RL_csrf_mcycle_ehr_data_canon
|
|
assign CAN_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
|
|
|
|
// rule RL_commitStage_notifyLSQCommit
|
|
assign CAN_FIRE_RL_commitStage_notifyLSQCommit =
|
|
rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data &&
|
|
!commitStage_commitTrap[133] &&
|
|
!rob$deqPort_0_deq_data[103] &&
|
|
!rob$deqPort_0_deq_data[18] &&
|
|
!rob$deqPort_0_deq_data[25] &&
|
|
rob$deqPort_0_deq_data[15] &&
|
|
!rob$deqPort_0_deq_data[14] ;
|
|
assign WILL_FIRE_RL_commitStage_notifyLSQCommit =
|
|
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
|
|
|
|
// rule RL_commitStage_doCommitNormalInst
|
|
assign CAN_FIRE_RL_commitStage_doCommitNormalInst =
|
|
rob$RDY_deqPort_0_deq_data &&
|
|
NOT_rob_deqPort_0_canDeq__4362_4363_OR_rob_RDY_ETC___d14401 &&
|
|
!commitStage_commitTrap[133] &&
|
|
!rob$deqPort_0_deq_data[103] &&
|
|
!rob$deqPort_0_deq_data[18] &&
|
|
rob$deqPort_0_deq_data[25] &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd0 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd21 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd17 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd18 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd13 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd16 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd15 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd19 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd20 ;
|
|
assign WILL_FIRE_RL_commitStage_doCommitNormalInst =
|
|
CAN_FIRE_RL_commitStage_doCommitNormalInst ;
|
|
|
|
// rule RL_csrf_minstret_ehr_data_canon
|
|
assign CAN_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_aluExe_1_doFinishAlu_T
|
|
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
|
|
coreFix_aluExe_1_exeToFinQ$first[17] &&
|
|
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
|
|
coreFix_aluExe_1_exeToFinQ$RDY_first &&
|
|
rob$RDY_setExecuted_doFinishAlu_1_set &&
|
|
epochManager$RDY_incrementEpoch &&
|
|
coreFix_trainBPQ_1$FULL_N ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_aluExe_0_doFinishAlu_T
|
|
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
|
|
coreFix_aluExe_0_exeToFinQ$first[17] &&
|
|
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
|
|
coreFix_aluExe_0_exeToFinQ$RDY_first &&
|
|
rob$RDY_setExecuted_doFinishAlu_0_set &&
|
|
epochManager$RDY_incrementEpoch &&
|
|
coreFix_trainBPQ_0$FULL_N ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_aluExe_0_doFinishAlu_F
|
|
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
|
|
!coreFix_aluExe_0_exeToFinQ$first[17] &&
|
|
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
|
|
coreFix_aluExe_0_exeToFinQ_RDY_first__2480_AND_ETC___d12518 ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_aluExe_1_doFinishAlu_F
|
|
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
|
|
!coreFix_aluExe_1_exeToFinQ$first[17] &&
|
|
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
|
|
coreFix_aluExe_1_exeToFinQ_RDY_first__1873_AND_ETC___d11912 ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_aluExe_1_doExeAlu
|
|
assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu =
|
|
coreFix_aluExe_1_regToExeQ$RDY_deq &&
|
|
coreFix_aluExe_1_exeToFinQ$RDY_enq &&
|
|
coreFix_aluExe_1_regToExeQ$RDY_first ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu =
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_aluExe_0_doExeAlu
|
|
assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu =
|
|
coreFix_aluExe_0_regToExeQ$RDY_deq &&
|
|
coreFix_aluExe_0_exeToFinQ$RDY_enq &&
|
|
coreFix_aluExe_0_regToExeQ$RDY_first ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu =
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_aluExe_1_doRegReadAlu
|
|
assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
|
|
coreFix_aluExe_1_dispToRegQ$RDY_deq &&
|
|
coreFix_aluExe_1_regToExeQ$RDY_enq &&
|
|
coreFix_aluExe_1_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_1_dispToRegQ_first__1279_BIT_13_ETC___d11364 ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_aluExe_0_doRegReadAlu
|
|
assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
|
|
coreFix_aluExe_0_dispToRegQ$RDY_deq &&
|
|
coreFix_aluExe_0_regToExeQ$RDY_enq &&
|
|
coreFix_aluExe_0_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_dispToRegQ_first__2070_BIT_13_ETC___d12155 ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_aluExe_0_doDispatchAlu
|
|
assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
|
|
coreFix_aluExe_0_dispToRegQ$RDY_enq &&
|
|
coreFix_aluExe_0_rsAlu$RDY_doDispatch &&
|
|
coreFix_aluExe_0_rsAlu$RDY_dispatchData ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
|
|
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_aluExe_1_doDispatchAlu
|
|
assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
|
|
coreFix_aluExe_1_dispToRegQ$RDY_enq &&
|
|
coreFix_aluExe_1_rsAlu$RDY_doDispatch &&
|
|
coreFix_aluExe_1_rsAlu$RDY_dispatchData ;
|
|
assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
|
|
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first &&
|
|
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3872 ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5264 ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6656 ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8048 ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
|
|
|
|
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv
|
|
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8097 ;
|
|
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqLdQ_fault
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
|
|
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
|
|
coreFix_memExe_lsq$RDY_firstLd &&
|
|
coreFix_memExe_lsq$firstLd[7] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
|
|
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
|
|
coreFix_memExe_lsq$RDY_firstLd &&
|
|
!coreFix_memExe_lsq$firstLd[7] &&
|
|
!coreFix_memExe_lsq$firstLd[101] &&
|
|
!coreFix_memExe_lsq$firstLd[16] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqLdQ_Lr_deq
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
|
|
!coreFix_memExe_respLrScAmoQ_empty &&
|
|
rob$RDY_setExecuted_deqLSQ &&
|
|
coreFix_memExe_lsq$RDY_deqLd &&
|
|
coreFix_memExe_lsq$RDY_firstLd &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
|
|
!mmio_dataRespQ_empty &&
|
|
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
|
|
mmio_dataRespQ_data_0[64] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
|
|
!mmio_dataRespQ_empty &&
|
|
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
|
|
!mmio_dataRespQ_data_0[64] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doFinishMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_doFinishMem =
|
|
rob$RDY_setExecuted_doFinishMem &&
|
|
coreFix_memExe_dTlb$RDY_deqProcResp &&
|
|
coreFix_memExe_dTlb$RDY_procResp ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doFinishMem =
|
|
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
|
|
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
|
|
coreFix_memExe_lsq$RDY_firstSt &&
|
|
!coreFix_memExe_lsq$firstSt[4] &&
|
|
!coreFix_memExe_lsq$firstSt[77] &&
|
|
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1 ||
|
|
coreFix_memExe_lsq$firstSt[158:157] == 2'd2) &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
|
|
coreFix_memExe_stb$noMatchStQ &&
|
|
(!coreFix_memExe_lsq$firstSt[151] ||
|
|
coreFix_memExe_stb$isEmpty) ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_MMIO_issue
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
|
|
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
|
|
coreFix_memExe_lsq$RDY_firstSt &&
|
|
!coreFix_memExe_lsq$firstSt[4] &&
|
|
coreFix_memExe_lsq$firstSt[158:157] != 2'd3 &&
|
|
coreFix_memExe_lsq$firstSt[77] &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
|
|
(!coreFix_memExe_lsq$firstSt[151] ||
|
|
coreFix_memExe_stb$isEmpty) ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
|
|
|
|
// rule RL_mmio_dataReqQ_canonicalize
|
|
assign CAN_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_sendLrScAmoToMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
|
|
(!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT ||
|
|
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
|
|
!coreFix_memExe_reqLrScAmoQ_empty_rl) ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
|
|
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
|
|
|
|
// rule RL_coreFix_memExe_doIssueLdFromIssueQ
|
|
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
|
|
coreFix_memExe_lsq$RDY_getIssueLd &&
|
|
!coreFix_memExe_forwardQ_full &&
|
|
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
|
|
// rule RL_coreFix_memExe_doIssueLdFromUpdate
|
|
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
|
|
!coreFix_memExe_forwardQ_full &&
|
|
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 &&
|
|
coreFix_memExe_issueLd$whas ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_fault
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
|
|
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
|
|
coreFix_memExe_lsq$RDY_firstSt &&
|
|
coreFix_memExe_lsq$firstSt[4] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_Fence
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
|
|
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
|
|
coreFix_memExe_lsq$RDY_firstSt &&
|
|
!coreFix_memExe_lsq$firstSt[4] &&
|
|
coreFix_memExe_lsq$firstSt[158:157] == 2'd3 &&
|
|
(!coreFix_memExe_lsq$firstSt[151] ||
|
|
coreFix_memExe_stb$isEmpty) ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
|
|
!coreFix_memExe_respLrScAmoQ_empty &&
|
|
rob$RDY_setExecuted_deqLSQ &&
|
|
coreFix_memExe_lsq$RDY_deqSt &&
|
|
coreFix_memExe_lsq$RDY_firstSt &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_MMIO_deq
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
|
|
!mmio_dataRespQ_empty &&
|
|
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
|
|
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
|
|
mmio_dataRespQ_data_0[64] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_MMIO_fault
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
|
|
!mmio_dataRespQ_empty &&
|
|
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
|
|
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
|
|
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
|
|
!mmio_dataRespQ_data_0[64] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
|
|
|
|
// rule RL_mmio_dataRespQ_canonicalize
|
|
assign CAN_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataRespQ_enqReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataRespQ_deqReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataRespQ_clearReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataPendQ_canonicalize
|
|
assign CAN_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataPendQ_enqReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataPendQ_deqReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_mmio_dataPendQ_clearReq_canon
|
|
assign CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_sendLdToMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem =
|
|
(!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT ||
|
|
coreFix_memExe_reqLdQ_empty_lat_0$whas ||
|
|
!coreFix_memExe_reqLdQ_empty_rl) &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem =
|
|
CAN_FIRE_RL_coreFix_memExe_sendLdToMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
|
|
|
|
// rule RL_coreFix_memExe_sendStToMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_sendStToMem =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
|
|
(!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT ||
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
|
|
!coreFix_memExe_reqStQ_empty_rl) ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_sendStToMem =
|
|
CAN_FIRE_RL_coreFix_memExe_sendStToMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2100 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
|
|
2'd0 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2669 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
|
|
2'd0 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
|
|
2'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
|
|
// rule RL_coreFix_memExe_doDeqStQ_St_Mem
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
|
|
coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt &&
|
|
coreFix_memExe_lsq$RDY_firstSt &&
|
|
!coreFix_memExe_lsq$firstSt[4] &&
|
|
coreFix_memExe_lsq$firstSt[158:157] == 2'd0 &&
|
|
!coreFix_memExe_lsq$firstSt[77] &&
|
|
coreFix_memExe_stb$getEnqIndex[2] ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
|
|
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_memExe_doRespLdMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem =
|
|
!coreFix_memExe_memRespLdQ_empty ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem =
|
|
CAN_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
|
|
// rule RL_coreFix_memExe_doRespLdForward
|
|
assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward =
|
|
!coreFix_memExe_forwardQ_empty ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward =
|
|
CAN_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
|
|
// rule RL_coreFix_memExe_doExeMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_doExeMem =
|
|
coreFix_memExe_regToExeQ$RDY_deq &&
|
|
coreFix_memExe_regToExeQ$RDY_first &&
|
|
coreFix_memExe_dTlb$RDY_procReq ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doExeMem =
|
|
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
|
|
|
|
// rule RL_prepareCachesAndTlbs
|
|
assign CAN_FIRE_RL_prepareCachesAndTlbs =
|
|
(!flush_tlbs ||
|
|
coreFix_memExe_dTlb$RDY_flush &&
|
|
fetchStage$RDY_iTlbIfc_flush) &&
|
|
(flush_reservation || flush_tlbs || update_vm_info) ;
|
|
assign WILL_FIRE_RL_prepareCachesAndTlbs =
|
|
CAN_FIRE_RL_prepareCachesAndTlbs ;
|
|
|
|
// rule RL_coreFix_memExe_doRegReadMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem =
|
|
coreFix_memExe_dispToRegQ$RDY_deq &&
|
|
coreFix_memExe_regToExeQ$RDY_enq &&
|
|
coreFix_memExe_dispToRegQ$RDY_first &&
|
|
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem =
|
|
CAN_FIRE_RL_coreFix_memExe_doRegReadMem &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_memExe_doDispatchMem
|
|
assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem =
|
|
coreFix_memExe_dispToRegQ$RDY_enq &&
|
|
coreFix_memExe_rsMem$RDY_doDispatch &&
|
|
coreFix_memExe_rsMem$RDY_dispatchData ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem =
|
|
CAN_FIRE_RL_coreFix_memExe_doDispatchMem &&
|
|
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
|
|
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit &&
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
|
|
1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_respLrScAmoQ_canonicalize
|
|
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_respLrScAmoQ_deqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_respLrScAmoQ_enqReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_memRespLdQ_canonicalize
|
|
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_memRespLdQ_clearReq_canon
|
|
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_coreFix_memExe_memRespLdQ_deqReq_canon
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assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
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// rule RL_coreFix_memExe_memRespLdQ_enqReq_canon
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assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
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// rule RL_coreFix_memExe_forwardQ_canonicalize
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assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
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// rule RL_coreFix_memExe_forwardQ_clearReq_canon
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assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
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// rule RL_coreFix_memExe_forwardQ_deqReq_canon
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assign CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
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// rule RL_coreFix_memExe_forwardQ_enqReq_canon
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assign CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqStQ_full_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqStQ_empty_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqStQ_data_0_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqLrScAmoQ_full_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqLdQ_full_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqLdQ_empty_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
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// rule RL_coreFix_memExe_reqLdQ_data_0_canon
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assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
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// rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv
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assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
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coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq &&
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coreFix_fpuMulDivExe_0_regToExeQ$RDY_first &&
|
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IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8423 ;
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assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
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CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
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// rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv
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assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
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coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq &&
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coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq &&
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coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
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sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8288 ;
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assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
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CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
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!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
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!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
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!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
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!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
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// rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv
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assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
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coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq &&
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coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch &&
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coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ;
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assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
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CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
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!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
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!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
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!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
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!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
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// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit
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assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
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!coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init ;
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assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
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CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
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// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon
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assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
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assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
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// rule RL_renameStage_doRenaming_Trap
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assign CAN_FIRE_RL_renameStage_doRenaming_Trap =
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epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq &&
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fetchStage$RDY_pipelines_0_first &&
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fetchStage$RDY_pipelines_0_deq &&
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mmio_pRqQ_empty &&
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epochManager$checkEpoch_0_check &&
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fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832 &&
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rob$isEmpty ;
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assign WILL_FIRE_RL_renameStage_doRenaming_Trap =
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CAN_FIRE_RL_renameStage_doRenaming_Trap &&
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!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
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!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
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// rule RL_renameStage_doRenaming_SystemInst
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assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst =
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epochManager$RDY_incrementEpoch &&
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rob_RDY_enqPort_0_enq__2617_AND_regRenamingTab_ETC___d13042 &&
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mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13065 &&
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rob$isEmpty ;
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assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst =
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CAN_FIRE_RL_renameStage_doRenaming_SystemInst &&
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!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
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!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
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// rule RL_csrInstOrInterruptInflight_canon
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assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
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assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
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// rule RL_commitStage_doSetLSQAtCommit
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assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit =
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MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 ||
|
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WILL_FIRE_RL_commitStage_notifyLSQCommit ;
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assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit =
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CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
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// rule RL_commitStage_doSetLSQAtCommit_1
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assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
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WILL_FIRE_RL_commitStage_doCommitNormalInst &&
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rob$deqPort_1_canDeq &&
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rob$deqPort_1_deq_data[25] &&
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!rob$deqPort_1_deq_data[18] &&
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!rob$deqPort_1_deq_data[103] &&
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rob$deqPort_1_deq_data[122:118] != 5'd0 &&
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rob$deqPort_1_deq_data[122:118] != 5'd21 &&
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rob$deqPort_1_deq_data[122:118] != 5'd17 &&
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rob$deqPort_1_deq_data[122:118] != 5'd18 &&
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rob$deqPort_1_deq_data[122:118] != 5'd13 &&
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rob$deqPort_1_deq_data[122:118] != 5'd16 &&
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rob$deqPort_1_deq_data[122:118] != 5'd15 &&
|
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rob$deqPort_1_deq_data[122:118] != 5'd19 &&
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rob$deqPort_1_deq_data[122:118] != 5'd20 &&
|
|
rob$deqPort_1_deq_data[13] ;
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assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
|
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CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
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|
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// rule RL_renameStage_doRenaming
|
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assign CAN_FIRE_RL_renameStage_doRenaming =
|
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(!fetchStage$pipelines_0_canDeq ||
|
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IF_fetchStage_RDY_pipelines_0_first__2592_AND__ETC___d13130) &&
|
|
IF_NOT_fetchStage_pipelines_0_canDeq__2593_259_ETC___d13531 &&
|
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IF_NOT_fetchStage_pipelines_0_canDeq__2593_259_ETC___d13539 &&
|
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NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13702 &&
|
|
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13704 ;
|
|
assign WILL_FIRE_RL_renameStage_doRenaming =
|
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CAN_FIRE_RL_renameStage_doRenaming &&
|
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!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
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|
|
// rule RL_mmio_pRqQ_canonicalize
|
|
assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
|
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|
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// rule RL_mmio_pRqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
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|
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// rule RL_mmio_pRqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
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|
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// rule RL_mmio_pRqQ_clearReq_canon
|
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assign CAN_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
|
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|
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// rule RL_coreFix_globalSpecUpdate_canon_correct_spec
|
|
assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
|
|
assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
|
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|
|
// inputs to muxes for submodule ports
|
|
assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
|
|
rob$deqPort_0_canDeq &&
|
|
rob$deqPort_0_deq_data[13] ;
|
|
assign MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3 =
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 =
|
|
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614 ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ;
|
|
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2591 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd4 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2523 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2527) ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2574 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3) ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2719 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
|
|
2'd0 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd4 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009) ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2115) ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd4 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630) ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd4 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2658 ;
|
|
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
|
|
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
|
|
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2597) ;
|
|
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 ;
|
|
assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd1 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2622) ;
|
|
assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2557 ;
|
|
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
|
|
(coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd9 ||
|
|
coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd10) ;
|
|
assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
|
|
(coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd9 ||
|
|
coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd10) ;
|
|
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
commitStage_commitTrap[4] ;
|
|
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 ;
|
|
assign MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 =
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap &&
|
|
!fetchStage$pipelines_0_first[4] &&
|
|
(IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[12] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[13] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[14]) ;
|
|
assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd16 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd29) ;
|
|
assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd29 ;
|
|
assign MUX_csrf_fflags_reg$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd0 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd2) ;
|
|
assign MUX_csrf_fs_reg$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd0 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd1 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd2 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ;
|
|
assign MUX_csrf_ie_vec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ;
|
|
assign MUX_csrf_ie_vec_1$write_1__SEL_2 =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ;
|
|
assign MUX_csrf_ie_vec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;
|
|
assign MUX_csrf_ie_vec_3$write_1__SEL_2 =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ;
|
|
assign MUX_csrf_mpp_reg$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;
|
|
assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ;
|
|
assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ;
|
|
assign MUX_csrf_prv_reg$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd20) ;
|
|
assign MUX_csrf_spp_reg$write_1__SEL_1 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ;
|
|
assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ;
|
|
assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13807 &&
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 ;
|
|
assign MUX_flush_reservation$write_1__SEL_1 =
|
|
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ;
|
|
assign MUX_flush_tlbs$write_1__SEL_1 =
|
|
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ;
|
|
assign MUX_rf$write_3_wr_1__SEL_1 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_rf$write_3_wr_1__SEL_2 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_rf$write_3_wr_1__SEL_3 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_rf$write_3_wr_1__SEL_4 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_rf$write_3_wr_1__PSEL_5 =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
|
|
assign MUX_rf$write_3_wr_1__SEL_5 =
|
|
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
|
|
assign MUX_rf$write_3_wr_2__SEL_5 =
|
|
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
|
|
assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ;
|
|
assign MUX_sbAggr$setReady_4_put_1__SEL_1 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_sbAggr$setReady_4_put_1__SEL_2 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_sbCons$setReady_3_put_1__SEL_1 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
|
|
coreFix_memExe_lsq$firstSt[150] ;
|
|
assign MUX_sbCons$setReady_3_put_1__SEL_2 =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
|
|
coreFix_memExe_lsq$firstLd[89] ;
|
|
assign MUX_sbCons$setReady_3_put_1__SEL_3 =
|
|
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
|
|
assign MUX_update_vm_info$write_1__SEL_1 =
|
|
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ;
|
|
assign MUX_commitStage_commitTrap$write_1__VAL_2 =
|
|
{ 1'd1,
|
|
rob$deqPort_0_deq_data[186:123],
|
|
rob$deqPort_0_deq_data[95:32],
|
|
rob$deqPort_0_deq_data[102],
|
|
rob$deqPort_0_deq_data[102] ?
|
|
CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q259 :
|
|
CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q260 } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 =
|
|
(k__h659336 == 1'd0 &&
|
|
fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13710) ?
|
|
{ fetchStage$pipelines_0_first[103:99],
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721,
|
|
fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
fetchStage$pipelines_0_first[64:32],
|
|
fetchStage$pipelines_0_first[159:136],
|
|
regRenamingTable$rename_0_getRename,
|
|
rob$enqPort_0_getEnqInstTag,
|
|
specTagManager$currentSpecBits,
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_0_get } :
|
|
{ fetchStage$pipelines_1_first[103:99],
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275,
|
|
fetchStage_pipelines_1_first__2604_BIT_77_3276_ETC___d13351,
|
|
fetchStage$pipelines_1_first[64:32],
|
|
fetchStage$pipelines_1_first[159:136],
|
|
regRenamingTable$rename_1_getRename,
|
|
rob$enqPort_1_getEnqInstTag,
|
|
renaming_spec_bits__h672935,
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_1_get } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 =
|
|
{ fetchStage$pipelines_0_first[103:99],
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721,
|
|
fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
fetchStage$pipelines_0_first[64:32],
|
|
fetchStage$pipelines_0_first[159:136],
|
|
regRenamingTable$rename_0_getRename,
|
|
rob$enqPort_0_getEnqInstTag,
|
|
specTagManager$currentSpecBits,
|
|
5'd10,
|
|
sbAggr$eagerLookup_0_get } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 =
|
|
{ 1'd1,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 =
|
|
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 =
|
|
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 =
|
|
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 =
|
|
{ 1'd1,
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 =
|
|
{ 1'd1,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 =
|
|
{ 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 =
|
|
{ 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ;
|
|
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 =
|
|
{ 1'd1, coreFix_memExe_lsq$getHit[7:1] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 ?
|
|
3'd3 :
|
|
3'd5) :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2531 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 ?
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
|
|
53'h15555555555555 } :
|
|
58'h155555555555554) :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2542 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
|
|
55'h15555555555555 } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
{ (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } :
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } :
|
|
{ (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 ?
|
|
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2502 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2515 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492 } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100],
|
|
2'd3,
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0],
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2000,
|
|
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd0) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 =
|
|
{ IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2705,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) :
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2518 ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 =
|
|
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84],
|
|
x__h283013 } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 =
|
|
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
|
|
x__h284458,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 =
|
|
{ 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2867,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 =
|
|
{ 2'd2,
|
|
addr__h287234,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2937 } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 =
|
|
{ x__h152848, x__h152854, 84'h82AAAAAAAAAAAAAAAAAAA } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 =
|
|
{ x__h156395, x__h156401, 84'hCAAAAAAAAAAAAAAAAAAAA } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 =
|
|
{ x__h159211,
|
|
x__h159215,
|
|
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
|
|
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
|
|
x__h161063,
|
|
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 =
|
|
{ 1'd0,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
resp_addr__h289138,
|
|
2'd0,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ;
|
|
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ;
|
|
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
coreFix_memExe_lsq$getIssueLd[76:72],
|
|
coreFix_memExe_lsq$issueLd[63:0] } ;
|
|
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
coreFix_memExe_issueLd$wget[76:72],
|
|
coreFix_memExe_lsq$issueLd[63:0] } ;
|
|
assign MUX_coreFix_memExe_lsq$getHit_1__VAL_2 =
|
|
{ 1'd0,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ;
|
|
assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 =
|
|
{ coreFix_memExe_stb$search[67],
|
|
coreFix_memExe_stb$search[67] ?
|
|
coreFix_memExe_stb$search[66:65] :
|
|
2'h2,
|
|
coreFix_memExe_stb$search[64],
|
|
coreFix_memExe_stb$search[64] ?
|
|
coreFix_memExe_stb$search[63:0] :
|
|
64'hAAAAAAAAAAAAAAAA } ;
|
|
always@(coreFix_memExe_memRespLdQ_deqP or
|
|
coreFix_memExe_memRespLdQ_data_0 or
|
|
coreFix_memExe_memRespLdQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_memRespLdQ_deqP)
|
|
1'd0:
|
|
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
|
|
coreFix_memExe_memRespLdQ_data_0[68:64];
|
|
1'd1:
|
|
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
|
|
coreFix_memExe_memRespLdQ_data_1[68:64];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_forwardQ_deqP or
|
|
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_forwardQ_deqP)
|
|
1'd0:
|
|
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
|
|
coreFix_memExe_forwardQ_data_0[68:64];
|
|
1'd1:
|
|
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
|
|
coreFix_memExe_forwardQ_data_1[68:64];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_memRespLdQ_deqP or
|
|
coreFix_memExe_memRespLdQ_data_0 or
|
|
coreFix_memExe_memRespLdQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_memRespLdQ_deqP)
|
|
1'd0:
|
|
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
|
|
coreFix_memExe_memRespLdQ_data_0[63:0];
|
|
1'd1:
|
|
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
|
|
coreFix_memExe_memRespLdQ_data_1[63:0];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_forwardQ_deqP or
|
|
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_forwardQ_deqP)
|
|
1'd0:
|
|
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
|
|
coreFix_memExe_forwardQ_data_0[63:0];
|
|
1'd1:
|
|
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
|
|
coreFix_memExe_forwardQ_data_1[63:0];
|
|
endcase
|
|
end
|
|
assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148],
|
|
x__h194294 } ;
|
|
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 =
|
|
{ 5'd0,
|
|
coreFix_memExe_lsq$firstSt[141:78],
|
|
2'd3,
|
|
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4,
|
|
coreFix_memExe_lsq$firstSt[76:5],
|
|
coreFix_memExe_lsq$firstSt[156:153],
|
|
coreFix_memExe_lsq$firstSt[69] &&
|
|
coreFix_memExe_lsq$firstSt[70] &&
|
|
coreFix_memExe_lsq$firstSt[71] &&
|
|
coreFix_memExe_lsq$firstSt[72] &&
|
|
coreFix_memExe_lsq$firstSt[73] &&
|
|
coreFix_memExe_lsq$firstSt[74] &&
|
|
coreFix_memExe_lsq$firstSt[75] &&
|
|
coreFix_memExe_lsq$firstSt[76],
|
|
coreFix_memExe_lsq$firstSt[152:151] } ;
|
|
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 =
|
|
{ 5'd0,
|
|
coreFix_memExe_lsq$firstLd[80:17],
|
|
84'h92AAAAAAAAAAAAAAAAAAA } ;
|
|
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) ?
|
|
{ 1'd1,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2559 } :
|
|
65'h10000000000000001) :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2562 ;
|
|
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2559 } ;
|
|
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ?
|
|
curData__h190083 :
|
|
{ {32{x__h190846[31]}}, x__h190846 } } ;
|
|
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 =
|
|
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
|
|
coreFix_aluExe_0_exeToFinQ$first[325:321],
|
|
coreFix_aluExe_0_exeToFinQ$first[18],
|
|
coreFix_aluExe_0_exeToFinQ$first[299:276],
|
|
1'd0 } ;
|
|
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 =
|
|
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
|
|
coreFix_aluExe_0_exeToFinQ$first[325:321],
|
|
coreFix_aluExe_0_exeToFinQ$first[18],
|
|
coreFix_aluExe_0_exeToFinQ$first[299:276],
|
|
1'd1 } ;
|
|
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 =
|
|
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
|
|
coreFix_aluExe_1_exeToFinQ$first[325:321],
|
|
coreFix_aluExe_1_exeToFinQ$first[18],
|
|
coreFix_aluExe_1_exeToFinQ$first[299:276],
|
|
1'd0 } ;
|
|
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 =
|
|
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
|
|
coreFix_aluExe_1_exeToFinQ$first[325:321],
|
|
coreFix_aluExe_1_exeToFinQ$first[18],
|
|
coreFix_aluExe_1_exeToFinQ$first[299:276],
|
|
1'd1 } ;
|
|
assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 =
|
|
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 ||
|
|
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ;
|
|
assign MUX_csrf_fflags_reg$write_1__VAL_2 =
|
|
csrf_fflags_reg | fflags__h702055 ;
|
|
always@(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 or
|
|
robdeqPort_0_deq_data_BITS_95_TO_32__q261)
|
|
begin
|
|
case (IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152)
|
|
6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_1 = 2'b11;
|
|
default: MUX_csrf_fs_reg$write_1__VAL_1 =
|
|
robdeqPort_0_deq_data_BITS_95_TO_32__q261[14:13];
|
|
endcase
|
|
end
|
|
assign MUX_csrf_ie_vec_1$write_1__VAL_1 =
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18)) ?
|
|
robdeqPort_0_deq_data_BITS_95_TO_32__q261[1] :
|
|
csrf_prev_ie_vec_1 ;
|
|
assign MUX_csrf_ie_vec_3$write_1__VAL_1 =
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ?
|
|
robdeqPort_0_deq_data_BITS_95_TO_32__q261[3] :
|
|
csrf_prev_ie_vec_3 ;
|
|
assign MUX_csrf_mepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
|
|
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 =
|
|
n__read__h699967 + 64'd1 ;
|
|
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 =
|
|
n__read__h699967 + { 62'd0, x__h702270 } ;
|
|
assign MUX_csrf_mpp_reg$write_1__VAL_1 =
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ?
|
|
MUX_csrf_mepc_csr$write_1__VAL_2[12:11] :
|
|
2'd0 ;
|
|
assign MUX_csrf_mtval_csr$write_1__VAL_1 =
|
|
commitStage_commitTrap[4] ? 64'd0 : trap_val__h690161 ;
|
|
assign MUX_csrf_mtval_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
|
|
assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 =
|
|
rob$deqPort_0_deq_data[122:118] != 5'd13 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 !=
|
|
6'd8 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 !=
|
|
6'd18 ||
|
|
MUX_csrf_mtval_csr$write_1__VAL_2[5] ;
|
|
assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 =
|
|
rob$deqPort_0_deq_data[122:118] != 5'd13 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 !=
|
|
6'd18 ||
|
|
MUX_csrf_mtval_csr$write_1__VAL_2[7] ;
|
|
assign MUX_csrf_prv_reg$write_1__VAL_1 =
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd19) ?
|
|
x__h699370 :
|
|
csrf_mpp_reg ;
|
|
assign MUX_csrf_prv_reg$write_1__VAL_2 =
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ?
|
|
2'd1 :
|
|
2'd3 ;
|
|
assign MUX_csrf_sepc_csr$write_1__VAL_2 = rob$deqPort_0_deq_data[95:32] ;
|
|
assign MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 =
|
|
(mmio_pRqQ_data_0[37:36] == 2'd2) ?
|
|
mmio_pRqQ_data_0[0] :
|
|
amoExec___d880[0] ;
|
|
assign MUX_csrf_spp_reg$write_1__VAL_1 =
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) &&
|
|
MUX_csrf_sepc_csr$write_1__VAL_2[8] ;
|
|
assign MUX_fetchStage$redirect_1__VAL_4 =
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ?
|
|
y_avValue__h690008 :
|
|
y_avValue__h691772 ;
|
|
always@(rob$deqPort_0_deq_data or
|
|
next_pc__h699310 or csrf_sepc_csr or csrf_mepc_csr)
|
|
begin
|
|
case (rob$deqPort_0_deq_data[122:118])
|
|
5'd19: MUX_fetchStage$redirect_1__VAL_5 = csrf_sepc_csr;
|
|
5'd20: MUX_fetchStage$redirect_1__VAL_5 = csrf_mepc_csr;
|
|
default: MUX_fetchStage$redirect_1__VAL_5 = next_pc__h699310;
|
|
endcase
|
|
end
|
|
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 =
|
|
{ 1'd1,
|
|
coreFix_memExe_dTlb$toParent_rqToP_first[1:0],
|
|
coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ;
|
|
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 =
|
|
{ 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ;
|
|
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
mmio_dataReqQ_data_0[141:78],
|
|
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262,
|
|
mmio_dataReqQ_data_0[71:0] } ;
|
|
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
fetchStage$mmioIfc_instReq_first_fst,
|
|
5'd2,
|
|
fetchStage$mmioIfc_instReq_first_snd,
|
|
72'hAAAAAAAAAAAAAAAAAA } ;
|
|
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 =
|
|
{ 1'd1,
|
|
coreFix_memExe_lsq$firstSt[141:78],
|
|
(coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ?
|
|
6'd42 :
|
|
{ 2'd3, coreFix_memExe_lsq$firstSt[156:153] },
|
|
coreFix_memExe_lsq$firstSt[76:5] } ;
|
|
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 =
|
|
{ 1'd1,
|
|
coreFix_memExe_lsq$firstLd[80:17],
|
|
6'd26,
|
|
coreFix_memExe_lsq$firstLd[15:0],
|
|
56'hAAAAAAAAAAAAAA } ;
|
|
assign MUX_rf$write_2_wr_2__VAL_1 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ?
|
|
data___1__h472962 :
|
|
data__h472428 ;
|
|
assign MUX_rf$write_2_wr_2__VAL_3 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
|
|
res_data__h335041 :
|
|
res_data__h335036 ;
|
|
assign MUX_rf$write_2_wr_2__VAL_4 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
|
|
res_data__h380736 :
|
|
res_data__h380731 ;
|
|
assign MUX_rf$write_2_wr_2__VAL_5 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
|
|
res_data__h426424 :
|
|
res_data__h426419 ;
|
|
assign MUX_rf$write_2_wr_2__VAL_6 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ?
|
|
data___1__h472154 :
|
|
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8062 ;
|
|
assign MUX_rf$write_3_wr_2__VAL_3 =
|
|
coreFix_memExe_lsq$firstLd[100] ?
|
|
coreFix_memExe_respLrScAmoQ_data_0 :
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 ;
|
|
assign MUX_rf$write_3_wr_2__VAL_4 =
|
|
coreFix_memExe_lsq$firstLd[100] ?
|
|
mmio_dataRespQ_data_0[63:0] :
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 ;
|
|
assign MUX_rob$enqPort_0_enq_1__VAL_1 =
|
|
{ fetchStage$pipelines_0_first[291:228],
|
|
fetchStage$pipelines_0_first[103:99],
|
|
fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
9'd296,
|
|
fetchStage$pipelines_0_first[227:164],
|
|
5'd0,
|
|
fetchStage$pipelines_0_first[11] &&
|
|
fetchStage$pipelines_0_first[10],
|
|
fetchStage$pipelines_0_first[98:96] != 3'd0 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd3 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd4,
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13776 } ;
|
|
assign MUX_rob$enqPort_0_enq_1__VAL_2 =
|
|
{ fetchStage$pipelines_0_first[291:228],
|
|
fetchStage$pipelines_0_first[103:99],
|
|
fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
2'd1,
|
|
!fetchStage$pipelines_0_first[4] &&
|
|
(IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[12] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[13] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[14]),
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d13023,
|
|
2'd0,
|
|
fetchStage$pipelines_0_first[227:164],
|
|
20'd13601,
|
|
specTagManager$currentSpecBits } ;
|
|
assign MUX_rob$enqPort_0_enq_1__VAL_3 =
|
|
{ fetchStage$pipelines_0_first[291:228],
|
|
fetchStage$pipelines_0_first[103:99],
|
|
fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
9'd296,
|
|
fetchStage$pipelines_0_first[227:164],
|
|
5'd0,
|
|
fetchStage$pipelines_0_first[11] &&
|
|
fetchStage$pipelines_0_first[10],
|
|
fetchStage$pipelines_0_first[98:96] != 3'd0,
|
|
13'h1521,
|
|
specTagManager$currentSpecBits } ;
|
|
assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 =
|
|
{ 1'd1,
|
|
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 } ;
|
|
assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 =
|
|
{ 1'd1,
|
|
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 } ;
|
|
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] :
|
|
res_fflags__h335037 ;
|
|
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] :
|
|
res_fflags__h380732 ;
|
|
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] :
|
|
res_fflags__h426420 ;
|
|
|
|
// inlined wires
|
|
assign csrf_minstret_ehr_data_lat_0$whas =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd31 ;
|
|
assign csrf_minstret_ehr_data_lat_1$whas =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst ;
|
|
assign csrf_minstret_ehr_data_dummy_1_0$whas =
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
|
|
assign csrf_mcycle_ehr_data_lat_0$wget = rob$deqPort_0_deq_data[95:32] ;
|
|
assign csrf_mcycle_ehr_data_lat_0$whas =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd30 ;
|
|
assign csrInstOrInterruptInflight_lat_1$whas =
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
|
|
fetchStage$pipelines_0_first[103:99] == 5'd13 ||
|
|
MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ;
|
|
assign mmio_dataReqQ_enqReq_lat_0$wget =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ?
|
|
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign mmio_dataReqQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
|
|
assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ;
|
|
assign mmio_dataRespQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ;
|
|
assign mmio_dataPendQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ;
|
|
assign mmio_cRqQ_enqReq_lat_0$wget =
|
|
WILL_FIRE_RL_mmio_sendDataReq ?
|
|
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign mmio_cRqQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ;
|
|
assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ;
|
|
assign mmio_pRsQ_deqReq_dummy_2_0$wget =
|
|
WILL_FIRE_RL_mmio_sendInstResp ||
|
|
WILL_FIRE_RL_mmio_sendDataResp ;
|
|
assign mmio_pRqQ_enqReq_lat_0$wget =
|
|
{ 1'd1,
|
|
mmioToPlatform_pRq_enq_x[38],
|
|
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265,
|
|
mmioToPlatform_pRq_enq_x[31:0] } ;
|
|
assign mmio_cRsQ_enqReq_lat_0$wget =
|
|
{ 1'd1, csrf_software_int_pend_vec_3 } ;
|
|
assign coreFix_globalSpecUpdate_correctSpecTag_0$whas =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
|
|
coreFix_aluExe_0_exeToFinQ$first[16] ;
|
|
assign coreFix_globalSpecUpdate_correctSpecTag_1$whas =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
|
|
coreFix_aluExe_1_exeToFinQ$first[16] ;
|
|
assign coreFix_aluExe_0_bypassWire_0$wget =
|
|
{ coreFix_aluExe_0_regToExeQ$first[316:310],
|
|
basicExec___d12459[321:258] } ;
|
|
assign coreFix_aluExe_0_bypassWire_0$whas =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
|
|
coreFix_aluExe_0_regToExeQ$first[317] ;
|
|
assign coreFix_aluExe_0_bypassWire_1$wget =
|
|
{ coreFix_aluExe_1_regToExeQ$first[316:310],
|
|
basicExec___d11852[321:258] } ;
|
|
assign coreFix_aluExe_0_bypassWire_1$whas =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
|
|
coreFix_aluExe_1_regToExeQ$first[317] ;
|
|
assign coreFix_aluExe_0_bypassWire_2$wget =
|
|
{ coreFix_aluExe_0_exeToFinQ$first[319:313],
|
|
coreFix_aluExe_0_exeToFinQ$first[275:212] } ;
|
|
assign coreFix_aluExe_0_bypassWire_2$whas =
|
|
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset &&
|
|
coreFix_aluExe_0_exeToFinQ$first[320] ;
|
|
assign coreFix_aluExe_0_bypassWire_3$wget =
|
|
{ coreFix_aluExe_1_exeToFinQ$first[319:313],
|
|
coreFix_aluExe_1_exeToFinQ$first[275:212] } ;
|
|
assign coreFix_aluExe_0_bypassWire_3$whas =
|
|
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset &&
|
|
coreFix_aluExe_1_exeToFinQ$first[320] ;
|
|
assign coreFix_aluExe_1_bypassWire_2$whas =
|
|
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset &&
|
|
coreFix_aluExe_0_exeToFinQ$first[320] ;
|
|
assign coreFix_aluExe_1_bypassWire_3$whas =
|
|
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset &&
|
|
coreFix_aluExe_1_exeToFinQ$first[320] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_2$whas =
|
|
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset &&
|
|
coreFix_aluExe_0_exeToFinQ$first[320] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_3$whas =
|
|
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset &&
|
|
coreFix_aluExe_1_exeToFinQ$first[320] ;
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225])
|
|
2'd0, 2'd1:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225];
|
|
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget = 2'd2;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
|
|
assign coreFix_memExe_bypassWire_2$whas =
|
|
_dor1coreFix_memExe_bypassWire_2$EN_wset &&
|
|
coreFix_aluExe_0_exeToFinQ$first[320] ;
|
|
assign coreFix_memExe_bypassWire_3$whas =
|
|
_dor1coreFix_memExe_bypassWire_3$EN_wset &&
|
|
coreFix_aluExe_1_exeToFinQ$first[320] ;
|
|
assign coreFix_memExe_issueLd$wget =
|
|
{ coreFix_memExe_dTlb$procResp[89:85],
|
|
coreFix_memExe_dTlb$procResp[174:111],
|
|
coreFix_memExe_dTlb$procResp[84:77] } ;
|
|
assign coreFix_memExe_issueLd$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd0 &&
|
|
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 &&
|
|
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1724 &&
|
|
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1737 &&
|
|
!coreFix_memExe_lsq$updateAddr ;
|
|
assign coreFix_memExe_reqLdQ_data_0_lat_0$wget =
|
|
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ?
|
|
coreFix_memExe_issueLd$wget[76:8] :
|
|
coreFix_memExe_lsq$getIssueLd[76:8] ;
|
|
assign coreFix_memExe_reqLdQ_data_0_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
assign coreFix_memExe_reqLdQ_empty_lat_0$whas =
|
|
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
assign coreFix_memExe_reqLdQ_full_lat_0$whas =
|
|
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ?
|
|
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 :
|
|
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
|
|
assign coreFix_memExe_reqStQ_data_0_lat_0$wget =
|
|
{ coreFix_memExe_stb$issue[635:576], 6'd0 } ;
|
|
assign coreFix_memExe_forwardQ_enqReq_lat_0$wget =
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ?
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign coreFix_memExe_forwardQ_enqReq_lat_0$whas =
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ||
|
|
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ;
|
|
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget =
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
|
|
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ;
|
|
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas =
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ;
|
|
always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1:
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1;
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2;
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
|
|
default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
|
|
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas =
|
|
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 ||
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or
|
|
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem:
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1;
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem:
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2;
|
|
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem:
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3;
|
|
default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
|
|
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ?
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82],
|
|
1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget =
|
|
{ 1'd1, dCacheToParent_fromP_enq_x } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget =
|
|
{ 1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2641 ;
|
|
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1:
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1;
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3:
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
|
|
59'h2AAAAAAAAAAAAAA;
|
|
default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
|
|
59'h2AAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 ||
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
|
|
assign coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas =
|
|
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
|
|
|
|
// register commitStage_commitTrap
|
|
assign commitStage_commitTrap$D_IN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle ?
|
|
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
|
|
MUX_commitStage_commitTrap$write_1__VAL_2 ;
|
|
assign commitStage_commitTrap$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
|
|
// register coreFix_doStatsReg
|
|
assign coreFix_doStatsReg$D_IN = 1'b0 ;
|
|
assign coreFix_doStatsReg$EN = 1'b0 ;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt + 4'd1 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN = 1'd1 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt == 4'd15 ;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ?
|
|
v__h601366 :
|
|
v__h600721 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN =
|
|
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget } ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN = 1'd1 ;
|
|
|
|
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN =
|
|
1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN =
|
|
1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd0 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd1 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd2 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd4 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd5 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd6 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd7 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
|
|
3'd0 :
|
|
_theResult_____2__h293689 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN =
|
|
1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN =
|
|
1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3050 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3070 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
|
|
3'd0 :
|
|
v__h293109 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN =
|
|
4'b0010 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN =
|
|
1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3050 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3059 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN =
|
|
{ !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3172 ||
|
|
(EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]),
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3239 } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3119 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3130 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3119 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3130 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3119 &&
|
|
_theResult_____2__h301685 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3152 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3175 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3119 &&
|
|
v__h296454 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN =
|
|
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3119 &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3152 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3162 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN =
|
|
{ IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2996,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
|
|
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 or
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1:
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1;
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2:
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
|
|
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
|
|
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd4 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN =
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3290 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3301 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3290 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3301 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3290 &&
|
|
_theResult_____2__h307679 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3347 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3290 &&
|
|
v__h306968 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN =
|
|
73'h0AAAAAAAAAAAAAAAAAA ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3290 &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3333 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN =
|
|
{ x_addr__h311242,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513],
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3439 ||
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]),
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3386 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3397 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3386 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3397 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3386 &&
|
|
_theResult_____2__h315533 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3443 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3386 &&
|
|
v__h310844 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN =
|
|
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN =
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3386 &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3429 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
|
|
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_data_0
|
|
assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN =
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ;
|
|
assign coreFix_memExe_dMem_perfReqQ_data_0$EN =
|
|
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1875 &&
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_empty
|
|
assign coreFix_memExe_dMem_perfReqQ_empty$D_IN =
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_rl ||
|
|
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1919 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_dMem_perfReqQ_full
|
|
assign coreFix_memExe_dMem_perfReqQ_full$D_IN =
|
|
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1875 &&
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1903 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_forwardQ_clearReq_rl
|
|
assign coreFix_memExe_forwardQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_forwardQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_forwardQ_data_0
|
|
assign coreFix_memExe_forwardQ_data_0$D_IN =
|
|
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
|
|
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
|
|
assign coreFix_memExe_forwardQ_data_0$EN =
|
|
coreFix_memExe_forwardQ_enqP == 1'd0 &&
|
|
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3709 &&
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3720 ;
|
|
|
|
// register coreFix_memExe_forwardQ_data_1
|
|
assign coreFix_memExe_forwardQ_data_1$D_IN =
|
|
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
|
|
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
|
|
assign coreFix_memExe_forwardQ_data_1$EN =
|
|
coreFix_memExe_forwardQ_enqP == 1'd1 &&
|
|
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3709 &&
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3720 ;
|
|
|
|
// register coreFix_memExe_forwardQ_deqP
|
|
assign coreFix_memExe_forwardQ_deqP$D_IN =
|
|
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3709 &&
|
|
_theResult_____2__h329102 ;
|
|
assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_forwardQ_deqReq_rl
|
|
assign coreFix_memExe_forwardQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_forwardQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_forwardQ_empty
|
|
assign coreFix_memExe_forwardQ_empty$D_IN =
|
|
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_forwardQ_clearReq_rl ||
|
|
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3742 &&
|
|
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3764 ;
|
|
assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_forwardQ_enqP
|
|
assign coreFix_memExe_forwardQ_enqP$D_IN =
|
|
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3709 &&
|
|
v__h328670 ;
|
|
assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_forwardQ_enqReq_rl
|
|
assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
|
|
assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_forwardQ_full
|
|
assign coreFix_memExe_forwardQ_full$D_IN =
|
|
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3709 &&
|
|
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3742 &&
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3751 ;
|
|
assign coreFix_memExe_forwardQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_clearReq_rl
|
|
assign coreFix_memExe_memRespLdQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_memRespLdQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_data_0
|
|
assign coreFix_memExe_memRespLdQ_data_0$D_IN =
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
|
|
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
|
|
assign coreFix_memExe_memRespLdQ_data_0$EN =
|
|
coreFix_memExe_memRespLdQ_enqP == 1'd0 &&
|
|
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3615 &&
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3626 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_data_1
|
|
assign coreFix_memExe_memRespLdQ_data_1$D_IN =
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
|
|
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
|
|
assign coreFix_memExe_memRespLdQ_data_1$EN =
|
|
coreFix_memExe_memRespLdQ_enqP == 1'd1 &&
|
|
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3615 &&
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3626 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_deqP
|
|
assign coreFix_memExe_memRespLdQ_deqP$D_IN =
|
|
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3615 &&
|
|
_theResult_____2__h325877 ;
|
|
assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_deqReq_rl
|
|
assign coreFix_memExe_memRespLdQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_memRespLdQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_empty
|
|
assign coreFix_memExe_memRespLdQ_empty$D_IN =
|
|
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_memRespLdQ_clearReq_rl ||
|
|
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3648 &&
|
|
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3670 ;
|
|
assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_enqP
|
|
assign coreFix_memExe_memRespLdQ_enqP$D_IN =
|
|
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3615 &&
|
|
v__h325445 ;
|
|
assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_enqReq_rl
|
|
assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
|
|
assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_memRespLdQ_full
|
|
assign coreFix_memExe_memRespLdQ_full$D_IN =
|
|
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3615 &&
|
|
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3648 &&
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3657 ;
|
|
assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqLdQ_data_0_rl
|
|
assign coreFix_memExe_reqLdQ_data_0_rl$D_IN =
|
|
coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLdQ_data_0_lat_0$wget :
|
|
coreFix_memExe_reqLdQ_data_0_rl ;
|
|
assign coreFix_memExe_reqLdQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqLdQ_empty_rl
|
|
assign coreFix_memExe_reqLdQ_empty_rl$D_IN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
|
|
!coreFix_memExe_reqLdQ_empty_lat_0$whas &&
|
|
coreFix_memExe_reqLdQ_empty_rl ;
|
|
assign coreFix_memExe_reqLdQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqLdQ_full_rl
|
|
assign coreFix_memExe_reqLdQ_full_rl$D_IN =
|
|
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
|
|
(coreFix_memExe_reqLdQ_full_lat_0$whas ||
|
|
coreFix_memExe_reqLdQ_full_rl) ;
|
|
assign coreFix_memExe_reqLdQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqLrScAmoQ_empty_rl
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN =
|
|
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
|
|
!coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas &&
|
|
coreFix_memExe_reqLrScAmoQ_empty_rl ;
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqLrScAmoQ_full_rl
|
|
assign coreFix_memExe_reqLrScAmoQ_full_rl$D_IN =
|
|
!CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem &&
|
|
(coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
|
|
coreFix_memExe_reqLrScAmoQ_full_rl) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqStQ_data_0_rl
|
|
assign coreFix_memExe_reqStQ_data_0_rl$D_IN =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
|
|
coreFix_memExe_reqStQ_data_0_lat_0$wget :
|
|
coreFix_memExe_reqStQ_data_0_rl ;
|
|
assign coreFix_memExe_reqStQ_data_0_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqStQ_empty_rl
|
|
assign coreFix_memExe_reqStQ_empty_rl$D_IN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
|
|
!CAN_FIRE_RL_coreFix_memExe_doIssueSB &&
|
|
coreFix_memExe_reqStQ_empty_rl ;
|
|
assign coreFix_memExe_reqStQ_empty_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_reqStQ_full_rl
|
|
assign coreFix_memExe_reqStQ_full_rl$D_IN =
|
|
!WILL_FIRE_RL_coreFix_memExe_sendStToMem &&
|
|
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
|
|
coreFix_memExe_reqStQ_full_rl) ;
|
|
assign coreFix_memExe_reqStQ_full_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
|
|
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_data_0
|
|
assign coreFix_memExe_respLrScAmoQ_data_0$D_IN =
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] :
|
|
coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ;
|
|
assign coreFix_memExe_respLrScAmoQ_data_0$EN =
|
|
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3539 &&
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3550 ;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_empty
|
|
assign coreFix_memExe_respLrScAmoQ_empty$D_IN =
|
|
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_respLrScAmoQ_clearReq_rl ||
|
|
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3581 ;
|
|
assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_respLrScAmoQ_full
|
|
assign coreFix_memExe_respLrScAmoQ_full$D_IN =
|
|
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3539 &&
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3566 ;
|
|
assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ;
|
|
|
|
// register coreFix_memExe_waitLrScAmoMMIOResp
|
|
always@(MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1:
|
|
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd0;
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue:
|
|
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd4;
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue:
|
|
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd2;
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue:
|
|
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd6;
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue:
|
|
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd7;
|
|
default: coreFix_memExe_waitLrScAmoMMIOResp$D_IN =
|
|
3'b010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_waitLrScAmoMMIOResp$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
|
|
|
|
// register csrInstOrInterruptInflight_rl
|
|
assign csrInstOrInterruptInflight_rl$D_IN =
|
|
csrInstOrInterruptInflight_lat_1$whas ?
|
|
1'd1 :
|
|
(MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ?
|
|
1'd0 :
|
|
csrInstOrInterruptInflight_rl) ;
|
|
assign csrInstOrInterruptInflight_rl$EN = 1'd1 ;
|
|
|
|
// register csrf_debug_int_pend
|
|
assign csrf_debug_int_pend$D_IN =
|
|
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 ?
|
|
csrf_mcycle_ehr_data_lat_0$wget[14] :
|
|
setDEIP_v ;
|
|
assign csrf_debug_int_pend$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd29 ||
|
|
EN_setDEIP ;
|
|
|
|
// register csrf_external_int_en_vec_0
|
|
assign csrf_external_int_en_vec_0$D_IN =
|
|
csrf_mcycle_ehr_data_lat_0$wget[8] ;
|
|
assign csrf_external_int_en_vec_0$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd9 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22) ;
|
|
|
|
// register csrf_external_int_en_vec_1
|
|
assign csrf_external_int_en_vec_1$D_IN =
|
|
csrf_mcycle_ehr_data_lat_0$wget[9] ;
|
|
assign csrf_external_int_en_vec_1$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd9 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22) ;
|
|
|
|
// register csrf_external_int_en_vec_3
|
|
assign csrf_external_int_en_vec_3$D_IN =
|
|
csrf_mcycle_ehr_data_lat_0$wget[11] ;
|
|
assign csrf_external_int_en_vec_3$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22 ;
|
|
|
|
// register csrf_external_int_pend_vec_0
|
|
assign csrf_external_int_pend_vec_0$D_IN =
|
|
csrf_mcycle_ehr_data_lat_0$wget[8] ;
|
|
assign csrf_external_int_pend_vec_0$EN =
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
|
|
|
|
// register csrf_external_int_pend_vec_1
|
|
assign csrf_external_int_pend_vec_1$D_IN =
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ?
|
|
csrf_mcycle_ehr_data_lat_0$wget[9] :
|
|
setSEIP_v ;
|
|
assign csrf_external_int_pend_vec_1$EN =
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 || EN_setSEIP ;
|
|
|
|
// register csrf_external_int_pend_vec_3
|
|
assign csrf_external_int_pend_vec_3$D_IN =
|
|
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 ?
|
|
csrf_mcycle_ehr_data_lat_0$wget[11] :
|
|
setMEIP_v ;
|
|
assign csrf_external_int_pend_vec_3$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd29 ||
|
|
EN_setMEIP ;
|
|
|
|
// register csrf_fflags_reg
|
|
assign csrf_fflags_reg$D_IN =
|
|
MUX_csrf_fflags_reg$write_1__SEL_1 ?
|
|
csrf_mcycle_ehr_data_lat_0$wget[4:0] :
|
|
MUX_csrf_fflags_reg$write_1__VAL_2 ;
|
|
assign csrf_fflags_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd0 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd2) ||
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
|
|
NOT_IF_NOT_rob_deqPort_0_canDeq__4362_4363_OR__ETC___d14479 ;
|
|
|
|
// register csrf_frm_reg
|
|
assign csrf_frm_reg$D_IN =
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd1) ?
|
|
csrf_mcycle_ehr_data_lat_0$wget[2:0] :
|
|
csrf_mcycle_ehr_data_lat_0$wget[7:5] ;
|
|
assign csrf_frm_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd1 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd2) ;
|
|
|
|
// register csrf_fs_reg
|
|
assign csrf_fs_reg$D_IN =
|
|
MUX_csrf_fs_reg$write_1__SEL_1 ?
|
|
MUX_csrf_fs_reg$write_1__VAL_1 :
|
|
2'b11 ;
|
|
assign csrf_fs_reg$EN =
|
|
MUX_csrf_fs_reg$write_1__SEL_1 ||
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
|
|
NOT_IF_NOT_rob_deqPort_0_canDeq__4362_4363_OR__ETC___d14479 ;
|
|
|
|
// register csrf_ie_vec_0
|
|
assign csrf_ie_vec_0$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ;
|
|
assign csrf_ie_vec_0$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ;
|
|
|
|
// register csrf_ie_vec_1
|
|
assign csrf_ie_vec_1$D_IN =
|
|
MUX_csrf_ie_vec_1$write_1__SEL_1 &&
|
|
MUX_csrf_ie_vec_1$write_1__VAL_1 ;
|
|
assign csrf_ie_vec_1$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ;
|
|
|
|
// register csrf_ie_vec_3
|
|
assign csrf_ie_vec_3$D_IN =
|
|
MUX_csrf_ie_vec_3$write_1__SEL_1 &&
|
|
MUX_csrf_ie_vec_3$write_1__VAL_1 ;
|
|
assign csrf_ie_vec_3$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ;
|
|
|
|
// register csrf_mcause_code_reg
|
|
assign csrf_mcause_code_reg$D_IN =
|
|
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
|
|
cause_code__h689130 :
|
|
csrf_mcycle_ehr_data_lat_0$wget[3:0] ;
|
|
assign csrf_mcause_code_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd27 ;
|
|
|
|
// register csrf_mcause_interrupt_reg
|
|
assign csrf_mcause_interrupt_reg$D_IN =
|
|
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
|
|
commitStage_commitTrap[4] :
|
|
csrf_mcycle_ehr_data_lat_0$wget[63] ;
|
|
assign csrf_mcause_interrupt_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd27 ;
|
|
|
|
// register csrf_mcounteren_cy_reg
|
|
assign csrf_mcounteren_cy_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[0] ;
|
|
assign csrf_mcounteren_cy_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd24 ;
|
|
|
|
// register csrf_mcounteren_ir_reg
|
|
assign csrf_mcounteren_ir_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[2] ;
|
|
assign csrf_mcounteren_ir_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd24 ;
|
|
|
|
// register csrf_mcounteren_tm_reg
|
|
assign csrf_mcounteren_tm_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1] ;
|
|
assign csrf_mcounteren_tm_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd24 ;
|
|
|
|
// register csrf_mcycle_ehr_data_rl
|
|
assign csrf_mcycle_ehr_data_rl$D_IN = upd__h4955 ;
|
|
assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ;
|
|
|
|
// register csrf_medeleg_13_11_reg
|
|
assign csrf_medeleg_13_11_reg$D_IN =
|
|
csrf_mcycle_ehr_data_lat_0$wget[13:11] ;
|
|
assign csrf_medeleg_13_11_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd20 ;
|
|
|
|
// register csrf_medeleg_15_reg
|
|
assign csrf_medeleg_15_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[15] ;
|
|
assign csrf_medeleg_15_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd20 ;
|
|
|
|
// register csrf_medeleg_9_0_reg
|
|
assign csrf_medeleg_9_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:0] ;
|
|
assign csrf_medeleg_9_0_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd20 ;
|
|
|
|
// register csrf_mepc_csr
|
|
assign csrf_mepc_csr$D_IN =
|
|
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
|
|
commitStage_commitTrap[132:69] :
|
|
rob$deqPort_0_deq_data[95:32] ;
|
|
assign csrf_mepc_csr$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd26 ;
|
|
|
|
// register csrf_mideleg_11_reg
|
|
assign csrf_mideleg_11_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[11] ;
|
|
assign csrf_mideleg_11_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd21 ;
|
|
|
|
// register csrf_mideleg_1_0_reg
|
|
assign csrf_mideleg_1_0_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[1:0] ;
|
|
assign csrf_mideleg_1_0_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd21 ;
|
|
|
|
// register csrf_mideleg_5_3_reg
|
|
assign csrf_mideleg_5_3_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[5:3] ;
|
|
assign csrf_mideleg_5_3_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd21 ;
|
|
|
|
// register csrf_mideleg_9_7_reg
|
|
assign csrf_mideleg_9_7_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[9:7] ;
|
|
assign csrf_mideleg_9_7_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd21 ;
|
|
|
|
// register csrf_minstret_ehr_data_rl
|
|
assign csrf_minstret_ehr_data_rl$D_IN =
|
|
csrf_minstret_ehr_data_lat_1$whas ?
|
|
upd__h3638 :
|
|
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ;
|
|
assign csrf_minstret_ehr_data_rl$EN = 1'd1 ;
|
|
|
|
// register csrf_mpp_reg
|
|
assign csrf_mpp_reg$D_IN =
|
|
MUX_csrf_mpp_reg$write_1__SEL_1 ?
|
|
MUX_csrf_mpp_reg$write_1__VAL_1 :
|
|
csrf_prv_reg ;
|
|
assign csrf_mpp_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ;
|
|
|
|
// register csrf_mprv_reg
|
|
assign csrf_mprv_reg$D_IN = csrf_mcycle_ehr_data_lat_0$wget[17] ;
|
|
assign csrf_mprv_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18 ;
|
|
|
|
// register csrf_mscratch_csr
|
|
assign csrf_mscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ;
|
|
assign csrf_mscratch_csr$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd25 ;
|
|
|
|
// register csrf_mtval_csr
|
|
assign csrf_mtval_csr$D_IN =
|
|
MUX_csrf_ie_vec_3$write_1__SEL_2 ?
|
|
MUX_csrf_mtval_csr$write_1__VAL_1 :
|
|
rob$deqPort_0_deq_data[95:32] ;
|
|
assign csrf_mtval_csr$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd28 ;
|
|
|
|
// register csrf_mtvec_base_hi_reg
|
|
assign csrf_mtvec_base_hi_reg$D_IN = csrf_mscratch_csr$D_IN[63:2] ;
|
|
assign csrf_mtvec_base_hi_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd23 ;
|
|
|
|
// register csrf_mtvec_mode_low_reg
|
|
assign csrf_mtvec_mode_low_reg$D_IN = csrf_mscratch_csr$D_IN[0] ;
|
|
assign csrf_mtvec_mode_low_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd23 ;
|
|
|
|
// register csrf_mxr_reg
|
|
assign csrf_mxr_reg$D_IN = csrf_mscratch_csr$D_IN[19] ;
|
|
assign csrf_mxr_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ;
|
|
|
|
// register csrf_ppn_reg
|
|
assign csrf_ppn_reg$D_IN = csrf_mscratch_csr$D_IN[43:0] ;
|
|
assign csrf_ppn_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd17 ;
|
|
|
|
// register csrf_prev_ie_vec_0
|
|
assign csrf_prev_ie_vec_0$D_IN = csrf_mscratch_csr$D_IN[4] ;
|
|
assign csrf_prev_ie_vec_0$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ;
|
|
|
|
// register csrf_prev_ie_vec_1
|
|
assign csrf_prev_ie_vec_1$D_IN =
|
|
MUX_csrf_prev_ie_vec_1$write_1__SEL_1 ?
|
|
MUX_csrf_prev_ie_vec_1$write_1__VAL_1 :
|
|
csrf_ie_vec_1 ;
|
|
assign csrf_prev_ie_vec_1$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ;
|
|
|
|
// register csrf_prev_ie_vec_3
|
|
assign csrf_prev_ie_vec_3$D_IN =
|
|
MUX_csrf_prev_ie_vec_3$write_1__SEL_1 ?
|
|
MUX_csrf_prev_ie_vec_3$write_1__VAL_1 :
|
|
csrf_ie_vec_3 ;
|
|
assign csrf_prev_ie_vec_3$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo20 ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 ;
|
|
|
|
// register csrf_prv_reg
|
|
assign csrf_prv_reg$D_IN =
|
|
MUX_csrf_prv_reg$write_1__SEL_1 ?
|
|
MUX_csrf_prv_reg$write_1__VAL_1 :
|
|
MUX_csrf_prv_reg$write_1__VAL_2 ;
|
|
assign csrf_prv_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd20) ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
|
|
|
|
// register csrf_scause_code_reg
|
|
assign csrf_scause_code_reg$D_IN =
|
|
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
|
|
cause_code__h689130 :
|
|
csrf_mscratch_csr$D_IN[3:0] ;
|
|
assign csrf_scause_code_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd14 ;
|
|
|
|
// register csrf_scause_interrupt_reg
|
|
assign csrf_scause_interrupt_reg$D_IN =
|
|
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
|
|
commitStage_commitTrap[4] :
|
|
csrf_mscratch_csr$D_IN[63] ;
|
|
assign csrf_scause_interrupt_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd14 ;
|
|
|
|
// register csrf_scounteren_cy_reg
|
|
assign csrf_scounteren_cy_reg$D_IN = csrf_mscratch_csr$D_IN[0] ;
|
|
assign csrf_scounteren_cy_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd11 ;
|
|
|
|
// register csrf_scounteren_ir_reg
|
|
assign csrf_scounteren_ir_reg$D_IN = csrf_mscratch_csr$D_IN[2] ;
|
|
assign csrf_scounteren_ir_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd11 ;
|
|
|
|
// register csrf_scounteren_tm_reg
|
|
assign csrf_scounteren_tm_reg$D_IN = csrf_mscratch_csr$D_IN[1] ;
|
|
assign csrf_scounteren_tm_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd11 ;
|
|
|
|
// register csrf_sepc_csr
|
|
assign csrf_sepc_csr$D_IN =
|
|
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
|
|
commitStage_commitTrap[132:69] :
|
|
rob$deqPort_0_deq_data[95:32] ;
|
|
assign csrf_sepc_csr$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd13 ;
|
|
|
|
// register csrf_software_int_en_vec_0
|
|
assign csrf_software_int_en_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ;
|
|
assign csrf_software_int_en_vec_0$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd9 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22) ;
|
|
|
|
// register csrf_software_int_en_vec_1
|
|
assign csrf_software_int_en_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ;
|
|
assign csrf_software_int_en_vec_1$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd9 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22) ;
|
|
|
|
// register csrf_software_int_en_vec_3
|
|
assign csrf_software_int_en_vec_3$D_IN = csrf_mscratch_csr$D_IN[3] ;
|
|
assign csrf_software_int_en_vec_3$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22 ;
|
|
|
|
// register csrf_software_int_pend_vec_0
|
|
assign csrf_software_int_pend_vec_0$D_IN = csrf_mscratch_csr$D_IN[0] ;
|
|
assign csrf_software_int_pend_vec_0$EN =
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
|
|
|
|
// register csrf_software_int_pend_vec_1
|
|
assign csrf_software_int_pend_vec_1$D_IN = csrf_mscratch_csr$D_IN[1] ;
|
|
assign csrf_software_int_pend_vec_1$EN =
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
|
|
|
|
// register csrf_software_int_pend_vec_3
|
|
assign csrf_software_int_pend_vec_3$D_IN =
|
|
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 ?
|
|
csrf_mscratch_csr$D_IN[3] :
|
|
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 ;
|
|
assign csrf_software_int_pend_vec_3$EN =
|
|
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
|
|
mmio_pRqQ_data_0[37:36] != 2'd0 &&
|
|
mmio_pRqQ_data_0[37:36] != 2'd1 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd29 ;
|
|
|
|
// register csrf_spp_reg
|
|
assign csrf_spp_reg$D_IN =
|
|
MUX_csrf_spp_reg$write_1__SEL_1 ?
|
|
MUX_csrf_spp_reg$write_1__VAL_1 :
|
|
csrf_prv_reg[0] ;
|
|
assign csrf_spp_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo28 ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ;
|
|
|
|
// register csrf_sscratch_csr
|
|
assign csrf_sscratch_csr$D_IN = rob$deqPort_0_deq_data[95:32] ;
|
|
assign csrf_sscratch_csr$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd12 ;
|
|
|
|
// register csrf_stats_module_doStats
|
|
assign csrf_stats_module_doStats$D_IN = recvDoStats_x ;
|
|
assign csrf_stats_module_doStats$EN = EN_recvDoStats ;
|
|
|
|
// register csrf_stval_csr
|
|
assign csrf_stval_csr$D_IN =
|
|
MUX_csrf_ie_vec_1$write_1__SEL_2 ?
|
|
MUX_csrf_mtval_csr$write_1__VAL_1 :
|
|
rob$deqPort_0_deq_data[95:32] ;
|
|
assign csrf_stval_csr$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd15 ;
|
|
|
|
// register csrf_stvec_base_hi_reg
|
|
assign csrf_stvec_base_hi_reg$D_IN = csrf_sscratch_csr$D_IN[63:2] ;
|
|
assign csrf_stvec_base_hi_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd10 ;
|
|
|
|
// register csrf_stvec_mode_low_reg
|
|
assign csrf_stvec_mode_low_reg$D_IN = csrf_sscratch_csr$D_IN[0] ;
|
|
assign csrf_stvec_mode_low_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd10 ;
|
|
|
|
// register csrf_sum_reg
|
|
assign csrf_sum_reg$D_IN = csrf_sscratch_csr$D_IN[18] ;
|
|
assign csrf_sum_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ;
|
|
|
|
// register csrf_time_reg
|
|
assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ;
|
|
assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ;
|
|
|
|
// register csrf_timer_int_en_vec_0
|
|
assign csrf_timer_int_en_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ;
|
|
assign csrf_timer_int_en_vec_0$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd9 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22) ;
|
|
|
|
// register csrf_timer_int_en_vec_1
|
|
assign csrf_timer_int_en_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ;
|
|
assign csrf_timer_int_en_vec_1$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd9 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22) ;
|
|
|
|
// register csrf_timer_int_en_vec_3
|
|
assign csrf_timer_int_en_vec_3$D_IN = csrf_sscratch_csr$D_IN[7] ;
|
|
assign csrf_timer_int_en_vec_3$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd22 ;
|
|
|
|
// register csrf_timer_int_pend_vec_0
|
|
assign csrf_timer_int_pend_vec_0$D_IN = csrf_sscratch_csr$D_IN[4] ;
|
|
assign csrf_timer_int_pend_vec_0$EN =
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
|
|
|
|
// register csrf_timer_int_pend_vec_1
|
|
assign csrf_timer_int_pend_vec_1$D_IN = csrf_sscratch_csr$D_IN[5] ;
|
|
assign csrf_timer_int_pend_vec_1$EN =
|
|
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ;
|
|
|
|
// register csrf_timer_int_pend_vec_3
|
|
assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ;
|
|
assign csrf_timer_int_pend_vec_3$EN =
|
|
WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
|
|
mmio_pRqQ_data_0[37:36] == 2'd2 ;
|
|
|
|
// register csrf_tsr_reg
|
|
assign csrf_tsr_reg$D_IN = csrf_sscratch_csr$D_IN[22] ;
|
|
assign csrf_tsr_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18 ;
|
|
|
|
// register csrf_tvm_reg
|
|
assign csrf_tvm_reg$D_IN = csrf_sscratch_csr$D_IN[20] ;
|
|
assign csrf_tvm_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18 ;
|
|
|
|
// register csrf_tw_reg
|
|
assign csrf_tw_reg$D_IN = csrf_sscratch_csr$D_IN[21] ;
|
|
assign csrf_tw_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18 ;
|
|
|
|
// register csrf_vm_mode_sv39_reg
|
|
assign csrf_vm_mode_sv39_reg$D_IN = csrf_sscratch_csr$D_IN[63] ;
|
|
assign csrf_vm_mode_sv39_reg$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd17 ;
|
|
|
|
// register flush_reservation
|
|
assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_1 ;
|
|
assign flush_reservation$EN =
|
|
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
|
|
|
|
// register flush_tlbs
|
|
assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ;
|
|
assign flush_tlbs$EN =
|
|
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
(rob$deqPort_0_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd17) ;
|
|
|
|
// register mmio_cRqQ_clearReq_rl
|
|
assign mmio_cRqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_cRqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_cRqQ_data_0
|
|
assign mmio_cRqQ_data_0$D_IN =
|
|
{ x__h45545,
|
|
(mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
|
|
mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ?
|
|
{ 5'd2,
|
|
mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[72] :
|
|
mmio_cRqQ_enqReq_rl[72] } :
|
|
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
|
|
mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[71:64] :
|
|
mmio_cRqQ_enqReq_rl[71:64],
|
|
x__h48081 } ;
|
|
assign mmio_cRqQ_data_0$EN =
|
|
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
|
|
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ;
|
|
|
|
// register mmio_cRqQ_deqReq_rl
|
|
assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_cRqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_cRqQ_empty
|
|
assign mmio_cRqQ_empty$D_IN =
|
|
mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl ||
|
|
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ;
|
|
assign mmio_cRqQ_empty$EN = 1'd1 ;
|
|
|
|
// register mmio_cRqQ_enqReq_rl
|
|
assign mmio_cRqQ_enqReq_rl$D_IN =
|
|
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_cRqQ_full
|
|
assign mmio_cRqQ_full$D_IN =
|
|
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
|
|
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ;
|
|
assign mmio_cRqQ_full$EN = 1'd1 ;
|
|
|
|
// register mmio_cRsQ_clearReq_rl
|
|
assign mmio_cRsQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_cRsQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_cRsQ_data_0
|
|
assign mmio_cRsQ_data_0$D_IN =
|
|
CAN_FIRE_RL_mmio_handlePRq ?
|
|
mmio_cRsQ_enqReq_lat_0$wget[0] :
|
|
mmio_cRsQ_enqReq_rl[0] ;
|
|
assign mmio_cRsQ_data_0$EN =
|
|
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
|
|
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ;
|
|
|
|
// register mmio_cRsQ_deqReq_rl
|
|
assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_cRsQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_cRsQ_empty
|
|
assign mmio_cRsQ_empty$D_IN =
|
|
mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl ||
|
|
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ;
|
|
assign mmio_cRsQ_empty$EN = 1'd1 ;
|
|
|
|
// register mmio_cRsQ_enqReq_rl
|
|
assign mmio_cRsQ_enqReq_rl$D_IN = 2'b0 ;
|
|
assign mmio_cRsQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_cRsQ_full
|
|
assign mmio_cRsQ_full$D_IN =
|
|
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
|
|
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ;
|
|
assign mmio_cRsQ_full$EN = 1'd1 ;
|
|
|
|
// register mmio_dataPendQ_clearReq_rl
|
|
assign mmio_dataPendQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_dataPendQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataPendQ_deqReq_rl
|
|
assign mmio_dataPendQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_dataPendQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataPendQ_empty
|
|
assign mmio_dataPendQ_empty$D_IN =
|
|
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT &&
|
|
mmio_dataPendQ_clearReq_rl ||
|
|
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ;
|
|
assign mmio_dataPendQ_empty$EN = 1'd1 ;
|
|
|
|
// register mmio_dataPendQ_enqReq_rl
|
|
assign mmio_dataPendQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_dataPendQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataPendQ_full
|
|
assign mmio_dataPendQ_full$D_IN =
|
|
(!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT ||
|
|
!mmio_dataPendQ_clearReq_rl) &&
|
|
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ;
|
|
assign mmio_dataPendQ_full$EN = 1'd1 ;
|
|
|
|
// register mmio_dataReqQ_clearReq_rl
|
|
assign mmio_dataReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_dataReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataReqQ_data_0
|
|
assign mmio_dataReqQ_data_0$D_IN =
|
|
{ x__h17638,
|
|
(mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
|
|
mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ?
|
|
{ 5'd2,
|
|
mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[72] :
|
|
mmio_dataReqQ_enqReq_rl[72] } :
|
|
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
|
|
mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[71:64] :
|
|
mmio_dataReqQ_enqReq_rl[71:64],
|
|
x__h20176 } ;
|
|
assign mmio_dataReqQ_data_0$EN =
|
|
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
|
|
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ;
|
|
|
|
// register mmio_dataReqQ_deqReq_rl
|
|
assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_dataReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataReqQ_empty
|
|
assign mmio_dataReqQ_empty$D_IN =
|
|
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT &&
|
|
mmio_dataReqQ_clearReq_rl ||
|
|
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ;
|
|
assign mmio_dataReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register mmio_dataReqQ_enqReq_rl
|
|
assign mmio_dataReqQ_enqReq_rl$D_IN =
|
|
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataReqQ_full
|
|
assign mmio_dataReqQ_full$D_IN =
|
|
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
|
|
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ;
|
|
assign mmio_dataReqQ_full$EN = 1'd1 ;
|
|
|
|
// register mmio_dataRespQ_clearReq_rl
|
|
assign mmio_dataRespQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_dataRespQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataRespQ_data_0
|
|
assign mmio_dataRespQ_data_0$D_IN =
|
|
CAN_FIRE_RL_mmio_sendDataResp ?
|
|
mmio_dataRespQ_enqReq_lat_0$wget[64:0] :
|
|
mmio_dataRespQ_enqReq_rl[64:0] ;
|
|
assign mmio_dataRespQ_data_0$EN =
|
|
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
|
|
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ;
|
|
|
|
// register mmio_dataRespQ_deqReq_rl
|
|
assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_dataRespQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataRespQ_empty
|
|
assign mmio_dataRespQ_empty$D_IN =
|
|
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT &&
|
|
mmio_dataRespQ_clearReq_rl ||
|
|
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ;
|
|
assign mmio_dataRespQ_empty$EN = 1'd1 ;
|
|
|
|
// register mmio_dataRespQ_enqReq_rl
|
|
assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
|
|
assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_dataRespQ_full
|
|
assign mmio_dataRespQ_full$D_IN =
|
|
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
|
|
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ;
|
|
assign mmio_dataRespQ_full$EN = 1'd1 ;
|
|
|
|
// register mmio_fromHostAddr
|
|
assign mmio_fromHostAddr$D_IN = coreReq_start_fromHostAddr[63:3] ;
|
|
assign mmio_fromHostAddr$EN = EN_coreReq_start ;
|
|
|
|
// register mmio_pRqQ_clearReq_rl
|
|
assign mmio_pRqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_pRqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_pRqQ_data_0
|
|
assign mmio_pRqQ_data_0$D_IN =
|
|
{ EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[38] :
|
|
mmio_pRqQ_enqReq_rl[38],
|
|
(EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd0 :
|
|
mmio_pRqQ_enqReq_rl[37:36] == 2'd0) ?
|
|
{ 5'd2,
|
|
EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[32] :
|
|
mmio_pRqQ_enqReq_rl[32] } :
|
|
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
|
|
x_data__h65339 } ;
|
|
assign mmio_pRqQ_data_0$EN =
|
|
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
|
|
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ;
|
|
|
|
// register mmio_pRqQ_deqReq_rl
|
|
assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_pRqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_pRqQ_empty
|
|
assign mmio_pRqQ_empty$D_IN =
|
|
mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl ||
|
|
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ;
|
|
assign mmio_pRqQ_empty$EN = 1'd1 ;
|
|
|
|
// register mmio_pRqQ_enqReq_rl
|
|
assign mmio_pRqQ_enqReq_rl$D_IN = 40'h2AAAAAAAAA ;
|
|
assign mmio_pRqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_pRqQ_full
|
|
assign mmio_pRqQ_full$D_IN =
|
|
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
|
|
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ;
|
|
assign mmio_pRqQ_full$EN = 1'd1 ;
|
|
|
|
// register mmio_pRsQ_clearReq_rl
|
|
assign mmio_pRsQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_pRsQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_pRsQ_data_0
|
|
assign mmio_pRsQ_data_0$D_IN =
|
|
{ EN_mmioToPlatform_pRs_enq ?
|
|
mmio_pRsQ_enqReq_lat_0$wget[66] :
|
|
mmio_pRsQ_enqReq_rl[66],
|
|
IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ;
|
|
assign mmio_pRsQ_data_0$EN =
|
|
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
|
|
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ;
|
|
|
|
// register mmio_pRsQ_deqReq_rl
|
|
assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign mmio_pRsQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_pRsQ_empty
|
|
assign mmio_pRsQ_empty$D_IN =
|
|
mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl ||
|
|
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ;
|
|
assign mmio_pRsQ_empty$EN = 1'd1 ;
|
|
|
|
// register mmio_pRsQ_enqReq_rl
|
|
assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ;
|
|
assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register mmio_pRsQ_full
|
|
assign mmio_pRsQ_full$D_IN =
|
|
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
|
|
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ;
|
|
assign mmio_pRsQ_full$EN = 1'd1 ;
|
|
|
|
// register mmio_toHostAddr
|
|
assign mmio_toHostAddr$D_IN = coreReq_start_toHostAddr[63:3] ;
|
|
assign mmio_toHostAddr$EN = EN_coreReq_start ;
|
|
|
|
// register outOfReset
|
|
assign outOfReset$D_IN = 1'd1 ;
|
|
assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ;
|
|
|
|
// register started
|
|
assign started$D_IN = 1'd1 ;
|
|
assign started$EN = EN_coreReq_start ;
|
|
|
|
// register update_vm_info
|
|
assign update_vm_info$D_IN = !MUX_update_vm_info$write_1__SEL_1 ;
|
|
assign update_vm_info$EN =
|
|
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
|
|
|
|
// submodule coreFix_aluExe_0_dispToRegQ
|
|
assign coreFix_aluExe_0_dispToRegQ$enq_x =
|
|
{ coreFix_aluExe_0_rsAlu$dispatchData[161:157],
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267,
|
|
coreFix_aluExe_0_rsAlu$dispatchData[135],
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268,
|
|
coreFix_aluExe_0_rsAlu$dispatchData[122:90],
|
|
coreFix_aluExe_0_rsAlu$dispatchData[65:21],
|
|
coreFix_aluExe_0_rsAlu$dispatchData[89:66],
|
|
coreFix_aluExe_0_rsAlu$dispatchData[8:4],
|
|
coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ;
|
|
assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
|
|
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
|
|
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_0_dispToRegQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
|
|
assign coreFix_aluExe_0_dispToRegQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
|
|
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_aluExe_0_exeToFinQ
|
|
assign coreFix_aluExe_0_exeToFinQ$enq_x =
|
|
{ coreFix_aluExe_0_regToExeQ$first[389:385],
|
|
coreFix_aluExe_0_regToExeQ$first[317:273],
|
|
basicExec___d12459[321:258],
|
|
coreFix_aluExe_0_regToExeQ$first[363],
|
|
basicExec___d12459[257:194],
|
|
basicExec___d12459[129:0],
|
|
coreFix_aluExe_0_regToExeQ$first[16:0] } ;
|
|
assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_0_exeToFinQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
|
|
assign coreFix_aluExe_0_exeToFinQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_aluExe_0_regToExeQ
|
|
assign coreFix_aluExe_0_regToExeQ$enq_x =
|
|
{ coreFix_aluExe_0_dispToRegQ$first[157:153],
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270,
|
|
coreFix_aluExe_0_dispToRegQ$first[131],
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271,
|
|
coreFix_aluExe_0_dispToRegQ$first[118:86],
|
|
coreFix_aluExe_0_dispToRegQ$first[61:17],
|
|
x__h634046,
|
|
x__h634047,
|
|
rob$getOrigPC_0_get,
|
|
rob$getOrigPredPC_0_get,
|
|
coreFix_aluExe_0_dispToRegQ$first[16:0] } ;
|
|
assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_0_regToExeQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
|
|
assign coreFix_aluExe_0_regToExeQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
|
|
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_aluExe_0_rsAlu
|
|
assign coreFix_aluExe_0_rsAlu$enq_x =
|
|
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 ?
|
|
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 :
|
|
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 ;
|
|
assign coreFix_aluExe_0_rsAlu$setRegReady_0_put =
|
|
{ 1'd1, coreFix_aluExe_0_rsAlu$dispatchData[40:34] } ;
|
|
assign coreFix_aluExe_0_rsAlu$setRegReady_1_put =
|
|
{ 1'd1, coreFix_aluExe_1_rsAlu$dispatchData[40:34] } ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
|
|
default: coreFix_aluExe_0_rsAlu$setRegReady_2_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_0_rsAlu$setRegReady_3_put =
|
|
{ 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
|
|
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
default: coreFix_aluExe_0_rsAlu$setRegReady_4_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
|
|
assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_0_rsAlu$EN_enq =
|
|
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd0 ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_doDispatch =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
|
|
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
|
|
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
|
|
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
|
|
coreFix_memExe_lsq$issueLd[72] ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put =
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_aluExe_1_dispToRegQ
|
|
assign coreFix_aluExe_1_dispToRegQ$enq_x =
|
|
{ coreFix_aluExe_1_rsAlu$dispatchData[161:157],
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273,
|
|
coreFix_aluExe_1_rsAlu$dispatchData[135],
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274,
|
|
coreFix_aluExe_1_rsAlu$dispatchData[122:90],
|
|
coreFix_aluExe_1_rsAlu$dispatchData[65:21],
|
|
coreFix_aluExe_1_rsAlu$dispatchData[89:66],
|
|
coreFix_aluExe_1_rsAlu$dispatchData[8:4],
|
|
coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ;
|
|
assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_1_dispToRegQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
|
|
assign coreFix_aluExe_1_dispToRegQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
|
|
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_aluExe_1_exeToFinQ
|
|
assign coreFix_aluExe_1_exeToFinQ$enq_x =
|
|
{ coreFix_aluExe_1_regToExeQ$first[389:385],
|
|
coreFix_aluExe_1_regToExeQ$first[317:273],
|
|
basicExec___d11852[321:258],
|
|
coreFix_aluExe_1_regToExeQ$first[363],
|
|
basicExec___d11852[257:194],
|
|
basicExec___d11852[129:0],
|
|
coreFix_aluExe_1_regToExeQ$first[16:0] } ;
|
|
assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_1_exeToFinQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
|
|
assign coreFix_aluExe_1_exeToFinQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_aluExe_1_regToExeQ
|
|
assign coreFix_aluExe_1_regToExeQ$enq_x =
|
|
{ coreFix_aluExe_1_dispToRegQ$first[157:153],
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276,
|
|
coreFix_aluExe_1_dispToRegQ$first[131],
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277,
|
|
coreFix_aluExe_1_dispToRegQ$first[118:86],
|
|
coreFix_aluExe_1_dispToRegQ$first[61:17],
|
|
x__h612962,
|
|
x__h612963,
|
|
rob$getOrigPC_1_get,
|
|
rob$getOrigPredPC_1_get,
|
|
coreFix_aluExe_1_dispToRegQ$first[16:0] } ;
|
|
assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_1_regToExeQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
|
|
assign coreFix_aluExe_1_regToExeQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
|
|
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_aluExe_1_rsAlu
|
|
assign coreFix_aluExe_1_rsAlu$enq_x =
|
|
(k__h659336 == 1'd1 &&
|
|
fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13710) ?
|
|
{ fetchStage$pipelines_0_first[103:99],
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721,
|
|
fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
fetchStage$pipelines_0_first[64:32],
|
|
fetchStage$pipelines_0_first[159:136],
|
|
regRenamingTable$rename_0_getRename,
|
|
rob$enqPort_0_getEnqInstTag,
|
|
specTagManager$currentSpecBits,
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_0_get } :
|
|
{ fetchStage$pipelines_1_first[103:99],
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275,
|
|
fetchStage_pipelines_1_first__2604_BIT_77_3276_ETC___d13351,
|
|
fetchStage$pipelines_1_first[64:32],
|
|
fetchStage$pipelines_1_first[159:136],
|
|
regRenamingTable$rename_1_getRename,
|
|
rob$enqPort_1_getEnqInstTag,
|
|
renaming_spec_bits__h672935,
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_1_get } ;
|
|
assign coreFix_aluExe_1_rsAlu$setRegReady_0_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
|
|
assign coreFix_aluExe_1_rsAlu$setRegReady_1_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
|
|
default: coreFix_aluExe_1_rsAlu$setRegReady_2_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_1_rsAlu$setRegReady_3_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
|
|
always@(MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
|
|
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
|
|
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
|
|
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
default: coreFix_aluExe_1_rsAlu$setRegReady_4_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
|
|
assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_aluExe_1_rsAlu$EN_enq =
|
|
WILL_FIRE_RL_renameStage_doRenaming && _dfoo16 ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_doDispatch =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
|
|
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
|
|
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
|
|
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
|
|
coreFix_memExe_lsq$issueLd[72] ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put =
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
|
|
assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x =
|
|
{ CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ;
|
|
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
|
|
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
|
|
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x =
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[225],
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10828,
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10864,
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10912,
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10954,
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10996,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put =
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10630,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 } ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9925,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280,
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 } ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put =
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 } ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x =
|
|
{ execFpuSimple___d11030,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd25 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd26 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd27 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
|
|
_theResult___fst__h600208 :
|
|
a__h599786 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser =
|
|
{ b__h599787 == 64'd0,
|
|
a__h599786,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0,
|
|
x__h600222,
|
|
a__h599786[63],
|
|
8'd0 } ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
|
|
_theResult___snd__h600209 :
|
|
b__h599787 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h599786 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h599787 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A =
|
|
a__h599786 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B =
|
|
b__h599787 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A =
|
|
a__h599786 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B =
|
|
b__h599787 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
|
|
always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[1:0])
|
|
2'd0:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
|
|
2'd1:
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
|
|
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[2] ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR = 1'b0 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_regToExeQ
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x =
|
|
{ CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12],
|
|
x__h478817,
|
|
x__h478818,
|
|
x__h478819,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq =
|
|
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13722) ?
|
|
{ IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721,
|
|
regRenamingTable$rename_0_getRename,
|
|
rob$enqPort_0_getEnqInstTag,
|
|
specTagManager$currentSpecBits,
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_0_get } :
|
|
{ IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275,
|
|
regRenamingTable$rename_1_getRename,
|
|
rob$enqPort_1_getEnqInstTag,
|
|
renaming_spec_bits__h672935,
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_1_get } ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
|
|
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
|
|
always@(MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
|
|
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
|
|
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13722 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
regRenamingTable_rename_1_canRename__3221_AND__ETC___d13850) ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
|
|
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
|
|
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
|
|
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
|
|
coreFix_memExe_lsq$issueLd[72] ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put =
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r =
|
|
{ x__h284446,
|
|
x__h284458,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2781,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2789,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2802,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2811,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2820,
|
|
x__h286312,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2828,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2832,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836,
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840 } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n =
|
|
x__h283013 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
|
|
2'd0) ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] :
|
|
3'd0) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n =
|
|
3'h0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
|
|
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1:
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574];
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512];
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157];
|
|
default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
|
|
3'b010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
|
|
2'd3,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 :
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 :
|
|
3'd3 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n =
|
|
3'h0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55],
|
|
55'h15555555555555 } ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2591 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd4 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
|
|
3'd1) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
|
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assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN =
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1'd1 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN =
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1'b0 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN =
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1'b0 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN =
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1'd1 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN =
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coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN =
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1'b0 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN =
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1'b0 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN =
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1'd1 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN =
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EN_dCacheToParent_fromP_enq ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN =
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1'b0 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN =
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1'b0 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN =
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1'd1 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
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assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN =
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
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coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2574 ||
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
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(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
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3'd2 ||
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coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
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3'd3) ||
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
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coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2719 &&
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coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
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2'd0 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
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assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN =
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1'd1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN =
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MUX_flush_reservation$write_1__SEL_1 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r =
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{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2867,
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CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284 } ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n =
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n =
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2'h0 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n =
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d =
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{ !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
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2'd3,
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n =
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n =
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coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n =
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coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n =
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coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit =
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CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
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CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry =
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
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(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
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coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689 ||
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!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692) ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ;
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assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ;
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// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
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always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
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coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
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coreFix_memExe_dMem_cache_m_banks_0_processAmo or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq)
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begin
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case (1'b1) // synopsys parallel_case
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1;
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MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
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coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc;
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
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coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0];
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq = 4'd2;
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default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
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4'b1010 /* unspecified value */ ;
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endcase
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end
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always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
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begin
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case (1'b1) // synopsys parallel_case
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1;
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
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1'd0;
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MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 ||
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
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1'd1;
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default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
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1'b0 /* unspecified value */ ;
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endcase
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end
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always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4)
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begin
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case (1'b1) // synopsys parallel_case
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1;
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MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2;
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3;
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
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default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
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570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
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endcase
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end
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always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new or
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer or
|
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 or
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer or
|
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4)
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begin
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case (1'b1) // synopsys parallel_case
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1;
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new:
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2;
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer:
|
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
|
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3;
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer:
|
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coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
|
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
|
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default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
|
|
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send =
|
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WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite =
|
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MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd4 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2647) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN =
|
|
EN_dCacheToParent_rqToP_deq ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN =
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ?
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 :
|
|
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2658 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN =
|
|
EN_dCacheToParent_rsToP_deq ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN =
|
|
1'b0 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN =
|
|
1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN =
|
|
1'd1 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN =
|
|
1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
|
|
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
|
|
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_dTlb
|
|
assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ;
|
|
assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ;
|
|
assign coreFix_memExe_dTlb$procReq_req =
|
|
{ coreFix_memExe_regToExeQ$first[192:190],
|
|
coreFix_memExe_regToExeQ$first[157:140],
|
|
coreFix_memExe_lsq$getOrigBE << vaddr__h180473[2:0],
|
|
vaddr__h180473,
|
|
coreFix_memExe_lsq$getOrigBE[7] ?
|
|
vaddr__h180473[2:0] != 3'd0 :
|
|
(coreFix_memExe_lsq$getOrigBE[3] ?
|
|
vaddr__h180473[1:0] != 2'd0 :
|
|
coreFix_memExe_lsq$getOrigBE[1] && vaddr__h180473[0]),
|
|
coreFix_memExe_regToExeQ$first[11:0] } ;
|
|
assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x =
|
|
{ l2Tlb$toChildren_rsToC_first[80:0],
|
|
l2Tlb$toChildren_rsToC_first[82:81] } ;
|
|
assign coreFix_memExe_dTlb$updateVMInfo_vm =
|
|
{ prv__h703579,
|
|
prv__h703579 != 2'd3 && csrf_vm_mode_sv39_reg,
|
|
csrf_mxr_reg,
|
|
csrf_sum_reg,
|
|
csrf_ppn_reg } ;
|
|
assign coreFix_memExe_dTlb$EN_flush = MUX_flush_tlbs$write_1__SEL_1 ;
|
|
assign coreFix_memExe_dTlb$EN_updateVMInfo =
|
|
MUX_update_vm_info$write_1__SEL_1 ;
|
|
assign coreFix_memExe_dTlb$EN_procReq =
|
|
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
|
|
assign coreFix_memExe_dTlb$EN_deqProcResp =
|
|
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
|
|
assign coreFix_memExe_dTlb$EN_toParent_rqToP_deq = CAN_FIRE_RL_sendDTlbReq ;
|
|
assign coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq =
|
|
CAN_FIRE_RL_sendRsToDTlb ;
|
|
assign coreFix_memExe_dTlb$EN_toParent_flush_request_get =
|
|
CAN_FIRE_RL_mkConnectionGetPut ;
|
|
assign coreFix_memExe_dTlb$EN_toParent_flush_response_put =
|
|
CAN_FIRE_RL_sendFlushDone ;
|
|
assign coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
assign coreFix_memExe_dTlb$EN_perf_setStatus = 1'b0 ;
|
|
assign coreFix_memExe_dTlb$EN_perf_req = 1'b0 ;
|
|
assign coreFix_memExe_dTlb$EN_perf_resp = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_dispToRegQ
|
|
assign coreFix_memExe_dispToRegQ$enq_x =
|
|
{ coreFix_memExe_rsMem$dispatchData[106:72],
|
|
coreFix_memExe_rsMem$dispatchData[65:21],
|
|
coreFix_memExe_rsMem$dispatchData[71:66],
|
|
coreFix_memExe_rsMem$dispatchData[20:9] } ;
|
|
assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_dispToRegQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
|
|
assign coreFix_memExe_dispToRegQ$EN_deq =
|
|
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
|
|
assign coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
|
|
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
|
|
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
|
|
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
|
|
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
|
|
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
|
|
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN =
|
|
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
|
|
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
|
|
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_lsq
|
|
assign coreFix_memExe_lsq$enqLd_dst =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13748) ?
|
|
regRenamingTable$rename_0_getRename[8:0] :
|
|
regRenamingTable$rename_1_getRename[8:0] ;
|
|
assign coreFix_memExe_lsq$enqLd_inst_tag =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13748) ?
|
|
rob$enqPort_0_getEnqInstTag :
|
|
rob$enqPort_1_getEnqInstTag ;
|
|
assign coreFix_memExe_lsq$enqLd_mem_inst =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13748) ?
|
|
fetchStage$pipelines_0_first[95:78] :
|
|
fetchStage$pipelines_1_first[95:78] ;
|
|
assign coreFix_memExe_lsq$enqLd_spec_bits =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13748) ?
|
|
specTagManager$currentSpecBits :
|
|
renaming_spec_bits__h672935 ;
|
|
assign coreFix_memExe_lsq$enqSt_dst =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13756) ?
|
|
regRenamingTable$rename_0_getRename[8:0] :
|
|
regRenamingTable$rename_1_getRename[8:0] ;
|
|
assign coreFix_memExe_lsq$enqSt_inst_tag =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13756) ?
|
|
rob$enqPort_0_getEnqInstTag :
|
|
rob$enqPort_1_getEnqInstTag ;
|
|
assign coreFix_memExe_lsq$enqSt_mem_inst =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13756) ?
|
|
fetchStage$pipelines_0_first[95:78] :
|
|
fetchStage$pipelines_1_first[95:78] ;
|
|
assign coreFix_memExe_lsq$enqSt_spec_bits =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13756) ?
|
|
specTagManager$currentSpecBits :
|
|
renaming_spec_bits__h672935 ;
|
|
assign coreFix_memExe_lsq$getHit_t =
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
|
|
MUX_coreFix_memExe_lsq$getHit_1__VAL_2 :
|
|
MUX_coreFix_memExe_lsq$getHit_1__VAL_2 ;
|
|
assign coreFix_memExe_lsq$getOrigBE_t =
|
|
coreFix_memExe_regToExeQ$first[145:140] ;
|
|
assign coreFix_memExe_lsq$issueLd_lsqTag =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
|
|
coreFix_memExe_lsq$getIssueLd[76:72] :
|
|
coreFix_memExe_issueLd$wget[76:72] ;
|
|
assign coreFix_memExe_lsq$issueLd_paddr =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
|
|
coreFix_memExe_lsq$getIssueLd[71:8] :
|
|
coreFix_memExe_issueLd$wget[71:8] ;
|
|
assign coreFix_memExe_lsq$issueLd_sbRes =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
|
|
MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 :
|
|
coreFix_memExe_stb$search ;
|
|
assign coreFix_memExe_lsq$issueLd_shiftedBE =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
|
|
coreFix_memExe_lsq$getIssueLd[7:0] :
|
|
coreFix_memExe_issueLd$wget[7:0] ;
|
|
assign coreFix_memExe_lsq$respLd_alignedData =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
|
|
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 :
|
|
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ;
|
|
assign coreFix_memExe_lsq$respLd_t =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
|
|
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 :
|
|
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ;
|
|
assign coreFix_memExe_lsq$setAtCommit_0_put =
|
|
rob$deqPort_0_deq_data[24:19] ;
|
|
assign coreFix_memExe_lsq$setAtCommit_1_put =
|
|
rob$deqPort_1_deq_data[24:19] ;
|
|
assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_lsq$updateAddr_fault =
|
|
{ coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
|
|
coreFix_memExe_dTlb$procResp[12] :
|
|
coreFix_memExe_dTlb$procResp[12] ||
|
|
coreFix_memExe_dTlb$procResp[110],
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853 } ;
|
|
assign coreFix_memExe_lsq$updateAddr_isMMIO =
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 ||
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1724 ||
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 ;
|
|
assign coreFix_memExe_lsq$updateAddr_lsqTag =
|
|
coreFix_memExe_dTlb$procResp[90:85] ;
|
|
assign coreFix_memExe_lsq$updateAddr_paddr =
|
|
coreFix_memExe_dTlb$procResp[174:111] ;
|
|
assign coreFix_memExe_lsq$updateAddr_shiftedBE =
|
|
coreFix_memExe_dTlb$procResp[84:77] ;
|
|
assign coreFix_memExe_lsq$updateData_d =
|
|
(coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ?
|
|
coreFix_memExe_regToExeQ$first[75:12] :
|
|
shiftData__h180478 ;
|
|
assign coreFix_memExe_lsq$updateData_t =
|
|
coreFix_memExe_regToExeQ$first[143:140] ;
|
|
assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
|
|
assign coreFix_memExe_lsq$EN_enqLd =
|
|
WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ;
|
|
assign coreFix_memExe_lsq$EN_enqSt =
|
|
WILL_FIRE_RL_renameStage_doRenaming && _dfoo2 ;
|
|
assign coreFix_memExe_lsq$EN_getHit =
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 ;
|
|
assign coreFix_memExe_lsq$EN_updateData =
|
|
WILL_FIRE_RL_coreFix_memExe_doExeMem &&
|
|
coreFix_memExe_regToExeQ$first[145] ;
|
|
assign coreFix_memExe_lsq$EN_updateAddr =
|
|
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
|
|
assign coreFix_memExe_lsq$EN_issueLd =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign coreFix_memExe_lsq$EN_getIssueLd =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ;
|
|
assign coreFix_memExe_lsq$EN_respLd =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
|
|
assign coreFix_memExe_lsq$EN_deqLd =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
|
|
assign coreFix_memExe_lsq$EN_deqSt =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ;
|
|
assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB =
|
|
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd1 ;
|
|
assign coreFix_memExe_lsq$EN_setAtCommit_0_put =
|
|
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
|
|
assign coreFix_memExe_lsq$EN_setAtCommit_1_put =
|
|
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
|
|
assign coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
|
|
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
|
|
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
|
|
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
|
|
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
|
|
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
|
|
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN =
|
|
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
|
|
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
|
|
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_regToExeQ
|
|
assign coreFix_memExe_regToExeQ$enq_x =
|
|
{ coreFix_memExe_dispToRegQ$first[97:63],
|
|
coreFix_memExe_dispToRegQ$first[29:12],
|
|
x__h180387,
|
|
x__h180388,
|
|
coreFix_memExe_dispToRegQ$first[11:0] } ;
|
|
assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_regToExeQ$EN_enq =
|
|
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
|
|
assign coreFix_memExe_regToExeQ$EN_deq =
|
|
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
|
|
assign coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
|
|
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN =
|
|
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
|
|
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
|
|
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
|
|
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
|
|
assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN =
|
|
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
|
|
assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
|
|
assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
|
|
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN =
|
|
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
|
|
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
|
|
assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLdQ_full_dummy2_0$EN =
|
|
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write &&
|
|
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
|
|
assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLdQ_full_dummy2_1$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
|
|
|
|
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
|
|
assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN =
|
|
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
|
|
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
|
|
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN =
|
|
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
|
|
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN =
|
|
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
|
|
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
|
|
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN =
|
|
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
|
|
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
|
|
|
|
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
|
|
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
|
|
assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
|
|
assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
|
|
assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
|
|
assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
|
|
assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqStQ_empty_dummy2_0$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
|
|
assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqStQ_empty_dummy2_1$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
|
|
assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
|
|
assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
|
|
assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_full_dummy2_0
|
|
assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqStQ_full_dummy2_0$EN =
|
|
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_full_dummy2_1
|
|
assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_reqStQ_full_dummy2_1$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
|
|
|
|
// submodule coreFix_memExe_reqStQ_full_dummy2_2
|
|
assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
|
|
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
|
|
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN =
|
|
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2557 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3) ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_rsMem
|
|
assign coreFix_memExe_rsMem$enq_x =
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13728) ?
|
|
{ fetchStage$pipelines_0_first[95:93],
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_64_2_ETC___d13744,
|
|
regRenamingTable$rename_0_getRename,
|
|
rob$enqPort_0_getEnqInstTag,
|
|
specTagManager$currentSpecBits,
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_0_get } :
|
|
{ fetchStage$pipelines_1_first[95:93],
|
|
IF_fetchStage_pipelines_1_first__2604_BIT_64_3_ETC___d13867,
|
|
regRenamingTable$rename_1_getRename,
|
|
rob$enqPort_1_getEnqInstTag,
|
|
renaming_spec_bits__h672935,
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1,
|
|
specTagManager$nextSpecTag,
|
|
sbAggr$eagerLookup_1_get } ;
|
|
assign coreFix_memExe_rsMem$setRegReady_0_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
|
|
assign coreFix_memExe_rsMem$setRegReady_1_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
coreFix_memExe_rsMem$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
coreFix_memExe_rsMem$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
coreFix_memExe_rsMem$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
coreFix_memExe_rsMem$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
coreFix_memExe_rsMem$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
coreFix_memExe_rsMem$setRegReady_2_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
|
|
default: coreFix_memExe_rsMem$setRegReady_2_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_rsMem$setRegReady_3_put =
|
|
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
|
|
always@(MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
|
|
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1:
|
|
coreFix_memExe_rsMem$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
|
|
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2:
|
|
coreFix_memExe_rsMem$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
|
|
coreFix_memExe_rsMem$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
|
|
coreFix_memExe_rsMem$setRegReady_4_put =
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
|
|
default: coreFix_memExe_rsMem$setRegReady_4_put =
|
|
8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ;
|
|
assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign coreFix_memExe_rsMem$EN_enq =
|
|
WILL_FIRE_RL_renameStage_doRenaming && _dfoo12 ;
|
|
assign coreFix_memExe_rsMem$EN_setRobEnqTime = 1'd1 ;
|
|
assign coreFix_memExe_rsMem$EN_doDispatch =
|
|
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
|
|
assign coreFix_memExe_rsMem$EN_setRegReady_0_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
|
|
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
|
|
assign coreFix_memExe_rsMem$EN_setRegReady_1_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
|
|
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
|
|
assign coreFix_memExe_rsMem$EN_setRegReady_2_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign coreFix_memExe_rsMem$EN_setRegReady_3_put =
|
|
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
|
|
coreFix_memExe_lsq$issueLd[72] ;
|
|
assign coreFix_memExe_rsMem$EN_setRegReady_4_put =
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ;
|
|
assign coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule coreFix_memExe_stb
|
|
assign coreFix_memExe_stb$deq_idx =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
|
|
assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ;
|
|
assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ;
|
|
assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ;
|
|
assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ;
|
|
assign coreFix_memExe_stb$getEnqIndex_paddr =
|
|
coreFix_memExe_lsq$firstSt[141:78] ;
|
|
assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ;
|
|
assign coreFix_memExe_stb$noMatchLdQ_paddr =
|
|
coreFix_memExe_lsq$firstLd[80:17] ;
|
|
assign coreFix_memExe_stb$noMatchStQ_be =
|
|
coreFix_memExe_lsq$firstSt[76:69] ;
|
|
assign coreFix_memExe_stb$noMatchStQ_paddr =
|
|
coreFix_memExe_lsq$firstSt[141:78] ;
|
|
assign coreFix_memExe_stb$search_be =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
|
|
coreFix_memExe_lsq$getIssueLd[7:0] :
|
|
coreFix_memExe_issueLd$wget[7:0] ;
|
|
assign coreFix_memExe_stb$search_paddr =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
|
|
coreFix_memExe_lsq$getIssueLd[71:8] :
|
|
coreFix_memExe_issueLd$wget[71:8] ;
|
|
assign coreFix_memExe_stb$EN_enq =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ;
|
|
assign coreFix_memExe_stb$EN_deq =
|
|
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd1 ;
|
|
assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
|
|
|
|
// submodule coreFix_trainBPQ_0
|
|
assign coreFix_trainBPQ_0$D_IN =
|
|
MUX_coreFix_trainBPQ_0$enq_1__SEL_1 ?
|
|
MUX_coreFix_trainBPQ_0$enq_1__VAL_1 :
|
|
MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ;
|
|
assign coreFix_trainBPQ_0$ENQ =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
|
|
(coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd9 ||
|
|
coreFix_aluExe_0_exeToFinQ$first[325:321] == 5'd10) ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
|
|
assign coreFix_trainBPQ_0$CLR = 1'b0 ;
|
|
|
|
// submodule coreFix_trainBPQ_1
|
|
assign coreFix_trainBPQ_1$D_IN =
|
|
MUX_coreFix_trainBPQ_1$enq_1__SEL_1 ?
|
|
MUX_coreFix_trainBPQ_1$enq_1__VAL_1 :
|
|
MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ;
|
|
assign coreFix_trainBPQ_1$ENQ =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
|
|
(coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd9 ||
|
|
coreFix_aluExe_1_exeToFinQ$first[325:321] == 5'd10) ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ;
|
|
assign coreFix_trainBPQ_1$CLR = 1'b0 ;
|
|
|
|
// submodule csrInstOrInterruptInflight_dummy2_0
|
|
assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ;
|
|
assign csrInstOrInterruptInflight_dummy2_0$EN =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
|
|
commitStage_commitTrap[4] ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 ;
|
|
|
|
// submodule csrInstOrInterruptInflight_dummy2_1
|
|
assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ;
|
|
assign csrInstOrInterruptInflight_dummy2_1$EN =
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
|
|
fetchStage$pipelines_0_first[103:99] == 5'd13 ||
|
|
MUX_csrInstOrInterruptInflight_dummy2_1$write_1__SEL_2 ;
|
|
|
|
// submodule csrf_mcycle_ehr_data_dummy2_0
|
|
assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ;
|
|
assign csrf_mcycle_ehr_data_dummy2_0$EN = csrf_mcycle_ehr_data_lat_0$whas ;
|
|
|
|
// submodule csrf_mcycle_ehr_data_dummy2_1
|
|
assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ;
|
|
assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule csrf_minstret_ehr_data_dummy2_0
|
|
assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ;
|
|
assign csrf_minstret_ehr_data_dummy2_0$EN =
|
|
csrf_minstret_ehr_data_lat_0$whas ;
|
|
|
|
// submodule csrf_minstret_ehr_data_dummy2_1
|
|
assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ;
|
|
assign csrf_minstret_ehr_data_dummy2_1$EN =
|
|
csrf_minstret_ehr_data_dummy_1_0$whas ;
|
|
|
|
// submodule csrf_stats_module_writeQ
|
|
assign csrf_stats_module_writeQ$D_IN = csrf_sscratch_csr$D_IN[0] ;
|
|
assign csrf_stats_module_writeQ$ENQ =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd7 ;
|
|
assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ;
|
|
assign csrf_stats_module_writeQ$CLR = 1'b0 ;
|
|
|
|
// submodule csrf_terminate_module_terminateQ
|
|
assign csrf_terminate_module_terminateQ$ENQ =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd6 ;
|
|
assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ;
|
|
assign csrf_terminate_module_terminateQ$CLR = 1'b0 ;
|
|
|
|
// submodule epochManager
|
|
assign epochManager$checkEpoch_0_check_e =
|
|
fetchStage$pipelines_0_first[163:160] ;
|
|
assign epochManager$checkEpoch_1_check_e =
|
|
fetchStage$pipelines_1_first[163:160] ;
|
|
assign epochManager$updatePrevEpoch_0_update_e =
|
|
fetchStage$pipelines_0_first[163:160] ;
|
|
assign epochManager$updatePrevEpoch_1_update_e =
|
|
fetchStage$pipelines_1_first[163:160] ;
|
|
assign epochManager$EN_updatePrevEpoch_0_update =
|
|
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
|
|
fetchStage$pipelines_0_canDeq ||
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
|
|
assign epochManager$EN_updatePrevEpoch_1_update =
|
|
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
|
|
fetchStage$pipelines_1_canDeq &&
|
|
!epochManager$checkEpoch_1_check ||
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13807 &&
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 ;
|
|
assign epochManager$EN_incrementEpoch =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!rob$deqPort_0_deq_data[12] ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
|
|
|
|
// submodule fetchStage
|
|
assign fetchStage$iMemIfc_perf_req_r = 2'h0 ;
|
|
assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ;
|
|
assign fetchStage$iMemIfc_to_parent_fromP_enq_x =
|
|
iCacheToParent_fromP_enq_x ;
|
|
assign fetchStage$iMemIfc_to_proc_request_put = 64'h0 ;
|
|
assign fetchStage$iTlbIfc_perf_req_r = 3'h0 ;
|
|
assign fetchStage$iTlbIfc_perf_setStatus_doStats = 1'b0 ;
|
|
assign fetchStage$iTlbIfc_toParent_rsFromP_enq_x =
|
|
l2Tlb$toChildren_rsToC_first[80:0] ;
|
|
assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ;
|
|
assign fetchStage$iTlbIfc_updateVMInfo_vm =
|
|
{ csrf_prv_reg,
|
|
csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg,
|
|
csrf_mxr_reg,
|
|
csrf_sum_reg,
|
|
csrf_ppn_reg } ;
|
|
assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ;
|
|
assign fetchStage$mmioIfc_setHtifAddrs_fromHost =
|
|
coreReq_start_fromHostAddr ;
|
|
assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ;
|
|
assign fetchStage$perf_req_r = 2'h0 ;
|
|
assign fetchStage$perf_setStatus_doStats = 1'b0 ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd or
|
|
rob$deqPort_0_deq_data or
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle or
|
|
MUX_fetchStage$redirect_1__VAL_4 or
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst or
|
|
MUX_fetchStage$redirect_1__VAL_5)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19];
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd:
|
|
fetchStage$redirect_pc = rob$deqPort_0_deq_data[186:123];
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle:
|
|
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_4;
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst:
|
|
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_5;
|
|
default: fetchStage$redirect_pc =
|
|
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign fetchStage$start_pc = coreReq_start_startpc ;
|
|
assign fetchStage$train_predictors_dpTrain =
|
|
coreFix_trainBPQ_1$EMPTY_N ?
|
|
coreFix_trainBPQ_1$D_OUT[24:1] :
|
|
coreFix_trainBPQ_0$D_OUT[24:1] ;
|
|
assign fetchStage$train_predictors_iType =
|
|
coreFix_trainBPQ_1$EMPTY_N ?
|
|
coreFix_trainBPQ_1$D_OUT[30:26] :
|
|
coreFix_trainBPQ_0$D_OUT[30:26] ;
|
|
assign fetchStage$train_predictors_mispred =
|
|
coreFix_trainBPQ_1$EMPTY_N ?
|
|
coreFix_trainBPQ_1$D_OUT[0] :
|
|
coreFix_trainBPQ_0$D_OUT[0] ;
|
|
assign fetchStage$train_predictors_next_pc =
|
|
coreFix_trainBPQ_1$EMPTY_N ?
|
|
coreFix_trainBPQ_1$D_OUT[94:31] :
|
|
coreFix_trainBPQ_0$D_OUT[94:31] ;
|
|
assign fetchStage$train_predictors_pc =
|
|
coreFix_trainBPQ_1$EMPTY_N ?
|
|
coreFix_trainBPQ_1$D_OUT[158:95] :
|
|
coreFix_trainBPQ_0$D_OUT[158:95] ;
|
|
assign fetchStage$train_predictors_taken =
|
|
coreFix_trainBPQ_1$EMPTY_N ?
|
|
coreFix_trainBPQ_1$D_OUT[25] :
|
|
coreFix_trainBPQ_0$D_OUT[25] ;
|
|
assign fetchStage$EN_pipelines_0_deq =
|
|
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
|
|
fetchStage$pipelines_0_canDeq ||
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
|
|
assign fetchStage$EN_pipelines_1_deq =
|
|
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
|
|
fetchStage$pipelines_1_canDeq &&
|
|
!epochManager$checkEpoch_1_check ||
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13807 &&
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 ;
|
|
assign fetchStage$EN_iTlbIfc_flush = MUX_flush_tlbs$write_1__SEL_1 ;
|
|
assign fetchStage$EN_iTlbIfc_updateVMInfo =
|
|
MUX_update_vm_info$write_1__SEL_1 ;
|
|
assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ;
|
|
assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ;
|
|
assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ;
|
|
assign fetchStage$EN_iTlbIfc_toParent_rsFromP_enq =
|
|
CAN_FIRE_RL_sendRsToITlb ;
|
|
assign fetchStage$EN_iTlbIfc_toParent_flush_request_get =
|
|
CAN_FIRE_RL_mkConnectionGetPut_1 ;
|
|
assign fetchStage$EN_iTlbIfc_toParent_flush_response_put =
|
|
CAN_FIRE_RL_sendFlushDone ;
|
|
assign fetchStage$EN_iTlbIfc_perf_setStatus = 1'b0 ;
|
|
assign fetchStage$EN_iTlbIfc_perf_req = 1'b0 ;
|
|
assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ;
|
|
assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ;
|
|
assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ;
|
|
assign fetchStage$EN_iMemIfc_flush = 1'b0 ;
|
|
assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ;
|
|
assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ;
|
|
assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ;
|
|
assign fetchStage$EN_iMemIfc_to_parent_rsToP_deq =
|
|
EN_iCacheToParent_rsToP_deq ;
|
|
assign fetchStage$EN_iMemIfc_to_parent_rqToP_deq =
|
|
EN_iCacheToParent_rqToP_deq ;
|
|
assign fetchStage$EN_iMemIfc_to_parent_fromP_enq =
|
|
EN_iCacheToParent_fromP_enq ;
|
|
assign fetchStage$EN_iMemIfc_cRqStuck_get = EN_deadlock_iCacheCRqStuck_get ;
|
|
assign fetchStage$EN_iMemIfc_pRqStuck_get = EN_deadlock_iCachePRqStuck_get ;
|
|
assign fetchStage$EN_mmioIfc_instReq_deq = WILL_FIRE_RL_mmio_sendInstReq ;
|
|
assign fetchStage$EN_mmioIfc_instResp_enq = CAN_FIRE_RL_mmio_sendInstResp ;
|
|
assign fetchStage$EN_mmioIfc_setHtifAddrs = EN_coreReq_start ;
|
|
assign fetchStage$EN_start = EN_coreReq_start ;
|
|
assign fetchStage$EN_stop = 1'b0 ;
|
|
assign fetchStage$EN_setWaitRedirect =
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
|
|
!rob$deqPort_0_deq_data[12] ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
|
|
assign fetchStage$EN_redirect =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
|
|
assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ;
|
|
assign fetchStage$EN_train_predictors =
|
|
coreFix_trainBPQ_1$EMPTY_N ||
|
|
WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
|
|
assign fetchStage$EN_flush_predictors = 1'b0 ;
|
|
assign fetchStage$EN_perf_setStatus = 1'b0 ;
|
|
assign fetchStage$EN_perf_req = 1'b0 ;
|
|
assign fetchStage$EN_perf_resp = 1'b0 ;
|
|
|
|
// submodule l2Tlb
|
|
assign l2Tlb$perf_req_r = 4'h0 ;
|
|
assign l2Tlb$perf_setStatus_doStats = 1'b0 ;
|
|
assign l2Tlb$toChildren_rqFromC_put =
|
|
WILL_FIRE_RL_sendDTlbReq ?
|
|
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 :
|
|
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ;
|
|
assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ;
|
|
assign l2Tlb$updateVMInfo_vmD = coreFix_memExe_dTlb$updateVMInfo_vm ;
|
|
assign l2Tlb$updateVMInfo_vmI = fetchStage$iTlbIfc_updateVMInfo_vm ;
|
|
assign l2Tlb$EN_updateVMInfo = MUX_update_vm_info$write_1__SEL_1 ;
|
|
assign l2Tlb$EN_toChildren_rqFromC_put =
|
|
WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ;
|
|
assign l2Tlb$EN_toChildren_rsToC_deq =
|
|
WILL_FIRE_RL_sendRsToITlb || WILL_FIRE_RL_sendRsToDTlb ;
|
|
assign l2Tlb$EN_toChildren_iTlbReqFlush_put =
|
|
CAN_FIRE_RL_mkConnectionGetPut_1 ;
|
|
assign l2Tlb$EN_toChildren_dTlbReqFlush_put =
|
|
CAN_FIRE_RL_mkConnectionGetPut ;
|
|
assign l2Tlb$EN_toChildren_flushDone_get = CAN_FIRE_RL_sendFlushDone ;
|
|
assign l2Tlb$EN_toMem_memReq_deq = EN_tlbToMem_memReq_deq ;
|
|
assign l2Tlb$EN_toMem_respLd_enq = EN_tlbToMem_respLd_enq ;
|
|
assign l2Tlb$EN_perf_setStatus = 1'b0 ;
|
|
assign l2Tlb$EN_perf_req = 1'b0 ;
|
|
assign l2Tlb$EN_perf_resp = 1'b0 ;
|
|
|
|
// submodule mmio_cRqQ_clearReq_dummy2_0
|
|
assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule mmio_cRqQ_clearReq_dummy2_1
|
|
assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule mmio_cRqQ_deqReq_dummy2_0
|
|
assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ;
|
|
|
|
// submodule mmio_cRqQ_deqReq_dummy2_1
|
|
assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_cRqQ_deqReq_dummy2_2
|
|
assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_cRqQ_enqReq_dummy2_0
|
|
assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_cRqQ_enqReq_dummy2_0$EN =
|
|
WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ;
|
|
|
|
// submodule mmio_cRqQ_enqReq_dummy2_1
|
|
assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_cRqQ_enqReq_dummy2_2
|
|
assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_cRsQ_clearReq_dummy2_0
|
|
assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule mmio_cRsQ_clearReq_dummy2_1
|
|
assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule mmio_cRsQ_deqReq_dummy2_0
|
|
assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ;
|
|
|
|
// submodule mmio_cRsQ_deqReq_dummy2_1
|
|
assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_cRsQ_deqReq_dummy2_2
|
|
assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_cRsQ_enqReq_dummy2_0
|
|
assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
|
|
|
|
// submodule mmio_cRsQ_enqReq_dummy2_1
|
|
assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_cRsQ_enqReq_dummy2_2
|
|
assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataPendQ_clearReq_dummy2_0
|
|
assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataPendQ_clearReq_dummy2_1
|
|
assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataPendQ_deqReq_dummy2_0
|
|
assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_dataPendQ_deqReq_dummy2_0$EN =
|
|
mmio_dataRespQ_deqReq_lat_0$whas ;
|
|
|
|
// submodule mmio_dataPendQ_deqReq_dummy2_1
|
|
assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataPendQ_deqReq_dummy2_2
|
|
assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataPendQ_enqReq_dummy2_0
|
|
assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_dataPendQ_enqReq_dummy2_0$EN =
|
|
mmio_dataPendQ_enqReq_lat_0$whas ;
|
|
|
|
// submodule mmio_dataPendQ_enqReq_dummy2_1
|
|
assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataPendQ_enqReq_dummy2_2
|
|
assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataReqQ_clearReq_dummy2_0
|
|
assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataReqQ_clearReq_dummy2_1
|
|
assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataReqQ_deqReq_dummy2_0
|
|
assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ;
|
|
|
|
// submodule mmio_dataReqQ_deqReq_dummy2_1
|
|
assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataReqQ_deqReq_dummy2_2
|
|
assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataReqQ_enqReq_dummy2_0
|
|
assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ;
|
|
|
|
// submodule mmio_dataReqQ_enqReq_dummy2_1
|
|
assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataReqQ_enqReq_dummy2_2
|
|
assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataRespQ_clearReq_dummy2_0
|
|
assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataRespQ_clearReq_dummy2_1
|
|
assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataRespQ_deqReq_dummy2_0
|
|
assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_dataRespQ_deqReq_dummy2_0$EN =
|
|
mmio_dataRespQ_deqReq_lat_0$whas ;
|
|
|
|
// submodule mmio_dataRespQ_deqReq_dummy2_1
|
|
assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataRespQ_deqReq_dummy2_2
|
|
assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_dataRespQ_enqReq_dummy2_0
|
|
assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ;
|
|
|
|
// submodule mmio_dataRespQ_enqReq_dummy2_1
|
|
assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_dataRespQ_enqReq_dummy2_2
|
|
assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_pRqQ_clearReq_dummy2_0
|
|
assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule mmio_pRqQ_clearReq_dummy2_1
|
|
assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule mmio_pRqQ_deqReq_dummy2_0
|
|
assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
|
|
|
|
// submodule mmio_pRqQ_deqReq_dummy2_1
|
|
assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_pRqQ_deqReq_dummy2_2
|
|
assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_pRqQ_enqReq_dummy2_0
|
|
assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ;
|
|
|
|
// submodule mmio_pRqQ_enqReq_dummy2_1
|
|
assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_pRqQ_enqReq_dummy2_2
|
|
assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_pRsQ_clearReq_dummy2_0
|
|
assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule mmio_pRsQ_clearReq_dummy2_1
|
|
assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule mmio_pRsQ_deqReq_dummy2_0
|
|
assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_dummy_2_0$wget ;
|
|
|
|
// submodule mmio_pRsQ_deqReq_dummy2_1
|
|
assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_pRsQ_deqReq_dummy2_2
|
|
assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule mmio_pRsQ_enqReq_dummy2_0
|
|
assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ;
|
|
|
|
// submodule mmio_pRsQ_enqReq_dummy2_1
|
|
assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule mmio_pRsQ_enqReq_dummy2_2
|
|
assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule perfReqQ
|
|
assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ;
|
|
assign perfReqQ$ENQ = EN_coreReq_perfReq ;
|
|
assign perfReqQ$DEQ = EN_coreIndInv_perfResp ;
|
|
assign perfReqQ$CLR = 1'b0 ;
|
|
|
|
// submodule regRenamingTable
|
|
assign regRenamingTable$rename_0_claimRename_r =
|
|
fetchStage$pipelines_0_first[31:5] ;
|
|
assign regRenamingTable$rename_0_claimRename_sb =
|
|
specTagManager$currentSpecBits ;
|
|
assign regRenamingTable$rename_0_getRename_r =
|
|
fetchStage$pipelines_0_first[31:5] ;
|
|
assign regRenamingTable$rename_1_claimRename_r =
|
|
fetchStage$pipelines_1_first[31:5] ;
|
|
assign regRenamingTable$rename_1_claimRename_sb =
|
|
renaming_spec_bits__h672935 ;
|
|
assign regRenamingTable$rename_1_getRename_r =
|
|
fetchStage$pipelines_1_first[31:5] ;
|
|
assign regRenamingTable$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign regRenamingTable$EN_rename_0_claimRename =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
|
|
assign regRenamingTable$EN_rename_1_claimRename =
|
|
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
|
|
assign regRenamingTable$EN_commit_0_commit =
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
|
|
rob$deqPort_0_canDeq ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
|
|
assign regRenamingTable$EN_commit_1_commit =
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
|
|
rob$deqPort_1_canDeq &&
|
|
rob$deqPort_1_deq_data[25] &&
|
|
!rob$deqPort_1_deq_data[18] &&
|
|
!rob$deqPort_1_deq_data[103] &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd0 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd21 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd17 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd18 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd13 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd16 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd15 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd19 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd20 ;
|
|
assign regRenamingTable$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign regRenamingTable$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule rf
|
|
assign rf$read_0_rd1_rindx = coreFix_aluExe_0_dispToRegQ$first[84:78] ;
|
|
assign rf$read_0_rd2_rindx = coreFix_aluExe_0_dispToRegQ$first[76:70] ;
|
|
assign rf$read_0_rd3_rindx = 7'h0 ;
|
|
assign rf$read_1_rd1_rindx = coreFix_aluExe_1_dispToRegQ$first[84:78] ;
|
|
assign rf$read_1_rd2_rindx = coreFix_aluExe_1_dispToRegQ$first[76:70] ;
|
|
assign rf$read_1_rd3_rindx = 7'h0 ;
|
|
assign rf$read_2_rd1_rindx =
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
|
|
assign rf$read_2_rd2_rindx =
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
|
|
assign rf$read_2_rd3_rindx =
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
|
|
assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ;
|
|
assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ;
|
|
assign rf$read_3_rd3_rindx = 7'h0 ;
|
|
assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ;
|
|
assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[319:313] ;
|
|
assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ;
|
|
assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[319:313] ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
MUX_rf$write_2_wr_2__VAL_1 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
MUX_rf$write_2_wr_2__VAL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
MUX_rf$write_2_wr_2__VAL_4 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
MUX_rf$write_2_wr_2__VAL_5 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
MUX_rf$write_2_wr_2__VAL_6)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_1;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
rf$write_2_wr_data =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_4;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_5;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6;
|
|
default: rf$write_2_wr_data =
|
|
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
rf$write_2_wr_rindx =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
rf$write_2_wr_rindx =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
rf$write_2_wr_rindx =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
rf$write_2_wr_rindx =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
rf$write_2_wr_rindx =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
rf$write_2_wr_rindx =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
|
|
default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(MUX_rf$write_3_wr_1__SEL_1 or
|
|
coreFix_memExe_respLrScAmoQ_data_0 or
|
|
MUX_rf$write_3_wr_1__SEL_2 or
|
|
mmio_dataRespQ_data_0 or
|
|
MUX_rf$write_3_wr_1__SEL_3 or
|
|
MUX_rf$write_3_wr_2__VAL_3 or
|
|
MUX_rf$write_3_wr_1__SEL_4 or
|
|
MUX_rf$write_3_wr_2__VAL_4 or
|
|
MUX_rf$write_3_wr_2__SEL_5 or coreFix_memExe_lsq$respLd)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_rf$write_3_wr_1__SEL_1:
|
|
rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0;
|
|
MUX_rf$write_3_wr_1__SEL_2:
|
|
rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0];
|
|
MUX_rf$write_3_wr_1__SEL_3:
|
|
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_3;
|
|
MUX_rf$write_3_wr_1__SEL_4:
|
|
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4;
|
|
MUX_rf$write_3_wr_2__SEL_5:
|
|
rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0];
|
|
default: rf$write_3_wr_data =
|
|
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(MUX_rf$write_3_wr_1__SEL_5 or
|
|
coreFix_memExe_lsq$respLd or
|
|
MUX_rf$write_3_wr_1__SEL_3 or
|
|
MUX_rf$write_3_wr_1__SEL_4 or
|
|
coreFix_memExe_lsq$firstLd or
|
|
MUX_rf$write_3_wr_1__SEL_1 or
|
|
MUX_rf$write_3_wr_1__SEL_2 or coreFix_memExe_lsq$firstSt)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_rf$write_3_wr_1__SEL_5:
|
|
rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[71:65];
|
|
MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4:
|
|
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82];
|
|
MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2:
|
|
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143];
|
|
default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign rf$EN_write_0_wr =
|
|
_dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[320] ;
|
|
assign rf$EN_write_1_wr =
|
|
_dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[320] ;
|
|
assign rf$EN_write_2_wr =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign rf$EN_write_3_wr =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
|
|
coreFix_memExe_lsq$respLd[72] ;
|
|
|
|
// submodule rob
|
|
always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or
|
|
MUX_rob$enqPort_0_enq_1__VAL_1 or
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap or
|
|
MUX_rob$enqPort_0_enq_1__VAL_2 or
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst or
|
|
MUX_rob$enqPort_0_enq_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2:
|
|
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_1;
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap:
|
|
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_2;
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst:
|
|
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3;
|
|
default: rob$enqPort_0_enq_x =
|
|
187'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign rob$enqPort_1_enq_x =
|
|
{ fetchStage$pipelines_1_first[291:228],
|
|
fetchStage$pipelines_1_first[103:99],
|
|
fetchStage_pipelines_1_first__2604_BIT_77_3276_ETC___d13351,
|
|
9'd296,
|
|
fetchStage$pipelines_1_first[227:164],
|
|
5'd0,
|
|
fetchStage$pipelines_1_first[11] &&
|
|
fetchStage$pipelines_1_first[10],
|
|
fetchStage$pipelines_1_first[98:96] != 3'd0 &&
|
|
fetchStage$pipelines_1_first[98:96] != 3'd1 &&
|
|
fetchStage$pipelines_1_first[98:96] != 3'd2 &&
|
|
fetchStage$pipelines_1_first[98:96] != 3'd3 &&
|
|
fetchStage$pipelines_1_first[98:96] != 3'd4,
|
|
fetchStage$pipelines_1_first[98:96] != 3'd2 ||
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13898 ||
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13861,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13908,
|
|
7'd32,
|
|
renaming_spec_bits__h672935 } ;
|
|
assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
|
|
assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
|
|
assign rob$getOrigPC_2_get_x = 12'h0 ;
|
|
assign rob$getOrigPredPC_0_get_x =
|
|
coreFix_aluExe_0_dispToRegQ$first[52:41] ;
|
|
assign rob$getOrigPredPC_1_get_x =
|
|
coreFix_aluExe_1_dispToRegQ$first[52:41] ;
|
|
always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or
|
|
MUX_rob$setExecuted_deqLSQ_2__VAL_3 or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or
|
|
MUX_rob$setExecuted_deqLSQ_2__VAL_6 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or
|
|
MUX_rob$setExecuted_deqLSQ_1__SEL_5 or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault:
|
|
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3;
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault:
|
|
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6;
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
|
|
MUX_rob$setExecuted_deqLSQ_1__SEL_5:
|
|
rob$setExecuted_deqLSQ_cause = 5'd10;
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault:
|
|
rob$setExecuted_deqLSQ_cause = 5'd21;
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault:
|
|
rob$setExecuted_deqLSQ_cause = 5'd23;
|
|
default: rob$setExecuted_deqLSQ_cause =
|
|
5'b01010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign rob$setExecuted_deqLSQ_ld_killed =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ?
|
|
coreFix_memExe_lsq$firstLd[2:0] :
|
|
3'd2 ;
|
|
assign rob$setExecuted_deqLSQ_x =
|
|
(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ?
|
|
coreFix_memExe_lsq$firstLd[113:102] :
|
|
coreFix_memExe_lsq$firstSt[170:159] ;
|
|
assign rob$setExecuted_doFinishAlu_0_set_cf =
|
|
coreFix_aluExe_0_exeToFinQ$first[146:17] ;
|
|
assign rob$setExecuted_doFinishAlu_0_set_csrData =
|
|
coreFix_aluExe_0_exeToFinQ$first[211:147] ;
|
|
assign rob$setExecuted_doFinishAlu_0_set_x =
|
|
coreFix_aluExe_0_exeToFinQ$first[311:300] ;
|
|
assign rob$setExecuted_doFinishAlu_1_set_cf =
|
|
coreFix_aluExe_1_exeToFinQ$first[146:17] ;
|
|
assign rob$setExecuted_doFinishAlu_1_set_csrData =
|
|
coreFix_aluExe_1_exeToFinQ$first[211:147] ;
|
|
assign rob$setExecuted_doFinishAlu_1_set_x =
|
|
coreFix_aluExe_1_exeToFinQ$first[311:300] ;
|
|
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33];
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2;
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3;
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
|
|
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4;
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0;
|
|
default: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
|
|
5'b01010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[23:12];
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[23:12];
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[23:12];
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[23:12];
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[23:12];
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
|
|
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[23:12];
|
|
default: rob$setExecuted_doFinishFpuMulDiv_0_set_x =
|
|
12'b101010101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign rob$setExecuted_doFinishMem_access_at_commit =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1737 &&
|
|
(coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 ||
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1724 ||
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 ||
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd4) ;
|
|
assign rob$setExecuted_doFinishMem_non_mmio_st_done =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1737 &&
|
|
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 &&
|
|
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1724 &&
|
|
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 &&
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd1 ;
|
|
assign rob$setExecuted_doFinishMem_vaddr =
|
|
coreFix_memExe_dTlb$procResp[76:13] ;
|
|
assign rob$setExecuted_doFinishMem_x =
|
|
coreFix_memExe_dTlb$procResp[102:91] ;
|
|
assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ;
|
|
assign rob$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
rob$specUpdate_incorrectSpeculation_inst_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[311:300];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
rob$specUpdate_incorrectSpeculation_inst_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[311:300];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
rob$specUpdate_incorrectSpeculation_inst_tag =
|
|
12'b101010101010 /* unspecified value */ ;
|
|
default: rob$specUpdate_incorrectSpeculation_inst_tag =
|
|
12'b101010101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign rob$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
rob$specUpdate_incorrectSpeculation_spec_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
rob$specUpdate_incorrectSpeculation_spec_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
rob$specUpdate_incorrectSpeculation_spec_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: rob$specUpdate_incorrectSpeculation_spec_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign rob$EN_enqPort_0_enq =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_Trap ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
|
|
assign rob$EN_enqPort_1_enq =
|
|
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
|
|
assign rob$EN_deqPort_0_deq =
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
|
|
rob$deqPort_0_canDeq ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
|
|
assign rob$EN_deqPort_1_deq =
|
|
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
|
|
rob$deqPort_1_canDeq &&
|
|
rob$deqPort_1_deq_data[25] &&
|
|
!rob$deqPort_1_deq_data[18] &&
|
|
!rob$deqPort_1_deq_data[103] &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd0 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd21 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd17 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd18 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd13 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd16 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd15 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd19 &&
|
|
rob$deqPort_1_deq_data[122:118] != 5'd20 ;
|
|
assign rob$EN_setLSQAtCommitNotified =
|
|
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
|
|
assign rob$EN_setExecuted_deqLSQ =
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ;
|
|
assign rob$EN_setExecuted_doFinishAlu_0_set =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign rob$EN_setExecuted_doFinishAlu_1_set =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign rob$EN_setExecuted_doFinishFpuMulDiv_0_set =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
|
|
assign rob$EN_setExecuted_doFinishMem =
|
|
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
|
|
assign rob$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign rob$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// submodule sbAggr
|
|
assign sbAggr$eagerLookup_0_get_r = regRenamingTable$rename_0_getRename ;
|
|
assign sbAggr$eagerLookup_1_get_r = regRenamingTable$rename_1_getRename ;
|
|
assign sbAggr$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
|
|
assign sbAggr$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
|
|
assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ;
|
|
assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
sbAggr$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
sbAggr$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
sbAggr$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
sbAggr$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
sbAggr$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
sbAggr$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
|
|
default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or
|
|
coreFix_memExe_lsq$getHit or
|
|
MUX_sbAggr$setReady_4_put_1__SEL_2 or
|
|
coreFix_memExe_lsq$firstLd or
|
|
MUX_sbAggr$setReady_4_put_1__SEL_1 or coreFix_memExe_lsq$firstSt)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 ||
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
|
|
sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1];
|
|
MUX_sbAggr$setReady_4_put_1__SEL_2:
|
|
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82];
|
|
MUX_sbAggr$setReady_4_put_1__SEL_1:
|
|
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143];
|
|
default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign sbAggr$EN_setBusy_0_set =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
|
|
assign sbAggr$EN_setBusy_1_set =
|
|
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
|
|
assign sbAggr$EN_setReady_0_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
|
|
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
|
|
assign sbAggr$EN_setReady_1_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
|
|
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
|
|
assign sbAggr$EN_setReady_2_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign sbAggr$EN_setReady_3_put =
|
|
_dor1sbAggr$EN_setReady_3_put &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
|
|
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
|
|
coreFix_memExe_lsq$issueLd[72] ;
|
|
assign sbAggr$EN_setReady_4_put =
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614 ||
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ;
|
|
|
|
// submodule sbCons
|
|
assign sbCons$eagerLookup_0_get_r = 33'h0 ;
|
|
assign sbCons$eagerLookup_1_get_r = 33'h0 ;
|
|
assign sbCons$lazyLookup_0_get_r =
|
|
coreFix_aluExe_0_dispToRegQ$first[85:53] ;
|
|
assign sbCons$lazyLookup_1_get_r =
|
|
coreFix_aluExe_1_dispToRegQ$first[85:53] ;
|
|
assign sbCons$lazyLookup_2_get_r =
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ;
|
|
assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ;
|
|
assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
|
|
assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
|
|
assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[319:313] ;
|
|
assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[319:313] ;
|
|
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
|
|
sbCons$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
|
|
sbCons$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
|
|
sbCons$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
|
|
sbCons$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
|
|
sbCons$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
|
|
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
|
|
sbCons$setReady_2_put =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
|
|
default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
always@(MUX_sbCons$setReady_3_put_1__SEL_1 or
|
|
coreFix_memExe_lsq$firstSt or
|
|
MUX_sbCons$setReady_3_put_1__SEL_2 or
|
|
coreFix_memExe_lsq$firstLd or
|
|
MUX_sbCons$setReady_3_put_1__SEL_3 or coreFix_memExe_lsq$respLd)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_sbCons$setReady_3_put_1__SEL_1:
|
|
sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143];
|
|
MUX_sbCons$setReady_3_put_1__SEL_2:
|
|
sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82];
|
|
MUX_sbCons$setReady_3_put_1__SEL_3:
|
|
sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[71:65];
|
|
default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign sbCons$EN_setBusy_0_set =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ||
|
|
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
|
|
assign sbCons$EN_setBusy_1_set =
|
|
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
|
|
assign sbCons$EN_setReady_0_put =
|
|
_dor1sbCons$EN_setReady_0_put &&
|
|
coreFix_aluExe_0_exeToFinQ$first[320] ;
|
|
assign sbCons$EN_setReady_1_put =
|
|
_dor1sbCons$EN_setReady_1_put &&
|
|
coreFix_aluExe_1_exeToFinQ$first[320] ;
|
|
assign sbCons$EN_setReady_2_put =
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
|
|
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
|
|
assign sbCons$EN_setReady_3_put =
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
|
|
coreFix_memExe_lsq$firstSt[150] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
|
|
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
|
|
coreFix_memExe_lsq$firstLd[89] ||
|
|
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
|
|
coreFix_memExe_lsq$respLd[72] ;
|
|
|
|
// submodule specTagManager
|
|
assign specTagManager$specUpdate_correctSpeculation_mask =
|
|
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 ;
|
|
assign specTagManager$specUpdate_incorrectSpeculation_kill_all =
|
|
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
|
|
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
|
|
coreFix_aluExe_1_exeToFinQ$first or
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
|
|
coreFix_aluExe_0_exeToFinQ$first or
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
|
|
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_1_exeToFinQ$first[15:12];
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
|
|
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
|
|
coreFix_aluExe_0_exeToFinQ$first[15:12];
|
|
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
|
|
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
default: specTagManager$specUpdate_incorrectSpeculation_kill_tag =
|
|
4'b1010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign specTagManager$EN_claimSpecTag =
|
|
WILL_FIRE_RL_renameStage_doRenaming &&
|
|
(fetchStage_pipelines_0_canDeq__2593_AND_specTa_ETC___d13762 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13885) ;
|
|
assign specTagManager$EN_specUpdate_incorrectSpeculation =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
|
|
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
|
|
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
|
|
assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ;
|
|
|
|
// remaining internal signals
|
|
module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]),
|
|
.amoExec_current_data(curData__h190083),
|
|
.amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]),
|
|
.amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]),
|
|
.amoExec(n__h191621));
|
|
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32],
|
|
3'd0 }),
|
|
.amoExec_current_data({ 63'd0,
|
|
msip__h75375 }),
|
|
.amoExec_in_data({ 32'd0, x__h75490 }),
|
|
.amoExec_upper_32_bits(1'd0),
|
|
.amoExec(amoExec___d880));
|
|
module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[389:385],
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_384_ETC__q220,
|
|
{ coreFix_aluExe_0_regToExeQ$first[363],
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_362_ETC__q221,
|
|
coreFix_aluExe_0_regToExeQ$first[350],
|
|
coreFix_aluExe_0_regToExeQ$first[349:318] } }),
|
|
.basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[272:209]),
|
|
.basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[208:145]),
|
|
.basicExec_pc(coreFix_aluExe_0_regToExeQ$first[144:81]),
|
|
.basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[80:17]),
|
|
.basicExec(basicExec___d12459));
|
|
module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[389:385],
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_384_ETC__q223,
|
|
{ coreFix_aluExe_1_regToExeQ$first[363],
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_362_ETC__q224,
|
|
coreFix_aluExe_1_regToExeQ$first[350],
|
|
coreFix_aluExe_1_regToExeQ$first[349:318] } }),
|
|
.basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[272:209]),
|
|
.basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[208:145]),
|
|
.basicExec_pc(coreFix_aluExe_1_regToExeQ$first[144:81]),
|
|
.basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[80:17]),
|
|
.basicExec(basicExec___d11852));
|
|
module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[103:99],
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721,
|
|
{ fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797,
|
|
fetchStage$pipelines_0_first[64],
|
|
x_data_imm__h666240 } }),
|
|
.checkForException_regs({ fetchStage$pipelines_0_first[31],
|
|
fetchStage$pipelines_0_first[30:25],
|
|
{ fetchStage$pipelines_0_first[24],
|
|
fetchStage$pipelines_0_first[23:18] },
|
|
{ fetchStage$pipelines_0_first[17],
|
|
fetchStage$pipelines_0_first[16:12],
|
|
fetchStage$pipelines_0_first[11],
|
|
fetchStage$pipelines_0_first[10:5] } }),
|
|
.checkForException_csrState({ x_decodeInfo_frm__h648859,
|
|
x__h608823 !=
|
|
2'd0,
|
|
{ prv__h703535,
|
|
csrf_tvm_reg,
|
|
{ csrf_tw_reg,
|
|
csrf_tsr_reg,
|
|
{ csrf_mcounteren_cy_reg,
|
|
csrf_mcounteren_cy_reg &&
|
|
csrf_scounteren_cy_reg,
|
|
{ csrf_mcounteren_ir_reg,
|
|
csrf_mcounteren_ir_reg &&
|
|
csrf_scounteren_ir_reg,
|
|
{ csrf_mcounteren_tm_reg,
|
|
csrf_mcounteren_tm_reg &&
|
|
csrf_scounteren_tm_reg } } } } } }),
|
|
.checkForException(checkForException___d12829));
|
|
module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[103:99],
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275,
|
|
{ fetchStage_pipelines_1_first__2604_BIT_77_3276_ETC___d13351,
|
|
fetchStage$pipelines_1_first[64],
|
|
x_data_imm__h680279 } }),
|
|
.checkForException_regs({ fetchStage$pipelines_1_first[31],
|
|
fetchStage$pipelines_1_first[30:25],
|
|
{ fetchStage$pipelines_1_first[24],
|
|
fetchStage$pipelines_1_first[23:18] },
|
|
{ fetchStage$pipelines_1_first[17],
|
|
fetchStage$pipelines_1_first[16:12],
|
|
fetchStage$pipelines_1_first[11],
|
|
fetchStage$pipelines_1_first[10:5] } }),
|
|
.checkForException_csrState({ x_decodeInfo_frm__h648859,
|
|
x__h608823 !=
|
|
2'd0,
|
|
{ prv__h703535,
|
|
csrf_tvm_reg,
|
|
{ csrf_tw_reg,
|
|
csrf_tsr_reg,
|
|
{ csrf_mcounteren_cy_reg,
|
|
csrf_mcounteren_cy_reg &&
|
|
csrf_scounteren_cy_reg,
|
|
{ csrf_mcounteren_ir_reg,
|
|
csrf_mcounteren_ir_reg &&
|
|
csrf_scounteren_ir_reg,
|
|
{ csrf_mcounteren_tm_reg,
|
|
csrf_mcounteren_tm_reg &&
|
|
csrf_scounteren_tm_reg } } } } } }),
|
|
.checkForException(checkForException___d13372));
|
|
module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229],
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[225] }),
|
|
.execFpuSimple_rVal1(rVal1__h478908),
|
|
.execFpuSimple_rVal2(rVal2__h478909),
|
|
.execFpuSimple(execFpuSimple___d11030));
|
|
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20 =
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4241 ?
|
|
_theResult___snd__h351423 :
|
|
_theResult____h343249 ;
|
|
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55 =
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5633 ?
|
|
_theResult___snd__h397113 :
|
|
_theResult____h388941 ;
|
|
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90 =
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7025 ?
|
|
_theResult___snd__h442801 :
|
|
_theResult____h434629 ;
|
|
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130 =
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8885 ?
|
|
_theResult___snd__h508263 :
|
|
_theResult____h499964 ;
|
|
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147 =
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9595 ?
|
|
_theResult___snd__h586265 :
|
|
_theResult____h577966 ;
|
|
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170 =
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10358 ?
|
|
_theResult___snd__h547064 :
|
|
_theResult____h538765 ;
|
|
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100 =
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7576 ?
|
|
_theResult___snd__h460567 :
|
|
_theResult____h452266 ;
|
|
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30 =
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4792 ?
|
|
_theResult___snd__h369189 :
|
|
_theResult____h360888 ;
|
|
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65 =
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6184 ?
|
|
_theResult___snd__h414879 :
|
|
_theResult____h406578 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7649 ?
|
|
_theResult___snd__h451383 :
|
|
_theResult___snd__h469173 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4472 ?
|
|
_theResult___snd__h360005 :
|
|
57'd0 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4865 ?
|
|
_theResult___snd__h360005 :
|
|
_theResult___snd__h377795 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5864 ?
|
|
_theResult___snd__h405695 :
|
|
57'd0 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6257 ?
|
|
_theResult___snd__h405695 :
|
|
_theResult___snd__h423485 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7256 ?
|
|
_theResult___snd__h451383 :
|
|
57'd0 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8573 ?
|
|
_theResult___snd__h498612 :
|
|
57'd0 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8935 ?
|
|
_theResult___snd__h498612 :
|
|
_theResult___snd__h517017 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9298 ?
|
|
_theResult___snd__h576614 :
|
|
57'd0 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9645 ?
|
|
_theResult___snd__h576614 :
|
|
_theResult___snd__h595019 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10061 ?
|
|
_theResult___snd__h537413 :
|
|
57'd0 ;
|
|
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173 =
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10408 ?
|
|
_theResult___snd__h537413 :
|
|
_theResult___snd__h555818 ;
|
|
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5061 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
((_theResult___fst_exp__h351360 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5046) :
|
|
((_theResult___fst_exp__h360016 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5059) ;
|
|
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5111 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
((_theResult___fst_exp__h351360 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5102) :
|
|
((_theResult___fst_exp__h360016 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5109) ;
|
|
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6453 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
((_theResult___fst_exp__h397050 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6438) :
|
|
((_theResult___fst_exp__h405706 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6451) ;
|
|
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6503 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
((_theResult___fst_exp__h397050 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6494) :
|
|
((_theResult___fst_exp__h405706 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6501) ;
|
|
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7845 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
((_theResult___fst_exp__h442738 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7830) :
|
|
((_theResult___fst_exp__h451394 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7843) ;
|
|
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7895 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
((_theResult___fst_exp__h442738 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7886) :
|
|
((_theResult___fst_exp__h451394 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7893) ;
|
|
assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10653 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10650) :
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
|
|
assign IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9891 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9888) :
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
|
|
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4239 =
|
|
(_theResult____h343249[56] ?
|
|
6'd0 :
|
|
(_theResult____h343249[55] ?
|
|
6'd1 :
|
|
(_theResult____h343249[54] ?
|
|
6'd2 :
|
|
(_theResult____h343249[53] ?
|
|
6'd3 :
|
|
(_theResult____h343249[52] ?
|
|
6'd4 :
|
|
(_theResult____h343249[51] ?
|
|
6'd5 :
|
|
(_theResult____h343249[50] ?
|
|
6'd6 :
|
|
(_theResult____h343249[49] ?
|
|
6'd7 :
|
|
(_theResult____h343249[48] ?
|
|
6'd8 :
|
|
(_theResult____h343249[47] ?
|
|
6'd9 :
|
|
(_theResult____h343249[46] ?
|
|
6'd10 :
|
|
(_theResult____h343249[45] ?
|
|
6'd11 :
|
|
(_theResult____h343249[44] ?
|
|
6'd12 :
|
|
(_theResult____h343249[43] ?
|
|
6'd13 :
|
|
(_theResult____h343249[42] ?
|
|
6'd14 :
|
|
(_theResult____h343249[41] ?
|
|
6'd15 :
|
|
(_theResult____h343249[40] ?
|
|
6'd16 :
|
|
(_theResult____h343249[39] ?
|
|
6'd17 :
|
|
(_theResult____h343249[38] ?
|
|
6'd18 :
|
|
(_theResult____h343249[37] ?
|
|
6'd19 :
|
|
(_theResult____h343249[36] ?
|
|
6'd20 :
|
|
(_theResult____h343249[35] ?
|
|
6'd21 :
|
|
(_theResult____h343249[34] ?
|
|
6'd22 :
|
|
(_theResult____h343249[33] ?
|
|
6'd23 :
|
|
(_theResult____h343249[32] ?
|
|
6'd24 :
|
|
(_theResult____h343249[31] ?
|
|
6'd25 :
|
|
(_theResult____h343249[30] ?
|
|
6'd26 :
|
|
(_theResult____h343249[29] ?
|
|
6'd27 :
|
|
(_theResult____h343249[28] ?
|
|
6'd28 :
|
|
(_theResult____h343249[27] ?
|
|
6'd29 :
|
|
(_theResult____h343249[26] ?
|
|
6'd30 :
|
|
(_theResult____h343249[25] ?
|
|
6'd31 :
|
|
(_theResult____h343249[24] ?
|
|
6'd32 :
|
|
(_theResult____h343249[23] ?
|
|
6'd33 :
|
|
(_theResult____h343249[22] ?
|
|
6'd34 :
|
|
(_theResult____h343249[21] ?
|
|
6'd35 :
|
|
(_theResult____h343249[20] ?
|
|
6'd36 :
|
|
(_theResult____h343249[19] ?
|
|
6'd37 :
|
|
(_theResult____h343249[18] ?
|
|
6'd38 :
|
|
(_theResult____h343249[17] ?
|
|
6'd39 :
|
|
(_theResult____h343249[16] ?
|
|
6'd40 :
|
|
(_theResult____h343249[15] ?
|
|
6'd41 :
|
|
(_theResult____h343249[14] ?
|
|
6'd42 :
|
|
(_theResult____h343249[13] ?
|
|
6'd43 :
|
|
(_theResult____h343249[12] ?
|
|
6'd44 :
|
|
(_theResult____h343249[11] ?
|
|
6'd45 :
|
|
(_theResult____h343249[10] ?
|
|
6'd46 :
|
|
(_theResult____h343249[9] ?
|
|
6'd47 :
|
|
(_theResult____h343249[8] ?
|
|
6'd48 :
|
|
(_theResult____h343249[7] ?
|
|
6'd49 :
|
|
(_theResult____h343249[6] ?
|
|
6'd50 :
|
|
(_theResult____h343249[5] ?
|
|
6'd51 :
|
|
(_theResult____h343249[4] ?
|
|
6'd52 :
|
|
(_theResult____h343249[3] ?
|
|
6'd53 :
|
|
(_theResult____h343249[2] ?
|
|
6'd54 :
|
|
(_theResult____h343249[1] ?
|
|
6'd55 :
|
|
(_theResult____h343249[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5631 =
|
|
(_theResult____h388941[56] ?
|
|
6'd0 :
|
|
(_theResult____h388941[55] ?
|
|
6'd1 :
|
|
(_theResult____h388941[54] ?
|
|
6'd2 :
|
|
(_theResult____h388941[53] ?
|
|
6'd3 :
|
|
(_theResult____h388941[52] ?
|
|
6'd4 :
|
|
(_theResult____h388941[51] ?
|
|
6'd5 :
|
|
(_theResult____h388941[50] ?
|
|
6'd6 :
|
|
(_theResult____h388941[49] ?
|
|
6'd7 :
|
|
(_theResult____h388941[48] ?
|
|
6'd8 :
|
|
(_theResult____h388941[47] ?
|
|
6'd9 :
|
|
(_theResult____h388941[46] ?
|
|
6'd10 :
|
|
(_theResult____h388941[45] ?
|
|
6'd11 :
|
|
(_theResult____h388941[44] ?
|
|
6'd12 :
|
|
(_theResult____h388941[43] ?
|
|
6'd13 :
|
|
(_theResult____h388941[42] ?
|
|
6'd14 :
|
|
(_theResult____h388941[41] ?
|
|
6'd15 :
|
|
(_theResult____h388941[40] ?
|
|
6'd16 :
|
|
(_theResult____h388941[39] ?
|
|
6'd17 :
|
|
(_theResult____h388941[38] ?
|
|
6'd18 :
|
|
(_theResult____h388941[37] ?
|
|
6'd19 :
|
|
(_theResult____h388941[36] ?
|
|
6'd20 :
|
|
(_theResult____h388941[35] ?
|
|
6'd21 :
|
|
(_theResult____h388941[34] ?
|
|
6'd22 :
|
|
(_theResult____h388941[33] ?
|
|
6'd23 :
|
|
(_theResult____h388941[32] ?
|
|
6'd24 :
|
|
(_theResult____h388941[31] ?
|
|
6'd25 :
|
|
(_theResult____h388941[30] ?
|
|
6'd26 :
|
|
(_theResult____h388941[29] ?
|
|
6'd27 :
|
|
(_theResult____h388941[28] ?
|
|
6'd28 :
|
|
(_theResult____h388941[27] ?
|
|
6'd29 :
|
|
(_theResult____h388941[26] ?
|
|
6'd30 :
|
|
(_theResult____h388941[25] ?
|
|
6'd31 :
|
|
(_theResult____h388941[24] ?
|
|
6'd32 :
|
|
(_theResult____h388941[23] ?
|
|
6'd33 :
|
|
(_theResult____h388941[22] ?
|
|
6'd34 :
|
|
(_theResult____h388941[21] ?
|
|
6'd35 :
|
|
(_theResult____h388941[20] ?
|
|
6'd36 :
|
|
(_theResult____h388941[19] ?
|
|
6'd37 :
|
|
(_theResult____h388941[18] ?
|
|
6'd38 :
|
|
(_theResult____h388941[17] ?
|
|
6'd39 :
|
|
(_theResult____h388941[16] ?
|
|
6'd40 :
|
|
(_theResult____h388941[15] ?
|
|
6'd41 :
|
|
(_theResult____h388941[14] ?
|
|
6'd42 :
|
|
(_theResult____h388941[13] ?
|
|
6'd43 :
|
|
(_theResult____h388941[12] ?
|
|
6'd44 :
|
|
(_theResult____h388941[11] ?
|
|
6'd45 :
|
|
(_theResult____h388941[10] ?
|
|
6'd46 :
|
|
(_theResult____h388941[9] ?
|
|
6'd47 :
|
|
(_theResult____h388941[8] ?
|
|
6'd48 :
|
|
(_theResult____h388941[7] ?
|
|
6'd49 :
|
|
(_theResult____h388941[6] ?
|
|
6'd50 :
|
|
(_theResult____h388941[5] ?
|
|
6'd51 :
|
|
(_theResult____h388941[4] ?
|
|
6'd52 :
|
|
(_theResult____h388941[3] ?
|
|
6'd53 :
|
|
(_theResult____h388941[2] ?
|
|
6'd54 :
|
|
(_theResult____h388941[1] ?
|
|
6'd55 :
|
|
(_theResult____h388941[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7023 =
|
|
(_theResult____h434629[56] ?
|
|
6'd0 :
|
|
(_theResult____h434629[55] ?
|
|
6'd1 :
|
|
(_theResult____h434629[54] ?
|
|
6'd2 :
|
|
(_theResult____h434629[53] ?
|
|
6'd3 :
|
|
(_theResult____h434629[52] ?
|
|
6'd4 :
|
|
(_theResult____h434629[51] ?
|
|
6'd5 :
|
|
(_theResult____h434629[50] ?
|
|
6'd6 :
|
|
(_theResult____h434629[49] ?
|
|
6'd7 :
|
|
(_theResult____h434629[48] ?
|
|
6'd8 :
|
|
(_theResult____h434629[47] ?
|
|
6'd9 :
|
|
(_theResult____h434629[46] ?
|
|
6'd10 :
|
|
(_theResult____h434629[45] ?
|
|
6'd11 :
|
|
(_theResult____h434629[44] ?
|
|
6'd12 :
|
|
(_theResult____h434629[43] ?
|
|
6'd13 :
|
|
(_theResult____h434629[42] ?
|
|
6'd14 :
|
|
(_theResult____h434629[41] ?
|
|
6'd15 :
|
|
(_theResult____h434629[40] ?
|
|
6'd16 :
|
|
(_theResult____h434629[39] ?
|
|
6'd17 :
|
|
(_theResult____h434629[38] ?
|
|
6'd18 :
|
|
(_theResult____h434629[37] ?
|
|
6'd19 :
|
|
(_theResult____h434629[36] ?
|
|
6'd20 :
|
|
(_theResult____h434629[35] ?
|
|
6'd21 :
|
|
(_theResult____h434629[34] ?
|
|
6'd22 :
|
|
(_theResult____h434629[33] ?
|
|
6'd23 :
|
|
(_theResult____h434629[32] ?
|
|
6'd24 :
|
|
(_theResult____h434629[31] ?
|
|
6'd25 :
|
|
(_theResult____h434629[30] ?
|
|
6'd26 :
|
|
(_theResult____h434629[29] ?
|
|
6'd27 :
|
|
(_theResult____h434629[28] ?
|
|
6'd28 :
|
|
(_theResult____h434629[27] ?
|
|
6'd29 :
|
|
(_theResult____h434629[26] ?
|
|
6'd30 :
|
|
(_theResult____h434629[25] ?
|
|
6'd31 :
|
|
(_theResult____h434629[24] ?
|
|
6'd32 :
|
|
(_theResult____h434629[23] ?
|
|
6'd33 :
|
|
(_theResult____h434629[22] ?
|
|
6'd34 :
|
|
(_theResult____h434629[21] ?
|
|
6'd35 :
|
|
(_theResult____h434629[20] ?
|
|
6'd36 :
|
|
(_theResult____h434629[19] ?
|
|
6'd37 :
|
|
(_theResult____h434629[18] ?
|
|
6'd38 :
|
|
(_theResult____h434629[17] ?
|
|
6'd39 :
|
|
(_theResult____h434629[16] ?
|
|
6'd40 :
|
|
(_theResult____h434629[15] ?
|
|
6'd41 :
|
|
(_theResult____h434629[14] ?
|
|
6'd42 :
|
|
(_theResult____h434629[13] ?
|
|
6'd43 :
|
|
(_theResult____h434629[12] ?
|
|
6'd44 :
|
|
(_theResult____h434629[11] ?
|
|
6'd45 :
|
|
(_theResult____h434629[10] ?
|
|
6'd46 :
|
|
(_theResult____h434629[9] ?
|
|
6'd47 :
|
|
(_theResult____h434629[8] ?
|
|
6'd48 :
|
|
(_theResult____h434629[7] ?
|
|
6'd49 :
|
|
(_theResult____h434629[6] ?
|
|
6'd50 :
|
|
(_theResult____h434629[5] ?
|
|
6'd51 :
|
|
(_theResult____h434629[4] ?
|
|
6'd52 :
|
|
(_theResult____h434629[3] ?
|
|
6'd53 :
|
|
(_theResult____h434629[2] ?
|
|
6'd54 :
|
|
(_theResult____h434629[1] ?
|
|
6'd55 :
|
|
(_theResult____h434629[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10356 =
|
|
(_theResult____h538765[56] ?
|
|
6'd0 :
|
|
(_theResult____h538765[55] ?
|
|
6'd1 :
|
|
(_theResult____h538765[54] ?
|
|
6'd2 :
|
|
(_theResult____h538765[53] ?
|
|
6'd3 :
|
|
(_theResult____h538765[52] ?
|
|
6'd4 :
|
|
(_theResult____h538765[51] ?
|
|
6'd5 :
|
|
(_theResult____h538765[50] ?
|
|
6'd6 :
|
|
(_theResult____h538765[49] ?
|
|
6'd7 :
|
|
(_theResult____h538765[48] ?
|
|
6'd8 :
|
|
(_theResult____h538765[47] ?
|
|
6'd9 :
|
|
(_theResult____h538765[46] ?
|
|
6'd10 :
|
|
(_theResult____h538765[45] ?
|
|
6'd11 :
|
|
(_theResult____h538765[44] ?
|
|
6'd12 :
|
|
(_theResult____h538765[43] ?
|
|
6'd13 :
|
|
(_theResult____h538765[42] ?
|
|
6'd14 :
|
|
(_theResult____h538765[41] ?
|
|
6'd15 :
|
|
(_theResult____h538765[40] ?
|
|
6'd16 :
|
|
(_theResult____h538765[39] ?
|
|
6'd17 :
|
|
(_theResult____h538765[38] ?
|
|
6'd18 :
|
|
(_theResult____h538765[37] ?
|
|
6'd19 :
|
|
(_theResult____h538765[36] ?
|
|
6'd20 :
|
|
(_theResult____h538765[35] ?
|
|
6'd21 :
|
|
(_theResult____h538765[34] ?
|
|
6'd22 :
|
|
(_theResult____h538765[33] ?
|
|
6'd23 :
|
|
(_theResult____h538765[32] ?
|
|
6'd24 :
|
|
(_theResult____h538765[31] ?
|
|
6'd25 :
|
|
(_theResult____h538765[30] ?
|
|
6'd26 :
|
|
(_theResult____h538765[29] ?
|
|
6'd27 :
|
|
(_theResult____h538765[28] ?
|
|
6'd28 :
|
|
(_theResult____h538765[27] ?
|
|
6'd29 :
|
|
(_theResult____h538765[26] ?
|
|
6'd30 :
|
|
(_theResult____h538765[25] ?
|
|
6'd31 :
|
|
(_theResult____h538765[24] ?
|
|
6'd32 :
|
|
(_theResult____h538765[23] ?
|
|
6'd33 :
|
|
(_theResult____h538765[22] ?
|
|
6'd34 :
|
|
(_theResult____h538765[21] ?
|
|
6'd35 :
|
|
(_theResult____h538765[20] ?
|
|
6'd36 :
|
|
(_theResult____h538765[19] ?
|
|
6'd37 :
|
|
(_theResult____h538765[18] ?
|
|
6'd38 :
|
|
(_theResult____h538765[17] ?
|
|
6'd39 :
|
|
(_theResult____h538765[16] ?
|
|
6'd40 :
|
|
(_theResult____h538765[15] ?
|
|
6'd41 :
|
|
(_theResult____h538765[14] ?
|
|
6'd42 :
|
|
(_theResult____h538765[13] ?
|
|
6'd43 :
|
|
(_theResult____h538765[12] ?
|
|
6'd44 :
|
|
(_theResult____h538765[11] ?
|
|
6'd45 :
|
|
(_theResult____h538765[10] ?
|
|
6'd46 :
|
|
(_theResult____h538765[9] ?
|
|
6'd47 :
|
|
(_theResult____h538765[8] ?
|
|
6'd48 :
|
|
(_theResult____h538765[7] ?
|
|
6'd49 :
|
|
(_theResult____h538765[6] ?
|
|
6'd50 :
|
|
(_theResult____h538765[5] ?
|
|
6'd51 :
|
|
(_theResult____h538765[4] ?
|
|
6'd52 :
|
|
(_theResult____h538765[3] ?
|
|
6'd53 :
|
|
(_theResult____h538765[2] ?
|
|
6'd54 :
|
|
(_theResult____h538765[1] ?
|
|
6'd55 :
|
|
(_theResult____h538765[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8883 =
|
|
(_theResult____h499964[56] ?
|
|
6'd0 :
|
|
(_theResult____h499964[55] ?
|
|
6'd1 :
|
|
(_theResult____h499964[54] ?
|
|
6'd2 :
|
|
(_theResult____h499964[53] ?
|
|
6'd3 :
|
|
(_theResult____h499964[52] ?
|
|
6'd4 :
|
|
(_theResult____h499964[51] ?
|
|
6'd5 :
|
|
(_theResult____h499964[50] ?
|
|
6'd6 :
|
|
(_theResult____h499964[49] ?
|
|
6'd7 :
|
|
(_theResult____h499964[48] ?
|
|
6'd8 :
|
|
(_theResult____h499964[47] ?
|
|
6'd9 :
|
|
(_theResult____h499964[46] ?
|
|
6'd10 :
|
|
(_theResult____h499964[45] ?
|
|
6'd11 :
|
|
(_theResult____h499964[44] ?
|
|
6'd12 :
|
|
(_theResult____h499964[43] ?
|
|
6'd13 :
|
|
(_theResult____h499964[42] ?
|
|
6'd14 :
|
|
(_theResult____h499964[41] ?
|
|
6'd15 :
|
|
(_theResult____h499964[40] ?
|
|
6'd16 :
|
|
(_theResult____h499964[39] ?
|
|
6'd17 :
|
|
(_theResult____h499964[38] ?
|
|
6'd18 :
|
|
(_theResult____h499964[37] ?
|
|
6'd19 :
|
|
(_theResult____h499964[36] ?
|
|
6'd20 :
|
|
(_theResult____h499964[35] ?
|
|
6'd21 :
|
|
(_theResult____h499964[34] ?
|
|
6'd22 :
|
|
(_theResult____h499964[33] ?
|
|
6'd23 :
|
|
(_theResult____h499964[32] ?
|
|
6'd24 :
|
|
(_theResult____h499964[31] ?
|
|
6'd25 :
|
|
(_theResult____h499964[30] ?
|
|
6'd26 :
|
|
(_theResult____h499964[29] ?
|
|
6'd27 :
|
|
(_theResult____h499964[28] ?
|
|
6'd28 :
|
|
(_theResult____h499964[27] ?
|
|
6'd29 :
|
|
(_theResult____h499964[26] ?
|
|
6'd30 :
|
|
(_theResult____h499964[25] ?
|
|
6'd31 :
|
|
(_theResult____h499964[24] ?
|
|
6'd32 :
|
|
(_theResult____h499964[23] ?
|
|
6'd33 :
|
|
(_theResult____h499964[22] ?
|
|
6'd34 :
|
|
(_theResult____h499964[21] ?
|
|
6'd35 :
|
|
(_theResult____h499964[20] ?
|
|
6'd36 :
|
|
(_theResult____h499964[19] ?
|
|
6'd37 :
|
|
(_theResult____h499964[18] ?
|
|
6'd38 :
|
|
(_theResult____h499964[17] ?
|
|
6'd39 :
|
|
(_theResult____h499964[16] ?
|
|
6'd40 :
|
|
(_theResult____h499964[15] ?
|
|
6'd41 :
|
|
(_theResult____h499964[14] ?
|
|
6'd42 :
|
|
(_theResult____h499964[13] ?
|
|
6'd43 :
|
|
(_theResult____h499964[12] ?
|
|
6'd44 :
|
|
(_theResult____h499964[11] ?
|
|
6'd45 :
|
|
(_theResult____h499964[10] ?
|
|
6'd46 :
|
|
(_theResult____h499964[9] ?
|
|
6'd47 :
|
|
(_theResult____h499964[8] ?
|
|
6'd48 :
|
|
(_theResult____h499964[7] ?
|
|
6'd49 :
|
|
(_theResult____h499964[6] ?
|
|
6'd50 :
|
|
(_theResult____h499964[5] ?
|
|
6'd51 :
|
|
(_theResult____h499964[4] ?
|
|
6'd52 :
|
|
(_theResult____h499964[3] ?
|
|
6'd53 :
|
|
(_theResult____h499964[2] ?
|
|
6'd54 :
|
|
(_theResult____h499964[1] ?
|
|
6'd55 :
|
|
(_theResult____h499964[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9593 =
|
|
(_theResult____h577966[56] ?
|
|
6'd0 :
|
|
(_theResult____h577966[55] ?
|
|
6'd1 :
|
|
(_theResult____h577966[54] ?
|
|
6'd2 :
|
|
(_theResult____h577966[53] ?
|
|
6'd3 :
|
|
(_theResult____h577966[52] ?
|
|
6'd4 :
|
|
(_theResult____h577966[51] ?
|
|
6'd5 :
|
|
(_theResult____h577966[50] ?
|
|
6'd6 :
|
|
(_theResult____h577966[49] ?
|
|
6'd7 :
|
|
(_theResult____h577966[48] ?
|
|
6'd8 :
|
|
(_theResult____h577966[47] ?
|
|
6'd9 :
|
|
(_theResult____h577966[46] ?
|
|
6'd10 :
|
|
(_theResult____h577966[45] ?
|
|
6'd11 :
|
|
(_theResult____h577966[44] ?
|
|
6'd12 :
|
|
(_theResult____h577966[43] ?
|
|
6'd13 :
|
|
(_theResult____h577966[42] ?
|
|
6'd14 :
|
|
(_theResult____h577966[41] ?
|
|
6'd15 :
|
|
(_theResult____h577966[40] ?
|
|
6'd16 :
|
|
(_theResult____h577966[39] ?
|
|
6'd17 :
|
|
(_theResult____h577966[38] ?
|
|
6'd18 :
|
|
(_theResult____h577966[37] ?
|
|
6'd19 :
|
|
(_theResult____h577966[36] ?
|
|
6'd20 :
|
|
(_theResult____h577966[35] ?
|
|
6'd21 :
|
|
(_theResult____h577966[34] ?
|
|
6'd22 :
|
|
(_theResult____h577966[33] ?
|
|
6'd23 :
|
|
(_theResult____h577966[32] ?
|
|
6'd24 :
|
|
(_theResult____h577966[31] ?
|
|
6'd25 :
|
|
(_theResult____h577966[30] ?
|
|
6'd26 :
|
|
(_theResult____h577966[29] ?
|
|
6'd27 :
|
|
(_theResult____h577966[28] ?
|
|
6'd28 :
|
|
(_theResult____h577966[27] ?
|
|
6'd29 :
|
|
(_theResult____h577966[26] ?
|
|
6'd30 :
|
|
(_theResult____h577966[25] ?
|
|
6'd31 :
|
|
(_theResult____h577966[24] ?
|
|
6'd32 :
|
|
(_theResult____h577966[23] ?
|
|
6'd33 :
|
|
(_theResult____h577966[22] ?
|
|
6'd34 :
|
|
(_theResult____h577966[21] ?
|
|
6'd35 :
|
|
(_theResult____h577966[20] ?
|
|
6'd36 :
|
|
(_theResult____h577966[19] ?
|
|
6'd37 :
|
|
(_theResult____h577966[18] ?
|
|
6'd38 :
|
|
(_theResult____h577966[17] ?
|
|
6'd39 :
|
|
(_theResult____h577966[16] ?
|
|
6'd40 :
|
|
(_theResult____h577966[15] ?
|
|
6'd41 :
|
|
(_theResult____h577966[14] ?
|
|
6'd42 :
|
|
(_theResult____h577966[13] ?
|
|
6'd43 :
|
|
(_theResult____h577966[12] ?
|
|
6'd44 :
|
|
(_theResult____h577966[11] ?
|
|
6'd45 :
|
|
(_theResult____h577966[10] ?
|
|
6'd46 :
|
|
(_theResult____h577966[9] ?
|
|
6'd47 :
|
|
(_theResult____h577966[8] ?
|
|
6'd48 :
|
|
(_theResult____h577966[7] ?
|
|
6'd49 :
|
|
(_theResult____h577966[6] ?
|
|
6'd50 :
|
|
(_theResult____h577966[5] ?
|
|
6'd51 :
|
|
(_theResult____h577966[4] ?
|
|
6'd52 :
|
|
(_theResult____h577966[3] ?
|
|
6'd53 :
|
|
(_theResult____h577966[2] ?
|
|
6'd54 :
|
|
(_theResult____h577966[1] ?
|
|
6'd55 :
|
|
(_theResult____h577966[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4790 =
|
|
(_theResult____h360888[56] ?
|
|
6'd0 :
|
|
(_theResult____h360888[55] ?
|
|
6'd1 :
|
|
(_theResult____h360888[54] ?
|
|
6'd2 :
|
|
(_theResult____h360888[53] ?
|
|
6'd3 :
|
|
(_theResult____h360888[52] ?
|
|
6'd4 :
|
|
(_theResult____h360888[51] ?
|
|
6'd5 :
|
|
(_theResult____h360888[50] ?
|
|
6'd6 :
|
|
(_theResult____h360888[49] ?
|
|
6'd7 :
|
|
(_theResult____h360888[48] ?
|
|
6'd8 :
|
|
(_theResult____h360888[47] ?
|
|
6'd9 :
|
|
(_theResult____h360888[46] ?
|
|
6'd10 :
|
|
(_theResult____h360888[45] ?
|
|
6'd11 :
|
|
(_theResult____h360888[44] ?
|
|
6'd12 :
|
|
(_theResult____h360888[43] ?
|
|
6'd13 :
|
|
(_theResult____h360888[42] ?
|
|
6'd14 :
|
|
(_theResult____h360888[41] ?
|
|
6'd15 :
|
|
(_theResult____h360888[40] ?
|
|
6'd16 :
|
|
(_theResult____h360888[39] ?
|
|
6'd17 :
|
|
(_theResult____h360888[38] ?
|
|
6'd18 :
|
|
(_theResult____h360888[37] ?
|
|
6'd19 :
|
|
(_theResult____h360888[36] ?
|
|
6'd20 :
|
|
(_theResult____h360888[35] ?
|
|
6'd21 :
|
|
(_theResult____h360888[34] ?
|
|
6'd22 :
|
|
(_theResult____h360888[33] ?
|
|
6'd23 :
|
|
(_theResult____h360888[32] ?
|
|
6'd24 :
|
|
(_theResult____h360888[31] ?
|
|
6'd25 :
|
|
(_theResult____h360888[30] ?
|
|
6'd26 :
|
|
(_theResult____h360888[29] ?
|
|
6'd27 :
|
|
(_theResult____h360888[28] ?
|
|
6'd28 :
|
|
(_theResult____h360888[27] ?
|
|
6'd29 :
|
|
(_theResult____h360888[26] ?
|
|
6'd30 :
|
|
(_theResult____h360888[25] ?
|
|
6'd31 :
|
|
(_theResult____h360888[24] ?
|
|
6'd32 :
|
|
(_theResult____h360888[23] ?
|
|
6'd33 :
|
|
(_theResult____h360888[22] ?
|
|
6'd34 :
|
|
(_theResult____h360888[21] ?
|
|
6'd35 :
|
|
(_theResult____h360888[20] ?
|
|
6'd36 :
|
|
(_theResult____h360888[19] ?
|
|
6'd37 :
|
|
(_theResult____h360888[18] ?
|
|
6'd38 :
|
|
(_theResult____h360888[17] ?
|
|
6'd39 :
|
|
(_theResult____h360888[16] ?
|
|
6'd40 :
|
|
(_theResult____h360888[15] ?
|
|
6'd41 :
|
|
(_theResult____h360888[14] ?
|
|
6'd42 :
|
|
(_theResult____h360888[13] ?
|
|
6'd43 :
|
|
(_theResult____h360888[12] ?
|
|
6'd44 :
|
|
(_theResult____h360888[11] ?
|
|
6'd45 :
|
|
(_theResult____h360888[10] ?
|
|
6'd46 :
|
|
(_theResult____h360888[9] ?
|
|
6'd47 :
|
|
(_theResult____h360888[8] ?
|
|
6'd48 :
|
|
(_theResult____h360888[7] ?
|
|
6'd49 :
|
|
(_theResult____h360888[6] ?
|
|
6'd50 :
|
|
(_theResult____h360888[5] ?
|
|
6'd51 :
|
|
(_theResult____h360888[4] ?
|
|
6'd52 :
|
|
(_theResult____h360888[3] ?
|
|
6'd53 :
|
|
(_theResult____h360888[2] ?
|
|
6'd54 :
|
|
(_theResult____h360888[1] ?
|
|
6'd55 :
|
|
(_theResult____h360888[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6182 =
|
|
(_theResult____h406578[56] ?
|
|
6'd0 :
|
|
(_theResult____h406578[55] ?
|
|
6'd1 :
|
|
(_theResult____h406578[54] ?
|
|
6'd2 :
|
|
(_theResult____h406578[53] ?
|
|
6'd3 :
|
|
(_theResult____h406578[52] ?
|
|
6'd4 :
|
|
(_theResult____h406578[51] ?
|
|
6'd5 :
|
|
(_theResult____h406578[50] ?
|
|
6'd6 :
|
|
(_theResult____h406578[49] ?
|
|
6'd7 :
|
|
(_theResult____h406578[48] ?
|
|
6'd8 :
|
|
(_theResult____h406578[47] ?
|
|
6'd9 :
|
|
(_theResult____h406578[46] ?
|
|
6'd10 :
|
|
(_theResult____h406578[45] ?
|
|
6'd11 :
|
|
(_theResult____h406578[44] ?
|
|
6'd12 :
|
|
(_theResult____h406578[43] ?
|
|
6'd13 :
|
|
(_theResult____h406578[42] ?
|
|
6'd14 :
|
|
(_theResult____h406578[41] ?
|
|
6'd15 :
|
|
(_theResult____h406578[40] ?
|
|
6'd16 :
|
|
(_theResult____h406578[39] ?
|
|
6'd17 :
|
|
(_theResult____h406578[38] ?
|
|
6'd18 :
|
|
(_theResult____h406578[37] ?
|
|
6'd19 :
|
|
(_theResult____h406578[36] ?
|
|
6'd20 :
|
|
(_theResult____h406578[35] ?
|
|
6'd21 :
|
|
(_theResult____h406578[34] ?
|
|
6'd22 :
|
|
(_theResult____h406578[33] ?
|
|
6'd23 :
|
|
(_theResult____h406578[32] ?
|
|
6'd24 :
|
|
(_theResult____h406578[31] ?
|
|
6'd25 :
|
|
(_theResult____h406578[30] ?
|
|
6'd26 :
|
|
(_theResult____h406578[29] ?
|
|
6'd27 :
|
|
(_theResult____h406578[28] ?
|
|
6'd28 :
|
|
(_theResult____h406578[27] ?
|
|
6'd29 :
|
|
(_theResult____h406578[26] ?
|
|
6'd30 :
|
|
(_theResult____h406578[25] ?
|
|
6'd31 :
|
|
(_theResult____h406578[24] ?
|
|
6'd32 :
|
|
(_theResult____h406578[23] ?
|
|
6'd33 :
|
|
(_theResult____h406578[22] ?
|
|
6'd34 :
|
|
(_theResult____h406578[21] ?
|
|
6'd35 :
|
|
(_theResult____h406578[20] ?
|
|
6'd36 :
|
|
(_theResult____h406578[19] ?
|
|
6'd37 :
|
|
(_theResult____h406578[18] ?
|
|
6'd38 :
|
|
(_theResult____h406578[17] ?
|
|
6'd39 :
|
|
(_theResult____h406578[16] ?
|
|
6'd40 :
|
|
(_theResult____h406578[15] ?
|
|
6'd41 :
|
|
(_theResult____h406578[14] ?
|
|
6'd42 :
|
|
(_theResult____h406578[13] ?
|
|
6'd43 :
|
|
(_theResult____h406578[12] ?
|
|
6'd44 :
|
|
(_theResult____h406578[11] ?
|
|
6'd45 :
|
|
(_theResult____h406578[10] ?
|
|
6'd46 :
|
|
(_theResult____h406578[9] ?
|
|
6'd47 :
|
|
(_theResult____h406578[8] ?
|
|
6'd48 :
|
|
(_theResult____h406578[7] ?
|
|
6'd49 :
|
|
(_theResult____h406578[6] ?
|
|
6'd50 :
|
|
(_theResult____h406578[5] ?
|
|
6'd51 :
|
|
(_theResult____h406578[4] ?
|
|
6'd52 :
|
|
(_theResult____h406578[3] ?
|
|
6'd53 :
|
|
(_theResult____h406578[2] ?
|
|
6'd54 :
|
|
(_theResult____h406578[1] ?
|
|
6'd55 :
|
|
(_theResult____h406578[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7574 =
|
|
(_theResult____h452266[56] ?
|
|
6'd0 :
|
|
(_theResult____h452266[55] ?
|
|
6'd1 :
|
|
(_theResult____h452266[54] ?
|
|
6'd2 :
|
|
(_theResult____h452266[53] ?
|
|
6'd3 :
|
|
(_theResult____h452266[52] ?
|
|
6'd4 :
|
|
(_theResult____h452266[51] ?
|
|
6'd5 :
|
|
(_theResult____h452266[50] ?
|
|
6'd6 :
|
|
(_theResult____h452266[49] ?
|
|
6'd7 :
|
|
(_theResult____h452266[48] ?
|
|
6'd8 :
|
|
(_theResult____h452266[47] ?
|
|
6'd9 :
|
|
(_theResult____h452266[46] ?
|
|
6'd10 :
|
|
(_theResult____h452266[45] ?
|
|
6'd11 :
|
|
(_theResult____h452266[44] ?
|
|
6'd12 :
|
|
(_theResult____h452266[43] ?
|
|
6'd13 :
|
|
(_theResult____h452266[42] ?
|
|
6'd14 :
|
|
(_theResult____h452266[41] ?
|
|
6'd15 :
|
|
(_theResult____h452266[40] ?
|
|
6'd16 :
|
|
(_theResult____h452266[39] ?
|
|
6'd17 :
|
|
(_theResult____h452266[38] ?
|
|
6'd18 :
|
|
(_theResult____h452266[37] ?
|
|
6'd19 :
|
|
(_theResult____h452266[36] ?
|
|
6'd20 :
|
|
(_theResult____h452266[35] ?
|
|
6'd21 :
|
|
(_theResult____h452266[34] ?
|
|
6'd22 :
|
|
(_theResult____h452266[33] ?
|
|
6'd23 :
|
|
(_theResult____h452266[32] ?
|
|
6'd24 :
|
|
(_theResult____h452266[31] ?
|
|
6'd25 :
|
|
(_theResult____h452266[30] ?
|
|
6'd26 :
|
|
(_theResult____h452266[29] ?
|
|
6'd27 :
|
|
(_theResult____h452266[28] ?
|
|
6'd28 :
|
|
(_theResult____h452266[27] ?
|
|
6'd29 :
|
|
(_theResult____h452266[26] ?
|
|
6'd30 :
|
|
(_theResult____h452266[25] ?
|
|
6'd31 :
|
|
(_theResult____h452266[24] ?
|
|
6'd32 :
|
|
(_theResult____h452266[23] ?
|
|
6'd33 :
|
|
(_theResult____h452266[22] ?
|
|
6'd34 :
|
|
(_theResult____h452266[21] ?
|
|
6'd35 :
|
|
(_theResult____h452266[20] ?
|
|
6'd36 :
|
|
(_theResult____h452266[19] ?
|
|
6'd37 :
|
|
(_theResult____h452266[18] ?
|
|
6'd38 :
|
|
(_theResult____h452266[17] ?
|
|
6'd39 :
|
|
(_theResult____h452266[16] ?
|
|
6'd40 :
|
|
(_theResult____h452266[15] ?
|
|
6'd41 :
|
|
(_theResult____h452266[14] ?
|
|
6'd42 :
|
|
(_theResult____h452266[13] ?
|
|
6'd43 :
|
|
(_theResult____h452266[12] ?
|
|
6'd44 :
|
|
(_theResult____h452266[11] ?
|
|
6'd45 :
|
|
(_theResult____h452266[10] ?
|
|
6'd46 :
|
|
(_theResult____h452266[9] ?
|
|
6'd47 :
|
|
(_theResult____h452266[8] ?
|
|
6'd48 :
|
|
(_theResult____h452266[7] ?
|
|
6'd49 :
|
|
(_theResult____h452266[6] ?
|
|
6'd50 :
|
|
(_theResult____h452266[5] ?
|
|
6'd51 :
|
|
(_theResult____h452266[4] ?
|
|
6'd52 :
|
|
(_theResult____h452266[3] ?
|
|
6'd53 :
|
|
(_theResult____h452266[2] ?
|
|
6'd54 :
|
|
(_theResult____h452266[1] ?
|
|
6'd55 :
|
|
(_theResult____h452266[0] ?
|
|
6'd56 :
|
|
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
|
|
6'd1 ;
|
|
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10400 =
|
|
(_theResult___fst_exp__h547001 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard38775_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186) ;
|
|
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10665 =
|
|
(_theResult___fst_exp__h547001 == 11'd2047) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard38775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192) ;
|
|
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8927 =
|
|
(_theResult___fst_exp__h508200 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard99974_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142) ;
|
|
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9637 =
|
|
(_theResult___fst_exp__h586202 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard77976_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157) ;
|
|
assign IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9903 =
|
|
(_theResult___fst_exp__h586202 == 11'd2047) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard77976_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161) ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4302 =
|
|
(guard__h343259 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
_theResult___fst_exp__h351360 :
|
|
_theResult___exp__h351876 ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4305 =
|
|
(guard__h343259 == 2'b0) ?
|
|
_theResult___fst_exp__h351360 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___exp__h351876 :
|
|
_theResult___fst_exp__h351360) ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4949 =
|
|
(guard__h343259 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
sfdin__h351354[56:34] :
|
|
_theResult___sfd__h351877 ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4951 =
|
|
(guard__h343259 == 2'b0) ?
|
|
sfdin__h351354[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___sfd__h351877 :
|
|
sfdin__h351354[56:34]) ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5694 =
|
|
(guard__h388951 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
_theResult___fst_exp__h397050 :
|
|
_theResult___exp__h397566 ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5697 =
|
|
(guard__h388951 == 2'b0) ?
|
|
_theResult___fst_exp__h397050 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___exp__h397566 :
|
|
_theResult___fst_exp__h397050) ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6341 =
|
|
(guard__h388951 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
sfdin__h397044[56:34] :
|
|
_theResult___sfd__h397567 ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6343 =
|
|
(guard__h388951 == 2'b0) ?
|
|
sfdin__h397044[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___sfd__h397567 :
|
|
sfdin__h397044[56:34]) ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7086 =
|
|
(guard__h434639 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
_theResult___fst_exp__h442738 :
|
|
_theResult___exp__h443254 ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7089 =
|
|
(guard__h434639 == 2'b0) ?
|
|
_theResult___fst_exp__h442738 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___exp__h443254 :
|
|
_theResult___fst_exp__h442738) ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7733 =
|
|
(guard__h434639 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
sfdin__h442732[56:34] :
|
|
_theResult___sfd__h443255 ;
|
|
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7735 =
|
|
(guard__h434639 == 2'b0) ?
|
|
sfdin__h442732[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___sfd__h443255 :
|
|
sfdin__h442732[56:34]) ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10512 =
|
|
(guard__h538775 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
|
|
_theResult___fst_exp__h547001 :
|
|
_theResult___exp__h547730 ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10514 =
|
|
(guard__h538775 == 2'b0) ?
|
|
_theResult___fst_exp__h547001 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
_theResult___exp__h547730 :
|
|
_theResult___fst_exp__h547001) ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10595 =
|
|
(guard__h538775 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
|
|
sfdin__h546995[56:5] :
|
|
_theResult___sfd__h547731 ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10597 =
|
|
(guard__h538775 == 2'b0) ?
|
|
sfdin__h546995[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
_theResult___sfd__h547731 :
|
|
sfdin__h546995[56:5]) ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9044 =
|
|
(guard__h499974 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
|
|
_theResult___fst_exp__h508200 :
|
|
_theResult___exp__h508929 ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9046 =
|
|
(guard__h499974 == 2'b0) ?
|
|
_theResult___fst_exp__h508200 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
_theResult___exp__h508929 :
|
|
_theResult___fst_exp__h508200) ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128 =
|
|
(guard__h499974 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
|
|
sfdin__h508194[56:5] :
|
|
_theResult___sfd__h508930 ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9130 =
|
|
(guard__h499974 == 2'b0) ?
|
|
sfdin__h508194[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
_theResult___sfd__h508930 :
|
|
sfdin__h508194[56:5]) ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9749 =
|
|
(guard__h577976 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
|
|
_theResult___fst_exp__h586202 :
|
|
_theResult___exp__h586931 ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9751 =
|
|
(guard__h577976 == 2'b0) ?
|
|
_theResult___fst_exp__h586202 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
_theResult___exp__h586931 :
|
|
_theResult___fst_exp__h586202) ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9832 =
|
|
(guard__h577976 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
|
|
sfdin__h586196[56:5] :
|
|
_theResult___sfd__h586932 ;
|
|
assign IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9834 =
|
|
(guard__h577976 == 2'b0) ?
|
|
sfdin__h586196[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
_theResult___sfd__h586932 :
|
|
sfdin__h586196[56:5]) ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4849 =
|
|
(guard__h360898 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
_theResult___fst_exp__h369126 :
|
|
_theResult___exp__h369642 ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4851 =
|
|
(guard__h360898 == 2'b0) ?
|
|
_theResult___fst_exp__h369126 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___exp__h369642 :
|
|
_theResult___fst_exp__h369126) ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4995 =
|
|
(guard__h360898 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
sfdin__h369120[56:34] :
|
|
_theResult___sfd__h369643 ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4997 =
|
|
(guard__h360898 == 2'b0) ?
|
|
sfdin__h369120[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___sfd__h369643 :
|
|
sfdin__h369120[56:34]) ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6241 =
|
|
(guard__h406588 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
_theResult___fst_exp__h414816 :
|
|
_theResult___exp__h415332 ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6243 =
|
|
(guard__h406588 == 2'b0) ?
|
|
_theResult___fst_exp__h414816 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___exp__h415332 :
|
|
_theResult___fst_exp__h414816) ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6387 =
|
|
(guard__h406588 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
sfdin__h414810[56:34] :
|
|
_theResult___sfd__h415333 ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6389 =
|
|
(guard__h406588 == 2'b0) ?
|
|
sfdin__h414810[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___sfd__h415333 :
|
|
sfdin__h414810[56:34]) ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7633 =
|
|
(guard__h452276 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
_theResult___fst_exp__h460504 :
|
|
_theResult___exp__h461020 ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7635 =
|
|
(guard__h452276 == 2'b0) ?
|
|
_theResult___fst_exp__h460504 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___exp__h461020 :
|
|
_theResult___fst_exp__h460504) ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7779 =
|
|
(guard__h452276 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
sfdin__h460498[56:34] :
|
|
_theResult___sfd__h461021 ;
|
|
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7781 =
|
|
(guard__h452276 == 2'b0) ?
|
|
sfdin__h460498[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___sfd__h461021 :
|
|
sfdin__h460498[56:34]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4524 =
|
|
(guard__h351968 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
_theResult___fst_exp__h360016 :
|
|
_theResult___exp__h360458 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4526 =
|
|
(guard__h351968 == 2'b0) ?
|
|
_theResult___fst_exp__h360016 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___exp__h360458 :
|
|
_theResult___fst_exp__h360016) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4918 =
|
|
(guard__h369734 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
_theResult___fst_exp__h377811 :
|
|
_theResult___exp__h378278 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4920 =
|
|
(guard__h369734 == 2'b0) ?
|
|
_theResult___fst_exp__h377811 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___exp__h378278 :
|
|
_theResult___fst_exp__h377811) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4968 =
|
|
(guard__h351968 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
_theResult___snd__h359967[56:34] :
|
|
_theResult___sfd__h360459 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4970 =
|
|
(guard__h351968 == 2'b0) ?
|
|
_theResult___snd__h359967[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___sfd__h360459 :
|
|
_theResult___snd__h359967[56:34]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5014 =
|
|
(guard__h369734 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
|
|
_theResult___snd__h377757[56:34] :
|
|
_theResult___sfd__h378279 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5016 =
|
|
(guard__h369734 == 2'b0) ?
|
|
_theResult___snd__h377757[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
_theResult___sfd__h378279 :
|
|
_theResult___snd__h377757[56:34]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5916 =
|
|
(guard__h397658 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
_theResult___fst_exp__h405706 :
|
|
_theResult___exp__h406148 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5918 =
|
|
(guard__h397658 == 2'b0) ?
|
|
_theResult___fst_exp__h405706 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___exp__h406148 :
|
|
_theResult___fst_exp__h405706) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6310 =
|
|
(guard__h415424 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
_theResult___fst_exp__h423501 :
|
|
_theResult___exp__h423968 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6312 =
|
|
(guard__h415424 == 2'b0) ?
|
|
_theResult___fst_exp__h423501 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___exp__h423968 :
|
|
_theResult___fst_exp__h423501) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6360 =
|
|
(guard__h397658 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
_theResult___snd__h405657[56:34] :
|
|
_theResult___sfd__h406149 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6362 =
|
|
(guard__h397658 == 2'b0) ?
|
|
_theResult___snd__h405657[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___sfd__h406149 :
|
|
_theResult___snd__h405657[56:34]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6406 =
|
|
(guard__h415424 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
|
|
_theResult___snd__h423447[56:34] :
|
|
_theResult___sfd__h423969 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6408 =
|
|
(guard__h415424 == 2'b0) ?
|
|
_theResult___snd__h423447[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
_theResult___sfd__h423969 :
|
|
_theResult___snd__h423447[56:34]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7308 =
|
|
(guard__h443346 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
_theResult___fst_exp__h451394 :
|
|
_theResult___exp__h451836 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7310 =
|
|
(guard__h443346 == 2'b0) ?
|
|
_theResult___fst_exp__h451394 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___exp__h451836 :
|
|
_theResult___fst_exp__h451394) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7702 =
|
|
(guard__h461112 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
_theResult___fst_exp__h469189 :
|
|
_theResult___exp__h469656 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7704 =
|
|
(guard__h461112 == 2'b0) ?
|
|
_theResult___fst_exp__h469189 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___exp__h469656 :
|
|
_theResult___fst_exp__h469189) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7752 =
|
|
(guard__h443346 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
_theResult___snd__h451345[56:34] :
|
|
_theResult___sfd__h451837 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7754 =
|
|
(guard__h443346 == 2'b0) ?
|
|
_theResult___snd__h451345[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___sfd__h451837 :
|
|
_theResult___snd__h451345[56:34]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7798 =
|
|
(guard__h461112 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
|
|
_theResult___snd__h469135[56:34] :
|
|
_theResult___sfd__h469657 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7800 =
|
|
(guard__h461112 == 2'b0) ?
|
|
_theResult___snd__h469135[56:34] :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
_theResult___sfd__h469657 :
|
|
_theResult___snd__h469135[56:34]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10474 =
|
|
(guard__h529463 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
|
|
_theResult___fst_exp__h537424 :
|
|
_theResult___exp__h538079 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10476 =
|
|
(guard__h529463 == 2'b0) ?
|
|
_theResult___fst_exp__h537424 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
_theResult___exp__h538079 :
|
|
_theResult___fst_exp__h537424) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10543 =
|
|
(guard__h547844 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
|
|
_theResult___fst_exp__h555834 :
|
|
_theResult___exp__h556514 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10545 =
|
|
(guard__h547844 == 2'b0) ?
|
|
_theResult___fst_exp__h555834 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
_theResult___exp__h556514 :
|
|
_theResult___fst_exp__h555834) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10569 =
|
|
(guard__h529463 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
|
|
_theResult___snd__h537375[56:5] :
|
|
_theResult___sfd__h538080 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10571 =
|
|
(guard__h529463 == 2'b0) ?
|
|
_theResult___snd__h537375[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
_theResult___sfd__h538080 :
|
|
_theResult___snd__h537375[56:5]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10614 =
|
|
(guard__h547844 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
|
|
_theResult___snd__h555780[56:5] :
|
|
_theResult___sfd__h556515 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10616 =
|
|
(guard__h547844 == 2'b0) ?
|
|
_theResult___snd__h555780[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
_theResult___sfd__h556515 :
|
|
_theResult___snd__h555780[56:5]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9001 =
|
|
(guard__h490662 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
|
|
_theResult___fst_exp__h498623 :
|
|
_theResult___exp__h499278 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9003 =
|
|
(guard__h490662 == 2'b0) ?
|
|
_theResult___fst_exp__h498623 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
_theResult___exp__h499278 :
|
|
_theResult___fst_exp__h498623) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9075 =
|
|
(guard__h509043 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
|
|
_theResult___fst_exp__h517033 :
|
|
_theResult___exp__h517713 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9077 =
|
|
(guard__h509043 == 2'b0) ?
|
|
_theResult___fst_exp__h517033 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
_theResult___exp__h517713 :
|
|
_theResult___fst_exp__h517033) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9101 =
|
|
(guard__h490662 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
|
|
_theResult___snd__h498574[56:5] :
|
|
_theResult___sfd__h499279 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9103 =
|
|
(guard__h490662 == 2'b0) ?
|
|
_theResult___snd__h498574[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
_theResult___sfd__h499279 :
|
|
_theResult___snd__h498574[56:5]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9147 =
|
|
(guard__h509043 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
|
|
_theResult___snd__h516979[56:5] :
|
|
_theResult___sfd__h517714 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9149 =
|
|
(guard__h509043 == 2'b0) ?
|
|
_theResult___snd__h516979[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
_theResult___sfd__h517714 :
|
|
_theResult___snd__h516979[56:5]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9711 =
|
|
(guard__h568664 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
|
|
_theResult___fst_exp__h576625 :
|
|
_theResult___exp__h577280 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9713 =
|
|
(guard__h568664 == 2'b0) ?
|
|
_theResult___fst_exp__h576625 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
_theResult___exp__h577280 :
|
|
_theResult___fst_exp__h576625) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9780 =
|
|
(guard__h587045 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
|
|
_theResult___fst_exp__h595035 :
|
|
_theResult___exp__h595715 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9782 =
|
|
(guard__h587045 == 2'b0) ?
|
|
_theResult___fst_exp__h595035 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
_theResult___exp__h595715 :
|
|
_theResult___fst_exp__h595035) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9806 =
|
|
(guard__h568664 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
|
|
_theResult___snd__h576576[56:5] :
|
|
_theResult___sfd__h577281 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9808 =
|
|
(guard__h568664 == 2'b0) ?
|
|
_theResult___snd__h576576[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
_theResult___sfd__h577281 :
|
|
_theResult___snd__h576576[56:5]) ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9851 =
|
|
(guard__h587045 == 2'b0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
|
|
_theResult___snd__h594981[56:5] :
|
|
_theResult___sfd__h595716 ;
|
|
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9853 =
|
|
(guard__h587045 == 2'b0) ?
|
|
_theResult___snd__h594981[56:5] :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
_theResult___sfd__h595716 :
|
|
_theResult___snd__h594981[56:5]) ;
|
|
assign IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664 =
|
|
(_theResult____h645120 == 15'd0 &&
|
|
(csrf_prv_reg == 2'd0 ||
|
|
csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ?
|
|
enabled_ints__h645664 :
|
|
_theResult____h645120 ;
|
|
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10446 =
|
|
(_theResult___fst_exp__h555834 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard47844_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190) ;
|
|
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10650 =
|
|
(_theResult___fst_exp__h537424 == 11'd2047) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard29463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ;
|
|
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10677 =
|
|
(_theResult___fst_exp__h555834 == 11'd2047) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard47844_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ;
|
|
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8973 =
|
|
(_theResult___fst_exp__h517033 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard09043_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140) ;
|
|
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9683 =
|
|
(_theResult___fst_exp__h595035 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard87045_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159) ;
|
|
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9888 =
|
|
(_theResult___fst_exp__h576625 == 11'd2047) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard68664_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ;
|
|
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9915 =
|
|
(_theResult___fst_exp__h595035 == 11'd2047) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard87045_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ;
|
|
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1843 =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 ?
|
|
4'd11 :
|
|
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ?
|
|
4'd12 :
|
|
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 ?
|
|
4'd13 :
|
|
4'd15)) ;
|
|
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1845 =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 ?
|
|
4'd8 :
|
|
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 ?
|
|
4'd9 :
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1843) ;
|
|
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 ?
|
|
4'd6 :
|
|
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 ?
|
|
4'd7 :
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1845) ;
|
|
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849 =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 ?
|
|
4'd4 :
|
|
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 ?
|
|
4'd5 :
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847) ;
|
|
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851 =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 ?
|
|
4'd2 :
|
|
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 ?
|
|
4'd3 :
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849) ;
|
|
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853 =
|
|
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1792 ?
|
|
4'd0 :
|
|
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 ?
|
|
4'd1 :
|
|
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851) ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12966 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd12 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd12) ?
|
|
4'd13 :
|
|
4'd15 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12967 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd11 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd11) ?
|
|
4'd12 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12966 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12968 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd10 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd10) ?
|
|
4'd11 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12967 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12969 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd9 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd9) ?
|
|
4'd9 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12968 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12970 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd8 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd8) ?
|
|
4'd8 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12969 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12971 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd7 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd7) ?
|
|
4'd7 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12970 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12972 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd6 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd6) ?
|
|
4'd6 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12971 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12973 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd5 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd5) ?
|
|
4'd5 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12972 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12974 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd4 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd4) ?
|
|
4'd4 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12973 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12975 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd3 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd3) ?
|
|
4'd3 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12974 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12976 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd2 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd2) ?
|
|
4'd2 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12975 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12977 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd1 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd1) ?
|
|
4'd1 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12976 ;
|
|
assign IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12978 =
|
|
(fetchStage$pipelines_0_first[4] ?
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 ==
|
|
4'd0 :
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 ==
|
|
4'd0) ?
|
|
4'd0 :
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12977 ;
|
|
assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 =
|
|
{ (mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
|
|
mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ?
|
|
2'd1 :
|
|
((mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
|
|
mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ?
|
|
2'd2 :
|
|
2'd3),
|
|
mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[75:72] :
|
|
mmio_cRqQ_enqReq_rl[75:72] } ;
|
|
assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 =
|
|
{ (mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
|
|
mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ?
|
|
2'd1 :
|
|
((mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
|
|
mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ?
|
|
2'd2 :
|
|
2'd3),
|
|
mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[75:72] :
|
|
mmio_dataReqQ_enqReq_rl[75:72] } ;
|
|
assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 =
|
|
{ (EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 :
|
|
mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ?
|
|
2'd1 :
|
|
((EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd2 :
|
|
mmio_pRqQ_enqReq_rl[37:36] == 2'd2) ?
|
|
2'd2 :
|
|
2'd3),
|
|
EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[35:32] :
|
|
mmio_pRqQ_enqReq_rl[35:32] } ;
|
|
assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 =
|
|
(EN_mmioToPlatform_pRs_enq ?
|
|
!mmio_pRsQ_enqReq_lat_0$wget[66] :
|
|
!mmio_pRsQ_enqReq_rl[66]) ?
|
|
{ EN_mmioToPlatform_pRs_enq ?
|
|
mmio_pRsQ_enqReq_lat_0$wget[65] :
|
|
mmio_pRsQ_enqReq_rl[65],
|
|
EN_mmioToPlatform_pRs_enq ?
|
|
mmio_pRsQ_enqReq_lat_0$wget[64:33] :
|
|
mmio_pRsQ_enqReq_rl[64:33],
|
|
EN_mmioToPlatform_pRs_enq ?
|
|
mmio_pRsQ_enqReq_lat_0$wget[32] :
|
|
mmio_pRsQ_enqReq_rl[32],
|
|
EN_mmioToPlatform_pRs_enq ?
|
|
mmio_pRsQ_enqReq_lat_0$wget[31:0] :
|
|
mmio_pRsQ_enqReq_rl[31:0] } :
|
|
{ 1'h0,
|
|
EN_mmioToPlatform_pRs_enq ?
|
|
mmio_pRsQ_enqReq_lat_0$wget[64:0] :
|
|
mmio_pRsQ_enqReq_rl[64:0] } ;
|
|
assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10105 =
|
|
(!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 ||
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 ||
|
|
_theResult___fst_exp__h537424 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard29463_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188) ;
|
|
assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8632 =
|
|
(!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 ||
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 ||
|
|
_theResult___fst_exp__h498623 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard90662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138) ;
|
|
assign IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9342 =
|
|
(!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 ||
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 ||
|
|
_theResult___fst_exp__h576625 == 11'd2047) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard68664_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155) ;
|
|
assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3__ETC___d13004 =
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] ?
|
|
4'd0 :
|
|
(IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] ?
|
|
4'd1 :
|
|
((IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2]) ?
|
|
4'd2 :
|
|
((IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3]) ?
|
|
4'd3 :
|
|
((IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4]) ?
|
|
4'd4 :
|
|
((IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6]) ?
|
|
4'd5 :
|
|
((IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7]) ?
|
|
4'd6 :
|
|
((IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8]) ?
|
|
4'd7 :
|
|
((IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10]) ?
|
|
4'd8 :
|
|
4'd9)))))))) ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12125 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12106 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12126 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12106)) ?
|
|
coreFix_aluExe_0_bypassWire_2$whas &&
|
|
coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12114 :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12125 ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12127 =
|
|
NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12117 ?
|
|
coreFix_aluExe_0_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[84:78] :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12126 ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12150 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12138 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12151 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12138)) ?
|
|
coreFix_aluExe_0_bypassWire_2$whas &&
|
|
coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12142 :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12150 ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12152 =
|
|
NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12145 ?
|
|
coreFix_aluExe_0_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[76:70] :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12151 ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12308 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12309 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12106)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12308 ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12320 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12321 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12138)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12320 ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11334 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11315 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11335 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11315)) ?
|
|
coreFix_aluExe_1_bypassWire_2$whas &&
|
|
coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11323 :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11334 ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11336 =
|
|
NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11326 ?
|
|
coreFix_aluExe_1_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[84:78] :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11335 ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11359 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11347 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11360 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11347)) ?
|
|
coreFix_aluExe_1_bypassWire_2$whas &&
|
|
coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11351 :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11359 ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11361 =
|
|
NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11354 ?
|
|
coreFix_aluExe_1_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[76:70] :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11360 ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11701 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11702 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11315)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11701 ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11713 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11714 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11347)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11713 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8234 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8215 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8235 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8215)) ?
|
|
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8223 :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8234 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8236 =
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8226 ?
|
|
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8235 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8258 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8246 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8259 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8246)) ?
|
|
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8250 :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8258 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8260 =
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8253 ?
|
|
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8259 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8282 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8270 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8283 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8270)) ?
|
|
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8274 :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8282 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8284 =
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8277 ?
|
|
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8283 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8329 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8330 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8215)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8329 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8340 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8341 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8246)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8340 ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8351 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8352 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8270)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8351 ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ?
|
|
coreFix_memExe_bypassWire_2$whas &&
|
|
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604 =
|
|
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ?
|
|
coreFix_memExe_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[61:55] :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
|
|
coreFix_aluExe_0_bypassWire_1$whas &&
|
|
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 :
|
|
coreFix_aluExe_0_bypassWire_0$whas ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ?
|
|
coreFix_memExe_bypassWire_2$whas &&
|
|
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628 =
|
|
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ?
|
|
coreFix_memExe_bypassWire_3$whas &&
|
|
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[53:47] :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
|
|
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
|
|
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
|
|
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 =
|
|
((!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ?
|
|
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 ;
|
|
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2078 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) ?
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2076 ;
|
|
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2095 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
|
|
2'd0 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088) ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
|
|
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2502 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) ?
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492 } :
|
|
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064) ?
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
|
|
4'd2 } :
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
|
|
1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
|
|
assign IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 =
|
|
(!coreFix_memExe_dTlb$procResp[110] &&
|
|
coreFix_memExe_dTlb$procResp[12]) ?
|
|
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 :
|
|
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 ;
|
|
assign IF_NOT_fetchStage_pipelines_0_canDeq__2593_259_ETC___d13531 =
|
|
((!fetchStage$pipelines_0_canDeq ||
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13161) &&
|
|
fetchStage$pipelines_1_canDeq) ?
|
|
fetchStage$RDY_pipelines_1_first &&
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first) &&
|
|
IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13528 :
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first ;
|
|
assign IF_NOT_fetchStage_pipelines_0_canDeq__2593_259_ETC___d13539 =
|
|
((!fetchStage$pipelines_0_canDeq ||
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13161) &&
|
|
fetchStage$pipelines_1_canDeq) ?
|
|
IF_NOT_fetchStage_pipelines_1_first__2604_BITS_ETC___d13538 :
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13536 ;
|
|
assign IF_NOT_fetchStage_pipelines_1_first__2604_BITS_ETC___d13463 =
|
|
(fetchStage$pipelines_1_first[98:96] == 3'd3 ||
|
|
fetchStage$pipelines_1_first[98:96] == 3'd4) ?
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13446 :
|
|
((fetchStage$pipelines_1_first[98:96] == 3'd2) ?
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13457 :
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first) &&
|
|
_0_OR_fetchStage_RDY_pipelines_0_first__2592_34_ETC___d13460) ;
|
|
assign IF_NOT_fetchStage_pipelines_1_first__2604_BITS_ETC___d13538 =
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13386 ?
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 ||
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13533 :
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13536 ;
|
|
assign IF_NOT_rob_deqPort_1_deq_data__4369_BIT_25_437_ETC___d14473 =
|
|
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
|
|
rob$deqPort_1_deq_data[103] ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd0 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd21 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd17 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd18 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd13 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd15 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd20) ?
|
|
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] :
|
|
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ||
|
|
rob$deqPort_1_deq_data[26] ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4864 =
|
|
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ==
|
|
8'd0) ?
|
|
9'd386 :
|
|
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34[7],
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34 }) -
|
|
9'd386 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5091 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 ?
|
|
((_theResult___fst_exp__h369126 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5076) :
|
|
((_theResult___fst_exp__h377811 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5089) ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5128 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 ?
|
|
((_theResult___fst_exp__h369126 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5119) :
|
|
((_theResult___fst_exp__h377811 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5126) ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5219 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5190[2] :
|
|
_theResult___fst_exp__h378359 == 8'd255 &&
|
|
_theResult___fst_sfd__h378360 == 23'd0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5190[1] :
|
|
_theResult___fst_exp__h377811 == 8'd0 &&
|
|
guard__h369734 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5245 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5190[0] :
|
|
_theResult___fst_exp__h377811 != 8'd255 &&
|
|
guard__h369734 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6256 =
|
|
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ==
|
|
8'd0) ?
|
|
9'd386 :
|
|
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69[7],
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69 }) -
|
|
9'd386 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6483 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 ?
|
|
((_theResult___fst_exp__h414816 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6468) :
|
|
((_theResult___fst_exp__h423501 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6481) ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6520 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 ?
|
|
((_theResult___fst_exp__h414816 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6511) :
|
|
((_theResult___fst_exp__h423501 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6518) ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6611 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6582[2] :
|
|
_theResult___fst_exp__h424049 == 8'd255 &&
|
|
_theResult___fst_sfd__h424050 == 23'd0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6582[1] :
|
|
_theResult___fst_exp__h423501 == 8'd0 &&
|
|
guard__h415424 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6637 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6582[0] :
|
|
_theResult___fst_exp__h423501 != 8'd255 &&
|
|
guard__h415424 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7648 =
|
|
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ==
|
|
8'd0) ?
|
|
9'd386 :
|
|
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104[7],
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104 }) -
|
|
9'd386 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7875 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 ?
|
|
((_theResult___fst_exp__h460504 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7860) :
|
|
((_theResult___fst_exp__h469189 == 8'd255) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7873) ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7912 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 ?
|
|
((_theResult___fst_exp__h460504 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7903) :
|
|
((_theResult___fst_exp__h469189 == 8'd255) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7910) ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8003 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7974[2] :
|
|
_theResult___fst_exp__h469737 == 8'd255 &&
|
|
_theResult___fst_sfd__h469738 == 23'd0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7974[1] :
|
|
_theResult___fst_exp__h469189 == 8'd0 &&
|
|
guard__h461112 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8029 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 ?
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7974[0] :
|
|
_theResult___fst_exp__h469189 != 8'd255 &&
|
|
guard__h461112 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10407 =
|
|
((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ==
|
|
11'd0) ?
|
|
12'd3074 :
|
|
{ SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172[10],
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172 }) -
|
|
12'd3074 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10448 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 ?
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 ?
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10400 :
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10446) :
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10679 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 ?
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 ?
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d10665 :
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10677) :
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10874 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10732[2] :
|
|
_theResult___fst_exp__h517816 == 11'd2047 &&
|
|
_theResult___fst_sfd__h517817 == 52'd0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10888 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10773[2] :
|
|
_theResult___fst_exp__h556617 == 11'd2047 &&
|
|
_theResult___fst_sfd__h556618 == 52'd0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10903 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10817[2] :
|
|
_theResult___fst_exp__h595818 == 11'd2047 &&
|
|
_theResult___fst_sfd__h595819 == 52'd0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10920 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10732[1] :
|
|
_theResult___fst_exp__h517033 == 11'd0 &&
|
|
guard__h509043 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10932 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10773[1] :
|
|
_theResult___fst_exp__h555834 == 11'd0 &&
|
|
guard__h547844 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10945 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10817[1] :
|
|
_theResult___fst_exp__h595035 == 11'd0 &&
|
|
guard__h587045 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10962 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10732[0] :
|
|
_theResult___fst_exp__h517033 != 11'd2047 &&
|
|
guard__h509043 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10974 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10773[0] :
|
|
_theResult___fst_exp__h555834 != 11'd2047 &&
|
|
guard__h547844 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10987 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 ?
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10817[0] :
|
|
_theResult___fst_exp__h595035 != 11'd2047 &&
|
|
guard__h587045 != 2'b0 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8934 =
|
|
((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ==
|
|
11'd0) ?
|
|
12'd3074 :
|
|
{ SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132[10],
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132 }) -
|
|
12'd3074 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8975 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 ?
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 ?
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d8927 :
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8973) :
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9644 =
|
|
((SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ==
|
|
11'd0) ?
|
|
12'd3074 :
|
|
{ SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149[10],
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149 }) -
|
|
12'd3074 ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9685 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 ?
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 ?
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9637 :
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9683) :
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
|
|
assign IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9917 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 ?
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 ?
|
|
IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe__ETC___d9903 :
|
|
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9915) :
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
|
|
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2069_ETC___d12101 =
|
|
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_aluExe_0_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_aluExe_0_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2069_ETC___d12135 =
|
|
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_aluExe_0_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_aluExe_0_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1278_ETC___d11310 =
|
|
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_aluExe_1_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_aluExe_1_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1278_ETC___d11344 =
|
|
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_aluExe_1_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_aluExe_1_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8210 =
|
|
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8243 =
|
|
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8267 =
|
|
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6524 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ?
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0 ||
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6485) :
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0 ||
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6522) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5862 =
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
|
|
6'd24 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
|
|
6'd25 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
|
|
6'd26 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
|
|
6'd27 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
|
|
6'd28 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
|
|
6'd29 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
|
|
6'd30 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
|
|
6'd31 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
|
|
6'd32 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
|
|
6'd33 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
|
|
6'd34 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
|
|
6'd35 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
|
|
6'd36 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
|
|
6'd37 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
|
|
6'd38 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
|
|
6'd39 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
|
|
6'd40 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
|
|
6'd41 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
|
|
6'd42 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
|
|
6'd43 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
|
|
6'd44 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
|
|
6'd45 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
|
|
6'd46 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
|
|
6'd47 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
|
|
6'd48 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
|
|
6'd49 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
|
|
6'd50 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
|
|
6'd51 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
|
|
6'd52 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
|
|
6'd53 :
|
|
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
|
|
6'd1) -
|
|
6'd1 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6485 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 ?
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6453 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 ?
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6483 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6522 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 ?
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6503 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6504) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 ?
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6520 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6504) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6586 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6568 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 &&
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6582[4] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6597 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6593 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 &&
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6582[3] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6613 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6605 :
|
|
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6611 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6626 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6620 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 &&
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6624 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6639 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6633 :
|
|
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6637 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4470 =
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
|
|
6'd24 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
|
|
6'd25 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
|
|
6'd26 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
|
|
6'd27 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
|
|
6'd28 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
|
|
6'd29 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
|
|
6'd30 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
|
|
6'd31 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
|
|
6'd32 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
|
|
6'd33 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
|
|
6'd34 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
|
|
6'd35 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
|
|
6'd36 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
|
|
6'd37 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
|
|
6'd38 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
|
|
6'd39 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
|
|
6'd40 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
|
|
6'd41 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
|
|
6'd42 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
|
|
6'd43 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
|
|
6'd44 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
|
|
6'd45 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
|
|
6'd46 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
|
|
6'd47 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
|
|
6'd48 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
|
|
6'd49 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
|
|
6'd50 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
|
|
6'd51 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
|
|
6'd52 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
|
|
6'd53 :
|
|
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
|
|
6'd1) -
|
|
6'd1 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5093 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 ?
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5061 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 ?
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5091 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5130 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 ?
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5111 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5112) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 ?
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5128 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5112) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5194 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5176 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 &&
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5190[4] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5205 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5201 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 &&
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5190[3] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5221 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5213 :
|
|
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5219 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5234 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5228 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 &&
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5232 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5247 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5241 :
|
|
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5245 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7254 =
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
|
|
6'd24 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
|
|
6'd25 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
|
|
6'd26 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
|
|
6'd27 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
|
|
6'd28 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
|
|
6'd29 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
|
|
6'd30 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
|
|
6'd31 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
|
|
6'd32 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
|
|
6'd33 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
|
|
6'd34 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
|
|
6'd35 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
|
|
6'd36 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
|
|
6'd37 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
|
|
6'd38 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
|
|
6'd39 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
|
|
6'd40 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
|
|
6'd41 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
|
|
6'd42 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
|
|
6'd43 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
|
|
6'd44 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
|
|
6'd45 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
|
|
6'd46 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
|
|
6'd47 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
|
|
6'd48 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
|
|
6'd49 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
|
|
6'd50 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
|
|
6'd51 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
|
|
6'd52 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
|
|
6'd53 :
|
|
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
|
|
6'd1) -
|
|
6'd1 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7877 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 ?
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7845 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 ?
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7875 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7914 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 ?
|
|
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7895 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7896) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 ?
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7912 :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7896) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7978 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7960 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 &&
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7974[4] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7989 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7985 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 &&
|
|
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7974[3] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8005 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d7997 :
|
|
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8003 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8018 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8012 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 &&
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8016 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8031 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8025 :
|
|
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8029 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5132 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ?
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0 ||
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5093) :
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0 ||
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5130) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7916 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ?
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0 ||
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7877) :
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0 ||
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7914) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8062 =
|
|
(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] ==
|
|
2'd0) ?
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] :
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 =
|
|
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8062[31:0] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10059 =
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[98] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[97] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[96] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[95] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[94] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[93] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[92] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[91] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[90] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[89] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[88] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[87] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[86] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[85] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[84] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[83] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[82] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[81] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[80] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[79] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[78] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[77] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[76] ?
|
|
6'd24 :
|
|
6'd57))))))))))))))))))))))) :
|
|
6'd1) -
|
|
6'd1 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10450 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0 ||
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d10105 :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10448) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10628 =
|
|
{ (coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255) ?
|
|
11'd2047 :
|
|
_theResult___fst_exp__h556629,
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) ?
|
|
_theResult___snd_fst_sfd__h518518 :
|
|
_theResult___fst_sfd__h556633 } ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10630 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] :
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10450,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10628 } ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10681 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0 ||
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d10653 :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10679) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10736 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 &&
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10715[4] :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 &&
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10732[4] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10777 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 &&
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10756[4] :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 &&
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10773[4] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10821 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 &&
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10800[4] :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 &&
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10817[4] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10836 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 &&
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10715[3] :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 &&
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10732[3] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10846 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 &&
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10756[3] :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 &&
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10773[3] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10857 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 &&
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10800[3] :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 &&
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 &&
|
|
_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10817[3] ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10876 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 ||
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10715[2] :
|
|
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10874 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10890 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 ||
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10756[2] :
|
|
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10888 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10905 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 ||
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10800[2] :
|
|
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10903 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10922 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 &&
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 ||
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10715[1]) :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 &&
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10920 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10934 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 &&
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 ||
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10756[1]) :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 &&
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10932 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10947 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 &&
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 ||
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10800[1]) :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 &&
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10945 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10964 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 ||
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10715[0] :
|
|
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10962 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10976 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 ||
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10756[0] :
|
|
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10974 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10989 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 ||
|
|
!_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 &&
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10800[0] :
|
|
!SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 ||
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10987 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8423 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ?
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8389 &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8402 :
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 ||
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8421 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8571 =
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[162] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[161] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[160] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[159] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[158] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[157] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[156] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[155] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[154] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[153] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[152] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[151] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[150] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[149] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[148] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[147] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[146] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[145] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[144] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[143] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[142] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[141] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[140] ?
|
|
6'd24 :
|
|
6'd57))))))))))))))))))))))) :
|
|
6'd1) -
|
|
6'd1 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8977 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0 ||
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d8632 :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8975) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9161 =
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8977,
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255) ?
|
|
11'd2047 :
|
|
_theResult___fst_exp__h517828,
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) ?
|
|
_theResult___snd_fst_sfd__h479576 :
|
|
_theResult___fst_sfd__h517832 } ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9161 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9296 =
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[34] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[33] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[32] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[31] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[30] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[29] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[28] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[27] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[26] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[25] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[24] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[23] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[22] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[21] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[20] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[19] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[18] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[17] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[16] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[15] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[14] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[13] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[12] ?
|
|
6'd24 :
|
|
6'd57))))))))))))))))))))))) :
|
|
6'd1) -
|
|
6'd1 ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9687 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0 ||
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
IF_NOT_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDi_ETC___d9342 :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9685) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9865 =
|
|
{ (coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255) ?
|
|
11'd2047 :
|
|
_theResult___fst_exp__h595830,
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) ?
|
|
_theResult___snd_fst_sfd__h557719 :
|
|
_theResult___fst_sfd__h595834 } ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9867 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] :
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9687,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9865 } ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9919 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0 ||
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
IF_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d9891 :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9917) ;
|
|
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9921 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
|
|
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[75],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } :
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9919,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9865 } ;
|
|
assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12536 =
|
|
coreFix_globalSpecUpdate_correctSpecTag_1$whas ?
|
|
result__h640846 :
|
|
w__h640841 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2076 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064) ?
|
|
NOT_coreFix_memExe_respLrScAmoQ_full_944_945_A_ETC___d2074 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2096 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064) ?
|
|
NOT_coreFix_memExe_respLrScAmoQ_full_944_945_A_ETC___d2074 :
|
|
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2095 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2099 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
|
|
3'd1) ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2098 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2190 =
|
|
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd7) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd6) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd5) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd4) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2195 =
|
|
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2190,
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd3) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd2) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2200 =
|
|
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2195,
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd1) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
|
|
3'd0) ?
|
|
n___1__h195697 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2513 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064) ?
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
|
|
4'd2,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } :
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
|
|
2'd0 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088) ?
|
|
{ 3'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } :
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
|
|
1'd1,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2515 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
|
|
3'd1) ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2514 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2531 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
|
|
3'd1) ?
|
|
3'd5 :
|
|
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
|
|
2'd0 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088) ?
|
|
3'd2 :
|
|
3'd3) ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2542 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
|
|
3'd1) ?
|
|
58'h155555555555554 :
|
|
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
|
|
2'd0 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088) ?
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
|
|
2'd0,
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
|
|
1'd0 } :
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
|
|
53'h15555555555555 }) ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2559 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2) ?
|
|
x__h194294 :
|
|
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142 ?
|
|
64'd0 :
|
|
64'd1) ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3038 =
|
|
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3050 =
|
|
_theResult_____2__h293689 == v__h293109 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3130 =
|
|
EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3145 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3152 =
|
|
_theResult_____2__h301685 == v__h296454 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3172 =
|
|
EN_dCacheToParent_fromP_enq ?
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3239 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3130 &&
|
|
(EN_dCacheToParent_fromP_enq ?
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ?
|
|
{ 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
|
|
EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } :
|
|
{ EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518],
|
|
EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516],
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3172 ||
|
|
(EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]),
|
|
EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3],
|
|
x__h299319 } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d2996 =
|
|
!MUX_flush_reservation$write_1__SEL_1 &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 =
|
|
MUX_flush_reservation$write_1__SEL_1 ?
|
|
58'h2AAAAAAAAAAAAAA :
|
|
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2039 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3) ?
|
|
!coreFix_memExe_respLrScAmoQ_full :
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd1 ||
|
|
coreFix_memExe_stb$RDY_deq ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2041 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2) ?
|
|
!coreFix_memExe_respLrScAmoQ_full :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd4 ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2039 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2042 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0) ?
|
|
!coreFix_memExe_memRespLdQ_full :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2041 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 =
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2042 &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd4 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd1 ||
|
|
coreFix_memExe_stb$RDY_deq)) ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2098 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019)) ?
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2096 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2100 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 ?
|
|
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2078 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2099 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136 =
|
|
{ (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2514 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019)) ?
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2136,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492 } :
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2513 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2562 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019)) ?
|
|
{ 1'd1,
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2559 } :
|
|
65'h10000000000000001 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2696 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692) ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2705 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692) ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] :
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
|
|
2'd0 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0],
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1990 =
|
|
{ (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd7) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd6) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd5) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1995 =
|
|
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1990,
|
|
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd4) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd3) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2000 =
|
|
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1995,
|
|
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd2) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128],
|
|
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
|
|
3'd1) ?
|
|
n__h191621 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2781 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) :
|
|
2'd0 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) :
|
|
3'd0 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2828 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) :
|
|
4'd0 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3301 =
|
|
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3316 =
|
|
EN_dCacheToParent_rqToP_deq ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324 =
|
|
_theResult_____2__h307679 == v__h306968 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3397 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3412 =
|
|
EN_dCacheToParent_rsToP_deq ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420 =
|
|
_theResult_____2__h315533 == v__h310844 ;
|
|
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3439 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 =
|
|
(coreFix_memExe_dTlb$procResp[105:103] == 3'd3) ?
|
|
4'd7 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1737 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd3 &&
|
|
!coreFix_memExe_dTlb$procResp[12] :
|
|
!coreFix_memExe_dTlb$procResp[12] &&
|
|
!coreFix_memExe_dTlb$procResp[110] ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1792 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd0 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd0 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd1 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd1 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd2 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd2 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd3 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd3 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd4 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd4 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd5 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd5 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd6 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd6 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd7 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd7 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd8 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd8 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd9 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd9 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd10 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd10 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd11 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd11 ;
|
|
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 =
|
|
coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 ?
|
|
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
|
|
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1788 ==
|
|
4'd12 :
|
|
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1787 ==
|
|
4'd12 ;
|
|
assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 =
|
|
(coreFix_memExe_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_memExe_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_memExe_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 =
|
|
(coreFix_memExe_dispToRegQ$RDY_first &&
|
|
coreFix_aluExe_0_bypassWire_0$whas &&
|
|
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
|
|
!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
coreFix_memExe_dispToRegQ$RDY_first :
|
|
!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
coreFix_memExe_dispToRegQ$RDY_first ;
|
|
assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3742 =
|
|
_theResult_____2__h329102 == v__h328670 ;
|
|
assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3735 =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
|
|
coreFix_memExe_forwardQ_deqReq_rl ;
|
|
assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3720 =
|
|
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
|
|
coreFix_memExe_forwardQ_enqReq_rl[69] ;
|
|
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 =
|
|
coreFix_memExe_lsq$firstLd[94] ?
|
|
(coreFix_memExe_lsq$firstLd[92] ?
|
|
{ 48'd0,
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 } :
|
|
{ {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359[15]}},
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 }) :
|
|
(coreFix_memExe_lsq$firstLd[92] ?
|
|
{ 56'd0,
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 } :
|
|
{ {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373[7]}},
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 }) ;
|
|
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 =
|
|
coreFix_memExe_lsq$firstLd[94] ?
|
|
(coreFix_memExe_lsq$firstLd[92] ?
|
|
{ 48'd0,
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 } :
|
|
{ {48{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407[15]}},
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 }) :
|
|
(coreFix_memExe_lsq$firstLd[92] ?
|
|
{ 56'd0,
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 } :
|
|
{ {56{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420[7]}},
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 }) ;
|
|
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 =
|
|
coreFix_memExe_lsq$firstLd[96] ?
|
|
(coreFix_memExe_lsq$firstLd[92] ?
|
|
{ 32'd0,
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 } :
|
|
{ {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348[31]}},
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 }) :
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 ;
|
|
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 =
|
|
coreFix_memExe_lsq$firstLd[96] ?
|
|
(coreFix_memExe_lsq$firstLd[92] ?
|
|
{ 32'd0,
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 } :
|
|
{ {32{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398[31]}},
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) :
|
|
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ;
|
|
assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3648 =
|
|
_theResult_____2__h325877 == v__h325445 ;
|
|
assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3641 =
|
|
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
|
|
coreFix_memExe_memRespLdQ_deqReq_rl ;
|
|
assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3626 =
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
|
|
coreFix_memExe_memRespLdQ_enqReq_rl[69] ;
|
|
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) :
|
|
2'd0 ;
|
|
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) :
|
|
3'd0 ;
|
|
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) :
|
|
4'd0 ;
|
|
assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3550 =
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
|
|
coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ;
|
|
assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 =
|
|
csrf_minstret_ehr_data_lat_0$whas ?
|
|
rob$deqPort_0_deq_data[95:32] :
|
|
csrf_minstret_ehr_data_rl ;
|
|
assign IF_fetchStage_RDY_pipelines_0_first__2592_AND__ETC___d13130 =
|
|
fetchStage_RDY_pipelines_0_first__2592_AND_NOT_ETC___d13126 ?
|
|
fetchStage$RDY_pipelines_0_first :
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage$RDY_pipelines_0_first ;
|
|
assign IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13465 =
|
|
(fetchStage$RDY_pipelines_1_first &&
|
|
(fetchStage$pipelines_1_first[98:96] == 3'd0 ||
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1)) ?
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first) &&
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13435 :
|
|
fetchStage$RDY_pipelines_1_first &&
|
|
IF_NOT_fetchStage_pipelines_1_first__2604_BITS_ETC___d13463 ;
|
|
assign IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13528 =
|
|
(fetchStage$RDY_pipelines_1_first &&
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first) &&
|
|
fetchStage_RDY_pipelines_0_first__2592_AND_fet_ETC___d13193 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13386) ?
|
|
IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13465 &&
|
|
(IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 ||
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first) :
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first ;
|
|
assign IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13575 =
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13568 ||
|
|
rob$RDY_enqPort_0_enq &&
|
|
regRenamingTable$RDY_rename_0_claimRename &&
|
|
regRenamingTable$RDY_rename_0_getRename &&
|
|
fetchStage$RDY_pipelines_0_deq &&
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$RDY_claimSpecTag) ;
|
|
assign IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d13023 =
|
|
(fetchStage$pipelines_0_first[4] ||
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[12] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[13] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[14]) ?
|
|
IF_IF_fetchStage_pipelines_0_first__2595_BIT_4_ETC___d12978 :
|
|
CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 ;
|
|
assign IF_fetchStage_pipelines_0_first__2595_BIT_64_2_ETC___d13744 =
|
|
{ fetchStage$pipelines_0_first[63:32],
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13732,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13735 ?
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13738 :
|
|
{ 1'h0,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13741 } } ;
|
|
assign IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13696 =
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13655 &&
|
|
IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13465 &&
|
|
(IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13680 ||
|
|
rob$RDY_enqPort_1_enq &&
|
|
regRenamingTable$RDY_rename_1_claimRename &&
|
|
regRenamingTable$RDY_rename_1_getRename &&
|
|
fetchStage_RDY_pipelines_1_deq__2607_AND_NOT_f_ETC___d13690) ;
|
|
assign IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13908 =
|
|
(fetchStage$pipelines_1_first[98:96] == 3'd2 &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13855 &&
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13862) ?
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13863 :
|
|
{ 1'h0,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13864 } ;
|
|
assign IF_fetchStage_pipelines_1_first__2604_BIT_64_3_ETC___d13867 =
|
|
{ fetchStage$pipelines_1_first[63:32],
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13861,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13862 ?
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13863 :
|
|
{ 1'h0,
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13864 } } ;
|
|
assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 =
|
|
mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[142] :
|
|
mmio_cRqQ_enqReq_rl[142] ;
|
|
assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 =
|
|
CAN_FIRE_RL_mmio_handlePRq ?
|
|
mmio_cRsQ_enqReq_lat_0$wget[1] :
|
|
mmio_cRsQ_enqReq_rl[1] ;
|
|
assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 =
|
|
mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[142] :
|
|
mmio_dataReqQ_enqReq_rl[142] ;
|
|
assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 =
|
|
CAN_FIRE_RL_mmio_sendDataResp ?
|
|
mmio_dataRespQ_enqReq_lat_0$wget[65] :
|
|
mmio_dataRespQ_enqReq_rl[65] ;
|
|
assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 =
|
|
EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[39] :
|
|
mmio_pRqQ_enqReq_rl[39] ;
|
|
assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 =
|
|
EN_mmioToPlatform_pRs_enq ?
|
|
mmio_pRsQ_enqReq_lat_0$wget[67] :
|
|
mmio_pRsQ_enqReq_rl[67] ;
|
|
assign IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14460 =
|
|
rob$deqPort_0_canDeq ? y_avValue_snd_fst__h702097 : 5'd0 ;
|
|
assign IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14482 =
|
|
rob$deqPort_0_canDeq ?
|
|
y_avValue_snd_snd_snd_fst__h702343 :
|
|
2'd0 ;
|
|
assign IF_rob_deqPort_1_canDeq__4366_THEN_IF_NOT_rob__ETC___d14474 =
|
|
rob$deqPort_1_canDeq ?
|
|
IF_NOT_rob_deqPort_1_deq_data__4369_BIT_25_437_ETC___d14473 :
|
|
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ;
|
|
assign IF_sfdin08194_BIT_4_THEN_2_ELSE_0__q131 =
|
|
sfdin__h508194[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin14810_BIT_33_THEN_2_ELSE_0__q66 =
|
|
sfdin__h414810[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin42732_BIT_33_THEN_2_ELSE_0__q91 =
|
|
sfdin__h442732[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin46995_BIT_4_THEN_2_ELSE_0__q171 =
|
|
sfdin__h546995[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin51354_BIT_33_THEN_2_ELSE_0__q21 =
|
|
sfdin__h351354[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin60498_BIT_33_THEN_2_ELSE_0__q101 =
|
|
sfdin__h460498[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin69120_BIT_33_THEN_2_ELSE_0__q31 =
|
|
sfdin__h369120[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin86196_BIT_4_THEN_2_ELSE_0__q148 =
|
|
sfdin__h586196[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_sfdin97044_BIT_33_THEN_2_ELSE_0__q56 =
|
|
sfdin__h397044[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd05657_BIT_33_THEN_2_ELSE_0__q58 =
|
|
_theResult___snd__h405657[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd16979_BIT_4_THEN_2_ELSE_0__q134 =
|
|
_theResult___snd__h516979[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd23447_BIT_33_THEN_2_ELSE_0__q71 =
|
|
_theResult___snd__h423447[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd37375_BIT_4_THEN_2_ELSE_0__q167 =
|
|
_theResult___snd__h537375[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd51345_BIT_33_THEN_2_ELSE_0__q93 =
|
|
_theResult___snd__h451345[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd55780_BIT_4_THEN_2_ELSE_0__q174 =
|
|
_theResult___snd__h555780[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd59967_BIT_33_THEN_2_ELSE_0__q23 =
|
|
_theResult___snd__h359967[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd69135_BIT_33_THEN_2_ELSE_0__q106 =
|
|
_theResult___snd__h469135[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd76576_BIT_4_THEN_2_ELSE_0__q144 =
|
|
_theResult___snd__h576576[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd77757_BIT_33_THEN_2_ELSE_0__q36 =
|
|
_theResult___snd__h377757[33] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd94981_BIT_4_THEN_2_ELSE_0__q151 =
|
|
_theResult___snd__h594981[4] ? 2'd2 : 2'd0 ;
|
|
assign IF_theResult___snd98574_BIT_4_THEN_2_ELSE_0__q127 =
|
|
_theResult___snd__h498574[4] ? 2'd2 : 2'd0 ;
|
|
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5213 =
|
|
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 ||
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5161[2] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5173[2]) ;
|
|
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5241 =
|
|
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 ||
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5161[0] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5173[0]) ;
|
|
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6605 =
|
|
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 ||
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6553[2] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6565[2]) ;
|
|
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6633 =
|
|
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 ||
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6553[0] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6565[0]) ;
|
|
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d7997 =
|
|
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 ||
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7945[2] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7957[2]) ;
|
|
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8025 =
|
|
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 ||
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7945[0] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7957[0]) ;
|
|
assign NOT_IF_NOT_rob_deqPort_0_canDeq__4362_4363_OR__ETC___d14479 =
|
|
(fflags__h702055 & csrf_fflags_reg) != fflags__h702055 ||
|
|
!r__h608815 &&
|
|
(IF_rob_deqPort_1_canDeq__4366_THEN_IF_NOT_rob__ETC___d14474 ||
|
|
fflags__h702055 != 5'd0) ;
|
|
assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13179 =
|
|
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 &&
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 ;
|
|
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12117 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12106) &&
|
|
(!coreFix_aluExe_0_bypassWire_2$whas ||
|
|
!coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12114) ;
|
|
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12145 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12138) &&
|
|
(!coreFix_aluExe_0_bypassWire_2$whas ||
|
|
!coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12142) ;
|
|
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11326 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11315) &&
|
|
(!coreFix_aluExe_1_bypassWire_2$whas ||
|
|
!coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11323) ;
|
|
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11354 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11347) &&
|
|
(!coreFix_aluExe_1_bypassWire_2$whas ||
|
|
!coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11351) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8226 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8215) &&
|
|
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8223) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8253 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8246) &&
|
|
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8250) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8277 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8270) &&
|
|
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
|
|
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8274) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5807 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4415 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7199 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10032 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[97] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[96] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[95] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[94] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[93] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[92] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[91] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[90] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[89] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[88] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[87] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[86] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[85] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[84] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[83] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[82] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[81] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[80] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[79] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[78] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[77] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[76] ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10739 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10736 ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10781 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10739 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10777) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10839 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10836 ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10850 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10839 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10846) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10879 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10876 ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10894 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10879 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10890) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10925 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10922 ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10938 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10925 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10934) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10967 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10964 ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10980 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10967 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10976) ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8544 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[161] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[160] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[159] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[158] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[157] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[156] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[155] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[154] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[153] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[152] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[151] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[150] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[149] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[148] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[147] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[146] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[145] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[144] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[143] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[142] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[141] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[140] ;
|
|
assign NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9269 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[33] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[32] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[31] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[30] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[29] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[28] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[27] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[26] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[25] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[24] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[23] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[22] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[21] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[20] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[19] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[18] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[17] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[16] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[15] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[14] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[13] &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[12] ;
|
|
assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583) &&
|
|
(!coreFix_memExe_bypassWire_2$whas ||
|
|
!coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591) ;
|
|
assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 =
|
|
(!coreFix_aluExe_0_bypassWire_0$whas ||
|
|
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
|
|
(!coreFix_aluExe_0_bypassWire_1$whas ||
|
|
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614) &&
|
|
(!coreFix_memExe_bypassWire_2$whas ||
|
|
!coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2518 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2658 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd3 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
|
|
2'd0 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3049 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3070 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
|
|
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
|
|
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3038 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3119 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3175 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3172) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3145 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2062 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2115 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
|
|
3'd1 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd4 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2525 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd3 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2527 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
|
|
3'd1 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2525) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2549 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3) ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2556 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2552 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2570 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2569 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2573 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2552 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2570) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2584 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd4 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2590 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd4 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2597 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2622 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd1 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd4 ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2647 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd3 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
|
|
2'd0 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2669 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2042 &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd4 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd1 ||
|
|
coreFix_memExe_stb$RDY_deq)) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3290 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3347 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT ||
|
|
(CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3316 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3386 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3443 =
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3439) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3412 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ;
|
|
assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1875 =
|
|
!coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_dMem_perfReqQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1919 =
|
|
(!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) &&
|
|
(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT &&
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_rl ||
|
|
coreFix_memExe_dMem_perfReqQ_empty) ;
|
|
assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3709 =
|
|
!coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_forwardQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3764 =
|
|
(!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT ||
|
|
(coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
|
|
!coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
|
|
!coreFix_memExe_forwardQ_enqReq_rl[69])) &&
|
|
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3735 ||
|
|
coreFix_memExe_forwardQ_empty) ;
|
|
assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3615 =
|
|
!coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_memRespLdQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3670 =
|
|
(!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT ||
|
|
(coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
|
|
!coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
|
|
!coreFix_memExe_memRespLdQ_enqReq_rl[69])) &&
|
|
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3641 ||
|
|
coreFix_memExe_memRespLdQ_empty) ;
|
|
assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 =
|
|
!coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT ||
|
|
!coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_reqLdQ_full_rl ;
|
|
assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 =
|
|
!coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT ||
|
|
!coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_reqLrScAmoQ_full_rl ;
|
|
assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3539 =
|
|
!coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT ||
|
|
!coreFix_memExe_respLrScAmoQ_clearReq_rl ;
|
|
assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3581 =
|
|
(!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT ||
|
|
(coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
|
|
!coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
|
|
!coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) &&
|
|
(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT &&
|
|
(coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ||
|
|
coreFix_memExe_respLrScAmoQ_deqReq_rl) ||
|
|
coreFix_memExe_respLrScAmoQ_empty) ;
|
|
assign NOT_coreFix_memExe_respLrScAmoQ_full_944_945_A_ETC___d2074 =
|
|
!coreFix_memExe_respLrScAmoQ_full &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ;
|
|
assign NOT_csrf_prv_reg_read__2623_ULE_1_3987_4051_OR_ETC___d14055 =
|
|
!csrf_prv_reg_read__2623_ULE_1___d13987 ||
|
|
(commitStage_commitTrap[4] ?
|
|
!_0b0_CONCAT_csrf_mideleg_11_reg_read__1600_1601_ETC___d14007 :
|
|
!_0b0_CONCAT_csrf_medeleg_15_reg_read__1592_1593_ETC___d14025) ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13218 =
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13200 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13215 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13446 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first) &&
|
|
(regRenamingTable_rename_0_canRename__3102_AND__ETC___d13443 ||
|
|
!regRenamingTable$rename_1_canRename ||
|
|
fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13432) ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13457 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first) &&
|
|
(regRenamingTable_rename_0_canRename__3102_AND__ETC___d13455 ||
|
|
!regRenamingTable$rename_1_canRename ||
|
|
fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13432) ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13479 =
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13200 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13476 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13494 =
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13488 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd3 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd4 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13508 =
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13200 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13511 =
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13508 &&
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q231 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13631 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13488 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd0 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143) &&
|
|
coreFix_aluExe_1_rsAlu$canEnq &&
|
|
!coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13650 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13621) &&
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q235 &&
|
|
(fetchStage$pipelines_1_first[103:99] == 5'd14 ||
|
|
coreFix_memExe_rsMem$RDY_enq) ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13702 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13577 &&
|
|
IF_fetchStage_RDY_pipelines_0_first__2592_AND__ETC___d13130) &&
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
fetchStage_pipelines_0_canDeq__2593_AND_fetchS_ETC___d13700 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13792 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13789) &&
|
|
coreFix_aluExe_1_rsAlu$canEnq &&
|
|
!coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13160) &&
|
|
fetchStage$pipelines_1_canDeq ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13799 =
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13215 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13810 =
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13807 &&
|
|
(fetchStage$pipelines_1_first[98:96] == 3'd0 ||
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1) &&
|
|
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__259_ETC___d13616 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13855 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210) &&
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q231 ;
|
|
assign NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13885 =
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13799 &&
|
|
specTagManager$canClaim &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805 &&
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 &&
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 =
|
|
fetchStage$pipelines_0_first[103:99] != 5'd0 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd21 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd17 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd18 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd13 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd16 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd15 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd19 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd20 &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BIT_4_2_ETC___d13046 &&
|
|
rob$enqPort_0_canEnq &&
|
|
epochManager$checkEpoch_0_check ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 =
|
|
fetchStage$pipelines_0_first[103:99] != 5'd0 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd21 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd17 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd18 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd13 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd16 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd15 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd19 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd20 &&
|
|
!fetchStage$pipelines_0_first[4] &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
epochManager$checkEpoch_0_check ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13161 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13160 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13379 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13160 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13393 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 &&
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13392 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13399 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 &&
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd0 ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1) &&
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 &&
|
|
(!coreFix_aluExe_0_rsAlu$canEnq ||
|
|
!coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139) ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13498 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13497 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13515 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13514 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13533 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13536 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13624 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13392 ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13776 =
|
|
{ fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
!coreFix_memExe_rsMem$canEnq ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13732,
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13735) ?
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13738 :
|
|
{ 1'h0,
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13741 },
|
|
7'd32,
|
|
specTagManager$currentSpecBits } ;
|
|
assign NOT_fetchStage_pipelines_0_first__2595_BIT_4_2_ETC___d13046 =
|
|
!fetchStage$pipelines_0_first[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[12] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[13] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[14] &&
|
|
!checkForException___d12829[4] ;
|
|
assign NOT_fetchStage_pipelines_1_canDeq__2601_2602_O_ETC___d12610 =
|
|
!fetchStage$pipelines_1_canDeq ||
|
|
fetchStage$RDY_pipelines_1_first &&
|
|
(epochManager$checkEpoch_1_check ||
|
|
fetchStage$RDY_pipelines_1_deq) ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13384 =
|
|
fetchStage$pipelines_1_first[103:99] != 5'd0 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd21 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd17 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd18 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd13 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd16 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd15 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd19 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd20 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BIT_4_3_ETC___d13376 &&
|
|
rob$enqPort_1_canEnq &&
|
|
epochManager$checkEpoch_1_check &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13379) ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13503 =
|
|
fetchStage$pipelines_1_first[103:99] != 5'd0 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd21 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd17 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd18 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd13 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd16 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd15 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd19 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd20 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BIT_4_3_ETC___d13376 &&
|
|
rob$enqPort_1_canEnq &&
|
|
epochManager$checkEpoch_1_check &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13498) ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13520 =
|
|
fetchStage$pipelines_1_first[103:99] != 5'd0 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd21 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd17 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd18 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd13 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd16 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd15 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd19 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd20 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BIT_4_3_ETC___d13376 &&
|
|
rob$enqPort_1_canEnq &&
|
|
epochManager$checkEpoch_1_check &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13515) ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805 =
|
|
fetchStage$pipelines_1_first[103:99] != 5'd0 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd21 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd17 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd18 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd13 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd16 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd15 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd19 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd20 &&
|
|
!fetchStage$pipelines_1_first[4] &&
|
|
!checkForException___d13372[4] &&
|
|
rob$enqPort_1_canEnq &&
|
|
epochManager$checkEpoch_1_check ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13386 =
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13218 &&
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13384 ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13482 =
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13479 &&
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13384 ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13807 =
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13799 &&
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805 ;
|
|
assign NOT_fetchStage_pipelines_1_first__2604_BIT_4_3_ETC___d13376 =
|
|
!fetchStage$pipelines_1_first[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[12] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[13] &&
|
|
!IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[14] &&
|
|
!checkForException___d13372[4] ;
|
|
assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 =
|
|
!mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ;
|
|
assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 =
|
|
(!mmio_cRqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(mmio_cRqQ_enqReq_lat_0$whas ?
|
|
!mmio_cRqQ_enqReq_lat_0$wget[142] :
|
|
!mmio_cRqQ_enqReq_rl[142])) &&
|
|
(mmio_cRqQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) ||
|
|
mmio_cRqQ_empty) ;
|
|
assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 =
|
|
!mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ;
|
|
assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 =
|
|
(!mmio_cRsQ_enqReq_dummy2_2$Q_OUT ||
|
|
(CAN_FIRE_RL_mmio_handlePRq ?
|
|
!mmio_cRsQ_enqReq_lat_0$wget[1] :
|
|
!mmio_cRsQ_enqReq_rl[1])) &&
|
|
(mmio_cRsQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) ||
|
|
mmio_cRsQ_empty) ;
|
|
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 =
|
|
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
|
|
coreFix_memExe_lsq$RDY_deqSt &&
|
|
coreFix_memExe_lsq$RDY_firstSt ;
|
|
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 =
|
|
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
|
|
coreFix_memExe_lsq$RDY_deqLd &&
|
|
coreFix_memExe_lsq$RDY_firstLd ;
|
|
assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 =
|
|
(!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT ||
|
|
!mmio_dataPendQ_enqReq_lat_0$whas &&
|
|
!mmio_dataPendQ_enqReq_rl) &&
|
|
(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT &&
|
|
(mmio_dataRespQ_deqReq_lat_0$whas ||
|
|
mmio_dataPendQ_deqReq_rl) ||
|
|
mmio_dataPendQ_empty) ;
|
|
assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 =
|
|
!mmio_dataReqQ_clearReq_dummy2_1$Q_OUT ||
|
|
!mmio_dataReqQ_clearReq_rl ;
|
|
assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 =
|
|
(!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
!mmio_dataReqQ_enqReq_lat_0$wget[142] :
|
|
!mmio_dataReqQ_enqReq_rl[142])) &&
|
|
(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT &&
|
|
(CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) ||
|
|
mmio_dataReqQ_empty) ;
|
|
assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 =
|
|
!mmio_dataRespQ_clearReq_dummy2_1$Q_OUT ||
|
|
!mmio_dataRespQ_clearReq_rl ;
|
|
assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 =
|
|
(!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT ||
|
|
(CAN_FIRE_RL_mmio_sendDataResp ?
|
|
!mmio_dataRespQ_enqReq_lat_0$wget[65] :
|
|
!mmio_dataRespQ_enqReq_rl[65])) &&
|
|
(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT &&
|
|
(mmio_dataRespQ_deqReq_lat_0$whas ||
|
|
mmio_dataRespQ_deqReq_rl) ||
|
|
mmio_dataRespQ_empty) ;
|
|
assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 =
|
|
!mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ;
|
|
assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 =
|
|
(!mmio_pRqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(EN_mmioToPlatform_pRq_enq ?
|
|
!mmio_pRqQ_enqReq_lat_0$wget[39] :
|
|
!mmio_pRqQ_enqReq_rl[39])) &&
|
|
(mmio_pRqQ_deqReq_dummy2_2$Q_OUT &&
|
|
(CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) ||
|
|
mmio_pRqQ_empty) ;
|
|
assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 =
|
|
!mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ;
|
|
assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 =
|
|
(!mmio_pRsQ_enqReq_dummy2_2$Q_OUT ||
|
|
(EN_mmioToPlatform_pRs_enq ?
|
|
!mmio_pRsQ_enqReq_lat_0$wget[67] :
|
|
!mmio_pRsQ_enqReq_rl[67])) &&
|
|
(mmio_pRsQ_deqReq_dummy2_2$Q_OUT &&
|
|
(mmio_pRsQ_deqReq_dummy_2_0$wget || mmio_pRsQ_deqReq_rl) ||
|
|
mmio_pRsQ_empty) ;
|
|
assign NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13488 =
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd0 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd21 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd17 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd18 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd13 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd16 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd15 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd19 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd20 ||
|
|
fetchStage$pipelines_0_first[4] ||
|
|
checkForException___d12829[4] ||
|
|
!rob$enqPort_0_canEnq ||
|
|
!epochManager$checkEpoch_0_check ;
|
|
assign NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542 =
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage$pipelines_0_first[4] ||
|
|
checkForException___d12829[4] ||
|
|
!rob$enqPort_0_canEnq ;
|
|
assign NOT_rob_deqPort_0_canDeq__4362_4363_OR_rob_RDY_ETC___d14401 =
|
|
(!rob$deqPort_0_canDeq ||
|
|
rob$RDY_deqPort_0_deq &&
|
|
regRenamingTable$RDY_commit_0_commit) &&
|
|
(!rob$deqPort_1_canDeq ||
|
|
rob$RDY_deqPort_1_deq_data &&
|
|
NOT_rob_deqPort_1_deq_data__4369_BIT_25_4370_4_ETC___d14398) ;
|
|
assign NOT_rob_deqPort_0_canDeq__4362_4363_OR_rob_deq_ETC___d14454 =
|
|
(!rob$deqPort_0_canDeq ||
|
|
rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] &&
|
|
!rob$deqPort_0_deq_data[103] &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd0 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd21 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd17 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd18 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd13 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd16 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd15 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd19 &&
|
|
rob$deqPort_0_deq_data[122:118] != 5'd20) &&
|
|
rob$deqPort_1_canDeq ;
|
|
assign NOT_rob_deqPort_0_deq_data__3921_BITS_122_TO_1_ETC___d14162 =
|
|
rob$deqPort_0_deq_data[122:118] != 5'd13 ||
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 !=
|
|
6'd7 ||
|
|
csrf_stats_module_writeQ$FULL_N) &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 !=
|
|
6'd6 ||
|
|
csrf_terminate_module_terminateQ$FULL_N) ;
|
|
assign NOT_rob_deqPort_1_deq_data__4369_BIT_25_4370_4_ETC___d14398 =
|
|
!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
|
|
rob$deqPort_1_deq_data[103] ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd0 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd21 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd17 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd18 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd13 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd15 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd20 ||
|
|
rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit ;
|
|
assign NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13621 =
|
|
!specTagManager$canClaim ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13488 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13568 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$RDY_nextSpecTag ;
|
|
assign NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13686 =
|
|
!specTagManager$canClaim ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13568 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$RDY_nextSpecTag ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2912 =
|
|
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 } ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2921 =
|
|
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2912,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 } ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2930 =
|
|
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2921,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 } ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2937 =
|
|
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250,
|
|
!CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251,
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2930,
|
|
x__h288783 } ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d14601 =
|
|
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 } ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14557 =
|
|
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 } ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14566 =
|
|
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14557,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 } ;
|
|
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14575 =
|
|
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d14566,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 } ;
|
|
assign SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13435 =
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416 ||
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1 &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13188 ||
|
|
!regRenamingTable$rename_1_canRename ||
|
|
fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13432 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5935 =
|
|
{ coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63[10],
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63 } ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5935 ^
|
|
12'h800) <=
|
|
12'd2175 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5935 ^
|
|
12'h800) <
|
|
12'd1922 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5935 +
|
|
12'd127 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q69 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] -
|
|
8'd127 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4543 =
|
|
{ coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28[10],
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28 } ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4543 ^
|
|
12'h800) <=
|
|
12'd2175 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4543 ^
|
|
12'h800) <
|
|
12'd1922 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4543 +
|
|
12'd127 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q34 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] -
|
|
8'd127 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7327 =
|
|
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98[10],
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98 } ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7327 ^
|
|
12'h800) <=
|
|
12'd2175 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7327 ^
|
|
12'h800) <
|
|
12'd1922 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q104 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] -
|
|
8'd127 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7327 +
|
|
12'd127 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10107 =
|
|
{ {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168[7]}},
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168 } ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10107 ^
|
|
12'h800) <=
|
|
12'd3071 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10107 ^
|
|
12'h800) <
|
|
12'd1026 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8634 =
|
|
{ {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128[7]}},
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128 } ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8634 ^
|
|
12'h800) <=
|
|
12'd3071 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8634 ^
|
|
12'h800) <
|
|
12'd1026 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9344 =
|
|
{ {4{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145[7]}},
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145 } ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9344 ^
|
|
12'h800) <=
|
|
12'd3071 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9344 ^
|
|
12'h800) <
|
|
12'd1026 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8634 +
|
|
12'd1023 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q132 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] -
|
|
11'd1023 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9344 +
|
|
12'd1023 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q149 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] -
|
|
11'd1023 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10107 +
|
|
12'd1023 ;
|
|
assign SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q172 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] -
|
|
11'd1023 ;
|
|
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4241 =
|
|
({ 3'd0,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4239 } ^
|
|
9'h100) <=
|
|
9'd256 ;
|
|
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5161 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h351360 == 8'd0 &&
|
|
(sfdin__h351354[56:34] == 23'd0 || guard__h343259 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h351957 == 8'd255 &&
|
|
_theResult___fst_sfd__h351958 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h351360 != 8'd255 &&
|
|
guard__h343259 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5633 =
|
|
({ 3'd0,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5631 } ^
|
|
9'h100) <=
|
|
9'd256 ;
|
|
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6553 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h397050 == 8'd0 &&
|
|
(sfdin__h397044[56:34] == 23'd0 || guard__h388951 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h397647 == 8'd255 &&
|
|
_theResult___fst_sfd__h397648 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h397050 != 8'd255 &&
|
|
guard__h388951 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7025 =
|
|
({ 3'd0,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7023 } ^
|
|
9'h100) <=
|
|
9'd256 ;
|
|
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7945 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h442738 == 8'd0 &&
|
|
(sfdin__h442732[56:34] == 23'd0 || guard__h434639 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h443335 == 8'd255 &&
|
|
_theResult___fst_sfd__h443336 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h442738 != 8'd255 &&
|
|
guard__h434639 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10358 =
|
|
({ 6'd0,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10356 } ^
|
|
12'h800) <=
|
|
12'd2048 ;
|
|
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10732 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h508200 == 11'd0 &&
|
|
(sfdin__h508194[56:5] == 52'd0 || guard__h499974 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h509032 == 11'd2047 &&
|
|
_theResult___fst_sfd__h509033 == 52'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h508200 != 11'd2047 &&
|
|
guard__h499974 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10773 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h547001 == 11'd0 &&
|
|
(sfdin__h546995[56:5] == 52'd0 || guard__h538775 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h547833 == 11'd2047 &&
|
|
_theResult___fst_sfd__h547834 == 52'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h547001 != 11'd2047 &&
|
|
guard__h538775 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10817 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h586202 == 11'd0 &&
|
|
(sfdin__h586196[56:5] == 52'd0 || guard__h577976 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h587034 == 11'd2047 &&
|
|
_theResult___fst_sfd__h587035 == 52'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h586202 != 11'd2047 &&
|
|
guard__h577976 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8885 =
|
|
({ 6'd0,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8883 } ^
|
|
12'h800) <=
|
|
12'd2048 ;
|
|
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9595 =
|
|
({ 6'd0,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9593 } ^
|
|
12'h800) <=
|
|
12'd2048 ;
|
|
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4792 =
|
|
({ 3'd0,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4790 } ^
|
|
9'h100) <=
|
|
9'd256 ;
|
|
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5190 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h369126 == 8'd0 &&
|
|
(sfdin__h369120[56:34] == 23'd0 || guard__h360898 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h369723 == 8'd255 &&
|
|
_theResult___fst_sfd__h369724 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h369126 != 8'd255 &&
|
|
guard__h360898 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6184 =
|
|
({ 3'd0,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6182 } ^
|
|
9'h100) <=
|
|
9'd256 ;
|
|
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6582 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h414816 == 8'd0 &&
|
|
(sfdin__h414810[56:34] == 23'd0 || guard__h406588 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h415413 == 8'd255 &&
|
|
_theResult___fst_sfd__h415414 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h414816 != 8'd255 &&
|
|
guard__h406588 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7576 =
|
|
({ 3'd0,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7574 } ^
|
|
9'h100) <=
|
|
9'd256 ;
|
|
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7974 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h460504 == 8'd0 &&
|
|
(sfdin__h460498[56:34] == 23'd0 || guard__h452276 != 2'b0),
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h461101 == 8'd255 &&
|
|
_theResult___fst_sfd__h461102 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h460504 != 8'd255 &&
|
|
guard__h452276 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4472 =
|
|
({ 3'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4470 } ^
|
|
9'h100) <=
|
|
9'd384 ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4865 =
|
|
({ 3'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4470 } ^
|
|
9'h100) <=
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4864 ^
|
|
9'h100) ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5173 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h360016 == 8'd0 &&
|
|
guard__h351968 != 2'b0,
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h360539 == 8'd255 &&
|
|
_theResult___fst_sfd__h360540 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h360016 != 8'd255 &&
|
|
guard__h351968 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5864 =
|
|
({ 3'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5862 } ^
|
|
9'h100) <=
|
|
9'd384 ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6257 =
|
|
({ 3'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5862 } ^
|
|
9'h100) <=
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6256 ^
|
|
9'h100) ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6565 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h405706 == 8'd0 &&
|
|
guard__h397658 != 2'b0,
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h406229 == 8'd255 &&
|
|
_theResult___fst_sfd__h406230 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h405706 != 8'd255 &&
|
|
guard__h397658 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7256 =
|
|
({ 3'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7254 } ^
|
|
9'h100) <=
|
|
9'd384 ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7649 =
|
|
({ 3'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7254 } ^
|
|
9'h100) <=
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7648 ^
|
|
9'h100) ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7957 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h451394 == 8'd0 &&
|
|
guard__h443346 != 2'b0,
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h451917 == 8'd255 &&
|
|
_theResult___fst_sfd__h451918 == 23'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h451394 != 8'd255 &&
|
|
guard__h443346 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10061 =
|
|
({ 6'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10059 } ^
|
|
12'h800) <=
|
|
12'd2944 ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10408 =
|
|
({ 6'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10059 } ^
|
|
12'h800) <=
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10407 ^
|
|
12'h800) ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10715 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h498623 == 11'd0 &&
|
|
guard__h490662 != 2'b0,
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h499381 == 11'd2047 &&
|
|
_theResult___fst_sfd__h499382 == 52'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h498623 != 11'd2047 &&
|
|
guard__h490662 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10756 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h537424 == 11'd0 &&
|
|
guard__h529463 != 2'b0,
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h538182 == 11'd2047 &&
|
|
_theResult___fst_sfd__h538183 == 52'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h537424 != 11'd2047 &&
|
|
guard__h529463 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10800 =
|
|
{ 3'd0,
|
|
_theResult___fst_exp__h576625 == 11'd0 &&
|
|
guard__h568664 != 2'b0,
|
|
1'd0 } |
|
|
{ 2'd0,
|
|
_theResult___fst_exp__h577383 == 11'd2047 &&
|
|
_theResult___fst_sfd__h577384 == 52'd0,
|
|
1'd0,
|
|
_theResult___fst_exp__h576625 != 11'd2047 &&
|
|
guard__h568664 != 2'b0 } ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8573 =
|
|
({ 6'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8571 } ^
|
|
12'h800) <=
|
|
12'd2944 ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8935 =
|
|
({ 6'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8571 } ^
|
|
12'h800) <=
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8934 ^
|
|
12'h800) ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9298 =
|
|
({ 6'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9296 } ^
|
|
12'h800) <=
|
|
12'd2944 ;
|
|
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9645 =
|
|
({ 6'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9296 } ^
|
|
12'h800) <=
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9644 ^
|
|
12'h800) ;
|
|
assign _0_OR_NOT_fetchStage_pipelines_0_first__2595_BI_ETC___d13549 =
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$RDY_nextSpecTag) &&
|
|
CASE_k59336_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 ;
|
|
assign _0_OR_NOT_fetchStage_pipelines_1_first__2604_BI_ETC___d13634 =
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
specTagManager$RDY_nextSpecTag) &&
|
|
CASE_fetchStagepipelines_0_canDeq_AND_NOT_fet_ETC__q234 ;
|
|
assign _0_OR_fetchStage_RDY_pipelines_0_first__2592_34_ETC___d13460 =
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1 &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13188 ||
|
|
!regRenamingTable$rename_1_canRename ||
|
|
fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13432 ;
|
|
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4550 =
|
|
sfd__h335644 >>
|
|
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4546[11] ?
|
|
12'hAAA :
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4546) ;
|
|
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5942 =
|
|
sfd__h381339 >>
|
|
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5938[11] ?
|
|
12'hAAA :
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5938) ;
|
|
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7334 =
|
|
sfd__h427027 >>
|
|
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7330[11] ?
|
|
12'hAAA :
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7330) ;
|
|
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10114 =
|
|
sfd__h518564 >>
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10110 ;
|
|
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8641 =
|
|
sfd__h479622 >>
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8637 ;
|
|
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9351 =
|
|
sfd__h557765 >>
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9347 ;
|
|
assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1592_1593_ETC___d14025 =
|
|
medeleg_csr__read__h607086[i__h689145] ;
|
|
assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1600_1601_ETC___d14007 =
|
|
mideleg_csr__read__h607181[i__h689305] ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4003 =
|
|
12'd3074 -
|
|
{ 6'd0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
|
|
6'd0 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
|
|
6'd1 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
|
|
6'd24 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
|
|
6'd25 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
|
|
6'd26 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
|
|
6'd27 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
|
|
6'd28 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
|
|
6'd29 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
|
|
6'd30 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
|
|
6'd31 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
|
|
6'd32 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
|
|
6'd33 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
|
|
6'd34 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
|
|
6'd35 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
|
|
6'd36 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
|
|
6'd37 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
|
|
6'd38 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
|
|
6'd39 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
|
|
6'd40 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
|
|
6'd41 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
|
|
6'd42 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
|
|
6'd43 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
|
|
6'd44 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
|
|
6'd45 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
|
|
6'd46 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
|
|
6'd47 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
|
|
6'd48 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
|
|
6'd49 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
|
|
6'd50 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
|
|
6'd51 :
|
|
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 =
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4003 ^
|
|
12'h800) <=
|
|
12'd2175 ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 =
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4003 ^
|
|
12'h800) <
|
|
12'd1922 ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5176 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5161[4] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5173[4]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5201 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5161[3] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5173[3]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5228 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5161[1] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5173[1]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5395 =
|
|
12'd3074 -
|
|
{ 6'd0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
|
|
6'd0 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
|
|
6'd1 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
|
|
6'd24 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
|
|
6'd25 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
|
|
6'd26 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
|
|
6'd27 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
|
|
6'd28 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
|
|
6'd29 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
|
|
6'd30 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
|
|
6'd31 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
|
|
6'd32 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
|
|
6'd33 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
|
|
6'd34 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
|
|
6'd35 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
|
|
6'd36 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
|
|
6'd37 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
|
|
6'd38 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
|
|
6'd39 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
|
|
6'd40 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
|
|
6'd41 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
|
|
6'd42 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
|
|
6'd43 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
|
|
6'd44 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
|
|
6'd45 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
|
|
6'd46 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
|
|
6'd47 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
|
|
6'd48 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
|
|
6'd49 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
|
|
6'd50 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
|
|
6'd51 :
|
|
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 =
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5395 ^
|
|
12'h800) <=
|
|
12'd2175 ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 =
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5395 ^
|
|
12'h800) <
|
|
12'd1922 ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6568 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6553[4] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6565[4]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6593 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6553[3] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6565[3]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6620 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6553[1] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6565[1]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6787 =
|
|
12'd3074 -
|
|
{ 6'd0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
|
|
6'd0 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
|
|
6'd1 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
|
|
6'd2 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
|
|
6'd3 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
|
|
6'd4 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
|
|
6'd5 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
|
|
6'd6 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
|
|
6'd7 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
|
|
6'd8 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
|
|
6'd9 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
|
|
6'd10 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
|
|
6'd11 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
|
|
6'd12 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
|
|
6'd13 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
|
|
6'd14 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
|
|
6'd15 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
|
|
6'd16 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
|
|
6'd17 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
|
|
6'd18 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
|
|
6'd19 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
|
|
6'd20 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
|
|
6'd21 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
|
|
6'd22 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
|
|
6'd23 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
|
|
6'd24 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
|
|
6'd25 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
|
|
6'd26 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
|
|
6'd27 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
|
|
6'd28 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
|
|
6'd29 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
|
|
6'd30 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
|
|
6'd31 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
|
|
6'd32 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
|
|
6'd33 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
|
|
6'd34 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
|
|
6'd35 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
|
|
6'd36 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
|
|
6'd37 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
|
|
6'd38 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
|
|
6'd39 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
|
|
6'd40 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
|
|
6'd41 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
|
|
6'd42 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
|
|
6'd43 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
|
|
6'd44 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
|
|
6'd45 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
|
|
6'd46 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
|
|
6'd47 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
|
|
6'd48 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
|
|
6'd49 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
|
|
6'd50 :
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
|
|
6'd51 :
|
|
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 =
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6787 ^
|
|
12'h800) <=
|
|
12'd2175 ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 =
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6787 ^
|
|
12'h800) <
|
|
12'd1922 ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7960 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7945[4] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7957[4]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7985 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7945[3] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7957[3]) ;
|
|
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8012 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 &&
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7945[1] :
|
|
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7957[1]) ;
|
|
assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10110 =
|
|
12'd3074 -
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10107 ;
|
|
assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8637 =
|
|
12'd3074 -
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8634 ;
|
|
assign _3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9347 =
|
|
12'd3074 -
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9344 ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8497 =
|
|
12'd3970 -
|
|
{ 7'd0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162] ?
|
|
5'd0 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[161] ?
|
|
5'd1 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[160] ?
|
|
5'd2 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[159] ?
|
|
5'd3 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[158] ?
|
|
5'd4 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[157] ?
|
|
5'd5 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[156] ?
|
|
5'd6 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[155] ?
|
|
5'd7 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[154] ?
|
|
5'd8 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[153] ?
|
|
5'd9 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[152] ?
|
|
5'd10 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[151] ?
|
|
5'd11 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[150] ?
|
|
5'd12 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[149] ?
|
|
5'd13 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[148] ?
|
|
5'd14 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[147] ?
|
|
5'd15 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[146] ?
|
|
5'd16 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[145] ?
|
|
5'd17 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[144] ?
|
|
5'd18 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[143] ?
|
|
5'd19 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[142] ?
|
|
5'd20 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[141] ?
|
|
5'd21 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[140] ?
|
|
5'd22 :
|
|
5'd23)))))))))))))))))))))) } ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 =
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8497 ^
|
|
12'h800) <=
|
|
12'd3071 ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 =
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8497 ^
|
|
12'h800) <
|
|
12'd1026 ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9222 =
|
|
12'd3970 -
|
|
{ 7'd0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34] ?
|
|
5'd0 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[33] ?
|
|
5'd1 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[32] ?
|
|
5'd2 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[31] ?
|
|
5'd3 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[30] ?
|
|
5'd4 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[29] ?
|
|
5'd5 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[28] ?
|
|
5'd6 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[27] ?
|
|
5'd7 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[26] ?
|
|
5'd8 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[25] ?
|
|
5'd9 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[24] ?
|
|
5'd10 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[23] ?
|
|
5'd11 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[22] ?
|
|
5'd12 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[21] ?
|
|
5'd13 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[20] ?
|
|
5'd14 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[19] ?
|
|
5'd15 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[18] ?
|
|
5'd16 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[17] ?
|
|
5'd17 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[16] ?
|
|
5'd18 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[15] ?
|
|
5'd19 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[14] ?
|
|
5'd20 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[13] ?
|
|
5'd21 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[12] ?
|
|
5'd22 :
|
|
5'd23)))))))))))))))))))))) } ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 =
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9222 ^
|
|
12'h800) <=
|
|
12'd3071 ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 =
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9222 ^
|
|
12'h800) <
|
|
12'd1026 ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9985 =
|
|
12'd3970 -
|
|
{ 7'd0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98] ?
|
|
5'd0 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[97] ?
|
|
5'd1 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[96] ?
|
|
5'd2 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[95] ?
|
|
5'd3 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[94] ?
|
|
5'd4 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[93] ?
|
|
5'd5 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[92] ?
|
|
5'd6 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[91] ?
|
|
5'd7 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[90] ?
|
|
5'd8 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[89] ?
|
|
5'd9 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[88] ?
|
|
5'd10 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[87] ?
|
|
5'd11 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[86] ?
|
|
5'd12 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[85] ?
|
|
5'd13 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[84] ?
|
|
5'd14 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[83] ?
|
|
5'd15 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[82] ?
|
|
5'd16 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[81] ?
|
|
5'd17 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[80] ?
|
|
5'd18 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[79] ?
|
|
5'd19 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[78] ?
|
|
5'd20 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[77] ?
|
|
5'd21 :
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[76] ?
|
|
5'd22 :
|
|
5'd23)))))))))))))))))))))) } ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 =
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9985 ^
|
|
12'h800) <=
|
|
12'd3071 ;
|
|
assign _3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 =
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9985 ^
|
|
12'h800) <
|
|
12'd1026 ;
|
|
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4546 =
|
|
12'd3970 -
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4543 ;
|
|
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5938 =
|
|
12'd3970 -
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5935 ;
|
|
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7330 =
|
|
12'd3970 -
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7327 ;
|
|
assign _dfoo12 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13728 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805 &&
|
|
fetchStage$pipelines_1_first[98:96] == 3'd2 &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13855 &&
|
|
fetchStage$pipelines_1_first[103:99] != 5'd14 ;
|
|
assign _dfoo16 =
|
|
k__h659336 == 1'd1 &&
|
|
fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13710 ||
|
|
(fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13783 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13792) ==
|
|
1'd1 &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13810 ;
|
|
assign _dfoo18 =
|
|
k__h659336 == 1'd0 &&
|
|
fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13710 ||
|
|
(fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13783 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13792) ==
|
|
1'd0 &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13810 ;
|
|
assign _dfoo2 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13756 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805 &&
|
|
fetchStage$pipelines_1_first[98:96] == 3'd2 &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13855 &&
|
|
fetchStage$pipelines_1_first[95:93] != 3'd0 &&
|
|
fetchStage$pipelines_1_first[95:93] != 3'd2 ;
|
|
assign _dfoo20 =
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd20 ;
|
|
assign _dfoo28 =
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
(IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd8 ||
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 ==
|
|
6'd18) ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd19 ;
|
|
assign _dfoo7 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13748 ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13797 &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805 &&
|
|
fetchStage$pipelines_1_first[98:96] == 3'd2 &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13855 &&
|
|
(fetchStage$pipelines_1_first[95:93] == 3'd0 ||
|
|
fetchStage$pipelines_1_first[95:93] == 3'd2) ;
|
|
assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign _dor1coreFix_aluExe_0_bypassWire_3$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_aluExe_1_bypassWire_2$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign _dor1coreFix_aluExe_1_bypassWire_3$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_bypassWire_2$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign _dor1coreFix_memExe_bypassWire_3$EN_wset =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1rf$EN_write_0_wr =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign _dor1rf$EN_write_1_wr =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign _dor1sbAggr$EN_setReady_3_put =
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
|
|
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
|
|
assign _dor1sbCons$EN_setReady_0_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
|
|
assign _dor1sbCons$EN_setReady_1_put =
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
|
|
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
|
|
assign _theResult_____2__h293689 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3038) ?
|
|
next_deqP___1__h293968 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ;
|
|
assign _theResult_____2__h301685 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3145) ?
|
|
next_deqP___1__h301964 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ;
|
|
assign _theResult_____2__h307679 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3316) ?
|
|
next_deqP___1__h308245 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ;
|
|
assign _theResult_____2__h315533 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3412) ?
|
|
next_deqP___1__h316099 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ;
|
|
assign _theResult_____2__h325877 =
|
|
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3641) ?
|
|
next_deqP___1__h326156 :
|
|
coreFix_memExe_memRespLdQ_deqP ;
|
|
assign _theResult_____2__h329102 =
|
|
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3735) ?
|
|
next_deqP___1__h329381 :
|
|
coreFix_memExe_forwardQ_deqP ;
|
|
assign _theResult____h343249 =
|
|
(value__h343871 == 54'd0) ? sfd__h335644 : 57'd1 ;
|
|
assign _theResult____h360888 =
|
|
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4546 ^
|
|
12'h800) <
|
|
12'd2105) ?
|
|
result__h361501 :
|
|
_theResult____h343249 ;
|
|
assign _theResult____h388941 =
|
|
(value__h389561 == 54'd0) ? sfd__h381339 : 57'd1 ;
|
|
assign _theResult____h406578 =
|
|
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5938 ^
|
|
12'h800) <
|
|
12'd2105) ?
|
|
result__h407191 :
|
|
_theResult____h388941 ;
|
|
assign _theResult____h434629 =
|
|
(value__h435249 == 54'd0) ? sfd__h427027 : 57'd1 ;
|
|
assign _theResult____h452266 =
|
|
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7330 ^
|
|
12'h800) <
|
|
12'd2105) ?
|
|
result__h452879 :
|
|
_theResult____h434629 ;
|
|
assign _theResult____h499964 =
|
|
((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8637 ^
|
|
12'h800) <
|
|
12'd2105) ?
|
|
result__h500577 :
|
|
((value__h484180 == 25'd0) ? sfd__h479622 : 57'd1) ;
|
|
assign _theResult____h538765 =
|
|
((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10110 ^
|
|
12'h800) <
|
|
12'd2105) ?
|
|
result__h539378 :
|
|
((value__h522981 == 25'd0) ? sfd__h518564 : 57'd1) ;
|
|
assign _theResult____h577966 =
|
|
((_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9347 ^
|
|
12'h800) <
|
|
12'd2105) ?
|
|
result__h578579 :
|
|
((value__h562182 == 25'd0) ? sfd__h557765 : 57'd1) ;
|
|
assign _theResult____h645120 =
|
|
(csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ?
|
|
enabled_ints___1__h645617 :
|
|
15'd0 ;
|
|
assign _theResult___exp__h351876 =
|
|
sfd__h351452[24] ?
|
|
((_theResult___fst_exp__h351360 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h378393) :
|
|
((_theResult___fst_exp__h351360 == 8'd0 &&
|
|
sfd__h351452[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h351360) ;
|
|
assign _theResult___exp__h360458 =
|
|
sfd__h360034[24] ?
|
|
((_theResult___fst_exp__h360016 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h378417) :
|
|
((_theResult___fst_exp__h360016 == 8'd0 &&
|
|
sfd__h360034[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h360016) ;
|
|
assign _theResult___exp__h369642 =
|
|
sfd__h369218[24] ?
|
|
((_theResult___fst_exp__h369126 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h378447) :
|
|
((_theResult___fst_exp__h369126 == 8'd0 &&
|
|
sfd__h369218[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h369126) ;
|
|
assign _theResult___exp__h378278 =
|
|
sfd__h377830[24] ?
|
|
((_theResult___fst_exp__h377811 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h378471) :
|
|
((_theResult___fst_exp__h377811 == 8'd0 &&
|
|
sfd__h377830[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h377811) ;
|
|
assign _theResult___exp__h378380 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047) ?
|
|
8'd255 :
|
|
_theResult___fst_exp__h378371 ;
|
|
assign _theResult___exp__h397566 =
|
|
sfd__h397142[24] ?
|
|
((_theResult___fst_exp__h397050 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h424083) :
|
|
((_theResult___fst_exp__h397050 == 8'd0 &&
|
|
sfd__h397142[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h397050) ;
|
|
assign _theResult___exp__h406148 =
|
|
sfd__h405724[24] ?
|
|
((_theResult___fst_exp__h405706 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h424107) :
|
|
((_theResult___fst_exp__h405706 == 8'd0 &&
|
|
sfd__h405724[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h405706) ;
|
|
assign _theResult___exp__h415332 =
|
|
sfd__h414908[24] ?
|
|
((_theResult___fst_exp__h414816 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h424137) :
|
|
((_theResult___fst_exp__h414816 == 8'd0 &&
|
|
sfd__h414908[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h414816) ;
|
|
assign _theResult___exp__h423968 =
|
|
sfd__h423520[24] ?
|
|
((_theResult___fst_exp__h423501 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h424161) :
|
|
((_theResult___fst_exp__h423501 == 8'd0 &&
|
|
sfd__h423520[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h423501) ;
|
|
assign _theResult___exp__h424070 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047) ?
|
|
8'd255 :
|
|
_theResult___fst_exp__h424061 ;
|
|
assign _theResult___exp__h443254 =
|
|
sfd__h442830[24] ?
|
|
((_theResult___fst_exp__h442738 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h469771) :
|
|
((_theResult___fst_exp__h442738 == 8'd0 &&
|
|
sfd__h442830[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h442738) ;
|
|
assign _theResult___exp__h451836 =
|
|
sfd__h451412[24] ?
|
|
((_theResult___fst_exp__h451394 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h469795) :
|
|
((_theResult___fst_exp__h451394 == 8'd0 &&
|
|
sfd__h451412[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h451394) ;
|
|
assign _theResult___exp__h461020 =
|
|
sfd__h460596[24] ?
|
|
((_theResult___fst_exp__h460504 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h469825) :
|
|
((_theResult___fst_exp__h460504 == 8'd0 &&
|
|
sfd__h460596[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h460504) ;
|
|
assign _theResult___exp__h469656 =
|
|
sfd__h469208[24] ?
|
|
((_theResult___fst_exp__h469189 == 8'd254) ?
|
|
8'd255 :
|
|
din_inc___2_exp__h469849) :
|
|
((_theResult___fst_exp__h469189 == 8'd0 &&
|
|
sfd__h469208[24:23] == 2'b01) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h469189) ;
|
|
assign _theResult___exp__h469758 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047) ?
|
|
8'd255 :
|
|
_theResult___fst_exp__h469749 ;
|
|
assign _theResult___exp__h499278 =
|
|
sfd__h498641[53] ?
|
|
((_theResult___fst_exp__h498623 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h517873) :
|
|
((_theResult___fst_exp__h498623 == 11'd0 &&
|
|
sfd__h498641[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h498623) ;
|
|
assign _theResult___exp__h508929 =
|
|
sfd__h508292[53] ?
|
|
((_theResult___fst_exp__h508200 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h517908) :
|
|
((_theResult___fst_exp__h508200 == 11'd0 &&
|
|
sfd__h508292[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h508200) ;
|
|
assign _theResult___exp__h517713 =
|
|
sfd__h517052[53] ?
|
|
((_theResult___fst_exp__h517033 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h517934) :
|
|
((_theResult___fst_exp__h517033 == 11'd0 &&
|
|
sfd__h517052[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h517033) ;
|
|
assign _theResult___exp__h538079 =
|
|
sfd__h537442[53] ?
|
|
((_theResult___fst_exp__h537424 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h556674) :
|
|
((_theResult___fst_exp__h537424 == 11'd0 &&
|
|
sfd__h537442[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h537424) ;
|
|
assign _theResult___exp__h547730 =
|
|
sfd__h547093[53] ?
|
|
((_theResult___fst_exp__h547001 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h556709) :
|
|
((_theResult___fst_exp__h547001 == 11'd0 &&
|
|
sfd__h547093[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h547001) ;
|
|
assign _theResult___exp__h556514 =
|
|
sfd__h555853[53] ?
|
|
((_theResult___fst_exp__h555834 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h556735) :
|
|
((_theResult___fst_exp__h555834 == 11'd0 &&
|
|
sfd__h555853[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h555834) ;
|
|
assign _theResult___exp__h577280 =
|
|
sfd__h576643[53] ?
|
|
((_theResult___fst_exp__h576625 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h595875) :
|
|
((_theResult___fst_exp__h576625 == 11'd0 &&
|
|
sfd__h576643[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h576625) ;
|
|
assign _theResult___exp__h586931 =
|
|
sfd__h586294[53] ?
|
|
((_theResult___fst_exp__h586202 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h595910) :
|
|
((_theResult___fst_exp__h586202 == 11'd0 &&
|
|
sfd__h586294[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h586202) ;
|
|
assign _theResult___exp__h595715 =
|
|
sfd__h595054[53] ?
|
|
((_theResult___fst_exp__h595035 == 11'd2046) ?
|
|
11'd2047 :
|
|
din_inc___2_exp__h595936) :
|
|
((_theResult___fst_exp__h595035 == 11'd0 &&
|
|
sfd__h595054[53:52] == 2'b01) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h595035) ;
|
|
assign _theResult___fst__h600208 =
|
|
a__h599786[63] ? a___1__h600213 : a__h599786 ;
|
|
assign _theResult___fst_exp__h351360 =
|
|
_theResult____h343249[56] ?
|
|
8'd2 :
|
|
_theResult___fst_exp__h351434 ;
|
|
assign _theResult___fst_exp__h351425 =
|
|
8'd0 -
|
|
{ 2'd0,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4239 } ;
|
|
assign _theResult___fst_exp__h351431 =
|
|
(!_theResult____h343249[56] && !_theResult____h343249[55] &&
|
|
!_theResult____h343249[54] &&
|
|
!_theResult____h343249[53] &&
|
|
!_theResult____h343249[52] &&
|
|
!_theResult____h343249[51] &&
|
|
!_theResult____h343249[50] &&
|
|
!_theResult____h343249[49] &&
|
|
!_theResult____h343249[48] &&
|
|
!_theResult____h343249[47] &&
|
|
!_theResult____h343249[46] &&
|
|
!_theResult____h343249[45] &&
|
|
!_theResult____h343249[44] &&
|
|
!_theResult____h343249[43] &&
|
|
!_theResult____h343249[42] &&
|
|
!_theResult____h343249[41] &&
|
|
!_theResult____h343249[40] &&
|
|
!_theResult____h343249[39] &&
|
|
!_theResult____h343249[38] &&
|
|
!_theResult____h343249[37] &&
|
|
!_theResult____h343249[36] &&
|
|
!_theResult____h343249[35] &&
|
|
!_theResult____h343249[34] &&
|
|
!_theResult____h343249[33] &&
|
|
!_theResult____h343249[32] &&
|
|
!_theResult____h343249[31] &&
|
|
!_theResult____h343249[30] &&
|
|
!_theResult____h343249[29] &&
|
|
!_theResult____h343249[28] &&
|
|
!_theResult____h343249[27] &&
|
|
!_theResult____h343249[26] &&
|
|
!_theResult____h343249[25] &&
|
|
!_theResult____h343249[24] &&
|
|
!_theResult____h343249[23] &&
|
|
!_theResult____h343249[22] &&
|
|
!_theResult____h343249[21] &&
|
|
!_theResult____h343249[20] &&
|
|
!_theResult____h343249[19] &&
|
|
!_theResult____h343249[18] &&
|
|
!_theResult____h343249[17] &&
|
|
!_theResult____h343249[16] &&
|
|
!_theResult____h343249[15] &&
|
|
!_theResult____h343249[14] &&
|
|
!_theResult____h343249[13] &&
|
|
!_theResult____h343249[12] &&
|
|
!_theResult____h343249[11] &&
|
|
!_theResult____h343249[10] &&
|
|
!_theResult____h343249[9] &&
|
|
!_theResult____h343249[8] &&
|
|
!_theResult____h343249[7] &&
|
|
!_theResult____h343249[6] &&
|
|
!_theResult____h343249[5] &&
|
|
!_theResult____h343249[4] &&
|
|
!_theResult____h343249[3] &&
|
|
!_theResult____h343249[2] &&
|
|
!_theResult____h343249[1] &&
|
|
!_theResult____h343249[0] ||
|
|
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4241) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h351425 ;
|
|
assign _theResult___fst_exp__h351434 =
|
|
(!_theResult____h343249[56] && _theResult____h343249[55]) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h351431 ;
|
|
assign _theResult___fst_exp__h351957 =
|
|
(_theResult___fst_exp__h351360 == 8'd255) ?
|
|
_theResult___fst_exp__h351360 :
|
|
_theResult___fst_exp__h351954 ;
|
|
assign _theResult___fst_exp__h360007 =
|
|
8'd129 -
|
|
{ 2'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4470 } ;
|
|
assign _theResult___fst_exp__h360013 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4415 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4472) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h360007 ;
|
|
assign _theResult___fst_exp__h360016 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___fst_exp__h360013 :
|
|
8'd129 ;
|
|
assign _theResult___fst_exp__h360539 =
|
|
(_theResult___fst_exp__h360016 == 8'd255) ?
|
|
_theResult___fst_exp__h360016 :
|
|
_theResult___fst_exp__h360536 ;
|
|
assign _theResult___fst_exp__h369126 =
|
|
_theResult____h360888[56] ?
|
|
8'd2 :
|
|
_theResult___fst_exp__h369200 ;
|
|
assign _theResult___fst_exp__h369191 =
|
|
8'd0 -
|
|
{ 2'd0,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4790 } ;
|
|
assign _theResult___fst_exp__h369197 =
|
|
(!_theResult____h360888[56] && !_theResult____h360888[55] &&
|
|
!_theResult____h360888[54] &&
|
|
!_theResult____h360888[53] &&
|
|
!_theResult____h360888[52] &&
|
|
!_theResult____h360888[51] &&
|
|
!_theResult____h360888[50] &&
|
|
!_theResult____h360888[49] &&
|
|
!_theResult____h360888[48] &&
|
|
!_theResult____h360888[47] &&
|
|
!_theResult____h360888[46] &&
|
|
!_theResult____h360888[45] &&
|
|
!_theResult____h360888[44] &&
|
|
!_theResult____h360888[43] &&
|
|
!_theResult____h360888[42] &&
|
|
!_theResult____h360888[41] &&
|
|
!_theResult____h360888[40] &&
|
|
!_theResult____h360888[39] &&
|
|
!_theResult____h360888[38] &&
|
|
!_theResult____h360888[37] &&
|
|
!_theResult____h360888[36] &&
|
|
!_theResult____h360888[35] &&
|
|
!_theResult____h360888[34] &&
|
|
!_theResult____h360888[33] &&
|
|
!_theResult____h360888[32] &&
|
|
!_theResult____h360888[31] &&
|
|
!_theResult____h360888[30] &&
|
|
!_theResult____h360888[29] &&
|
|
!_theResult____h360888[28] &&
|
|
!_theResult____h360888[27] &&
|
|
!_theResult____h360888[26] &&
|
|
!_theResult____h360888[25] &&
|
|
!_theResult____h360888[24] &&
|
|
!_theResult____h360888[23] &&
|
|
!_theResult____h360888[22] &&
|
|
!_theResult____h360888[21] &&
|
|
!_theResult____h360888[20] &&
|
|
!_theResult____h360888[19] &&
|
|
!_theResult____h360888[18] &&
|
|
!_theResult____h360888[17] &&
|
|
!_theResult____h360888[16] &&
|
|
!_theResult____h360888[15] &&
|
|
!_theResult____h360888[14] &&
|
|
!_theResult____h360888[13] &&
|
|
!_theResult____h360888[12] &&
|
|
!_theResult____h360888[11] &&
|
|
!_theResult____h360888[10] &&
|
|
!_theResult____h360888[9] &&
|
|
!_theResult____h360888[8] &&
|
|
!_theResult____h360888[7] &&
|
|
!_theResult____h360888[6] &&
|
|
!_theResult____h360888[5] &&
|
|
!_theResult____h360888[4] &&
|
|
!_theResult____h360888[3] &&
|
|
!_theResult____h360888[2] &&
|
|
!_theResult____h360888[1] &&
|
|
!_theResult____h360888[0] ||
|
|
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4792) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h369191 ;
|
|
assign _theResult___fst_exp__h369200 =
|
|
(!_theResult____h360888[56] && _theResult____h360888[55]) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h369197 ;
|
|
assign _theResult___fst_exp__h369723 =
|
|
(_theResult___fst_exp__h369126 == 8'd255) ?
|
|
_theResult___fst_exp__h369126 :
|
|
_theResult___fst_exp__h369720 ;
|
|
assign _theResult___fst_exp__h377763 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ==
|
|
8'd0) ?
|
|
8'd1 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] ;
|
|
assign _theResult___fst_exp__h377802 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q29[7:0] -
|
|
{ 2'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4470 } ;
|
|
assign _theResult___fst_exp__h377808 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4415 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4865) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h377802 ;
|
|
assign _theResult___fst_exp__h377811 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___fst_exp__h377808 :
|
|
_theResult___fst_exp__h377763 ;
|
|
assign _theResult___fst_exp__h378359 =
|
|
(_theResult___fst_exp__h377811 == 8'd255) ?
|
|
_theResult___fst_exp__h377811 :
|
|
_theResult___fst_exp__h378356 ;
|
|
assign _theResult___fst_exp__h378368 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 ?
|
|
_theResult___snd_fst_exp__h360542 :
|
|
_theResult___fst_exp__h343231) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 ?
|
|
_theResult___snd_fst_exp__h378362 :
|
|
_theResult___fst_exp__h343231) ;
|
|
assign _theResult___fst_exp__h378371 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h378368 ;
|
|
assign _theResult___fst_exp__h397050 =
|
|
_theResult____h388941[56] ?
|
|
8'd2 :
|
|
_theResult___fst_exp__h397124 ;
|
|
assign _theResult___fst_exp__h397115 =
|
|
8'd0 -
|
|
{ 2'd0,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5631 } ;
|
|
assign _theResult___fst_exp__h397121 =
|
|
(!_theResult____h388941[56] && !_theResult____h388941[55] &&
|
|
!_theResult____h388941[54] &&
|
|
!_theResult____h388941[53] &&
|
|
!_theResult____h388941[52] &&
|
|
!_theResult____h388941[51] &&
|
|
!_theResult____h388941[50] &&
|
|
!_theResult____h388941[49] &&
|
|
!_theResult____h388941[48] &&
|
|
!_theResult____h388941[47] &&
|
|
!_theResult____h388941[46] &&
|
|
!_theResult____h388941[45] &&
|
|
!_theResult____h388941[44] &&
|
|
!_theResult____h388941[43] &&
|
|
!_theResult____h388941[42] &&
|
|
!_theResult____h388941[41] &&
|
|
!_theResult____h388941[40] &&
|
|
!_theResult____h388941[39] &&
|
|
!_theResult____h388941[38] &&
|
|
!_theResult____h388941[37] &&
|
|
!_theResult____h388941[36] &&
|
|
!_theResult____h388941[35] &&
|
|
!_theResult____h388941[34] &&
|
|
!_theResult____h388941[33] &&
|
|
!_theResult____h388941[32] &&
|
|
!_theResult____h388941[31] &&
|
|
!_theResult____h388941[30] &&
|
|
!_theResult____h388941[29] &&
|
|
!_theResult____h388941[28] &&
|
|
!_theResult____h388941[27] &&
|
|
!_theResult____h388941[26] &&
|
|
!_theResult____h388941[25] &&
|
|
!_theResult____h388941[24] &&
|
|
!_theResult____h388941[23] &&
|
|
!_theResult____h388941[22] &&
|
|
!_theResult____h388941[21] &&
|
|
!_theResult____h388941[20] &&
|
|
!_theResult____h388941[19] &&
|
|
!_theResult____h388941[18] &&
|
|
!_theResult____h388941[17] &&
|
|
!_theResult____h388941[16] &&
|
|
!_theResult____h388941[15] &&
|
|
!_theResult____h388941[14] &&
|
|
!_theResult____h388941[13] &&
|
|
!_theResult____h388941[12] &&
|
|
!_theResult____h388941[11] &&
|
|
!_theResult____h388941[10] &&
|
|
!_theResult____h388941[9] &&
|
|
!_theResult____h388941[8] &&
|
|
!_theResult____h388941[7] &&
|
|
!_theResult____h388941[6] &&
|
|
!_theResult____h388941[5] &&
|
|
!_theResult____h388941[4] &&
|
|
!_theResult____h388941[3] &&
|
|
!_theResult____h388941[2] &&
|
|
!_theResult____h388941[1] &&
|
|
!_theResult____h388941[0] ||
|
|
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5633) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h397115 ;
|
|
assign _theResult___fst_exp__h397124 =
|
|
(!_theResult____h388941[56] && _theResult____h388941[55]) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h397121 ;
|
|
assign _theResult___fst_exp__h397647 =
|
|
(_theResult___fst_exp__h397050 == 8'd255) ?
|
|
_theResult___fst_exp__h397050 :
|
|
_theResult___fst_exp__h397644 ;
|
|
assign _theResult___fst_exp__h405697 =
|
|
8'd129 -
|
|
{ 2'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5862 } ;
|
|
assign _theResult___fst_exp__h405703 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5807 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5864) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h405697 ;
|
|
assign _theResult___fst_exp__h405706 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___fst_exp__h405703 :
|
|
8'd129 ;
|
|
assign _theResult___fst_exp__h406229 =
|
|
(_theResult___fst_exp__h405706 == 8'd255) ?
|
|
_theResult___fst_exp__h405706 :
|
|
_theResult___fst_exp__h406226 ;
|
|
assign _theResult___fst_exp__h414816 =
|
|
_theResult____h406578[56] ?
|
|
8'd2 :
|
|
_theResult___fst_exp__h414890 ;
|
|
assign _theResult___fst_exp__h414881 =
|
|
8'd0 -
|
|
{ 2'd0,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6182 } ;
|
|
assign _theResult___fst_exp__h414887 =
|
|
(!_theResult____h406578[56] && !_theResult____h406578[55] &&
|
|
!_theResult____h406578[54] &&
|
|
!_theResult____h406578[53] &&
|
|
!_theResult____h406578[52] &&
|
|
!_theResult____h406578[51] &&
|
|
!_theResult____h406578[50] &&
|
|
!_theResult____h406578[49] &&
|
|
!_theResult____h406578[48] &&
|
|
!_theResult____h406578[47] &&
|
|
!_theResult____h406578[46] &&
|
|
!_theResult____h406578[45] &&
|
|
!_theResult____h406578[44] &&
|
|
!_theResult____h406578[43] &&
|
|
!_theResult____h406578[42] &&
|
|
!_theResult____h406578[41] &&
|
|
!_theResult____h406578[40] &&
|
|
!_theResult____h406578[39] &&
|
|
!_theResult____h406578[38] &&
|
|
!_theResult____h406578[37] &&
|
|
!_theResult____h406578[36] &&
|
|
!_theResult____h406578[35] &&
|
|
!_theResult____h406578[34] &&
|
|
!_theResult____h406578[33] &&
|
|
!_theResult____h406578[32] &&
|
|
!_theResult____h406578[31] &&
|
|
!_theResult____h406578[30] &&
|
|
!_theResult____h406578[29] &&
|
|
!_theResult____h406578[28] &&
|
|
!_theResult____h406578[27] &&
|
|
!_theResult____h406578[26] &&
|
|
!_theResult____h406578[25] &&
|
|
!_theResult____h406578[24] &&
|
|
!_theResult____h406578[23] &&
|
|
!_theResult____h406578[22] &&
|
|
!_theResult____h406578[21] &&
|
|
!_theResult____h406578[20] &&
|
|
!_theResult____h406578[19] &&
|
|
!_theResult____h406578[18] &&
|
|
!_theResult____h406578[17] &&
|
|
!_theResult____h406578[16] &&
|
|
!_theResult____h406578[15] &&
|
|
!_theResult____h406578[14] &&
|
|
!_theResult____h406578[13] &&
|
|
!_theResult____h406578[12] &&
|
|
!_theResult____h406578[11] &&
|
|
!_theResult____h406578[10] &&
|
|
!_theResult____h406578[9] &&
|
|
!_theResult____h406578[8] &&
|
|
!_theResult____h406578[7] &&
|
|
!_theResult____h406578[6] &&
|
|
!_theResult____h406578[5] &&
|
|
!_theResult____h406578[4] &&
|
|
!_theResult____h406578[3] &&
|
|
!_theResult____h406578[2] &&
|
|
!_theResult____h406578[1] &&
|
|
!_theResult____h406578[0] ||
|
|
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6184) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h414881 ;
|
|
assign _theResult___fst_exp__h414890 =
|
|
(!_theResult____h406578[56] && _theResult____h406578[55]) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h414887 ;
|
|
assign _theResult___fst_exp__h415413 =
|
|
(_theResult___fst_exp__h414816 == 8'd255) ?
|
|
_theResult___fst_exp__h414816 :
|
|
_theResult___fst_exp__h415410 ;
|
|
assign _theResult___fst_exp__h423453 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ==
|
|
8'd0) ?
|
|
8'd1 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] ;
|
|
assign _theResult___fst_exp__h423492 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q64[7:0] -
|
|
{ 2'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5862 } ;
|
|
assign _theResult___fst_exp__h423498 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5807 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6257) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h423492 ;
|
|
assign _theResult___fst_exp__h423501 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___fst_exp__h423498 :
|
|
_theResult___fst_exp__h423453 ;
|
|
assign _theResult___fst_exp__h424049 =
|
|
(_theResult___fst_exp__h423501 == 8'd255) ?
|
|
_theResult___fst_exp__h423501 :
|
|
_theResult___fst_exp__h424046 ;
|
|
assign _theResult___fst_exp__h424058 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 ?
|
|
_theResult___snd_fst_exp__h406232 :
|
|
_theResult___fst_exp__h388923) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 ?
|
|
_theResult___snd_fst_exp__h424052 :
|
|
_theResult___fst_exp__h388923) ;
|
|
assign _theResult___fst_exp__h424061 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h424058 ;
|
|
assign _theResult___fst_exp__h442738 =
|
|
_theResult____h434629[56] ?
|
|
8'd2 :
|
|
_theResult___fst_exp__h442812 ;
|
|
assign _theResult___fst_exp__h442803 =
|
|
8'd0 -
|
|
{ 2'd0,
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7023 } ;
|
|
assign _theResult___fst_exp__h442809 =
|
|
(!_theResult____h434629[56] && !_theResult____h434629[55] &&
|
|
!_theResult____h434629[54] &&
|
|
!_theResult____h434629[53] &&
|
|
!_theResult____h434629[52] &&
|
|
!_theResult____h434629[51] &&
|
|
!_theResult____h434629[50] &&
|
|
!_theResult____h434629[49] &&
|
|
!_theResult____h434629[48] &&
|
|
!_theResult____h434629[47] &&
|
|
!_theResult____h434629[46] &&
|
|
!_theResult____h434629[45] &&
|
|
!_theResult____h434629[44] &&
|
|
!_theResult____h434629[43] &&
|
|
!_theResult____h434629[42] &&
|
|
!_theResult____h434629[41] &&
|
|
!_theResult____h434629[40] &&
|
|
!_theResult____h434629[39] &&
|
|
!_theResult____h434629[38] &&
|
|
!_theResult____h434629[37] &&
|
|
!_theResult____h434629[36] &&
|
|
!_theResult____h434629[35] &&
|
|
!_theResult____h434629[34] &&
|
|
!_theResult____h434629[33] &&
|
|
!_theResult____h434629[32] &&
|
|
!_theResult____h434629[31] &&
|
|
!_theResult____h434629[30] &&
|
|
!_theResult____h434629[29] &&
|
|
!_theResult____h434629[28] &&
|
|
!_theResult____h434629[27] &&
|
|
!_theResult____h434629[26] &&
|
|
!_theResult____h434629[25] &&
|
|
!_theResult____h434629[24] &&
|
|
!_theResult____h434629[23] &&
|
|
!_theResult____h434629[22] &&
|
|
!_theResult____h434629[21] &&
|
|
!_theResult____h434629[20] &&
|
|
!_theResult____h434629[19] &&
|
|
!_theResult____h434629[18] &&
|
|
!_theResult____h434629[17] &&
|
|
!_theResult____h434629[16] &&
|
|
!_theResult____h434629[15] &&
|
|
!_theResult____h434629[14] &&
|
|
!_theResult____h434629[13] &&
|
|
!_theResult____h434629[12] &&
|
|
!_theResult____h434629[11] &&
|
|
!_theResult____h434629[10] &&
|
|
!_theResult____h434629[9] &&
|
|
!_theResult____h434629[8] &&
|
|
!_theResult____h434629[7] &&
|
|
!_theResult____h434629[6] &&
|
|
!_theResult____h434629[5] &&
|
|
!_theResult____h434629[4] &&
|
|
!_theResult____h434629[3] &&
|
|
!_theResult____h434629[2] &&
|
|
!_theResult____h434629[1] &&
|
|
!_theResult____h434629[0] ||
|
|
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7025) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h442803 ;
|
|
assign _theResult___fst_exp__h442812 =
|
|
(!_theResult____h434629[56] && _theResult____h434629[55]) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h442809 ;
|
|
assign _theResult___fst_exp__h443335 =
|
|
(_theResult___fst_exp__h442738 == 8'd255) ?
|
|
_theResult___fst_exp__h442738 :
|
|
_theResult___fst_exp__h443332 ;
|
|
assign _theResult___fst_exp__h451385 =
|
|
8'd129 -
|
|
{ 2'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7254 } ;
|
|
assign _theResult___fst_exp__h451391 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7199 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7256) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h451385 ;
|
|
assign _theResult___fst_exp__h451394 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___fst_exp__h451391 :
|
|
8'd129 ;
|
|
assign _theResult___fst_exp__h451917 =
|
|
(_theResult___fst_exp__h451394 == 8'd255) ?
|
|
_theResult___fst_exp__h451394 :
|
|
_theResult___fst_exp__h451914 ;
|
|
assign _theResult___fst_exp__h460504 =
|
|
_theResult____h452266[56] ?
|
|
8'd2 :
|
|
_theResult___fst_exp__h460578 ;
|
|
assign _theResult___fst_exp__h460569 =
|
|
8'd0 -
|
|
{ 2'd0,
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7574 } ;
|
|
assign _theResult___fst_exp__h460575 =
|
|
(!_theResult____h452266[56] && !_theResult____h452266[55] &&
|
|
!_theResult____h452266[54] &&
|
|
!_theResult____h452266[53] &&
|
|
!_theResult____h452266[52] &&
|
|
!_theResult____h452266[51] &&
|
|
!_theResult____h452266[50] &&
|
|
!_theResult____h452266[49] &&
|
|
!_theResult____h452266[48] &&
|
|
!_theResult____h452266[47] &&
|
|
!_theResult____h452266[46] &&
|
|
!_theResult____h452266[45] &&
|
|
!_theResult____h452266[44] &&
|
|
!_theResult____h452266[43] &&
|
|
!_theResult____h452266[42] &&
|
|
!_theResult____h452266[41] &&
|
|
!_theResult____h452266[40] &&
|
|
!_theResult____h452266[39] &&
|
|
!_theResult____h452266[38] &&
|
|
!_theResult____h452266[37] &&
|
|
!_theResult____h452266[36] &&
|
|
!_theResult____h452266[35] &&
|
|
!_theResult____h452266[34] &&
|
|
!_theResult____h452266[33] &&
|
|
!_theResult____h452266[32] &&
|
|
!_theResult____h452266[31] &&
|
|
!_theResult____h452266[30] &&
|
|
!_theResult____h452266[29] &&
|
|
!_theResult____h452266[28] &&
|
|
!_theResult____h452266[27] &&
|
|
!_theResult____h452266[26] &&
|
|
!_theResult____h452266[25] &&
|
|
!_theResult____h452266[24] &&
|
|
!_theResult____h452266[23] &&
|
|
!_theResult____h452266[22] &&
|
|
!_theResult____h452266[21] &&
|
|
!_theResult____h452266[20] &&
|
|
!_theResult____h452266[19] &&
|
|
!_theResult____h452266[18] &&
|
|
!_theResult____h452266[17] &&
|
|
!_theResult____h452266[16] &&
|
|
!_theResult____h452266[15] &&
|
|
!_theResult____h452266[14] &&
|
|
!_theResult____h452266[13] &&
|
|
!_theResult____h452266[12] &&
|
|
!_theResult____h452266[11] &&
|
|
!_theResult____h452266[10] &&
|
|
!_theResult____h452266[9] &&
|
|
!_theResult____h452266[8] &&
|
|
!_theResult____h452266[7] &&
|
|
!_theResult____h452266[6] &&
|
|
!_theResult____h452266[5] &&
|
|
!_theResult____h452266[4] &&
|
|
!_theResult____h452266[3] &&
|
|
!_theResult____h452266[2] &&
|
|
!_theResult____h452266[1] &&
|
|
!_theResult____h452266[0] ||
|
|
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7576) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h460569 ;
|
|
assign _theResult___fst_exp__h460578 =
|
|
(!_theResult____h452266[56] && _theResult____h452266[55]) ?
|
|
8'd1 :
|
|
_theResult___fst_exp__h460575 ;
|
|
assign _theResult___fst_exp__h461101 =
|
|
(_theResult___fst_exp__h460504 == 8'd255) ?
|
|
_theResult___fst_exp__h460504 :
|
|
_theResult___fst_exp__h461098 ;
|
|
assign _theResult___fst_exp__h469141 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ==
|
|
8'd0) ?
|
|
8'd1 :
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] ;
|
|
assign _theResult___fst_exp__h469180 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q99[7:0] -
|
|
{ 2'd0,
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7254 } ;
|
|
assign _theResult___fst_exp__h469186 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7199 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7649) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h469180 ;
|
|
assign _theResult___fst_exp__h469189 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___fst_exp__h469186 :
|
|
_theResult___fst_exp__h469141 ;
|
|
assign _theResult___fst_exp__h469737 =
|
|
(_theResult___fst_exp__h469189 == 8'd255) ?
|
|
_theResult___fst_exp__h469189 :
|
|
_theResult___fst_exp__h469734 ;
|
|
assign _theResult___fst_exp__h469746 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 ?
|
|
_theResult___snd_fst_exp__h451920 :
|
|
_theResult___fst_exp__h434611) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 ?
|
|
_theResult___snd_fst_exp__h469740 :
|
|
_theResult___fst_exp__h434611) ;
|
|
assign _theResult___fst_exp__h469749 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) ?
|
|
8'd0 :
|
|
_theResult___fst_exp__h469746 ;
|
|
assign _theResult___fst_exp__h483550 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
|
|
11'd2047 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 ;
|
|
assign _theResult___fst_exp__h498614 =
|
|
11'd897 -
|
|
{ 5'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8571 } ;
|
|
assign _theResult___fst_exp__h498620 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8544 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8573) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h498614 ;
|
|
assign _theResult___fst_exp__h498623 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
_theResult___fst_exp__h498620 :
|
|
11'd897 ;
|
|
assign _theResult___fst_exp__h499378 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q136 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9007 ;
|
|
assign _theResult___fst_exp__h499381 =
|
|
(_theResult___fst_exp__h498623 == 11'd2047) ?
|
|
_theResult___fst_exp__h498623 :
|
|
_theResult___fst_exp__h499378 ;
|
|
assign _theResult___fst_exp__h508200 =
|
|
_theResult____h499964[56] ?
|
|
11'd2 :
|
|
_theResult___fst_exp__h508274 ;
|
|
assign _theResult___fst_exp__h508265 =
|
|
11'd0 -
|
|
{ 5'd0,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8883 } ;
|
|
assign _theResult___fst_exp__h508271 =
|
|
(!_theResult____h499964[56] && !_theResult____h499964[55] &&
|
|
!_theResult____h499964[54] &&
|
|
!_theResult____h499964[53] &&
|
|
!_theResult____h499964[52] &&
|
|
!_theResult____h499964[51] &&
|
|
!_theResult____h499964[50] &&
|
|
!_theResult____h499964[49] &&
|
|
!_theResult____h499964[48] &&
|
|
!_theResult____h499964[47] &&
|
|
!_theResult____h499964[46] &&
|
|
!_theResult____h499964[45] &&
|
|
!_theResult____h499964[44] &&
|
|
!_theResult____h499964[43] &&
|
|
!_theResult____h499964[42] &&
|
|
!_theResult____h499964[41] &&
|
|
!_theResult____h499964[40] &&
|
|
!_theResult____h499964[39] &&
|
|
!_theResult____h499964[38] &&
|
|
!_theResult____h499964[37] &&
|
|
!_theResult____h499964[36] &&
|
|
!_theResult____h499964[35] &&
|
|
!_theResult____h499964[34] &&
|
|
!_theResult____h499964[33] &&
|
|
!_theResult____h499964[32] &&
|
|
!_theResult____h499964[31] &&
|
|
!_theResult____h499964[30] &&
|
|
!_theResult____h499964[29] &&
|
|
!_theResult____h499964[28] &&
|
|
!_theResult____h499964[27] &&
|
|
!_theResult____h499964[26] &&
|
|
!_theResult____h499964[25] &&
|
|
!_theResult____h499964[24] &&
|
|
!_theResult____h499964[23] &&
|
|
!_theResult____h499964[22] &&
|
|
!_theResult____h499964[21] &&
|
|
!_theResult____h499964[20] &&
|
|
!_theResult____h499964[19] &&
|
|
!_theResult____h499964[18] &&
|
|
!_theResult____h499964[17] &&
|
|
!_theResult____h499964[16] &&
|
|
!_theResult____h499964[15] &&
|
|
!_theResult____h499964[14] &&
|
|
!_theResult____h499964[13] &&
|
|
!_theResult____h499964[12] &&
|
|
!_theResult____h499964[11] &&
|
|
!_theResult____h499964[10] &&
|
|
!_theResult____h499964[9] &&
|
|
!_theResult____h499964[8] &&
|
|
!_theResult____h499964[7] &&
|
|
!_theResult____h499964[6] &&
|
|
!_theResult____h499964[5] &&
|
|
!_theResult____h499964[4] &&
|
|
!_theResult____h499964[3] &&
|
|
!_theResult____h499964[2] &&
|
|
!_theResult____h499964[1] &&
|
|
!_theResult____h499964[0] ||
|
|
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d8885) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h508265 ;
|
|
assign _theResult___fst_exp__h508274 =
|
|
(!_theResult____h499964[56] && _theResult____h499964[55]) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h508271 ;
|
|
assign _theResult___fst_exp__h509029 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q204 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9050 ;
|
|
assign _theResult___fst_exp__h509032 =
|
|
(_theResult___fst_exp__h508200 == 11'd2047) ?
|
|
_theResult___fst_exp__h508200 :
|
|
_theResult___fst_exp__h509029 ;
|
|
assign _theResult___fst_exp__h516985 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ==
|
|
11'd0) ?
|
|
11'd1 :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] ;
|
|
assign _theResult___fst_exp__h517024 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q129[10:0] -
|
|
{ 5'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8571 } ;
|
|
assign _theResult___fst_exp__h517030 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8544 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d8935) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h517024 ;
|
|
assign _theResult___fst_exp__h517033 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
_theResult___fst_exp__h517030 :
|
|
_theResult___fst_exp__h516985 ;
|
|
assign _theResult___fst_exp__h517813 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q206 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9081 ;
|
|
assign _theResult___fst_exp__h517816 =
|
|
(_theResult___fst_exp__h517033 == 11'd2047) ?
|
|
_theResult___fst_exp__h517033 :
|
|
_theResult___fst_exp__h517813 ;
|
|
assign _theResult___fst_exp__h517825 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 ?
|
|
_theResult___snd_fst_exp__h499384 :
|
|
_theResult___fst_exp__h483550) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 ?
|
|
_theResult___snd_fst_exp__h517819 :
|
|
_theResult___fst_exp__h483550) ;
|
|
assign _theResult___fst_exp__h517828 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h517825 ;
|
|
assign _theResult___fst_exp__h522351 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
|
|
11'd2047 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 ;
|
|
assign _theResult___fst_exp__h537415 =
|
|
11'd897 -
|
|
{ 5'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10059 } ;
|
|
assign _theResult___fst_exp__h537421 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10032 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10061) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h537415 ;
|
|
assign _theResult___fst_exp__h537424 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
_theResult___fst_exp__h537421 :
|
|
11'd897 ;
|
|
assign _theResult___fst_exp__h538179 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q176 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10480 ;
|
|
assign _theResult___fst_exp__h538182 =
|
|
(_theResult___fst_exp__h537424 == 11'd2047) ?
|
|
_theResult___fst_exp__h537424 :
|
|
_theResult___fst_exp__h538179 ;
|
|
assign _theResult___fst_exp__h547001 =
|
|
_theResult____h538765[56] ?
|
|
11'd2 :
|
|
_theResult___fst_exp__h547075 ;
|
|
assign _theResult___fst_exp__h547066 =
|
|
11'd0 -
|
|
{ 5'd0,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10356 } ;
|
|
assign _theResult___fst_exp__h547072 =
|
|
(!_theResult____h538765[56] && !_theResult____h538765[55] &&
|
|
!_theResult____h538765[54] &&
|
|
!_theResult____h538765[53] &&
|
|
!_theResult____h538765[52] &&
|
|
!_theResult____h538765[51] &&
|
|
!_theResult____h538765[50] &&
|
|
!_theResult____h538765[49] &&
|
|
!_theResult____h538765[48] &&
|
|
!_theResult____h538765[47] &&
|
|
!_theResult____h538765[46] &&
|
|
!_theResult____h538765[45] &&
|
|
!_theResult____h538765[44] &&
|
|
!_theResult____h538765[43] &&
|
|
!_theResult____h538765[42] &&
|
|
!_theResult____h538765[41] &&
|
|
!_theResult____h538765[40] &&
|
|
!_theResult____h538765[39] &&
|
|
!_theResult____h538765[38] &&
|
|
!_theResult____h538765[37] &&
|
|
!_theResult____h538765[36] &&
|
|
!_theResult____h538765[35] &&
|
|
!_theResult____h538765[34] &&
|
|
!_theResult____h538765[33] &&
|
|
!_theResult____h538765[32] &&
|
|
!_theResult____h538765[31] &&
|
|
!_theResult____h538765[30] &&
|
|
!_theResult____h538765[29] &&
|
|
!_theResult____h538765[28] &&
|
|
!_theResult____h538765[27] &&
|
|
!_theResult____h538765[26] &&
|
|
!_theResult____h538765[25] &&
|
|
!_theResult____h538765[24] &&
|
|
!_theResult____h538765[23] &&
|
|
!_theResult____h538765[22] &&
|
|
!_theResult____h538765[21] &&
|
|
!_theResult____h538765[20] &&
|
|
!_theResult____h538765[19] &&
|
|
!_theResult____h538765[18] &&
|
|
!_theResult____h538765[17] &&
|
|
!_theResult____h538765[16] &&
|
|
!_theResult____h538765[15] &&
|
|
!_theResult____h538765[14] &&
|
|
!_theResult____h538765[13] &&
|
|
!_theResult____h538765[12] &&
|
|
!_theResult____h538765[11] &&
|
|
!_theResult____h538765[10] &&
|
|
!_theResult____h538765[9] &&
|
|
!_theResult____h538765[8] &&
|
|
!_theResult____h538765[7] &&
|
|
!_theResult____h538765[6] &&
|
|
!_theResult____h538765[5] &&
|
|
!_theResult____h538765[4] &&
|
|
!_theResult____h538765[3] &&
|
|
!_theResult____h538765[2] &&
|
|
!_theResult____h538765[1] &&
|
|
!_theResult____h538765[0] ||
|
|
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d10358) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h547066 ;
|
|
assign _theResult___fst_exp__h547075 =
|
|
(!_theResult____h538765[56] && _theResult____h538765[55]) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h547072 ;
|
|
assign _theResult___fst_exp__h547830 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q178 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10518 ;
|
|
assign _theResult___fst_exp__h547833 =
|
|
(_theResult___fst_exp__h547001 == 11'd2047) ?
|
|
_theResult___fst_exp__h547001 :
|
|
_theResult___fst_exp__h547830 ;
|
|
assign _theResult___fst_exp__h555786 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ==
|
|
11'd0) ?
|
|
11'd1 :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] ;
|
|
assign _theResult___fst_exp__h555825 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q169[10:0] -
|
|
{ 5'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10059 } ;
|
|
assign _theResult___fst_exp__h555831 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10032 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10408) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h555825 ;
|
|
assign _theResult___fst_exp__h555834 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
_theResult___fst_exp__h555831 :
|
|
_theResult___fst_exp__h555786 ;
|
|
assign _theResult___fst_exp__h556614 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q182 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10549 ;
|
|
assign _theResult___fst_exp__h556617 =
|
|
(_theResult___fst_exp__h555834 == 11'd2047) ?
|
|
_theResult___fst_exp__h555834 :
|
|
_theResult___fst_exp__h556614 ;
|
|
assign _theResult___fst_exp__h556626 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 ?
|
|
_theResult___snd_fst_exp__h538185 :
|
|
_theResult___fst_exp__h522351) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 ?
|
|
_theResult___snd_fst_exp__h556620 :
|
|
_theResult___fst_exp__h522351) ;
|
|
assign _theResult___fst_exp__h556629 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h556626 ;
|
|
assign _theResult___fst_exp__h561552 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
|
|
11'd2047 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 ;
|
|
assign _theResult___fst_exp__h576616 =
|
|
11'd897 -
|
|
{ 5'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9296 } ;
|
|
assign _theResult___fst_exp__h576622 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9269 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9298) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h576616 ;
|
|
assign _theResult___fst_exp__h576625 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
_theResult___fst_exp__h576622 :
|
|
11'd897 ;
|
|
assign _theResult___fst_exp__h577380 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q153 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9717 ;
|
|
assign _theResult___fst_exp__h577383 =
|
|
(_theResult___fst_exp__h576625 == 11'd2047) ?
|
|
_theResult___fst_exp__h576625 :
|
|
_theResult___fst_exp__h577380 ;
|
|
assign _theResult___fst_exp__h586202 =
|
|
_theResult____h577966[56] ?
|
|
11'd2 :
|
|
_theResult___fst_exp__h586276 ;
|
|
assign _theResult___fst_exp__h586267 =
|
|
11'd0 -
|
|
{ 5'd0,
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9593 } ;
|
|
assign _theResult___fst_exp__h586273 =
|
|
(!_theResult____h577966[56] && !_theResult____h577966[55] &&
|
|
!_theResult____h577966[54] &&
|
|
!_theResult____h577966[53] &&
|
|
!_theResult____h577966[52] &&
|
|
!_theResult____h577966[51] &&
|
|
!_theResult____h577966[50] &&
|
|
!_theResult____h577966[49] &&
|
|
!_theResult____h577966[48] &&
|
|
!_theResult____h577966[47] &&
|
|
!_theResult____h577966[46] &&
|
|
!_theResult____h577966[45] &&
|
|
!_theResult____h577966[44] &&
|
|
!_theResult____h577966[43] &&
|
|
!_theResult____h577966[42] &&
|
|
!_theResult____h577966[41] &&
|
|
!_theResult____h577966[40] &&
|
|
!_theResult____h577966[39] &&
|
|
!_theResult____h577966[38] &&
|
|
!_theResult____h577966[37] &&
|
|
!_theResult____h577966[36] &&
|
|
!_theResult____h577966[35] &&
|
|
!_theResult____h577966[34] &&
|
|
!_theResult____h577966[33] &&
|
|
!_theResult____h577966[32] &&
|
|
!_theResult____h577966[31] &&
|
|
!_theResult____h577966[30] &&
|
|
!_theResult____h577966[29] &&
|
|
!_theResult____h577966[28] &&
|
|
!_theResult____h577966[27] &&
|
|
!_theResult____h577966[26] &&
|
|
!_theResult____h577966[25] &&
|
|
!_theResult____h577966[24] &&
|
|
!_theResult____h577966[23] &&
|
|
!_theResult____h577966[22] &&
|
|
!_theResult____h577966[21] &&
|
|
!_theResult____h577966[20] &&
|
|
!_theResult____h577966[19] &&
|
|
!_theResult____h577966[18] &&
|
|
!_theResult____h577966[17] &&
|
|
!_theResult____h577966[16] &&
|
|
!_theResult____h577966[15] &&
|
|
!_theResult____h577966[14] &&
|
|
!_theResult____h577966[13] &&
|
|
!_theResult____h577966[12] &&
|
|
!_theResult____h577966[11] &&
|
|
!_theResult____h577966[10] &&
|
|
!_theResult____h577966[9] &&
|
|
!_theResult____h577966[8] &&
|
|
!_theResult____h577966[7] &&
|
|
!_theResult____h577966[6] &&
|
|
!_theResult____h577966[5] &&
|
|
!_theResult____h577966[4] &&
|
|
!_theResult____h577966[3] &&
|
|
!_theResult____h577966[2] &&
|
|
!_theResult____h577966[1] &&
|
|
!_theResult____h577966[0] ||
|
|
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulD_ETC___d9595) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h586267 ;
|
|
assign _theResult___fst_exp__h586276 =
|
|
(!_theResult____h577966[56] && _theResult____h577966[55]) ?
|
|
11'd1 :
|
|
_theResult___fst_exp__h586273 ;
|
|
assign _theResult___fst_exp__h587031 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q180 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9755 ;
|
|
assign _theResult___fst_exp__h587034 =
|
|
(_theResult___fst_exp__h586202 == 11'd2047) ?
|
|
_theResult___fst_exp__h586202 :
|
|
_theResult___fst_exp__h587031 ;
|
|
assign _theResult___fst_exp__h594987 =
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ==
|
|
11'd0) ?
|
|
11'd1 :
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] ;
|
|
assign _theResult___fst_exp__h595026 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC__q146[10:0] -
|
|
{ 5'd0,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9296 } ;
|
|
assign _theResult___fst_exp__h595032 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9269 ||
|
|
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9645) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h595026 ;
|
|
assign _theResult___fst_exp__h595035 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
_theResult___fst_exp__h595032 :
|
|
_theResult___fst_exp__h594987 ;
|
|
assign _theResult___fst_exp__h595815 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q184 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9786 ;
|
|
assign _theResult___fst_exp__h595818 =
|
|
(_theResult___fst_exp__h595035 == 11'd2047) ?
|
|
_theResult___fst_exp__h595035 :
|
|
_theResult___fst_exp__h595815 ;
|
|
assign _theResult___fst_exp__h595827 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 ?
|
|
_theResult___snd_fst_exp__h577386 :
|
|
_theResult___fst_exp__h561552) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 ?
|
|
_theResult___snd_fst_exp__h595821 :
|
|
_theResult___fst_exp__h561552) ;
|
|
assign _theResult___fst_exp__h595830 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h595827 ;
|
|
assign _theResult___fst_sfd__h351958 =
|
|
(_theResult___fst_exp__h351360 == 8'd255) ?
|
|
sfdin__h351354[56:34] :
|
|
_theResult___fst_sfd__h351955 ;
|
|
assign _theResult___fst_sfd__h360540 =
|
|
(_theResult___fst_exp__h360016 == 8'd255) ?
|
|
_theResult___snd__h359967[56:34] :
|
|
_theResult___fst_sfd__h360537 ;
|
|
assign _theResult___fst_sfd__h369724 =
|
|
(_theResult___fst_exp__h369126 == 8'd255) ?
|
|
sfdin__h369120[56:34] :
|
|
_theResult___fst_sfd__h369721 ;
|
|
assign _theResult___fst_sfd__h378360 =
|
|
(_theResult___fst_exp__h377811 == 8'd255) ?
|
|
_theResult___snd__h377757[56:34] :
|
|
_theResult___fst_sfd__h378357 ;
|
|
assign _theResult___fst_sfd__h378369 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4004 ?
|
|
_theResult___snd_fst_sfd__h360543 :
|
|
_theResult___fst_sfd__h343232) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4544 ?
|
|
_theResult___snd_fst_sfd__h378363 :
|
|
_theResult___fst_sfd__h343232) ;
|
|
assign _theResult___fst_sfd__h378375 =
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) ?
|
|
23'd0 :
|
|
_theResult___fst_sfd__h378369 ;
|
|
assign _theResult___fst_sfd__h397648 =
|
|
(_theResult___fst_exp__h397050 == 8'd255) ?
|
|
sfdin__h397044[56:34] :
|
|
_theResult___fst_sfd__h397645 ;
|
|
assign _theResult___fst_sfd__h406230 =
|
|
(_theResult___fst_exp__h405706 == 8'd255) ?
|
|
_theResult___snd__h405657[56:34] :
|
|
_theResult___fst_sfd__h406227 ;
|
|
assign _theResult___fst_sfd__h415414 =
|
|
(_theResult___fst_exp__h414816 == 8'd255) ?
|
|
sfdin__h414810[56:34] :
|
|
_theResult___fst_sfd__h415411 ;
|
|
assign _theResult___fst_sfd__h424050 =
|
|
(_theResult___fst_exp__h423501 == 8'd255) ?
|
|
_theResult___snd__h423447[56:34] :
|
|
_theResult___fst_sfd__h424047 ;
|
|
assign _theResult___fst_sfd__h424059 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5396 ?
|
|
_theResult___snd_fst_sfd__h406233 :
|
|
_theResult___fst_sfd__h388924) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5936 ?
|
|
_theResult___snd_fst_sfd__h424053 :
|
|
_theResult___fst_sfd__h388924) ;
|
|
assign _theResult___fst_sfd__h424065 =
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) ?
|
|
23'd0 :
|
|
_theResult___fst_sfd__h424059 ;
|
|
assign _theResult___fst_sfd__h443336 =
|
|
(_theResult___fst_exp__h442738 == 8'd255) ?
|
|
sfdin__h442732[56:34] :
|
|
_theResult___fst_sfd__h443333 ;
|
|
assign _theResult___fst_sfd__h451918 =
|
|
(_theResult___fst_exp__h451394 == 8'd255) ?
|
|
_theResult___snd__h451345[56:34] :
|
|
_theResult___fst_sfd__h451915 ;
|
|
assign _theResult___fst_sfd__h461102 =
|
|
(_theResult___fst_exp__h460504 == 8'd255) ?
|
|
sfdin__h460498[56:34] :
|
|
_theResult___fst_sfd__h461099 ;
|
|
assign _theResult___fst_sfd__h469738 =
|
|
(_theResult___fst_exp__h469189 == 8'd255) ?
|
|
_theResult___snd__h469135[56:34] :
|
|
_theResult___fst_sfd__h469735 ;
|
|
assign _theResult___fst_sfd__h469747 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6788 ?
|
|
_theResult___snd_fst_sfd__h451921 :
|
|
_theResult___fst_sfd__h434612) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7328 ?
|
|
_theResult___snd_fst_sfd__h469741 :
|
|
_theResult___fst_sfd__h434612) ;
|
|
assign _theResult___fst_sfd__h469753 =
|
|
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) ?
|
|
23'd0 :
|
|
_theResult___fst_sfd__h469747 ;
|
|
assign _theResult___fst_sfd__h483551 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
|
|
52'd0 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 ;
|
|
assign _theResult___fst_sfd__h499379 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q208 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9107 ;
|
|
assign _theResult___fst_sfd__h499382 =
|
|
(_theResult___fst_exp__h498623 == 11'd2047) ?
|
|
_theResult___snd__h498574[56:5] :
|
|
_theResult___fst_sfd__h499379 ;
|
|
assign _theResult___fst_sfd__h509030 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q210 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9134 ;
|
|
assign _theResult___fst_sfd__h509033 =
|
|
(_theResult___fst_exp__h508200 == 11'd2047) ?
|
|
sfdin__h508194[56:5] :
|
|
_theResult___fst_sfd__h509030 ;
|
|
assign _theResult___fst_sfd__h517814 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q212 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9153 ;
|
|
assign _theResult___fst_sfd__h517817 =
|
|
(_theResult___fst_exp__h517033 == 11'd2047) ?
|
|
_theResult___snd__h516979[56:5] :
|
|
_theResult___fst_sfd__h517814 ;
|
|
assign _theResult___fst_sfd__h517826 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8498 ?
|
|
_theResult___snd_fst_sfd__h499385 :
|
|
_theResult___fst_sfd__h483551) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8635 ?
|
|
_theResult___snd_fst_sfd__h517820 :
|
|
_theResult___fst_sfd__h483551) ;
|
|
assign _theResult___fst_sfd__h517832 =
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
|
|
52'd0 :
|
|
_theResult___fst_sfd__h517826 ;
|
|
assign _theResult___fst_sfd__h522352 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
|
|
52'd0 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 ;
|
|
assign _theResult___fst_sfd__h538180 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q198 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10575 ;
|
|
assign _theResult___fst_sfd__h538183 =
|
|
(_theResult___fst_exp__h537424 == 11'd2047) ?
|
|
_theResult___snd__h537375[56:5] :
|
|
_theResult___fst_sfd__h538180 ;
|
|
assign _theResult___fst_sfd__h547831 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q202 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10601 ;
|
|
assign _theResult___fst_sfd__h547834 =
|
|
(_theResult___fst_exp__h547001 == 11'd2047) ?
|
|
sfdin__h546995[56:5] :
|
|
_theResult___fst_sfd__h547831 ;
|
|
assign _theResult___fst_sfd__h556615 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q200 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10620 ;
|
|
assign _theResult___fst_sfd__h556618 =
|
|
(_theResult___fst_exp__h555834 == 11'd2047) ?
|
|
_theResult___snd__h555780[56:5] :
|
|
_theResult___fst_sfd__h556615 ;
|
|
assign _theResult___fst_sfd__h556627 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9986 ?
|
|
_theResult___snd_fst_sfd__h538186 :
|
|
_theResult___fst_sfd__h522352) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10108 ?
|
|
_theResult___snd_fst_sfd__h556621 :
|
|
_theResult___fst_sfd__h522352) ;
|
|
assign _theResult___fst_sfd__h556633 =
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
|
|
52'd0 :
|
|
_theResult___fst_sfd__h556627 ;
|
|
assign _theResult___fst_sfd__h561553 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
|
|
52'd0 :
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 ;
|
|
assign _theResult___fst_sfd__h577381 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q214 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9812 ;
|
|
assign _theResult___fst_sfd__h577384 =
|
|
(_theResult___fst_exp__h576625 == 11'd2047) ?
|
|
_theResult___snd__h576576[56:5] :
|
|
_theResult___fst_sfd__h577381 ;
|
|
assign _theResult___fst_sfd__h587032 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q216 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9838 ;
|
|
assign _theResult___fst_sfd__h587035 =
|
|
(_theResult___fst_exp__h586202 == 11'd2047) ?
|
|
sfdin__h586196[56:5] :
|
|
_theResult___fst_sfd__h587032 ;
|
|
assign _theResult___fst_sfd__h595816 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q218 :
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9857 ;
|
|
assign _theResult___fst_sfd__h595819 =
|
|
(_theResult___fst_exp__h595035 == 11'd2047) ?
|
|
_theResult___snd__h594981[56:5] :
|
|
_theResult___fst_sfd__h595816 ;
|
|
assign _theResult___fst_sfd__h595828 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
(_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9223 ?
|
|
_theResult___snd_fst_sfd__h577387 :
|
|
_theResult___fst_sfd__h561553) :
|
|
(SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9345 ?
|
|
_theResult___snd_fst_sfd__h595822 :
|
|
_theResult___fst_sfd__h561553) ;
|
|
assign _theResult___fst_sfd__h595834 =
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
|
|
52'd0 :
|
|
_theResult___fst_sfd__h595828 ;
|
|
assign _theResult___sfd__h351877 =
|
|
sfd__h351452[24] ?
|
|
((_theResult___fst_exp__h351360 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h351452[23:1]) :
|
|
sfd__h351452[22:0] ;
|
|
assign _theResult___sfd__h360459 =
|
|
sfd__h360034[24] ?
|
|
((_theResult___fst_exp__h360016 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h360034[23:1]) :
|
|
sfd__h360034[22:0] ;
|
|
assign _theResult___sfd__h369643 =
|
|
sfd__h369218[24] ?
|
|
((_theResult___fst_exp__h369126 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h369218[23:1]) :
|
|
sfd__h369218[22:0] ;
|
|
assign _theResult___sfd__h378279 =
|
|
sfd__h377830[24] ?
|
|
((_theResult___fst_exp__h377811 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h377830[23:1]) :
|
|
sfd__h377830[22:0] ;
|
|
assign _theResult___sfd__h378381 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) ?
|
|
_theResult___snd_fst_sfd__h335594 :
|
|
_theResult___fst_sfd__h378375 ;
|
|
assign _theResult___sfd__h397567 =
|
|
sfd__h397142[24] ?
|
|
((_theResult___fst_exp__h397050 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h397142[23:1]) :
|
|
sfd__h397142[22:0] ;
|
|
assign _theResult___sfd__h406149 =
|
|
sfd__h405724[24] ?
|
|
((_theResult___fst_exp__h405706 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h405724[23:1]) :
|
|
sfd__h405724[22:0] ;
|
|
assign _theResult___sfd__h415333 =
|
|
sfd__h414908[24] ?
|
|
((_theResult___fst_exp__h414816 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h414908[23:1]) :
|
|
sfd__h414908[22:0] ;
|
|
assign _theResult___sfd__h423969 =
|
|
sfd__h423520[24] ?
|
|
((_theResult___fst_exp__h423501 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h423520[23:1]) :
|
|
sfd__h423520[22:0] ;
|
|
assign _theResult___sfd__h424071 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) ?
|
|
_theResult___snd_fst_sfd__h381289 :
|
|
_theResult___fst_sfd__h424065 ;
|
|
assign _theResult___sfd__h443255 =
|
|
sfd__h442830[24] ?
|
|
((_theResult___fst_exp__h442738 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h442830[23:1]) :
|
|
sfd__h442830[22:0] ;
|
|
assign _theResult___sfd__h451837 =
|
|
sfd__h451412[24] ?
|
|
((_theResult___fst_exp__h451394 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h451412[23:1]) :
|
|
sfd__h451412[22:0] ;
|
|
assign _theResult___sfd__h461021 =
|
|
sfd__h460596[24] ?
|
|
((_theResult___fst_exp__h460504 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h460596[23:1]) :
|
|
sfd__h460596[22:0] ;
|
|
assign _theResult___sfd__h469657 =
|
|
sfd__h469208[24] ?
|
|
((_theResult___fst_exp__h469189 == 8'd254) ?
|
|
23'd0 :
|
|
sfd__h469208[23:1]) :
|
|
sfd__h469208[22:0] ;
|
|
assign _theResult___sfd__h469759 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) ?
|
|
_theResult___snd_fst_sfd__h426977 :
|
|
_theResult___fst_sfd__h469753 ;
|
|
assign _theResult___sfd__h499279 =
|
|
sfd__h498641[53] ?
|
|
((_theResult___fst_exp__h498623 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h498641[52:1]) :
|
|
sfd__h498641[51:0] ;
|
|
assign _theResult___sfd__h508930 =
|
|
sfd__h508292[53] ?
|
|
((_theResult___fst_exp__h508200 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h508292[52:1]) :
|
|
sfd__h508292[51:0] ;
|
|
assign _theResult___sfd__h517714 =
|
|
sfd__h517052[53] ?
|
|
((_theResult___fst_exp__h517033 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h517052[52:1]) :
|
|
sfd__h517052[51:0] ;
|
|
assign _theResult___sfd__h538080 =
|
|
sfd__h537442[53] ?
|
|
((_theResult___fst_exp__h537424 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h537442[52:1]) :
|
|
sfd__h537442[51:0] ;
|
|
assign _theResult___sfd__h547731 =
|
|
sfd__h547093[53] ?
|
|
((_theResult___fst_exp__h547001 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h547093[52:1]) :
|
|
sfd__h547093[51:0] ;
|
|
assign _theResult___sfd__h556515 =
|
|
sfd__h555853[53] ?
|
|
((_theResult___fst_exp__h555834 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h555853[52:1]) :
|
|
sfd__h555853[51:0] ;
|
|
assign _theResult___sfd__h577281 =
|
|
sfd__h576643[53] ?
|
|
((_theResult___fst_exp__h576625 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h576643[52:1]) :
|
|
sfd__h576643[51:0] ;
|
|
assign _theResult___sfd__h586932 =
|
|
sfd__h586294[53] ?
|
|
((_theResult___fst_exp__h586202 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h586294[52:1]) :
|
|
sfd__h586294[51:0] ;
|
|
assign _theResult___sfd__h595716 =
|
|
sfd__h595054[53] ?
|
|
((_theResult___fst_exp__h595035 == 11'd2046) ?
|
|
52'd0 :
|
|
sfd__h595054[52:1]) :
|
|
sfd__h595054[51:0] ;
|
|
assign _theResult___snd__h351371 = { _theResult____h343249[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h351382 =
|
|
(!_theResult____h343249[56] && _theResult____h343249[55]) ?
|
|
_theResult___snd__h351384 :
|
|
_theResult___snd__h351394 ;
|
|
assign _theResult___snd__h351384 = { _theResult____h343249[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h351394 =
|
|
(!_theResult____h343249[56] && !_theResult____h343249[55] &&
|
|
!_theResult____h343249[54] &&
|
|
!_theResult____h343249[53] &&
|
|
!_theResult____h343249[52] &&
|
|
!_theResult____h343249[51] &&
|
|
!_theResult____h343249[50] &&
|
|
!_theResult____h343249[49] &&
|
|
!_theResult____h343249[48] &&
|
|
!_theResult____h343249[47] &&
|
|
!_theResult____h343249[46] &&
|
|
!_theResult____h343249[45] &&
|
|
!_theResult____h343249[44] &&
|
|
!_theResult____h343249[43] &&
|
|
!_theResult____h343249[42] &&
|
|
!_theResult____h343249[41] &&
|
|
!_theResult____h343249[40] &&
|
|
!_theResult____h343249[39] &&
|
|
!_theResult____h343249[38] &&
|
|
!_theResult____h343249[37] &&
|
|
!_theResult____h343249[36] &&
|
|
!_theResult____h343249[35] &&
|
|
!_theResult____h343249[34] &&
|
|
!_theResult____h343249[33] &&
|
|
!_theResult____h343249[32] &&
|
|
!_theResult____h343249[31] &&
|
|
!_theResult____h343249[30] &&
|
|
!_theResult____h343249[29] &&
|
|
!_theResult____h343249[28] &&
|
|
!_theResult____h343249[27] &&
|
|
!_theResult____h343249[26] &&
|
|
!_theResult____h343249[25] &&
|
|
!_theResult____h343249[24] &&
|
|
!_theResult____h343249[23] &&
|
|
!_theResult____h343249[22] &&
|
|
!_theResult____h343249[21] &&
|
|
!_theResult____h343249[20] &&
|
|
!_theResult____h343249[19] &&
|
|
!_theResult____h343249[18] &&
|
|
!_theResult____h343249[17] &&
|
|
!_theResult____h343249[16] &&
|
|
!_theResult____h343249[15] &&
|
|
!_theResult____h343249[14] &&
|
|
!_theResult____h343249[13] &&
|
|
!_theResult____h343249[12] &&
|
|
!_theResult____h343249[11] &&
|
|
!_theResult____h343249[10] &&
|
|
!_theResult____h343249[9] &&
|
|
!_theResult____h343249[8] &&
|
|
!_theResult____h343249[7] &&
|
|
!_theResult____h343249[6] &&
|
|
!_theResult____h343249[5] &&
|
|
!_theResult____h343249[4] &&
|
|
!_theResult____h343249[3] &&
|
|
!_theResult____h343249[2] &&
|
|
!_theResult____h343249[1] &&
|
|
!_theResult____h343249[0]) ?
|
|
_theResult____h343249 :
|
|
_theResult___snd__h351400 ;
|
|
assign _theResult___snd__h351400 =
|
|
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q20[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h351423 =
|
|
_theResult____h343249 <<
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4239 ;
|
|
assign _theResult___snd__h359967 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___snd__h359976 :
|
|
_theResult___snd__h359969 ;
|
|
assign _theResult___snd__h359969 =
|
|
{ coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5],
|
|
5'd0 } ;
|
|
assign _theResult___snd__h359976 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4415) ?
|
|
sfd__h335644 :
|
|
_theResult___snd__h359982 ;
|
|
assign _theResult___snd__h359982 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q22[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h360005 =
|
|
sfd__h335644 <<
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4470 ;
|
|
assign _theResult___snd__h369137 = { _theResult____h360888[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h369148 =
|
|
(!_theResult____h360888[56] && _theResult____h360888[55]) ?
|
|
_theResult___snd__h369150 :
|
|
_theResult___snd__h369160 ;
|
|
assign _theResult___snd__h369150 = { _theResult____h360888[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h369160 =
|
|
(!_theResult____h360888[56] && !_theResult____h360888[55] &&
|
|
!_theResult____h360888[54] &&
|
|
!_theResult____h360888[53] &&
|
|
!_theResult____h360888[52] &&
|
|
!_theResult____h360888[51] &&
|
|
!_theResult____h360888[50] &&
|
|
!_theResult____h360888[49] &&
|
|
!_theResult____h360888[48] &&
|
|
!_theResult____h360888[47] &&
|
|
!_theResult____h360888[46] &&
|
|
!_theResult____h360888[45] &&
|
|
!_theResult____h360888[44] &&
|
|
!_theResult____h360888[43] &&
|
|
!_theResult____h360888[42] &&
|
|
!_theResult____h360888[41] &&
|
|
!_theResult____h360888[40] &&
|
|
!_theResult____h360888[39] &&
|
|
!_theResult____h360888[38] &&
|
|
!_theResult____h360888[37] &&
|
|
!_theResult____h360888[36] &&
|
|
!_theResult____h360888[35] &&
|
|
!_theResult____h360888[34] &&
|
|
!_theResult____h360888[33] &&
|
|
!_theResult____h360888[32] &&
|
|
!_theResult____h360888[31] &&
|
|
!_theResult____h360888[30] &&
|
|
!_theResult____h360888[29] &&
|
|
!_theResult____h360888[28] &&
|
|
!_theResult____h360888[27] &&
|
|
!_theResult____h360888[26] &&
|
|
!_theResult____h360888[25] &&
|
|
!_theResult____h360888[24] &&
|
|
!_theResult____h360888[23] &&
|
|
!_theResult____h360888[22] &&
|
|
!_theResult____h360888[21] &&
|
|
!_theResult____h360888[20] &&
|
|
!_theResult____h360888[19] &&
|
|
!_theResult____h360888[18] &&
|
|
!_theResult____h360888[17] &&
|
|
!_theResult____h360888[16] &&
|
|
!_theResult____h360888[15] &&
|
|
!_theResult____h360888[14] &&
|
|
!_theResult____h360888[13] &&
|
|
!_theResult____h360888[12] &&
|
|
!_theResult____h360888[11] &&
|
|
!_theResult____h360888[10] &&
|
|
!_theResult____h360888[9] &&
|
|
!_theResult____h360888[8] &&
|
|
!_theResult____h360888[7] &&
|
|
!_theResult____h360888[6] &&
|
|
!_theResult____h360888[5] &&
|
|
!_theResult____h360888[4] &&
|
|
!_theResult____h360888[3] &&
|
|
!_theResult____h360888[2] &&
|
|
!_theResult____h360888[1] &&
|
|
!_theResult____h360888[0]) ?
|
|
_theResult____h360888 :
|
|
_theResult___snd__h369166 ;
|
|
assign _theResult___snd__h369166 =
|
|
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q30[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h369189 =
|
|
_theResult____h360888 <<
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4790 ;
|
|
assign _theResult___snd__h377757 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___snd__h377771 :
|
|
_theResult___snd__h359969 ;
|
|
assign _theResult___snd__h377771 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4415) ?
|
|
sfd__h335644 :
|
|
_theResult___snd__h377777 ;
|
|
assign _theResult___snd__h377777 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q35[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h377795 =
|
|
sfd__h335644 <<
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4864[8] ?
|
|
9'h0AA :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4864) ;
|
|
assign _theResult___snd__h397061 = { _theResult____h388941[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h397072 =
|
|
(!_theResult____h388941[56] && _theResult____h388941[55]) ?
|
|
_theResult___snd__h397074 :
|
|
_theResult___snd__h397084 ;
|
|
assign _theResult___snd__h397074 = { _theResult____h388941[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h397084 =
|
|
(!_theResult____h388941[56] && !_theResult____h388941[55] &&
|
|
!_theResult____h388941[54] &&
|
|
!_theResult____h388941[53] &&
|
|
!_theResult____h388941[52] &&
|
|
!_theResult____h388941[51] &&
|
|
!_theResult____h388941[50] &&
|
|
!_theResult____h388941[49] &&
|
|
!_theResult____h388941[48] &&
|
|
!_theResult____h388941[47] &&
|
|
!_theResult____h388941[46] &&
|
|
!_theResult____h388941[45] &&
|
|
!_theResult____h388941[44] &&
|
|
!_theResult____h388941[43] &&
|
|
!_theResult____h388941[42] &&
|
|
!_theResult____h388941[41] &&
|
|
!_theResult____h388941[40] &&
|
|
!_theResult____h388941[39] &&
|
|
!_theResult____h388941[38] &&
|
|
!_theResult____h388941[37] &&
|
|
!_theResult____h388941[36] &&
|
|
!_theResult____h388941[35] &&
|
|
!_theResult____h388941[34] &&
|
|
!_theResult____h388941[33] &&
|
|
!_theResult____h388941[32] &&
|
|
!_theResult____h388941[31] &&
|
|
!_theResult____h388941[30] &&
|
|
!_theResult____h388941[29] &&
|
|
!_theResult____h388941[28] &&
|
|
!_theResult____h388941[27] &&
|
|
!_theResult____h388941[26] &&
|
|
!_theResult____h388941[25] &&
|
|
!_theResult____h388941[24] &&
|
|
!_theResult____h388941[23] &&
|
|
!_theResult____h388941[22] &&
|
|
!_theResult____h388941[21] &&
|
|
!_theResult____h388941[20] &&
|
|
!_theResult____h388941[19] &&
|
|
!_theResult____h388941[18] &&
|
|
!_theResult____h388941[17] &&
|
|
!_theResult____h388941[16] &&
|
|
!_theResult____h388941[15] &&
|
|
!_theResult____h388941[14] &&
|
|
!_theResult____h388941[13] &&
|
|
!_theResult____h388941[12] &&
|
|
!_theResult____h388941[11] &&
|
|
!_theResult____h388941[10] &&
|
|
!_theResult____h388941[9] &&
|
|
!_theResult____h388941[8] &&
|
|
!_theResult____h388941[7] &&
|
|
!_theResult____h388941[6] &&
|
|
!_theResult____h388941[5] &&
|
|
!_theResult____h388941[4] &&
|
|
!_theResult____h388941[3] &&
|
|
!_theResult____h388941[2] &&
|
|
!_theResult____h388941[1] &&
|
|
!_theResult____h388941[0]) ?
|
|
_theResult____h388941 :
|
|
_theResult___snd__h397090 ;
|
|
assign _theResult___snd__h397090 =
|
|
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q55[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h397113 =
|
|
_theResult____h388941 <<
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5631 ;
|
|
assign _theResult___snd__h405657 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___snd__h405666 :
|
|
_theResult___snd__h405659 ;
|
|
assign _theResult___snd__h405659 =
|
|
{ coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5],
|
|
5'd0 } ;
|
|
assign _theResult___snd__h405666 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5807) ?
|
|
sfd__h381339 :
|
|
_theResult___snd__h405672 ;
|
|
assign _theResult___snd__h405672 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q57[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h405695 =
|
|
sfd__h381339 <<
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5862 ;
|
|
assign _theResult___snd__h414827 = { _theResult____h406578[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h414838 =
|
|
(!_theResult____h406578[56] && _theResult____h406578[55]) ?
|
|
_theResult___snd__h414840 :
|
|
_theResult___snd__h414850 ;
|
|
assign _theResult___snd__h414840 = { _theResult____h406578[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h414850 =
|
|
(!_theResult____h406578[56] && !_theResult____h406578[55] &&
|
|
!_theResult____h406578[54] &&
|
|
!_theResult____h406578[53] &&
|
|
!_theResult____h406578[52] &&
|
|
!_theResult____h406578[51] &&
|
|
!_theResult____h406578[50] &&
|
|
!_theResult____h406578[49] &&
|
|
!_theResult____h406578[48] &&
|
|
!_theResult____h406578[47] &&
|
|
!_theResult____h406578[46] &&
|
|
!_theResult____h406578[45] &&
|
|
!_theResult____h406578[44] &&
|
|
!_theResult____h406578[43] &&
|
|
!_theResult____h406578[42] &&
|
|
!_theResult____h406578[41] &&
|
|
!_theResult____h406578[40] &&
|
|
!_theResult____h406578[39] &&
|
|
!_theResult____h406578[38] &&
|
|
!_theResult____h406578[37] &&
|
|
!_theResult____h406578[36] &&
|
|
!_theResult____h406578[35] &&
|
|
!_theResult____h406578[34] &&
|
|
!_theResult____h406578[33] &&
|
|
!_theResult____h406578[32] &&
|
|
!_theResult____h406578[31] &&
|
|
!_theResult____h406578[30] &&
|
|
!_theResult____h406578[29] &&
|
|
!_theResult____h406578[28] &&
|
|
!_theResult____h406578[27] &&
|
|
!_theResult____h406578[26] &&
|
|
!_theResult____h406578[25] &&
|
|
!_theResult____h406578[24] &&
|
|
!_theResult____h406578[23] &&
|
|
!_theResult____h406578[22] &&
|
|
!_theResult____h406578[21] &&
|
|
!_theResult____h406578[20] &&
|
|
!_theResult____h406578[19] &&
|
|
!_theResult____h406578[18] &&
|
|
!_theResult____h406578[17] &&
|
|
!_theResult____h406578[16] &&
|
|
!_theResult____h406578[15] &&
|
|
!_theResult____h406578[14] &&
|
|
!_theResult____h406578[13] &&
|
|
!_theResult____h406578[12] &&
|
|
!_theResult____h406578[11] &&
|
|
!_theResult____h406578[10] &&
|
|
!_theResult____h406578[9] &&
|
|
!_theResult____h406578[8] &&
|
|
!_theResult____h406578[7] &&
|
|
!_theResult____h406578[6] &&
|
|
!_theResult____h406578[5] &&
|
|
!_theResult____h406578[4] &&
|
|
!_theResult____h406578[3] &&
|
|
!_theResult____h406578[2] &&
|
|
!_theResult____h406578[1] &&
|
|
!_theResult____h406578[0]) ?
|
|
_theResult____h406578 :
|
|
_theResult___snd__h414856 ;
|
|
assign _theResult___snd__h414856 =
|
|
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q65[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h414879 =
|
|
_theResult____h406578 <<
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6182 ;
|
|
assign _theResult___snd__h423447 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___snd__h423461 :
|
|
_theResult___snd__h405659 ;
|
|
assign _theResult___snd__h423461 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5807) ?
|
|
sfd__h381339 :
|
|
_theResult___snd__h423467 ;
|
|
assign _theResult___snd__h423467 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q70[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h423485 =
|
|
sfd__h381339 <<
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6256[8] ?
|
|
9'h0AA :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6256) ;
|
|
assign _theResult___snd__h442749 = { _theResult____h434629[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h442760 =
|
|
(!_theResult____h434629[56] && _theResult____h434629[55]) ?
|
|
_theResult___snd__h442762 :
|
|
_theResult___snd__h442772 ;
|
|
assign _theResult___snd__h442762 = { _theResult____h434629[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h442772 =
|
|
(!_theResult____h434629[56] && !_theResult____h434629[55] &&
|
|
!_theResult____h434629[54] &&
|
|
!_theResult____h434629[53] &&
|
|
!_theResult____h434629[52] &&
|
|
!_theResult____h434629[51] &&
|
|
!_theResult____h434629[50] &&
|
|
!_theResult____h434629[49] &&
|
|
!_theResult____h434629[48] &&
|
|
!_theResult____h434629[47] &&
|
|
!_theResult____h434629[46] &&
|
|
!_theResult____h434629[45] &&
|
|
!_theResult____h434629[44] &&
|
|
!_theResult____h434629[43] &&
|
|
!_theResult____h434629[42] &&
|
|
!_theResult____h434629[41] &&
|
|
!_theResult____h434629[40] &&
|
|
!_theResult____h434629[39] &&
|
|
!_theResult____h434629[38] &&
|
|
!_theResult____h434629[37] &&
|
|
!_theResult____h434629[36] &&
|
|
!_theResult____h434629[35] &&
|
|
!_theResult____h434629[34] &&
|
|
!_theResult____h434629[33] &&
|
|
!_theResult____h434629[32] &&
|
|
!_theResult____h434629[31] &&
|
|
!_theResult____h434629[30] &&
|
|
!_theResult____h434629[29] &&
|
|
!_theResult____h434629[28] &&
|
|
!_theResult____h434629[27] &&
|
|
!_theResult____h434629[26] &&
|
|
!_theResult____h434629[25] &&
|
|
!_theResult____h434629[24] &&
|
|
!_theResult____h434629[23] &&
|
|
!_theResult____h434629[22] &&
|
|
!_theResult____h434629[21] &&
|
|
!_theResult____h434629[20] &&
|
|
!_theResult____h434629[19] &&
|
|
!_theResult____h434629[18] &&
|
|
!_theResult____h434629[17] &&
|
|
!_theResult____h434629[16] &&
|
|
!_theResult____h434629[15] &&
|
|
!_theResult____h434629[14] &&
|
|
!_theResult____h434629[13] &&
|
|
!_theResult____h434629[12] &&
|
|
!_theResult____h434629[11] &&
|
|
!_theResult____h434629[10] &&
|
|
!_theResult____h434629[9] &&
|
|
!_theResult____h434629[8] &&
|
|
!_theResult____h434629[7] &&
|
|
!_theResult____h434629[6] &&
|
|
!_theResult____h434629[5] &&
|
|
!_theResult____h434629[4] &&
|
|
!_theResult____h434629[3] &&
|
|
!_theResult____h434629[2] &&
|
|
!_theResult____h434629[1] &&
|
|
!_theResult____h434629[0]) ?
|
|
_theResult____h434629 :
|
|
_theResult___snd__h442778 ;
|
|
assign _theResult___snd__h442778 =
|
|
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q90[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h442801 =
|
|
_theResult____h434629 <<
|
|
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7023 ;
|
|
assign _theResult___snd__h451345 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___snd__h451354 :
|
|
_theResult___snd__h451347 ;
|
|
assign _theResult___snd__h451347 =
|
|
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5],
|
|
5'd0 } ;
|
|
assign _theResult___snd__h451354 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7199) ?
|
|
sfd__h427027 :
|
|
_theResult___snd__h451360 ;
|
|
assign _theResult___snd__h451360 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q92[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h451383 =
|
|
sfd__h427027 <<
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7254 ;
|
|
assign _theResult___snd__h460515 = { _theResult____h452266[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h460526 =
|
|
(!_theResult____h452266[56] && _theResult____h452266[55]) ?
|
|
_theResult___snd__h460528 :
|
|
_theResult___snd__h460538 ;
|
|
assign _theResult___snd__h460528 = { _theResult____h452266[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h460538 =
|
|
(!_theResult____h452266[56] && !_theResult____h452266[55] &&
|
|
!_theResult____h452266[54] &&
|
|
!_theResult____h452266[53] &&
|
|
!_theResult____h452266[52] &&
|
|
!_theResult____h452266[51] &&
|
|
!_theResult____h452266[50] &&
|
|
!_theResult____h452266[49] &&
|
|
!_theResult____h452266[48] &&
|
|
!_theResult____h452266[47] &&
|
|
!_theResult____h452266[46] &&
|
|
!_theResult____h452266[45] &&
|
|
!_theResult____h452266[44] &&
|
|
!_theResult____h452266[43] &&
|
|
!_theResult____h452266[42] &&
|
|
!_theResult____h452266[41] &&
|
|
!_theResult____h452266[40] &&
|
|
!_theResult____h452266[39] &&
|
|
!_theResult____h452266[38] &&
|
|
!_theResult____h452266[37] &&
|
|
!_theResult____h452266[36] &&
|
|
!_theResult____h452266[35] &&
|
|
!_theResult____h452266[34] &&
|
|
!_theResult____h452266[33] &&
|
|
!_theResult____h452266[32] &&
|
|
!_theResult____h452266[31] &&
|
|
!_theResult____h452266[30] &&
|
|
!_theResult____h452266[29] &&
|
|
!_theResult____h452266[28] &&
|
|
!_theResult____h452266[27] &&
|
|
!_theResult____h452266[26] &&
|
|
!_theResult____h452266[25] &&
|
|
!_theResult____h452266[24] &&
|
|
!_theResult____h452266[23] &&
|
|
!_theResult____h452266[22] &&
|
|
!_theResult____h452266[21] &&
|
|
!_theResult____h452266[20] &&
|
|
!_theResult____h452266[19] &&
|
|
!_theResult____h452266[18] &&
|
|
!_theResult____h452266[17] &&
|
|
!_theResult____h452266[16] &&
|
|
!_theResult____h452266[15] &&
|
|
!_theResult____h452266[14] &&
|
|
!_theResult____h452266[13] &&
|
|
!_theResult____h452266[12] &&
|
|
!_theResult____h452266[11] &&
|
|
!_theResult____h452266[10] &&
|
|
!_theResult____h452266[9] &&
|
|
!_theResult____h452266[8] &&
|
|
!_theResult____h452266[7] &&
|
|
!_theResult____h452266[6] &&
|
|
!_theResult____h452266[5] &&
|
|
!_theResult____h452266[4] &&
|
|
!_theResult____h452266[3] &&
|
|
!_theResult____h452266[2] &&
|
|
!_theResult____h452266[1] &&
|
|
!_theResult____h452266[0]) ?
|
|
_theResult____h452266 :
|
|
_theResult___snd__h460544 ;
|
|
assign _theResult___snd__h460544 =
|
|
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q100[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h460567 =
|
|
_theResult____h452266 <<
|
|
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7574 ;
|
|
assign _theResult___snd__h469135 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0) ?
|
|
_theResult___snd__h469149 :
|
|
_theResult___snd__h451347 ;
|
|
assign _theResult___snd__h469149 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd0 &&
|
|
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7199) ?
|
|
sfd__h427027 :
|
|
_theResult___snd__h469155 ;
|
|
assign _theResult___snd__h469155 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q105[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h469173 =
|
|
sfd__h427027 <<
|
|
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7648[8] ?
|
|
9'h0AA :
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7648) ;
|
|
assign _theResult___snd__h498574 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
_theResult___snd__h498583 :
|
|
_theResult___snd__h498576 ;
|
|
assign _theResult___snd__h498576 =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 34'd0 } ;
|
|
assign _theResult___snd__h498583 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8544) ?
|
|
sfd__h479622 :
|
|
_theResult___snd__h498589 ;
|
|
assign _theResult___snd__h498589 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q126[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h498612 =
|
|
sfd__h479622 <<
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8571 ;
|
|
assign _theResult___snd__h508211 = { _theResult____h499964[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h508222 =
|
|
(!_theResult____h499964[56] && _theResult____h499964[55]) ?
|
|
_theResult___snd__h508224 :
|
|
_theResult___snd__h508234 ;
|
|
assign _theResult___snd__h508224 = { _theResult____h499964[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h508234 =
|
|
(!_theResult____h499964[56] && !_theResult____h499964[55] &&
|
|
!_theResult____h499964[54] &&
|
|
!_theResult____h499964[53] &&
|
|
!_theResult____h499964[52] &&
|
|
!_theResult____h499964[51] &&
|
|
!_theResult____h499964[50] &&
|
|
!_theResult____h499964[49] &&
|
|
!_theResult____h499964[48] &&
|
|
!_theResult____h499964[47] &&
|
|
!_theResult____h499964[46] &&
|
|
!_theResult____h499964[45] &&
|
|
!_theResult____h499964[44] &&
|
|
!_theResult____h499964[43] &&
|
|
!_theResult____h499964[42] &&
|
|
!_theResult____h499964[41] &&
|
|
!_theResult____h499964[40] &&
|
|
!_theResult____h499964[39] &&
|
|
!_theResult____h499964[38] &&
|
|
!_theResult____h499964[37] &&
|
|
!_theResult____h499964[36] &&
|
|
!_theResult____h499964[35] &&
|
|
!_theResult____h499964[34] &&
|
|
!_theResult____h499964[33] &&
|
|
!_theResult____h499964[32] &&
|
|
!_theResult____h499964[31] &&
|
|
!_theResult____h499964[30] &&
|
|
!_theResult____h499964[29] &&
|
|
!_theResult____h499964[28] &&
|
|
!_theResult____h499964[27] &&
|
|
!_theResult____h499964[26] &&
|
|
!_theResult____h499964[25] &&
|
|
!_theResult____h499964[24] &&
|
|
!_theResult____h499964[23] &&
|
|
!_theResult____h499964[22] &&
|
|
!_theResult____h499964[21] &&
|
|
!_theResult____h499964[20] &&
|
|
!_theResult____h499964[19] &&
|
|
!_theResult____h499964[18] &&
|
|
!_theResult____h499964[17] &&
|
|
!_theResult____h499964[16] &&
|
|
!_theResult____h499964[15] &&
|
|
!_theResult____h499964[14] &&
|
|
!_theResult____h499964[13] &&
|
|
!_theResult____h499964[12] &&
|
|
!_theResult____h499964[11] &&
|
|
!_theResult____h499964[10] &&
|
|
!_theResult____h499964[9] &&
|
|
!_theResult____h499964[8] &&
|
|
!_theResult____h499964[7] &&
|
|
!_theResult____h499964[6] &&
|
|
!_theResult____h499964[5] &&
|
|
!_theResult____h499964[4] &&
|
|
!_theResult____h499964[3] &&
|
|
!_theResult____h499964[2] &&
|
|
!_theResult____h499964[1] &&
|
|
!_theResult____h499964[0]) ?
|
|
_theResult____h499964 :
|
|
_theResult___snd__h508240 ;
|
|
assign _theResult___snd__h508240 =
|
|
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q130[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h508263 =
|
|
_theResult____h499964 <<
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d8883 ;
|
|
assign _theResult___snd__h516979 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0) ?
|
|
_theResult___snd__h516993 :
|
|
_theResult___snd__h498576 ;
|
|
assign _theResult___snd__h516993 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[162] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d8544) ?
|
|
sfd__h479622 :
|
|
_theResult___snd__h516999 ;
|
|
assign _theResult___snd__h516999 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q133[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h517017 =
|
|
sfd__h479622 <<
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8934 ;
|
|
assign _theResult___snd__h537375 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
_theResult___snd__h537384 :
|
|
_theResult___snd__h537377 ;
|
|
assign _theResult___snd__h537377 =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 34'd0 } ;
|
|
assign _theResult___snd__h537384 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10032) ?
|
|
sfd__h518564 :
|
|
_theResult___snd__h537390 ;
|
|
assign _theResult___snd__h537390 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q166[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h537413 =
|
|
sfd__h518564 <<
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10059 ;
|
|
assign _theResult___snd__h547012 = { _theResult____h538765[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h547023 =
|
|
(!_theResult____h538765[56] && _theResult____h538765[55]) ?
|
|
_theResult___snd__h547025 :
|
|
_theResult___snd__h547035 ;
|
|
assign _theResult___snd__h547025 = { _theResult____h538765[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h547035 =
|
|
(!_theResult____h538765[56] && !_theResult____h538765[55] &&
|
|
!_theResult____h538765[54] &&
|
|
!_theResult____h538765[53] &&
|
|
!_theResult____h538765[52] &&
|
|
!_theResult____h538765[51] &&
|
|
!_theResult____h538765[50] &&
|
|
!_theResult____h538765[49] &&
|
|
!_theResult____h538765[48] &&
|
|
!_theResult____h538765[47] &&
|
|
!_theResult____h538765[46] &&
|
|
!_theResult____h538765[45] &&
|
|
!_theResult____h538765[44] &&
|
|
!_theResult____h538765[43] &&
|
|
!_theResult____h538765[42] &&
|
|
!_theResult____h538765[41] &&
|
|
!_theResult____h538765[40] &&
|
|
!_theResult____h538765[39] &&
|
|
!_theResult____h538765[38] &&
|
|
!_theResult____h538765[37] &&
|
|
!_theResult____h538765[36] &&
|
|
!_theResult____h538765[35] &&
|
|
!_theResult____h538765[34] &&
|
|
!_theResult____h538765[33] &&
|
|
!_theResult____h538765[32] &&
|
|
!_theResult____h538765[31] &&
|
|
!_theResult____h538765[30] &&
|
|
!_theResult____h538765[29] &&
|
|
!_theResult____h538765[28] &&
|
|
!_theResult____h538765[27] &&
|
|
!_theResult____h538765[26] &&
|
|
!_theResult____h538765[25] &&
|
|
!_theResult____h538765[24] &&
|
|
!_theResult____h538765[23] &&
|
|
!_theResult____h538765[22] &&
|
|
!_theResult____h538765[21] &&
|
|
!_theResult____h538765[20] &&
|
|
!_theResult____h538765[19] &&
|
|
!_theResult____h538765[18] &&
|
|
!_theResult____h538765[17] &&
|
|
!_theResult____h538765[16] &&
|
|
!_theResult____h538765[15] &&
|
|
!_theResult____h538765[14] &&
|
|
!_theResult____h538765[13] &&
|
|
!_theResult____h538765[12] &&
|
|
!_theResult____h538765[11] &&
|
|
!_theResult____h538765[10] &&
|
|
!_theResult____h538765[9] &&
|
|
!_theResult____h538765[8] &&
|
|
!_theResult____h538765[7] &&
|
|
!_theResult____h538765[6] &&
|
|
!_theResult____h538765[5] &&
|
|
!_theResult____h538765[4] &&
|
|
!_theResult____h538765[3] &&
|
|
!_theResult____h538765[2] &&
|
|
!_theResult____h538765[1] &&
|
|
!_theResult____h538765[0]) ?
|
|
_theResult____h538765 :
|
|
_theResult___snd__h547041 ;
|
|
assign _theResult___snd__h547041 =
|
|
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q170[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h547064 =
|
|
_theResult____h538765 <<
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d10356 ;
|
|
assign _theResult___snd__h555780 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0) ?
|
|
_theResult___snd__h555794 :
|
|
_theResult___snd__h537377 ;
|
|
assign _theResult___snd__h555794 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[98] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10032) ?
|
|
sfd__h518564 :
|
|
_theResult___snd__h555800 ;
|
|
assign _theResult___snd__h555800 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q173[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h555818 =
|
|
sfd__h518564 <<
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10407 ;
|
|
assign _theResult___snd__h576576 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
_theResult___snd__h576585 :
|
|
_theResult___snd__h576578 ;
|
|
assign _theResult___snd__h576578 =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 34'd0 } ;
|
|
assign _theResult___snd__h576585 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9269) ?
|
|
sfd__h557765 :
|
|
_theResult___snd__h576591 ;
|
|
assign _theResult___snd__h576591 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q143[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h576614 =
|
|
sfd__h557765 <<
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9296 ;
|
|
assign _theResult___snd__h586213 = { _theResult____h577966[55:0], 1'd0 } ;
|
|
assign _theResult___snd__h586224 =
|
|
(!_theResult____h577966[56] && _theResult____h577966[55]) ?
|
|
_theResult___snd__h586226 :
|
|
_theResult___snd__h586236 ;
|
|
assign _theResult___snd__h586226 = { _theResult____h577966[54:0], 2'd0 } ;
|
|
assign _theResult___snd__h586236 =
|
|
(!_theResult____h577966[56] && !_theResult____h577966[55] &&
|
|
!_theResult____h577966[54] &&
|
|
!_theResult____h577966[53] &&
|
|
!_theResult____h577966[52] &&
|
|
!_theResult____h577966[51] &&
|
|
!_theResult____h577966[50] &&
|
|
!_theResult____h577966[49] &&
|
|
!_theResult____h577966[48] &&
|
|
!_theResult____h577966[47] &&
|
|
!_theResult____h577966[46] &&
|
|
!_theResult____h577966[45] &&
|
|
!_theResult____h577966[44] &&
|
|
!_theResult____h577966[43] &&
|
|
!_theResult____h577966[42] &&
|
|
!_theResult____h577966[41] &&
|
|
!_theResult____h577966[40] &&
|
|
!_theResult____h577966[39] &&
|
|
!_theResult____h577966[38] &&
|
|
!_theResult____h577966[37] &&
|
|
!_theResult____h577966[36] &&
|
|
!_theResult____h577966[35] &&
|
|
!_theResult____h577966[34] &&
|
|
!_theResult____h577966[33] &&
|
|
!_theResult____h577966[32] &&
|
|
!_theResult____h577966[31] &&
|
|
!_theResult____h577966[30] &&
|
|
!_theResult____h577966[29] &&
|
|
!_theResult____h577966[28] &&
|
|
!_theResult____h577966[27] &&
|
|
!_theResult____h577966[26] &&
|
|
!_theResult____h577966[25] &&
|
|
!_theResult____h577966[24] &&
|
|
!_theResult____h577966[23] &&
|
|
!_theResult____h577966[22] &&
|
|
!_theResult____h577966[21] &&
|
|
!_theResult____h577966[20] &&
|
|
!_theResult____h577966[19] &&
|
|
!_theResult____h577966[18] &&
|
|
!_theResult____h577966[17] &&
|
|
!_theResult____h577966[16] &&
|
|
!_theResult____h577966[15] &&
|
|
!_theResult____h577966[14] &&
|
|
!_theResult____h577966[13] &&
|
|
!_theResult____h577966[12] &&
|
|
!_theResult____h577966[11] &&
|
|
!_theResult____h577966[10] &&
|
|
!_theResult____h577966[9] &&
|
|
!_theResult____h577966[8] &&
|
|
!_theResult____h577966[7] &&
|
|
!_theResult____h577966[6] &&
|
|
!_theResult____h577966[5] &&
|
|
!_theResult____h577966[4] &&
|
|
!_theResult____h577966[3] &&
|
|
!_theResult____h577966[2] &&
|
|
!_theResult____h577966[1] &&
|
|
!_theResult____h577966[0]) ?
|
|
_theResult____h577966 :
|
|
_theResult___snd__h586242 ;
|
|
assign _theResult___snd__h586242 =
|
|
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_coreFix_fpuM_ETC__q147[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h586265 =
|
|
_theResult____h577966 <<
|
|
IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_r_ETC___d9593 ;
|
|
assign _theResult___snd__h594981 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0) ?
|
|
_theResult___snd__h594995 :
|
|
_theResult___snd__h576578 ;
|
|
assign _theResult___snd__h594995 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] == 8'd0 &&
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[34] &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d9269) ?
|
|
sfd__h557765 :
|
|
_theResult___snd__h595001 ;
|
|
assign _theResult___snd__h595001 =
|
|
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_regToExe_ETC__q150[54:0],
|
|
2'd0 } ;
|
|
assign _theResult___snd__h595019 =
|
|
sfd__h557765 <<
|
|
IF_SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9644 ;
|
|
assign _theResult___snd__h600209 =
|
|
b__h599787[63] ? b___1__h600258 : b__h599787 ;
|
|
assign _theResult___snd_fst_exp__h360542 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
_theResult___fst_exp__h351957 :
|
|
_theResult___fst_exp__h360539 ;
|
|
assign _theResult___snd_fst_exp__h378362 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 ?
|
|
_theResult___fst_exp__h369723 :
|
|
_theResult___fst_exp__h378359 ;
|
|
assign _theResult___snd_fst_exp__h406232 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
_theResult___fst_exp__h397647 :
|
|
_theResult___fst_exp__h406229 ;
|
|
assign _theResult___snd_fst_exp__h424052 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 ?
|
|
_theResult___fst_exp__h415413 :
|
|
_theResult___fst_exp__h424049 ;
|
|
assign _theResult___snd_fst_exp__h451920 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
_theResult___fst_exp__h443335 :
|
|
_theResult___fst_exp__h451917 ;
|
|
assign _theResult___snd_fst_exp__h469740 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 ?
|
|
_theResult___fst_exp__h461101 :
|
|
_theResult___fst_exp__h469737 ;
|
|
assign _theResult___snd_fst_exp__h499384 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h499381 ;
|
|
assign _theResult___snd_fst_exp__h517819 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 ?
|
|
_theResult___fst_exp__h509032 :
|
|
_theResult___fst_exp__h517816 ;
|
|
assign _theResult___snd_fst_exp__h538185 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h538182 ;
|
|
assign _theResult___snd_fst_exp__h556620 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 ?
|
|
_theResult___fst_exp__h547833 :
|
|
_theResult___fst_exp__h556617 ;
|
|
assign _theResult___snd_fst_exp__h577386 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 ?
|
|
11'd0 :
|
|
_theResult___fst_exp__h577383 ;
|
|
assign _theResult___snd_fst_exp__h595821 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 ?
|
|
_theResult___fst_exp__h587034 :
|
|
_theResult___fst_exp__h595818 ;
|
|
assign _theResult___snd_fst_sfd__h335594 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ==
|
|
23'd0) ?
|
|
23'd2097152 :
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ;
|
|
assign _theResult___snd_fst_sfd__h360543 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4005 ?
|
|
_theResult___fst_sfd__h351958 :
|
|
_theResult___fst_sfd__h360540 ;
|
|
assign _theResult___snd_fst_sfd__h378363 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4545 ?
|
|
_theResult___fst_sfd__h369724 :
|
|
_theResult___fst_sfd__h378360 ;
|
|
assign _theResult___snd_fst_sfd__h381289 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ==
|
|
23'd0) ?
|
|
23'd2097152 :
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ;
|
|
assign _theResult___snd_fst_sfd__h406233 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5397 ?
|
|
_theResult___fst_sfd__h397648 :
|
|
_theResult___fst_sfd__h406230 ;
|
|
assign _theResult___snd_fst_sfd__h424053 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5937 ?
|
|
_theResult___fst_sfd__h415414 :
|
|
_theResult___fst_sfd__h424050 ;
|
|
assign _theResult___snd_fst_sfd__h426977 =
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ==
|
|
23'd0) ?
|
|
23'd2097152 :
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ;
|
|
assign _theResult___snd_fst_sfd__h451921 =
|
|
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6789 ?
|
|
_theResult___fst_sfd__h443336 :
|
|
_theResult___fst_sfd__h451918 ;
|
|
assign _theResult___snd_fst_sfd__h469741 =
|
|
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7329 ?
|
|
_theResult___fst_sfd__h461102 :
|
|
_theResult___fst_sfd__h469738 ;
|
|
assign _theResult___snd_fst_sfd__h479576 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] == 23'd0) ?
|
|
52'h4000000000000 :
|
|
out___1_sfd__h479325 ;
|
|
assign _theResult___snd_fst_sfd__h499385 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8500 ?
|
|
52'd0 :
|
|
_theResult___fst_sfd__h499382 ;
|
|
assign _theResult___snd_fst_sfd__h517820 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d8636 ?
|
|
_theResult___fst_sfd__h509033 :
|
|
_theResult___fst_sfd__h517817 ;
|
|
assign _theResult___snd_fst_sfd__h518518 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] == 23'd0) ?
|
|
52'h4000000000000 :
|
|
out___1_sfd__h518267 ;
|
|
assign _theResult___snd_fst_sfd__h538186 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9988 ?
|
|
52'd0 :
|
|
_theResult___fst_sfd__h538183 ;
|
|
assign _theResult___snd_fst_sfd__h556621 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d10109 ?
|
|
_theResult___fst_sfd__h547834 :
|
|
_theResult___fst_sfd__h556618 ;
|
|
assign _theResult___snd_fst_sfd__h557719 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) ?
|
|
52'h4000000000000 :
|
|
out___1_sfd__h557468 ;
|
|
assign _theResult___snd_fst_sfd__h577387 =
|
|
_3970_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d9225 ?
|
|
52'd0 :
|
|
_theResult___fst_sfd__h577384 ;
|
|
assign _theResult___snd_fst_sfd__h595822 =
|
|
SEXT_coreFix_fpuMulDivExe_0_regToExeQ_first__3_ETC___d9346 ?
|
|
_theResult___fst_sfd__h587035 :
|
|
_theResult___fst_sfd__h595819 ;
|
|
assign a___1__h599927 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ?
|
|
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } :
|
|
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2[31]}},
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 } ;
|
|
assign a___1__h600213 = 64'd0 - a__h599786 ;
|
|
assign a__h599786 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
|
|
a___1__h599927 :
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
|
|
assign b___1__h599928 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
|
|
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3[31]}},
|
|
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 } :
|
|
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ;
|
|
assign b___1__h600258 = 64'd0 - b__h599787 ;
|
|
assign b__h599787 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
|
|
b___1__h599928 :
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
|
|
assign base__h691735 = { csrf_stvec_base_hi_reg, 2'b0 } ;
|
|
assign base__h691938 = { csrf_mtvec_base_hi_reg, 2'b0 } ;
|
|
assign cause_code__h689130 =
|
|
commitStage_commitTrap[4] ? i__h689305 : i__h689145 ;
|
|
assign coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12093 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
|
|
assign coreFix_aluExe_0_bypassWire_0_wget__2091_BITS__ETC___d12132 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
|
|
assign coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12106 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
|
|
assign coreFix_aluExe_0_bypassWire_1_wget__2104_BITS__ETC___d12138 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
|
|
assign coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12114 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
|
|
assign coreFix_aluExe_0_bypassWire_2_wget__2112_BITS__ETC___d12142 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
|
|
assign coreFix_aluExe_0_dispToRegQ_first__2070_BIT_13_ETC___d12155 =
|
|
(coreFix_aluExe_0_dispToRegQ$first[131] ||
|
|
sbCons$lazyLookup_0_get[3] ||
|
|
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2069_ETC___d12101 &&
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12127) &&
|
|
(sbCons$lazyLookup_0_get[2] ||
|
|
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2069_ETC___d12135 &&
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12152) ;
|
|
assign coreFix_aluExe_0_exeToFinQ_RDY_first__2480_AND_ETC___d12518 =
|
|
coreFix_aluExe_0_exeToFinQ$RDY_first &&
|
|
rob$RDY_setExecuted_doFinishAlu_0_set &&
|
|
(coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd9 &&
|
|
coreFix_aluExe_0_exeToFinQ$first[325:321] != 5'd10 ||
|
|
coreFix_trainBPQ_0$FULL_N) ;
|
|
assign coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139 =
|
|
coreFix_aluExe_0_rsAlu$approximateCount <
|
|
coreFix_aluExe_1_rsAlu$approximateCount ;
|
|
assign coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11302 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
|
|
assign coreFix_aluExe_1_bypassWire_0_wget__1300_BITS__ETC___d11341 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
|
|
assign coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11315 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
|
|
assign coreFix_aluExe_1_bypassWire_1_wget__1313_BITS__ETC___d11347 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
|
|
assign coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11323 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
|
|
assign coreFix_aluExe_1_bypassWire_2_wget__1321_BITS__ETC___d11351 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
|
|
assign coreFix_aluExe_1_dispToRegQ_first__1279_BIT_13_ETC___d11364 =
|
|
(coreFix_aluExe_1_dispToRegQ$first[131] ||
|
|
sbCons$lazyLookup_1_get[3] ||
|
|
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1278_ETC___d11310 &&
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11336) &&
|
|
(sbCons$lazyLookup_1_get[2] ||
|
|
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1278_ETC___d11344 &&
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11361) ;
|
|
assign coreFix_aluExe_1_exeToFinQ_RDY_first__1873_AND_ETC___d11912 =
|
|
coreFix_aluExe_1_exeToFinQ$RDY_first &&
|
|
rob$RDY_setExecuted_doFinishAlu_1_set &&
|
|
(coreFix_aluExe_1_exeToFinQ$first[325:321] != 5'd9 &&
|
|
coreFix_aluExe_1_exeToFinQ$first[325:321] != 5'd10 ||
|
|
coreFix_trainBPQ_1$FULL_N) ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8202 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8240 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__200__ETC___d8264 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8215 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8246 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__213__ETC___d8270 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8223 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8250 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
|
|
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__221__ETC___d8274 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5264 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned &&
|
|
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q63 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] -
|
|
11'd1023 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q28 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] -
|
|
11'd1023 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q98 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] -
|
|
11'd1023 ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3872 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned &&
|
|
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ;
|
|
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6656 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
|
|
!coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned &&
|
|
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8094 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
|
|
(!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
|
|
((coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
|
|
2'd2) ?
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid :
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] !=
|
|
2'd3 ||
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid)) ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8097 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
|
|
!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned &&
|
|
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8094 ;
|
|
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8048 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
|
|
!coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned &&
|
|
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10826 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10781 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10821) ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10862 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10850 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10857) ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10910 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10894 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10905) ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10952 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10938 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10947) ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10994 =
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10980 |
|
|
((coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] == 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd255 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
(coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0 ||
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] != 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10989) ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q168 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] - 8'd127 ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q3 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q128 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] - 8'd127 ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q2 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ;
|
|
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_42_ETC__q145 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] - 8'd127 ;
|
|
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__35_ETC___d13641 =
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
|
|
regRenamingTable$RDY_rename_1_getRename &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13621) ;
|
|
assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[61:55] ;
|
|
assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608 =
|
|
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[53:47] ;
|
|
assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[61:55] ;
|
|
assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 =
|
|
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[53:47] ;
|
|
assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[61:55] ;
|
|
assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 =
|
|
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
|
|
coreFix_memExe_dispToRegQ$first[53:47] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2569 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
|
|
2'd0 &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
|
|
y__h251971 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3059 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023 ||
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
|
|
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3162 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3130 ||
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2062 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2062 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2719 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ==
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
|
|
2'd2 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2523 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019 &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd3 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142) ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2552 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd2 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2557 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2549 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2556 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2574 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2549 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2573 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2591 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2584 ||
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2590 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2611 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2088 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2614 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd0 &&
|
|
coreFix_memExe_lsq$getHit[8] &&
|
|
!coreFix_memExe_lsq$getHit[9] ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2611 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2635 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
|
|
3'd3 &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2064 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2641 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2635 ||
|
|
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
|
|
3'd1) &&
|
|
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638 ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2009 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2019 &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
|
|
3'd3 ||
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2689 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2692 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
|
|
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2789 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2802 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2811 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2820 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2832 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3333 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3301 ||
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_dCacheToParent_rqToP_deq &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ;
|
|
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3429 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3397 ||
|
|
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_dCacheToParent_rsToP_deq &&
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) &&
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ;
|
|
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1903 =
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ||
|
|
(!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_dMem_perfReqQ_deqReq_rl) &&
|
|
coreFix_memExe_dMem_perfReqQ_full ;
|
|
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 =
|
|
coreFix_memExe_dTlb$procResp[174:114] < 61'd402653184 ;
|
|
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1724 =
|
|
coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ;
|
|
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 =
|
|
coreFix_memExe_dTlb$procResp[174:114] == mmio_fromHostAddr ;
|
|
assign coreFix_memExe_dTlb_procResp__712_BIT_110_715__ETC___d1729 =
|
|
!coreFix_memExe_dTlb$procResp[12] &&
|
|
!coreFix_memExe_dTlb$procResp[110] &&
|
|
(coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 ||
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1724 ||
|
|
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727) ;
|
|
assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3751 =
|
|
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3720 ||
|
|
(!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT ||
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
|
|
!coreFix_memExe_forwardQ_deqReq_rl) &&
|
|
coreFix_memExe_forwardQ_full ;
|
|
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3657 =
|
|
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3626 ||
|
|
(!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT ||
|
|
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
|
|
!coreFix_memExe_memRespLdQ_deqReq_rl) &&
|
|
coreFix_memExe_memRespLdQ_full ;
|
|
assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 =
|
|
coreFix_memExe_regToExeQ$first[189:158] ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ;
|
|
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ;
|
|
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3566 =
|
|
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3550 ||
|
|
(!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT ||
|
|
!coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas &&
|
|
!coreFix_memExe_respLrScAmoQ_deqReq_rl) &&
|
|
coreFix_memExe_respLrScAmoQ_full ;
|
|
assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14167 =
|
|
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
|
|
rob$RDY_deqPort_0_deq_data &&
|
|
rob$RDY_deqPort_0_deq &&
|
|
regRenamingTable$RDY_commit_0_commit &&
|
|
fetchStage$iTlbIfc_noPendingReq &&
|
|
coreFix_memExe_dTlb$noPendingReq &&
|
|
NOT_rob_deqPort_0_deq_data__3921_BITS_122_TO_1_ETC___d14162 ;
|
|
assign csrf_debug_int_pend_read__1643_CONCAT_0b0_2627_ETC___d12632 =
|
|
{ csrf_debug_int_pend,
|
|
2'b0,
|
|
csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3,
|
|
1'd0,
|
|
csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1,
|
|
csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ;
|
|
assign csrf_debug_int_pend_read__1643_CONCAT_0b0_2627_ETC___d12637 =
|
|
{ csrf_debug_int_pend_read__1643_CONCAT_0b0_2627_ETC___d12632,
|
|
csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3,
|
|
1'd0,
|
|
csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1,
|
|
csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ;
|
|
assign csrf_prv_reg_read__2623_ULE_1_3987_AND_IF_comm_ETC___d14027 =
|
|
csrf_prv_reg_read__2623_ULE_1___d13987 &&
|
|
(commitStage_commitTrap[4] ?
|
|
_0b0_CONCAT_csrf_mideleg_11_reg_read__1600_1601_ETC___d14007 :
|
|
_0b0_CONCAT_csrf_medeleg_15_reg_read__1592_1593_ETC___d14025) ;
|
|
assign csrf_prv_reg_read__2623_ULE_1___d13987 = csrf_prv_reg <= 2'd1 ;
|
|
assign data72428_BITS_31_TO_0__q5 = data__h472428[31:0] ;
|
|
assign data___1__h472154 =
|
|
{ {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125[31]}},
|
|
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q125 } ;
|
|
assign data___1__h472962 =
|
|
{ {32{data72428_BITS_31_TO_0__q5[31]}},
|
|
data72428_BITS_31_TO_0__q5 } ;
|
|
assign data__h472428 =
|
|
(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
|
|
2'd2) ?
|
|
x_quotient__h472342 :
|
|
x_remainder__h472343 ;
|
|
assign din_inc___2_exp__h378393 = _theResult___fst_exp__h351360 + 8'd1 ;
|
|
assign din_inc___2_exp__h378417 = _theResult___fst_exp__h360016 + 8'd1 ;
|
|
assign din_inc___2_exp__h378447 = _theResult___fst_exp__h369126 + 8'd1 ;
|
|
assign din_inc___2_exp__h378471 = _theResult___fst_exp__h377811 + 8'd1 ;
|
|
assign din_inc___2_exp__h424083 = _theResult___fst_exp__h397050 + 8'd1 ;
|
|
assign din_inc___2_exp__h424107 = _theResult___fst_exp__h405706 + 8'd1 ;
|
|
assign din_inc___2_exp__h424137 = _theResult___fst_exp__h414816 + 8'd1 ;
|
|
assign din_inc___2_exp__h424161 = _theResult___fst_exp__h423501 + 8'd1 ;
|
|
assign din_inc___2_exp__h469771 = _theResult___fst_exp__h442738 + 8'd1 ;
|
|
assign din_inc___2_exp__h469795 = _theResult___fst_exp__h451394 + 8'd1 ;
|
|
assign din_inc___2_exp__h469825 = _theResult___fst_exp__h460504 + 8'd1 ;
|
|
assign din_inc___2_exp__h469849 = _theResult___fst_exp__h469189 + 8'd1 ;
|
|
assign din_inc___2_exp__h517873 = _theResult___fst_exp__h498623 + 11'd1 ;
|
|
assign din_inc___2_exp__h517908 = _theResult___fst_exp__h508200 + 11'd1 ;
|
|
assign din_inc___2_exp__h517934 = _theResult___fst_exp__h517033 + 11'd1 ;
|
|
assign din_inc___2_exp__h556674 = _theResult___fst_exp__h537424 + 11'd1 ;
|
|
assign din_inc___2_exp__h556709 = _theResult___fst_exp__h547001 + 11'd1 ;
|
|
assign din_inc___2_exp__h556735 = _theResult___fst_exp__h555834 + 11'd1 ;
|
|
assign din_inc___2_exp__h595875 = _theResult___fst_exp__h576625 + 11'd1 ;
|
|
assign din_inc___2_exp__h595910 = _theResult___fst_exp__h586202 + 11'd1 ;
|
|
assign din_inc___2_exp__h595936 = _theResult___fst_exp__h595035 + 11'd1 ;
|
|
assign enabled_ints___1__h645617 = pend_ints__h645118 & y__h645629 ;
|
|
assign enabled_ints__h645664 =
|
|
pend_ints__h645118 &
|
|
{ r1__read_BITS_12_TO_0___h645640, csrf_mideleg_1_0_reg } ;
|
|
assign fcsr_csr__read__h606094 = { 56'd0, x__h608768 } ;
|
|
assign fetchStage_RDY_pipelines_0_first__2592_AND_NOT_ETC___d13126 =
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 ;
|
|
assign fetchStage_RDY_pipelines_0_first__2592_AND_fet_ETC___d13193 =
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1 &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13188 ||
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
IF_fetchStage_RDY_pipelines_0_first__2592_AND__ETC___d13130 ;
|
|
assign fetchStage_RDY_pipelines_1_deq__2607_AND_NOT_f_ETC___d13690 =
|
|
fetchStage$RDY_pipelines_1_deq &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13686) &&
|
|
(fetchStage$pipelines_1_first[98:96] != 3'd1 ||
|
|
specTagManager$RDY_claimSpecTag) ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13710 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd0 ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1) &&
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_NOT_fe_ETC___d13783 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13707 &&
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13392 ||
|
|
!coreFix_aluExe_0_rsAlu$canEnq ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_fetchS_ETC___d13700 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13583 ||
|
|
!fetchStage$pipelines_1_canDeq ||
|
|
fetchStage$RDY_pipelines_1_first &&
|
|
(fetchStage_pipelines_1_first__2604_BITS_98_TO__ETC___d13594 ||
|
|
!regRenamingTable$rename_1_canRename ||
|
|
fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13599 ||
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13696) &&
|
|
IF_fetchStage_RDY_pipelines_1_first__2603_AND__ETC___d13528 ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13638 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd3 ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd4) ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13644 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13645 =
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13644 ||
|
|
!coreFix_memExe_rsMem$canEnq ||
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q230 ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13666 =
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13638 ||
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
|
|
fetchStage$pipelines_0_canDeq &&
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13659 ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13898 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13896 ||
|
|
!coreFix_memExe_rsMem$canEnq ||
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q230 ;
|
|
assign fetchStage_pipelines_0_canDeq__2593_AND_specTa_ETC___d13762 =
|
|
fetchStage$pipelines_0_canDeq && specTagManager$canClaim &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13200 =
|
|
fetchStage$pipelines_0_first[103:99] == 5'd0 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd21 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd17 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd18 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd13 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd16 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd15 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd19 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd20 ||
|
|
fetchStage$pipelines_0_first[4] ||
|
|
checkForException___d12829[4] ||
|
|
!rob$enqPort_0_canEnq ||
|
|
!epochManager$checkEpoch_0_check ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13404 =
|
|
fetchStage$pipelines_0_first[103:99] == 5'd0 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd21 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd17 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd18 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd13 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd16 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd15 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd19 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd20 ||
|
|
fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832 ||
|
|
!rob$enqPort_0_canEnq ||
|
|
!epochManager$checkEpoch_0_check ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13392 =
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd0 ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1) &&
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 &&
|
|
(!coreFix_aluExe_1_rsAlu$canEnq ||
|
|
coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139) ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13411 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13404 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd0 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13470 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13577 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13566 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13575 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13583 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13582 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13605 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13404 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd0 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 ||
|
|
coreFix_aluExe_1_rsAlu$canEnq &&
|
|
!coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13612 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13404 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd0 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 ||
|
|
coreFix_aluExe_0_rsAlu$canEnq &&
|
|
coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13659 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13200 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13658 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13670 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage_pipelines_0_first__2595_BITS_103_TO_ETC___d13200 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13669 ;
|
|
assign fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13789 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim ||
|
|
!regRenamingTable$rename_0_canRename ||
|
|
fetchStage$pipelines_0_first[4] ||
|
|
checkForException___d12829[4] ||
|
|
!rob$enqPort_0_canEnq ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd0 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 ;
|
|
assign fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832 =
|
|
fetchStage$pipelines_0_first[4] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[12] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[13] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[14] ||
|
|
checkForException___d12829[4] ;
|
|
assign fetchStage_pipelines_0_first__2595_BIT_77_2722_ETC___d12797 =
|
|
{ fetchStage$pipelines_0_first[77],
|
|
CASE_fetchStagepipelines_0_first_BITS_76_TO_6_ETC__q225 } ;
|
|
assign fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13432 =
|
|
fetchStage$pipelines_1_first[103:99] == 5'd0 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd21 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd17 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd18 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd13 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd16 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd15 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd19 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd20 ||
|
|
fetchStage_pipelines_1_first__2604_BIT_4_3249__ETC___d13427 ||
|
|
!rob$enqPort_1_canEnq ||
|
|
!epochManager$checkEpoch_1_check ||
|
|
!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
IF_fetchStage_RDY_pipelines_0_first__2592_AND__ETC___d13130 ;
|
|
assign fetchStage_pipelines_1_first__2604_BITS_103_TO_ETC___d13599 =
|
|
fetchStage$pipelines_1_first[103:99] == 5'd0 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd21 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd17 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd18 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd13 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd16 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd15 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd19 ||
|
|
fetchStage$pipelines_1_first[103:99] == 5'd20 ||
|
|
fetchStage$pipelines_1_first[4] ||
|
|
checkForException___d13372[4] ||
|
|
!rob$enqPort_1_canEnq ||
|
|
!epochManager$checkEpoch_1_check ||
|
|
fetchStage$pipelines_0_canDeq &&
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13583 ;
|
|
assign fetchStage_pipelines_1_first__2604_BITS_98_TO__ETC___d13594 =
|
|
fetchStage$pipelines_1_first[98:96] == 3'd1 &&
|
|
(fetchStage$pipelines_0_canDeq &&
|
|
regRenamingTable_rename_0_canRename__3102_AND__ETC___d13591 ||
|
|
!specTagManager$canClaim) ;
|
|
assign fetchStage_pipelines_1_first__2604_BIT_4_3249__ETC___d13427 =
|
|
fetchStage$pipelines_1_first[4] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[0] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[1] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[2] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[3] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[4] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[5] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[6] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[7] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[8] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[9] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[10] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[11] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[12] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[13] ||
|
|
IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3_2624_26_ETC___d12664[14] ||
|
|
checkForException___d13372[4] ;
|
|
assign fetchStage_pipelines_1_first__2604_BIT_77_3276_ETC___d13351 =
|
|
{ fetchStage$pipelines_1_first[77],
|
|
CASE_fetchStagepipelines_1_first_BITS_76_TO_6_ETC__q228 } ;
|
|
assign fflags__h702055 =
|
|
NOT_rob_deqPort_0_canDeq__4362_4363_OR_rob_deq_ETC___d14454 ?
|
|
y_avValue_snd_fst__h702081 :
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14460 ;
|
|
assign fflags_csr__read__h606069 = { 59'd0, csrf_fflags_reg } ;
|
|
assign frm_csr__read__h606080 = { 61'd0, csrf_frm_reg } ;
|
|
assign guard__h343259 =
|
|
{ IF_sfdin51354_BIT_33_THEN_2_ELSE_0__q21[1],
|
|
{ sfdin__h351354[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h351968 =
|
|
{ IF_theResult___snd59967_BIT_33_THEN_2_ELSE_0__q23[1],
|
|
{ _theResult___snd__h359967[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h360898 =
|
|
{ IF_sfdin69120_BIT_33_THEN_2_ELSE_0__q31[1],
|
|
{ sfdin__h369120[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h361496 = x__h361598 != 57'd0 ;
|
|
assign guard__h369734 =
|
|
{ IF_theResult___snd77757_BIT_33_THEN_2_ELSE_0__q36[1],
|
|
{ _theResult___snd__h377757[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h388951 =
|
|
{ IF_sfdin97044_BIT_33_THEN_2_ELSE_0__q56[1],
|
|
{ sfdin__h397044[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h397658 =
|
|
{ IF_theResult___snd05657_BIT_33_THEN_2_ELSE_0__q58[1],
|
|
{ _theResult___snd__h405657[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h406588 =
|
|
{ IF_sfdin14810_BIT_33_THEN_2_ELSE_0__q66[1],
|
|
{ sfdin__h414810[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h407186 = x__h407288 != 57'd0 ;
|
|
assign guard__h415424 =
|
|
{ IF_theResult___snd23447_BIT_33_THEN_2_ELSE_0__q71[1],
|
|
{ _theResult___snd__h423447[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h434639 =
|
|
{ IF_sfdin42732_BIT_33_THEN_2_ELSE_0__q91[1],
|
|
{ sfdin__h442732[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h443346 =
|
|
{ IF_theResult___snd51345_BIT_33_THEN_2_ELSE_0__q93[1],
|
|
{ _theResult___snd__h451345[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h452276 =
|
|
{ IF_sfdin60498_BIT_33_THEN_2_ELSE_0__q101[1],
|
|
{ sfdin__h460498[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h452874 = x__h452976 != 57'd0 ;
|
|
assign guard__h461112 =
|
|
{ IF_theResult___snd69135_BIT_33_THEN_2_ELSE_0__q106[1],
|
|
{ _theResult___snd__h469135[32:0], 23'd0 } != 56'd0 } ;
|
|
assign guard__h490662 =
|
|
{ IF_theResult___snd98574_BIT_4_THEN_2_ELSE_0__q127[1],
|
|
{ _theResult___snd__h498574[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h499974 =
|
|
{ IF_sfdin08194_BIT_4_THEN_2_ELSE_0__q131[1],
|
|
{ sfdin__h508194[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h500572 = x__h500672 != 57'd0 ;
|
|
assign guard__h509043 =
|
|
{ IF_theResult___snd16979_BIT_4_THEN_2_ELSE_0__q134[1],
|
|
{ _theResult___snd__h516979[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h529463 =
|
|
{ IF_theResult___snd37375_BIT_4_THEN_2_ELSE_0__q167[1],
|
|
{ _theResult___snd__h537375[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h538775 =
|
|
{ IF_sfdin46995_BIT_4_THEN_2_ELSE_0__q171[1],
|
|
{ sfdin__h546995[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h539373 = x__h539473 != 57'd0 ;
|
|
assign guard__h547844 =
|
|
{ IF_theResult___snd55780_BIT_4_THEN_2_ELSE_0__q174[1],
|
|
{ _theResult___snd__h555780[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h568664 =
|
|
{ IF_theResult___snd76576_BIT_4_THEN_2_ELSE_0__q144[1],
|
|
{ _theResult___snd__h576576[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h577976 =
|
|
{ IF_sfdin86196_BIT_4_THEN_2_ELSE_0__q148[1],
|
|
{ sfdin__h586196[3:0], 52'd0 } != 56'd0 } ;
|
|
assign guard__h578574 = x__h578674 != 57'd0 ;
|
|
assign guard__h587045 =
|
|
{ IF_theResult___snd94981_BIT_4_THEN_2_ELSE_0__q151[1],
|
|
{ _theResult___snd__h594981[3:0], 52'd0 } != 56'd0 } ;
|
|
assign idx__h673066 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13393 ||
|
|
!coreFix_aluExe_0_rsAlu$canEnq ||
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13411) &&
|
|
coreFix_aluExe_1_rsAlu$canEnq &&
|
|
!coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139 ;
|
|
assign k__h659336 =
|
|
!coreFix_aluExe_0_rsAlu$canEnq ||
|
|
coreFix_aluExe_1_rsAlu$canEnq &&
|
|
!coreFix_aluExe_0_rsAlu_approximateCount__3137__ETC___d13139 ;
|
|
assign mcause_csr__read__h607741 =
|
|
{ r1__read__h610292, csrf_mcause_code_reg } ;
|
|
assign mcounteren_csr__read__h607486 =
|
|
{ r1__read__h610279, csrf_mcounteren_cy_reg } ;
|
|
assign medeleg_csr__read__h607086 =
|
|
{ r1__read__h610115, csrf_medeleg_9_0_reg } ;
|
|
assign mideleg_csr__read__h607181 =
|
|
{ r1__read__h610132, csrf_mideleg_1_0_reg } ;
|
|
assign mie_csr__read__h607312 =
|
|
{ r1__read__h610156, csrf_software_int_en_vec_0 } ;
|
|
assign mip_csr__read__h607981 =
|
|
{ r1__read__h610298, csrf_software_int_pend_vec_0 } ;
|
|
assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 =
|
|
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ||
|
|
(!mmio_cRqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) &&
|
|
mmio_cRqQ_full ;
|
|
assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 =
|
|
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ||
|
|
(!mmio_cRsQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) &&
|
|
mmio_cRsQ_full ;
|
|
assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 =
|
|
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT &&
|
|
(mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) ||
|
|
(!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT ||
|
|
!mmio_dataRespQ_deqReq_lat_0$whas &&
|
|
!mmio_dataPendQ_deqReq_rl) &&
|
|
mmio_dataPendQ_full ;
|
|
assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 =
|
|
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ||
|
|
(!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) &&
|
|
mmio_dataReqQ_full ;
|
|
assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 =
|
|
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ||
|
|
(!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT ||
|
|
!mmio_dataRespQ_deqReq_lat_0$whas &&
|
|
!mmio_dataRespQ_deqReq_rl) &&
|
|
mmio_dataRespQ_full ;
|
|
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13065 =
|
|
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BIT_4_2_ETC___d13046 &&
|
|
(fetchStage$pipelines_0_first[103:99] == 5'd0 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd21 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd17 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd18 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd13 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd16 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd15 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd19 ||
|
|
fetchStage$pipelines_0_first[103:99] == 5'd20) ;
|
|
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13704 =
|
|
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BIT_4_2_ETC___d13046 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd0 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd21 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd17 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd18 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd13 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd16 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd15 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd19 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd20 ;
|
|
assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 =
|
|
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ||
|
|
(!mmio_pRqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) &&
|
|
mmio_pRqQ_full ;
|
|
assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 =
|
|
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ||
|
|
(!mmio_pRsQ_deqReq_dummy2_2$Q_OUT ||
|
|
!mmio_pRsQ_deqReq_dummy_2_0$wget && !mmio_pRsQ_deqReq_rl) &&
|
|
mmio_pRsQ_full ;
|
|
assign msip__h75375 = csrf_software_int_pend_vec_3 ;
|
|
assign mstatus_csr__read__h606938 = { r1__read__h609994, csrf_ie_vec_0 } ;
|
|
assign mtvec_csr__read__h607394 =
|
|
{ r1__read__h610274, csrf_mtvec_mode_low_reg } ;
|
|
assign n___1__h195697 =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] :
|
|
x__h194294[63:56],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] :
|
|
x__h194294[55:48],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] :
|
|
x__h194294[47:40],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] :
|
|
x__h194294[39:32],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] :
|
|
x__h194294[31:24],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] :
|
|
x__h194294[23:16],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] :
|
|
x__h194294[15:8],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] :
|
|
x__h194294[7:0] } ;
|
|
assign n__read__h608085 =
|
|
(csrf_mcycle_ehr_data_dummy2_0$Q_OUT &&
|
|
csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ?
|
|
csrf_mcycle_ehr_data_rl :
|
|
64'd0 ;
|
|
assign n__read__h608276 =
|
|
(csrf_minstret_ehr_data_dummy2_0$Q_OUT &&
|
|
csrf_minstret_ehr_data_dummy2_1$Q_OUT) ?
|
|
csrf_minstret_ehr_data_rl :
|
|
64'd0 ;
|
|
assign n__read__h6133 =
|
|
csrf_mcycle_ehr_data_dummy2_1$Q_OUT ?
|
|
(csrf_mcycle_ehr_data_lat_0$whas ?
|
|
rob$deqPort_0_deq_data[95:32] :
|
|
csrf_mcycle_ehr_data_rl) :
|
|
64'd0 ;
|
|
assign n__read__h699967 =
|
|
csrf_minstret_ehr_data_dummy2_1$Q_OUT ?
|
|
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 :
|
|
64'd0 ;
|
|
assign next_deqP___1__h293968 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ==
|
|
3'd7) ?
|
|
3'd0 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP +
|
|
3'd1 ;
|
|
assign next_deqP___1__h301964 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h308245 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h316099 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h326156 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ;
|
|
assign next_deqP___1__h329381 = coreFix_memExe_forwardQ_deqP + 1'd1 ;
|
|
assign next_pc__h699310 =
|
|
(rob$deqPort_0_deq_data[97:96] == 2'd0) ?
|
|
rob$deqPort_0_deq_data[95:32] :
|
|
rob$deqPort_0_deq_data[186:123] + 64'd4 ;
|
|
assign out___1_sfd__h479325 =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[162:140], 29'd0 } ;
|
|
assign out___1_sfd__h518267 =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[98:76], 29'd0 } ;
|
|
assign out___1_sfd__h557468 =
|
|
{ coreFix_fpuMulDivExe_0_regToExeQ$first[34:12], 29'd0 } ;
|
|
assign out_exp__h351879 =
|
|
sfdin__h351354[34] ?
|
|
_theResult___exp__h351876 :
|
|
_theResult___fst_exp__h351360 ;
|
|
assign out_exp__h360461 =
|
|
_theResult___snd__h359967[34] ?
|
|
_theResult___exp__h360458 :
|
|
_theResult___fst_exp__h360016 ;
|
|
assign out_exp__h369645 =
|
|
sfdin__h369120[34] ?
|
|
_theResult___exp__h369642 :
|
|
_theResult___fst_exp__h369126 ;
|
|
assign out_exp__h378281 =
|
|
_theResult___snd__h377757[34] ?
|
|
_theResult___exp__h378278 :
|
|
_theResult___fst_exp__h377811 ;
|
|
assign out_exp__h397569 =
|
|
sfdin__h397044[34] ?
|
|
_theResult___exp__h397566 :
|
|
_theResult___fst_exp__h397050 ;
|
|
assign out_exp__h406151 =
|
|
_theResult___snd__h405657[34] ?
|
|
_theResult___exp__h406148 :
|
|
_theResult___fst_exp__h405706 ;
|
|
assign out_exp__h415335 =
|
|
sfdin__h414810[34] ?
|
|
_theResult___exp__h415332 :
|
|
_theResult___fst_exp__h414816 ;
|
|
assign out_exp__h423971 =
|
|
_theResult___snd__h423447[34] ?
|
|
_theResult___exp__h423968 :
|
|
_theResult___fst_exp__h423501 ;
|
|
assign out_exp__h443257 =
|
|
sfdin__h442732[34] ?
|
|
_theResult___exp__h443254 :
|
|
_theResult___fst_exp__h442738 ;
|
|
assign out_exp__h451839 =
|
|
_theResult___snd__h451345[34] ?
|
|
_theResult___exp__h451836 :
|
|
_theResult___fst_exp__h451394 ;
|
|
assign out_exp__h461023 =
|
|
sfdin__h460498[34] ?
|
|
_theResult___exp__h461020 :
|
|
_theResult___fst_exp__h460504 ;
|
|
assign out_exp__h469659 =
|
|
_theResult___snd__h469135[34] ?
|
|
_theResult___exp__h469656 :
|
|
_theResult___fst_exp__h469189 ;
|
|
assign out_exp__h499281 =
|
|
_theResult___snd__h498574[5] ?
|
|
_theResult___exp__h499278 :
|
|
_theResult___fst_exp__h498623 ;
|
|
assign out_exp__h508932 =
|
|
sfdin__h508194[5] ?
|
|
_theResult___exp__h508929 :
|
|
_theResult___fst_exp__h508200 ;
|
|
assign out_exp__h517716 =
|
|
_theResult___snd__h516979[5] ?
|
|
_theResult___exp__h517713 :
|
|
_theResult___fst_exp__h517033 ;
|
|
assign out_exp__h538082 =
|
|
_theResult___snd__h537375[5] ?
|
|
_theResult___exp__h538079 :
|
|
_theResult___fst_exp__h537424 ;
|
|
assign out_exp__h547733 =
|
|
sfdin__h546995[5] ?
|
|
_theResult___exp__h547730 :
|
|
_theResult___fst_exp__h547001 ;
|
|
assign out_exp__h556517 =
|
|
_theResult___snd__h555780[5] ?
|
|
_theResult___exp__h556514 :
|
|
_theResult___fst_exp__h555834 ;
|
|
assign out_exp__h577283 =
|
|
_theResult___snd__h576576[5] ?
|
|
_theResult___exp__h577280 :
|
|
_theResult___fst_exp__h576625 ;
|
|
assign out_exp__h586934 =
|
|
sfdin__h586196[5] ?
|
|
_theResult___exp__h586931 :
|
|
_theResult___fst_exp__h586202 ;
|
|
assign out_exp__h595718 =
|
|
_theResult___snd__h594981[5] ?
|
|
_theResult___exp__h595715 :
|
|
_theResult___fst_exp__h595035 ;
|
|
assign out_f_exp__h378657 =
|
|
(_theResult___exp__h378380 == 8'd255 &&
|
|
_theResult___sfd__h378381 != 23'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047) ?
|
|
8'd255 :
|
|
_theResult___fst_exp__h378371 ;
|
|
assign out_f_exp__h424347 =
|
|
(_theResult___exp__h424070 == 8'd255 &&
|
|
_theResult___sfd__h424071 != 23'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047) ?
|
|
8'd255 :
|
|
_theResult___fst_exp__h424061 ;
|
|
assign out_f_exp__h470035 =
|
|
(_theResult___exp__h469758 == 8'd255 &&
|
|
_theResult___sfd__h469759 != 23'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047) ?
|
|
8'd255 :
|
|
_theResult___fst_exp__h469749 ;
|
|
assign out_f_sfd__h378658 =
|
|
(_theResult___exp__h378380 == 8'd255 &&
|
|
_theResult___sfd__h378381 != 23'd0) ?
|
|
23'd4194304 :
|
|
_theResult___sfd__h378381 ;
|
|
assign out_f_sfd__h424348 =
|
|
(_theResult___exp__h424070 == 8'd255 &&
|
|
_theResult___sfd__h424071 != 23'd0) ?
|
|
23'd4194304 :
|
|
_theResult___sfd__h424071 ;
|
|
assign out_f_sfd__h470036 =
|
|
(_theResult___exp__h469758 == 8'd255 &&
|
|
_theResult___sfd__h469759 != 23'd0) ?
|
|
23'd4194304 :
|
|
_theResult___sfd__h469759 ;
|
|
assign out_sfd__h351880 =
|
|
sfdin__h351354[34] ?
|
|
_theResult___sfd__h351877 :
|
|
sfdin__h351354[56:34] ;
|
|
assign out_sfd__h360462 =
|
|
_theResult___snd__h359967[34] ?
|
|
_theResult___sfd__h360459 :
|
|
_theResult___snd__h359967[56:34] ;
|
|
assign out_sfd__h369646 =
|
|
sfdin__h369120[34] ?
|
|
_theResult___sfd__h369643 :
|
|
sfdin__h369120[56:34] ;
|
|
assign out_sfd__h378282 =
|
|
_theResult___snd__h377757[34] ?
|
|
_theResult___sfd__h378279 :
|
|
_theResult___snd__h377757[56:34] ;
|
|
assign out_sfd__h397570 =
|
|
sfdin__h397044[34] ?
|
|
_theResult___sfd__h397567 :
|
|
sfdin__h397044[56:34] ;
|
|
assign out_sfd__h406152 =
|
|
_theResult___snd__h405657[34] ?
|
|
_theResult___sfd__h406149 :
|
|
_theResult___snd__h405657[56:34] ;
|
|
assign out_sfd__h415336 =
|
|
sfdin__h414810[34] ?
|
|
_theResult___sfd__h415333 :
|
|
sfdin__h414810[56:34] ;
|
|
assign out_sfd__h423972 =
|
|
_theResult___snd__h423447[34] ?
|
|
_theResult___sfd__h423969 :
|
|
_theResult___snd__h423447[56:34] ;
|
|
assign out_sfd__h443258 =
|
|
sfdin__h442732[34] ?
|
|
_theResult___sfd__h443255 :
|
|
sfdin__h442732[56:34] ;
|
|
assign out_sfd__h451840 =
|
|
_theResult___snd__h451345[34] ?
|
|
_theResult___sfd__h451837 :
|
|
_theResult___snd__h451345[56:34] ;
|
|
assign out_sfd__h461024 =
|
|
sfdin__h460498[34] ?
|
|
_theResult___sfd__h461021 :
|
|
sfdin__h460498[56:34] ;
|
|
assign out_sfd__h469660 =
|
|
_theResult___snd__h469135[34] ?
|
|
_theResult___sfd__h469657 :
|
|
_theResult___snd__h469135[56:34] ;
|
|
assign out_sfd__h499282 =
|
|
_theResult___snd__h498574[5] ?
|
|
_theResult___sfd__h499279 :
|
|
_theResult___snd__h498574[56:5] ;
|
|
assign out_sfd__h508933 =
|
|
sfdin__h508194[5] ?
|
|
_theResult___sfd__h508930 :
|
|
sfdin__h508194[56:5] ;
|
|
assign out_sfd__h517717 =
|
|
_theResult___snd__h516979[5] ?
|
|
_theResult___sfd__h517714 :
|
|
_theResult___snd__h516979[56:5] ;
|
|
assign out_sfd__h538083 =
|
|
_theResult___snd__h537375[5] ?
|
|
_theResult___sfd__h538080 :
|
|
_theResult___snd__h537375[56:5] ;
|
|
assign out_sfd__h547734 =
|
|
sfdin__h546995[5] ?
|
|
_theResult___sfd__h547731 :
|
|
sfdin__h546995[56:5] ;
|
|
assign out_sfd__h556518 =
|
|
_theResult___snd__h555780[5] ?
|
|
_theResult___sfd__h556515 :
|
|
_theResult___snd__h555780[56:5] ;
|
|
assign out_sfd__h577284 =
|
|
_theResult___snd__h576576[5] ?
|
|
_theResult___sfd__h577281 :
|
|
_theResult___snd__h576576[56:5] ;
|
|
assign out_sfd__h586935 =
|
|
sfdin__h586196[5] ?
|
|
_theResult___sfd__h586932 :
|
|
sfdin__h586196[56:5] ;
|
|
assign out_sfd__h595719 =
|
|
_theResult___snd__h594981[5] ?
|
|
_theResult___sfd__h595716 :
|
|
_theResult___snd__h594981[56:5] ;
|
|
assign pend_ints__h645118 =
|
|
{ csrf_debug_int_pend_read__1643_CONCAT_0b0_2627_ETC___d12637,
|
|
csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3,
|
|
1'd0,
|
|
csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1,
|
|
csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ;
|
|
assign prv__h703535 = csrf_prv_reg ;
|
|
assign prv__h703579 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ;
|
|
assign q___1__h473027 =
|
|
64'd0 -
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ;
|
|
assign r1__read_BITS_12_TO_0___h645640 =
|
|
{ 3'd0,
|
|
csrf_mideleg_11_reg,
|
|
1'b0,
|
|
csrf_mideleg_9_7_reg,
|
|
1'b0,
|
|
csrf_mideleg_5_3_reg,
|
|
1'b0 } ;
|
|
assign r1__read__h608783 = { r1__read__h608785, csrf_ie_vec_1 } ;
|
|
assign r1__read__h608785 = { r1__read__h608787, 2'b0 } ;
|
|
assign r1__read__h608787 = { r1__read__h608789, csrf_prev_ie_vec_0 } ;
|
|
assign r1__read__h608789 = { r1__read__h608791, csrf_prev_ie_vec_1 } ;
|
|
assign r1__read__h608791 = { r1__read__h608793, 2'b0 } ;
|
|
assign r1__read__h608793 = { r1__read__h608795, csrf_spp_reg } ;
|
|
assign r1__read__h608795 = { r1__read__h608797, 4'b0 } ;
|
|
assign r1__read__h608797 = { r1__read__h608799, csrf_fs_reg } ;
|
|
assign r1__read__h608799 = { r1__read__h608801, 2'd0 } ;
|
|
assign r1__read__h608801 = { r1__read__h608803, 1'b0 } ;
|
|
assign r1__read__h608803 = { r1__read__h608805, csrf_sum_reg } ;
|
|
assign r1__read__h608805 = { r1__read__h608807, csrf_mxr_reg } ;
|
|
assign r1__read__h608807 = { r1__read__h608809, 12'b0 } ;
|
|
assign r1__read__h608809 = { r1__read__h608811, 2'b10 } ;
|
|
assign r1__read__h608811 = { r__h608815, 29'b0 } ;
|
|
assign r1__read__h609187 =
|
|
{ r1__read__h609189, csrf_software_int_en_vec_1 } ;
|
|
assign r1__read__h609189 = { r1__read__h609191, 2'b0 } ;
|
|
assign r1__read__h609191 = { r1__read__h609193, csrf_timer_int_en_vec_0 } ;
|
|
assign r1__read__h609193 = { r1__read__h609195, csrf_timer_int_en_vec_1 } ;
|
|
assign r1__read__h609195 = { r1__read__h609197, 2'b0 } ;
|
|
assign r1__read__h609197 =
|
|
{ r1__read__h609199, csrf_external_int_en_vec_0 } ;
|
|
assign r1__read__h609199 = { 54'b0, csrf_external_int_en_vec_1 } ;
|
|
assign r1__read__h609717 = { csrf_stvec_base_hi_reg, 1'b0 } ;
|
|
assign r1__read__h609722 = { r1__read__h609724, csrf_scounteren_tm_reg } ;
|
|
assign r1__read__h609724 = { 61'd0, csrf_scounteren_ir_reg } ;
|
|
assign r1__read__h609735 = { csrf_scause_interrupt_reg, 59'b0 } ;
|
|
assign r1__read__h609741 =
|
|
{ r1__read__h609743, csrf_software_int_pend_vec_1 } ;
|
|
assign r1__read__h609743 = { r1__read__h609745, 2'b0 } ;
|
|
assign r1__read__h609745 =
|
|
{ r1__read__h609747, csrf_timer_int_pend_vec_0 } ;
|
|
assign r1__read__h609747 =
|
|
{ r1__read__h609749, csrf_timer_int_pend_vec_1 } ;
|
|
assign r1__read__h609749 = { r1__read__h609751, 2'b0 } ;
|
|
assign r1__read__h609751 =
|
|
{ r1__read__h609753, csrf_external_int_pend_vec_0 } ;
|
|
assign r1__read__h609753 = { 54'b0, csrf_external_int_pend_vec_1 } ;
|
|
assign r1__read__h609971 = { vm_mode_reg__read__h609977, 16'd0 } ;
|
|
assign r1__read__h609994 = { r1__read__h609996, csrf_ie_vec_1 } ;
|
|
assign r1__read__h609996 = { r1__read__h609998, 1'b0 } ;
|
|
assign r1__read__h609998 = { r1__read__h610000, csrf_ie_vec_3 } ;
|
|
assign r1__read__h610000 = { r1__read__h610002, csrf_prev_ie_vec_0 } ;
|
|
assign r1__read__h610002 = { r1__read__h610004, csrf_prev_ie_vec_1 } ;
|
|
assign r1__read__h610004 = { r1__read__h610006, 1'b0 } ;
|
|
assign r1__read__h610006 = { r1__read__h610008, csrf_prev_ie_vec_3 } ;
|
|
assign r1__read__h610008 = { r1__read__h610010, csrf_spp_reg } ;
|
|
assign r1__read__h610010 = { r1__read__h610012, 2'b0 } ;
|
|
assign r1__read__h610012 = { r1__read__h610014, csrf_mpp_reg } ;
|
|
assign r1__read__h610014 = { r1__read__h610016, csrf_fs_reg } ;
|
|
assign r1__read__h610016 = { r1__read__h610018, 2'd0 } ;
|
|
assign r1__read__h610018 = { r1__read__h610020, csrf_mprv_reg } ;
|
|
assign r1__read__h610020 = { r1__read__h610022, csrf_sum_reg } ;
|
|
assign r1__read__h610022 = { r1__read__h610024, csrf_mxr_reg } ;
|
|
assign r1__read__h610024 = { r1__read__h610026, csrf_tvm_reg } ;
|
|
assign r1__read__h610026 = { r1__read__h610028, csrf_tw_reg } ;
|
|
assign r1__read__h610028 = { r1__read__h610030, csrf_tsr_reg } ;
|
|
assign r1__read__h610030 = { r1__read__h610032, 9'b0 } ;
|
|
assign r1__read__h610032 = { r1__read__h610034, 2'b10 } ;
|
|
assign r1__read__h610034 = { r1__read__h610036, 2'b10 } ;
|
|
assign r1__read__h610036 = { r__h608815, 27'b0 } ;
|
|
assign r1__read__h610115 = { r1__read__h610117, 1'b0 } ;
|
|
assign r1__read__h610117 = { r1__read__h610119, csrf_medeleg_13_11_reg } ;
|
|
assign r1__read__h610119 = { r1__read__h610121, 1'b0 } ;
|
|
assign r1__read__h610121 = { 48'b0, csrf_medeleg_15_reg } ;
|
|
assign r1__read__h610132 = { r1__read__h610134, 1'b0 } ;
|
|
assign r1__read__h610134 = { r1__read__h610136, csrf_mideleg_5_3_reg } ;
|
|
assign r1__read__h610136 = { r1__read__h610138, 1'b0 } ;
|
|
assign r1__read__h610138 = { r1__read__h610140, csrf_mideleg_9_7_reg } ;
|
|
assign r1__read__h610140 = { r1__read__h610142, 1'b0 } ;
|
|
assign r1__read__h610142 = { 52'b0, csrf_mideleg_11_reg } ;
|
|
assign r1__read__h610156 =
|
|
{ r1__read__h610158, csrf_software_int_en_vec_1 } ;
|
|
assign r1__read__h610158 = { r1__read__h610160, 1'b0 } ;
|
|
assign r1__read__h610160 =
|
|
{ r1__read__h610162, csrf_software_int_en_vec_3 } ;
|
|
assign r1__read__h610162 = { r1__read__h610164, csrf_timer_int_en_vec_0 } ;
|
|
assign r1__read__h610164 = { r1__read__h610166, csrf_timer_int_en_vec_1 } ;
|
|
assign r1__read__h610166 = { r1__read__h610168, 1'b0 } ;
|
|
assign r1__read__h610168 = { r1__read__h610170, csrf_timer_int_en_vec_3 } ;
|
|
assign r1__read__h610170 =
|
|
{ r1__read__h610172, csrf_external_int_en_vec_0 } ;
|
|
assign r1__read__h610172 =
|
|
{ r1__read__h610174, csrf_external_int_en_vec_1 } ;
|
|
assign r1__read__h610174 = { r1__read__h610176, 1'b0 } ;
|
|
assign r1__read__h610176 = { 52'd4, csrf_external_int_en_vec_3 } ;
|
|
assign r1__read__h610274 = { csrf_mtvec_base_hi_reg, 1'b0 } ;
|
|
assign r1__read__h610279 = { r1__read__h610281, csrf_mcounteren_tm_reg } ;
|
|
assign r1__read__h610281 = { 61'd0, csrf_mcounteren_ir_reg } ;
|
|
assign r1__read__h610292 = { csrf_mcause_interrupt_reg, 59'b0 } ;
|
|
assign r1__read__h610298 =
|
|
{ r1__read__h610300, csrf_software_int_pend_vec_1 } ;
|
|
assign r1__read__h610300 = { r1__read__h610302, 1'b0 } ;
|
|
assign r1__read__h610302 =
|
|
{ r1__read__h610304, csrf_software_int_pend_vec_3 } ;
|
|
assign r1__read__h610304 =
|
|
{ r1__read__h610306, csrf_timer_int_pend_vec_0 } ;
|
|
assign r1__read__h610306 =
|
|
{ r1__read__h610308, csrf_timer_int_pend_vec_1 } ;
|
|
assign r1__read__h610308 = { r1__read__h610310, 1'b0 } ;
|
|
assign r1__read__h610310 =
|
|
{ r1__read__h610312, csrf_timer_int_pend_vec_3 } ;
|
|
assign r1__read__h610312 =
|
|
{ r1__read__h610314, csrf_external_int_pend_vec_0 } ;
|
|
assign r1__read__h610314 =
|
|
{ r1__read__h610316, csrf_external_int_pend_vec_1 } ;
|
|
assign r1__read__h610316 = { r1__read__h610318, 1'b0 } ;
|
|
assign r1__read__h610318 =
|
|
{ r1__read__h610320, csrf_external_int_pend_vec_3 } ;
|
|
assign r1__read__h610320 = { r1__read__h610322, 2'b0 } ;
|
|
assign r1__read__h610322 = { 49'b0, csrf_debug_int_pend } ;
|
|
assign rVal1__h478908 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
|
|
assign rVal2__h478909 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
|
|
assign r___1__h473053 =
|
|
64'd0 -
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ;
|
|
assign r__h608815 = csrf_fs_reg == 2'b11 ;
|
|
assign regRenamingTable_RDY_rename_0_getRename__3034__ETC___d13562 =
|
|
regRenamingTable$RDY_rename_0_getRename &&
|
|
CASE_fetchStagepipelines_0_first_BITS_95_TO_9_ETC__q233 &&
|
|
(fetchStage$pipelines_0_first[103:99] == 5'd14 ||
|
|
coreFix_memExe_rsMem$RDY_enq) ;
|
|
assign regRenamingTable_RDY_rename_1_getRename__3618__ETC___d13636 =
|
|
regRenamingTable$RDY_rename_1_getRename &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_specTagManager_canClaim__3100_3187_OR_NOT__ETC___d13621) &&
|
|
_0_OR_NOT_fetchStage_pipelines_1_first__2604_BI_ETC___d13634 ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13188 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 ||
|
|
!specTagManager$canClaim ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13443 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd3 ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd4) ||
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13455 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13173 &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 ||
|
|
!coreFix_memExe_rsMem$canEnq ||
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q230 ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13591 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13589 &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13722 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd3 ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd4) &&
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13728 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 &&
|
|
fetchStage$pipelines_0_first[103:99] != 5'd14 ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13748 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 &&
|
|
(fetchStage$pipelines_0_first[95:93] == 3'd0 ||
|
|
fetchStage$pipelines_0_first[95:93] == 3'd2) ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13756 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 &&
|
|
fetchStage$pipelines_0_first[95:93] != 3'd0 &&
|
|
fetchStage$pipelines_0_first[95:93] != 3'd2 ;
|
|
assign regRenamingTable_rename_0_canRename__3102_AND__ETC___d13896 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
!checkForException___d12829[4] &&
|
|
rob$enqPort_0_canEnq &&
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 ;
|
|
assign regRenamingTable_rename_1_canRename__3221_AND__ETC___d13850 =
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13805 &&
|
|
(fetchStage$pipelines_1_first[98:96] == 3'd3 ||
|
|
fetchStage$pipelines_1_first[98:96] == 3'd4) &&
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
NOT_regRenamingTable_rename_0_canRename__3102__ETC___d13542 ||
|
|
fetchStage$pipelines_0_first[98:96] != 3'd3 &&
|
|
fetchStage$pipelines_0_first[98:96] != 3'd4) &&
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
|
|
assign renaming_spec_bits__h672935 =
|
|
fetchStage$pipelines_0_canDeq ?
|
|
y_avValue_snd_fst__h670400 :
|
|
specTagManager$currentSpecBits ;
|
|
assign res_data__h335036 = { 32'd0, x__h335048 } ;
|
|
assign res_data__h335041 =
|
|
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ^
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68],
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) ?
|
|
63'h7FF8000000000000 :
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ;
|
|
assign res_data__h380731 = { 32'd0, x__h380743 } ;
|
|
assign res_data__h380736 =
|
|
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ^
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68],
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) ?
|
|
63'h7FF8000000000000 :
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ;
|
|
assign res_data__h426419 = { 32'd0, x__h426431 } ;
|
|
assign res_data__h426424 =
|
|
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ^
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68],
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
|
|
11'd2047 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) ?
|
|
63'h7FF8000000000000 :
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ;
|
|
assign res_fflags__h335037 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] |
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] |
|
|
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5194,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5205,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5221,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5234,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5247 } ;
|
|
assign res_fflags__h380732 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] |
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] |
|
|
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6586,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6597,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6613,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6626,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6639 } ;
|
|
assign res_fflags__h426420 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] |
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] |
|
|
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7978,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7989,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8005,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8018,
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd2047 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd0 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
|
|
52'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8031 } ;
|
|
assign resp_addr__h289138 =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ;
|
|
assign result__h361501 =
|
|
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4550[56:1],
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4550[0] |
|
|
guard__h361496 } ;
|
|
assign result__h407191 =
|
|
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5942[56:1],
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5942[0] |
|
|
guard__h407186 } ;
|
|
assign result__h452879 =
|
|
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7334[56:1],
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7334[0] |
|
|
guard__h452874 } ;
|
|
assign result__h500577 =
|
|
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8641[56:1],
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d8641[0] |
|
|
guard__h500572 } ;
|
|
assign result__h539378 =
|
|
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10114[56:1],
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d10114[0] |
|
|
guard__h539373 } ;
|
|
assign result__h578579 =
|
|
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9351[56:1],
|
|
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_regToExe_ETC___d9351[0] |
|
|
guard__h578574 } ;
|
|
assign result__h640846 = w__h640841 & y__h640875 ;
|
|
assign result__h640897 = ~x__h640896 ;
|
|
assign rob_RDY_enqPort_0_enq__2617_AND_regRenamingTab_ETC___d13042 =
|
|
rob$RDY_enqPort_0_enq &&
|
|
regRenamingTable$RDY_rename_0_claimRename &&
|
|
regRenamingTable$RDY_rename_0_getRename &&
|
|
fetchStage$RDY_pipelines_0_first &&
|
|
fetchStage$RDY_pipelines_0_deq &&
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd0 ||
|
|
coreFix_aluExe_0_rsAlu$RDY_enq) ;
|
|
assign robdeqPort_0_deq_data_BITS_95_TO_32__q261 =
|
|
rob$deqPort_0_deq_data[95:32] ;
|
|
assign satp_csr__read__h606795 = { r1__read__h609971, csrf_ppn_reg } ;
|
|
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8287 =
|
|
(sbCons$lazyLookup_2_get[2] ||
|
|
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8243 &&
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8260) &&
|
|
(sbCons$lazyLookup_2_get[1] ||
|
|
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8267 &&
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8284) ;
|
|
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8288 =
|
|
(sbCons$lazyLookup_2_get[3] ||
|
|
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8210 &&
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8236) &&
|
|
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8287 ;
|
|
assign sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 =
|
|
(sbCons$lazyLookup_3_get[3] ||
|
|
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 &&
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604) &&
|
|
(sbCons$lazyLookup_3_get[2] ||
|
|
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 &&
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ;
|
|
assign sbIdx__h156274 =
|
|
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
|
|
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
|
|
coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] :
|
|
coreFix_memExe_reqStQ_data_0_rl[65:64]) :
|
|
2'd0 ;
|
|
assign scause_csr__read__h606593 =
|
|
{ r1__read__h609735, csrf_scause_code_reg } ;
|
|
assign scounteren_csr__read__h606455 =
|
|
{ r1__read__h609722, csrf_scounteren_cy_reg } ;
|
|
assign sfd__h335644 = { value__h343871, 3'd0 } ;
|
|
assign sfd__h351452 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h351360 != 8'd0,
|
|
sfdin__h351354[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h360034 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h360016 != 8'd0,
|
|
_theResult___snd__h359967[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h369218 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h369126 != 8'd0,
|
|
sfdin__h369120[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h377830 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h377811 != 8'd0,
|
|
_theResult___snd__h377757[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h381339 = { value__h389561, 3'd0 } ;
|
|
assign sfd__h397142 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h397050 != 8'd0,
|
|
sfdin__h397044[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h405724 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h405706 != 8'd0,
|
|
_theResult___snd__h405657[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h414908 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h414816 != 8'd0,
|
|
sfdin__h414810[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h423520 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h423501 != 8'd0,
|
|
_theResult___snd__h423447[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h427027 = { value__h435249, 3'd0 } ;
|
|
assign sfd__h442830 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h442738 != 8'd0,
|
|
sfdin__h442732[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h451412 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h451394 != 8'd0,
|
|
_theResult___snd__h451345[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h460596 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h460504 != 8'd0,
|
|
sfdin__h460498[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h469208 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h469189 != 8'd0,
|
|
_theResult___snd__h469135[56:34] } +
|
|
25'd1 ;
|
|
assign sfd__h479622 = { value__h484180, 32'd0 } ;
|
|
assign sfd__h498641 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h498623 != 11'd0,
|
|
_theResult___snd__h498574[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h508292 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h508200 != 11'd0,
|
|
sfdin__h508194[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h517052 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h517033 != 11'd0,
|
|
_theResult___snd__h516979[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h518564 = { value__h522981, 32'd0 } ;
|
|
assign sfd__h537442 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h537424 != 11'd0,
|
|
_theResult___snd__h537375[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h547093 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h547001 != 11'd0,
|
|
sfdin__h546995[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h555853 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h555834 != 11'd0,
|
|
_theResult___snd__h555780[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h557765 = { value__h562182, 32'd0 } ;
|
|
assign sfd__h576643 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h576625 != 11'd0,
|
|
_theResult___snd__h576576[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h586294 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h586202 != 11'd0,
|
|
sfdin__h586196[56:5] } +
|
|
54'd1 ;
|
|
assign sfd__h595054 =
|
|
{ 1'b0,
|
|
_theResult___fst_exp__h595035 != 11'd0,
|
|
_theResult___snd__h594981[56:5] } +
|
|
54'd1 ;
|
|
assign sfdin__h351354 =
|
|
_theResult____h343249[56] ?
|
|
_theResult___snd__h351371 :
|
|
_theResult___snd__h351382 ;
|
|
assign sfdin__h369120 =
|
|
_theResult____h360888[56] ?
|
|
_theResult___snd__h369137 :
|
|
_theResult___snd__h369148 ;
|
|
assign sfdin__h397044 =
|
|
_theResult____h388941[56] ?
|
|
_theResult___snd__h397061 :
|
|
_theResult___snd__h397072 ;
|
|
assign sfdin__h414810 =
|
|
_theResult____h406578[56] ?
|
|
_theResult___snd__h414827 :
|
|
_theResult___snd__h414838 ;
|
|
assign sfdin__h442732 =
|
|
_theResult____h434629[56] ?
|
|
_theResult___snd__h442749 :
|
|
_theResult___snd__h442760 ;
|
|
assign sfdin__h460498 =
|
|
_theResult____h452266[56] ?
|
|
_theResult___snd__h460515 :
|
|
_theResult___snd__h460526 ;
|
|
assign sfdin__h508194 =
|
|
_theResult____h499964[56] ?
|
|
_theResult___snd__h508211 :
|
|
_theResult___snd__h508222 ;
|
|
assign sfdin__h546995 =
|
|
_theResult____h538765[56] ?
|
|
_theResult___snd__h547012 :
|
|
_theResult___snd__h547023 ;
|
|
assign sfdin__h586196 =
|
|
_theResult____h577966[56] ?
|
|
_theResult___snd__h586213 :
|
|
_theResult___snd__h586224 ;
|
|
assign shiftData__h180478 =
|
|
coreFix_memExe_regToExeQ$first[75:12] << x__h180610 ;
|
|
assign sie_csr__read__h606359 =
|
|
{ r1__read__h609187, csrf_software_int_en_vec_0 } ;
|
|
assign sip_csr__read__h606732 =
|
|
{ r1__read__h609741, csrf_software_int_pend_vec_0 } ;
|
|
assign spec_bits__h676030 = specTagManager$currentSpecBits | y__h676043 ;
|
|
assign sstatus_csr__read__h606290 = { r1__read__h608783, csrf_ie_vec_0 } ;
|
|
assign stvec_csr__read__h606402 =
|
|
{ r1__read__h609717, csrf_stvec_mode_low_reg } ;
|
|
assign upd__h3638 =
|
|
WILL_FIRE_RL_commitStage_doCommitSystemInst ?
|
|
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 :
|
|
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ;
|
|
assign upd__h4955 = n__read__h6133 + 64'd1 ;
|
|
assign v__h293109 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3023) ?
|
|
v__h293340 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ;
|
|
assign v__h293340 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
|
|
3'd7) ?
|
|
3'd0 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP +
|
|
3'd1 ;
|
|
assign v__h296454 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3130) ?
|
|
v__h296972 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ;
|
|
assign v__h296972 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ;
|
|
assign v__h306968 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3301) ?
|
|
v__h307199 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ;
|
|
assign v__h307199 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ;
|
|
assign v__h310844 =
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3397) ?
|
|
v__h311075 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ;
|
|
assign v__h311075 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ;
|
|
assign v__h325445 =
|
|
(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3626) ?
|
|
v__h325676 :
|
|
coreFix_memExe_memRespLdQ_enqP ;
|
|
assign v__h325676 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ;
|
|
assign v__h328670 =
|
|
(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3720) ?
|
|
v__h328901 :
|
|
coreFix_memExe_forwardQ_enqP ;
|
|
assign v__h328901 = coreFix_memExe_forwardQ_enqP + 1'd1 ;
|
|
assign v__h600721 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ?
|
|
v__h600731 :
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ;
|
|
assign v__h600731 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ;
|
|
assign v__h601366 = v__h600721 - 2'd1 ;
|
|
assign v__h604700 =
|
|
sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h605606 ;
|
|
assign v__h628235 =
|
|
sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h628988 ;
|
|
assign vaddr__h180473 =
|
|
coreFix_memExe_regToExeQ$first[139:76] +
|
|
{ {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4[31]}},
|
|
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q4 } ;
|
|
assign value__h343871 =
|
|
{ 1'b0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
|
|
11'd0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ;
|
|
assign value__h389561 =
|
|
{ 1'b0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
|
|
11'd0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ;
|
|
assign value__h435249 =
|
|
{ 1'b0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
|
|
11'd0,
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ;
|
|
assign value__h484180 =
|
|
{ 1'b0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] != 8'd0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] } ;
|
|
assign value__h522981 =
|
|
{ 1'b0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] != 8'd0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] } ;
|
|
assign value__h562182 =
|
|
{ 1'b0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] != 8'd0,
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] } ;
|
|
assign vm_mode_reg__read__h609977 = { csrf_vm_mode_sv39_reg, 3'b0 } ;
|
|
assign w__h640841 =
|
|
coreFix_globalSpecUpdate_correctSpecTag_0$whas ?
|
|
result__h640897 :
|
|
12'd4095 ;
|
|
assign x__h152848 =
|
|
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] :
|
|
coreFix_memExe_reqLdQ_data_0_rl[68:64]) :
|
|
5'd0 ;
|
|
assign x__h152854 =
|
|
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] :
|
|
coreFix_memExe_reqLdQ_data_0_rl[63:0]) :
|
|
64'd0 ;
|
|
assign x__h156395 = { 3'd0, sbIdx__h156274 } ;
|
|
assign x__h156401 =
|
|
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
|
|
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
|
|
coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] :
|
|
coreFix_memExe_reqStQ_data_0_rl[63:0]) :
|
|
64'd0 ;
|
|
assign x__h159211 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) :
|
|
5'd0 ;
|
|
assign x__h159215 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) :
|
|
64'd0 ;
|
|
assign x__h161063 =
|
|
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] :
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) :
|
|
64'd0 ;
|
|
assign x__h17638 =
|
|
mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[141:78] :
|
|
mmio_dataReqQ_enqReq_rl[141:78] ;
|
|
assign x__h180387 =
|
|
sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h179475 ;
|
|
assign x__h180388 =
|
|
sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180081 ;
|
|
assign x__h180610 = { vaddr__h180473[2:0], 3'b0 } ;
|
|
assign x__h190846 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ?
|
|
curData__h190083[63:32] :
|
|
curData__h190083[31:0] ;
|
|
assign x__h20176 =
|
|
mmio_dataReqQ_enqReq_lat_0$whas ?
|
|
mmio_dataReqQ_enqReq_lat_0$wget[63:0] :
|
|
mmio_dataReqQ_enqReq_rl[63:0] ;
|
|
assign x__h284446 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) :
|
|
5'd0 ;
|
|
assign x__h284458 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) :
|
|
64'd0 ;
|
|
assign x__h286312 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
|
|
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) :
|
|
64'd0 ;
|
|
assign x__h299319 =
|
|
EN_dCacheToParent_fromP_enq ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ;
|
|
assign x__h335048 =
|
|
{ (_theResult___exp__h378380 != 8'd255 ||
|
|
_theResult___sfd__h378381 == 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5132,
|
|
out_f_exp__h378657,
|
|
out_f_sfd__h378658 } ;
|
|
assign x__h361598 =
|
|
sfd__h335644 << (x__h361631[11] ? 12'hAAA : x__h361631) ;
|
|
assign x__h361631 =
|
|
12'd57 -
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4546 ;
|
|
assign x__h380743 =
|
|
{ (_theResult___exp__h424070 != 8'd255 ||
|
|
_theResult___sfd__h424071 == 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6524,
|
|
out_f_exp__h424347,
|
|
out_f_sfd__h424348 } ;
|
|
assign x__h407288 =
|
|
sfd__h381339 << (x__h407321[11] ? 12'hAAA : x__h407321) ;
|
|
assign x__h407321 =
|
|
12'd57 -
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5938 ;
|
|
assign x__h426431 =
|
|
{ (_theResult___exp__h469758 != 8'd255 ||
|
|
_theResult___sfd__h469759 == 23'd0) &&
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7916,
|
|
out_f_exp__h470035,
|
|
out_f_sfd__h470036 } ;
|
|
assign x__h452976 =
|
|
sfd__h427027 << (x__h453009[11] ? 12'hAAA : x__h453009) ;
|
|
assign x__h453009 =
|
|
12'd57 -
|
|
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7330 ;
|
|
assign x__h45545 =
|
|
mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[141:78] :
|
|
mmio_cRqQ_enqReq_rl[141:78] ;
|
|
assign x__h478817 =
|
|
sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h475953 ;
|
|
assign x__h478818 =
|
|
sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h476561 ;
|
|
assign x__h478819 =
|
|
sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477163 ;
|
|
assign x__h48081 =
|
|
mmio_cRqQ_enqReq_lat_0$whas ?
|
|
mmio_cRqQ_enqReq_lat_0$wget[63:0] :
|
|
mmio_cRqQ_enqReq_rl[63:0] ;
|
|
assign x__h500672 = sfd__h479622 << x__h500705 ;
|
|
assign x__h500705 =
|
|
12'd57 -
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d8637 ;
|
|
assign x__h539473 = sfd__h518564 << x__h539506 ;
|
|
assign x__h539506 =
|
|
12'd57 -
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d10110 ;
|
|
assign x__h578674 = sfd__h557765 << x__h578707 ;
|
|
assign x__h578707 =
|
|
12'd57 -
|
|
_3074_MINUS_SEXT_coreFix_fpuMulDivExe_0_regToEx_ETC___d9347 ;
|
|
assign x__h600222 = a__h599786[63] ^ b__h599787[63] ;
|
|
assign x__h608768 = { csrf_frm_reg, csrf_fflags_reg } ;
|
|
assign x__h608823 = csrf_fs_reg ;
|
|
assign x__h612962 =
|
|
coreFix_aluExe_1_dispToRegQ$first[131] ?
|
|
rVal1__h605816 :
|
|
v__h604700 ;
|
|
assign x__h612963 =
|
|
sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h610852 ;
|
|
assign x__h634046 =
|
|
coreFix_aluExe_0_dispToRegQ$first[131] ?
|
|
rVal1__h629196 :
|
|
v__h628235 ;
|
|
assign x__h634047 =
|
|
sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h631946 ;
|
|
assign x__h640845 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ;
|
|
assign x__h640896 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ;
|
|
assign x__h691750 = { cause_code__h689130, 2'b0 } ;
|
|
assign x__h699370 = { 1'b0, csrf_spp_reg } ;
|
|
assign x__h702270 =
|
|
NOT_rob_deqPort_0_canDeq__4362_4363_OR_rob_deq_ETC___d14454 ?
|
|
y_avValue_snd_snd_snd_fst__h702327 :
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14482 ;
|
|
assign x__h75490 = mmio_pRqQ_data_0[31:0] ;
|
|
assign x_addr__h311242 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ;
|
|
assign x_data__h65339 =
|
|
EN_mmioToPlatform_pRq_enq ?
|
|
mmio_pRqQ_enqReq_lat_0$wget[31:0] :
|
|
mmio_pRqQ_enqReq_rl[31:0] ;
|
|
assign x_data_imm__h666240 = fetchStage$pipelines_0_first[63:32] ;
|
|
assign x_data_imm__h680279 = fetchStage$pipelines_1_first[63:32] ;
|
|
assign x_decodeInfo_frm__h648859 = csrf_frm_reg ;
|
|
assign x_quotient__h472342 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
|
|
64'hFFFFFFFFFFFFFFFF :
|
|
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ?
|
|
q___1__h473027 :
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ;
|
|
assign x_reg_ifc__read__h606199 = { 63'd0, csrf_stats_module_doStats } ;
|
|
assign x_remainder__h472343 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] :
|
|
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ?
|
|
r___1__h473053 :
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ;
|
|
assign y__h251971 =
|
|
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ;
|
|
assign y__h640875 = ~x__h640845 ;
|
|
assign y__h645629 =
|
|
{ 3'd7,
|
|
~csrf_mideleg_11_reg,
|
|
1'd1,
|
|
~csrf_mideleg_9_7_reg,
|
|
1'd1,
|
|
~csrf_mideleg_5_3_reg,
|
|
1'd1,
|
|
~csrf_mideleg_1_0_reg } ;
|
|
assign y__h676043 = 12'd1 << specTagManager$nextSpecTag ;
|
|
assign y_avValue__h179475 =
|
|
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ;
|
|
assign y_avValue__h180081 =
|
|
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ;
|
|
assign y_avValue__h475953 =
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8226 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8330 ;
|
|
assign y_avValue__h476561 =
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8253 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8341 ;
|
|
assign y_avValue__h477163 =
|
|
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8277 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8352 ;
|
|
assign y_avValue__h605606 =
|
|
NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11326 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11702 ;
|
|
assign y_avValue__h610852 =
|
|
NOT_coreFix_aluExe_1_bypassWire_0_whas__1299_1_ETC___d11354 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__129_ETC___d11714 ;
|
|
assign y_avValue__h628988 =
|
|
NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12117 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12309 ;
|
|
assign y_avValue__h631946 =
|
|
NOT_coreFix_aluExe_0_bypassWire_0_whas__2090_2_ETC___d12145 ?
|
|
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
|
|
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__209_ETC___d12321 ;
|
|
assign y_avValue__h690008 =
|
|
(csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ?
|
|
base__h691735 + { 58'd0, x__h691750 } :
|
|
base__h691735 ;
|
|
assign y_avValue__h691772 =
|
|
(csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ?
|
|
base__h691938 + { 58'd0, x__h691750 } :
|
|
base__h691938 ;
|
|
assign y_avValue_fst__h670126 =
|
|
(fetchStage$pipelines_0_first[98:96] == 3'd1) ?
|
|
spec_bits__h676030 :
|
|
specTagManager$currentSpecBits ;
|
|
assign y_avValue_snd_fst__h670400 =
|
|
((fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim) &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123) ?
|
|
y_avValue_snd_fst__h670435 :
|
|
specTagManager$currentSpecBits ;
|
|
assign y_avValue_snd_fst__h670435 =
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 ?
|
|
y_avValue_fst__h670126 :
|
|
specTagManager$currentSpecBits ;
|
|
assign y_avValue_snd_fst__h702081 =
|
|
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
|
|
rob$deqPort_1_deq_data[103] ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd0 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd21 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd17 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd18 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd13 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd15 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd20) ?
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14460 :
|
|
y_avValue_snd_fst__h702089 ;
|
|
assign y_avValue_snd_fst__h702089 =
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14460 |
|
|
rob$deqPort_1_deq_data[31:27] ;
|
|
assign y_avValue_snd_fst__h702097 =
|
|
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
|
|
rob$deqPort_0_deq_data[103] ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd0 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd21 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd17 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd18 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd15 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd20) ?
|
|
5'd0 :
|
|
rob$deqPort_0_deq_data[31:27] ;
|
|
assign y_avValue_snd_snd_snd_fst__h702327 =
|
|
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
|
|
rob$deqPort_1_deq_data[103] ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd0 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd21 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd17 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd18 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd13 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd15 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_1_deq_data[122:118] == 5'd20) ?
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14482 :
|
|
y_avValue_snd_snd_snd_fst__h702335 ;
|
|
assign y_avValue_snd_snd_snd_fst__h702335 =
|
|
IF_rob_deqPort_0_canDeq__4362_THEN_IF_NOT_rob__ETC___d14482 +
|
|
2'd1 ;
|
|
assign y_avValue_snd_snd_snd_fst__h702343 =
|
|
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
|
|
rob$deqPort_0_deq_data[103] ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd0 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd21 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd17 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd18 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd16 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd15 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd19 ||
|
|
rob$deqPort_0_deq_data[122:118] == 5'd20) ?
|
|
2'd0 :
|
|
2'd1 ;
|
|
always@(mmio_cRqQ_data_0)
|
|
begin
|
|
case (mmio_cRqQ_data_0[77:76])
|
|
2'd0, 2'd1, 2'd2:
|
|
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 =
|
|
mmio_cRqQ_data_0[77:72];
|
|
2'd3:
|
|
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q1 =
|
|
{ 2'd3, mmio_cRqQ_data_0[75:72] };
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87])
|
|
3'd0:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
|
|
3'd1:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
|
|
3'd2:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
|
|
3'd3:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
|
|
3'd4:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
|
|
3'd5:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
|
|
3'd6:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
|
|
3'd7:
|
|
x__h194294 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP)
|
|
3'd0:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
|
|
3'd1:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
|
|
3'd2:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
|
|
3'd3:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
|
|
3'd4:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
|
|
3'd5:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
|
|
3'd6:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
|
|
3'd7:
|
|
x__h283013 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
addr__h287234 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518];
|
|
1'd1:
|
|
addr__h287234 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91])
|
|
3'd0:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
|
|
3'd1:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
|
|
3'd2:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
|
|
3'd3:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
|
|
3'd4:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
|
|
3'd5:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
|
|
3'd6:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
|
|
3'd7:
|
|
curData__h190083 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
|
|
endcase
|
|
end
|
|
always@(commitStage_commitTrap)
|
|
begin
|
|
case (commitStage_commitTrap[3:0])
|
|
4'd0, 4'd1, 4'd3, 4'd12:
|
|
trap_val__h690161 = commitStage_commitTrap[132:69];
|
|
default: trap_val__h690161 =
|
|
(commitStage_commitTrap[3:0] != 4'd2 &&
|
|
commitStage_commitTrap[3:0] != 4'd8 &&
|
|
commitStage_commitTrap[3:0] != 4'd9 &&
|
|
commitStage_commitTrap[3:0] != 4'd11) ?
|
|
commitStage_commitTrap[68:5] :
|
|
64'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
x__h288783 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0];
|
|
1'd1:
|
|
x__h288783 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0];
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_dispToRegQ$first or
|
|
fflags_csr__read__h606069 or
|
|
frm_csr__read__h606080 or
|
|
fcsr_csr__read__h606094 or
|
|
sstatus_csr__read__h606290 or
|
|
sie_csr__read__h606359 or
|
|
stvec_csr__read__h606402 or
|
|
scounteren_csr__read__h606455 or
|
|
csrf_sscratch_csr or
|
|
csrf_sepc_csr or
|
|
scause_csr__read__h606593 or
|
|
csrf_stval_csr or
|
|
sip_csr__read__h606732 or
|
|
satp_csr__read__h606795 or
|
|
mstatus_csr__read__h606938 or
|
|
medeleg_csr__read__h607086 or
|
|
mideleg_csr__read__h607181 or
|
|
mie_csr__read__h607312 or
|
|
mtvec_csr__read__h607394 or
|
|
mcounteren_csr__read__h607486 or
|
|
csrf_mscratch_csr or
|
|
csrf_mepc_csr or
|
|
mcause_csr__read__h607741 or
|
|
csrf_mtval_csr or
|
|
mip_csr__read__h607981 or
|
|
x_reg_ifc__read__h606199 or
|
|
n__read__h608085 or n__read__h608276 or csrf_time_reg)
|
|
begin
|
|
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
|
|
12'd1: rVal1__h605816 = fflags_csr__read__h606069;
|
|
12'd2: rVal1__h605816 = frm_csr__read__h606080;
|
|
12'd3: rVal1__h605816 = fcsr_csr__read__h606094;
|
|
12'd256: rVal1__h605816 = sstatus_csr__read__h606290;
|
|
12'd260: rVal1__h605816 = sie_csr__read__h606359;
|
|
12'd261: rVal1__h605816 = stvec_csr__read__h606402;
|
|
12'd262: rVal1__h605816 = scounteren_csr__read__h606455;
|
|
12'd320: rVal1__h605816 = csrf_sscratch_csr;
|
|
12'd321: rVal1__h605816 = csrf_sepc_csr;
|
|
12'd322: rVal1__h605816 = scause_csr__read__h606593;
|
|
12'd323: rVal1__h605816 = csrf_stval_csr;
|
|
12'd324: rVal1__h605816 = sip_csr__read__h606732;
|
|
12'd384: rVal1__h605816 = satp_csr__read__h606795;
|
|
12'd768: rVal1__h605816 = mstatus_csr__read__h606938;
|
|
12'd769: rVal1__h605816 = 64'h8000000000041129;
|
|
12'd770: rVal1__h605816 = medeleg_csr__read__h607086;
|
|
12'd771: rVal1__h605816 = mideleg_csr__read__h607181;
|
|
12'd772: rVal1__h605816 = mie_csr__read__h607312;
|
|
12'd773: rVal1__h605816 = mtvec_csr__read__h607394;
|
|
12'd774: rVal1__h605816 = mcounteren_csr__read__h607486;
|
|
12'd832: rVal1__h605816 = csrf_mscratch_csr;
|
|
12'd833: rVal1__h605816 = csrf_mepc_csr;
|
|
12'd834: rVal1__h605816 = mcause_csr__read__h607741;
|
|
12'd835: rVal1__h605816 = csrf_mtval_csr;
|
|
12'd836: rVal1__h605816 = mip_csr__read__h607981;
|
|
12'd2048: rVal1__h605816 = 64'd0;
|
|
12'd2049: rVal1__h605816 = x_reg_ifc__read__h606199;
|
|
12'd2816, 12'd3072: rVal1__h605816 = n__read__h608085;
|
|
12'd2818, 12'd3074: rVal1__h605816 = n__read__h608276;
|
|
12'd3073: rVal1__h605816 = csrf_time_reg;
|
|
default: rVal1__h605816 = 64'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_dispToRegQ$first or
|
|
fflags_csr__read__h606069 or
|
|
frm_csr__read__h606080 or
|
|
fcsr_csr__read__h606094 or
|
|
sstatus_csr__read__h606290 or
|
|
sie_csr__read__h606359 or
|
|
stvec_csr__read__h606402 or
|
|
scounteren_csr__read__h606455 or
|
|
csrf_sscratch_csr or
|
|
csrf_sepc_csr or
|
|
scause_csr__read__h606593 or
|
|
csrf_stval_csr or
|
|
sip_csr__read__h606732 or
|
|
satp_csr__read__h606795 or
|
|
mstatus_csr__read__h606938 or
|
|
medeleg_csr__read__h607086 or
|
|
mideleg_csr__read__h607181 or
|
|
mie_csr__read__h607312 or
|
|
mtvec_csr__read__h607394 or
|
|
mcounteren_csr__read__h607486 or
|
|
csrf_mscratch_csr or
|
|
csrf_mepc_csr or
|
|
mcause_csr__read__h607741 or
|
|
csrf_mtval_csr or
|
|
mip_csr__read__h607981 or
|
|
x_reg_ifc__read__h606199 or
|
|
n__read__h608085 or n__read__h608276 or csrf_time_reg)
|
|
begin
|
|
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
|
|
12'd1: rVal1__h629196 = fflags_csr__read__h606069;
|
|
12'd2: rVal1__h629196 = frm_csr__read__h606080;
|
|
12'd3: rVal1__h629196 = fcsr_csr__read__h606094;
|
|
12'd256: rVal1__h629196 = sstatus_csr__read__h606290;
|
|
12'd260: rVal1__h629196 = sie_csr__read__h606359;
|
|
12'd261: rVal1__h629196 = stvec_csr__read__h606402;
|
|
12'd262: rVal1__h629196 = scounteren_csr__read__h606455;
|
|
12'd320: rVal1__h629196 = csrf_sscratch_csr;
|
|
12'd321: rVal1__h629196 = csrf_sepc_csr;
|
|
12'd322: rVal1__h629196 = scause_csr__read__h606593;
|
|
12'd323: rVal1__h629196 = csrf_stval_csr;
|
|
12'd324: rVal1__h629196 = sip_csr__read__h606732;
|
|
12'd384: rVal1__h629196 = satp_csr__read__h606795;
|
|
12'd768: rVal1__h629196 = mstatus_csr__read__h606938;
|
|
12'd769: rVal1__h629196 = 64'h8000000000041129;
|
|
12'd770: rVal1__h629196 = medeleg_csr__read__h607086;
|
|
12'd771: rVal1__h629196 = mideleg_csr__read__h607181;
|
|
12'd772: rVal1__h629196 = mie_csr__read__h607312;
|
|
12'd773: rVal1__h629196 = mtvec_csr__read__h607394;
|
|
12'd774: rVal1__h629196 = mcounteren_csr__read__h607486;
|
|
12'd832: rVal1__h629196 = csrf_mscratch_csr;
|
|
12'd833: rVal1__h629196 = csrf_mepc_csr;
|
|
12'd834: rVal1__h629196 = mcause_csr__read__h607741;
|
|
12'd835: rVal1__h629196 = csrf_mtval_csr;
|
|
12'd836: rVal1__h629196 = mip_csr__read__h607981;
|
|
12'd2048: rVal1__h629196 = 64'd0;
|
|
12'd2049: rVal1__h629196 = x_reg_ifc__read__h606199;
|
|
12'd2816, 12'd3072: rVal1__h629196 = n__read__h608085;
|
|
12'd2818, 12'd3074: rVal1__h629196 = n__read__h608276;
|
|
12'd3073: rVal1__h629196 = csrf_time_reg;
|
|
default: rVal1__h629196 = 64'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0, 3'd1: _theResult___fst_exp__h434611 = 8'd255;
|
|
3'd2:
|
|
_theResult___fst_exp__h434611 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
8'd254 :
|
|
8'd255;
|
|
3'd3:
|
|
_theResult___fst_exp__h434611 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
8'd255 :
|
|
8'd254;
|
|
3'd4: _theResult___fst_exp__h434611 = 8'd254;
|
|
default: _theResult___fst_exp__h434611 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0, 3'd1: _theResult___fst_exp__h343231 = 8'd255;
|
|
3'd2:
|
|
_theResult___fst_exp__h343231 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
8'd254 :
|
|
8'd255;
|
|
3'd3:
|
|
_theResult___fst_exp__h343231 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
8'd255 :
|
|
8'd254;
|
|
3'd4: _theResult___fst_exp__h343231 = 8'd254;
|
|
default: _theResult___fst_exp__h343231 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0, 3'd1: _theResult___fst_sfd__h343232 = 23'd0;
|
|
3'd2:
|
|
_theResult___fst_sfd__h343232 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
23'd8388607 :
|
|
23'd0;
|
|
3'd3:
|
|
_theResult___fst_sfd__h343232 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
|
|
23'd0 :
|
|
23'd8388607;
|
|
3'd4: _theResult___fst_sfd__h343232 = 23'd8388607;
|
|
default: _theResult___fst_sfd__h343232 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0, 3'd1: _theResult___fst_exp__h388923 = 8'd255;
|
|
3'd2:
|
|
_theResult___fst_exp__h388923 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
8'd254 :
|
|
8'd255;
|
|
3'd3:
|
|
_theResult___fst_exp__h388923 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
8'd255 :
|
|
8'd254;
|
|
3'd4: _theResult___fst_exp__h388923 = 8'd254;
|
|
default: _theResult___fst_exp__h388923 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0, 3'd1: _theResult___fst_sfd__h388924 = 23'd0;
|
|
3'd2:
|
|
_theResult___fst_sfd__h388924 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
23'd8388607 :
|
|
23'd0;
|
|
3'd3:
|
|
_theResult___fst_sfd__h388924 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
|
|
23'd0 :
|
|
23'd8388607;
|
|
3'd4: _theResult___fst_sfd__h388924 = 23'd8388607;
|
|
default: _theResult___fst_sfd__h388924 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0, 3'd1: _theResult___fst_sfd__h434612 = 23'd0;
|
|
3'd2:
|
|
_theResult___fst_sfd__h434612 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
23'd8388607 :
|
|
23'd0;
|
|
3'd3:
|
|
_theResult___fst_sfd__h434612 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
|
|
23'd0 :
|
|
23'd8388607;
|
|
3'd4: _theResult___fst_sfd__h434612 = 23'd8388607;
|
|
default: _theResult___fst_sfd__h434612 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd2046;
|
|
3'd2:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
11'd2047 :
|
|
11'd2046;
|
|
3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
11'd2046 :
|
|
11'd2047;
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q6 = 11'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
|
|
52'hFFFFFFFFFFFFF;
|
|
3'd2:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
52'd0 :
|
|
52'hFFFFFFFFFFFFF;
|
|
3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ?
|
|
52'hFFFFFFFFFFFFF :
|
|
52'd0;
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q7 = 52'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 11'd2046;
|
|
3'd2:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
11'd2047 :
|
|
11'd2046;
|
|
3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
11'd2046 :
|
|
11'd2047;
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q8 = 11'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
|
|
52'hFFFFFFFFFFFFF;
|
|
3'd2:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
52'd0 :
|
|
52'hFFFFFFFFFFFFF;
|
|
3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ?
|
|
52'hFFFFFFFFFFFFF :
|
|
52'd0;
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q9 = 52'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 11'd2046;
|
|
3'd2:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
11'd2047 :
|
|
11'd2046;
|
|
3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
11'd2046 :
|
|
11'd2047;
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q10 = 11'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
|
|
52'hFFFFFFFFFFFFF;
|
|
3'd2:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
52'd0 :
|
|
52'hFFFFFFFFFFFFF;
|
|
3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ?
|
|
52'hFFFFFFFFFFFFF :
|
|
52'd0;
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q11 = 52'd0;
|
|
endcase
|
|
end
|
|
always@(commitStage_commitTrap)
|
|
begin
|
|
case (commitStage_commitTrap[3:0])
|
|
4'd0,
|
|
4'd1,
|
|
4'd2,
|
|
4'd3,
|
|
4'd4,
|
|
4'd5,
|
|
4'd6,
|
|
4'd7,
|
|
4'd8,
|
|
4'd9,
|
|
4'd11,
|
|
4'd12,
|
|
4'd13:
|
|
i__h689145 = commitStage_commitTrap[3:0];
|
|
default: i__h689145 = 4'd15;
|
|
endcase
|
|
end
|
|
always@(commitStage_commitTrap)
|
|
begin
|
|
case (commitStage_commitTrap[3:0])
|
|
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11:
|
|
i__h689305 = commitStage_commitTrap[3:0];
|
|
default: i__h689305 = 4'd14;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstLd[19])
|
|
1'd0:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[31:0];
|
|
1'd1:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[63:32];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstLd[19:18])
|
|
2'd0:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[15:0];
|
|
2'd1:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[31:16];
|
|
2'd2:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[47:32];
|
|
2'd3:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[63:48];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstLd[19:17])
|
|
3'd0:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[7:0];
|
|
3'd1:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[15:8];
|
|
3'd2:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[23:16];
|
|
3'd3:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[31:24];
|
|
3'd4:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[39:32];
|
|
3'd5:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[47:40];
|
|
3'd6:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[55:48];
|
|
3'd7:
|
|
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
|
|
coreFix_memExe_respLrScAmoQ_data_0[63:56];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstLd[19:18])
|
|
2'd0:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
|
|
mmio_dataRespQ_data_0[15:0];
|
|
2'd1:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
|
|
mmio_dataRespQ_data_0[31:16];
|
|
2'd2:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
|
|
mmio_dataRespQ_data_0[47:32];
|
|
2'd3:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
|
|
mmio_dataRespQ_data_0[63:48];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstLd[19])
|
|
1'd0:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
|
|
mmio_dataRespQ_data_0[31:0];
|
|
1'd1:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
|
|
mmio_dataRespQ_data_0[63:32];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstLd[19:17])
|
|
3'd0:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[7:0];
|
|
3'd1:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[15:8];
|
|
3'd2:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[23:16];
|
|
3'd3:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[31:24];
|
|
3'd4:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[39:32];
|
|
3'd5:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[47:40];
|
|
3'd6:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[55:48];
|
|
3'd7:
|
|
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
|
|
mmio_dataRespQ_data_0[63:56];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dTlb$procResp)
|
|
begin
|
|
case (coreFix_memExe_dTlb$procResp[105:103])
|
|
3'd0, 3'd2:
|
|
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 = 4'd4;
|
|
default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q12 = 4'd6;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dTlb$procResp)
|
|
begin
|
|
case (coreFix_memExe_dTlb$procResp[109:106])
|
|
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
|
|
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 =
|
|
coreFix_memExe_dTlb$procResp[109:106];
|
|
4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd10;
|
|
4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd11;
|
|
4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd12;
|
|
default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q13 = 4'd13;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2867 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2];
|
|
1'd1:
|
|
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2867 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q14 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q15 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q16 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q17 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q18 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q19 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5112 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5112 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h351968 or
|
|
_theResult___fst_exp__h360016 or
|
|
out_exp__h360461 or _theResult___exp__h360458)
|
|
begin
|
|
case (guard__h351968)
|
|
2'b0, 2'b01:
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q24 =
|
|
_theResult___fst_exp__h360016;
|
|
2'b10:
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q24 =
|
|
out_exp__h360461;
|
|
2'b11:
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q24 =
|
|
_theResult___exp__h360458;
|
|
endcase
|
|
end
|
|
always@(guard__h351968 or
|
|
_theResult___fst_exp__h360016 or _theResult___exp__h360458)
|
|
begin
|
|
case (guard__h351968)
|
|
2'b0:
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q25 =
|
|
_theResult___fst_exp__h360016;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q25 =
|
|
_theResult___exp__h360458;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q24 or
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q25 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4524 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4526 or
|
|
_theResult___fst_exp__h360016)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h360536 =
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q24;
|
|
3'd1:
|
|
_theResult___fst_exp__h360536 =
|
|
CASE_guard51968_0b0_theResult___fst_exp60016_0_ETC__q25;
|
|
3'd2:
|
|
_theResult___fst_exp__h360536 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4524;
|
|
3'd3:
|
|
_theResult___fst_exp__h360536 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4526;
|
|
3'd4: _theResult___fst_exp__h360536 = _theResult___fst_exp__h360016;
|
|
default: _theResult___fst_exp__h360536 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h343259 or
|
|
_theResult___fst_exp__h351360 or
|
|
out_exp__h351879 or _theResult___exp__h351876)
|
|
begin
|
|
case (guard__h343259)
|
|
2'b0, 2'b01:
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q26 =
|
|
_theResult___fst_exp__h351360;
|
|
2'b10:
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q26 =
|
|
out_exp__h351879;
|
|
2'b11:
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q26 =
|
|
_theResult___exp__h351876;
|
|
endcase
|
|
end
|
|
always@(guard__h343259 or
|
|
_theResult___fst_exp__h351360 or _theResult___exp__h351876)
|
|
begin
|
|
case (guard__h343259)
|
|
2'b0:
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q27 =
|
|
_theResult___fst_exp__h351360;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q27 =
|
|
_theResult___exp__h351876;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q26 or
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q27 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4302 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4305 or
|
|
_theResult___fst_exp__h351360)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h351954 =
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q26;
|
|
3'd1:
|
|
_theResult___fst_exp__h351954 =
|
|
CASE_guard43259_0b0_theResult___fst_exp51360_0_ETC__q27;
|
|
3'd2:
|
|
_theResult___fst_exp__h351954 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4302;
|
|
3'd3:
|
|
_theResult___fst_exp__h351954 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4305;
|
|
3'd4: _theResult___fst_exp__h351954 = _theResult___fst_exp__h351360;
|
|
default: _theResult___fst_exp__h351954 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h360898 or
|
|
_theResult___fst_exp__h369126 or
|
|
out_exp__h369645 or _theResult___exp__h369642)
|
|
begin
|
|
case (guard__h360898)
|
|
2'b0, 2'b01:
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q32 =
|
|
_theResult___fst_exp__h369126;
|
|
2'b10:
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q32 =
|
|
out_exp__h369645;
|
|
2'b11:
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q32 =
|
|
_theResult___exp__h369642;
|
|
endcase
|
|
end
|
|
always@(guard__h360898 or
|
|
_theResult___fst_exp__h369126 or _theResult___exp__h369642)
|
|
begin
|
|
case (guard__h360898)
|
|
2'b0:
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q33 =
|
|
_theResult___fst_exp__h369126;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q33 =
|
|
_theResult___exp__h369642;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q32 or
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q33 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4849 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4851 or
|
|
_theResult___fst_exp__h369126)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h369720 =
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q32;
|
|
3'd1:
|
|
_theResult___fst_exp__h369720 =
|
|
CASE_guard60898_0b0_theResult___fst_exp69126_0_ETC__q33;
|
|
3'd2:
|
|
_theResult___fst_exp__h369720 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4849;
|
|
3'd3:
|
|
_theResult___fst_exp__h369720 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4851;
|
|
3'd4: _theResult___fst_exp__h369720 = _theResult___fst_exp__h369126;
|
|
default: _theResult___fst_exp__h369720 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h369734 or
|
|
_theResult___fst_exp__h377811 or
|
|
out_exp__h378281 or _theResult___exp__h378278)
|
|
begin
|
|
case (guard__h369734)
|
|
2'b0, 2'b01:
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q37 =
|
|
_theResult___fst_exp__h377811;
|
|
2'b10:
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q37 =
|
|
out_exp__h378281;
|
|
2'b11:
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q37 =
|
|
_theResult___exp__h378278;
|
|
endcase
|
|
end
|
|
always@(guard__h369734 or
|
|
_theResult___fst_exp__h377811 or _theResult___exp__h378278)
|
|
begin
|
|
case (guard__h369734)
|
|
2'b0:
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q38 =
|
|
_theResult___fst_exp__h377811;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q38 =
|
|
_theResult___exp__h378278;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q37 or
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q38 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4918 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4920 or
|
|
_theResult___fst_exp__h377811)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h378356 =
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q37;
|
|
3'd1:
|
|
_theResult___fst_exp__h378356 =
|
|
CASE_guard69734_0b0_theResult___fst_exp77811_0_ETC__q38;
|
|
3'd2:
|
|
_theResult___fst_exp__h378356 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4918;
|
|
3'd3:
|
|
_theResult___fst_exp__h378356 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4920;
|
|
3'd4: _theResult___fst_exp__h378356 = _theResult___fst_exp__h377811;
|
|
default: _theResult___fst_exp__h378356 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h351968 or
|
|
_theResult___snd__h359967 or
|
|
out_sfd__h360462 or _theResult___sfd__h360459)
|
|
begin
|
|
case (guard__h351968)
|
|
2'b0, 2'b01:
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q39 =
|
|
_theResult___snd__h359967[56:34];
|
|
2'b10:
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q39 =
|
|
out_sfd__h360462;
|
|
2'b11:
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q39 =
|
|
_theResult___sfd__h360459;
|
|
endcase
|
|
end
|
|
always@(guard__h351968 or
|
|
_theResult___snd__h359967 or _theResult___sfd__h360459)
|
|
begin
|
|
case (guard__h351968)
|
|
2'b0:
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q40 =
|
|
_theResult___snd__h359967[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q40 =
|
|
_theResult___sfd__h360459;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q39 or
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q40 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4968 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4970 or
|
|
_theResult___snd__h359967)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h360537 =
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q39;
|
|
3'd1:
|
|
_theResult___fst_sfd__h360537 =
|
|
CASE_guard51968_0b0_theResult___snd59967_BITS__ETC__q40;
|
|
3'd2:
|
|
_theResult___fst_sfd__h360537 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4968;
|
|
3'd3:
|
|
_theResult___fst_sfd__h360537 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4970;
|
|
3'd4: _theResult___fst_sfd__h360537 = _theResult___snd__h359967[56:34];
|
|
default: _theResult___fst_sfd__h360537 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h343259 or
|
|
sfdin__h351354 or out_sfd__h351880 or _theResult___sfd__h351877)
|
|
begin
|
|
case (guard__h343259)
|
|
2'b0, 2'b01:
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q41 =
|
|
sfdin__h351354[56:34];
|
|
2'b10:
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q41 =
|
|
out_sfd__h351880;
|
|
2'b11:
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q41 =
|
|
_theResult___sfd__h351877;
|
|
endcase
|
|
end
|
|
always@(guard__h343259 or sfdin__h351354 or _theResult___sfd__h351877)
|
|
begin
|
|
case (guard__h343259)
|
|
2'b0:
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q42 =
|
|
sfdin__h351354[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q42 =
|
|
_theResult___sfd__h351877;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q41 or
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q42 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4949 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4951 or
|
|
sfdin__h351354)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h351955 =
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q41;
|
|
3'd1:
|
|
_theResult___fst_sfd__h351955 =
|
|
CASE_guard43259_0b0_sfdin51354_BITS_56_TO_34_0_ETC__q42;
|
|
3'd2:
|
|
_theResult___fst_sfd__h351955 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4949;
|
|
3'd3:
|
|
_theResult___fst_sfd__h351955 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4951;
|
|
3'd4: _theResult___fst_sfd__h351955 = sfdin__h351354[56:34];
|
|
default: _theResult___fst_sfd__h351955 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h360898 or
|
|
sfdin__h369120 or out_sfd__h369646 or _theResult___sfd__h369643)
|
|
begin
|
|
case (guard__h360898)
|
|
2'b0, 2'b01:
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q43 =
|
|
sfdin__h369120[56:34];
|
|
2'b10:
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q43 =
|
|
out_sfd__h369646;
|
|
2'b11:
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q43 =
|
|
_theResult___sfd__h369643;
|
|
endcase
|
|
end
|
|
always@(guard__h360898 or sfdin__h369120 or _theResult___sfd__h369643)
|
|
begin
|
|
case (guard__h360898)
|
|
2'b0:
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q44 =
|
|
sfdin__h369120[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q44 =
|
|
_theResult___sfd__h369643;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q43 or
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q44 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4995 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4997 or
|
|
sfdin__h369120)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h369721 =
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q43;
|
|
3'd1:
|
|
_theResult___fst_sfd__h369721 =
|
|
CASE_guard60898_0b0_sfdin69120_BITS_56_TO_34_0_ETC__q44;
|
|
3'd2:
|
|
_theResult___fst_sfd__h369721 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4995;
|
|
3'd3:
|
|
_theResult___fst_sfd__h369721 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4997;
|
|
3'd4: _theResult___fst_sfd__h369721 = sfdin__h369120[56:34];
|
|
default: _theResult___fst_sfd__h369721 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h369734 or
|
|
_theResult___snd__h377757 or
|
|
out_sfd__h378282 or _theResult___sfd__h378279)
|
|
begin
|
|
case (guard__h369734)
|
|
2'b0, 2'b01:
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q45 =
|
|
_theResult___snd__h377757[56:34];
|
|
2'b10:
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q45 =
|
|
out_sfd__h378282;
|
|
2'b11:
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q45 =
|
|
_theResult___sfd__h378279;
|
|
endcase
|
|
end
|
|
always@(guard__h369734 or
|
|
_theResult___snd__h377757 or _theResult___sfd__h378279)
|
|
begin
|
|
case (guard__h369734)
|
|
2'b0:
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q46 =
|
|
_theResult___snd__h377757[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q46 =
|
|
_theResult___sfd__h378279;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q45 or
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q46 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5014 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5016 or
|
|
_theResult___snd__h377757)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h378357 =
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q45;
|
|
3'd1:
|
|
_theResult___fst_sfd__h378357 =
|
|
CASE_guard69734_0b0_theResult___snd77757_BITS__ETC__q46;
|
|
3'd2:
|
|
_theResult___fst_sfd__h378357 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5014;
|
|
3'd3:
|
|
_theResult___fst_sfd__h378357 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5016;
|
|
3'd4: _theResult___fst_sfd__h378357 = _theResult___snd__h377757[56:34];
|
|
default: _theResult___fst_sfd__h378357 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h343259 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h343259)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard43259_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard43259_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 =
|
|
guard__h343259 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard43259_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47 or
|
|
guard__h343259)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5102 =
|
|
CASE_guard43259_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q47;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5102 =
|
|
(guard__h343259 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
(guard__h343259 == 2'b01 || guard__h343259 == 2'b10 ||
|
|
guard__h343259 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5102 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5102 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h343259 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h343259)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard43259_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard43259_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 =
|
|
guard__h343259 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard43259_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48 or
|
|
guard__h343259)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5046 =
|
|
CASE_guard43259_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q48;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5046 =
|
|
(guard__h343259 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
guard__h343259 != 2'b01 && guard__h343259 != 2'b10 &&
|
|
guard__h343259 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5046 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5046 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h351968 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h351968)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard51968_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard51968_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 =
|
|
guard__h351968 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard51968_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49 or
|
|
guard__h351968)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5109 =
|
|
CASE_guard51968_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q49;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5109 =
|
|
(guard__h351968 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
(guard__h351968 == 2'b01 || guard__h351968 == 2'b10 ||
|
|
guard__h351968 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5109 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5109 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h351968 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h351968)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard51968_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard51968_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 =
|
|
guard__h351968 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard51968_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50 or
|
|
guard__h351968)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5059 =
|
|
CASE_guard51968_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q50;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5059 =
|
|
(guard__h351968 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
guard__h351968 != 2'b01 && guard__h351968 != 2'b10 &&
|
|
guard__h351968 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5059 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5059 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h369734 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h369734)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard69734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard69734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 =
|
|
guard__h369734 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard69734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51 or
|
|
guard__h369734)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5089 =
|
|
CASE_guard69734_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q51;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5089 =
|
|
(guard__h369734 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
guard__h369734 != 2'b01 && guard__h369734 != 2'b10 &&
|
|
guard__h369734 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5089 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5089 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h360898 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h360898)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard60898_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard60898_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 =
|
|
guard__h360898 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard60898_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52 or
|
|
guard__h360898)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5119 =
|
|
CASE_guard60898_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q52;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5119 =
|
|
(guard__h360898 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
(guard__h360898 == 2'b01 || guard__h360898 == 2'b10 ||
|
|
guard__h360898 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5119 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5119 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h360898 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h360898)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard60898_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard60898_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 =
|
|
guard__h360898 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard60898_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53 or
|
|
guard__h360898)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5076 =
|
|
CASE_guard60898_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q53;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5076 =
|
|
(guard__h360898 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
guard__h360898 != 2'b01 && guard__h360898 != 2'b10 &&
|
|
guard__h360898 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5076 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5076 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h369734 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (guard__h369734)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard69734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
2'd3:
|
|
CASE_guard69734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 =
|
|
guard__h369734 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
|
|
CASE_guard69734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54 or
|
|
guard__h369734)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5126 =
|
|
CASE_guard69734_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q54;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5126 =
|
|
(guard__h369734 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
|
|
(guard__h369734 == 2'b01 || guard__h369734 == 2'b10 ||
|
|
guard__h369734 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5126 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5126 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h397658 or
|
|
_theResult___fst_exp__h405706 or
|
|
out_exp__h406151 or _theResult___exp__h406148)
|
|
begin
|
|
case (guard__h397658)
|
|
2'b0, 2'b01:
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q59 =
|
|
_theResult___fst_exp__h405706;
|
|
2'b10:
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q59 =
|
|
out_exp__h406151;
|
|
2'b11:
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q59 =
|
|
_theResult___exp__h406148;
|
|
endcase
|
|
end
|
|
always@(guard__h397658 or
|
|
_theResult___fst_exp__h405706 or _theResult___exp__h406148)
|
|
begin
|
|
case (guard__h397658)
|
|
2'b0:
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q60 =
|
|
_theResult___fst_exp__h405706;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q60 =
|
|
_theResult___exp__h406148;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q59 or
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q60 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5916 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5918 or
|
|
_theResult___fst_exp__h405706)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h406226 =
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q59;
|
|
3'd1:
|
|
_theResult___fst_exp__h406226 =
|
|
CASE_guard97658_0b0_theResult___fst_exp05706_0_ETC__q60;
|
|
3'd2:
|
|
_theResult___fst_exp__h406226 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5916;
|
|
3'd3:
|
|
_theResult___fst_exp__h406226 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5918;
|
|
3'd4: _theResult___fst_exp__h406226 = _theResult___fst_exp__h405706;
|
|
default: _theResult___fst_exp__h406226 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h388951 or
|
|
_theResult___fst_exp__h397050 or
|
|
out_exp__h397569 or _theResult___exp__h397566)
|
|
begin
|
|
case (guard__h388951)
|
|
2'b0, 2'b01:
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q61 =
|
|
_theResult___fst_exp__h397050;
|
|
2'b10:
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q61 =
|
|
out_exp__h397569;
|
|
2'b11:
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q61 =
|
|
_theResult___exp__h397566;
|
|
endcase
|
|
end
|
|
always@(guard__h388951 or
|
|
_theResult___fst_exp__h397050 or _theResult___exp__h397566)
|
|
begin
|
|
case (guard__h388951)
|
|
2'b0:
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q62 =
|
|
_theResult___fst_exp__h397050;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q62 =
|
|
_theResult___exp__h397566;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q61 or
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q62 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5694 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5697 or
|
|
_theResult___fst_exp__h397050)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h397644 =
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q61;
|
|
3'd1:
|
|
_theResult___fst_exp__h397644 =
|
|
CASE_guard88951_0b0_theResult___fst_exp97050_0_ETC__q62;
|
|
3'd2:
|
|
_theResult___fst_exp__h397644 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5694;
|
|
3'd3:
|
|
_theResult___fst_exp__h397644 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5697;
|
|
3'd4: _theResult___fst_exp__h397644 = _theResult___fst_exp__h397050;
|
|
default: _theResult___fst_exp__h397644 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h406588 or
|
|
_theResult___fst_exp__h414816 or
|
|
out_exp__h415335 or _theResult___exp__h415332)
|
|
begin
|
|
case (guard__h406588)
|
|
2'b0, 2'b01:
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q67 =
|
|
_theResult___fst_exp__h414816;
|
|
2'b10:
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q67 =
|
|
out_exp__h415335;
|
|
2'b11:
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q67 =
|
|
_theResult___exp__h415332;
|
|
endcase
|
|
end
|
|
always@(guard__h406588 or
|
|
_theResult___fst_exp__h414816 or _theResult___exp__h415332)
|
|
begin
|
|
case (guard__h406588)
|
|
2'b0:
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q68 =
|
|
_theResult___fst_exp__h414816;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q68 =
|
|
_theResult___exp__h415332;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q67 or
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q68 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6241 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6243 or
|
|
_theResult___fst_exp__h414816)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h415410 =
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q67;
|
|
3'd1:
|
|
_theResult___fst_exp__h415410 =
|
|
CASE_guard06588_0b0_theResult___fst_exp14816_0_ETC__q68;
|
|
3'd2:
|
|
_theResult___fst_exp__h415410 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6241;
|
|
3'd3:
|
|
_theResult___fst_exp__h415410 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6243;
|
|
3'd4: _theResult___fst_exp__h415410 = _theResult___fst_exp__h414816;
|
|
default: _theResult___fst_exp__h415410 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h415424 or
|
|
_theResult___fst_exp__h423501 or
|
|
out_exp__h423971 or _theResult___exp__h423968)
|
|
begin
|
|
case (guard__h415424)
|
|
2'b0, 2'b01:
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q72 =
|
|
_theResult___fst_exp__h423501;
|
|
2'b10:
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q72 =
|
|
out_exp__h423971;
|
|
2'b11:
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q72 =
|
|
_theResult___exp__h423968;
|
|
endcase
|
|
end
|
|
always@(guard__h415424 or
|
|
_theResult___fst_exp__h423501 or _theResult___exp__h423968)
|
|
begin
|
|
case (guard__h415424)
|
|
2'b0:
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q73 =
|
|
_theResult___fst_exp__h423501;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q73 =
|
|
_theResult___exp__h423968;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q72 or
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q73 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6310 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6312 or
|
|
_theResult___fst_exp__h423501)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h424046 =
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q72;
|
|
3'd1:
|
|
_theResult___fst_exp__h424046 =
|
|
CASE_guard15424_0b0_theResult___fst_exp23501_0_ETC__q73;
|
|
3'd2:
|
|
_theResult___fst_exp__h424046 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6310;
|
|
3'd3:
|
|
_theResult___fst_exp__h424046 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6312;
|
|
3'd4: _theResult___fst_exp__h424046 = _theResult___fst_exp__h423501;
|
|
default: _theResult___fst_exp__h424046 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h397658 or
|
|
_theResult___snd__h405657 or
|
|
out_sfd__h406152 or _theResult___sfd__h406149)
|
|
begin
|
|
case (guard__h397658)
|
|
2'b0, 2'b01:
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q74 =
|
|
_theResult___snd__h405657[56:34];
|
|
2'b10:
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q74 =
|
|
out_sfd__h406152;
|
|
2'b11:
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q74 =
|
|
_theResult___sfd__h406149;
|
|
endcase
|
|
end
|
|
always@(guard__h397658 or
|
|
_theResult___snd__h405657 or _theResult___sfd__h406149)
|
|
begin
|
|
case (guard__h397658)
|
|
2'b0:
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q75 =
|
|
_theResult___snd__h405657[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q75 =
|
|
_theResult___sfd__h406149;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q74 or
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q75 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6360 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6362 or
|
|
_theResult___snd__h405657)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h406227 =
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q74;
|
|
3'd1:
|
|
_theResult___fst_sfd__h406227 =
|
|
CASE_guard97658_0b0_theResult___snd05657_BITS__ETC__q75;
|
|
3'd2:
|
|
_theResult___fst_sfd__h406227 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6360;
|
|
3'd3:
|
|
_theResult___fst_sfd__h406227 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6362;
|
|
3'd4: _theResult___fst_sfd__h406227 = _theResult___snd__h405657[56:34];
|
|
default: _theResult___fst_sfd__h406227 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h388951 or
|
|
sfdin__h397044 or out_sfd__h397570 or _theResult___sfd__h397567)
|
|
begin
|
|
case (guard__h388951)
|
|
2'b0, 2'b01:
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q76 =
|
|
sfdin__h397044[56:34];
|
|
2'b10:
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q76 =
|
|
out_sfd__h397570;
|
|
2'b11:
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q76 =
|
|
_theResult___sfd__h397567;
|
|
endcase
|
|
end
|
|
always@(guard__h388951 or sfdin__h397044 or _theResult___sfd__h397567)
|
|
begin
|
|
case (guard__h388951)
|
|
2'b0:
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q77 =
|
|
sfdin__h397044[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q77 =
|
|
_theResult___sfd__h397567;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q76 or
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q77 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6341 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6343 or
|
|
sfdin__h397044)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h397645 =
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q76;
|
|
3'd1:
|
|
_theResult___fst_sfd__h397645 =
|
|
CASE_guard88951_0b0_sfdin97044_BITS_56_TO_34_0_ETC__q77;
|
|
3'd2:
|
|
_theResult___fst_sfd__h397645 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6341;
|
|
3'd3:
|
|
_theResult___fst_sfd__h397645 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6343;
|
|
3'd4: _theResult___fst_sfd__h397645 = sfdin__h397044[56:34];
|
|
default: _theResult___fst_sfd__h397645 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h406588 or
|
|
sfdin__h414810 or out_sfd__h415336 or _theResult___sfd__h415333)
|
|
begin
|
|
case (guard__h406588)
|
|
2'b0, 2'b01:
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q78 =
|
|
sfdin__h414810[56:34];
|
|
2'b10:
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q78 =
|
|
out_sfd__h415336;
|
|
2'b11:
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q78 =
|
|
_theResult___sfd__h415333;
|
|
endcase
|
|
end
|
|
always@(guard__h406588 or sfdin__h414810 or _theResult___sfd__h415333)
|
|
begin
|
|
case (guard__h406588)
|
|
2'b0:
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q79 =
|
|
sfdin__h414810[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q79 =
|
|
_theResult___sfd__h415333;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q78 or
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q79 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6387 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6389 or
|
|
sfdin__h414810)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h415411 =
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q78;
|
|
3'd1:
|
|
_theResult___fst_sfd__h415411 =
|
|
CASE_guard06588_0b0_sfdin14810_BITS_56_TO_34_0_ETC__q79;
|
|
3'd2:
|
|
_theResult___fst_sfd__h415411 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6387;
|
|
3'd3:
|
|
_theResult___fst_sfd__h415411 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6389;
|
|
3'd4: _theResult___fst_sfd__h415411 = sfdin__h414810[56:34];
|
|
default: _theResult___fst_sfd__h415411 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h415424 or
|
|
_theResult___snd__h423447 or
|
|
out_sfd__h423972 or _theResult___sfd__h423969)
|
|
begin
|
|
case (guard__h415424)
|
|
2'b0, 2'b01:
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q80 =
|
|
_theResult___snd__h423447[56:34];
|
|
2'b10:
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q80 =
|
|
out_sfd__h423972;
|
|
2'b11:
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q80 =
|
|
_theResult___sfd__h423969;
|
|
endcase
|
|
end
|
|
always@(guard__h415424 or
|
|
_theResult___snd__h423447 or _theResult___sfd__h423969)
|
|
begin
|
|
case (guard__h415424)
|
|
2'b0:
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q81 =
|
|
_theResult___snd__h423447[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q81 =
|
|
_theResult___sfd__h423969;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q80 or
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q81 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6406 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6408 or
|
|
_theResult___snd__h423447)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h424047 =
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q80;
|
|
3'd1:
|
|
_theResult___fst_sfd__h424047 =
|
|
CASE_guard15424_0b0_theResult___snd23447_BITS__ETC__q81;
|
|
3'd2:
|
|
_theResult___fst_sfd__h424047 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6406;
|
|
3'd3:
|
|
_theResult___fst_sfd__h424047 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6408;
|
|
3'd4: _theResult___fst_sfd__h424047 = _theResult___snd__h423447[56:34];
|
|
default: _theResult___fst_sfd__h424047 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h388951 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h388951)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard88951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q82 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard88951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q82 =
|
|
guard__h388951 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard88951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q82 or
|
|
guard__h388951)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6438 =
|
|
CASE_guard88951_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q82;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6438 =
|
|
(guard__h388951 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
guard__h388951 != 2'b01 && guard__h388951 != 2'b10 &&
|
|
guard__h388951 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6438 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6438 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h388951 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h388951)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard88951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard88951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 =
|
|
guard__h388951 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard88951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83 or
|
|
guard__h388951)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6494 =
|
|
CASE_guard88951_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q83;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6494 =
|
|
(guard__h388951 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
(guard__h388951 == 2'b01 || guard__h388951 == 2'b10 ||
|
|
guard__h388951 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6494 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6494 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h397658 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h397658)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard97658_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard97658_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 =
|
|
guard__h397658 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard97658_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84 or
|
|
guard__h397658)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6501 =
|
|
CASE_guard97658_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q84;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6501 =
|
|
(guard__h397658 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
(guard__h397658 == 2'b01 || guard__h397658 == 2'b10 ||
|
|
guard__h397658 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6501 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6501 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h397658 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h397658)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard97658_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard97658_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 =
|
|
guard__h397658 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard97658_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85 or
|
|
guard__h397658)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6451 =
|
|
CASE_guard97658_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q85;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6451 =
|
|
(guard__h397658 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
guard__h397658 != 2'b01 && guard__h397658 != 2'b10 &&
|
|
guard__h397658 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6451 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6451 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h406588 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h406588)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard06588_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard06588_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 =
|
|
guard__h406588 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard06588_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86 or
|
|
guard__h406588)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6511 =
|
|
CASE_guard06588_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q86;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6511 =
|
|
(guard__h406588 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
(guard__h406588 == 2'b01 || guard__h406588 == 2'b10 ||
|
|
guard__h406588 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6511 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6511 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h406588 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h406588)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard06588_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard06588_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 =
|
|
guard__h406588 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard06588_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87 or
|
|
guard__h406588)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6468 =
|
|
CASE_guard06588_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q87;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6468 =
|
|
(guard__h406588 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
guard__h406588 != 2'b01 && guard__h406588 != 2'b10 &&
|
|
guard__h406588 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6468 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6468 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h415424 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h415424)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard15424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard15424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 =
|
|
guard__h415424 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard15424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88 or
|
|
guard__h415424)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6518 =
|
|
CASE_guard15424_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q88;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6518 =
|
|
(guard__h415424 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
(guard__h415424 == 2'b01 || guard__h415424 == 2'b10 ||
|
|
guard__h415424 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6518 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6518 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h415424 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (guard__h415424)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard15424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
2'd3:
|
|
CASE_guard15424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 =
|
|
guard__h415424 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
|
|
CASE_guard15424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89 or
|
|
guard__h415424)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6481 =
|
|
CASE_guard15424_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q89;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6481 =
|
|
(guard__h415424 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
|
|
guard__h415424 != 2'b01 && guard__h415424 != 2'b10 &&
|
|
guard__h415424 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6481 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6481 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6504 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6504 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h443346 or
|
|
_theResult___fst_exp__h451394 or
|
|
out_exp__h451839 or _theResult___exp__h451836)
|
|
begin
|
|
case (guard__h443346)
|
|
2'b0, 2'b01:
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q94 =
|
|
_theResult___fst_exp__h451394;
|
|
2'b10:
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q94 =
|
|
out_exp__h451839;
|
|
2'b11:
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q94 =
|
|
_theResult___exp__h451836;
|
|
endcase
|
|
end
|
|
always@(guard__h443346 or
|
|
_theResult___fst_exp__h451394 or _theResult___exp__h451836)
|
|
begin
|
|
case (guard__h443346)
|
|
2'b0:
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q95 =
|
|
_theResult___fst_exp__h451394;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q95 =
|
|
_theResult___exp__h451836;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q94 or
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q95 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7308 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7310 or
|
|
_theResult___fst_exp__h451394)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h451914 =
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q94;
|
|
3'd1:
|
|
_theResult___fst_exp__h451914 =
|
|
CASE_guard43346_0b0_theResult___fst_exp51394_0_ETC__q95;
|
|
3'd2:
|
|
_theResult___fst_exp__h451914 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7308;
|
|
3'd3:
|
|
_theResult___fst_exp__h451914 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7310;
|
|
3'd4: _theResult___fst_exp__h451914 = _theResult___fst_exp__h451394;
|
|
default: _theResult___fst_exp__h451914 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h434639 or
|
|
_theResult___fst_exp__h442738 or
|
|
out_exp__h443257 or _theResult___exp__h443254)
|
|
begin
|
|
case (guard__h434639)
|
|
2'b0, 2'b01:
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q96 =
|
|
_theResult___fst_exp__h442738;
|
|
2'b10:
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q96 =
|
|
out_exp__h443257;
|
|
2'b11:
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q96 =
|
|
_theResult___exp__h443254;
|
|
endcase
|
|
end
|
|
always@(guard__h434639 or
|
|
_theResult___fst_exp__h442738 or _theResult___exp__h443254)
|
|
begin
|
|
case (guard__h434639)
|
|
2'b0:
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q97 =
|
|
_theResult___fst_exp__h442738;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q97 =
|
|
_theResult___exp__h443254;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q96 or
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q97 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7086 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7089 or
|
|
_theResult___fst_exp__h442738)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h443332 =
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q96;
|
|
3'd1:
|
|
_theResult___fst_exp__h443332 =
|
|
CASE_guard34639_0b0_theResult___fst_exp42738_0_ETC__q97;
|
|
3'd2:
|
|
_theResult___fst_exp__h443332 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7086;
|
|
3'd3:
|
|
_theResult___fst_exp__h443332 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7089;
|
|
3'd4: _theResult___fst_exp__h443332 = _theResult___fst_exp__h442738;
|
|
default: _theResult___fst_exp__h443332 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h452276 or
|
|
_theResult___fst_exp__h460504 or
|
|
out_exp__h461023 or _theResult___exp__h461020)
|
|
begin
|
|
case (guard__h452276)
|
|
2'b0, 2'b01:
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q102 =
|
|
_theResult___fst_exp__h460504;
|
|
2'b10:
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q102 =
|
|
out_exp__h461023;
|
|
2'b11:
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q102 =
|
|
_theResult___exp__h461020;
|
|
endcase
|
|
end
|
|
always@(guard__h452276 or
|
|
_theResult___fst_exp__h460504 or _theResult___exp__h461020)
|
|
begin
|
|
case (guard__h452276)
|
|
2'b0:
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q103 =
|
|
_theResult___fst_exp__h460504;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q103 =
|
|
_theResult___exp__h461020;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q102 or
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q103 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7633 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7635 or
|
|
_theResult___fst_exp__h460504)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h461098 =
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q102;
|
|
3'd1:
|
|
_theResult___fst_exp__h461098 =
|
|
CASE_guard52276_0b0_theResult___fst_exp60504_0_ETC__q103;
|
|
3'd2:
|
|
_theResult___fst_exp__h461098 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7633;
|
|
3'd3:
|
|
_theResult___fst_exp__h461098 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7635;
|
|
3'd4: _theResult___fst_exp__h461098 = _theResult___fst_exp__h460504;
|
|
default: _theResult___fst_exp__h461098 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h461112 or
|
|
_theResult___fst_exp__h469189 or
|
|
out_exp__h469659 or _theResult___exp__h469656)
|
|
begin
|
|
case (guard__h461112)
|
|
2'b0, 2'b01:
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q107 =
|
|
_theResult___fst_exp__h469189;
|
|
2'b10:
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q107 =
|
|
out_exp__h469659;
|
|
2'b11:
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q107 =
|
|
_theResult___exp__h469656;
|
|
endcase
|
|
end
|
|
always@(guard__h461112 or
|
|
_theResult___fst_exp__h469189 or _theResult___exp__h469656)
|
|
begin
|
|
case (guard__h461112)
|
|
2'b0:
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q108 =
|
|
_theResult___fst_exp__h469189;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q108 =
|
|
_theResult___exp__h469656;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q107 or
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q108 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7702 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7704 or
|
|
_theResult___fst_exp__h469189)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_exp__h469734 =
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q107;
|
|
3'd1:
|
|
_theResult___fst_exp__h469734 =
|
|
CASE_guard61112_0b0_theResult___fst_exp69189_0_ETC__q108;
|
|
3'd2:
|
|
_theResult___fst_exp__h469734 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7702;
|
|
3'd3:
|
|
_theResult___fst_exp__h469734 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7704;
|
|
3'd4: _theResult___fst_exp__h469734 = _theResult___fst_exp__h469189;
|
|
default: _theResult___fst_exp__h469734 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h443346 or
|
|
_theResult___snd__h451345 or
|
|
out_sfd__h451840 or _theResult___sfd__h451837)
|
|
begin
|
|
case (guard__h443346)
|
|
2'b0, 2'b01:
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q109 =
|
|
_theResult___snd__h451345[56:34];
|
|
2'b10:
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q109 =
|
|
out_sfd__h451840;
|
|
2'b11:
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q109 =
|
|
_theResult___sfd__h451837;
|
|
endcase
|
|
end
|
|
always@(guard__h443346 or
|
|
_theResult___snd__h451345 or _theResult___sfd__h451837)
|
|
begin
|
|
case (guard__h443346)
|
|
2'b0:
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q110 =
|
|
_theResult___snd__h451345[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q110 =
|
|
_theResult___sfd__h451837;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q109 or
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q110 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7752 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7754 or
|
|
_theResult___snd__h451345)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h451915 =
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q109;
|
|
3'd1:
|
|
_theResult___fst_sfd__h451915 =
|
|
CASE_guard43346_0b0_theResult___snd51345_BITS__ETC__q110;
|
|
3'd2:
|
|
_theResult___fst_sfd__h451915 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7752;
|
|
3'd3:
|
|
_theResult___fst_sfd__h451915 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7754;
|
|
3'd4: _theResult___fst_sfd__h451915 = _theResult___snd__h451345[56:34];
|
|
default: _theResult___fst_sfd__h451915 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h434639 or
|
|
sfdin__h442732 or out_sfd__h443258 or _theResult___sfd__h443255)
|
|
begin
|
|
case (guard__h434639)
|
|
2'b0, 2'b01:
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q111 =
|
|
sfdin__h442732[56:34];
|
|
2'b10:
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q111 =
|
|
out_sfd__h443258;
|
|
2'b11:
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q111 =
|
|
_theResult___sfd__h443255;
|
|
endcase
|
|
end
|
|
always@(guard__h434639 or sfdin__h442732 or _theResult___sfd__h443255)
|
|
begin
|
|
case (guard__h434639)
|
|
2'b0:
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q112 =
|
|
sfdin__h442732[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q112 =
|
|
_theResult___sfd__h443255;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q111 or
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q112 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7733 or
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7735 or
|
|
sfdin__h442732)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h443333 =
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q111;
|
|
3'd1:
|
|
_theResult___fst_sfd__h443333 =
|
|
CASE_guard34639_0b0_sfdin42732_BITS_56_TO_34_0_ETC__q112;
|
|
3'd2:
|
|
_theResult___fst_sfd__h443333 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7733;
|
|
3'd3:
|
|
_theResult___fst_sfd__h443333 =
|
|
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7735;
|
|
3'd4: _theResult___fst_sfd__h443333 = sfdin__h442732[56:34];
|
|
default: _theResult___fst_sfd__h443333 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h452276 or
|
|
sfdin__h460498 or out_sfd__h461024 or _theResult___sfd__h461021)
|
|
begin
|
|
case (guard__h452276)
|
|
2'b0, 2'b01:
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q113 =
|
|
sfdin__h460498[56:34];
|
|
2'b10:
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q113 =
|
|
out_sfd__h461024;
|
|
2'b11:
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q113 =
|
|
_theResult___sfd__h461021;
|
|
endcase
|
|
end
|
|
always@(guard__h452276 or sfdin__h460498 or _theResult___sfd__h461021)
|
|
begin
|
|
case (guard__h452276)
|
|
2'b0:
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q114 =
|
|
sfdin__h460498[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q114 =
|
|
_theResult___sfd__h461021;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q113 or
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q114 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7779 or
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7781 or
|
|
sfdin__h460498)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h461099 =
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q113;
|
|
3'd1:
|
|
_theResult___fst_sfd__h461099 =
|
|
CASE_guard52276_0b0_sfdin60498_BITS_56_TO_34_0_ETC__q114;
|
|
3'd2:
|
|
_theResult___fst_sfd__h461099 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7779;
|
|
3'd3:
|
|
_theResult___fst_sfd__h461099 =
|
|
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7781;
|
|
3'd4: _theResult___fst_sfd__h461099 = sfdin__h460498[56:34];
|
|
default: _theResult___fst_sfd__h461099 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h461112 or
|
|
_theResult___snd__h469135 or
|
|
out_sfd__h469660 or _theResult___sfd__h469657)
|
|
begin
|
|
case (guard__h461112)
|
|
2'b0, 2'b01:
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q115 =
|
|
_theResult___snd__h469135[56:34];
|
|
2'b10:
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q115 =
|
|
out_sfd__h469660;
|
|
2'b11:
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q115 =
|
|
_theResult___sfd__h469657;
|
|
endcase
|
|
end
|
|
always@(guard__h461112 or
|
|
_theResult___snd__h469135 or _theResult___sfd__h469657)
|
|
begin
|
|
case (guard__h461112)
|
|
2'b0:
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q116 =
|
|
_theResult___snd__h469135[56:34];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q116 =
|
|
_theResult___sfd__h469657;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q115 or
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q116 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7798 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7800 or
|
|
_theResult___snd__h469135)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
_theResult___fst_sfd__h469735 =
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q115;
|
|
3'd1:
|
|
_theResult___fst_sfd__h469735 =
|
|
CASE_guard61112_0b0_theResult___snd69135_BITS__ETC__q116;
|
|
3'd2:
|
|
_theResult___fst_sfd__h469735 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7798;
|
|
3'd3:
|
|
_theResult___fst_sfd__h469735 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7800;
|
|
3'd4: _theResult___fst_sfd__h469735 = _theResult___snd__h469135[56:34];
|
|
default: _theResult___fst_sfd__h469735 = 23'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h434639 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h434639)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard34639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard34639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 =
|
|
guard__h434639 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard34639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117 or
|
|
guard__h434639)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7886 =
|
|
CASE_guard34639_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q117;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7886 =
|
|
(guard__h434639 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
(guard__h434639 == 2'b01 || guard__h434639 == 2'b10 ||
|
|
guard__h434639 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7886 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7886 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h434639 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h434639)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard34639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard34639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 =
|
|
guard__h434639 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard34639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118 or
|
|
guard__h434639)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7830 =
|
|
CASE_guard34639_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q118;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7830 =
|
|
(guard__h434639 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
guard__h434639 != 2'b01 && guard__h434639 != 2'b10 &&
|
|
guard__h434639 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7830 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7830 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h443346 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h443346)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard43346_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard43346_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 =
|
|
guard__h443346 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard43346_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119 or
|
|
guard__h443346)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7893 =
|
|
CASE_guard43346_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q119;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7893 =
|
|
(guard__h443346 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
(guard__h443346 == 2'b01 || guard__h443346 == 2'b10 ||
|
|
guard__h443346 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7893 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7893 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h443346 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h443346)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard43346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard43346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 =
|
|
guard__h443346 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard43346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120 or
|
|
guard__h443346)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7843 =
|
|
CASE_guard43346_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q120;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7843 =
|
|
(guard__h443346 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
guard__h443346 != 2'b01 && guard__h443346 != 2'b10 &&
|
|
guard__h443346 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7843 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7843 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h452276 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h452276)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard52276_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard52276_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 =
|
|
guard__h452276 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard52276_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121 or
|
|
guard__h452276)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7903 =
|
|
CASE_guard52276_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q121;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7903 =
|
|
(guard__h452276 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
(guard__h452276 == 2'b01 || guard__h452276 == 2'b10 ||
|
|
guard__h452276 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7903 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7903 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h452276 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h452276)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard52276_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard52276_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 =
|
|
guard__h452276 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard52276_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122 or
|
|
guard__h452276)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7860 =
|
|
CASE_guard52276_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q122;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7860 =
|
|
(guard__h452276 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
guard__h452276 != 2'b01 && guard__h452276 != 2'b10 &&
|
|
guard__h452276 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7860 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7860 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h461112 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h461112)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard61112_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard61112_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 =
|
|
guard__h461112 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard61112_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or
|
|
guard__h461112)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7910 =
|
|
CASE_guard61112_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7910 =
|
|
(guard__h461112 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
(guard__h461112 == 2'b01 || guard__h461112 == 2'b10 ||
|
|
guard__h461112 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7910 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7910 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(guard__h461112 or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (guard__h461112)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard61112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
2'd3:
|
|
CASE_guard61112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 =
|
|
guard__h461112 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
|
|
CASE_guard61112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124 or
|
|
guard__h461112)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7873 =
|
|
CASE_guard61112_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q124;
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7873 =
|
|
(guard__h461112 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
|
|
guard__h461112 != 2'b01 && guard__h461112 != 2'b10 &&
|
|
guard__h461112 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7873 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7873 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7896 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7896 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
|
|
3'd4 &&
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
|
|
3'd4 ||
|
|
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put or
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8389 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
|
|
5'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8389 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put;
|
|
5'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8389 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8389 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 ||
|
|
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
|
|
endcase
|
|
end
|
|
always@(guard__h490662 or
|
|
_theResult___fst_exp__h498623 or _theResult___exp__h499278)
|
|
begin
|
|
case (guard__h490662)
|
|
2'b0:
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q135 =
|
|
_theResult___fst_exp__h498623;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q135 =
|
|
_theResult___exp__h499278;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h498623 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9003 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9001 or
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q135)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9007 =
|
|
_theResult___fst_exp__h498623;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9007 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9003;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9007 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9001;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9007 =
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q135;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9007 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h490662 or
|
|
_theResult___fst_exp__h498623 or
|
|
out_exp__h499281 or _theResult___exp__h499278)
|
|
begin
|
|
case (guard__h490662)
|
|
2'b0, 2'b01:
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q136 =
|
|
_theResult___fst_exp__h498623;
|
|
2'b10:
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q136 =
|
|
out_exp__h499281;
|
|
2'b11:
|
|
CASE_guard90662_0b0_theResult___fst_exp98623_0_ETC__q136 =
|
|
_theResult___exp__h499278;
|
|
endcase
|
|
end
|
|
always@(guard__h490662 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h490662)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard90662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
2'd3:
|
|
CASE_guard90662_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q137 =
|
|
guard__h490662 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h490662)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
|
|
(guard__h490662 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
|
|
(guard__h490662 == 2'b01 || guard__h490662 == 2'b10 ||
|
|
guard__h490662 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q138 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
endcase
|
|
end
|
|
always@(guard__h509043 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h509043)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard09043_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
2'd3:
|
|
CASE_guard09043_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q139 =
|
|
guard__h509043 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509043)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
|
|
(guard__h509043 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
|
|
(guard__h509043 == 2'b01 || guard__h509043 == 2'b10 ||
|
|
guard__h509043 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q140 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
endcase
|
|
end
|
|
always@(guard__h499974 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h499974)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard99974_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
2'd3:
|
|
CASE_guard99974_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q141 =
|
|
guard__h499974 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h499974)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
|
|
(guard__h499974 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
|
|
(guard__h499974 == 2'b01 || guard__h499974 == 2'b10 ||
|
|
guard__h499974 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q142 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
|
|
endcase
|
|
end
|
|
always@(guard__h568664 or
|
|
_theResult___fst_exp__h576625 or _theResult___exp__h577280)
|
|
begin
|
|
case (guard__h568664)
|
|
2'b0:
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q152 =
|
|
_theResult___fst_exp__h576625;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q152 =
|
|
_theResult___exp__h577280;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h576625 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9713 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9711 or
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q152)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9717 =
|
|
_theResult___fst_exp__h576625;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9717 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9713;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9717 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9711;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9717 =
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q152;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9717 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h568664 or
|
|
_theResult___fst_exp__h576625 or
|
|
out_exp__h577283 or _theResult___exp__h577280)
|
|
begin
|
|
case (guard__h568664)
|
|
2'b0, 2'b01:
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q153 =
|
|
_theResult___fst_exp__h576625;
|
|
2'b10:
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q153 =
|
|
out_exp__h577283;
|
|
2'b11:
|
|
CASE_guard68664_0b0_theResult___fst_exp76625_0_ETC__q153 =
|
|
_theResult___exp__h577280;
|
|
endcase
|
|
end
|
|
always@(guard__h568664 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h568664)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard68664_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
2'd3:
|
|
CASE_guard68664_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q154 =
|
|
guard__h568664 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568664)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
|
|
(guard__h568664 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
(guard__h568664 == 2'b01 || guard__h568664 == 2'b10 ||
|
|
guard__h568664 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q155 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(guard__h577976 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h577976)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard77976_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
2'd3:
|
|
CASE_guard77976_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q156 =
|
|
guard__h577976 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577976)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
|
|
(guard__h577976 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
(guard__h577976 == 2'b01 || guard__h577976 == 2'b10 ||
|
|
guard__h577976 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q157 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(guard__h587045 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h587045)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard87045_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
2'd3:
|
|
CASE_guard87045_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q158 =
|
|
guard__h587045 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587045)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
|
|
(guard__h587045 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
(guard__h587045 == 2'b01 || guard__h587045 == 2'b10 ||
|
|
guard__h587045 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q159 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(guard__h577976 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h577976)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard77976_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
2'd3:
|
|
CASE_guard77976_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q160 =
|
|
guard__h577976 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h577976)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
|
|
(guard__h577976 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
guard__h577976 != 2'b01 && guard__h577976 != 2'b10 &&
|
|
guard__h577976 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q161 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(guard__h568664 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h568664)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard68664_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
2'd3:
|
|
CASE_guard68664_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q162 =
|
|
guard__h568664 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h568664)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
|
|
(guard__h568664 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
guard__h568664 != 2'b01 && guard__h568664 != 2'b10 &&
|
|
guard__h568664 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(guard__h587045 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h587045)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard87045_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
2'd3:
|
|
CASE_guard87045_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q164 =
|
|
guard__h587045 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587045)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
|
|
(guard__h587045 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
|
|
guard__h587045 != 2'b01 && guard__h587045 != 2'b10 &&
|
|
guard__h587045 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
|
|
endcase
|
|
end
|
|
always@(guard__h529463 or
|
|
_theResult___fst_exp__h537424 or _theResult___exp__h538079)
|
|
begin
|
|
case (guard__h529463)
|
|
2'b0:
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q175 =
|
|
_theResult___fst_exp__h537424;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q175 =
|
|
_theResult___exp__h538079;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h537424 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10476 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10474 or
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q175)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10480 =
|
|
_theResult___fst_exp__h537424;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10480 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10476;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10480 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10474;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10480 =
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q175;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10480 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h529463 or
|
|
_theResult___fst_exp__h537424 or
|
|
out_exp__h538082 or _theResult___exp__h538079)
|
|
begin
|
|
case (guard__h529463)
|
|
2'b0, 2'b01:
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q176 =
|
|
_theResult___fst_exp__h537424;
|
|
2'b10:
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q176 =
|
|
out_exp__h538082;
|
|
2'b11:
|
|
CASE_guard29463_0b0_theResult___fst_exp37424_0_ETC__q176 =
|
|
_theResult___exp__h538079;
|
|
endcase
|
|
end
|
|
always@(guard__h538775 or
|
|
_theResult___fst_exp__h547001 or _theResult___exp__h547730)
|
|
begin
|
|
case (guard__h538775)
|
|
2'b0:
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q177 =
|
|
_theResult___fst_exp__h547001;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q177 =
|
|
_theResult___exp__h547730;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h547001 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10514 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10512 or
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q177)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10518 =
|
|
_theResult___fst_exp__h547001;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10518 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10514;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10518 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10512;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10518 =
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q177;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10518 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h538775 or
|
|
_theResult___fst_exp__h547001 or
|
|
out_exp__h547733 or _theResult___exp__h547730)
|
|
begin
|
|
case (guard__h538775)
|
|
2'b0, 2'b01:
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q178 =
|
|
_theResult___fst_exp__h547001;
|
|
2'b10:
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q178 =
|
|
out_exp__h547733;
|
|
2'b11:
|
|
CASE_guard38775_0b0_theResult___fst_exp47001_0_ETC__q178 =
|
|
_theResult___exp__h547730;
|
|
endcase
|
|
end
|
|
always@(guard__h577976 or
|
|
_theResult___fst_exp__h586202 or _theResult___exp__h586931)
|
|
begin
|
|
case (guard__h577976)
|
|
2'b0:
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q179 =
|
|
_theResult___fst_exp__h586202;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q179 =
|
|
_theResult___exp__h586931;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h586202 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9751 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9749 or
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q179)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9755 =
|
|
_theResult___fst_exp__h586202;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9755 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9751;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9755 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9749;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9755 =
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q179;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9755 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h577976 or
|
|
_theResult___fst_exp__h586202 or
|
|
out_exp__h586934 or _theResult___exp__h586931)
|
|
begin
|
|
case (guard__h577976)
|
|
2'b0, 2'b01:
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q180 =
|
|
_theResult___fst_exp__h586202;
|
|
2'b10:
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q180 =
|
|
out_exp__h586934;
|
|
2'b11:
|
|
CASE_guard77976_0b0_theResult___fst_exp86202_0_ETC__q180 =
|
|
_theResult___exp__h586931;
|
|
endcase
|
|
end
|
|
always@(guard__h547844 or
|
|
_theResult___fst_exp__h555834 or _theResult___exp__h556514)
|
|
begin
|
|
case (guard__h547844)
|
|
2'b0:
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q181 =
|
|
_theResult___fst_exp__h555834;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q181 =
|
|
_theResult___exp__h556514;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h555834 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10545 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10543 or
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q181)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10549 =
|
|
_theResult___fst_exp__h555834;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10549 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10545;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10549 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10543;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10549 =
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q181;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10549 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h547844 or
|
|
_theResult___fst_exp__h555834 or
|
|
out_exp__h556517 or _theResult___exp__h556514)
|
|
begin
|
|
case (guard__h547844)
|
|
2'b0, 2'b01:
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q182 =
|
|
_theResult___fst_exp__h555834;
|
|
2'b10:
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q182 =
|
|
out_exp__h556517;
|
|
2'b11:
|
|
CASE_guard47844_0b0_theResult___fst_exp55834_0_ETC__q182 =
|
|
_theResult___exp__h556514;
|
|
endcase
|
|
end
|
|
always@(guard__h587045 or
|
|
_theResult___fst_exp__h595035 or _theResult___exp__h595715)
|
|
begin
|
|
case (guard__h587045)
|
|
2'b0:
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q183 =
|
|
_theResult___fst_exp__h595035;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q183 =
|
|
_theResult___exp__h595715;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h595035 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9782 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9780 or
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q183)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9786 =
|
|
_theResult___fst_exp__h595035;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9786 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9782;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9786 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9780;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9786 =
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q183;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9786 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h587045 or
|
|
_theResult___fst_exp__h595035 or
|
|
out_exp__h595718 or _theResult___exp__h595715)
|
|
begin
|
|
case (guard__h587045)
|
|
2'b0, 2'b01:
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q184 =
|
|
_theResult___fst_exp__h595035;
|
|
2'b10:
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q184 =
|
|
out_exp__h595718;
|
|
2'b11:
|
|
CASE_guard87045_0b0_theResult___fst_exp95035_0_ETC__q184 =
|
|
_theResult___exp__h595715;
|
|
endcase
|
|
end
|
|
always@(guard__h538775 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h538775)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard38775_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
2'd3:
|
|
CASE_guard38775_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q185 =
|
|
guard__h538775 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538775)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
|
|
(guard__h538775 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
(guard__h538775 == 2'b01 || guard__h538775 == 2'b10 ||
|
|
guard__h538775 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q186 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(guard__h529463 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h529463)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard29463_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
2'd3:
|
|
CASE_guard29463_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q187 =
|
|
guard__h529463 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529463)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
|
|
(guard__h529463 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
(guard__h529463 == 2'b01 || guard__h529463 == 2'b10 ||
|
|
guard__h529463 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q188 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(guard__h547844 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h547844)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard47844_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
2'd3:
|
|
CASE_guard47844_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q189 =
|
|
guard__h547844 == 2'b11 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547844)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
|
|
(guard__h547844 == 2'b0) ?
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
(guard__h547844 == 2'b01 || guard__h547844 == 2'b10 ||
|
|
guard__h547844 == 2'b11) &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q190 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(guard__h538775 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h538775)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard38775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
2'd3:
|
|
CASE_guard38775_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q191 =
|
|
guard__h538775 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h538775)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
|
|
(guard__h538775 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
guard__h538775 != 2'b01 && guard__h538775 != 2'b10 &&
|
|
guard__h538775 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q192 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(guard__h529463 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h529463)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard29463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
2'd3:
|
|
CASE_guard29463_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q193 =
|
|
guard__h529463 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h529463)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
|
|
(guard__h529463 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
guard__h529463 != 2'b01 && guard__h529463 != 2'b10 &&
|
|
guard__h529463 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(guard__h547844 or coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (guard__h547844)
|
|
2'b0, 2'b01, 2'b10:
|
|
CASE_guard47844_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
2'd3:
|
|
CASE_guard47844_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q195 =
|
|
guard__h547844 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h547844)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
|
|
(guard__h547844 == 2'b0) ?
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
|
|
guard__h547844 != 2'b01 && guard__h547844 != 2'b10 &&
|
|
guard__h547844 != 2'b11 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
|
|
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
|
|
endcase
|
|
end
|
|
always@(guard__h529463 or
|
|
_theResult___snd__h537375 or _theResult___sfd__h538080)
|
|
begin
|
|
case (guard__h529463)
|
|
2'b0:
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q197 =
|
|
_theResult___snd__h537375[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q197 =
|
|
_theResult___sfd__h538080;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___snd__h537375 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10571 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10569 or
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q197)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10575 =
|
|
_theResult___snd__h537375[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10575 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10571;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10575 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10569;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10575 =
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q197;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10575 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h529463 or
|
|
_theResult___snd__h537375 or
|
|
out_sfd__h538083 or _theResult___sfd__h538080)
|
|
begin
|
|
case (guard__h529463)
|
|
2'b0, 2'b01:
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q198 =
|
|
_theResult___snd__h537375[56:5];
|
|
2'b10:
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q198 =
|
|
out_sfd__h538083;
|
|
2'b11:
|
|
CASE_guard29463_0b0_theResult___snd37375_BITS__ETC__q198 =
|
|
_theResult___sfd__h538080;
|
|
endcase
|
|
end
|
|
always@(guard__h547844 or
|
|
_theResult___snd__h555780 or _theResult___sfd__h556515)
|
|
begin
|
|
case (guard__h547844)
|
|
2'b0:
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q199 =
|
|
_theResult___snd__h555780[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q199 =
|
|
_theResult___sfd__h556515;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___snd__h555780 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10616 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10614 or
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q199)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10620 =
|
|
_theResult___snd__h555780[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10620 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10616;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10620 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10614;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10620 =
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q199;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10620 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h547844 or
|
|
_theResult___snd__h555780 or
|
|
out_sfd__h556518 or _theResult___sfd__h556515)
|
|
begin
|
|
case (guard__h547844)
|
|
2'b0, 2'b01:
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q200 =
|
|
_theResult___snd__h555780[56:5];
|
|
2'b10:
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q200 =
|
|
out_sfd__h556518;
|
|
2'b11:
|
|
CASE_guard47844_0b0_theResult___snd55780_BITS__ETC__q200 =
|
|
_theResult___sfd__h556515;
|
|
endcase
|
|
end
|
|
always@(guard__h538775 or sfdin__h546995 or _theResult___sfd__h547731)
|
|
begin
|
|
case (guard__h538775)
|
|
2'b0:
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q201 =
|
|
sfdin__h546995[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q201 =
|
|
_theResult___sfd__h547731;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
sfdin__h546995 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10597 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10595 or
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q201)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10601 =
|
|
sfdin__h546995[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10601 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10597;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10601 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d10595;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10601 =
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q201;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10601 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h538775 or
|
|
sfdin__h546995 or out_sfd__h547734 or _theResult___sfd__h547731)
|
|
begin
|
|
case (guard__h538775)
|
|
2'b0, 2'b01:
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q202 =
|
|
sfdin__h546995[56:5];
|
|
2'b10:
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q202 =
|
|
out_sfd__h547734;
|
|
2'b11:
|
|
CASE_guard38775_0b0_sfdin46995_BITS_56_TO_5_0b_ETC__q202 =
|
|
_theResult___sfd__h547731;
|
|
endcase
|
|
end
|
|
always@(guard__h499974 or
|
|
_theResult___fst_exp__h508200 or _theResult___exp__h508929)
|
|
begin
|
|
case (guard__h499974)
|
|
2'b0:
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q203 =
|
|
_theResult___fst_exp__h508200;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q203 =
|
|
_theResult___exp__h508929;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h508200 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9046 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9044 or
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q203)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9050 =
|
|
_theResult___fst_exp__h508200;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9050 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9046;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9050 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9044;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9050 =
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q203;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9050 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h499974 or
|
|
_theResult___fst_exp__h508200 or
|
|
out_exp__h508932 or _theResult___exp__h508929)
|
|
begin
|
|
case (guard__h499974)
|
|
2'b0, 2'b01:
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q204 =
|
|
_theResult___fst_exp__h508200;
|
|
2'b10:
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q204 =
|
|
out_exp__h508932;
|
|
2'b11:
|
|
CASE_guard99974_0b0_theResult___fst_exp08200_0_ETC__q204 =
|
|
_theResult___exp__h508929;
|
|
endcase
|
|
end
|
|
always@(guard__h509043 or
|
|
_theResult___fst_exp__h517033 or _theResult___exp__h517713)
|
|
begin
|
|
case (guard__h509043)
|
|
2'b0:
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q205 =
|
|
_theResult___fst_exp__h517033;
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q205 =
|
|
_theResult___exp__h517713;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___fst_exp__h517033 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9077 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9075 or
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q205)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9081 =
|
|
_theResult___fst_exp__h517033;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9081 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9077;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9081 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9075;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9081 =
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q205;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9081 =
|
|
11'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h509043 or
|
|
_theResult___fst_exp__h517033 or
|
|
out_exp__h517716 or _theResult___exp__h517713)
|
|
begin
|
|
case (guard__h509043)
|
|
2'b0, 2'b01:
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q206 =
|
|
_theResult___fst_exp__h517033;
|
|
2'b10:
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q206 =
|
|
out_exp__h517716;
|
|
2'b11:
|
|
CASE_guard09043_0b0_theResult___fst_exp17033_0_ETC__q206 =
|
|
_theResult___exp__h517713;
|
|
endcase
|
|
end
|
|
always@(guard__h490662 or
|
|
_theResult___snd__h498574 or _theResult___sfd__h499279)
|
|
begin
|
|
case (guard__h490662)
|
|
2'b0:
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q207 =
|
|
_theResult___snd__h498574[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q207 =
|
|
_theResult___sfd__h499279;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___snd__h498574 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9103 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9101 or
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q207)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9107 =
|
|
_theResult___snd__h498574[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9107 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9103;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9107 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9101;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9107 =
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q207;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9107 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h490662 or
|
|
_theResult___snd__h498574 or
|
|
out_sfd__h499282 or _theResult___sfd__h499279)
|
|
begin
|
|
case (guard__h490662)
|
|
2'b0, 2'b01:
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q208 =
|
|
_theResult___snd__h498574[56:5];
|
|
2'b10:
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q208 =
|
|
out_sfd__h499282;
|
|
2'b11:
|
|
CASE_guard90662_0b0_theResult___snd98574_BITS__ETC__q208 =
|
|
_theResult___sfd__h499279;
|
|
endcase
|
|
end
|
|
always@(guard__h499974 or sfdin__h508194 or _theResult___sfd__h508930)
|
|
begin
|
|
case (guard__h499974)
|
|
2'b0:
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q209 =
|
|
sfdin__h508194[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q209 =
|
|
_theResult___sfd__h508930;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
sfdin__h508194 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9130 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128 or
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q209)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9134 =
|
|
sfdin__h508194[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9134 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9130;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9134 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9128;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9134 =
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q209;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9134 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h499974 or
|
|
sfdin__h508194 or out_sfd__h508933 or _theResult___sfd__h508930)
|
|
begin
|
|
case (guard__h499974)
|
|
2'b0, 2'b01:
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q210 =
|
|
sfdin__h508194[56:5];
|
|
2'b10:
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q210 =
|
|
out_sfd__h508933;
|
|
2'b11:
|
|
CASE_guard99974_0b0_sfdin08194_BITS_56_TO_5_0b_ETC__q210 =
|
|
_theResult___sfd__h508930;
|
|
endcase
|
|
end
|
|
always@(guard__h509043 or
|
|
_theResult___snd__h516979 or _theResult___sfd__h517714)
|
|
begin
|
|
case (guard__h509043)
|
|
2'b0:
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q211 =
|
|
_theResult___snd__h516979[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q211 =
|
|
_theResult___sfd__h517714;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___snd__h516979 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9149 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9147 or
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q211)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9153 =
|
|
_theResult___snd__h516979[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9153 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9149;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9153 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9147;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9153 =
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q211;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9153 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h509043 or
|
|
_theResult___snd__h516979 or
|
|
out_sfd__h517717 or _theResult___sfd__h517714)
|
|
begin
|
|
case (guard__h509043)
|
|
2'b0, 2'b01:
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q212 =
|
|
_theResult___snd__h516979[56:5];
|
|
2'b10:
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q212 =
|
|
out_sfd__h517717;
|
|
2'b11:
|
|
CASE_guard09043_0b0_theResult___snd16979_BITS__ETC__q212 =
|
|
_theResult___sfd__h517714;
|
|
endcase
|
|
end
|
|
always@(guard__h568664 or
|
|
_theResult___snd__h576576 or _theResult___sfd__h577281)
|
|
begin
|
|
case (guard__h568664)
|
|
2'b0:
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q213 =
|
|
_theResult___snd__h576576[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q213 =
|
|
_theResult___sfd__h577281;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___snd__h576576 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9808 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9806 or
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q213)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9812 =
|
|
_theResult___snd__h576576[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9812 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9808;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9812 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9806;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9812 =
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q213;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9812 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h568664 or
|
|
_theResult___snd__h576576 or
|
|
out_sfd__h577284 or _theResult___sfd__h577281)
|
|
begin
|
|
case (guard__h568664)
|
|
2'b0, 2'b01:
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q214 =
|
|
_theResult___snd__h576576[56:5];
|
|
2'b10:
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q214 =
|
|
out_sfd__h577284;
|
|
2'b11:
|
|
CASE_guard68664_0b0_theResult___snd76576_BITS__ETC__q214 =
|
|
_theResult___sfd__h577281;
|
|
endcase
|
|
end
|
|
always@(guard__h577976 or sfdin__h586196 or _theResult___sfd__h586932)
|
|
begin
|
|
case (guard__h577976)
|
|
2'b0:
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q215 =
|
|
sfdin__h586196[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q215 =
|
|
_theResult___sfd__h586932;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
sfdin__h586196 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9834 or
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9832 or
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q215)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9838 =
|
|
sfdin__h586196[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9838 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9834;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9838 =
|
|
IF_IF_IF_IF_3074_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d9832;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9838 =
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q215;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9838 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h577976 or
|
|
sfdin__h586196 or out_sfd__h586935 or _theResult___sfd__h586932)
|
|
begin
|
|
case (guard__h577976)
|
|
2'b0, 2'b01:
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q216 =
|
|
sfdin__h586196[56:5];
|
|
2'b10:
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q216 =
|
|
out_sfd__h586935;
|
|
2'b11:
|
|
CASE_guard77976_0b0_sfdin86196_BITS_56_TO_5_0b_ETC__q216 =
|
|
_theResult___sfd__h586932;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10862 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10850 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10839)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1, 5'd2, 5'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10864 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10850;
|
|
5'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10864 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10839;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10864 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10862;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10826 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10781 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10739)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1, 5'd2, 5'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10828 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10781;
|
|
5'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10828 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10739;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10828 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10826;
|
|
endcase
|
|
end
|
|
always@(guard__h587045 or
|
|
_theResult___snd__h594981 or _theResult___sfd__h595716)
|
|
begin
|
|
case (guard__h587045)
|
|
2'b0:
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q217 =
|
|
_theResult___snd__h594981[56:5];
|
|
2'b01, 2'b10, 2'b11:
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q217 =
|
|
_theResult___sfd__h595716;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
_theResult___snd__h594981 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9853 or
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9851 or
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q217)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9857 =
|
|
_theResult___snd__h594981[56:5];
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9857 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9853;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9857 =
|
|
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9851;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9857 =
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q217;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9857 =
|
|
52'd0;
|
|
endcase
|
|
end
|
|
always@(guard__h587045 or
|
|
_theResult___snd__h594981 or
|
|
out_sfd__h595719 or _theResult___sfd__h595716)
|
|
begin
|
|
case (guard__h587045)
|
|
2'b0, 2'b01:
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q218 =
|
|
_theResult___snd__h594981[56:5];
|
|
2'b10:
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q218 =
|
|
out_sfd__h595719;
|
|
2'b11:
|
|
CASE_guard87045_0b0_theResult___snd94981_BITS__ETC__q218 =
|
|
_theResult___sfd__h595716;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10910 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10894 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10879)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1, 5'd2, 5'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10912 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10894;
|
|
5'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10912 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10879;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10912 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10910;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10952 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10938 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10925)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1, 5'd2, 5'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10954 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10938;
|
|
5'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10954 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10925;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10954 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10952;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10994 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10980 or
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10967)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1, 5'd2, 5'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10996 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10980;
|
|
5'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10996 =
|
|
NOT_coreFix_fpuMulDivExe_0_regToExeQ_first__36_ETC___d10967;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10996 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ_first__364_BI_ETC___d10994;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_aluExe_0_regToExeQ$first[367:365])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_367_ETC__q219 =
|
|
coreFix_aluExe_0_regToExeQ$first[367:365];
|
|
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_367_ETC__q219 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_regToExeQ$first or
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_367_ETC__q219)
|
|
begin
|
|
case (coreFix_aluExe_0_regToExeQ$first[384:382])
|
|
3'd3, 3'd2, 3'd1, 3'd0:
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_384_ETC__q220 =
|
|
coreFix_aluExe_0_regToExeQ$first[384:364];
|
|
3'd4:
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_384_ETC__q220 =
|
|
{ coreFix_aluExe_0_regToExeQ$first[384:382],
|
|
9'h0AA,
|
|
coreFix_aluExe_0_regToExeQ$first[372:368],
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_367_ETC__q219,
|
|
coreFix_aluExe_0_regToExeQ$first[364] };
|
|
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_384_ETC__q220 =
|
|
{ 3'd5, 18'h2AAAA };
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_aluExe_0_regToExeQ$first[362:351])
|
|
12'd3860,
|
|
12'd3859,
|
|
12'd3858,
|
|
12'd3857,
|
|
12'd2818,
|
|
12'd2816,
|
|
12'd836,
|
|
12'd835,
|
|
12'd834,
|
|
12'd833,
|
|
12'd832,
|
|
12'd774,
|
|
12'd773,
|
|
12'd772,
|
|
12'd771,
|
|
12'd770,
|
|
12'd769,
|
|
12'd768,
|
|
12'd384,
|
|
12'd324,
|
|
12'd323,
|
|
12'd322,
|
|
12'd321,
|
|
12'd320,
|
|
12'd262,
|
|
12'd261,
|
|
12'd260,
|
|
12'd256,
|
|
12'd2049,
|
|
12'd2048,
|
|
12'd3074,
|
|
12'd3073,
|
|
12'd3072,
|
|
12'd3,
|
|
12'd2,
|
|
12'd1:
|
|
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_362_ETC__q221 =
|
|
coreFix_aluExe_0_regToExeQ$first[362:351];
|
|
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_362_ETC__q221 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_regToExeQ$first)
|
|
begin
|
|
case (coreFix_aluExe_1_regToExeQ$first[367:365])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_367_ETC__q222 =
|
|
coreFix_aluExe_1_regToExeQ$first[367:365];
|
|
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_367_ETC__q222 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_regToExeQ$first or
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_367_ETC__q222)
|
|
begin
|
|
case (coreFix_aluExe_1_regToExeQ$first[384:382])
|
|
3'd3, 3'd2, 3'd1, 3'd0:
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_384_ETC__q223 =
|
|
coreFix_aluExe_1_regToExeQ$first[384:364];
|
|
3'd4:
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_384_ETC__q223 =
|
|
{ coreFix_aluExe_1_regToExeQ$first[384:382],
|
|
9'h0AA,
|
|
coreFix_aluExe_1_regToExeQ$first[372:368],
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_367_ETC__q222,
|
|
coreFix_aluExe_1_regToExeQ$first[364] };
|
|
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_384_ETC__q223 =
|
|
{ 3'd5, 18'h2AAAA };
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_regToExeQ$first)
|
|
begin
|
|
case (coreFix_aluExe_1_regToExeQ$first[362:351])
|
|
12'd3860,
|
|
12'd3859,
|
|
12'd3858,
|
|
12'd3857,
|
|
12'd2818,
|
|
12'd2816,
|
|
12'd836,
|
|
12'd835,
|
|
12'd834,
|
|
12'd833,
|
|
12'd832,
|
|
12'd774,
|
|
12'd773,
|
|
12'd772,
|
|
12'd771,
|
|
12'd770,
|
|
12'd769,
|
|
12'd768,
|
|
12'd384,
|
|
12'd324,
|
|
12'd323,
|
|
12'd322,
|
|
12'd321,
|
|
12'd320,
|
|
12'd262,
|
|
12'd261,
|
|
12'd260,
|
|
12'd256,
|
|
12'd2049,
|
|
12'd2048,
|
|
12'd3074,
|
|
12'd3073,
|
|
12'd3072,
|
|
12'd3,
|
|
12'd2,
|
|
12'd1:
|
|
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_362_ETC__q224 =
|
|
coreFix_aluExe_1_regToExeQ$first[362:351];
|
|
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_362_ETC__q224 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[3:0])
|
|
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 =
|
|
fetchStage$pipelines_0_first[3:0];
|
|
4'd11:
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 = 4'd10;
|
|
4'd12:
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 = 4'd11;
|
|
4'd13:
|
|
IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 = 4'd12;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BIT_4_26_ETC___d12898 =
|
|
4'd13;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[76:65])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_fetchStagepipelines_0_first_BITS_76_TO_6_ETC__q225 =
|
|
fetchStage$pipelines_0_first[76:65];
|
|
default: CASE_fetchStagepipelines_0_first_BITS_76_TO_6_ETC__q225 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[81:79])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_fetchStagepipelines_0_first_BITS_81_TO_7_ETC__q226 =
|
|
fetchStage$pipelines_0_first[81:79];
|
|
default: CASE_fetchStagepipelines_0_first_BITS_81_TO_7_ETC__q226 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
CASE_fetchStagepipelines_0_first_BITS_81_TO_7_ETC__q226)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721 =
|
|
fetchStage$pipelines_0_first[98:78];
|
|
3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721 =
|
|
{ fetchStage$pipelines_0_first[98:96],
|
|
9'h0AA,
|
|
fetchStage$pipelines_0_first[86:82],
|
|
CASE_fetchStagepipelines_0_first_BITS_81_TO_7_ETC__q226,
|
|
fetchStage$pipelines_0_first[78] };
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d12721 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(checkForException___d12829)
|
|
begin
|
|
case (checkForException___d12829[3:0])
|
|
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 =
|
|
checkForException___d12829[3:0];
|
|
4'd11:
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 = 4'd10;
|
|
4'd12:
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 = 4'd11;
|
|
4'd13:
|
|
IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 = 4'd12;
|
|
default: IF_checkForException_2829_BIT_4_2830_THEN_IF_c_ETC___d12927 =
|
|
4'd13;
|
|
endcase
|
|
end
|
|
always@(IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3__ETC___d13004)
|
|
begin
|
|
case (IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3__ETC___d13004)
|
|
4'd0, 4'd1:
|
|
CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 =
|
|
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623_EQ_3__ETC___d13004;
|
|
4'd2: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 = 4'd3;
|
|
4'd3: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 = 4'd4;
|
|
4'd4: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 = 4'd5;
|
|
4'd5: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 = 4'd7;
|
|
4'd6: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 = 4'd8;
|
|
4'd7: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 = 4'd9;
|
|
4'd8: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 = 4'd11;
|
|
default: CASE_IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2623__ETC__q227 =
|
|
4'd14;
|
|
endcase
|
|
end
|
|
always@(k__h659336 or
|
|
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
|
|
begin
|
|
case (k__h659336)
|
|
1'd0:
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 =
|
|
coreFix_aluExe_0_rsAlu$canEnq;
|
|
1'd1:
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 =
|
|
coreFix_aluExe_1_rsAlu$canEnq;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 =
|
|
coreFix_memExe_lsq$enqLdTag[6];
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 =
|
|
coreFix_memExe_lsq$enqStTag[6];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 or
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13160 =
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13160 =
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13160 =
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156;
|
|
endcase
|
|
end
|
|
always@(k__h659336 or
|
|
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
|
|
begin
|
|
case (k__h659336)
|
|
1'd0:
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 =
|
|
!coreFix_aluExe_0_rsAlu$canEnq;
|
|
1'd1:
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 =
|
|
!coreFix_aluExe_1_rsAlu$canEnq;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
regRenamingTable$rename_0_canRename or
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123 or
|
|
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13179 or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 =
|
|
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13179;
|
|
3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 =
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 =
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13184 =
|
|
regRenamingTable$rename_0_canRename &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_10_ETC___d13123;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 =
|
|
!coreFix_memExe_lsq$enqLdTag[6];
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 =
|
|
!coreFix_memExe_lsq$enqStTag[6];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 or
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 or
|
|
specTagManager$canClaim or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13215 =
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 ||
|
|
fetchStage$pipelines_0_first[98:96] == 3'd1 &&
|
|
!specTagManager$canClaim;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13215 =
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13215 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
(!coreFix_memExe_rsMem$canEnq ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210);
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[76:65])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_fetchStagepipelines_1_first_BITS_76_TO_6_ETC__q228 =
|
|
fetchStage$pipelines_1_first[76:65];
|
|
default: CASE_fetchStagepipelines_1_first_BITS_76_TO_6_ETC__q228 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[81:79])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_fetchStagepipelines_1_first_BITS_81_TO_7_ETC__q229 =
|
|
fetchStage$pipelines_1_first[81:79];
|
|
default: CASE_fetchStagepipelines_1_first_BITS_81_TO_7_ETC__q229 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
CASE_fetchStagepipelines_1_first_BITS_81_TO_7_ETC__q229)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[98:96])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275 =
|
|
fetchStage$pipelines_1_first[98:78];
|
|
3'd4:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275 =
|
|
{ fetchStage$pipelines_1_first[98:96],
|
|
9'h0AA,
|
|
fetchStage$pipelines_1_first[86:82],
|
|
CASE_fetchStagepipelines_1_first_BITS_81_TO_7_ETC__q229,
|
|
fetchStage$pipelines_1_first[78] };
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13275 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(idx__h673066 or
|
|
fetchStage$pipelines_0_canDeq or
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13393 or
|
|
coreFix_aluExe_0_rsAlu$canEnq or
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13399 or
|
|
coreFix_aluExe_1_rsAlu$canEnq)
|
|
begin
|
|
case (idx__h673066)
|
|
1'd0:
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13393 ||
|
|
!coreFix_aluExe_0_rsAlu$canEnq;
|
|
1'd1:
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416 =
|
|
fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13399 ||
|
|
!coreFix_aluExe_1_rsAlu$canEnq;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[95:93])
|
|
3'd0, 3'd2:
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q230 =
|
|
!coreFix_memExe_lsq$enqLdTag[6];
|
|
default: CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q230 =
|
|
!coreFix_memExe_lsq$enqStTag[6];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832 or
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 or
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13470 or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13476 =
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 ||
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13470;
|
|
3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13476 =
|
|
!coreFix_memExe_rsMem$canEnq ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 ||
|
|
fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13476 =
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
|
|
fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13476 =
|
|
fetchStage_pipelines_0_first__2595_BIT_4_2622__ETC___d12832;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 or
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13497 =
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13497 =
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 or
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13514 =
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13514 =
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13514 =
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[95:93])
|
|
3'd0, 3'd2:
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q231 =
|
|
coreFix_memExe_lsq$enqLdTag[6];
|
|
default: CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q231 =
|
|
coreFix_memExe_lsq$enqStTag[6];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
regRenamingTable$rename_1_canRename or
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13384 or
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416 or
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13482 or
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13511 or
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13520 or
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13494 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13503)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 =
|
|
!SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416 &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_98_ETC___d13482;
|
|
3'd2:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 =
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13511 &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13520;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 =
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13494 &&
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13503;
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13525 =
|
|
regRenamingTable$rename_1_canRename &&
|
|
NOT_fetchStage_pipelines_1_first__2604_BITS_10_ETC___d13384;
|
|
endcase
|
|
end
|
|
always@(k__h659336 or
|
|
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
|
|
begin
|
|
case (k__h659336)
|
|
1'd0:
|
|
CASE_k59336_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 =
|
|
coreFix_aluExe_0_rsAlu$RDY_enq;
|
|
1'd1:
|
|
CASE_k59336_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q232 =
|
|
coreFix_aluExe_1_rsAlu$RDY_enq;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[95:93])
|
|
3'd0, 3'd2:
|
|
CASE_fetchStagepipelines_0_first_BITS_95_TO_9_ETC__q233 =
|
|
coreFix_memExe_lsq$RDY_enqLd;
|
|
default: CASE_fetchStagepipelines_0_first_BITS_95_TO_9_ETC__q233 =
|
|
coreFix_memExe_lsq$RDY_enqSt;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 or
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13568 =
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13568 =
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13568 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
(!coreFix_memExe_rsMem$canEnq ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210);
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 or
|
|
regRenamingTable_RDY_rename_0_getRename__3034__ETC___d13562 or
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 or
|
|
regRenamingTable$RDY_rename_0_getRename or
|
|
_0_OR_NOT_fetchStage_pipelines_0_first__2595_BI_ETC___d13549 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13566 =
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 ||
|
|
regRenamingTable$RDY_rename_0_getRename &&
|
|
_0_OR_NOT_fetchStage_pipelines_0_first__2595_BI_ETC___d13549;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13566 =
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
|
|
regRenamingTable$RDY_rename_0_getRename;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13566 =
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
!coreFix_memExe_rsMem$canEnq ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 ||
|
|
regRenamingTable_RDY_rename_0_getRename__3034__ETC___d13562;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 or
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13582 =
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13582 =
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13582 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
(!coreFix_memExe_rsMem$canEnq ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210);
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156 or
|
|
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 or
|
|
specTagManager$canClaim or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13589 =
|
|
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__313_ETC___d13177 &&
|
|
(fetchStage$pipelines_0_first[98:96] != 3'd1 ||
|
|
specTagManager$canClaim);
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13589 =
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13589 =
|
|
fetchStage$pipelines_0_first[98:96] != 3'd2 ||
|
|
coreFix_memExe_rsMem$canEnq &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13156;
|
|
endcase
|
|
end
|
|
always@(idx__h673066 or
|
|
fetchStage$pipelines_0_canDeq or
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13605 or
|
|
coreFix_aluExe_0_rsAlu$canEnq or
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13612 or
|
|
coreFix_aluExe_1_rsAlu$canEnq)
|
|
begin
|
|
case (idx__h673066)
|
|
1'd0:
|
|
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__259_ETC___d13616 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13605) &&
|
|
coreFix_aluExe_0_rsAlu$canEnq;
|
|
1'd1:
|
|
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__259_ETC___d13616 =
|
|
(!fetchStage$pipelines_0_canDeq ||
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13612) &&
|
|
coreFix_aluExe_1_rsAlu$canEnq;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_canDeq or
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13624 or
|
|
coreFix_aluExe_0_rsAlu$canEnq or
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13631 or
|
|
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
|
|
begin
|
|
case (fetchStage$pipelines_0_canDeq &&
|
|
NOT_fetchStage_pipelines_0_first__2595_BITS_98_ETC___d13624 ||
|
|
!coreFix_aluExe_0_rsAlu$canEnq ||
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13631)
|
|
1'd0:
|
|
CASE_fetchStagepipelines_0_canDeq_AND_NOT_fet_ETC__q234 =
|
|
coreFix_aluExe_0_rsAlu$RDY_enq;
|
|
1'd1:
|
|
CASE_fetchStagepipelines_0_canDeq_AND_NOT_fet_ETC__q234 =
|
|
coreFix_aluExe_1_rsAlu$RDY_enq;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[95:93])
|
|
3'd0, 3'd2:
|
|
CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q235 =
|
|
coreFix_memExe_lsq$RDY_enqLd;
|
|
default: CASE_fetchStagepipelines_1_first_BITS_95_TO_9_ETC__q235 =
|
|
coreFix_memExe_lsq$RDY_enqSt;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_rsMem$canEnq or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 or
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13658 =
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13658 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
(!coreFix_memExe_rsMem$canEnq ||
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210);
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210 or
|
|
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13669 =
|
|
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3133_co_ETC___d13143;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13669 =
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_98__ETC___d13669 =
|
|
fetchStage$pipelines_0_first[98:96] == 3'd2 &&
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13210;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13645 or
|
|
fetchStage$pipelines_0_canDeq or
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13670 or
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416 or
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13666)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13680 =
|
|
SEL_ARR_fetchStage_pipelines_0_canDeq__2593_AN_ETC___d13416;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13680 =
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13666;
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13680 =
|
|
fetchStage$pipelines_1_first[98:96] == 3'd2 &&
|
|
(fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13645 ||
|
|
fetchStage$pipelines_0_canDeq &&
|
|
fetchStage_pipelines_0_first__2595_BITS_98_TO__ETC___d13670);
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13645 or
|
|
regRenamingTable$RDY_rename_1_getRename or
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13650 or
|
|
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__259_ETC___d13616 or
|
|
regRenamingTable_RDY_rename_1_getRename__3618__ETC___d13636 or
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13638 or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__35_ETC___d13641)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[98:96])
|
|
3'd0, 3'd1:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13655 =
|
|
!SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__259_ETC___d13616 ||
|
|
regRenamingTable_RDY_rename_1_getRename__3618__ETC___d13636;
|
|
3'd3, 3'd4:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13655 =
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13638 ||
|
|
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__35_ETC___d13641;
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_98__ETC___d13655 =
|
|
fetchStage$pipelines_1_first[98:96] != 3'd2 ||
|
|
fetchStage_pipelines_0_canDeq__2593_AND_regRen_ETC___d13645 ||
|
|
regRenamingTable$RDY_rename_1_getRename &&
|
|
NOT_fetchStage_pipelines_0_canDeq__2593_2594_O_ETC___d13650;
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13735 =
|
|
!coreFix_memExe_lsq$enqLdTag[5];
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13735 =
|
|
!coreFix_memExe_lsq$enqStTag[5];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13732 =
|
|
coreFix_memExe_lsq$enqLdTag[5];
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13732 =
|
|
coreFix_memExe_lsq$enqStTag[5];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13741 =
|
|
coreFix_memExe_lsq$enqLdTag[3:0];
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13741 =
|
|
coreFix_memExe_lsq$enqStTag[3:0];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_0_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_0_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13738 =
|
|
coreFix_memExe_lsq$enqLdTag[4:0];
|
|
default: IF_fetchStage_pipelines_0_first__2595_BITS_95__ETC___d13738 =
|
|
coreFix_memExe_lsq$enqStTag[4:0];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13864 =
|
|
coreFix_memExe_lsq$enqLdTag[3:0];
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13864 =
|
|
coreFix_memExe_lsq$enqStTag[3:0];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13862 =
|
|
!coreFix_memExe_lsq$enqLdTag[5];
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13862 =
|
|
!coreFix_memExe_lsq$enqStTag[5];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13861 =
|
|
coreFix_memExe_lsq$enqLdTag[5];
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13861 =
|
|
coreFix_memExe_lsq$enqStTag[5];
|
|
endcase
|
|
end
|
|
always@(fetchStage$pipelines_1_first or
|
|
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
|
|
begin
|
|
case (fetchStage$pipelines_1_first[95:93])
|
|
3'd0, 3'd2:
|
|
IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13863 =
|
|
coreFix_memExe_lsq$enqLdTag[4:0];
|
|
default: IF_fetchStage_pipelines_1_first__2604_BITS_95__ETC___d13863 =
|
|
coreFix_memExe_lsq$enqStTag[4:0];
|
|
endcase
|
|
end
|
|
always@(rob$deqPort_0_deq_data)
|
|
begin
|
|
case (rob$deqPort_0_deq_data[116:105])
|
|
12'd1:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd0;
|
|
12'd2:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd1;
|
|
12'd3:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd2;
|
|
12'd256:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd8;
|
|
12'd260:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd9;
|
|
12'd261:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd10;
|
|
12'd262:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd11;
|
|
12'd320:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd12;
|
|
12'd321:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd13;
|
|
12'd322:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd14;
|
|
12'd323:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd15;
|
|
12'd324:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd16;
|
|
12'd384:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd17;
|
|
12'd768:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd18;
|
|
12'd769:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd19;
|
|
12'd770:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd20;
|
|
12'd771:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd21;
|
|
12'd772:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd22;
|
|
12'd773:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd23;
|
|
12'd774:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd24;
|
|
12'd832:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd25;
|
|
12'd833:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd26;
|
|
12'd834:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd27;
|
|
12'd835:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd28;
|
|
12'd836:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd29;
|
|
12'd2048:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd6;
|
|
12'd2049:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd7;
|
|
12'd2816:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd30;
|
|
12'd2818:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd31;
|
|
12'd3072:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd3;
|
|
12'd3073:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd4;
|
|
12'd3074:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd5;
|
|
12'd3857:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd32;
|
|
12'd3858:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd33;
|
|
12'd3859:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd34;
|
|
12'd3860:
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 = 6'd35;
|
|
default: IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 =
|
|
6'd36;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q236 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q237 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q238 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q239 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q240 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q241 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd0:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
|
|
3'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 = 3'd4;
|
|
3'd2:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 = 3'd3;
|
|
3'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 = 3'd2;
|
|
3'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 = 3'd1;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10691 =
|
|
3'd0;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
|
|
coreFix_memExe_stb$deq or
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142 or
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2200)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79])
|
|
3'd0, 3'd2, 3'd4:
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
|
|
3'd1:
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492 =
|
|
{ coreFix_memExe_stb$deq[575] ?
|
|
coreFix_memExe_stb$deq[511:504] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504],
|
|
coreFix_memExe_stb$deq[574] ?
|
|
coreFix_memExe_stb$deq[503:496] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496],
|
|
coreFix_memExe_stb$deq[573] ?
|
|
coreFix_memExe_stb$deq[495:488] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488],
|
|
coreFix_memExe_stb$deq[572] ?
|
|
coreFix_memExe_stb$deq[487:480] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480],
|
|
coreFix_memExe_stb$deq[571] ?
|
|
coreFix_memExe_stb$deq[479:472] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472],
|
|
coreFix_memExe_stb$deq[570] ?
|
|
coreFix_memExe_stb$deq[471:464] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464],
|
|
coreFix_memExe_stb$deq[569] ?
|
|
coreFix_memExe_stb$deq[463:456] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456],
|
|
coreFix_memExe_stb$deq[568] ?
|
|
coreFix_memExe_stb$deq[455:448] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448],
|
|
coreFix_memExe_stb$deq[567] ?
|
|
coreFix_memExe_stb$deq[447:440] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440],
|
|
coreFix_memExe_stb$deq[566] ?
|
|
coreFix_memExe_stb$deq[439:432] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432],
|
|
coreFix_memExe_stb$deq[565] ?
|
|
coreFix_memExe_stb$deq[431:424] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424],
|
|
coreFix_memExe_stb$deq[564] ?
|
|
coreFix_memExe_stb$deq[423:416] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416],
|
|
coreFix_memExe_stb$deq[563] ?
|
|
coreFix_memExe_stb$deq[415:408] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408],
|
|
coreFix_memExe_stb$deq[562] ?
|
|
coreFix_memExe_stb$deq[407:400] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400],
|
|
coreFix_memExe_stb$deq[561] ?
|
|
coreFix_memExe_stb$deq[399:392] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392],
|
|
coreFix_memExe_stb$deq[560] ?
|
|
coreFix_memExe_stb$deq[391:384] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384],
|
|
coreFix_memExe_stb$deq[559] ?
|
|
coreFix_memExe_stb$deq[383:376] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376],
|
|
coreFix_memExe_stb$deq[558] ?
|
|
coreFix_memExe_stb$deq[375:368] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368],
|
|
coreFix_memExe_stb$deq[557] ?
|
|
coreFix_memExe_stb$deq[367:360] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360],
|
|
coreFix_memExe_stb$deq[556] ?
|
|
coreFix_memExe_stb$deq[359:352] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352],
|
|
coreFix_memExe_stb$deq[555] ?
|
|
coreFix_memExe_stb$deq[351:344] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344],
|
|
coreFix_memExe_stb$deq[554] ?
|
|
coreFix_memExe_stb$deq[343:336] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336],
|
|
coreFix_memExe_stb$deq[553] ?
|
|
coreFix_memExe_stb$deq[335:328] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328],
|
|
coreFix_memExe_stb$deq[552] ?
|
|
coreFix_memExe_stb$deq[327:320] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320],
|
|
coreFix_memExe_stb$deq[551] ?
|
|
coreFix_memExe_stb$deq[319:312] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312],
|
|
coreFix_memExe_stb$deq[550] ?
|
|
coreFix_memExe_stb$deq[311:304] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304],
|
|
coreFix_memExe_stb$deq[549] ?
|
|
coreFix_memExe_stb$deq[303:296] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296],
|
|
coreFix_memExe_stb$deq[548] ?
|
|
coreFix_memExe_stb$deq[295:288] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288],
|
|
coreFix_memExe_stb$deq[547] ?
|
|
coreFix_memExe_stb$deq[287:280] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280],
|
|
coreFix_memExe_stb$deq[546] ?
|
|
coreFix_memExe_stb$deq[279:272] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272],
|
|
coreFix_memExe_stb$deq[545] ?
|
|
coreFix_memExe_stb$deq[271:264] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264],
|
|
coreFix_memExe_stb$deq[544] ?
|
|
coreFix_memExe_stb$deq[263:256] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256],
|
|
coreFix_memExe_stb$deq[543] ?
|
|
coreFix_memExe_stb$deq[255:248] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248],
|
|
coreFix_memExe_stb$deq[542] ?
|
|
coreFix_memExe_stb$deq[247:240] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240],
|
|
coreFix_memExe_stb$deq[541] ?
|
|
coreFix_memExe_stb$deq[239:232] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232],
|
|
coreFix_memExe_stb$deq[540] ?
|
|
coreFix_memExe_stb$deq[231:224] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224],
|
|
coreFix_memExe_stb$deq[539] ?
|
|
coreFix_memExe_stb$deq[223:216] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216],
|
|
coreFix_memExe_stb$deq[538] ?
|
|
coreFix_memExe_stb$deq[215:208] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208],
|
|
coreFix_memExe_stb$deq[537] ?
|
|
coreFix_memExe_stb$deq[207:200] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200],
|
|
coreFix_memExe_stb$deq[536] ?
|
|
coreFix_memExe_stb$deq[199:192] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192],
|
|
coreFix_memExe_stb$deq[535] ?
|
|
coreFix_memExe_stb$deq[191:184] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184],
|
|
coreFix_memExe_stb$deq[534] ?
|
|
coreFix_memExe_stb$deq[183:176] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176],
|
|
coreFix_memExe_stb$deq[533] ?
|
|
coreFix_memExe_stb$deq[175:168] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168],
|
|
coreFix_memExe_stb$deq[532] ?
|
|
coreFix_memExe_stb$deq[167:160] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160],
|
|
coreFix_memExe_stb$deq[531] ?
|
|
coreFix_memExe_stb$deq[159:152] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152],
|
|
coreFix_memExe_stb$deq[530] ?
|
|
coreFix_memExe_stb$deq[151:144] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144],
|
|
coreFix_memExe_stb$deq[529] ?
|
|
coreFix_memExe_stb$deq[143:136] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136],
|
|
coreFix_memExe_stb$deq[528] ?
|
|
coreFix_memExe_stb$deq[135:128] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128],
|
|
coreFix_memExe_stb$deq[527] ?
|
|
coreFix_memExe_stb$deq[127:120] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120],
|
|
coreFix_memExe_stb$deq[526] ?
|
|
coreFix_memExe_stb$deq[119:112] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112],
|
|
coreFix_memExe_stb$deq[525] ?
|
|
coreFix_memExe_stb$deq[111:104] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104],
|
|
coreFix_memExe_stb$deq[524] ?
|
|
coreFix_memExe_stb$deq[103:96] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96],
|
|
coreFix_memExe_stb$deq[523] ?
|
|
coreFix_memExe_stb$deq[95:88] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88],
|
|
coreFix_memExe_stb$deq[522] ?
|
|
coreFix_memExe_stb$deq[87:80] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80],
|
|
coreFix_memExe_stb$deq[521] ?
|
|
coreFix_memExe_stb$deq[79:72] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72],
|
|
coreFix_memExe_stb$deq[520] ?
|
|
coreFix_memExe_stb$deq[71:64] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64],
|
|
coreFix_memExe_stb$deq[519] ?
|
|
coreFix_memExe_stb$deq[63:56] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56],
|
|
coreFix_memExe_stb$deq[518] ?
|
|
coreFix_memExe_stb$deq[55:48] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48],
|
|
coreFix_memExe_stb$deq[517] ?
|
|
coreFix_memExe_stb$deq[47:40] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40],
|
|
coreFix_memExe_stb$deq[516] ?
|
|
coreFix_memExe_stb$deq[39:32] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32],
|
|
coreFix_memExe_stb$deq[515] ?
|
|
coreFix_memExe_stb$deq[31:24] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24],
|
|
coreFix_memExe_stb$deq[514] ?
|
|
coreFix_memExe_stb$deq[23:16] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16],
|
|
coreFix_memExe_stb$deq[513] ?
|
|
coreFix_memExe_stb$deq[15:8] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8],
|
|
coreFix_memExe_stb$deq[512] ?
|
|
coreFix_memExe_stb$deq[7:0] :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] };
|
|
3'd3:
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2142 ?
|
|
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2200 :
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
|
|
default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2492 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
|
|
3'd4, 3'd3, 3'd2, 3'd1, 3'd0:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q242 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9867 or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162 or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9921)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9925 =
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162;
|
|
5'd25:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9925 =
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9867;
|
|
5'd26, 5'd27:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9925 =
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9921;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9925 =
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9867;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q243 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q244 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q250 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q251 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515];
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8402 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq;
|
|
5'd3:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8402 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq;
|
|
5'd4:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8402 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8402 =
|
|
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228])
|
|
2'd0, 2'd1:
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8421 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq;
|
|
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d8421 =
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q252 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q253 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q254 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q255 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q256 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q257 =
|
|
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
|
|
endcase
|
|
end
|
|
always@(rob$deqPort_0_deq_data)
|
|
begin
|
|
case (rob$deqPort_0_deq_data[101:98])
|
|
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11:
|
|
CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q259 =
|
|
rob$deqPort_0_deq_data[101:98];
|
|
default: CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q259 =
|
|
4'd14;
|
|
endcase
|
|
end
|
|
always@(rob$deqPort_0_deq_data)
|
|
begin
|
|
case (rob$deqPort_0_deq_data[101:98])
|
|
4'd0,
|
|
4'd1,
|
|
4'd2,
|
|
4'd3,
|
|
4'd4,
|
|
4'd5,
|
|
4'd6,
|
|
4'd7,
|
|
4'd8,
|
|
4'd9,
|
|
4'd11,
|
|
4'd12,
|
|
4'd13:
|
|
CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q260 =
|
|
rob$deqPort_0_deq_data[101:98];
|
|
default: CASE_robdeqPort_0_deq_data_BITS_101_TO_98_0_r_ETC__q260 =
|
|
4'd15;
|
|
endcase
|
|
end
|
|
always@(mmio_dataReqQ_data_0)
|
|
begin
|
|
case (mmio_dataReqQ_data_0[77:76])
|
|
2'd0, 2'd1, 2'd2:
|
|
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262 =
|
|
mmio_dataReqQ_data_0[77:72];
|
|
2'd3:
|
|
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q262 =
|
|
{ 2'd3, mmio_dataReqQ_data_0[75:72] };
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstLd)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstLd[6:3])
|
|
4'd0,
|
|
4'd1,
|
|
4'd2,
|
|
4'd3,
|
|
4'd4,
|
|
4'd5,
|
|
4'd6,
|
|
4'd7,
|
|
4'd8,
|
|
4'd9,
|
|
4'd11,
|
|
4'd12,
|
|
4'd13:
|
|
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 =
|
|
coreFix_memExe_lsq$firstLd[6:3];
|
|
default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q263 =
|
|
4'd15;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_lsq$firstSt)
|
|
begin
|
|
case (coreFix_memExe_lsq$firstSt[3:0])
|
|
4'd0,
|
|
4'd1,
|
|
4'd2,
|
|
4'd3,
|
|
4'd4,
|
|
4'd5,
|
|
4'd6,
|
|
4'd7,
|
|
4'd8,
|
|
4'd9,
|
|
4'd11,
|
|
4'd12,
|
|
4'd13:
|
|
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 =
|
|
coreFix_memExe_lsq$firstSt[3:0];
|
|
default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q264 =
|
|
4'd15;
|
|
endcase
|
|
end
|
|
always@(mmioToPlatform_pRq_enq_x)
|
|
begin
|
|
case (mmioToPlatform_pRq_enq_x[37:36])
|
|
2'd0, 2'd1, 2'd2:
|
|
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265 =
|
|
mmioToPlatform_pRq_enq_x[37:32];
|
|
2'd3:
|
|
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q265 =
|
|
{ 2'd3, mmioToPlatform_pRq_enq_x[35:32] };
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_rsAlu$dispatchData)
|
|
begin
|
|
case (coreFix_aluExe_0_rsAlu$dispatchData[139:137])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266 =
|
|
coreFix_aluExe_0_rsAlu$dispatchData[139:137];
|
|
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_rsAlu$dispatchData or
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266)
|
|
begin
|
|
case (coreFix_aluExe_0_rsAlu$dispatchData[156:154])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 =
|
|
coreFix_aluExe_0_rsAlu$dispatchData[156:136];
|
|
3'd4:
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 =
|
|
{ coreFix_aluExe_0_rsAlu$dispatchData[156:154],
|
|
9'h0AA,
|
|
coreFix_aluExe_0_rsAlu$dispatchData[144:140],
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q266,
|
|
coreFix_aluExe_0_rsAlu$dispatchData[136] };
|
|
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q267 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_rsAlu$dispatchData)
|
|
begin
|
|
case (coreFix_aluExe_0_rsAlu$dispatchData[134:123])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
|
|
coreFix_aluExe_0_rsAlu$dispatchData[134:123];
|
|
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q268 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_dispToRegQ$first)
|
|
begin
|
|
case (coreFix_aluExe_0_dispToRegQ$first[135:133])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269 =
|
|
coreFix_aluExe_0_dispToRegQ$first[135:133];
|
|
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_dispToRegQ$first or
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269)
|
|
begin
|
|
case (coreFix_aluExe_0_dispToRegQ$first[152:150])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270 =
|
|
coreFix_aluExe_0_dispToRegQ$first[152:132];
|
|
3'd4:
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270 =
|
|
{ coreFix_aluExe_0_dispToRegQ$first[152:150],
|
|
9'h0AA,
|
|
coreFix_aluExe_0_dispToRegQ$first[140:136],
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q269,
|
|
coreFix_aluExe_0_dispToRegQ$first[132] };
|
|
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q270 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_0_dispToRegQ$first)
|
|
begin
|
|
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271 =
|
|
coreFix_aluExe_0_dispToRegQ$first[130:119];
|
|
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q271 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_rsAlu$dispatchData)
|
|
begin
|
|
case (coreFix_aluExe_1_rsAlu$dispatchData[139:137])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272 =
|
|
coreFix_aluExe_1_rsAlu$dispatchData[139:137];
|
|
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_rsAlu$dispatchData or
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272)
|
|
begin
|
|
case (coreFix_aluExe_1_rsAlu$dispatchData[156:154])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 =
|
|
coreFix_aluExe_1_rsAlu$dispatchData[156:136];
|
|
3'd4:
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 =
|
|
{ coreFix_aluExe_1_rsAlu$dispatchData[156:154],
|
|
9'h0AA,
|
|
coreFix_aluExe_1_rsAlu$dispatchData[144:140],
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q272,
|
|
coreFix_aluExe_1_rsAlu$dispatchData[136] };
|
|
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q273 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_rsAlu$dispatchData)
|
|
begin
|
|
case (coreFix_aluExe_1_rsAlu$dispatchData[134:123])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
|
|
coreFix_aluExe_1_rsAlu$dispatchData[134:123];
|
|
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q274 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_dispToRegQ$first)
|
|
begin
|
|
case (coreFix_aluExe_1_dispToRegQ$first[135:133])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275 =
|
|
coreFix_aluExe_1_dispToRegQ$first[135:133];
|
|
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_dispToRegQ$first or
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275)
|
|
begin
|
|
case (coreFix_aluExe_1_dispToRegQ$first[152:150])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276 =
|
|
coreFix_aluExe_1_dispToRegQ$first[152:132];
|
|
3'd4:
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276 =
|
|
{ coreFix_aluExe_1_dispToRegQ$first[152:150],
|
|
9'h0AA,
|
|
coreFix_aluExe_1_dispToRegQ$first[140:136],
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q275,
|
|
coreFix_aluExe_1_dispToRegQ$first[132] };
|
|
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q276 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(coreFix_aluExe_1_dispToRegQ$first)
|
|
begin
|
|
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
|
|
12'd1,
|
|
12'd2,
|
|
12'd3,
|
|
12'd256,
|
|
12'd260,
|
|
12'd261,
|
|
12'd262,
|
|
12'd320,
|
|
12'd321,
|
|
12'd322,
|
|
12'd323,
|
|
12'd324,
|
|
12'd384,
|
|
12'd768,
|
|
12'd769,
|
|
12'd770,
|
|
12'd771,
|
|
12'd772,
|
|
12'd773,
|
|
12'd774,
|
|
12'd832,
|
|
12'd833,
|
|
12'd834,
|
|
12'd835,
|
|
12'd836,
|
|
12'd2048,
|
|
12'd2049,
|
|
12'd2816,
|
|
12'd2818,
|
|
12'd3072,
|
|
12'd3073,
|
|
12'd3074,
|
|
12'd3857,
|
|
12'd3858,
|
|
12'd3859,
|
|
12'd3860:
|
|
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277 =
|
|
coreFix_aluExe_1_dispToRegQ$first[130:119];
|
|
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q277 =
|
|
12'd2303;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278 =
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67];
|
|
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or
|
|
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 =
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 =
|
|
{ coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84],
|
|
9'h0AA,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70],
|
|
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q278,
|
|
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] };
|
|
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q279 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162 or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10630 or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10681 or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10628)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280 =
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10630;
|
|
5'd1:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280 =
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
|
|
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[139],
|
|
coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } :
|
|
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10681,
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10628 };
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q280 =
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d9162;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10630)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
|
|
5'd0, 5'd1:
|
|
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
|
|
64'h3FF0000000000000;
|
|
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q281 =
|
|
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__364_ETC___d10630;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58])
|
|
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282 =
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58];
|
|
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282 = 3'd7;
|
|
endcase
|
|
end
|
|
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or
|
|
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282)
|
|
begin
|
|
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75])
|
|
3'd0, 3'd1, 3'd2, 3'd3:
|
|
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 =
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57];
|
|
3'd4:
|
|
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 =
|
|
{ coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75],
|
|
9'h0AA,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61],
|
|
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q282,
|
|
coreFix_fpuMulDivExe_0_dispToRegQ$first[57] };
|
|
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q283 =
|
|
21'd1485482;
|
|
endcase
|
|
end
|
|
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
|
|
begin
|
|
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
|
|
1'd0:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0];
|
|
1'd1:
|
|
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q284 =
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0];
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
|
|
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
|
|
4'd0;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
|
|
2'd3;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd2;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
1'd1;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
3'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
4'd2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
1'd1;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
|
|
59'h2AAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
|
|
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd1;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
72'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
72'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
1'd1;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
73'h0AAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
1'd1;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
1'd0;
|
|
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
|
|
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
|
|
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
|
|
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
70'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
|
|
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
|
|
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
70'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
69'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
66'h2AAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
65'h0AAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0;
|
|
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
|
|
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0;
|
|
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
|
|
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
|
|
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0;
|
|
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3;
|
|
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
|
|
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
|
|
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
142'h000000000000000004000000000000000000;
|
|
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
142'h000000000000000004000000000000000000;
|
|
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
66'h0AAAAAAAAAAAAAAAA;
|
|
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
|
|
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 39'h0400000000;
|
|
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA;
|
|
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA;
|
|
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA;
|
|
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
|
|
outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
started <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (commitStage_commitTrap$EN)
|
|
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
|
|
commitStage_commitTrap$D_IN;
|
|
if (coreFix_doStatsReg$EN)
|
|
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN;
|
|
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN)
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
|
|
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN)
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN;
|
|
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN)
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
|
|
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN)
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
|
|
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN)
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN)
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN;
|
|
if (coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN)
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_perfReqQ_data_0$EN)
|
|
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
|
|
if (coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN)
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_perfReqQ_empty$EN)
|
|
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_perfReqQ_empty$D_IN;
|
|
if (coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN)
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_dMem_perfReqQ_full$EN)
|
|
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_dMem_perfReqQ_full$D_IN;
|
|
if (coreFix_memExe_forwardQ_clearReq_rl$EN)
|
|
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_forwardQ_data_0$EN)
|
|
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_data_0$D_IN;
|
|
if (coreFix_memExe_forwardQ_data_1$EN)
|
|
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_data_1$D_IN;
|
|
if (coreFix_memExe_forwardQ_deqP$EN)
|
|
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_deqP$D_IN;
|
|
if (coreFix_memExe_forwardQ_deqReq_rl$EN)
|
|
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_forwardQ_empty$EN)
|
|
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_empty$D_IN;
|
|
if (coreFix_memExe_forwardQ_enqP$EN)
|
|
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_enqP$D_IN;
|
|
if (coreFix_memExe_forwardQ_enqReq_rl$EN)
|
|
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_forwardQ_full$EN)
|
|
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_forwardQ_full$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_clearReq_rl$EN)
|
|
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_data_0$EN)
|
|
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_data_0$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_data_1$EN)
|
|
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_data_1$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_deqP$EN)
|
|
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_deqP$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_deqReq_rl$EN)
|
|
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_empty$EN)
|
|
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_empty$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_enqP$EN)
|
|
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_enqP$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_enqReq_rl$EN)
|
|
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_memRespLdQ_full$EN)
|
|
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_memRespLdQ_full$D_IN;
|
|
if (coreFix_memExe_reqLdQ_data_0_rl$EN)
|
|
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqLdQ_data_0_rl$D_IN;
|
|
if (coreFix_memExe_reqLdQ_empty_rl$EN)
|
|
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqLdQ_empty_rl$D_IN;
|
|
if (coreFix_memExe_reqLdQ_full_rl$EN)
|
|
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqLdQ_full_rl$D_IN;
|
|
if (coreFix_memExe_reqLrScAmoQ_data_0_rl$EN)
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
|
|
if (coreFix_memExe_reqLrScAmoQ_empty_rl$EN)
|
|
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN;
|
|
if (coreFix_memExe_reqLrScAmoQ_full_rl$EN)
|
|
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqLrScAmoQ_full_rl$D_IN;
|
|
if (coreFix_memExe_reqStQ_data_0_rl$EN)
|
|
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqStQ_data_0_rl$D_IN;
|
|
if (coreFix_memExe_reqStQ_empty_rl$EN)
|
|
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqStQ_empty_rl$D_IN;
|
|
if (coreFix_memExe_reqStQ_full_rl$EN)
|
|
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_reqStQ_full_rl$D_IN;
|
|
if (coreFix_memExe_respLrScAmoQ_clearReq_rl$EN)
|
|
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN;
|
|
if (coreFix_memExe_respLrScAmoQ_data_0$EN)
|
|
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_respLrScAmoQ_data_0$D_IN;
|
|
if (coreFix_memExe_respLrScAmoQ_deqReq_rl$EN)
|
|
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN;
|
|
if (coreFix_memExe_respLrScAmoQ_empty$EN)
|
|
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_respLrScAmoQ_empty$D_IN;
|
|
if (coreFix_memExe_respLrScAmoQ_enqReq_rl$EN)
|
|
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
|
|
if (coreFix_memExe_respLrScAmoQ_full$EN)
|
|
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_respLrScAmoQ_full$D_IN;
|
|
if (coreFix_memExe_waitLrScAmoMMIOResp$EN)
|
|
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY
|
|
coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
|
|
if (csrInstOrInterruptInflight_rl$EN)
|
|
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY
|
|
csrInstOrInterruptInflight_rl$D_IN;
|
|
if (csrf_debug_int_pend$EN)
|
|
csrf_debug_int_pend <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_debug_int_pend$D_IN;
|
|
if (csrf_external_int_en_vec_0$EN)
|
|
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_external_int_en_vec_0$D_IN;
|
|
if (csrf_external_int_en_vec_1$EN)
|
|
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_external_int_en_vec_1$D_IN;
|
|
if (csrf_external_int_en_vec_3$EN)
|
|
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_external_int_en_vec_3$D_IN;
|
|
if (csrf_external_int_pend_vec_0$EN)
|
|
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_external_int_pend_vec_0$D_IN;
|
|
if (csrf_external_int_pend_vec_1$EN)
|
|
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_external_int_pend_vec_1$D_IN;
|
|
if (csrf_external_int_pend_vec_3$EN)
|
|
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_external_int_pend_vec_3$D_IN;
|
|
if (csrf_fflags_reg$EN)
|
|
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY csrf_fflags_reg$D_IN;
|
|
if (csrf_frm_reg$EN)
|
|
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY csrf_frm_reg$D_IN;
|
|
if (csrf_fs_reg$EN)
|
|
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY csrf_fs_reg$D_IN;
|
|
if (csrf_ie_vec_0$EN)
|
|
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_0$D_IN;
|
|
if (csrf_ie_vec_1$EN)
|
|
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN;
|
|
if (csrf_ie_vec_3$EN)
|
|
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN;
|
|
if (csrf_mcause_code_reg$EN)
|
|
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mcause_code_reg$D_IN;
|
|
if (csrf_mcause_interrupt_reg$EN)
|
|
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mcause_interrupt_reg$D_IN;
|
|
if (csrf_mcounteren_cy_reg$EN)
|
|
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mcounteren_cy_reg$D_IN;
|
|
if (csrf_mcounteren_ir_reg$EN)
|
|
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mcounteren_ir_reg$D_IN;
|
|
if (csrf_mcounteren_tm_reg$EN)
|
|
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mcounteren_tm_reg$D_IN;
|
|
if (csrf_mcycle_ehr_data_rl$EN)
|
|
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mcycle_ehr_data_rl$D_IN;
|
|
if (csrf_medeleg_13_11_reg$EN)
|
|
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_medeleg_13_11_reg$D_IN;
|
|
if (csrf_medeleg_15_reg$EN)
|
|
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_medeleg_15_reg$D_IN;
|
|
if (csrf_medeleg_9_0_reg$EN)
|
|
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_medeleg_9_0_reg$D_IN;
|
|
if (csrf_mepc_csr$EN)
|
|
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN;
|
|
if (csrf_mideleg_11_reg$EN)
|
|
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mideleg_11_reg$D_IN;
|
|
if (csrf_mideleg_1_0_reg$EN)
|
|
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mideleg_1_0_reg$D_IN;
|
|
if (csrf_mideleg_5_3_reg$EN)
|
|
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mideleg_5_3_reg$D_IN;
|
|
if (csrf_mideleg_9_7_reg$EN)
|
|
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mideleg_9_7_reg$D_IN;
|
|
if (csrf_minstret_ehr_data_rl$EN)
|
|
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_minstret_ehr_data_rl$D_IN;
|
|
if (csrf_mpp_reg$EN)
|
|
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY csrf_mpp_reg$D_IN;
|
|
if (csrf_mprv_reg$EN)
|
|
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN;
|
|
if (csrf_mscratch_csr$EN)
|
|
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN;
|
|
if (csrf_mtval_csr$EN)
|
|
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN;
|
|
if (csrf_mtvec_base_hi_reg$EN)
|
|
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mtvec_base_hi_reg$D_IN;
|
|
if (csrf_mtvec_mode_low_reg$EN)
|
|
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_mtvec_mode_low_reg$D_IN;
|
|
if (csrf_mxr_reg$EN)
|
|
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN;
|
|
if (csrf_ppn_reg$EN)
|
|
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY csrf_ppn_reg$D_IN;
|
|
if (csrf_prev_ie_vec_0$EN)
|
|
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_0$D_IN;
|
|
if (csrf_prev_ie_vec_1$EN)
|
|
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_1$D_IN;
|
|
if (csrf_prev_ie_vec_3$EN)
|
|
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN;
|
|
if (csrf_prv_reg$EN)
|
|
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN;
|
|
if (csrf_scause_code_reg$EN)
|
|
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_scause_code_reg$D_IN;
|
|
if (csrf_scause_interrupt_reg$EN)
|
|
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_scause_interrupt_reg$D_IN;
|
|
if (csrf_scounteren_cy_reg$EN)
|
|
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_scounteren_cy_reg$D_IN;
|
|
if (csrf_scounteren_ir_reg$EN)
|
|
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_scounteren_ir_reg$D_IN;
|
|
if (csrf_scounteren_tm_reg$EN)
|
|
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_scounteren_tm_reg$D_IN;
|
|
if (csrf_sepc_csr$EN)
|
|
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN;
|
|
if (csrf_software_int_en_vec_0$EN)
|
|
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_software_int_en_vec_0$D_IN;
|
|
if (csrf_software_int_en_vec_1$EN)
|
|
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_software_int_en_vec_1$D_IN;
|
|
if (csrf_software_int_en_vec_3$EN)
|
|
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_software_int_en_vec_3$D_IN;
|
|
if (csrf_software_int_pend_vec_0$EN)
|
|
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_software_int_pend_vec_0$D_IN;
|
|
if (csrf_software_int_pend_vec_1$EN)
|
|
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_software_int_pend_vec_1$D_IN;
|
|
if (csrf_software_int_pend_vec_3$EN)
|
|
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_software_int_pend_vec_3$D_IN;
|
|
if (csrf_spp_reg$EN)
|
|
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY csrf_spp_reg$D_IN;
|
|
if (csrf_sscratch_csr$EN)
|
|
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_sscratch_csr$D_IN;
|
|
if (csrf_stats_module_doStats$EN)
|
|
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_stats_module_doStats$D_IN;
|
|
if (csrf_stval_csr$EN)
|
|
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN;
|
|
if (csrf_stvec_base_hi_reg$EN)
|
|
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_stvec_base_hi_reg$D_IN;
|
|
if (csrf_stvec_mode_low_reg$EN)
|
|
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_stvec_mode_low_reg$D_IN;
|
|
if (csrf_sum_reg$EN)
|
|
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN;
|
|
if (csrf_time_reg$EN)
|
|
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY csrf_time_reg$D_IN;
|
|
if (csrf_timer_int_en_vec_0$EN)
|
|
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_timer_int_en_vec_0$D_IN;
|
|
if (csrf_timer_int_en_vec_1$EN)
|
|
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_timer_int_en_vec_1$D_IN;
|
|
if (csrf_timer_int_en_vec_3$EN)
|
|
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_timer_int_en_vec_3$D_IN;
|
|
if (csrf_timer_int_pend_vec_0$EN)
|
|
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_timer_int_pend_vec_0$D_IN;
|
|
if (csrf_timer_int_pend_vec_1$EN)
|
|
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_timer_int_pend_vec_1$D_IN;
|
|
if (csrf_timer_int_pend_vec_3$EN)
|
|
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_timer_int_pend_vec_3$D_IN;
|
|
if (csrf_tsr_reg$EN)
|
|
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_tsr_reg$D_IN;
|
|
if (csrf_tvm_reg$EN)
|
|
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY csrf_tvm_reg$D_IN;
|
|
if (csrf_tw_reg$EN)
|
|
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY csrf_tw_reg$D_IN;
|
|
if (csrf_vm_mode_sv39_reg$EN)
|
|
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY
|
|
csrf_vm_mode_sv39_reg$D_IN;
|
|
if (flush_reservation$EN)
|
|
flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN;
|
|
if (flush_tlbs$EN)
|
|
flush_tlbs <= `BSV_ASSIGNMENT_DELAY flush_tlbs$D_IN;
|
|
if (mmio_cRqQ_clearReq_rl$EN)
|
|
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_cRqQ_clearReq_rl$D_IN;
|
|
if (mmio_cRqQ_data_0$EN)
|
|
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_data_0$D_IN;
|
|
if (mmio_cRqQ_deqReq_rl$EN)
|
|
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_cRqQ_deqReq_rl$D_IN;
|
|
if (mmio_cRqQ_empty$EN)
|
|
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_empty$D_IN;
|
|
if (mmio_cRqQ_enqReq_rl$EN)
|
|
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_cRqQ_enqReq_rl$D_IN;
|
|
if (mmio_cRqQ_full$EN)
|
|
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_full$D_IN;
|
|
if (mmio_cRsQ_clearReq_rl$EN)
|
|
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_cRsQ_clearReq_rl$D_IN;
|
|
if (mmio_cRsQ_data_0$EN)
|
|
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_data_0$D_IN;
|
|
if (mmio_cRsQ_deqReq_rl$EN)
|
|
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_cRsQ_deqReq_rl$D_IN;
|
|
if (mmio_cRsQ_empty$EN)
|
|
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_empty$D_IN;
|
|
if (mmio_cRsQ_enqReq_rl$EN)
|
|
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_cRsQ_enqReq_rl$D_IN;
|
|
if (mmio_cRsQ_full$EN)
|
|
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_full$D_IN;
|
|
if (mmio_dataPendQ_clearReq_rl$EN)
|
|
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataPendQ_clearReq_rl$D_IN;
|
|
if (mmio_dataPendQ_deqReq_rl$EN)
|
|
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataPendQ_deqReq_rl$D_IN;
|
|
if (mmio_dataPendQ_empty$EN)
|
|
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataPendQ_empty$D_IN;
|
|
if (mmio_dataPendQ_enqReq_rl$EN)
|
|
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataPendQ_enqReq_rl$D_IN;
|
|
if (mmio_dataPendQ_full$EN)
|
|
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataPendQ_full$D_IN;
|
|
if (mmio_dataReqQ_clearReq_rl$EN)
|
|
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataReqQ_clearReq_rl$D_IN;
|
|
if (mmio_dataReqQ_data_0$EN)
|
|
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataReqQ_data_0$D_IN;
|
|
if (mmio_dataReqQ_deqReq_rl$EN)
|
|
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataReqQ_deqReq_rl$D_IN;
|
|
if (mmio_dataReqQ_empty$EN)
|
|
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataReqQ_empty$D_IN;
|
|
if (mmio_dataReqQ_enqReq_rl$EN)
|
|
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataReqQ_enqReq_rl$D_IN;
|
|
if (mmio_dataReqQ_full$EN)
|
|
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_dataReqQ_full$D_IN;
|
|
if (mmio_dataRespQ_clearReq_rl$EN)
|
|
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataRespQ_clearReq_rl$D_IN;
|
|
if (mmio_dataRespQ_data_0$EN)
|
|
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataRespQ_data_0$D_IN;
|
|
if (mmio_dataRespQ_deqReq_rl$EN)
|
|
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataRespQ_deqReq_rl$D_IN;
|
|
if (mmio_dataRespQ_empty$EN)
|
|
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataRespQ_empty$D_IN;
|
|
if (mmio_dataRespQ_enqReq_rl$EN)
|
|
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataRespQ_enqReq_rl$D_IN;
|
|
if (mmio_dataRespQ_full$EN)
|
|
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_dataRespQ_full$D_IN;
|
|
if (mmio_fromHostAddr$EN)
|
|
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_fromHostAddr$D_IN;
|
|
if (mmio_pRqQ_clearReq_rl$EN)
|
|
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_pRqQ_clearReq_rl$D_IN;
|
|
if (mmio_pRqQ_data_0$EN)
|
|
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_data_0$D_IN;
|
|
if (mmio_pRqQ_deqReq_rl$EN)
|
|
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_pRqQ_deqReq_rl$D_IN;
|
|
if (mmio_pRqQ_empty$EN)
|
|
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_empty$D_IN;
|
|
if (mmio_pRqQ_enqReq_rl$EN)
|
|
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_pRqQ_enqReq_rl$D_IN;
|
|
if (mmio_pRqQ_full$EN)
|
|
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_full$D_IN;
|
|
if (mmio_pRsQ_clearReq_rl$EN)
|
|
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_pRsQ_clearReq_rl$D_IN;
|
|
if (mmio_pRsQ_data_0$EN)
|
|
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_data_0$D_IN;
|
|
if (mmio_pRsQ_deqReq_rl$EN)
|
|
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_pRsQ_deqReq_rl$D_IN;
|
|
if (mmio_pRsQ_empty$EN)
|
|
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_empty$D_IN;
|
|
if (mmio_pRsQ_enqReq_rl$EN)
|
|
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
mmio_pRsQ_enqReq_rl$D_IN;
|
|
if (mmio_pRsQ_full$EN)
|
|
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_full$D_IN;
|
|
if (mmio_toHostAddr$EN)
|
|
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN;
|
|
if (outOfReset$EN)
|
|
outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN;
|
|
if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN;
|
|
if (update_vm_info$EN)
|
|
update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
commitStage_commitTrap = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_doStatsReg = 1'h0;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit = 2'h2;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 = 3'h2;
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP = 3'h2;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl = 4'hA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 =
|
|
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 =
|
|
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl =
|
|
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_processAmo =
|
|
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl =
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 =
|
|
72'hAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 =
|
|
72'hAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl =
|
|
73'h0AAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 =
|
|
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 =
|
|
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl =
|
|
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0;
|
|
coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA;
|
|
coreFix_memExe_dMem_perfReqQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_dMem_perfReqQ_empty = 1'h0;
|
|
coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A;
|
|
coreFix_memExe_dMem_perfReqQ_full = 1'h0;
|
|
coreFix_memExe_forwardQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_forwardQ_deqP = 1'h0;
|
|
coreFix_memExe_forwardQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_forwardQ_empty = 1'h0;
|
|
coreFix_memExe_forwardQ_enqP = 1'h0;
|
|
coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_forwardQ_full = 1'h0;
|
|
coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_memRespLdQ_deqP = 1'h0;
|
|
coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_memRespLdQ_empty = 1'h0;
|
|
coreFix_memExe_memRespLdQ_enqP = 1'h0;
|
|
coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_memRespLdQ_full = 1'h0;
|
|
coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_reqLdQ_empty_rl = 1'h0;
|
|
coreFix_memExe_reqLdQ_full_rl = 1'h0;
|
|
coreFix_memExe_reqLrScAmoQ_data_0_rl =
|
|
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0;
|
|
coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0;
|
|
coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_reqStQ_empty_rl = 1'h0;
|
|
coreFix_memExe_reqStQ_full_rl = 1'h0;
|
|
coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0;
|
|
coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0;
|
|
coreFix_memExe_respLrScAmoQ_empty = 1'h0;
|
|
coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
|
|
coreFix_memExe_respLrScAmoQ_full = 1'h0;
|
|
coreFix_memExe_waitLrScAmoMMIOResp = 3'h2;
|
|
csrInstOrInterruptInflight_rl = 1'h0;
|
|
csrf_debug_int_pend = 1'h0;
|
|
csrf_external_int_en_vec_0 = 1'h0;
|
|
csrf_external_int_en_vec_1 = 1'h0;
|
|
csrf_external_int_en_vec_3 = 1'h0;
|
|
csrf_external_int_pend_vec_0 = 1'h0;
|
|
csrf_external_int_pend_vec_1 = 1'h0;
|
|
csrf_external_int_pend_vec_3 = 1'h0;
|
|
csrf_fflags_reg = 5'h0A;
|
|
csrf_frm_reg = 3'h2;
|
|
csrf_fs_reg = 2'h2;
|
|
csrf_ie_vec_0 = 1'h0;
|
|
csrf_ie_vec_1 = 1'h0;
|
|
csrf_ie_vec_3 = 1'h0;
|
|
csrf_mcause_code_reg = 4'hA;
|
|
csrf_mcause_interrupt_reg = 1'h0;
|
|
csrf_mcounteren_cy_reg = 1'h0;
|
|
csrf_mcounteren_ir_reg = 1'h0;
|
|
csrf_mcounteren_tm_reg = 1'h0;
|
|
csrf_mcycle_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_medeleg_13_11_reg = 3'h2;
|
|
csrf_medeleg_15_reg = 1'h0;
|
|
csrf_medeleg_9_0_reg = 10'h2AA;
|
|
csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_mideleg_11_reg = 1'h0;
|
|
csrf_mideleg_1_0_reg = 2'h2;
|
|
csrf_mideleg_5_3_reg = 3'h2;
|
|
csrf_mideleg_9_7_reg = 3'h2;
|
|
csrf_minstret_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_mpp_reg = 2'h2;
|
|
csrf_mprv_reg = 1'h0;
|
|
csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
|
|
csrf_mtvec_mode_low_reg = 1'h0;
|
|
csrf_mxr_reg = 1'h0;
|
|
csrf_ppn_reg = 44'hAAAAAAAAAAA;
|
|
csrf_prev_ie_vec_0 = 1'h0;
|
|
csrf_prev_ie_vec_1 = 1'h0;
|
|
csrf_prev_ie_vec_3 = 1'h0;
|
|
csrf_prv_reg = 2'h2;
|
|
csrf_scause_code_reg = 4'hA;
|
|
csrf_scause_interrupt_reg = 1'h0;
|
|
csrf_scounteren_cy_reg = 1'h0;
|
|
csrf_scounteren_ir_reg = 1'h0;
|
|
csrf_scounteren_tm_reg = 1'h0;
|
|
csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_software_int_en_vec_0 = 1'h0;
|
|
csrf_software_int_en_vec_1 = 1'h0;
|
|
csrf_software_int_en_vec_3 = 1'h0;
|
|
csrf_software_int_pend_vec_0 = 1'h0;
|
|
csrf_software_int_pend_vec_1 = 1'h0;
|
|
csrf_software_int_pend_vec_3 = 1'h0;
|
|
csrf_spp_reg = 1'h0;
|
|
csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_stats_module_doStats = 1'h0;
|
|
csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
|
|
csrf_stvec_mode_low_reg = 1'h0;
|
|
csrf_sum_reg = 1'h0;
|
|
csrf_time_reg = 64'hAAAAAAAAAAAAAAAA;
|
|
csrf_timer_int_en_vec_0 = 1'h0;
|
|
csrf_timer_int_en_vec_1 = 1'h0;
|
|
csrf_timer_int_en_vec_3 = 1'h0;
|
|
csrf_timer_int_pend_vec_0 = 1'h0;
|
|
csrf_timer_int_pend_vec_1 = 1'h0;
|
|
csrf_timer_int_pend_vec_3 = 1'h0;
|
|
csrf_tsr_reg = 1'h0;
|
|
csrf_tvm_reg = 1'h0;
|
|
csrf_tw_reg = 1'h0;
|
|
csrf_vm_mode_sv39_reg = 1'h0;
|
|
flush_reservation = 1'h0;
|
|
flush_tlbs = 1'h0;
|
|
mmio_cRqQ_clearReq_rl = 1'h0;
|
|
mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
mmio_cRqQ_deqReq_rl = 1'h0;
|
|
mmio_cRqQ_empty = 1'h0;
|
|
mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
mmio_cRqQ_full = 1'h0;
|
|
mmio_cRsQ_clearReq_rl = 1'h0;
|
|
mmio_cRsQ_data_0 = 1'h0;
|
|
mmio_cRsQ_deqReq_rl = 1'h0;
|
|
mmio_cRsQ_empty = 1'h0;
|
|
mmio_cRsQ_enqReq_rl = 2'h2;
|
|
mmio_cRsQ_full = 1'h0;
|
|
mmio_dataPendQ_clearReq_rl = 1'h0;
|
|
mmio_dataPendQ_deqReq_rl = 1'h0;
|
|
mmio_dataPendQ_empty = 1'h0;
|
|
mmio_dataPendQ_enqReq_rl = 1'h0;
|
|
mmio_dataPendQ_full = 1'h0;
|
|
mmio_dataReqQ_clearReq_rl = 1'h0;
|
|
mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
mmio_dataReqQ_deqReq_rl = 1'h0;
|
|
mmio_dataReqQ_empty = 1'h0;
|
|
mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
mmio_dataReqQ_full = 1'h0;
|
|
mmio_dataRespQ_clearReq_rl = 1'h0;
|
|
mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
|
|
mmio_dataRespQ_deqReq_rl = 1'h0;
|
|
mmio_dataRespQ_empty = 1'h0;
|
|
mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
mmio_dataRespQ_full = 1'h0;
|
|
mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
|
|
mmio_pRqQ_clearReq_rl = 1'h0;
|
|
mmio_pRqQ_data_0 = 39'h2AAAAAAAAA;
|
|
mmio_pRqQ_deqReq_rl = 1'h0;
|
|
mmio_pRqQ_empty = 1'h0;
|
|
mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA;
|
|
mmio_pRqQ_full = 1'h0;
|
|
mmio_pRsQ_clearReq_rl = 1'h0;
|
|
mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA;
|
|
mmio_pRsQ_deqReq_rl = 1'h0;
|
|
mmio_pRsQ_empty = 1'h0;
|
|
mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA;
|
|
mmio_pRsQ_full = 1'h0;
|
|
mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
|
|
outOfReset = 1'h0;
|
|
started = 1'h0;
|
|
update_vm_info = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_outOfReset)
|
|
$fwrite(32'h80000002, "mkProc came out of reset\n");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
|
|
rob$deqPort_0_deq_data[122:118] == 5'd13 &&
|
|
IF_rob_deqPort_0_deq_data__3921_BIT_117_4078_T_ETC___d14152 == 6'd6)
|
|
$display("[Terminate CSR] being written (val = %x), ",
|
|
"send terminate signal to host",
|
|
rob$deqPort_0_deq_data[95:32]);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
|
|
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
|
|
v__h600721 == 2'd0)
|
|
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkCore
|
|
|