113f888d37
New method 'debug_external_interrupt_req' to support emulation of a debug module starts at P3_Core interface and is plumbed all the way in to the CSR register MIP as interrupt [14]. The corresponding MIE[14] is always 1, so it is never masked. Still todo: should not be masked by MSTATUS interrupt-enables either. Also expanded interrupt-detection logic, mcause etc. to extend up to interrupt 14. Builds in standalone mode, runs ISA tests. Builds in src_SSITH_P3, generating RTL.
105 lines
3.0 KiB
Verilog
105 lines
3.0 KiB
Verilog
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// Copyright (c) 2000-2009 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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// Bluespec primitive module which generates a periodic clock
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// This module is not synthesizable
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module ClockGen(CLK_OUT);
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parameter v1Width = 5;
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parameter v2Width = 5;
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parameter initDelay = 5;
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parameter initValue = 1'b0;
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parameter otherValue = 1'b1 ;
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output CLK_OUT ;
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reg CLK_OUT ;
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// synopsys translate_off
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// Clock is set to initValue for initDelay, and
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// then repeats set to value1 for value1Width
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initial
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begin : clock_loop
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#0 ;
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CLK_OUT = initValue ;
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# initDelay ;
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forever
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begin
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CLK_OUT = otherValue ;
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# v1Width ;
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CLK_OUT = initValue ;
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# v2Width ;
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end // forever begin
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end // initial begin
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// Some assertions about parameter values
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initial
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begin : parameter_assertions
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integer ok ;
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ok = 1 ;
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if (! ( (( initValue == 1'b0 ) && ( otherValue == 1'b1 )) ||
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(( initValue == 1'b1 ) && ( otherValue == 1'b0 )) ) )
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begin
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ok = 0;
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$display ( "ERROR ClockGen.v: clock values must be complements" ) ;
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end // if ( (( initValue != 0 ) && ( otherValue != 1 )) ||...
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if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))
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begin
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ok = 0;
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$display( "ERROR ClockGen.v: duty cycle must be greater then 0") ;
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end // if ( ( v1Width <= 0 ) || ( v2Width <= 0 ))
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if ( ok == 0 ) $finish ;
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end // initial begin
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// synopsys translate_on
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endmodule // ClockGen
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`ifdef testBluespec
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module testClockGen1() ;
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wire clkout ;
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ClockGen#(8,24,16,1'b1,1'b0) u1( clkout );
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initial
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begin
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$dumpfile("ClockGen.dump");
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$dumpvars(5) ;
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$dumpon ;
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#10000 $finish ;
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end
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endmodule // testClockGen
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`endif
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