233 lines
7.3 KiB
Plaintext
Executable File
233 lines
7.3 KiB
Plaintext
Executable File
/*
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* Copyright (c) 2019 Peter Rugg
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* @BERI_LICENSE_HEADER_START@
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*
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* Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
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* license agreements. See the NOTICE file distributed with this work for
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* additional information regarding copyright ownership. BERI licenses this
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* file to you under the BERI Hardware-Software License, Version 1.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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*
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* http://www.beri-open-systems.org/legal/license-1-0.txt
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*
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* Unless required by applicable law or agreed to in writing, Work distributed
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* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* @BERI_LICENSE_HEADER_END@
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*/
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import ISA_Decls::*;
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import CHERICap::*;
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import CHERICC_Fat::*;
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typedef TMul#(XLEN, 2) CLEN;
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// Exception codes
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typedef enum {
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None = 5'd0,
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LengthViolation = 5'd1,
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TagViolation = 5'd2,
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SealViolation = 5'd3,
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TypeViolation = 5'd4,
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CallTrap = 5'd5,
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ReturnTrap = 5'd6,
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StackUnderflow = 5'd7,
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SoftwarePermViolation = 5'd8,
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MMUStoreCapProhibit = 5'd9,
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RepresentViolation = 5'd10,
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UnalignedBase = 5'd11,
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// 5'd12 - 5'd15 reserved
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GlobalViolation = 5'd16,
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PermitXViolation = 5'd17,
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PermitRViolation = 5'd18,
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PermitWViolation = 5'd19,
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PermitRCapViolation = 5'd20,
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PermitWCapViolation = 5'd21,
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PermitWLocalCapViolation = 5'd22,
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PermitSealViolation = 5'd23,
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PermitASRViolation = 5'd24,
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PermitCCallViolation = 5'd25,
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PermitUnsealViolation = 5'd26,
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PermitSetCIDViolation = 5'd27
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// 5'd28 - 5'd31 reserved
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} CHERIException deriving(Bits, Eq, FShow);
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typedef struct {
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Bit #(6) cheri_exc_reg;
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CHERIException cheri_exc_code;
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} CSR_XCapCause deriving(Bits, Eq, FShow);
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CSR_XCapCause noCapCause = CSR_XCapCause {cheri_exc_code: None,
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cheri_exc_reg: unpack(0)};
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function Bit#(64) xccsr_to_word(CSR_XCapCause xccsr);
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return zeroExtend({xccsr.cheri_exc_reg, pack(xccsr.cheri_exc_code), 3'b0, 1'b1, 1'b1});
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endfunction
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function Reg#(Bit#(64)) csr_capcause(Reg#(CSR_XCapCause) r);
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return (interface Reg;
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method Bit#(64) _read = xccsr_to_word(r._read);
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method Action _write(Bit#(64) x) =
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r._write(CSR_XCapCause{cheri_exc_reg: x[15:10], cheri_exc_code: unpack(x[9:5]) });
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endinterface);
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endfunction
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// SCR map
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typedef enum {
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`define SCR(s,v) s = v,
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`include "SCRs.bsvi"
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`undef SCR
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// As with CSRs, SCR that catches all unimplemented SCRs
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SCR_None = 5'd10
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} SCR deriving(Bits, Eq, FShow, Bounded);
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function SCR unpackSCR(Bit#(5) x);
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return (case(x)
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`define SCR(s,v) pack(SCR'(s)): (s);
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`include "SCRs.bsvi"
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`undef SCR
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default : (SCR_None);
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endcase);
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endfunction
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function CapPipe update_scr_via_csr (CapPipe old_scr, WordXL new_csr);
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let new_scr = setOffset(old_scr, new_csr);
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let ret = new_scr.value;
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if (!new_scr.exact || (getKind(old_scr) != UNSEALED)) begin
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ret = setValidCap(ret, False);
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end
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return ret;
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endfunction
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RegName cCallRD = 31;
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// Instruction field encodings
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// Top-level opcodes
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Opcode op_cap_Manip = 7'h5b;
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//Opcode op_cap_Mem = 7'h0b; // Not yet implemented
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// ================================================================
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// op_cap_Manip opcode subdivision
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// f3 selects between immediate and 3-reg instructions
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Bit #(3) f3_cap_ThreeOp = 3'h0;
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Bit #(3) f3_cap_CIncOffsetImmediate = 3'h1;
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Bit #(3) f3_cap_CSetBoundsImmediate = 3'h2;
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// 3'h3-3'h7 unused
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// ================================================================
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// op_cap_ThreeOp opcode subdivision
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// f7 selects between 3-reg operations
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// 7'h00 unused
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Bit #(7) f7_cap_CSpecialRW = 7'h01;
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// 7'h02-7'h07 unused
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Bit #(7) f7_cap_CSetBounds = 7'h08;
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Bit #(7) f7_cap_CSetBoundsExact = 7'h09;
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// 7'h0a unused
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Bit #(7) f7_cap_CSeal = 7'h0b;
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Bit #(7) f7_cap_CUnseal = 7'h0c;
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Bit #(7) f7_cap_CAndPerm = 7'h0d;
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Bit #(7) f7_cap_CSetFlags = 7'h0e;
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Bit #(7) f7_cap_CSetOffset = 7'h0f;
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Bit #(7) f7_cap_CSetAddr = 7'h10;
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Bit #(7) f7_cap_CIncOffset = 7'h11;
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Bit #(7) f7_cap_CToPtr = 7'h12;
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Bit #(7) f7_cap_CFromPtr = 7'h13;
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Bit #(7) f7_cap_CSub = 7'h14;
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// 7'h15-7'h1c unused
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Bit #(7) f7_cap_CBuildCap = 7'h1d;
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Bit #(7) f7_cap_CCopyType = 7'h1e;
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Bit #(7) f7_cap_CCSeal = 7'h1f;
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Bit #(7) f7_cap_CTestSubset = 7'h20;
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// 7'h21-7'hfb unused
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Bit #(7) f7_cap_Stores = 7'h7c;
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Bit #(7) f7_cap_Loads = 7'h7d;
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Bit #(7) f7_cap_TwoSrc = 7'h7e;
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Bit #(7) f7_cap_TwoOp = 7'h7f;
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// ================================================================
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// f7_cap_TwoSrc opcode subdivision
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// rd selects between 2-reg operations
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// 5'h00 unused
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Bit #(5) rd_cap_CCall = 5'h01;
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// 5'h02-5'h1f unused
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// ================================================================
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// f7_cap_TwoOp opcode subdivision
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// f5rs2 selects between 2-reg operations (f5rs2 instead of f5 because f5
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// is already used in RISC-V and is in a different position
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Bit #(5) f5rs2_cap_CGetPerm = 5'h00;
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Bit #(5) f5rs2_cap_CGetType = 5'h01;
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Bit #(5) f5rs2_cap_CGetBase = 5'h02;
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Bit #(5) f5rs2_cap_CGetLen = 5'h03;
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Bit #(5) f5rs2_cap_CGetTag = 5'h04;
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Bit #(5) f5rs2_cap_CGetSealed = 5'h05;
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Bit #(5) f5rs2_cap_CGetOffset = 5'h06;
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Bit #(5) f5rs2_cap_CGetFlags = 5'h07;
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Bit #(5) f5rs2_cap_CRRL = 5'h08;
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Bit #(5) f5rs2_cap_CRAM = 5'h09;
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Bit #(5) f5rs2_cap_CMove = 5'h0a;
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Bit #(5) f5rs2_cap_CClearTag = 5'h0b;
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Bit #(5) f5rs2_cap_CJALR = 5'h0c;
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Bit #(5) f5rs2_cap_CClearReg = 5'h0d;
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// 5'h0e unused
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Bit #(5) f5rs2_cap_CGetAddr = 5'h0f;
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Bit #(5) f5rs2_cap_CClearFPReg = 5'h10;
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// 5'h11-5'h1f unused (5'h1f reserved for 1-reg instructions
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// ================================================================
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// f7_cap_{Load, Store} opcode subdivision
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MemReqSize cap_mem_SIZE_B = 'h0;
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MemReqSize cap_mem_SIZE_H = 'h1;
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MemReqSize cap_mem_SIZE_W = 'h2;
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MemReqSize cap_mem_SIZE_D = 'h3;
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//MemReqSize f5rs2_cap_mem_SIZE_Q = 'h4; //TODO
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Bit #(1) cap_mem_ddc = 1'h0;
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Bit #(1) cap_mem_cap = 1'h1;
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Bit #(1) cap_mem_unsigned = 1'h1;
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Bit #(1) cap_mem_signed = 1'h0;
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// ================================================================
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// Other:
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// Region in MISC_MEM for LQ
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Bit #(3) f3_LQ = 3'h2;
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Bit #(3) f3_SQ = 3'b100;
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`ifdef RV64
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Bit #(3) w_SIZE_CAP = f3_SQ;
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Bit #(3) w_SIZE_MAX = f3_SQ;
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`else //RV32
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Bit #(3) w_SIZE_CAP = f3_SD;
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Bit #(3) w_SIZE_MAX = f3_SD;
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`endif
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Bit #(3) f3_AMO_CAP = w_SIZE_CAP;
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// Special cases of Otypes that are extended to XLEN
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Bit #(XLEN) otype_unsealed_ext = -1;
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Bit #(XLEN) otype_sentry_ext = -2;
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Bit #(XLEN) otype_res0_ext = -3;
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Bit #(XLEN) otype_res1_ext = -4;
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