1532 lines
52 KiB
Verilog
1532 lines
52 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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// On Wed Jun 24 20:10:12 BST 2020
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_dmi_read_addr O 1
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// dmi_read_data O 32
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// RDY_dmi_read_data O 1
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// RDY_dmi_write O 1
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// hart0_reset_client_request_get O 1 reg
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// RDY_hart0_reset_client_request_get O 1 reg
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// RDY_hart0_reset_client_response_put O 1 reg
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// hart0_client_run_halt_request_get O 1 reg
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// RDY_hart0_client_run_halt_request_get O 1 reg
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// RDY_hart0_client_run_halt_response_put O 1 reg
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// hart0_get_other_req_get O 4 reg
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// RDY_hart0_get_other_req_get O 1 reg
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// hart0_gpr_mem_client_request_get O 70 reg
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// RDY_hart0_gpr_mem_client_request_get O 1 reg
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// RDY_hart0_gpr_mem_client_response_put O 1 reg
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// hart0_fpr_mem_client_request_get O 70 reg
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// RDY_hart0_fpr_mem_client_request_get O 1 reg
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// RDY_hart0_fpr_mem_client_response_put O 1 reg
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// hart0_csr_mem_client_request_get O 77 reg
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// RDY_hart0_csr_mem_client_request_get O 1 reg
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// RDY_hart0_csr_mem_client_response_put O 1 reg
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// ndm_reset_client_request_get O 1 reg
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// RDY_ndm_reset_client_request_get O 1 reg
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// RDY_ndm_reset_client_response_put O 1 reg
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// master_awid O 4
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// master_awaddr O 64
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// master_awlen O 8
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// master_awsize O 3
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// master_awburst O 2
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// master_awlock O 1
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// master_awcache O 4
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// master_awprot O 3
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// master_awqos O 4
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// master_awregion O 4
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// master_awvalid O 1
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// master_wdata O 64
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// master_wstrb O 8
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// master_wlast O 1
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// master_wuser O 1
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// master_wvalid O 1
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// master_bready O 1
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// master_arid O 4
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// master_araddr O 64
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// master_arlen O 8
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// master_arsize O 3
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// master_arburst O 2
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// master_arlock O 1
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// master_arcache O 4
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// master_arprot O 3
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// master_arqos O 4
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// master_arregion O 4
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// master_arvalid O 1
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// master_rready O 1
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// CLK I 1 clock
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// RST_N I 1 reset
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// dmi_read_addr_dm_addr I 7 reg
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// dmi_write_dm_addr I 7
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// dmi_write_dm_word I 32
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// hart0_reset_client_response_put I 1 reg
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// hart0_client_run_halt_response_put I 1 reg
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// hart0_gpr_mem_client_response_put I 65 reg
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// hart0_fpr_mem_client_response_put I 65 reg
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// hart0_csr_mem_client_response_put I 65 reg
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// ndm_reset_client_response_put I 1 reg
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// master_awready I 1
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// master_wready I 1
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// master_bvalid I 1
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// master_bid I 4
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// master_bresp I 2
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// master_arready I 1
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// master_rvalid I 1
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// master_rid I 4
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// master_rdata I 64
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// master_rresp I 2
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// master_rlast I 1
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// master_ruser I 1
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// EN_dmi_read_addr I 1
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// EN_dmi_write I 1
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// EN_hart0_reset_client_response_put I 1
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// EN_hart0_client_run_halt_response_put I 1
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// EN_hart0_gpr_mem_client_response_put I 1
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// EN_hart0_fpr_mem_client_response_put I 1
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// EN_hart0_csr_mem_client_response_put I 1
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// EN_ndm_reset_client_response_put I 1
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// EN_dmi_read_data I 1
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// EN_hart0_reset_client_request_get I 1
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// EN_hart0_client_run_halt_request_get I 1
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// EN_hart0_get_other_req_get I 1
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// EN_hart0_gpr_mem_client_request_get I 1
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// EN_hart0_fpr_mem_client_request_get I 1
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// EN_hart0_csr_mem_client_request_get I 1
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// EN_ndm_reset_client_request_get I 1
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//
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// Combinational paths from inputs to outputs:
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awid
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awaddr
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awlen
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awsize
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awburst
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awlock
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awcache
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awprot
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awqos
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awregion
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awuser
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// (dmi_write_dm_addr,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_awvalid
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_wdata
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_wstrb
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_wlast
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_wuser
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write) -> master_wvalid
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arid
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_araddr
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arlen
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arsize
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arburst
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arlock
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arcache
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arprot
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arqos
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arregion
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_aruser
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// (dmi_write_dm_addr,
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// dmi_write_dm_word,
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// master_rvalid,
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// master_rid,
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// master_rdata,
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// master_rresp,
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// master_rlast,
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// master_ruser,
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// EN_dmi_write,
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// EN_dmi_read_data) -> master_arvalid
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// EN_dmi_read_data -> dmi_read_data
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDebug_Module(CLK,
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RST_N,
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dmi_read_addr_dm_addr,
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EN_dmi_read_addr,
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RDY_dmi_read_addr,
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EN_dmi_read_data,
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dmi_read_data,
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RDY_dmi_read_data,
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dmi_write_dm_addr,
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dmi_write_dm_word,
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EN_dmi_write,
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RDY_dmi_write,
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EN_hart0_reset_client_request_get,
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hart0_reset_client_request_get,
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RDY_hart0_reset_client_request_get,
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hart0_reset_client_response_put,
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EN_hart0_reset_client_response_put,
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RDY_hart0_reset_client_response_put,
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EN_hart0_client_run_halt_request_get,
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hart0_client_run_halt_request_get,
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RDY_hart0_client_run_halt_request_get,
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hart0_client_run_halt_response_put,
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EN_hart0_client_run_halt_response_put,
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RDY_hart0_client_run_halt_response_put,
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EN_hart0_get_other_req_get,
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hart0_get_other_req_get,
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RDY_hart0_get_other_req_get,
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EN_hart0_gpr_mem_client_request_get,
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hart0_gpr_mem_client_request_get,
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RDY_hart0_gpr_mem_client_request_get,
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hart0_gpr_mem_client_response_put,
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EN_hart0_gpr_mem_client_response_put,
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RDY_hart0_gpr_mem_client_response_put,
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EN_hart0_fpr_mem_client_request_get,
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hart0_fpr_mem_client_request_get,
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RDY_hart0_fpr_mem_client_request_get,
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hart0_fpr_mem_client_response_put,
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EN_hart0_fpr_mem_client_response_put,
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RDY_hart0_fpr_mem_client_response_put,
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EN_hart0_csr_mem_client_request_get,
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hart0_csr_mem_client_request_get,
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RDY_hart0_csr_mem_client_request_get,
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hart0_csr_mem_client_response_put,
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EN_hart0_csr_mem_client_response_put,
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RDY_hart0_csr_mem_client_response_put,
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EN_ndm_reset_client_request_get,
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ndm_reset_client_request_get,
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RDY_ndm_reset_client_request_get,
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ndm_reset_client_response_put,
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EN_ndm_reset_client_response_put,
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RDY_ndm_reset_client_response_put,
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master_awid,
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master_awaddr,
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master_awlen,
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master_awsize,
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master_awburst,
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master_awlock,
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master_awcache,
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master_awprot,
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master_awqos,
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master_awregion,
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master_awvalid,
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master_awready,
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master_wdata,
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master_wstrb,
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master_wlast,
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master_wuser,
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master_wvalid,
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master_wready,
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master_bvalid,
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master_bid,
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master_bresp,
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master_bready,
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master_arid,
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master_araddr,
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master_arlen,
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master_arsize,
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master_arburst,
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master_arlock,
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master_arcache,
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master_arprot,
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master_arqos,
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master_arregion,
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master_arvalid,
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master_arready,
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master_rvalid,
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master_rid,
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master_rdata,
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master_rresp,
|
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master_rlast,
|
|
master_ruser,
|
|
|
|
master_rready);
|
|
input CLK;
|
|
input RST_N;
|
|
|
|
// action method dmi_read_addr
|
|
input [6 : 0] dmi_read_addr_dm_addr;
|
|
input EN_dmi_read_addr;
|
|
output RDY_dmi_read_addr;
|
|
|
|
// actionvalue method dmi_read_data
|
|
input EN_dmi_read_data;
|
|
output [31 : 0] dmi_read_data;
|
|
output RDY_dmi_read_data;
|
|
|
|
// action method dmi_write
|
|
input [6 : 0] dmi_write_dm_addr;
|
|
input [31 : 0] dmi_write_dm_word;
|
|
input EN_dmi_write;
|
|
output RDY_dmi_write;
|
|
|
|
// actionvalue method hart0_reset_client_request_get
|
|
input EN_hart0_reset_client_request_get;
|
|
output hart0_reset_client_request_get;
|
|
output RDY_hart0_reset_client_request_get;
|
|
|
|
// action method hart0_reset_client_response_put
|
|
input hart0_reset_client_response_put;
|
|
input EN_hart0_reset_client_response_put;
|
|
output RDY_hart0_reset_client_response_put;
|
|
|
|
// actionvalue method hart0_client_run_halt_request_get
|
|
input EN_hart0_client_run_halt_request_get;
|
|
output hart0_client_run_halt_request_get;
|
|
output RDY_hart0_client_run_halt_request_get;
|
|
|
|
// action method hart0_client_run_halt_response_put
|
|
input hart0_client_run_halt_response_put;
|
|
input EN_hart0_client_run_halt_response_put;
|
|
output RDY_hart0_client_run_halt_response_put;
|
|
|
|
// actionvalue method hart0_get_other_req_get
|
|
input EN_hart0_get_other_req_get;
|
|
output [3 : 0] hart0_get_other_req_get;
|
|
output RDY_hart0_get_other_req_get;
|
|
|
|
// actionvalue method hart0_gpr_mem_client_request_get
|
|
input EN_hart0_gpr_mem_client_request_get;
|
|
output [69 : 0] hart0_gpr_mem_client_request_get;
|
|
output RDY_hart0_gpr_mem_client_request_get;
|
|
|
|
// action method hart0_gpr_mem_client_response_put
|
|
input [64 : 0] hart0_gpr_mem_client_response_put;
|
|
input EN_hart0_gpr_mem_client_response_put;
|
|
output RDY_hart0_gpr_mem_client_response_put;
|
|
|
|
// actionvalue method hart0_fpr_mem_client_request_get
|
|
input EN_hart0_fpr_mem_client_request_get;
|
|
output [69 : 0] hart0_fpr_mem_client_request_get;
|
|
output RDY_hart0_fpr_mem_client_request_get;
|
|
|
|
// action method hart0_fpr_mem_client_response_put
|
|
input [64 : 0] hart0_fpr_mem_client_response_put;
|
|
input EN_hart0_fpr_mem_client_response_put;
|
|
output RDY_hart0_fpr_mem_client_response_put;
|
|
|
|
// actionvalue method hart0_csr_mem_client_request_get
|
|
input EN_hart0_csr_mem_client_request_get;
|
|
output [76 : 0] hart0_csr_mem_client_request_get;
|
|
output RDY_hart0_csr_mem_client_request_get;
|
|
|
|
// action method hart0_csr_mem_client_response_put
|
|
input [64 : 0] hart0_csr_mem_client_response_put;
|
|
input EN_hart0_csr_mem_client_response_put;
|
|
output RDY_hart0_csr_mem_client_response_put;
|
|
|
|
// actionvalue method ndm_reset_client_request_get
|
|
input EN_ndm_reset_client_request_get;
|
|
output ndm_reset_client_request_get;
|
|
output RDY_ndm_reset_client_request_get;
|
|
|
|
// action method ndm_reset_client_response_put
|
|
input ndm_reset_client_response_put;
|
|
input EN_ndm_reset_client_response_put;
|
|
output RDY_ndm_reset_client_response_put;
|
|
|
|
// value method master_aw_awid
|
|
output [3 : 0] master_awid;
|
|
|
|
// value method master_aw_awaddr
|
|
output [63 : 0] master_awaddr;
|
|
|
|
// value method master_aw_awlen
|
|
output [7 : 0] master_awlen;
|
|
|
|
// value method master_aw_awsize
|
|
output [2 : 0] master_awsize;
|
|
|
|
// value method master_aw_awburst
|
|
output [1 : 0] master_awburst;
|
|
|
|
// value method master_aw_awlock
|
|
output master_awlock;
|
|
|
|
// value method master_aw_awcache
|
|
output [3 : 0] master_awcache;
|
|
|
|
// value method master_aw_awprot
|
|
output [2 : 0] master_awprot;
|
|
|
|
// value method master_aw_awqos
|
|
output [3 : 0] master_awqos;
|
|
|
|
// value method master_aw_awregion
|
|
output [3 : 0] master_awregion;
|
|
|
|
// value method master_aw_awuser
|
|
|
|
// value method master_aw_awvalid
|
|
output master_awvalid;
|
|
|
|
// action method master_aw_awready
|
|
input master_awready;
|
|
|
|
// value method master_w_wdata
|
|
output [63 : 0] master_wdata;
|
|
|
|
// value method master_w_wstrb
|
|
output [7 : 0] master_wstrb;
|
|
|
|
// value method master_w_wlast
|
|
output master_wlast;
|
|
|
|
// value method master_w_wuser
|
|
output master_wuser;
|
|
|
|
// value method master_w_wvalid
|
|
output master_wvalid;
|
|
|
|
// action method master_w_wready
|
|
input master_wready;
|
|
|
|
// action method master_b_bflit
|
|
input master_bvalid;
|
|
input [3 : 0] master_bid;
|
|
input [1 : 0] master_bresp;
|
|
|
|
// value method master_b_bready
|
|
output master_bready;
|
|
|
|
// value method master_ar_arid
|
|
output [3 : 0] master_arid;
|
|
|
|
// value method master_ar_araddr
|
|
output [63 : 0] master_araddr;
|
|
|
|
// value method master_ar_arlen
|
|
output [7 : 0] master_arlen;
|
|
|
|
// value method master_ar_arsize
|
|
output [2 : 0] master_arsize;
|
|
|
|
// value method master_ar_arburst
|
|
output [1 : 0] master_arburst;
|
|
|
|
// value method master_ar_arlock
|
|
output master_arlock;
|
|
|
|
// value method master_ar_arcache
|
|
output [3 : 0] master_arcache;
|
|
|
|
// value method master_ar_arprot
|
|
output [2 : 0] master_arprot;
|
|
|
|
// value method master_ar_arqos
|
|
output [3 : 0] master_arqos;
|
|
|
|
// value method master_ar_arregion
|
|
output [3 : 0] master_arregion;
|
|
|
|
// value method master_ar_aruser
|
|
|
|
// value method master_ar_arvalid
|
|
output master_arvalid;
|
|
|
|
// action method master_ar_arready
|
|
input master_arready;
|
|
|
|
// action method master_r_rflit
|
|
input master_rvalid;
|
|
input [3 : 0] master_rid;
|
|
input [63 : 0] master_rdata;
|
|
input [1 : 0] master_rresp;
|
|
input master_rlast;
|
|
input master_ruser;
|
|
|
|
// value method master_r_rready
|
|
output master_rready;
|
|
|
|
// signals for module outputs
|
|
reg [31 : 0] dmi_read_data;
|
|
wire [76 : 0] hart0_csr_mem_client_request_get;
|
|
wire [69 : 0] hart0_fpr_mem_client_request_get,
|
|
hart0_gpr_mem_client_request_get;
|
|
wire [63 : 0] master_araddr, master_awaddr, master_wdata;
|
|
wire [7 : 0] master_arlen, master_awlen, master_wstrb;
|
|
wire [3 : 0] hart0_get_other_req_get,
|
|
master_arcache,
|
|
master_arid,
|
|
master_arqos,
|
|
master_arregion,
|
|
master_awcache,
|
|
master_awid,
|
|
master_awqos,
|
|
master_awregion;
|
|
wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize;
|
|
wire [1 : 0] master_arburst, master_awburst;
|
|
wire RDY_dmi_read_addr,
|
|
RDY_dmi_read_data,
|
|
RDY_dmi_write,
|
|
RDY_hart0_client_run_halt_request_get,
|
|
RDY_hart0_client_run_halt_response_put,
|
|
RDY_hart0_csr_mem_client_request_get,
|
|
RDY_hart0_csr_mem_client_response_put,
|
|
RDY_hart0_fpr_mem_client_request_get,
|
|
RDY_hart0_fpr_mem_client_response_put,
|
|
RDY_hart0_get_other_req_get,
|
|
RDY_hart0_gpr_mem_client_request_get,
|
|
RDY_hart0_gpr_mem_client_response_put,
|
|
RDY_hart0_reset_client_request_get,
|
|
RDY_hart0_reset_client_response_put,
|
|
RDY_ndm_reset_client_request_get,
|
|
RDY_ndm_reset_client_response_put,
|
|
hart0_client_run_halt_request_get,
|
|
hart0_reset_client_request_get,
|
|
master_arlock,
|
|
master_arvalid,
|
|
master_awlock,
|
|
master_awvalid,
|
|
master_bready,
|
|
master_rready,
|
|
master_wlast,
|
|
master_wuser,
|
|
master_wvalid,
|
|
ndm_reset_client_request_get;
|
|
|
|
// ports of submodule dm_abstract_commands
|
|
wire [76 : 0] dm_abstract_commands$hart0_csr_mem_client_request_get;
|
|
wire [69 : 0] dm_abstract_commands$hart0_fpr_mem_client_request_get,
|
|
dm_abstract_commands$hart0_gpr_mem_client_request_get;
|
|
wire [64 : 0] dm_abstract_commands$hart0_csr_mem_client_response_put,
|
|
dm_abstract_commands$hart0_fpr_mem_client_response_put,
|
|
dm_abstract_commands$hart0_gpr_mem_client_response_put;
|
|
wire [31 : 0] dm_abstract_commands$av_read,
|
|
dm_abstract_commands$write_dm_word;
|
|
wire [6 : 0] dm_abstract_commands$av_read_dm_addr,
|
|
dm_abstract_commands$write_dm_addr;
|
|
wire dm_abstract_commands$EN_av_read,
|
|
dm_abstract_commands$EN_hart0_csr_mem_client_request_get,
|
|
dm_abstract_commands$EN_hart0_csr_mem_client_response_put,
|
|
dm_abstract_commands$EN_hart0_fpr_mem_client_request_get,
|
|
dm_abstract_commands$EN_hart0_fpr_mem_client_response_put,
|
|
dm_abstract_commands$EN_hart0_gpr_mem_client_request_get,
|
|
dm_abstract_commands$EN_hart0_gpr_mem_client_response_put,
|
|
dm_abstract_commands$EN_reset,
|
|
dm_abstract_commands$EN_write,
|
|
dm_abstract_commands$RDY_hart0_csr_mem_client_request_get,
|
|
dm_abstract_commands$RDY_hart0_csr_mem_client_response_put,
|
|
dm_abstract_commands$RDY_hart0_fpr_mem_client_request_get,
|
|
dm_abstract_commands$RDY_hart0_fpr_mem_client_response_put,
|
|
dm_abstract_commands$RDY_hart0_gpr_mem_client_request_get,
|
|
dm_abstract_commands$RDY_hart0_gpr_mem_client_response_put;
|
|
|
|
// ports of submodule dm_run_control
|
|
wire [31 : 0] dm_run_control$av_read, dm_run_control$write_dm_word;
|
|
wire [6 : 0] dm_run_control$av_read_dm_addr, dm_run_control$write_dm_addr;
|
|
wire [3 : 0] dm_run_control$hart0_get_other_req_get;
|
|
wire dm_run_control$EN_av_read,
|
|
dm_run_control$EN_hart0_client_run_halt_request_get,
|
|
dm_run_control$EN_hart0_client_run_halt_response_put,
|
|
dm_run_control$EN_hart0_get_other_req_get,
|
|
dm_run_control$EN_hart0_reset_client_request_get,
|
|
dm_run_control$EN_hart0_reset_client_response_put,
|
|
dm_run_control$EN_ndm_reset_client_request_get,
|
|
dm_run_control$EN_ndm_reset_client_response_put,
|
|
dm_run_control$EN_reset,
|
|
dm_run_control$EN_write,
|
|
dm_run_control$RDY_hart0_client_run_halt_request_get,
|
|
dm_run_control$RDY_hart0_client_run_halt_response_put,
|
|
dm_run_control$RDY_hart0_get_other_req_get,
|
|
dm_run_control$RDY_hart0_reset_client_request_get,
|
|
dm_run_control$RDY_hart0_reset_client_response_put,
|
|
dm_run_control$RDY_ndm_reset_client_request_get,
|
|
dm_run_control$RDY_ndm_reset_client_response_put,
|
|
dm_run_control$RDY_write,
|
|
dm_run_control$dmactive,
|
|
dm_run_control$hart0_client_run_halt_request_get,
|
|
dm_run_control$hart0_client_run_halt_response_put,
|
|
dm_run_control$hart0_reset_client_request_get,
|
|
dm_run_control$hart0_reset_client_response_put,
|
|
dm_run_control$ndm_reset_client_request_get,
|
|
dm_run_control$ndm_reset_client_response_put;
|
|
|
|
// ports of submodule dm_system_bus
|
|
wire [63 : 0] dm_system_bus$master_araddr,
|
|
dm_system_bus$master_awaddr,
|
|
dm_system_bus$master_rdata,
|
|
dm_system_bus$master_wdata;
|
|
wire [31 : 0] dm_system_bus$av_read, dm_system_bus$write_dm_word;
|
|
wire [7 : 0] dm_system_bus$master_arlen,
|
|
dm_system_bus$master_awlen,
|
|
dm_system_bus$master_wstrb;
|
|
wire [6 : 0] dm_system_bus$av_read_dm_addr, dm_system_bus$write_dm_addr;
|
|
wire [3 : 0] dm_system_bus$master_arcache,
|
|
dm_system_bus$master_arid,
|
|
dm_system_bus$master_arqos,
|
|
dm_system_bus$master_arregion,
|
|
dm_system_bus$master_awcache,
|
|
dm_system_bus$master_awid,
|
|
dm_system_bus$master_awqos,
|
|
dm_system_bus$master_awregion,
|
|
dm_system_bus$master_bid,
|
|
dm_system_bus$master_rid;
|
|
wire [2 : 0] dm_system_bus$master_arprot,
|
|
dm_system_bus$master_arsize,
|
|
dm_system_bus$master_awprot,
|
|
dm_system_bus$master_awsize;
|
|
wire [1 : 0] dm_system_bus$master_arburst,
|
|
dm_system_bus$master_awburst,
|
|
dm_system_bus$master_bresp,
|
|
dm_system_bus$master_rresp;
|
|
wire dm_system_bus$EN_av_read,
|
|
dm_system_bus$EN_reset,
|
|
dm_system_bus$EN_write,
|
|
dm_system_bus$RDY_av_read,
|
|
dm_system_bus$RDY_reset,
|
|
dm_system_bus$RDY_write,
|
|
dm_system_bus$master_arlock,
|
|
dm_system_bus$master_arready,
|
|
dm_system_bus$master_arvalid,
|
|
dm_system_bus$master_awlock,
|
|
dm_system_bus$master_awready,
|
|
dm_system_bus$master_awvalid,
|
|
dm_system_bus$master_bready,
|
|
dm_system_bus$master_bvalid,
|
|
dm_system_bus$master_rlast,
|
|
dm_system_bus$master_rready,
|
|
dm_system_bus$master_ruser,
|
|
dm_system_bus$master_rvalid,
|
|
dm_system_bus$master_wlast,
|
|
dm_system_bus$master_wready,
|
|
dm_system_bus$master_wuser,
|
|
dm_system_bus$master_wvalid;
|
|
|
|
// ports of submodule f_read_addr
|
|
wire [6 : 0] f_read_addr$D_IN, f_read_addr$D_OUT;
|
|
wire f_read_addr$CLR,
|
|
f_read_addr$DEQ,
|
|
f_read_addr$EMPTY_N,
|
|
f_read_addr$ENQ,
|
|
f_read_addr$FULL_N;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_rl_reset,
|
|
CAN_FIRE_dmi_read_addr,
|
|
CAN_FIRE_dmi_read_data,
|
|
CAN_FIRE_dmi_write,
|
|
CAN_FIRE_hart0_client_run_halt_request_get,
|
|
CAN_FIRE_hart0_client_run_halt_response_put,
|
|
CAN_FIRE_hart0_csr_mem_client_request_get,
|
|
CAN_FIRE_hart0_csr_mem_client_response_put,
|
|
CAN_FIRE_hart0_fpr_mem_client_request_get,
|
|
CAN_FIRE_hart0_fpr_mem_client_response_put,
|
|
CAN_FIRE_hart0_get_other_req_get,
|
|
CAN_FIRE_hart0_gpr_mem_client_request_get,
|
|
CAN_FIRE_hart0_gpr_mem_client_response_put,
|
|
CAN_FIRE_hart0_reset_client_request_get,
|
|
CAN_FIRE_hart0_reset_client_response_put,
|
|
CAN_FIRE_master_ar_arready,
|
|
CAN_FIRE_master_aw_awready,
|
|
CAN_FIRE_master_b_bflit,
|
|
CAN_FIRE_master_r_rflit,
|
|
CAN_FIRE_master_w_wready,
|
|
CAN_FIRE_ndm_reset_client_request_get,
|
|
CAN_FIRE_ndm_reset_client_response_put,
|
|
WILL_FIRE_RL_rl_reset,
|
|
WILL_FIRE_dmi_read_addr,
|
|
WILL_FIRE_dmi_read_data,
|
|
WILL_FIRE_dmi_write,
|
|
WILL_FIRE_hart0_client_run_halt_request_get,
|
|
WILL_FIRE_hart0_client_run_halt_response_put,
|
|
WILL_FIRE_hart0_csr_mem_client_request_get,
|
|
WILL_FIRE_hart0_csr_mem_client_response_put,
|
|
WILL_FIRE_hart0_fpr_mem_client_request_get,
|
|
WILL_FIRE_hart0_fpr_mem_client_response_put,
|
|
WILL_FIRE_hart0_get_other_req_get,
|
|
WILL_FIRE_hart0_gpr_mem_client_request_get,
|
|
WILL_FIRE_hart0_gpr_mem_client_response_put,
|
|
WILL_FIRE_hart0_reset_client_request_get,
|
|
WILL_FIRE_hart0_reset_client_response_put,
|
|
WILL_FIRE_master_ar_arready,
|
|
WILL_FIRE_master_aw_awready,
|
|
WILL_FIRE_master_b_bflit,
|
|
WILL_FIRE_master_r_rflit,
|
|
WILL_FIRE_master_w_wready,
|
|
WILL_FIRE_ndm_reset_client_request_get,
|
|
WILL_FIRE_ndm_reset_client_response_put;
|
|
|
|
// declarations used by system tasks
|
|
// synopsys translate_off
|
|
reg [31 : 0] v__h772;
|
|
reg [31 : 0] v__h766;
|
|
// synopsys translate_on
|
|
|
|
// action method dmi_read_addr
|
|
assign RDY_dmi_read_addr = dm_run_control$dmactive && f_read_addr$FULL_N ;
|
|
assign CAN_FIRE_dmi_read_addr =
|
|
dm_run_control$dmactive && f_read_addr$FULL_N ;
|
|
assign WILL_FIRE_dmi_read_addr = EN_dmi_read_addr ;
|
|
|
|
// actionvalue method dmi_read_data
|
|
always@(f_read_addr$D_OUT or
|
|
dm_abstract_commands$av_read or
|
|
dm_run_control$av_read or dm_system_bus$av_read)
|
|
begin
|
|
case (f_read_addr$D_OUT)
|
|
7'h04,
|
|
7'h05,
|
|
7'h06,
|
|
7'h07,
|
|
7'h08,
|
|
7'h09,
|
|
7'h0A,
|
|
7'h0B,
|
|
7'h0C,
|
|
7'h0D,
|
|
7'h0F,
|
|
7'h16,
|
|
7'h17,
|
|
7'h18,
|
|
7'h20:
|
|
dmi_read_data = dm_abstract_commands$av_read;
|
|
7'h10,
|
|
7'h11,
|
|
7'h12,
|
|
7'h13,
|
|
7'h14,
|
|
7'h15,
|
|
7'h19,
|
|
7'h30,
|
|
7'h40,
|
|
7'h5F,
|
|
7'h60:
|
|
dmi_read_data = dm_run_control$av_read;
|
|
7'h38, 7'h39, 7'h3A, 7'h3B, 7'h3C, 7'h3D, 7'h3E, 7'h3F:
|
|
dmi_read_data = dm_system_bus$av_read;
|
|
default: dmi_read_data = 32'd0;
|
|
endcase
|
|
end
|
|
assign RDY_dmi_read_data =
|
|
f_read_addr$EMPTY_N &&
|
|
(f_read_addr$D_OUT != 7'h38 && f_read_addr$D_OUT != 7'h39 &&
|
|
f_read_addr$D_OUT != 7'h3A &&
|
|
f_read_addr$D_OUT != 7'h3B &&
|
|
f_read_addr$D_OUT != 7'h3C &&
|
|
f_read_addr$D_OUT != 7'h3D &&
|
|
f_read_addr$D_OUT != 7'h3E &&
|
|
f_read_addr$D_OUT != 7'h3F ||
|
|
dm_system_bus$RDY_av_read) ;
|
|
assign CAN_FIRE_dmi_read_data = RDY_dmi_read_data ;
|
|
assign WILL_FIRE_dmi_read_data = EN_dmi_read_data ;
|
|
|
|
// action method dmi_write
|
|
assign RDY_dmi_write =
|
|
dm_run_control$dmactive && dm_run_control$RDY_write &&
|
|
dm_system_bus$RDY_write ;
|
|
assign CAN_FIRE_dmi_write =
|
|
dm_run_control$dmactive && dm_run_control$RDY_write &&
|
|
dm_system_bus$RDY_write ;
|
|
assign WILL_FIRE_dmi_write = EN_dmi_write ;
|
|
|
|
// actionvalue method hart0_reset_client_request_get
|
|
assign hart0_reset_client_request_get =
|
|
dm_run_control$hart0_reset_client_request_get ;
|
|
assign RDY_hart0_reset_client_request_get =
|
|
dm_run_control$RDY_hart0_reset_client_request_get ;
|
|
assign CAN_FIRE_hart0_reset_client_request_get =
|
|
dm_run_control$RDY_hart0_reset_client_request_get ;
|
|
assign WILL_FIRE_hart0_reset_client_request_get =
|
|
EN_hart0_reset_client_request_get ;
|
|
|
|
// action method hart0_reset_client_response_put
|
|
assign RDY_hart0_reset_client_response_put =
|
|
dm_run_control$RDY_hart0_reset_client_response_put ;
|
|
assign CAN_FIRE_hart0_reset_client_response_put =
|
|
dm_run_control$RDY_hart0_reset_client_response_put ;
|
|
assign WILL_FIRE_hart0_reset_client_response_put =
|
|
EN_hart0_reset_client_response_put ;
|
|
|
|
// actionvalue method hart0_client_run_halt_request_get
|
|
assign hart0_client_run_halt_request_get =
|
|
dm_run_control$hart0_client_run_halt_request_get ;
|
|
assign RDY_hart0_client_run_halt_request_get =
|
|
dm_run_control$RDY_hart0_client_run_halt_request_get ;
|
|
assign CAN_FIRE_hart0_client_run_halt_request_get =
|
|
dm_run_control$RDY_hart0_client_run_halt_request_get ;
|
|
assign WILL_FIRE_hart0_client_run_halt_request_get =
|
|
EN_hart0_client_run_halt_request_get ;
|
|
|
|
// action method hart0_client_run_halt_response_put
|
|
assign RDY_hart0_client_run_halt_response_put =
|
|
dm_run_control$RDY_hart0_client_run_halt_response_put ;
|
|
assign CAN_FIRE_hart0_client_run_halt_response_put =
|
|
dm_run_control$RDY_hart0_client_run_halt_response_put ;
|
|
assign WILL_FIRE_hart0_client_run_halt_response_put =
|
|
EN_hart0_client_run_halt_response_put ;
|
|
|
|
// actionvalue method hart0_get_other_req_get
|
|
assign hart0_get_other_req_get = dm_run_control$hart0_get_other_req_get ;
|
|
assign RDY_hart0_get_other_req_get =
|
|
dm_run_control$RDY_hart0_get_other_req_get ;
|
|
assign CAN_FIRE_hart0_get_other_req_get =
|
|
dm_run_control$RDY_hart0_get_other_req_get ;
|
|
assign WILL_FIRE_hart0_get_other_req_get = EN_hart0_get_other_req_get ;
|
|
|
|
// actionvalue method hart0_gpr_mem_client_request_get
|
|
assign hart0_gpr_mem_client_request_get =
|
|
dm_abstract_commands$hart0_gpr_mem_client_request_get ;
|
|
assign RDY_hart0_gpr_mem_client_request_get =
|
|
dm_abstract_commands$RDY_hart0_gpr_mem_client_request_get ;
|
|
assign CAN_FIRE_hart0_gpr_mem_client_request_get =
|
|
dm_abstract_commands$RDY_hart0_gpr_mem_client_request_get ;
|
|
assign WILL_FIRE_hart0_gpr_mem_client_request_get =
|
|
EN_hart0_gpr_mem_client_request_get ;
|
|
|
|
// action method hart0_gpr_mem_client_response_put
|
|
assign RDY_hart0_gpr_mem_client_response_put =
|
|
dm_abstract_commands$RDY_hart0_gpr_mem_client_response_put ;
|
|
assign CAN_FIRE_hart0_gpr_mem_client_response_put =
|
|
dm_abstract_commands$RDY_hart0_gpr_mem_client_response_put ;
|
|
assign WILL_FIRE_hart0_gpr_mem_client_response_put =
|
|
EN_hart0_gpr_mem_client_response_put ;
|
|
|
|
// actionvalue method hart0_fpr_mem_client_request_get
|
|
assign hart0_fpr_mem_client_request_get =
|
|
dm_abstract_commands$hart0_fpr_mem_client_request_get ;
|
|
assign RDY_hart0_fpr_mem_client_request_get =
|
|
dm_abstract_commands$RDY_hart0_fpr_mem_client_request_get ;
|
|
assign CAN_FIRE_hart0_fpr_mem_client_request_get =
|
|
dm_abstract_commands$RDY_hart0_fpr_mem_client_request_get ;
|
|
assign WILL_FIRE_hart0_fpr_mem_client_request_get =
|
|
EN_hart0_fpr_mem_client_request_get ;
|
|
|
|
// action method hart0_fpr_mem_client_response_put
|
|
assign RDY_hart0_fpr_mem_client_response_put =
|
|
dm_abstract_commands$RDY_hart0_fpr_mem_client_response_put ;
|
|
assign CAN_FIRE_hart0_fpr_mem_client_response_put =
|
|
dm_abstract_commands$RDY_hart0_fpr_mem_client_response_put ;
|
|
assign WILL_FIRE_hart0_fpr_mem_client_response_put =
|
|
EN_hart0_fpr_mem_client_response_put ;
|
|
|
|
// actionvalue method hart0_csr_mem_client_request_get
|
|
assign hart0_csr_mem_client_request_get =
|
|
dm_abstract_commands$hart0_csr_mem_client_request_get ;
|
|
assign RDY_hart0_csr_mem_client_request_get =
|
|
dm_abstract_commands$RDY_hart0_csr_mem_client_request_get ;
|
|
assign CAN_FIRE_hart0_csr_mem_client_request_get =
|
|
dm_abstract_commands$RDY_hart0_csr_mem_client_request_get ;
|
|
assign WILL_FIRE_hart0_csr_mem_client_request_get =
|
|
EN_hart0_csr_mem_client_request_get ;
|
|
|
|
// action method hart0_csr_mem_client_response_put
|
|
assign RDY_hart0_csr_mem_client_response_put =
|
|
dm_abstract_commands$RDY_hart0_csr_mem_client_response_put ;
|
|
assign CAN_FIRE_hart0_csr_mem_client_response_put =
|
|
dm_abstract_commands$RDY_hart0_csr_mem_client_response_put ;
|
|
assign WILL_FIRE_hart0_csr_mem_client_response_put =
|
|
EN_hart0_csr_mem_client_response_put ;
|
|
|
|
// actionvalue method ndm_reset_client_request_get
|
|
assign ndm_reset_client_request_get =
|
|
dm_run_control$ndm_reset_client_request_get ;
|
|
assign RDY_ndm_reset_client_request_get =
|
|
dm_run_control$RDY_ndm_reset_client_request_get ;
|
|
assign CAN_FIRE_ndm_reset_client_request_get =
|
|
dm_run_control$RDY_ndm_reset_client_request_get ;
|
|
assign WILL_FIRE_ndm_reset_client_request_get =
|
|
EN_ndm_reset_client_request_get ;
|
|
|
|
// action method ndm_reset_client_response_put
|
|
assign RDY_ndm_reset_client_response_put =
|
|
dm_run_control$RDY_ndm_reset_client_response_put ;
|
|
assign CAN_FIRE_ndm_reset_client_response_put =
|
|
dm_run_control$RDY_ndm_reset_client_response_put ;
|
|
assign WILL_FIRE_ndm_reset_client_response_put =
|
|
EN_ndm_reset_client_response_put ;
|
|
|
|
// value method master_aw_awid
|
|
assign master_awid = dm_system_bus$master_awid ;
|
|
|
|
// value method master_aw_awaddr
|
|
assign master_awaddr = dm_system_bus$master_awaddr ;
|
|
|
|
// value method master_aw_awlen
|
|
assign master_awlen = dm_system_bus$master_awlen ;
|
|
|
|
// value method master_aw_awsize
|
|
assign master_awsize = dm_system_bus$master_awsize ;
|
|
|
|
// value method master_aw_awburst
|
|
assign master_awburst = dm_system_bus$master_awburst ;
|
|
|
|
// value method master_aw_awlock
|
|
assign master_awlock = dm_system_bus$master_awlock ;
|
|
|
|
// value method master_aw_awcache
|
|
assign master_awcache = dm_system_bus$master_awcache ;
|
|
|
|
// value method master_aw_awprot
|
|
assign master_awprot = dm_system_bus$master_awprot ;
|
|
|
|
// value method master_aw_awqos
|
|
assign master_awqos = dm_system_bus$master_awqos ;
|
|
|
|
// value method master_aw_awregion
|
|
assign master_awregion = dm_system_bus$master_awregion ;
|
|
|
|
// value method master_aw_awvalid
|
|
assign master_awvalid = dm_system_bus$master_awvalid ;
|
|
|
|
// action method master_aw_awready
|
|
assign CAN_FIRE_master_aw_awready = 1'd1 ;
|
|
assign WILL_FIRE_master_aw_awready = 1'd1 ;
|
|
|
|
// value method master_w_wdata
|
|
assign master_wdata = dm_system_bus$master_wdata ;
|
|
|
|
// value method master_w_wstrb
|
|
assign master_wstrb = dm_system_bus$master_wstrb ;
|
|
|
|
// value method master_w_wlast
|
|
assign master_wlast = dm_system_bus$master_wlast ;
|
|
|
|
// value method master_w_wuser
|
|
assign master_wuser = dm_system_bus$master_wuser ;
|
|
|
|
// value method master_w_wvalid
|
|
assign master_wvalid = dm_system_bus$master_wvalid ;
|
|
|
|
// action method master_w_wready
|
|
assign CAN_FIRE_master_w_wready = 1'd1 ;
|
|
assign WILL_FIRE_master_w_wready = 1'd1 ;
|
|
|
|
// action method master_b_bflit
|
|
assign CAN_FIRE_master_b_bflit = 1'd1 ;
|
|
assign WILL_FIRE_master_b_bflit = 1'd1 ;
|
|
|
|
// value method master_b_bready
|
|
assign master_bready = dm_system_bus$master_bready ;
|
|
|
|
// value method master_ar_arid
|
|
assign master_arid = dm_system_bus$master_arid ;
|
|
|
|
// value method master_ar_araddr
|
|
assign master_araddr = dm_system_bus$master_araddr ;
|
|
|
|
// value method master_ar_arlen
|
|
assign master_arlen = dm_system_bus$master_arlen ;
|
|
|
|
// value method master_ar_arsize
|
|
assign master_arsize = dm_system_bus$master_arsize ;
|
|
|
|
// value method master_ar_arburst
|
|
assign master_arburst = dm_system_bus$master_arburst ;
|
|
|
|
// value method master_ar_arlock
|
|
assign master_arlock = dm_system_bus$master_arlock ;
|
|
|
|
// value method master_ar_arcache
|
|
assign master_arcache = dm_system_bus$master_arcache ;
|
|
|
|
// value method master_ar_arprot
|
|
assign master_arprot = dm_system_bus$master_arprot ;
|
|
|
|
// value method master_ar_arqos
|
|
assign master_arqos = dm_system_bus$master_arqos ;
|
|
|
|
// value method master_ar_arregion
|
|
assign master_arregion = dm_system_bus$master_arregion ;
|
|
|
|
// value method master_ar_arvalid
|
|
assign master_arvalid = dm_system_bus$master_arvalid ;
|
|
|
|
// action method master_ar_arready
|
|
assign CAN_FIRE_master_ar_arready = 1'd1 ;
|
|
assign WILL_FIRE_master_ar_arready = 1'd1 ;
|
|
|
|
// action method master_r_rflit
|
|
assign CAN_FIRE_master_r_rflit = 1'd1 ;
|
|
assign WILL_FIRE_master_r_rflit = 1'd1 ;
|
|
|
|
// value method master_r_rready
|
|
assign master_rready = dm_system_bus$master_rready ;
|
|
|
|
// submodule dm_abstract_commands
|
|
mkDM_Abstract_Commands dm_abstract_commands(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.av_read_dm_addr(dm_abstract_commands$av_read_dm_addr),
|
|
.hart0_csr_mem_client_response_put(dm_abstract_commands$hart0_csr_mem_client_response_put),
|
|
.hart0_fpr_mem_client_response_put(dm_abstract_commands$hart0_fpr_mem_client_response_put),
|
|
.hart0_gpr_mem_client_response_put(dm_abstract_commands$hart0_gpr_mem_client_response_put),
|
|
.write_dm_addr(dm_abstract_commands$write_dm_addr),
|
|
.write_dm_word(dm_abstract_commands$write_dm_word),
|
|
.EN_reset(dm_abstract_commands$EN_reset),
|
|
.EN_av_read(dm_abstract_commands$EN_av_read),
|
|
.EN_write(dm_abstract_commands$EN_write),
|
|
.EN_hart0_gpr_mem_client_request_get(dm_abstract_commands$EN_hart0_gpr_mem_client_request_get),
|
|
.EN_hart0_gpr_mem_client_response_put(dm_abstract_commands$EN_hart0_gpr_mem_client_response_put),
|
|
.EN_hart0_fpr_mem_client_request_get(dm_abstract_commands$EN_hart0_fpr_mem_client_request_get),
|
|
.EN_hart0_fpr_mem_client_response_put(dm_abstract_commands$EN_hart0_fpr_mem_client_response_put),
|
|
.EN_hart0_csr_mem_client_request_get(dm_abstract_commands$EN_hart0_csr_mem_client_request_get),
|
|
.EN_hart0_csr_mem_client_response_put(dm_abstract_commands$EN_hart0_csr_mem_client_response_put),
|
|
.RDY_reset(),
|
|
.av_read(dm_abstract_commands$av_read),
|
|
.RDY_av_read(),
|
|
.RDY_write(),
|
|
.hart0_gpr_mem_client_request_get(dm_abstract_commands$hart0_gpr_mem_client_request_get),
|
|
.RDY_hart0_gpr_mem_client_request_get(dm_abstract_commands$RDY_hart0_gpr_mem_client_request_get),
|
|
.RDY_hart0_gpr_mem_client_response_put(dm_abstract_commands$RDY_hart0_gpr_mem_client_response_put),
|
|
.hart0_fpr_mem_client_request_get(dm_abstract_commands$hart0_fpr_mem_client_request_get),
|
|
.RDY_hart0_fpr_mem_client_request_get(dm_abstract_commands$RDY_hart0_fpr_mem_client_request_get),
|
|
.RDY_hart0_fpr_mem_client_response_put(dm_abstract_commands$RDY_hart0_fpr_mem_client_response_put),
|
|
.hart0_csr_mem_client_request_get(dm_abstract_commands$hart0_csr_mem_client_request_get),
|
|
.RDY_hart0_csr_mem_client_request_get(dm_abstract_commands$RDY_hart0_csr_mem_client_request_get),
|
|
.RDY_hart0_csr_mem_client_response_put(dm_abstract_commands$RDY_hart0_csr_mem_client_response_put));
|
|
|
|
// submodule dm_run_control
|
|
mkDM_Run_Control dm_run_control(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.av_read_dm_addr(dm_run_control$av_read_dm_addr),
|
|
.hart0_client_run_halt_response_put(dm_run_control$hart0_client_run_halt_response_put),
|
|
.hart0_reset_client_response_put(dm_run_control$hart0_reset_client_response_put),
|
|
.ndm_reset_client_response_put(dm_run_control$ndm_reset_client_response_put),
|
|
.write_dm_addr(dm_run_control$write_dm_addr),
|
|
.write_dm_word(dm_run_control$write_dm_word),
|
|
.EN_reset(dm_run_control$EN_reset),
|
|
.EN_av_read(dm_run_control$EN_av_read),
|
|
.EN_write(dm_run_control$EN_write),
|
|
.EN_hart0_reset_client_request_get(dm_run_control$EN_hart0_reset_client_request_get),
|
|
.EN_hart0_reset_client_response_put(dm_run_control$EN_hart0_reset_client_response_put),
|
|
.EN_hart0_client_run_halt_request_get(dm_run_control$EN_hart0_client_run_halt_request_get),
|
|
.EN_hart0_client_run_halt_response_put(dm_run_control$EN_hart0_client_run_halt_response_put),
|
|
.EN_hart0_get_other_req_get(dm_run_control$EN_hart0_get_other_req_get),
|
|
.EN_ndm_reset_client_request_get(dm_run_control$EN_ndm_reset_client_request_get),
|
|
.EN_ndm_reset_client_response_put(dm_run_control$EN_ndm_reset_client_response_put),
|
|
.dmactive(dm_run_control$dmactive),
|
|
.RDY_dmactive(),
|
|
.RDY_reset(),
|
|
.av_read(dm_run_control$av_read),
|
|
.RDY_av_read(),
|
|
.RDY_write(dm_run_control$RDY_write),
|
|
.hart0_reset_client_request_get(dm_run_control$hart0_reset_client_request_get),
|
|
.RDY_hart0_reset_client_request_get(dm_run_control$RDY_hart0_reset_client_request_get),
|
|
.RDY_hart0_reset_client_response_put(dm_run_control$RDY_hart0_reset_client_response_put),
|
|
.hart0_client_run_halt_request_get(dm_run_control$hart0_client_run_halt_request_get),
|
|
.RDY_hart0_client_run_halt_request_get(dm_run_control$RDY_hart0_client_run_halt_request_get),
|
|
.RDY_hart0_client_run_halt_response_put(dm_run_control$RDY_hart0_client_run_halt_response_put),
|
|
.hart0_get_other_req_get(dm_run_control$hart0_get_other_req_get),
|
|
.RDY_hart0_get_other_req_get(dm_run_control$RDY_hart0_get_other_req_get),
|
|
.ndm_reset_client_request_get(dm_run_control$ndm_reset_client_request_get),
|
|
.RDY_ndm_reset_client_request_get(dm_run_control$RDY_ndm_reset_client_request_get),
|
|
.RDY_ndm_reset_client_response_put(dm_run_control$RDY_ndm_reset_client_response_put));
|
|
|
|
// submodule dm_system_bus
|
|
mkDM_System_Bus dm_system_bus(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.av_read_dm_addr(dm_system_bus$av_read_dm_addr),
|
|
.master_arready(dm_system_bus$master_arready),
|
|
.master_awready(dm_system_bus$master_awready),
|
|
.master_bid(dm_system_bus$master_bid),
|
|
.master_bresp(dm_system_bus$master_bresp),
|
|
.master_bvalid(dm_system_bus$master_bvalid),
|
|
.master_rdata(dm_system_bus$master_rdata),
|
|
.master_rid(dm_system_bus$master_rid),
|
|
.master_rlast(dm_system_bus$master_rlast),
|
|
.master_rresp(dm_system_bus$master_rresp),
|
|
.master_ruser(dm_system_bus$master_ruser),
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|
.master_rvalid(dm_system_bus$master_rvalid),
|
|
.master_wready(dm_system_bus$master_wready),
|
|
.write_dm_addr(dm_system_bus$write_dm_addr),
|
|
.write_dm_word(dm_system_bus$write_dm_word),
|
|
.EN_reset(dm_system_bus$EN_reset),
|
|
.EN_av_read(dm_system_bus$EN_av_read),
|
|
.EN_write(dm_system_bus$EN_write),
|
|
.RDY_reset(dm_system_bus$RDY_reset),
|
|
.av_read(dm_system_bus$av_read),
|
|
.RDY_av_read(dm_system_bus$RDY_av_read),
|
|
.RDY_write(dm_system_bus$RDY_write),
|
|
.master_awid(dm_system_bus$master_awid),
|
|
.master_awaddr(dm_system_bus$master_awaddr),
|
|
.master_awlen(dm_system_bus$master_awlen),
|
|
.master_awsize(dm_system_bus$master_awsize),
|
|
.master_awburst(dm_system_bus$master_awburst),
|
|
.master_awlock(dm_system_bus$master_awlock),
|
|
.master_awcache(dm_system_bus$master_awcache),
|
|
.master_awprot(dm_system_bus$master_awprot),
|
|
.master_awqos(dm_system_bus$master_awqos),
|
|
.master_awregion(dm_system_bus$master_awregion),
|
|
.master_awvalid(dm_system_bus$master_awvalid),
|
|
.master_wdata(dm_system_bus$master_wdata),
|
|
.master_wstrb(dm_system_bus$master_wstrb),
|
|
.master_wlast(dm_system_bus$master_wlast),
|
|
.master_wuser(dm_system_bus$master_wuser),
|
|
.master_wvalid(dm_system_bus$master_wvalid),
|
|
.master_bready(dm_system_bus$master_bready),
|
|
.master_arid(dm_system_bus$master_arid),
|
|
.master_araddr(dm_system_bus$master_araddr),
|
|
.master_arlen(dm_system_bus$master_arlen),
|
|
.master_arsize(dm_system_bus$master_arsize),
|
|
.master_arburst(dm_system_bus$master_arburst),
|
|
.master_arlock(dm_system_bus$master_arlock),
|
|
.master_arcache(dm_system_bus$master_arcache),
|
|
.master_arprot(dm_system_bus$master_arprot),
|
|
.master_arqos(dm_system_bus$master_arqos),
|
|
.master_arregion(dm_system_bus$master_arregion),
|
|
.master_arvalid(dm_system_bus$master_arvalid),
|
|
.master_rready(dm_system_bus$master_rready));
|
|
|
|
// submodule f_read_addr
|
|
FIFO1 #(.width(32'd7), .guarded(32'd1)) f_read_addr(.RST(RST_N),
|
|
.CLK(CLK),
|
|
.D_IN(f_read_addr$D_IN),
|
|
.ENQ(f_read_addr$ENQ),
|
|
.DEQ(f_read_addr$DEQ),
|
|
.CLR(f_read_addr$CLR),
|
|
.D_OUT(f_read_addr$D_OUT),
|
|
.FULL_N(f_read_addr$FULL_N),
|
|
.EMPTY_N(f_read_addr$EMPTY_N));
|
|
|
|
// rule RL_rl_reset
|
|
assign CAN_FIRE_RL_rl_reset =
|
|
dm_system_bus$RDY_reset && !dm_run_control$dmactive ;
|
|
assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;
|
|
|
|
// submodule dm_abstract_commands
|
|
assign dm_abstract_commands$av_read_dm_addr = f_read_addr$D_OUT ;
|
|
assign dm_abstract_commands$hart0_csr_mem_client_response_put =
|
|
hart0_csr_mem_client_response_put ;
|
|
assign dm_abstract_commands$hart0_fpr_mem_client_response_put =
|
|
hart0_fpr_mem_client_response_put ;
|
|
assign dm_abstract_commands$hart0_gpr_mem_client_response_put =
|
|
hart0_gpr_mem_client_response_put ;
|
|
assign dm_abstract_commands$write_dm_addr = dmi_write_dm_addr ;
|
|
assign dm_abstract_commands$write_dm_word = dmi_write_dm_word ;
|
|
assign dm_abstract_commands$EN_reset = CAN_FIRE_RL_rl_reset ;
|
|
assign dm_abstract_commands$EN_av_read =
|
|
EN_dmi_read_data &&
|
|
(f_read_addr$D_OUT == 7'h16 || f_read_addr$D_OUT == 7'h17 ||
|
|
f_read_addr$D_OUT == 7'h04 ||
|
|
f_read_addr$D_OUT == 7'h05 ||
|
|
f_read_addr$D_OUT == 7'h06 ||
|
|
f_read_addr$D_OUT == 7'h07 ||
|
|
f_read_addr$D_OUT == 7'h08 ||
|
|
f_read_addr$D_OUT == 7'h09 ||
|
|
f_read_addr$D_OUT == 7'h0A ||
|
|
f_read_addr$D_OUT == 7'h0B ||
|
|
f_read_addr$D_OUT == 7'h0C ||
|
|
f_read_addr$D_OUT == 7'h0D ||
|
|
f_read_addr$D_OUT == 7'h0F ||
|
|
f_read_addr$D_OUT == 7'h18 ||
|
|
f_read_addr$D_OUT == 7'h20) ;
|
|
assign dm_abstract_commands$EN_write =
|
|
EN_dmi_write &&
|
|
(dmi_write_dm_addr == 7'h16 || dmi_write_dm_addr == 7'h17 ||
|
|
dmi_write_dm_addr == 7'h04 ||
|
|
dmi_write_dm_addr == 7'h05 ||
|
|
dmi_write_dm_addr == 7'h06 ||
|
|
dmi_write_dm_addr == 7'h07 ||
|
|
dmi_write_dm_addr == 7'h08 ||
|
|
dmi_write_dm_addr == 7'h09 ||
|
|
dmi_write_dm_addr == 7'h0A ||
|
|
dmi_write_dm_addr == 7'h0B ||
|
|
dmi_write_dm_addr == 7'h0C ||
|
|
dmi_write_dm_addr == 7'h0D ||
|
|
dmi_write_dm_addr == 7'h0F ||
|
|
dmi_write_dm_addr == 7'h18 ||
|
|
dmi_write_dm_addr == 7'h20) ;
|
|
assign dm_abstract_commands$EN_hart0_gpr_mem_client_request_get =
|
|
EN_hart0_gpr_mem_client_request_get ;
|
|
assign dm_abstract_commands$EN_hart0_gpr_mem_client_response_put =
|
|
EN_hart0_gpr_mem_client_response_put ;
|
|
assign dm_abstract_commands$EN_hart0_fpr_mem_client_request_get =
|
|
EN_hart0_fpr_mem_client_request_get ;
|
|
assign dm_abstract_commands$EN_hart0_fpr_mem_client_response_put =
|
|
EN_hart0_fpr_mem_client_response_put ;
|
|
assign dm_abstract_commands$EN_hart0_csr_mem_client_request_get =
|
|
EN_hart0_csr_mem_client_request_get ;
|
|
assign dm_abstract_commands$EN_hart0_csr_mem_client_response_put =
|
|
EN_hart0_csr_mem_client_response_put ;
|
|
|
|
// submodule dm_run_control
|
|
assign dm_run_control$av_read_dm_addr = f_read_addr$D_OUT ;
|
|
assign dm_run_control$hart0_client_run_halt_response_put =
|
|
hart0_client_run_halt_response_put ;
|
|
assign dm_run_control$hart0_reset_client_response_put =
|
|
hart0_reset_client_response_put ;
|
|
assign dm_run_control$ndm_reset_client_response_put =
|
|
ndm_reset_client_response_put ;
|
|
assign dm_run_control$write_dm_addr = dmi_write_dm_addr ;
|
|
assign dm_run_control$write_dm_word = dmi_write_dm_word ;
|
|
assign dm_run_control$EN_reset = CAN_FIRE_RL_rl_reset ;
|
|
assign dm_run_control$EN_av_read =
|
|
EN_dmi_read_data &&
|
|
(f_read_addr$D_OUT == 7'h10 || f_read_addr$D_OUT == 7'h11 ||
|
|
f_read_addr$D_OUT == 7'h12 ||
|
|
f_read_addr$D_OUT == 7'h13 ||
|
|
f_read_addr$D_OUT == 7'h14 ||
|
|
f_read_addr$D_OUT == 7'h15 ||
|
|
f_read_addr$D_OUT == 7'h19 ||
|
|
f_read_addr$D_OUT == 7'h30 ||
|
|
f_read_addr$D_OUT == 7'h40 ||
|
|
f_read_addr$D_OUT == 7'h5F ||
|
|
f_read_addr$D_OUT == 7'h60) ;
|
|
assign dm_run_control$EN_write =
|
|
EN_dmi_write &&
|
|
(dmi_write_dm_addr == 7'h10 || dmi_write_dm_addr == 7'h11 ||
|
|
dmi_write_dm_addr == 7'h12 ||
|
|
dmi_write_dm_addr == 7'h13 ||
|
|
dmi_write_dm_addr == 7'h14 ||
|
|
dmi_write_dm_addr == 7'h15 ||
|
|
dmi_write_dm_addr == 7'h19 ||
|
|
dmi_write_dm_addr == 7'h30 ||
|
|
dmi_write_dm_addr == 7'h40 ||
|
|
dmi_write_dm_addr == 7'h5F ||
|
|
dmi_write_dm_addr == 7'h60) ;
|
|
assign dm_run_control$EN_hart0_reset_client_request_get =
|
|
EN_hart0_reset_client_request_get ;
|
|
assign dm_run_control$EN_hart0_reset_client_response_put =
|
|
EN_hart0_reset_client_response_put ;
|
|
assign dm_run_control$EN_hart0_client_run_halt_request_get =
|
|
EN_hart0_client_run_halt_request_get ;
|
|
assign dm_run_control$EN_hart0_client_run_halt_response_put =
|
|
EN_hart0_client_run_halt_response_put ;
|
|
assign dm_run_control$EN_hart0_get_other_req_get =
|
|
EN_hart0_get_other_req_get ;
|
|
assign dm_run_control$EN_ndm_reset_client_request_get =
|
|
EN_ndm_reset_client_request_get ;
|
|
assign dm_run_control$EN_ndm_reset_client_response_put =
|
|
EN_ndm_reset_client_response_put ;
|
|
|
|
// submodule dm_system_bus
|
|
assign dm_system_bus$av_read_dm_addr = f_read_addr$D_OUT ;
|
|
assign dm_system_bus$master_arready = master_arready ;
|
|
assign dm_system_bus$master_awready = master_awready ;
|
|
assign dm_system_bus$master_bid = master_bid ;
|
|
assign dm_system_bus$master_bresp = master_bresp ;
|
|
assign dm_system_bus$master_bvalid = master_bvalid ;
|
|
assign dm_system_bus$master_rdata = master_rdata ;
|
|
assign dm_system_bus$master_rid = master_rid ;
|
|
assign dm_system_bus$master_rlast = master_rlast ;
|
|
assign dm_system_bus$master_rresp = master_rresp ;
|
|
assign dm_system_bus$master_ruser = master_ruser ;
|
|
assign dm_system_bus$master_rvalid = master_rvalid ;
|
|
assign dm_system_bus$master_wready = master_wready ;
|
|
assign dm_system_bus$write_dm_addr = dmi_write_dm_addr ;
|
|
assign dm_system_bus$write_dm_word = dmi_write_dm_word ;
|
|
assign dm_system_bus$EN_reset = CAN_FIRE_RL_rl_reset ;
|
|
assign dm_system_bus$EN_av_read =
|
|
EN_dmi_read_data &&
|
|
(f_read_addr$D_OUT == 7'h38 || f_read_addr$D_OUT == 7'h39 ||
|
|
f_read_addr$D_OUT == 7'h3A ||
|
|
f_read_addr$D_OUT == 7'h3B ||
|
|
f_read_addr$D_OUT == 7'h3C ||
|
|
f_read_addr$D_OUT == 7'h3D ||
|
|
f_read_addr$D_OUT == 7'h3E ||
|
|
f_read_addr$D_OUT == 7'h3F) ;
|
|
assign dm_system_bus$EN_write =
|
|
EN_dmi_write &&
|
|
(dmi_write_dm_addr == 7'h38 || dmi_write_dm_addr == 7'h39 ||
|
|
dmi_write_dm_addr == 7'h3A ||
|
|
dmi_write_dm_addr == 7'h3B ||
|
|
dmi_write_dm_addr == 7'h3C ||
|
|
dmi_write_dm_addr == 7'h3D ||
|
|
dmi_write_dm_addr == 7'h3E ||
|
|
dmi_write_dm_addr == 7'h3F) ;
|
|
|
|
// submodule f_read_addr
|
|
assign f_read_addr$D_IN = dmi_read_addr_dm_addr ;
|
|
assign f_read_addr$ENQ = EN_dmi_read_addr ;
|
|
assign f_read_addr$DEQ = EN_dmi_read_data ;
|
|
assign f_read_addr$CLR = 1'b0 ;
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_reset)
|
|
begin
|
|
v__h772 = $stime;
|
|
#0;
|
|
end
|
|
v__h766 = v__h772 / 32'd10;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h766);
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkDebug_Module
|
|
|