85 lines
2.7 KiB
Verilog
85 lines
2.7 KiB
Verilog
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// Copyright (c) 2000-2012 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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// A synchronization module for resets. Output resets are held for
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// RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous,
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// while deassertion is synchronized to the clock.
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module SyncResetA (
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IN_RST,
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CLK,
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OUT_RST
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);
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parameter RSTDELAY = 1 ; // Width of reset shift reg
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input CLK ;
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input IN_RST ;
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output OUT_RST ;
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reg [RSTDELAY:0] reset_hold ;
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wire [RSTDELAY+1:0] next_reset = {reset_hold, ~ `BSV_RESET_VALUE} ;
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assign OUT_RST = reset_hold[RSTDELAY] ;
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always @( posedge CLK or `BSV_RESET_EDGE IN_RST )
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begin
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if (IN_RST == `BSV_RESET_VALUE)
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begin
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reset_hold <= `BSV_ASSIGNMENT_DELAY {RSTDELAY+1 {`BSV_RESET_VALUE}} ;
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end
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else
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begin
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reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
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end
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end // always @ ( posedge CLK or `BSV_RESET_EDGE IN_RST )
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else // not BSV_NO_INITIAL_BLOCKS
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// synopsys translate_off
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initial
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begin
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#0 ;
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// initialize out of reset forcing the designer to do one
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reset_hold = {(RSTDELAY + 1) {~ `BSV_RESET_VALUE}} ;
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end
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// synopsys translate_on
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`endif // BSV_NO_INITIAL_BLOCKS
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endmodule // SyncResetA
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