6ebe612ff8
* Fixed the Decoding of (C)JAL * Use CSR addresses instead of offsets * Fixed offsets correctly * Fixed all offsets I could spot * Fix use of modifyOffset function * Corrected brAddrCalc function * Preliminary fix for ddc offsetting * Use setAddr instead of incOffset for DDC * Deleted unnecessarily added lines in ALU pipeline * Deleted white space * Switched off verbosity for ALU pipeline * Removed unnecessary print import
232 lines
7.1 KiB
Plaintext
Executable File
232 lines
7.1 KiB
Plaintext
Executable File
/*
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* Copyright (c) 2020 Peter Rugg
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* Copyright (c) 2020 Jonathan Woodruff
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* All rights reserved.
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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* This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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*
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* @BERI_LICENSE_HEADER_START@
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*
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* Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
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* license agreements. See the NOTICE file distributed with this work for
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* additional information regarding copyright ownership. BERI licenses this
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* file to you under the BERI Hardware-Software License, Version 1.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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*
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* http://www.beri-open-systems.org/legal/license-1-0.txt
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*
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* Unless required by applicable law or agreed to in writing, Work distributed
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* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* @BERI_LICENSE_HEADER_END@
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*/
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import ISA_Decls::*;
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import CHERICap::*;
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import CHERICC_Fat::*;
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typedef TMul#(XLEN, 2) CLEN;
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// Exception codes
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typedef struct { Bit#(5) code; } CHERIException deriving(Bits, Eq);
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`define CHERIException(n, v) CHERIException cheriExc``n = CHERIException { code: v };
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`include "CHERIExceptions.bsvi"
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`undef CHERIException
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instance FShow#(CHERIException);
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function Fmt fshow(CHERIException exc);
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return (case(exc.code)
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`define CHERIException(n, v) v: $format(`"``cheriExc``n```");
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`include "CHERIExceptions.bsvi"
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`undef CHERIException
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default: $format("cheriExcUnknown");
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endcase);
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endfunction
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endinstance
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typedef struct {
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Bit #(6) cheri_exc_reg;
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CHERIException cheri_exc_code;
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} CSR_XCapCause deriving(Bits, Eq, FShow);
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CSR_XCapCause noCapCause = CSR_XCapCause {cheri_exc_code: cheriExcNone,
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cheri_exc_reg: unpack(0)};
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// SCR map
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typedef struct { Bit#(5) addr; } SCR deriving(Bits, Eq);
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`define SCR(n, v) SCR scrAddr``n = SCR { addr: v };
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`include "SCRs.bsvi"
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// As with CSRs, SCR that catches all unimplemented SCRs
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`SCR(None, 5'd10)
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`undef SCR
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instance FShow#(SCR);
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function Fmt fshow(SCR scr);
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return (case(scr.addr)
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`define SCR(n, v) v: $format(`"``scrAddr``n```");
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`include "SCRs.bsvi"
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`undef SCR
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default: $format("scrAddrNone");
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endcase);
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endfunction
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endinstance
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function SCR unpackSCR(Bit#(5) addr);
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return (case(addr)
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`define SCR(n, v) v: scrAddr``n;
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`include "SCRs.bsvi"
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`undef SCR
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default: scrAddrNone;
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endcase);
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endfunction
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function CapPipe update_scr_via_csr (CapPipe old_scr, WordXL new_csr, Bool allow_sealed);
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let new_scr = setAddr(old_scr, new_csr);
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let ret = new_scr.value;
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if (!new_scr.exact || (getKind(old_scr) != UNSEALED && !allow_sealed)) begin
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ret = setValidCap(ret, False);
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end
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return ret;
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endfunction
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RegName cCallRD = 31;
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// Instruction field encodings
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// Top-level opcodes
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Opcode op_cap_Manip = 7'h5b;
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//Opcode op_cap_Mem = 7'h0b; // Not yet implemented
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// ================================================================
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// op_cap_Manip opcode subdivision
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// f3 selects between immediate and 3-reg instructions
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Bit #(3) f3_cap_ThreeOp = 3'h0;
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Bit #(3) f3_cap_CIncOffsetImmediate = 3'h1;
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Bit #(3) f3_cap_CSetBoundsImmediate = 3'h2;
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// 3'h3-3'h7 unused
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// ================================================================
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// op_cap_ThreeOp opcode subdivision
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// f7 selects between 3-reg operations
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// 7'h00 unused
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Bit #(7) f7_cap_CSpecialRW = 7'h01;
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// 7'h02-7'h07 unused
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Bit #(7) f7_cap_CSetBounds = 7'h08;
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Bit #(7) f7_cap_CSetBoundsExact = 7'h09;
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// 7'h0a unused
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Bit #(7) f7_cap_CSeal = 7'h0b;
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Bit #(7) f7_cap_CUnseal = 7'h0c;
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Bit #(7) f7_cap_CAndPerm = 7'h0d;
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Bit #(7) f7_cap_CSetFlags = 7'h0e;
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Bit #(7) f7_cap_CSetOffset = 7'h0f;
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Bit #(7) f7_cap_CSetAddr = 7'h10;
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Bit #(7) f7_cap_CIncOffset = 7'h11;
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Bit #(7) f7_cap_CToPtr = 7'h12;
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Bit #(7) f7_cap_CFromPtr = 7'h13;
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Bit #(7) f7_cap_CSub = 7'h14;
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// 7'h15 unused
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Bit #(7) f7_cap_CSetHigh = 7'h16;
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// 7'h17-7'h1c unused
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Bit #(7) f7_cap_CBuildCap = 7'h1d;
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Bit #(7) f7_cap_CCopyType = 7'h1e;
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Bit #(7) f7_cap_CCSeal = 7'h1f;
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Bit #(7) f7_cap_CTestSubset = 7'h20;
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Bit #(7) f7_cap_CSetEqualExact = 7'h21;
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// 7'h22-7'hfb unused
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Bit #(7) f7_cap_Stores = 7'h7c;
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Bit #(7) f7_cap_Loads = 7'h7d;
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Bit #(7) f7_cap_TwoSrc = 7'h7e;
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Bit #(7) f7_cap_TwoOp = 7'h7f;
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// ================================================================
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// f7_cap_TwoSrc opcode subdivision
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// rd selects between 2-reg operations
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// 5'h00 unused
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Bit #(5) rd_cap_CCall = 5'h01;
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// 5'h02-5'h1f unused
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// ================================================================
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// f7_cap_TwoOp opcode subdivision
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// f5rs2 selects between 2-reg operations (f5rs2 instead of f5 because f5
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// is already used in RISC-V and is in a different position
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Bit #(5) f5rs2_cap_CGetPerm = 5'h00;
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Bit #(5) f5rs2_cap_CGetType = 5'h01;
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Bit #(5) f5rs2_cap_CGetBase = 5'h02;
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Bit #(5) f5rs2_cap_CGetLen = 5'h03;
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Bit #(5) f5rs2_cap_CGetTag = 5'h04;
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Bit #(5) f5rs2_cap_CGetSealed = 5'h05;
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Bit #(5) f5rs2_cap_CGetOffset = 5'h06;
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Bit #(5) f5rs2_cap_CGetFlags = 5'h07;
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Bit #(5) f5rs2_cap_CRRL = 5'h08;
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Bit #(5) f5rs2_cap_CRAM = 5'h09;
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Bit #(5) f5rs2_cap_CMove = 5'h0a;
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Bit #(5) f5rs2_cap_CClearTag = 5'h0b;
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Bit #(5) f5rs2_cap_JALR_CAP = 5'h0c;
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Bit #(5) f5rs2_cap_CClearReg = 5'h0d;
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// 5'h0e unused
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Bit #(5) f5rs2_cap_CGetAddr = 5'h0f;
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Bit #(5) f5rs2_cap_CClearFPReg = 5'h10;
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Bit #(5) f5rs2_cap_CSealEntry = 5'h11;
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Bit #(5) f5rs2_cap_CLoadTags = 5'h12;
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// 5'h13 unused
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Bit #(5) f5rs2_cap_JALR_PCC = 5'h14;
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// 5'h15-5'h16 unused
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Bit #(5) f5rs2_cap_CGetHigh = 5'h17;
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// 5'h18-5'h1f unused (5'h1f reserved for 1-reg instructions)
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// ================================================================
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// f7_cap_{Load, Store} opcode subdivision
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MemReqSize cap_mem_SIZE_B = 'h0;
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MemReqSize cap_mem_SIZE_H = 'h1;
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MemReqSize cap_mem_SIZE_W = 'h2;
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MemReqSize cap_mem_SIZE_D = 'h3;
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//MemReqSize f5rs2_cap_mem_SIZE_Q = 'h4; //TODO
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Bit #(1) cap_mem_ddc = 1'h0;
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Bit #(1) cap_mem_cap = 1'h1;
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Bit #(1) cap_mem_unsigned = 1'h1;
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Bit #(1) cap_mem_signed = 1'h0;
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// ================================================================
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// Other:
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// Region in MISC_MEM for LQ
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Bit #(3) f3_LQ = 3'h2;
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Bit #(3) f3_SQ = 3'b100;
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`ifdef RV64
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Bit #(3) w_SIZE_CAP = f3_SQ;
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Bit #(3) w_SIZE_MAX = f3_SQ;
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`else //RV32
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Bit #(3) w_SIZE_CAP = f3_SD;
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Bit #(3) w_SIZE_MAX = f3_SD;
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`endif
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Bit #(3) f3_AMO_CAP = w_SIZE_CAP;
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// Special cases of Otypes that are extended to XLEN
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Bit #(XLEN) otype_unsealed_ext = -1;
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Bit #(XLEN) otype_sentry_ext = -2;
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Bit #(XLEN) otype_res0_ext = -3;
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Bit #(XLEN) otype_res1_ext = -4;
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