150 lines
3.6 KiB
Verilog
150 lines
3.6 KiB
Verilog
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// Copyright (c) 2000-2012 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_NO_MAIN_V
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`else
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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`ifdef BSV_RESET_NAME
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`else
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`define BSV_RESET_NAME RST_N
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`endif
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`ifdef BSV_TIMESCALE
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`timescale `BSV_TIMESCALE
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`endif
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module main();
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reg CLK;
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// reg CLK_GATE;
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reg RST;
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reg [31:0] cycle;
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reg do_vcd;
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reg do_fsdb;
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reg do_fst;
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reg do_cycles;
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`TOP top(.CLK(CLK), /* .CLK_GATE(CLK_GATE), */ .`BSV_RESET_NAME(RST));
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// For Sce-Mi linkage, insert code here
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`ifdef BSV_SCEMI_LINK
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`include `BSV_SCEMI_LINK
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`endif
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`ifdef BSV_DUMP_LEVEL
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`else
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`define BSV_DUMP_LEVEL 0
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`endif
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`ifdef BSV_DUMP_TOP
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`else
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`define BSV_DUMP_TOP main
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`endif
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reg [8*256:1] filename;
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initial begin
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// CLK_GATE = 1'b1;
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// CLK = 1'b0; // This line will cause a neg edge of clk at t=0!
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// RST = !`BSV_RESET_VALUE'b0; // This needs #0, to allow always blocks to wait
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cycle = 0;
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do_vcd = $test$plusargs("bscvcd") ;
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do_fst = $test$plusargs("bscfst") ;
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do_fsdb = $test$plusargs("bscfsdb") ;
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do_cycles = $test$plusargs("bsccycle") ;
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if ($value$plusargs("bscvcd=%s", filename))
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do_vcd = 1; // avoids bug in cvc
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else if (do_vcd)
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filename = "dump.vcd";
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if ($value$plusargs("bscfsdb=%s", filename))
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do_fsdb = 1; // avoids bug in cvc
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else if (do_fsdb)
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filename = "dump.fsdb";
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`ifdef BSC_FSDB
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if (do_fsdb) begin
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$fsdbDumpfile(filename);
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$fsdbDumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
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end
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`else
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// if (do_fst && ! do_vcd) begin
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// $dumpfile("|vcd2fst -F -f dump.fst -");
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// $dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
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// end
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if (do_vcd) begin
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$dumpfile(filename);
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$dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
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end
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`endif
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#0
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RST = `BSV_RESET_VALUE;
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#1;
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CLK = 1'b1;
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// $display("reset");
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#1;
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RST = !`BSV_RESET_VALUE;
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// $display("reset done");
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// #200010;
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// $finish;
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end
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`ifndef NO_CLOCK // for cosim
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always
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begin
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#1
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if (do_cycles)
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$display("cycle %0d", cycle) ;
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cycle = cycle + 1 ;
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#4;
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CLK = 1'b0 ;
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#5;
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CLK = 1'b1 ;
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end // always begin
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`endif // `ifndef NO_CLOCK
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endmodule
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`endif
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