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ac6043ce2d6e74feb3e76a5d7ac2b06365fd3fbd
Toooba/src_SSITH_P3/Verilog_RTL/mkCore.v
rsnikhil ac6043ce2d Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization 
(1) riscy-ooo was mapping all unimplemented CSRs to a benign, user-privilege read-write CSR
    Instead, we now catch this RenameStage and steer it to a trap.
(2) MSTATUS.FS was initialized to 2'b00 (absent/off); should be 2'b01 (present and initial)
2020-03-03 13:56:31 -05:00

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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_coreReq_start O 1 const
// RDY_coreReq_perfReq O 1 reg
// coreIndInv_perfResp O 73
// RDY_coreIndInv_perfResp O 1 reg
// RDY_coreIndInv_terminate O 1 reg
// dCacheToParent_rsToP_notEmpty O 1
// RDY_dCacheToParent_rsToP_notEmpty O 1 const
// RDY_dCacheToParent_rsToP_deq O 1
// dCacheToParent_rsToP_first O 579
// RDY_dCacheToParent_rsToP_first O 1
// dCacheToParent_rqToP_notEmpty O 1
// RDY_dCacheToParent_rqToP_notEmpty O 1 const
// RDY_dCacheToParent_rqToP_deq O 1
// dCacheToParent_rqToP_first O 72
// RDY_dCacheToParent_rqToP_first O 1
// dCacheToParent_fromP_notFull O 1
// RDY_dCacheToParent_fromP_notFull O 1 const
// RDY_dCacheToParent_fromP_enq O 1
// iCacheToParent_rsToP_notEmpty O 1
// RDY_iCacheToParent_rsToP_notEmpty O 1 const
// RDY_iCacheToParent_rsToP_deq O 1
// iCacheToParent_rsToP_first O 579
// RDY_iCacheToParent_rsToP_first O 1
// iCacheToParent_rqToP_notEmpty O 1
// RDY_iCacheToParent_rqToP_notEmpty O 1 const
// RDY_iCacheToParent_rqToP_deq O 1
// iCacheToParent_rqToP_first O 72
// RDY_iCacheToParent_rqToP_first O 1
// iCacheToParent_fromP_notFull O 1
// RDY_iCacheToParent_fromP_notFull O 1 const
// RDY_iCacheToParent_fromP_enq O 1
// tlbToMem_memReq_notEmpty O 1
// RDY_tlbToMem_memReq_notEmpty O 1 const
// RDY_tlbToMem_memReq_deq O 1
// tlbToMem_memReq_first O 65
// RDY_tlbToMem_memReq_first O 1
// tlbToMem_respLd_notFull O 1
// RDY_tlbToMem_respLd_notFull O 1 const
// RDY_tlbToMem_respLd_enq O 1
// mmioToPlatform_cRq_notEmpty O 1
// RDY_mmioToPlatform_cRq_notEmpty O 1 const
// RDY_mmioToPlatform_cRq_deq O 1
// mmioToPlatform_cRq_first O 142
// RDY_mmioToPlatform_cRq_first O 1
// mmioToPlatform_pRs_notFull O 1
// RDY_mmioToPlatform_pRs_notFull O 1 const
// RDY_mmioToPlatform_pRs_enq O 1
// mmioToPlatform_pRq_notFull O 1
// RDY_mmioToPlatform_pRq_notFull O 1 const
// RDY_mmioToPlatform_pRq_enq O 1
// mmioToPlatform_cRs_notEmpty O 1
// RDY_mmioToPlatform_cRs_notEmpty O 1 const
// RDY_mmioToPlatform_cRs_deq O 1
// mmioToPlatform_cRs_first O 1 reg
// RDY_mmioToPlatform_cRs_first O 1
// RDY_mmioToPlatform_setTime O 1 const
// sendDoStats O 1 reg
// RDY_sendDoStats O 1 reg
// RDY_recvDoStats O 1 const
// deadlock_dCacheCRqStuck_get O 73 const
// RDY_deadlock_dCacheCRqStuck_get O 1 const
// deadlock_dCachePRqStuck_get O 68 const
// RDY_deadlock_dCachePRqStuck_get O 1 const
// deadlock_iCacheCRqStuck_get O 68 const
// RDY_deadlock_iCacheCRqStuck_get O 1 const
// deadlock_iCachePRqStuck_get O 68 const
// RDY_deadlock_iCachePRqStuck_get O 1 const
// deadlock_renameInstStuck_get O 78 const
// RDY_deadlock_renameInstStuck_get O 1 const
// deadlock_renameCorrectPathStuck_get O 78 const
// RDY_deadlock_renameCorrectPathStuck_get O 1 const
// deadlock_commitInstStuck_get O 163 const
// RDY_deadlock_commitInstStuck_get O 1 const
// deadlock_commitUserInstStuck_get O 163 const
// RDY_deadlock_commitUserInstStuck_get O 1 const
// RDY_deadlock_checkStarted_get O 1 const
// renameDebug_renameErr_get O 89 const
// RDY_renameDebug_renameErr_get O 1 const
// RDY_setMEIP O 1 const
// RDY_setSEIP O 1 const
// RDY_hart0_run_halt_server_request_put O 1 reg
// hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_gpr_mem_server_request_put O 1 reg
// hart0_gpr_mem_server_response_get O 65 reg
// RDY_hart0_gpr_mem_server_response_get O 1 reg
// RDY_hart0_fpr_mem_server_request_put O 1 reg
// hart0_fpr_mem_server_response_get O 65 reg
// RDY_hart0_fpr_mem_server_response_get O 1 reg
// RDY_hart0_csr_mem_server_request_put O 1 reg
// hart0_csr_mem_server_response_get O 65 reg
// RDY_hart0_csr_mem_server_response_get O 1 reg
// v_to_TV_0_get O 785
// RDY_v_to_TV_0_get O 1 reg
// v_to_TV_1_get O 785
// RDY_v_to_TV_1_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// coreReq_start_startpc I 64
// coreReq_start_toHostAddr I 64 reg
// coreReq_start_fromHostAddr I 64 reg
// coreReq_perfReq_loc I 4 reg
// coreReq_perfReq_t I 5 reg
// dCacheToParent_fromP_enq_x I 583
// iCacheToParent_fromP_enq_x I 583
// tlbToMem_respLd_enq_x I 65
// mmioToPlatform_pRs_enq_x I 67
// mmioToPlatform_pRq_enq_x I 39
// mmioToPlatform_setTime_t I 64 reg
// recvDoStats_x I 1 reg
// setMEIP_v I 1
// setSEIP_v I 1
// hart0_run_halt_server_request_put I 1 reg
// hart0_gpr_mem_server_request_put I 70 reg
// hart0_fpr_mem_server_request_put I 70 reg
// hart0_csr_mem_server_request_put I 77 reg
// EN_coreReq_start I 1
// EN_coreReq_perfReq I 1
// EN_coreIndInv_terminate I 1
// EN_dCacheToParent_rsToP_deq I 1
// EN_dCacheToParent_rqToP_deq I 1
// EN_dCacheToParent_fromP_enq I 1
// EN_iCacheToParent_rsToP_deq I 1
// EN_iCacheToParent_rqToP_deq I 1
// EN_iCacheToParent_fromP_enq I 1
// EN_tlbToMem_memReq_deq I 1
// EN_tlbToMem_respLd_enq I 1
// EN_mmioToPlatform_cRq_deq I 1
// EN_mmioToPlatform_pRs_enq I 1
// EN_mmioToPlatform_pRq_enq I 1
// EN_mmioToPlatform_cRs_deq I 1
// EN_mmioToPlatform_setTime I 1
// EN_recvDoStats I 1
// EN_deadlock_checkStarted_get I 1 unused
// EN_setMEIP I 1
// EN_setSEIP I 1
// EN_hart0_run_halt_server_request_put I 1
// EN_hart0_gpr_mem_server_request_put I 1
// EN_hart0_fpr_mem_server_request_put I 1
// EN_hart0_csr_mem_server_request_put I 1
// EN_coreIndInv_perfResp I 1
// EN_sendDoStats I 1
// EN_deadlock_dCacheCRqStuck_get I 1 unused
// EN_deadlock_dCachePRqStuck_get I 1 unused
// EN_deadlock_iCacheCRqStuck_get I 1 unused
// EN_deadlock_iCachePRqStuck_get I 1 unused
// EN_deadlock_renameInstStuck_get I 1 unused
// EN_deadlock_renameCorrectPathStuck_get I 1 unused
// EN_deadlock_commitInstStuck_get I 1 unused
// EN_deadlock_commitUserInstStuck_get I 1 unused
// EN_renameDebug_renameErr_get I 1 unused
// EN_hart0_run_halt_server_response_get I 1
// EN_hart0_gpr_mem_server_response_get I 1
// EN_hart0_fpr_mem_server_response_get I 1
// EN_hart0_csr_mem_server_response_get I 1
// EN_v_to_TV_0_get I 1
// EN_v_to_TV_1_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCore(CLK,
RST_N,
coreReq_start_startpc,
coreReq_start_toHostAddr,
coreReq_start_fromHostAddr,
EN_coreReq_start,
RDY_coreReq_start,
coreReq_perfReq_loc,
coreReq_perfReq_t,
EN_coreReq_perfReq,
RDY_coreReq_perfReq,
EN_coreIndInv_perfResp,
coreIndInv_perfResp,
RDY_coreIndInv_perfResp,
EN_coreIndInv_terminate,
RDY_coreIndInv_terminate,
dCacheToParent_rsToP_notEmpty,
RDY_dCacheToParent_rsToP_notEmpty,
EN_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_deq,
dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_first,
dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rqToP_notEmpty,
EN_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_deq,
dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_first,
dCacheToParent_fromP_notFull,
RDY_dCacheToParent_fromP_notFull,
dCacheToParent_fromP_enq_x,
EN_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_enq,
iCacheToParent_rsToP_notEmpty,
RDY_iCacheToParent_rsToP_notEmpty,
EN_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_deq,
iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_first,
iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rqToP_notEmpty,
EN_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_deq,
iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_first,
iCacheToParent_fromP_notFull,
RDY_iCacheToParent_fromP_notFull,
iCacheToParent_fromP_enq_x,
EN_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_enq,
tlbToMem_memReq_notEmpty,
RDY_tlbToMem_memReq_notEmpty,
EN_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_deq,
tlbToMem_memReq_first,
RDY_tlbToMem_memReq_first,
tlbToMem_respLd_notFull,
RDY_tlbToMem_respLd_notFull,
tlbToMem_respLd_enq_x,
EN_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_enq,
mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRq_notEmpty,
EN_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_deq,
mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_first,
mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_pRs_notFull,
mmioToPlatform_pRs_enq_x,
EN_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_enq,
mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRq_notFull,
mmioToPlatform_pRq_enq_x,
EN_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_enq,
mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_cRs_notEmpty,
EN_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_deq,
mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_first,
mmioToPlatform_setTime_t,
EN_mmioToPlatform_setTime,
RDY_mmioToPlatform_setTime,
EN_sendDoStats,
sendDoStats,
RDY_sendDoStats,
recvDoStats_x,
EN_recvDoStats,
RDY_recvDoStats,
EN_deadlock_dCacheCRqStuck_get,
deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
EN_deadlock_dCachePRqStuck_get,
deadlock_dCachePRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
EN_deadlock_iCacheCRqStuck_get,
deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
EN_deadlock_iCachePRqStuck_get,
deadlock_iCachePRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
EN_deadlock_renameInstStuck_get,
deadlock_renameInstStuck_get,
RDY_deadlock_renameInstStuck_get,
EN_deadlock_renameCorrectPathStuck_get,
deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
EN_deadlock_commitInstStuck_get,
deadlock_commitInstStuck_get,
RDY_deadlock_commitInstStuck_get,
EN_deadlock_commitUserInstStuck_get,
deadlock_commitUserInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
EN_deadlock_checkStarted_get,
RDY_deadlock_checkStarted_get,
EN_renameDebug_renameErr_get,
renameDebug_renameErr_get,
RDY_renameDebug_renameErr_get,
setMEIP_v,
EN_setMEIP,
RDY_setMEIP,
setSEIP_v,
EN_setSEIP,
RDY_setSEIP,
hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_response_get,
hart0_run_halt_server_response_get,
RDY_hart0_run_halt_server_response_get,
hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_response_get,
hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
RDY_hart0_fpr_mem_server_response_get,
hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_response_get,
hart0_csr_mem_server_response_get,
RDY_hart0_csr_mem_server_response_get,
EN_v_to_TV_0_get,
v_to_TV_0_get,
RDY_v_to_TV_0_get,
EN_v_to_TV_1_get,
v_to_TV_1_get,
RDY_v_to_TV_1_get);
input CLK;
input RST_N;
// action method coreReq_start
input [63 : 0] coreReq_start_startpc;
input [63 : 0] coreReq_start_toHostAddr;
input [63 : 0] coreReq_start_fromHostAddr;
input EN_coreReq_start;
output RDY_coreReq_start;
// action method coreReq_perfReq
input [3 : 0] coreReq_perfReq_loc;
input [4 : 0] coreReq_perfReq_t;
input EN_coreReq_perfReq;
output RDY_coreReq_perfReq;
// actionvalue method coreIndInv_perfResp
input EN_coreIndInv_perfResp;
output [72 : 0] coreIndInv_perfResp;
output RDY_coreIndInv_perfResp;
// action method coreIndInv_terminate
input EN_coreIndInv_terminate;
output RDY_coreIndInv_terminate;
// value method dCacheToParent_rsToP_notEmpty
output dCacheToParent_rsToP_notEmpty;
output RDY_dCacheToParent_rsToP_notEmpty;
// action method dCacheToParent_rsToP_deq
input EN_dCacheToParent_rsToP_deq;
output RDY_dCacheToParent_rsToP_deq;
// value method dCacheToParent_rsToP_first
output [578 : 0] dCacheToParent_rsToP_first;
output RDY_dCacheToParent_rsToP_first;
// value method dCacheToParent_rqToP_notEmpty
output dCacheToParent_rqToP_notEmpty;
output RDY_dCacheToParent_rqToP_notEmpty;
// action method dCacheToParent_rqToP_deq
input EN_dCacheToParent_rqToP_deq;
output RDY_dCacheToParent_rqToP_deq;
// value method dCacheToParent_rqToP_first
output [71 : 0] dCacheToParent_rqToP_first;
output RDY_dCacheToParent_rqToP_first;
// value method dCacheToParent_fromP_notFull
output dCacheToParent_fromP_notFull;
output RDY_dCacheToParent_fromP_notFull;
// action method dCacheToParent_fromP_enq
input [582 : 0] dCacheToParent_fromP_enq_x;
input EN_dCacheToParent_fromP_enq;
output RDY_dCacheToParent_fromP_enq;
// value method iCacheToParent_rsToP_notEmpty
output iCacheToParent_rsToP_notEmpty;
output RDY_iCacheToParent_rsToP_notEmpty;
// action method iCacheToParent_rsToP_deq
input EN_iCacheToParent_rsToP_deq;
output RDY_iCacheToParent_rsToP_deq;
// value method iCacheToParent_rsToP_first
output [578 : 0] iCacheToParent_rsToP_first;
output RDY_iCacheToParent_rsToP_first;
// value method iCacheToParent_rqToP_notEmpty
output iCacheToParent_rqToP_notEmpty;
output RDY_iCacheToParent_rqToP_notEmpty;
// action method iCacheToParent_rqToP_deq
input EN_iCacheToParent_rqToP_deq;
output RDY_iCacheToParent_rqToP_deq;
// value method iCacheToParent_rqToP_first
output [71 : 0] iCacheToParent_rqToP_first;
output RDY_iCacheToParent_rqToP_first;
// value method iCacheToParent_fromP_notFull
output iCacheToParent_fromP_notFull;
output RDY_iCacheToParent_fromP_notFull;
// action method iCacheToParent_fromP_enq
input [582 : 0] iCacheToParent_fromP_enq_x;
input EN_iCacheToParent_fromP_enq;
output RDY_iCacheToParent_fromP_enq;
// value method tlbToMem_memReq_notEmpty
output tlbToMem_memReq_notEmpty;
output RDY_tlbToMem_memReq_notEmpty;
// action method tlbToMem_memReq_deq
input EN_tlbToMem_memReq_deq;
output RDY_tlbToMem_memReq_deq;
// value method tlbToMem_memReq_first
output [64 : 0] tlbToMem_memReq_first;
output RDY_tlbToMem_memReq_first;
// value method tlbToMem_respLd_notFull
output tlbToMem_respLd_notFull;
output RDY_tlbToMem_respLd_notFull;
// action method tlbToMem_respLd_enq
input [64 : 0] tlbToMem_respLd_enq_x;
input EN_tlbToMem_respLd_enq;
output RDY_tlbToMem_respLd_enq;
// value method mmioToPlatform_cRq_notEmpty
output mmioToPlatform_cRq_notEmpty;
output RDY_mmioToPlatform_cRq_notEmpty;
// action method mmioToPlatform_cRq_deq
input EN_mmioToPlatform_cRq_deq;
output RDY_mmioToPlatform_cRq_deq;
// value method mmioToPlatform_cRq_first
output [141 : 0] mmioToPlatform_cRq_first;
output RDY_mmioToPlatform_cRq_first;
// value method mmioToPlatform_pRs_notFull
output mmioToPlatform_pRs_notFull;
output RDY_mmioToPlatform_pRs_notFull;
// action method mmioToPlatform_pRs_enq
input [66 : 0] mmioToPlatform_pRs_enq_x;
input EN_mmioToPlatform_pRs_enq;
output RDY_mmioToPlatform_pRs_enq;
// value method mmioToPlatform_pRq_notFull
output mmioToPlatform_pRq_notFull;
output RDY_mmioToPlatform_pRq_notFull;
// action method mmioToPlatform_pRq_enq
input [38 : 0] mmioToPlatform_pRq_enq_x;
input EN_mmioToPlatform_pRq_enq;
output RDY_mmioToPlatform_pRq_enq;
// value method mmioToPlatform_cRs_notEmpty
output mmioToPlatform_cRs_notEmpty;
output RDY_mmioToPlatform_cRs_notEmpty;
// action method mmioToPlatform_cRs_deq
input EN_mmioToPlatform_cRs_deq;
output RDY_mmioToPlatform_cRs_deq;
// value method mmioToPlatform_cRs_first
output mmioToPlatform_cRs_first;
output RDY_mmioToPlatform_cRs_first;
// action method mmioToPlatform_setTime
input [63 : 0] mmioToPlatform_setTime_t;
input EN_mmioToPlatform_setTime;
output RDY_mmioToPlatform_setTime;
// actionvalue method sendDoStats
input EN_sendDoStats;
output sendDoStats;
output RDY_sendDoStats;
// action method recvDoStats
input recvDoStats_x;
input EN_recvDoStats;
output RDY_recvDoStats;
// actionvalue method deadlock_dCacheCRqStuck_get
input EN_deadlock_dCacheCRqStuck_get;
output [72 : 0] deadlock_dCacheCRqStuck_get;
output RDY_deadlock_dCacheCRqStuck_get;
// actionvalue method deadlock_dCachePRqStuck_get
input EN_deadlock_dCachePRqStuck_get;
output [67 : 0] deadlock_dCachePRqStuck_get;
output RDY_deadlock_dCachePRqStuck_get;
// actionvalue method deadlock_iCacheCRqStuck_get
input EN_deadlock_iCacheCRqStuck_get;
output [67 : 0] deadlock_iCacheCRqStuck_get;
output RDY_deadlock_iCacheCRqStuck_get;
// actionvalue method deadlock_iCachePRqStuck_get
input EN_deadlock_iCachePRqStuck_get;
output [67 : 0] deadlock_iCachePRqStuck_get;
output RDY_deadlock_iCachePRqStuck_get;
// actionvalue method deadlock_renameInstStuck_get
input EN_deadlock_renameInstStuck_get;
output [77 : 0] deadlock_renameInstStuck_get;
output RDY_deadlock_renameInstStuck_get;
// actionvalue method deadlock_renameCorrectPathStuck_get
input EN_deadlock_renameCorrectPathStuck_get;
output [77 : 0] deadlock_renameCorrectPathStuck_get;
output RDY_deadlock_renameCorrectPathStuck_get;
// actionvalue method deadlock_commitInstStuck_get
input EN_deadlock_commitInstStuck_get;
output [162 : 0] deadlock_commitInstStuck_get;
output RDY_deadlock_commitInstStuck_get;
// actionvalue method deadlock_commitUserInstStuck_get
input EN_deadlock_commitUserInstStuck_get;
output [162 : 0] deadlock_commitUserInstStuck_get;
output RDY_deadlock_commitUserInstStuck_get;
// action method deadlock_checkStarted_get
input EN_deadlock_checkStarted_get;
output RDY_deadlock_checkStarted_get;
// actionvalue method renameDebug_renameErr_get
input EN_renameDebug_renameErr_get;
output [88 : 0] renameDebug_renameErr_get;
output RDY_renameDebug_renameErr_get;
// action method setMEIP
input setMEIP_v;
input EN_setMEIP;
output RDY_setMEIP;
// action method setSEIP
input setSEIP_v;
input EN_setSEIP;
output RDY_setSEIP;
// action method hart0_run_halt_server_request_put
input hart0_run_halt_server_request_put;
input EN_hart0_run_halt_server_request_put;
output RDY_hart0_run_halt_server_request_put;
// actionvalue method hart0_run_halt_server_response_get
input EN_hart0_run_halt_server_response_get;
output hart0_run_halt_server_response_get;
output RDY_hart0_run_halt_server_response_get;
// action method hart0_gpr_mem_server_request_put
input [69 : 0] hart0_gpr_mem_server_request_put;
input EN_hart0_gpr_mem_server_request_put;
output RDY_hart0_gpr_mem_server_request_put;
// actionvalue method hart0_gpr_mem_server_response_get
input EN_hart0_gpr_mem_server_response_get;
output [64 : 0] hart0_gpr_mem_server_response_get;
output RDY_hart0_gpr_mem_server_response_get;
// action method hart0_fpr_mem_server_request_put
input [69 : 0] hart0_fpr_mem_server_request_put;
input EN_hart0_fpr_mem_server_request_put;
output RDY_hart0_fpr_mem_server_request_put;
// actionvalue method hart0_fpr_mem_server_response_get
input EN_hart0_fpr_mem_server_response_get;
output [64 : 0] hart0_fpr_mem_server_response_get;
output RDY_hart0_fpr_mem_server_response_get;
// action method hart0_csr_mem_server_request_put
input [76 : 0] hart0_csr_mem_server_request_put;
input EN_hart0_csr_mem_server_request_put;
output RDY_hart0_csr_mem_server_request_put;
// actionvalue method hart0_csr_mem_server_response_get
input EN_hart0_csr_mem_server_response_get;
output [64 : 0] hart0_csr_mem_server_response_get;
output RDY_hart0_csr_mem_server_response_get;
// actionvalue method v_to_TV_0_get
input EN_v_to_TV_0_get;
output [784 : 0] v_to_TV_0_get;
output RDY_v_to_TV_0_get;
// actionvalue method v_to_TV_1_get
input EN_v_to_TV_1_get;
output [784 : 0] v_to_TV_1_get;
output RDY_v_to_TV_1_get;
// signals for module outputs
wire [784 : 0] v_to_TV_0_get, v_to_TV_1_get;
wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first;
wire [162 : 0] deadlock_commitInstStuck_get,
deadlock_commitUserInstStuck_get;
wire [141 : 0] mmioToPlatform_cRq_first;
wire [88 : 0] renameDebug_renameErr_get;
wire [77 : 0] deadlock_renameCorrectPathStuck_get,
deadlock_renameInstStuck_get;
wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get;
wire [71 : 0] dCacheToParent_rqToP_first, iCacheToParent_rqToP_first;
wire [67 : 0] deadlock_dCachePRqStuck_get,
deadlock_iCacheCRqStuck_get,
deadlock_iCachePRqStuck_get;
wire [64 : 0] hart0_csr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
tlbToMem_memReq_first;
wire RDY_coreIndInv_perfResp,
RDY_coreIndInv_terminate,
RDY_coreReq_perfReq,
RDY_coreReq_start,
RDY_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_notFull,
RDY_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_notEmpty,
RDY_deadlock_checkStarted_get,
RDY_deadlock_commitInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameInstStuck_get,
RDY_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_response_get,
RDY_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_response_get,
RDY_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_response_get,
RDY_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_notFull,
RDY_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_notEmpty,
RDY_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_setTime,
RDY_recvDoStats,
RDY_renameDebug_renameErr_get,
RDY_sendDoStats,
RDY_setMEIP,
RDY_setSEIP,
RDY_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_first,
RDY_tlbToMem_memReq_notEmpty,
RDY_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_notFull,
RDY_v_to_TV_0_get,
RDY_v_to_TV_1_get,
dCacheToParent_fromP_notFull,
dCacheToParent_rqToP_notEmpty,
dCacheToParent_rsToP_notEmpty,
hart0_run_halt_server_response_get,
iCacheToParent_fromP_notFull,
iCacheToParent_rqToP_notEmpty,
iCacheToParent_rsToP_notEmpty,
mmioToPlatform_cRq_notEmpty,
mmioToPlatform_cRs_first,
mmioToPlatform_cRs_notEmpty,
mmioToPlatform_pRq_notFull,
mmioToPlatform_pRs_notFull,
sendDoStats,
tlbToMem_memReq_notEmpty,
tlbToMem_respLd_notFull;
// inlined wires
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget;
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget;
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget;
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget;
wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget;
wire [76 : 0] coreFix_memExe_issueLd$wget;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget;
wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget,
coreFix_aluExe_0_bypassWire_1$wget,
coreFix_aluExe_0_bypassWire_2$wget,
coreFix_aluExe_0_bypassWire_3$wget;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget,
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget;
wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget,
mmio_dataRespQ_enqReq_lat_0$wget;
wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget;
wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget;
wire coreFix_aluExe_0_bypassWire_0$whas,
coreFix_aluExe_0_bypassWire_1$whas,
coreFix_aluExe_0_bypassWire_2$whas,
coreFix_aluExe_0_bypassWire_3$whas,
coreFix_aluExe_1_bypassWire_2$whas,
coreFix_aluExe_1_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_bypassWire_2$whas,
coreFix_fpuMulDivExe_0_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_globalSpecUpdate_correctSpecTag_0$whas,
coreFix_globalSpecUpdate_correctSpecTag_1$whas,
coreFix_memExe_bypassWire_2$whas,
coreFix_memExe_bypassWire_3$whas,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas,
coreFix_memExe_forwardQ_enqReq_lat_0$whas,
coreFix_memExe_issueLd$whas,
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas,
coreFix_memExe_reqLdQ_data_0_lat_0$whas,
coreFix_memExe_reqLdQ_empty_lat_0$whas,
coreFix_memExe_reqLdQ_full_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas,
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas,
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas,
csrInstOrInterruptInflight_lat_1$whas,
csrf_mcycle_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_dummy_1_0$whas,
csrf_minstret_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_lat_1$whas,
mmio_cRqQ_enqReq_lat_0$whas,
mmio_dataPendQ_enqReq_lat_0$whas,
mmio_dataReqQ_enqReq_lat_0$whas,
mmio_dataRespQ_deqReq_lat_0$whas,
mmio_pRsQ_deqReq_lat_0$whas;
// register commitStage_commitTrap
reg [165 : 0] commitStage_commitTrap;
wire [165 : 0] commitStage_commitTrap$D_IN;
wire commitStage_commitTrap$EN;
// register commitStage_rg_just_after_reset
reg commitStage_rg_just_after_reset;
wire commitStage_rg_just_after_reset$D_IN,
commitStage_rg_just_after_reset$EN;
// register commitStage_rg_run_state
reg commitStage_rg_run_state;
wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN;
// register commitStage_rg_serial_num
reg [63 : 0] commitStage_rg_serial_num;
reg [63 : 0] commitStage_rg_serial_num$D_IN;
wire commitStage_rg_serial_num$EN;
// register coreFix_doStatsReg
reg coreFix_doStatsReg;
wire coreFix_doStatsReg$D_IN, coreFix_doStatsReg$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt;
wire [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit;
wire [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl;
wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo;
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
reg [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
reg coreFix_memExe_dMem_perfReqQ_clearReq_rl;
wire coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_data_0
reg [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0;
wire [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
wire coreFix_memExe_dMem_perfReqQ_data_0$EN;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
reg coreFix_memExe_dMem_perfReqQ_deqReq_rl;
wire coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_empty
reg coreFix_memExe_dMem_perfReqQ_empty;
wire coreFix_memExe_dMem_perfReqQ_empty$D_IN,
coreFix_memExe_dMem_perfReqQ_empty$EN;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
reg [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl;
wire [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_full
reg coreFix_memExe_dMem_perfReqQ_full;
wire coreFix_memExe_dMem_perfReqQ_full$D_IN,
coreFix_memExe_dMem_perfReqQ_full$EN;
// register coreFix_memExe_forwardQ_clearReq_rl
reg coreFix_memExe_forwardQ_clearReq_rl;
wire coreFix_memExe_forwardQ_clearReq_rl$D_IN,
coreFix_memExe_forwardQ_clearReq_rl$EN;
// register coreFix_memExe_forwardQ_data_0
reg [68 : 0] coreFix_memExe_forwardQ_data_0;
wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN;
wire coreFix_memExe_forwardQ_data_0$EN;
// register coreFix_memExe_forwardQ_data_1
reg [68 : 0] coreFix_memExe_forwardQ_data_1;
wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN;
wire coreFix_memExe_forwardQ_data_1$EN;
// register coreFix_memExe_forwardQ_deqP
reg coreFix_memExe_forwardQ_deqP;
wire coreFix_memExe_forwardQ_deqP$D_IN, coreFix_memExe_forwardQ_deqP$EN;
// register coreFix_memExe_forwardQ_deqReq_rl
reg coreFix_memExe_forwardQ_deqReq_rl;
wire coreFix_memExe_forwardQ_deqReq_rl$D_IN,
coreFix_memExe_forwardQ_deqReq_rl$EN;
// register coreFix_memExe_forwardQ_empty
reg coreFix_memExe_forwardQ_empty;
wire coreFix_memExe_forwardQ_empty$D_IN, coreFix_memExe_forwardQ_empty$EN;
// register coreFix_memExe_forwardQ_enqP
reg coreFix_memExe_forwardQ_enqP;
wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN;
// register coreFix_memExe_forwardQ_enqReq_rl
reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN;
wire coreFix_memExe_forwardQ_enqReq_rl$EN;
// register coreFix_memExe_forwardQ_full
reg coreFix_memExe_forwardQ_full;
wire coreFix_memExe_forwardQ_full$D_IN, coreFix_memExe_forwardQ_full$EN;
// register coreFix_memExe_memRespLdQ_clearReq_rl
reg coreFix_memExe_memRespLdQ_clearReq_rl;
wire coreFix_memExe_memRespLdQ_clearReq_rl$D_IN,
coreFix_memExe_memRespLdQ_clearReq_rl$EN;
// register coreFix_memExe_memRespLdQ_data_0
reg [68 : 0] coreFix_memExe_memRespLdQ_data_0;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN;
wire coreFix_memExe_memRespLdQ_data_0$EN;
// register coreFix_memExe_memRespLdQ_data_1
reg [68 : 0] coreFix_memExe_memRespLdQ_data_1;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN;
wire coreFix_memExe_memRespLdQ_data_1$EN;
// register coreFix_memExe_memRespLdQ_deqP
reg coreFix_memExe_memRespLdQ_deqP;
wire coreFix_memExe_memRespLdQ_deqP$D_IN, coreFix_memExe_memRespLdQ_deqP$EN;
// register coreFix_memExe_memRespLdQ_deqReq_rl
reg coreFix_memExe_memRespLdQ_deqReq_rl;
wire coreFix_memExe_memRespLdQ_deqReq_rl$D_IN,
coreFix_memExe_memRespLdQ_deqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_empty
reg coreFix_memExe_memRespLdQ_empty;
wire coreFix_memExe_memRespLdQ_empty$D_IN,
coreFix_memExe_memRespLdQ_empty$EN;
// register coreFix_memExe_memRespLdQ_enqP
reg coreFix_memExe_memRespLdQ_enqP;
wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN;
// register coreFix_memExe_memRespLdQ_enqReq_rl
reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
wire coreFix_memExe_memRespLdQ_enqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_full
reg coreFix_memExe_memRespLdQ_full;
wire coreFix_memExe_memRespLdQ_full$D_IN, coreFix_memExe_memRespLdQ_full$EN;
// register coreFix_memExe_reqLdQ_data_0_rl
reg [68 : 0] coreFix_memExe_reqLdQ_data_0_rl;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLdQ_data_0_rl$EN;
// register coreFix_memExe_reqLdQ_empty_rl
reg coreFix_memExe_reqLdQ_empty_rl;
wire coreFix_memExe_reqLdQ_empty_rl$D_IN, coreFix_memExe_reqLdQ_empty_rl$EN;
// register coreFix_memExe_reqLdQ_full_rl
reg coreFix_memExe_reqLdQ_full_rl;
wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
reg coreFix_memExe_reqLrScAmoQ_empty_rl;
wire coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_full_rl
reg coreFix_memExe_reqLrScAmoQ_full_rl;
wire coreFix_memExe_reqLrScAmoQ_full_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_full_rl$EN;
// register coreFix_memExe_reqStQ_data_0_rl
reg [65 : 0] coreFix_memExe_reqStQ_data_0_rl;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_rl$D_IN;
wire coreFix_memExe_reqStQ_data_0_rl$EN;
// register coreFix_memExe_reqStQ_empty_rl
reg coreFix_memExe_reqStQ_empty_rl;
wire coreFix_memExe_reqStQ_empty_rl$D_IN, coreFix_memExe_reqStQ_empty_rl$EN;
// register coreFix_memExe_reqStQ_full_rl
reg coreFix_memExe_reqStQ_full_rl;
wire coreFix_memExe_reqStQ_full_rl$D_IN, coreFix_memExe_reqStQ_full_rl$EN;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
reg coreFix_memExe_respLrScAmoQ_clearReq_rl;
wire coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_data_0
reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0;
wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN;
wire coreFix_memExe_respLrScAmoQ_data_0$EN;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
reg coreFix_memExe_respLrScAmoQ_deqReq_rl;
wire coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_empty
reg coreFix_memExe_respLrScAmoQ_empty;
wire coreFix_memExe_respLrScAmoQ_empty$D_IN,
coreFix_memExe_respLrScAmoQ_empty$EN;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl;
wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_full
reg coreFix_memExe_respLrScAmoQ_full;
wire coreFix_memExe_respLrScAmoQ_full$D_IN,
coreFix_memExe_respLrScAmoQ_full$EN;
// register coreFix_memExe_waitLrScAmoMMIOResp
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp;
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
wire coreFix_memExe_waitLrScAmoMMIOResp$EN;
// register csrInstOrInterruptInflight_rl
reg csrInstOrInterruptInflight_rl;
wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN;
// register csrf_external_int_en_vec_0
reg csrf_external_int_en_vec_0;
wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN;
// register csrf_external_int_en_vec_1
reg csrf_external_int_en_vec_1;
wire csrf_external_int_en_vec_1$D_IN, csrf_external_int_en_vec_1$EN;
// register csrf_external_int_en_vec_3
reg csrf_external_int_en_vec_3;
wire csrf_external_int_en_vec_3$D_IN, csrf_external_int_en_vec_3$EN;
// register csrf_external_int_pend_vec_0
reg csrf_external_int_pend_vec_0;
wire csrf_external_int_pend_vec_0$D_IN, csrf_external_int_pend_vec_0$EN;
// register csrf_external_int_pend_vec_1
reg csrf_external_int_pend_vec_1;
reg csrf_external_int_pend_vec_1$D_IN;
wire csrf_external_int_pend_vec_1$EN;
// register csrf_external_int_pend_vec_3
reg csrf_external_int_pend_vec_3;
reg csrf_external_int_pend_vec_3$D_IN;
wire csrf_external_int_pend_vec_3$EN;
// register csrf_fflags_reg
reg [4 : 0] csrf_fflags_reg;
reg [4 : 0] csrf_fflags_reg$D_IN;
wire csrf_fflags_reg$EN;
// register csrf_frm_reg
reg [2 : 0] csrf_frm_reg;
wire [2 : 0] csrf_frm_reg$D_IN;
wire csrf_frm_reg$EN;
// register csrf_fs_reg
reg [1 : 0] csrf_fs_reg;
reg [1 : 0] csrf_fs_reg$D_IN;
wire csrf_fs_reg$EN;
// register csrf_ie_vec_0
reg csrf_ie_vec_0;
wire csrf_ie_vec_0$D_IN, csrf_ie_vec_0$EN;
// register csrf_ie_vec_1
reg csrf_ie_vec_1;
reg csrf_ie_vec_1$D_IN;
wire csrf_ie_vec_1$EN;
// register csrf_ie_vec_3
reg csrf_ie_vec_3;
reg csrf_ie_vec_3$D_IN;
wire csrf_ie_vec_3$EN;
// register csrf_mcause_code_reg
reg [3 : 0] csrf_mcause_code_reg;
reg [3 : 0] csrf_mcause_code_reg$D_IN;
wire csrf_mcause_code_reg$EN;
// register csrf_mcause_interrupt_reg
reg csrf_mcause_interrupt_reg;
reg csrf_mcause_interrupt_reg$D_IN;
wire csrf_mcause_interrupt_reg$EN;
// register csrf_mcounteren_cy_reg
reg csrf_mcounteren_cy_reg;
wire csrf_mcounteren_cy_reg$D_IN, csrf_mcounteren_cy_reg$EN;
// register csrf_mcounteren_ir_reg
reg csrf_mcounteren_ir_reg;
wire csrf_mcounteren_ir_reg$D_IN, csrf_mcounteren_ir_reg$EN;
// register csrf_mcounteren_tm_reg
reg csrf_mcounteren_tm_reg;
wire csrf_mcounteren_tm_reg$D_IN, csrf_mcounteren_tm_reg$EN;
// register csrf_mcycle_ehr_data_rl
reg [63 : 0] csrf_mcycle_ehr_data_rl;
wire [63 : 0] csrf_mcycle_ehr_data_rl$D_IN;
wire csrf_mcycle_ehr_data_rl$EN;
// register csrf_medeleg_13_11_reg
reg [2 : 0] csrf_medeleg_13_11_reg;
wire [2 : 0] csrf_medeleg_13_11_reg$D_IN;
wire csrf_medeleg_13_11_reg$EN;
// register csrf_medeleg_15_reg
reg csrf_medeleg_15_reg;
wire csrf_medeleg_15_reg$D_IN, csrf_medeleg_15_reg$EN;
// register csrf_medeleg_9_0_reg
reg [9 : 0] csrf_medeleg_9_0_reg;
wire [9 : 0] csrf_medeleg_9_0_reg$D_IN;
wire csrf_medeleg_9_0_reg$EN;
// register csrf_mepc_csr
reg [63 : 0] csrf_mepc_csr;
reg [63 : 0] csrf_mepc_csr$D_IN;
wire csrf_mepc_csr$EN;
// register csrf_mideleg_11_reg
reg csrf_mideleg_11_reg;
wire csrf_mideleg_11_reg$D_IN, csrf_mideleg_11_reg$EN;
// register csrf_mideleg_1_0_reg
reg [1 : 0] csrf_mideleg_1_0_reg;
wire [1 : 0] csrf_mideleg_1_0_reg$D_IN;
wire csrf_mideleg_1_0_reg$EN;
// register csrf_mideleg_5_3_reg
reg [2 : 0] csrf_mideleg_5_3_reg;
wire [2 : 0] csrf_mideleg_5_3_reg$D_IN;
wire csrf_mideleg_5_3_reg$EN;
// register csrf_mideleg_9_7_reg
reg [2 : 0] csrf_mideleg_9_7_reg;
wire [2 : 0] csrf_mideleg_9_7_reg$D_IN;
wire csrf_mideleg_9_7_reg$EN;
// register csrf_minstret_ehr_data_rl
reg [63 : 0] csrf_minstret_ehr_data_rl;
wire [63 : 0] csrf_minstret_ehr_data_rl$D_IN;
wire csrf_minstret_ehr_data_rl$EN;
// register csrf_mpp_reg
reg [1 : 0] csrf_mpp_reg;
reg [1 : 0] csrf_mpp_reg$D_IN;
wire csrf_mpp_reg$EN;
// register csrf_mprv_reg
reg csrf_mprv_reg;
wire csrf_mprv_reg$D_IN, csrf_mprv_reg$EN;
// register csrf_mscratch_csr
reg [63 : 0] csrf_mscratch_csr;
wire [63 : 0] csrf_mscratch_csr$D_IN;
wire csrf_mscratch_csr$EN;
// register csrf_mtval_csr
reg [63 : 0] csrf_mtval_csr;
reg [63 : 0] csrf_mtval_csr$D_IN;
wire csrf_mtval_csr$EN;
// register csrf_mtvec_base_hi_reg
reg [61 : 0] csrf_mtvec_base_hi_reg;
wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN;
wire csrf_mtvec_base_hi_reg$EN;
// register csrf_mtvec_mode_low_reg
reg csrf_mtvec_mode_low_reg;
wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN;
// register csrf_mxr_reg
reg csrf_mxr_reg;
wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN;
// register csrf_ppn_reg
reg [43 : 0] csrf_ppn_reg;
wire [43 : 0] csrf_ppn_reg$D_IN;
wire csrf_ppn_reg$EN;
// register csrf_prev_ie_vec_0
reg csrf_prev_ie_vec_0;
wire csrf_prev_ie_vec_0$D_IN, csrf_prev_ie_vec_0$EN;
// register csrf_prev_ie_vec_1
reg csrf_prev_ie_vec_1;
reg csrf_prev_ie_vec_1$D_IN;
wire csrf_prev_ie_vec_1$EN;
// register csrf_prev_ie_vec_3
reg csrf_prev_ie_vec_3;
reg csrf_prev_ie_vec_3$D_IN;
wire csrf_prev_ie_vec_3$EN;
// register csrf_prv_reg
reg [1 : 0] csrf_prv_reg;
reg [1 : 0] csrf_prv_reg$D_IN;
wire csrf_prv_reg$EN;
// register csrf_rg_dcsr
reg [63 : 0] csrf_rg_dcsr;
reg [63 : 0] csrf_rg_dcsr$D_IN;
wire csrf_rg_dcsr$EN;
// register csrf_rg_dpc
reg [63 : 0] csrf_rg_dpc;
reg [63 : 0] csrf_rg_dpc$D_IN;
wire csrf_rg_dpc$EN;
// register csrf_rg_dscratch0
reg [63 : 0] csrf_rg_dscratch0;
wire [63 : 0] csrf_rg_dscratch0$D_IN;
wire csrf_rg_dscratch0$EN;
// register csrf_rg_dscratch1
reg [63 : 0] csrf_rg_dscratch1;
wire [63 : 0] csrf_rg_dscratch1$D_IN;
wire csrf_rg_dscratch1$EN;
// register csrf_rg_tdata1_data
reg [58 : 0] csrf_rg_tdata1_data;
wire [58 : 0] csrf_rg_tdata1_data$D_IN;
wire csrf_rg_tdata1_data$EN;
// register csrf_rg_tdata1_dmode
reg csrf_rg_tdata1_dmode;
wire csrf_rg_tdata1_dmode$D_IN, csrf_rg_tdata1_dmode$EN;
// register csrf_rg_tdata2
reg [63 : 0] csrf_rg_tdata2;
wire [63 : 0] csrf_rg_tdata2$D_IN;
wire csrf_rg_tdata2$EN;
// register csrf_rg_tdata3
reg [63 : 0] csrf_rg_tdata3;
wire [63 : 0] csrf_rg_tdata3$D_IN;
wire csrf_rg_tdata3$EN;
// register csrf_rg_tselect
reg [63 : 0] csrf_rg_tselect;
wire [63 : 0] csrf_rg_tselect$D_IN;
wire csrf_rg_tselect$EN;
// register csrf_scause_code_reg
reg [3 : 0] csrf_scause_code_reg;
reg [3 : 0] csrf_scause_code_reg$D_IN;
wire csrf_scause_code_reg$EN;
// register csrf_scause_interrupt_reg
reg csrf_scause_interrupt_reg;
reg csrf_scause_interrupt_reg$D_IN;
wire csrf_scause_interrupt_reg$EN;
// register csrf_scounteren_cy_reg
reg csrf_scounteren_cy_reg;
wire csrf_scounteren_cy_reg$D_IN, csrf_scounteren_cy_reg$EN;
// register csrf_scounteren_ir_reg
reg csrf_scounteren_ir_reg;
wire csrf_scounteren_ir_reg$D_IN, csrf_scounteren_ir_reg$EN;
// register csrf_scounteren_tm_reg
reg csrf_scounteren_tm_reg;
wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN;
// register csrf_sepc_csr
reg [63 : 0] csrf_sepc_csr;
reg [63 : 0] csrf_sepc_csr$D_IN;
wire csrf_sepc_csr$EN;
// register csrf_software_int_en_vec_0
reg csrf_software_int_en_vec_0;
wire csrf_software_int_en_vec_0$D_IN, csrf_software_int_en_vec_0$EN;
// register csrf_software_int_en_vec_1
reg csrf_software_int_en_vec_1;
wire csrf_software_int_en_vec_1$D_IN, csrf_software_int_en_vec_1$EN;
// register csrf_software_int_en_vec_3
reg csrf_software_int_en_vec_3;
wire csrf_software_int_en_vec_3$D_IN, csrf_software_int_en_vec_3$EN;
// register csrf_software_int_pend_vec_0
reg csrf_software_int_pend_vec_0;
wire csrf_software_int_pend_vec_0$D_IN, csrf_software_int_pend_vec_0$EN;
// register csrf_software_int_pend_vec_1
reg csrf_software_int_pend_vec_1;
wire csrf_software_int_pend_vec_1$D_IN, csrf_software_int_pend_vec_1$EN;
// register csrf_software_int_pend_vec_3
reg csrf_software_int_pend_vec_3;
reg csrf_software_int_pend_vec_3$D_IN;
wire csrf_software_int_pend_vec_3$EN;
// register csrf_spp_reg
reg csrf_spp_reg;
reg csrf_spp_reg$D_IN;
wire csrf_spp_reg$EN;
// register csrf_sscratch_csr
reg [63 : 0] csrf_sscratch_csr;
wire [63 : 0] csrf_sscratch_csr$D_IN;
wire csrf_sscratch_csr$EN;
// register csrf_stats_module_doStats
reg csrf_stats_module_doStats;
wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN;
// register csrf_stval_csr
reg [63 : 0] csrf_stval_csr;
reg [63 : 0] csrf_stval_csr$D_IN;
wire csrf_stval_csr$EN;
// register csrf_stvec_base_hi_reg
reg [61 : 0] csrf_stvec_base_hi_reg;
wire [61 : 0] csrf_stvec_base_hi_reg$D_IN;
wire csrf_stvec_base_hi_reg$EN;
// register csrf_stvec_mode_low_reg
reg csrf_stvec_mode_low_reg;
wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN;
// register csrf_sum_reg
reg csrf_sum_reg;
wire csrf_sum_reg$D_IN, csrf_sum_reg$EN;
// register csrf_time_reg
reg [63 : 0] csrf_time_reg;
wire [63 : 0] csrf_time_reg$D_IN;
wire csrf_time_reg$EN;
// register csrf_timer_int_en_vec_0
reg csrf_timer_int_en_vec_0;
wire csrf_timer_int_en_vec_0$D_IN, csrf_timer_int_en_vec_0$EN;
// register csrf_timer_int_en_vec_1
reg csrf_timer_int_en_vec_1;
wire csrf_timer_int_en_vec_1$D_IN, csrf_timer_int_en_vec_1$EN;
// register csrf_timer_int_en_vec_3
reg csrf_timer_int_en_vec_3;
wire csrf_timer_int_en_vec_3$D_IN, csrf_timer_int_en_vec_3$EN;
// register csrf_timer_int_pend_vec_0
reg csrf_timer_int_pend_vec_0;
wire csrf_timer_int_pend_vec_0$D_IN, csrf_timer_int_pend_vec_0$EN;
// register csrf_timer_int_pend_vec_1
reg csrf_timer_int_pend_vec_1;
wire csrf_timer_int_pend_vec_1$D_IN, csrf_timer_int_pend_vec_1$EN;
// register csrf_timer_int_pend_vec_3
reg csrf_timer_int_pend_vec_3;
wire csrf_timer_int_pend_vec_3$D_IN, csrf_timer_int_pend_vec_3$EN;
// register csrf_tsr_reg
reg csrf_tsr_reg;
wire csrf_tsr_reg$D_IN, csrf_tsr_reg$EN;
// register csrf_tvm_reg
reg csrf_tvm_reg;
wire csrf_tvm_reg$D_IN, csrf_tvm_reg$EN;
// register csrf_tw_reg
reg csrf_tw_reg;
wire csrf_tw_reg$D_IN, csrf_tw_reg$EN;
// register csrf_vm_mode_sv39_reg
reg csrf_vm_mode_sv39_reg;
wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN;
// register flush_brpred
reg flush_brpred;
wire flush_brpred$D_IN, flush_brpred$EN;
// register flush_caches
reg flush_caches;
wire flush_caches$D_IN, flush_caches$EN;
// register flush_reservation
reg flush_reservation;
wire flush_reservation$D_IN, flush_reservation$EN;
// register flush_tlbs
reg flush_tlbs;
wire flush_tlbs$D_IN, flush_tlbs$EN;
// register mmio_cRqQ_clearReq_rl
reg mmio_cRqQ_clearReq_rl;
wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN;
// register mmio_cRqQ_data_0
reg [141 : 0] mmio_cRqQ_data_0;
wire [141 : 0] mmio_cRqQ_data_0$D_IN;
wire mmio_cRqQ_data_0$EN;
// register mmio_cRqQ_deqReq_rl
reg mmio_cRqQ_deqReq_rl;
wire mmio_cRqQ_deqReq_rl$D_IN, mmio_cRqQ_deqReq_rl$EN;
// register mmio_cRqQ_empty
reg mmio_cRqQ_empty;
wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN;
// register mmio_cRqQ_enqReq_rl
reg [142 : 0] mmio_cRqQ_enqReq_rl;
wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN;
wire mmio_cRqQ_enqReq_rl$EN;
// register mmio_cRqQ_full
reg mmio_cRqQ_full;
wire mmio_cRqQ_full$D_IN, mmio_cRqQ_full$EN;
// register mmio_cRsQ_clearReq_rl
reg mmio_cRsQ_clearReq_rl;
wire mmio_cRsQ_clearReq_rl$D_IN, mmio_cRsQ_clearReq_rl$EN;
// register mmio_cRsQ_data_0
reg mmio_cRsQ_data_0;
wire mmio_cRsQ_data_0$D_IN, mmio_cRsQ_data_0$EN;
// register mmio_cRsQ_deqReq_rl
reg mmio_cRsQ_deqReq_rl;
wire mmio_cRsQ_deqReq_rl$D_IN, mmio_cRsQ_deqReq_rl$EN;
// register mmio_cRsQ_empty
reg mmio_cRsQ_empty;
wire mmio_cRsQ_empty$D_IN, mmio_cRsQ_empty$EN;
// register mmio_cRsQ_enqReq_rl
reg [1 : 0] mmio_cRsQ_enqReq_rl;
wire [1 : 0] mmio_cRsQ_enqReq_rl$D_IN;
wire mmio_cRsQ_enqReq_rl$EN;
// register mmio_cRsQ_full
reg mmio_cRsQ_full;
wire mmio_cRsQ_full$D_IN, mmio_cRsQ_full$EN;
// register mmio_dataPendQ_clearReq_rl
reg mmio_dataPendQ_clearReq_rl;
wire mmio_dataPendQ_clearReq_rl$D_IN, mmio_dataPendQ_clearReq_rl$EN;
// register mmio_dataPendQ_deqReq_rl
reg mmio_dataPendQ_deqReq_rl;
wire mmio_dataPendQ_deqReq_rl$D_IN, mmio_dataPendQ_deqReq_rl$EN;
// register mmio_dataPendQ_empty
reg mmio_dataPendQ_empty;
wire mmio_dataPendQ_empty$D_IN, mmio_dataPendQ_empty$EN;
// register mmio_dataPendQ_enqReq_rl
reg mmio_dataPendQ_enqReq_rl;
wire mmio_dataPendQ_enqReq_rl$D_IN, mmio_dataPendQ_enqReq_rl$EN;
// register mmio_dataPendQ_full
reg mmio_dataPendQ_full;
wire mmio_dataPendQ_full$D_IN, mmio_dataPendQ_full$EN;
// register mmio_dataReqQ_clearReq_rl
reg mmio_dataReqQ_clearReq_rl;
wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN;
// register mmio_dataReqQ_data_0
reg [141 : 0] mmio_dataReqQ_data_0;
wire [141 : 0] mmio_dataReqQ_data_0$D_IN;
wire mmio_dataReqQ_data_0$EN;
// register mmio_dataReqQ_deqReq_rl
reg mmio_dataReqQ_deqReq_rl;
wire mmio_dataReqQ_deqReq_rl$D_IN, mmio_dataReqQ_deqReq_rl$EN;
// register mmio_dataReqQ_empty
reg mmio_dataReqQ_empty;
wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN;
// register mmio_dataReqQ_enqReq_rl
reg [142 : 0] mmio_dataReqQ_enqReq_rl;
wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN;
wire mmio_dataReqQ_enqReq_rl$EN;
// register mmio_dataReqQ_full
reg mmio_dataReqQ_full;
wire mmio_dataReqQ_full$D_IN, mmio_dataReqQ_full$EN;
// register mmio_dataRespQ_clearReq_rl
reg mmio_dataRespQ_clearReq_rl;
wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN;
// register mmio_dataRespQ_data_0
reg [64 : 0] mmio_dataRespQ_data_0;
wire [64 : 0] mmio_dataRespQ_data_0$D_IN;
wire mmio_dataRespQ_data_0$EN;
// register mmio_dataRespQ_deqReq_rl
reg mmio_dataRespQ_deqReq_rl;
wire mmio_dataRespQ_deqReq_rl$D_IN, mmio_dataRespQ_deqReq_rl$EN;
// register mmio_dataRespQ_empty
reg mmio_dataRespQ_empty;
wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN;
// register mmio_dataRespQ_enqReq_rl
reg [65 : 0] mmio_dataRespQ_enqReq_rl;
wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN;
wire mmio_dataRespQ_enqReq_rl$EN;
// register mmio_dataRespQ_full
reg mmio_dataRespQ_full;
wire mmio_dataRespQ_full$D_IN, mmio_dataRespQ_full$EN;
// register mmio_fromHostAddr
reg [60 : 0] mmio_fromHostAddr;
wire [60 : 0] mmio_fromHostAddr$D_IN;
wire mmio_fromHostAddr$EN;
// register mmio_pRqQ_clearReq_rl
reg mmio_pRqQ_clearReq_rl;
wire mmio_pRqQ_clearReq_rl$D_IN, mmio_pRqQ_clearReq_rl$EN;
// register mmio_pRqQ_data_0
reg [38 : 0] mmio_pRqQ_data_0;
wire [38 : 0] mmio_pRqQ_data_0$D_IN;
wire mmio_pRqQ_data_0$EN;
// register mmio_pRqQ_deqReq_rl
reg mmio_pRqQ_deqReq_rl;
wire mmio_pRqQ_deqReq_rl$D_IN, mmio_pRqQ_deqReq_rl$EN;
// register mmio_pRqQ_empty
reg mmio_pRqQ_empty;
wire mmio_pRqQ_empty$D_IN, mmio_pRqQ_empty$EN;
// register mmio_pRqQ_enqReq_rl
reg [39 : 0] mmio_pRqQ_enqReq_rl;
wire [39 : 0] mmio_pRqQ_enqReq_rl$D_IN;
wire mmio_pRqQ_enqReq_rl$EN;
// register mmio_pRqQ_full
reg mmio_pRqQ_full;
wire mmio_pRqQ_full$D_IN, mmio_pRqQ_full$EN;
// register mmio_pRsQ_clearReq_rl
reg mmio_pRsQ_clearReq_rl;
wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN;
// register mmio_pRsQ_data_0
reg [66 : 0] mmio_pRsQ_data_0;
wire [66 : 0] mmio_pRsQ_data_0$D_IN;
wire mmio_pRsQ_data_0$EN;
// register mmio_pRsQ_deqReq_rl
reg mmio_pRsQ_deqReq_rl;
wire mmio_pRsQ_deqReq_rl$D_IN, mmio_pRsQ_deqReq_rl$EN;
// register mmio_pRsQ_empty
reg mmio_pRsQ_empty;
wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN;
// register mmio_pRsQ_enqReq_rl
reg [67 : 0] mmio_pRsQ_enqReq_rl;
wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN;
wire mmio_pRsQ_enqReq_rl$EN;
// register mmio_pRsQ_full
reg mmio_pRsQ_full;
wire mmio_pRsQ_full$D_IN, mmio_pRsQ_full$EN;
// register mmio_toHostAddr
reg [60 : 0] mmio_toHostAddr;
wire [60 : 0] mmio_toHostAddr$D_IN;
wire mmio_toHostAddr$EN;
// register outOfReset
reg outOfReset;
wire outOfReset$D_IN, outOfReset$EN;
// register renameStage_rg_m_halt_req
reg [4 : 0] renameStage_rg_m_halt_req;
reg [4 : 0] renameStage_rg_m_halt_req$D_IN;
wire renameStage_rg_m_halt_req$EN;
// register rg_core_run_state
reg [1 : 0] rg_core_run_state;
reg [1 : 0] rg_core_run_state$D_IN;
wire rg_core_run_state$EN;
// register started
reg started;
wire started$D_IN, started$EN;
// register update_vm_info
reg update_vm_info;
wire update_vm_info$D_IN, update_vm_info$EN;
// ports of submodule commitStage_f_rob_data
wire [425 : 0] commitStage_f_rob_data$D_IN, commitStage_f_rob_data$D_OUT;
wire commitStage_f_rob_data$CLR,
commitStage_f_rob_data$DEQ,
commitStage_f_rob_data$EMPTY_N,
commitStage_f_rob_data$ENQ,
commitStage_f_rob_data$FULL_N;
// ports of submodule coreFix_aluExe_0_dispToRegQ
reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x,
coreFix_aluExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_dispToRegQ$EN_deq,
coreFix_aluExe_0_dispToRegQ$EN_enq,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_dispToRegQ$RDY_deq,
coreFix_aluExe_0_dispToRegQ$RDY_enq,
coreFix_aluExe_0_dispToRegQ$RDY_first,
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_exeToFinQ
reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [326 : 0] coreFix_aluExe_0_exeToFinQ$enq_x,
coreFix_aluExe_0_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_exeToFinQ$EN_deq,
coreFix_aluExe_0_exeToFinQ$EN_enq,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_exeToFinQ$RDY_deq,
coreFix_aluExe_0_exeToFinQ$RDY_enq,
coreFix_aluExe_0_exeToFinQ$RDY_first,
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_regToExeQ
reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_0_regToExeQ$enq_x,
coreFix_aluExe_0_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_regToExeQ$EN_deq,
coreFix_aluExe_0_regToExeQ$EN_enq,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_regToExeQ$RDY_deq,
coreFix_aluExe_0_regToExeQ$RDY_enq,
coreFix_aluExe_0_regToExeQ$RDY_first,
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_rsAlu
reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put,
coreFix_aluExe_0_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData,
coreFix_aluExe_0_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put,
coreFix_aluExe_0_rsAlu$setRegReady_1_put,
coreFix_aluExe_0_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_0_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_0_rsAlu$approximateCount;
wire coreFix_aluExe_0_rsAlu$EN_doDispatch,
coreFix_aluExe_0_rsAlu$EN_enq,
coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_0_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_rsAlu$RDY_dispatchData,
coreFix_aluExe_0_rsAlu$RDY_doDispatch,
coreFix_aluExe_0_rsAlu$RDY_enq,
coreFix_aluExe_0_rsAlu$canEnq,
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_dispToRegQ
reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x,
coreFix_aluExe_1_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_dispToRegQ$EN_deq,
coreFix_aluExe_1_dispToRegQ$EN_enq,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_dispToRegQ$RDY_deq,
coreFix_aluExe_1_dispToRegQ$RDY_enq,
coreFix_aluExe_1_dispToRegQ$RDY_first,
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_exeToFinQ
reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [326 : 0] coreFix_aluExe_1_exeToFinQ$enq_x,
coreFix_aluExe_1_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_exeToFinQ$EN_deq,
coreFix_aluExe_1_exeToFinQ$EN_enq,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_exeToFinQ$RDY_deq,
coreFix_aluExe_1_exeToFinQ$RDY_enq,
coreFix_aluExe_1_exeToFinQ$RDY_first,
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_regToExeQ
reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_1_regToExeQ$enq_x,
coreFix_aluExe_1_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_regToExeQ$EN_deq,
coreFix_aluExe_1_regToExeQ$EN_enq,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_regToExeQ$RDY_deq,
coreFix_aluExe_1_regToExeQ$RDY_enq,
coreFix_aluExe_1_regToExeQ$RDY_first,
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_rsAlu
reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put,
coreFix_aluExe_1_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData,
coreFix_aluExe_1_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put,
coreFix_aluExe_1_rsAlu$setRegReady_1_put,
coreFix_aluExe_1_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_1_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_1_rsAlu$approximateCount;
wire coreFix_aluExe_1_rsAlu$EN_doDispatch,
coreFix_aluExe_1_rsAlu$EN_enq,
coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_1_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_rsAlu$RDY_dispatchData,
coreFix_aluExe_1_rsAlu$RDY_doDispatch,
coreFix_aluExe_1_rsAlu$RDY_enq,
coreFix_aluExe_1_rsAlu$canEnq,
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ
reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x,
coreFix_fpuMulDivExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first,
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
wire [130 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
wire [195 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get;
wire [66 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put;
wire coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag;
wire [101 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata;
wire [75 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
reg [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN;
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ;
// ports of submodule coreFix_fpuMulDivExe_0_regToExeQ
reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x,
coreFix_fpuMulDivExe_0_regToExeQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_enq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first,
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put;
reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag;
wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x;
wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put;
wire [5 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t;
wire coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n;
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq;
wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr;
wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData;
wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq;
wire [1 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n;
wire coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r;
reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam;
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq;
reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first;
wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dTlb
reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag;
wire [246 : 0] coreFix_memExe_dTlb$procResp;
wire [177 : 0] coreFix_memExe_dTlb$procReq_req;
wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x;
wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm;
wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first;
wire [11 : 0] coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask;
wire [2 : 0] coreFix_memExe_dTlb$perf_req_r;
wire coreFix_memExe_dTlb$EN_deqProcResp,
coreFix_memExe_dTlb$EN_flush,
coreFix_memExe_dTlb$EN_perf_req,
coreFix_memExe_dTlb$EN_perf_resp,
coreFix_memExe_dTlb$EN_perf_setStatus,
coreFix_memExe_dTlb$EN_procReq,
coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation,
coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dTlb$EN_toParent_flush_request_get,
coreFix_memExe_dTlb$EN_toParent_flush_response_put,
coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$EN_toParent_rqToP_deq,
coreFix_memExe_dTlb$EN_updateVMInfo,
coreFix_memExe_dTlb$RDY_deqProcResp,
coreFix_memExe_dTlb$RDY_flush,
coreFix_memExe_dTlb$RDY_procReq,
coreFix_memExe_dTlb$RDY_procResp,
coreFix_memExe_dTlb$RDY_toParent_flush_request_get,
coreFix_memExe_dTlb$RDY_toParent_flush_response_put,
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_first,
coreFix_memExe_dTlb$flush_done,
coreFix_memExe_dTlb$noPendingReq,
coreFix_memExe_dTlb$perf_setStatus_doStats,
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dispToRegQ
reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x,
coreFix_memExe_dispToRegQ$first;
wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_dispToRegQ$EN_deq,
coreFix_memExe_dispToRegQ$EN_enq,
coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dispToRegQ$RDY_deq,
coreFix_memExe_dispToRegQ$RDY_enq,
coreFix_memExe_dispToRegQ$RDY_first,
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$EN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_lsq
reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag;
wire [170 : 0] coreFix_memExe_lsq$firstSt;
wire [113 : 0] coreFix_memExe_lsq$firstLd;
wire [85 : 0] coreFix_memExe_lsq$respLd;
wire [76 : 0] coreFix_memExe_lsq$getIssueLd;
wire [74 : 0] coreFix_memExe_lsq$issueLd;
wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes;
wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr,
coreFix_memExe_lsq$respLd_alignedData,
coreFix_memExe_lsq$updateAddr_paddr,
coreFix_memExe_lsq$updateData_d;
wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst,
coreFix_memExe_lsq$enqSt_mem_inst;
wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag,
coreFix_memExe_lsq$enqLd_spec_bits,
coreFix_memExe_lsq$enqSt_inst_tag,
coreFix_memExe_lsq$enqSt_spec_bits,
coreFix_memExe_lsq$specUpdate_correctSpeculation_mask;
wire [9 : 0] coreFix_memExe_lsq$getHit;
wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst;
wire [7 : 0] coreFix_memExe_lsq$getOrigBE,
coreFix_memExe_lsq$issueLd_shiftedBE,
coreFix_memExe_lsq$updateAddr_shiftedBE;
wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag;
wire [5 : 0] coreFix_memExe_lsq$getHit_t,
coreFix_memExe_lsq$getOrigBE_t,
coreFix_memExe_lsq$setAtCommit_0_put,
coreFix_memExe_lsq$setAtCommit_1_put,
coreFix_memExe_lsq$updateAddr_lsqTag;
wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag,
coreFix_memExe_lsq$respLd_t,
coreFix_memExe_lsq$updateAddr_fault;
wire [3 : 0] coreFix_memExe_lsq$updateData_t;
wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx;
wire coreFix_memExe_lsq$EN_deqLd,
coreFix_memExe_lsq$EN_deqSt,
coreFix_memExe_lsq$EN_enqLd,
coreFix_memExe_lsq$EN_enqSt,
coreFix_memExe_lsq$EN_getHit,
coreFix_memExe_lsq$EN_getIssueLd,
coreFix_memExe_lsq$EN_issueLd,
coreFix_memExe_lsq$EN_respLd,
coreFix_memExe_lsq$EN_setAtCommit_0_put,
coreFix_memExe_lsq$EN_setAtCommit_1_put,
coreFix_memExe_lsq$EN_specUpdate_correctSpeculation,
coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_lsq$EN_updateAddr,
coreFix_memExe_lsq$EN_updateData,
coreFix_memExe_lsq$EN_wakeupLdStalledBySB,
coreFix_memExe_lsq$RDY_deqLd,
coreFix_memExe_lsq$RDY_deqSt,
coreFix_memExe_lsq$RDY_enqLd,
coreFix_memExe_lsq$RDY_enqSt,
coreFix_memExe_lsq$RDY_firstLd,
coreFix_memExe_lsq$RDY_firstSt,
coreFix_memExe_lsq$RDY_getIssueLd,
coreFix_memExe_lsq$noWrongPathLoads,
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all,
coreFix_memExe_lsq$stqEmpty,
coreFix_memExe_lsq$updateAddr,
coreFix_memExe_lsq$updateAddr_isMMIO;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_regToExeQ
reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [192 : 0] coreFix_memExe_regToExeQ$enq_x,
coreFix_memExe_regToExeQ$first;
wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_regToExeQ$EN_deq,
coreFix_memExe_regToExeQ$EN_enq,
coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_regToExeQ$RDY_deq,
coreFix_memExe_regToExeQ$RDY_enq,
coreFix_memExe_regToExeQ$RDY_first,
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0
wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1
wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_1$EN,
coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2
wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_2$EN,
coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0
wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_0$EN,
coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1
wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_1$EN,
coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2
wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_2$EN,
coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0
wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1
wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_1$EN,
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0
wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1
wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0
wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1
wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_1$EN,
coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2
wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_2$EN,
coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0
wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1
wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_0
wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN,
coreFix_memExe_reqStQ_full_dummy2_0$EN,
coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_1
wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN,
coreFix_memExe_reqStQ_full_dummy2_1$EN,
coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_2
wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN,
coreFix_memExe_reqStQ_full_dummy2_2$EN,
coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_rsMem
reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put,
coreFix_memExe_rsMem$setRegReady_4_put;
reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag;
wire [106 : 0] coreFix_memExe_rsMem$dispatchData,
coreFix_memExe_rsMem$enq_x;
wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put,
coreFix_memExe_rsMem$setRegReady_1_put,
coreFix_memExe_rsMem$setRegReady_3_put;
wire [5 : 0] coreFix_memExe_rsMem$setRobEnqTime_t;
wire coreFix_memExe_rsMem$EN_doDispatch,
coreFix_memExe_rsMem$EN_enq,
coreFix_memExe_rsMem$EN_setRegReady_0_put,
coreFix_memExe_rsMem$EN_setRegReady_1_put,
coreFix_memExe_rsMem$EN_setRegReady_2_put,
coreFix_memExe_rsMem$EN_setRegReady_3_put,
coreFix_memExe_rsMem$EN_setRegReady_4_put,
coreFix_memExe_rsMem$EN_setRobEnqTime,
coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation,
coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_rsMem$RDY_dispatchData,
coreFix_memExe_rsMem$RDY_doDispatch,
coreFix_memExe_rsMem$RDY_enq,
coreFix_memExe_rsMem$canEnq,
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_stb
wire [635 : 0] coreFix_memExe_stb$issue;
wire [633 : 0] coreFix_memExe_stb$deq;
wire [67 : 0] coreFix_memExe_stb$search;
wire [63 : 0] coreFix_memExe_stb$enq_data,
coreFix_memExe_stb$enq_paddr,
coreFix_memExe_stb$getEnqIndex_paddr,
coreFix_memExe_stb$noMatchLdQ_paddr,
coreFix_memExe_stb$noMatchStQ_paddr,
coreFix_memExe_stb$search_paddr;
wire [7 : 0] coreFix_memExe_stb$enq_be,
coreFix_memExe_stb$noMatchLdQ_be,
coreFix_memExe_stb$noMatchStQ_be,
coreFix_memExe_stb$search_be;
wire [2 : 0] coreFix_memExe_stb$getEnqIndex;
wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx;
wire coreFix_memExe_stb$EN_deq,
coreFix_memExe_stb$EN_enq,
coreFix_memExe_stb$EN_issue,
coreFix_memExe_stb$RDY_deq,
coreFix_memExe_stb$RDY_enq,
coreFix_memExe_stb$RDY_issue,
coreFix_memExe_stb$isEmpty,
coreFix_memExe_stb$noMatchLdQ,
coreFix_memExe_stb$noMatchStQ;
// ports of submodule coreFix_trainBPQ_0
wire [159 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT;
wire coreFix_trainBPQ_0$CLR,
coreFix_trainBPQ_0$DEQ,
coreFix_trainBPQ_0$EMPTY_N,
coreFix_trainBPQ_0$ENQ,
coreFix_trainBPQ_0$FULL_N;
// ports of submodule coreFix_trainBPQ_1
wire [159 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT;
wire coreFix_trainBPQ_1$CLR,
coreFix_trainBPQ_1$DEQ,
coreFix_trainBPQ_1$EMPTY_N,
coreFix_trainBPQ_1$ENQ,
coreFix_trainBPQ_1$FULL_N;
// ports of submodule csrInstOrInterruptInflight_dummy2_0
wire csrInstOrInterruptInflight_dummy2_0$D_IN,
csrInstOrInterruptInflight_dummy2_0$EN,
csrInstOrInterruptInflight_dummy2_0$Q_OUT;
// ports of submodule csrInstOrInterruptInflight_dummy2_1
wire csrInstOrInterruptInflight_dummy2_1$D_IN,
csrInstOrInterruptInflight_dummy2_1$EN,
csrInstOrInterruptInflight_dummy2_1$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_0
wire csrf_mcycle_ehr_data_dummy2_0$D_IN,
csrf_mcycle_ehr_data_dummy2_0$EN,
csrf_mcycle_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_1
wire csrf_mcycle_ehr_data_dummy2_1$D_IN,
csrf_mcycle_ehr_data_dummy2_1$EN,
csrf_mcycle_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_0
wire csrf_minstret_ehr_data_dummy2_0$D_IN,
csrf_minstret_ehr_data_dummy2_0$EN,
csrf_minstret_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_1
wire csrf_minstret_ehr_data_dummy2_1$D_IN,
csrf_minstret_ehr_data_dummy2_1$EN,
csrf_minstret_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_stats_module_writeQ
wire csrf_stats_module_writeQ$CLR,
csrf_stats_module_writeQ$DEQ,
csrf_stats_module_writeQ$D_IN,
csrf_stats_module_writeQ$D_OUT,
csrf_stats_module_writeQ$EMPTY_N,
csrf_stats_module_writeQ$ENQ,
csrf_stats_module_writeQ$FULL_N;
// ports of submodule csrf_terminate_module_terminateQ
wire csrf_terminate_module_terminateQ$CLR,
csrf_terminate_module_terminateQ$DEQ,
csrf_terminate_module_terminateQ$EMPTY_N,
csrf_terminate_module_terminateQ$ENQ,
csrf_terminate_module_terminateQ$FULL_N;
// ports of submodule epochManager
wire [3 : 0] epochManager$checkEpoch_0_check_e,
epochManager$checkEpoch_1_check_e,
epochManager$updatePrevEpoch_0_update_e,
epochManager$updatePrevEpoch_1_update_e;
wire epochManager$EN_incrementEpoch,
epochManager$EN_updatePrevEpoch_0_update,
epochManager$EN_updatePrevEpoch_1_update,
epochManager$RDY_incrementEpoch,
epochManager$checkEpoch_0_check,
epochManager$checkEpoch_1_check;
// ports of submodule f_csr_reqs
wire [76 : 0] f_csr_reqs$D_IN, f_csr_reqs$D_OUT;
wire f_csr_reqs$CLR,
f_csr_reqs$DEQ,
f_csr_reqs$EMPTY_N,
f_csr_reqs$ENQ,
f_csr_reqs$FULL_N;
// ports of submodule f_csr_rsps
reg [64 : 0] f_csr_rsps$D_IN;
wire [64 : 0] f_csr_rsps$D_OUT;
wire f_csr_rsps$CLR,
f_csr_rsps$DEQ,
f_csr_rsps$EMPTY_N,
f_csr_rsps$ENQ,
f_csr_rsps$FULL_N;
// ports of submodule f_fpr_reqs
wire [69 : 0] f_fpr_reqs$D_IN, f_fpr_reqs$D_OUT;
wire f_fpr_reqs$CLR,
f_fpr_reqs$DEQ,
f_fpr_reqs$EMPTY_N,
f_fpr_reqs$ENQ,
f_fpr_reqs$FULL_N;
// ports of submodule f_fpr_rsps
reg [64 : 0] f_fpr_rsps$D_IN;
wire [64 : 0] f_fpr_rsps$D_OUT;
wire f_fpr_rsps$CLR,
f_fpr_rsps$DEQ,
f_fpr_rsps$EMPTY_N,
f_fpr_rsps$ENQ,
f_fpr_rsps$FULL_N;
// ports of submodule f_gpr_reqs
wire [69 : 0] f_gpr_reqs$D_IN, f_gpr_reqs$D_OUT;
wire f_gpr_reqs$CLR,
f_gpr_reqs$DEQ,
f_gpr_reqs$EMPTY_N,
f_gpr_reqs$ENQ,
f_gpr_reqs$FULL_N;
// ports of submodule f_gpr_rsps
reg [64 : 0] f_gpr_rsps$D_IN;
wire [64 : 0] f_gpr_rsps$D_OUT;
wire f_gpr_rsps$CLR,
f_gpr_rsps$DEQ,
f_gpr_rsps$EMPTY_N,
f_gpr_rsps$ENQ,
f_gpr_rsps$FULL_N;
// ports of submodule f_run_halt_reqs
wire f_run_halt_reqs$CLR,
f_run_halt_reqs$DEQ,
f_run_halt_reqs$D_IN,
f_run_halt_reqs$D_OUT,
f_run_halt_reqs$EMPTY_N,
f_run_halt_reqs$ENQ,
f_run_halt_reqs$FULL_N;
// ports of submodule f_run_halt_rsps
wire f_run_halt_rsps$CLR,
f_run_halt_rsps$DEQ,
f_run_halt_rsps$D_IN,
f_run_halt_rsps$D_OUT,
f_run_halt_rsps$EMPTY_N,
f_run_halt_rsps$ENQ,
f_run_halt_rsps$FULL_N;
// ports of submodule fetchStage
reg [63 : 0] fetchStage$redirect_pc;
wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x;
wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first;
wire [387 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first;
wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x;
wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first;
wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get,
fetchStage$iMemIfc_pRqStuck_get;
wire [65 : 0] fetchStage$mmioIfc_instResp_enq_x;
wire [63 : 0] fetchStage$iMemIfc_to_proc_request_put,
fetchStage$iTlbIfc_to_proc_request_put,
fetchStage$mmioIfc_instReq_first_fst,
fetchStage$mmioIfc_setHtifAddrs_fromHost,
fetchStage$mmioIfc_setHtifAddrs_toHost,
fetchStage$start_pc,
fetchStage$train_predictors_next_pc,
fetchStage$train_predictors_pc;
wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm;
wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first;
wire [23 : 0] fetchStage$train_predictors_dpTrain;
wire [4 : 0] fetchStage$train_predictors_iType;
wire [2 : 0] fetchStage$iTlbIfc_perf_req_r;
wire [1 : 0] fetchStage$iMemIfc_perf_req_r, fetchStage$perf_req_r;
wire fetchStage$EN_done_flushing,
fetchStage$EN_flush_predictors,
fetchStage$EN_iMemIfc_cRqStuck_get,
fetchStage$EN_iMemIfc_flush,
fetchStage$EN_iMemIfc_pRqStuck_get,
fetchStage$EN_iMemIfc_perf_req,
fetchStage$EN_iMemIfc_perf_resp,
fetchStage$EN_iMemIfc_perf_setStatus,
fetchStage$EN_iMemIfc_to_parent_fromP_enq,
fetchStage$EN_iMemIfc_to_parent_rqToP_deq,
fetchStage$EN_iMemIfc_to_parent_rsToP_deq,
fetchStage$EN_iMemIfc_to_proc_request_put,
fetchStage$EN_iMemIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_flush,
fetchStage$EN_iTlbIfc_perf_req,
fetchStage$EN_iTlbIfc_perf_resp,
fetchStage$EN_iTlbIfc_perf_setStatus,
fetchStage$EN_iTlbIfc_toParent_flush_request_get,
fetchStage$EN_iTlbIfc_toParent_flush_response_put,
fetchStage$EN_iTlbIfc_toParent_rqToP_deq,
fetchStage$EN_iTlbIfc_toParent_rsFromP_enq,
fetchStage$EN_iTlbIfc_to_proc_request_put,
fetchStage$EN_iTlbIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_updateVMInfo,
fetchStage$EN_mmioIfc_instReq_deq,
fetchStage$EN_mmioIfc_instResp_enq,
fetchStage$EN_mmioIfc_setHtifAddrs,
fetchStage$EN_perf_req,
fetchStage$EN_perf_resp,
fetchStage$EN_perf_setStatus,
fetchStage$EN_pipelines_0_deq,
fetchStage$EN_pipelines_1_deq,
fetchStage$EN_redirect,
fetchStage$EN_setWaitFlush,
fetchStage$EN_setWaitRedirect,
fetchStage$EN_start,
fetchStage$EN_stop,
fetchStage$EN_train_predictors,
fetchStage$RDY_done_flushing,
fetchStage$RDY_iMemIfc_cRqStuck_get,
fetchStage$RDY_iMemIfc_pRqStuck_get,
fetchStage$RDY_iMemIfc_to_parent_fromP_enq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_first,
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rsToP_first,
fetchStage$RDY_iTlbIfc_flush,
fetchStage$RDY_iTlbIfc_toParent_flush_request_get,
fetchStage$RDY_iTlbIfc_toParent_flush_response_put,
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq,
fetchStage$RDY_iTlbIfc_toParent_rqToP_first,
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq,
fetchStage$RDY_mmioIfc_instReq_deq,
fetchStage$RDY_mmioIfc_instReq_first_fst,
fetchStage$RDY_mmioIfc_instReq_first_snd,
fetchStage$RDY_mmioIfc_instResp_enq,
fetchStage$RDY_pipelines_0_deq,
fetchStage$RDY_pipelines_0_first,
fetchStage$RDY_pipelines_1_deq,
fetchStage$RDY_pipelines_1_first,
fetchStage$emptyForFlush,
fetchStage$flush_predictors_done,
fetchStage$iMemIfc_flush_done,
fetchStage$iMemIfc_perf_setStatus_doStats,
fetchStage$iMemIfc_to_parent_fromP_notFull,
fetchStage$iMemIfc_to_parent_rqToP_notEmpty,
fetchStage$iMemIfc_to_parent_rsToP_notEmpty,
fetchStage$iTlbIfc_flush_done,
fetchStage$iTlbIfc_noPendingReq,
fetchStage$iTlbIfc_perf_setStatus_doStats,
fetchStage$mmioIfc_instReq_first_snd,
fetchStage$perf_setStatus_doStats,
fetchStage$pipelines_0_canDeq,
fetchStage$pipelines_1_canDeq,
fetchStage$train_predictors_isCompressed,
fetchStage$train_predictors_mispred,
fetchStage$train_predictors_taken;
// ports of submodule l2Tlb
wire [83 : 0] l2Tlb$toChildren_rsToC_first;
wire [64 : 0] l2Tlb$toMem_memReq_first, l2Tlb$toMem_respLd_enq_x;
wire [48 : 0] l2Tlb$updateVMInfo_vmD, l2Tlb$updateVMInfo_vmI;
wire [29 : 0] l2Tlb$toChildren_rqFromC_put;
wire [3 : 0] l2Tlb$perf_req_r;
wire l2Tlb$EN_perf_req,
l2Tlb$EN_perf_resp,
l2Tlb$EN_perf_setStatus,
l2Tlb$EN_toChildren_dTlbReqFlush_put,
l2Tlb$EN_toChildren_flushDone_get,
l2Tlb$EN_toChildren_iTlbReqFlush_put,
l2Tlb$EN_toChildren_rqFromC_put,
l2Tlb$EN_toChildren_rsToC_deq,
l2Tlb$EN_toMem_memReq_deq,
l2Tlb$EN_toMem_respLd_enq,
l2Tlb$EN_updateVMInfo,
l2Tlb$RDY_toChildren_dTlbReqFlush_put,
l2Tlb$RDY_toChildren_flushDone_get,
l2Tlb$RDY_toChildren_iTlbReqFlush_put,
l2Tlb$RDY_toChildren_rqFromC_put,
l2Tlb$RDY_toChildren_rsToC_deq,
l2Tlb$RDY_toChildren_rsToC_first,
l2Tlb$RDY_toMem_memReq_deq,
l2Tlb$RDY_toMem_memReq_first,
l2Tlb$RDY_toMem_respLd_enq,
l2Tlb$perf_setStatus_doStats,
l2Tlb$toMem_memReq_notEmpty,
l2Tlb$toMem_respLd_notFull;
// ports of submodule mmio_cRqQ_clearReq_dummy2_0
wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_clearReq_dummy2_1
wire mmio_cRqQ_clearReq_dummy2_1$D_IN,
mmio_cRqQ_clearReq_dummy2_1$EN,
mmio_cRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRqQ_deqReq_dummy2_0
wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_1
wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_2
wire mmio_cRqQ_deqReq_dummy2_2$D_IN,
mmio_cRqQ_deqReq_dummy2_2$EN,
mmio_cRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRqQ_enqReq_dummy2_0
wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_1
wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_2
wire mmio_cRqQ_enqReq_dummy2_2$D_IN,
mmio_cRqQ_enqReq_dummy2_2$EN,
mmio_cRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_clearReq_dummy2_0
wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_clearReq_dummy2_1
wire mmio_cRsQ_clearReq_dummy2_1$D_IN,
mmio_cRsQ_clearReq_dummy2_1$EN,
mmio_cRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRsQ_deqReq_dummy2_0
wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_1
wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_2
wire mmio_cRsQ_deqReq_dummy2_2$D_IN,
mmio_cRsQ_deqReq_dummy2_2$EN,
mmio_cRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_enqReq_dummy2_0
wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_1
wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_2
wire mmio_cRsQ_enqReq_dummy2_2$D_IN,
mmio_cRsQ_enqReq_dummy2_2$EN,
mmio_cRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_0
wire mmio_dataPendQ_clearReq_dummy2_0$D_IN,
mmio_dataPendQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_1
wire mmio_dataPendQ_clearReq_dummy2_1$D_IN,
mmio_dataPendQ_clearReq_dummy2_1$EN,
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_0
wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_1
wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_2
wire mmio_dataPendQ_deqReq_dummy2_2$D_IN,
mmio_dataPendQ_deqReq_dummy2_2$EN,
mmio_dataPendQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_0
wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_1
wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_2
wire mmio_dataPendQ_enqReq_dummy2_2$D_IN,
mmio_dataPendQ_enqReq_dummy2_2$EN,
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_0
wire mmio_dataReqQ_clearReq_dummy2_0$D_IN,
mmio_dataReqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_1
wire mmio_dataReqQ_clearReq_dummy2_1$D_IN,
mmio_dataReqQ_clearReq_dummy2_1$EN,
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_0
wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_1
wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_2
wire mmio_dataReqQ_deqReq_dummy2_2$D_IN,
mmio_dataReqQ_deqReq_dummy2_2$EN,
mmio_dataReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_0
wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_1
wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_2
wire mmio_dataReqQ_enqReq_dummy2_2$D_IN,
mmio_dataReqQ_enqReq_dummy2_2$EN,
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_0
wire mmio_dataRespQ_clearReq_dummy2_0$D_IN,
mmio_dataRespQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_1
wire mmio_dataRespQ_clearReq_dummy2_1$D_IN,
mmio_dataRespQ_clearReq_dummy2_1$EN,
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_0
wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_1
wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_2
wire mmio_dataRespQ_deqReq_dummy2_2$D_IN,
mmio_dataRespQ_deqReq_dummy2_2$EN,
mmio_dataRespQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_0
wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_1
wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_2
wire mmio_dataRespQ_enqReq_dummy2_2$D_IN,
mmio_dataRespQ_enqReq_dummy2_2$EN,
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_clearReq_dummy2_0
wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_clearReq_dummy2_1
wire mmio_pRqQ_clearReq_dummy2_1$D_IN,
mmio_pRqQ_clearReq_dummy2_1$EN,
mmio_pRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRqQ_deqReq_dummy2_0
wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_1
wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_2
wire mmio_pRqQ_deqReq_dummy2_2$D_IN,
mmio_pRqQ_deqReq_dummy2_2$EN,
mmio_pRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_enqReq_dummy2_0
wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_1
wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_2
wire mmio_pRqQ_enqReq_dummy2_2$D_IN,
mmio_pRqQ_enqReq_dummy2_2$EN,
mmio_pRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_clearReq_dummy2_0
wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_clearReq_dummy2_1
wire mmio_pRsQ_clearReq_dummy2_1$D_IN,
mmio_pRsQ_clearReq_dummy2_1$EN,
mmio_pRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRsQ_deqReq_dummy2_0
wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_1
wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_2
wire mmio_pRsQ_deqReq_dummy2_2$D_IN,
mmio_pRsQ_deqReq_dummy2_2$EN,
mmio_pRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_enqReq_dummy2_0
wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_1
wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_2
wire mmio_pRsQ_enqReq_dummy2_2$D_IN,
mmio_pRsQ_enqReq_dummy2_2$EN,
mmio_pRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule perfReqQ
wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT;
wire perfReqQ$CLR,
perfReqQ$DEQ,
perfReqQ$EMPTY_N,
perfReqQ$ENQ,
perfReqQ$FULL_N;
// ports of submodule regRenamingTable
reg [26 : 0] regRenamingTable$rename_0_getRename_r;
reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag;
wire [32 : 0] regRenamingTable$rename_0_getRename,
regRenamingTable$rename_1_getRename;
wire [26 : 0] regRenamingTable$rename_0_claimRename_r,
regRenamingTable$rename_1_claimRename_r,
regRenamingTable$rename_1_getRename_r;
wire [11 : 0] regRenamingTable$rename_0_claimRename_sb,
regRenamingTable$rename_1_claimRename_sb,
regRenamingTable$specUpdate_correctSpeculation_mask;
wire regRenamingTable$EN_commit_0_commit,
regRenamingTable$EN_commit_1_commit,
regRenamingTable$EN_rename_0_claimRename,
regRenamingTable$EN_rename_1_claimRename,
regRenamingTable$EN_specUpdate_correctSpeculation,
regRenamingTable$EN_specUpdate_incorrectSpeculation,
regRenamingTable$RDY_commit_0_commit,
regRenamingTable$RDY_commit_1_commit,
regRenamingTable$RDY_rename_0_claimRename,
regRenamingTable$RDY_rename_0_getRename,
regRenamingTable$RDY_rename_1_claimRename,
regRenamingTable$RDY_rename_1_getRename,
regRenamingTable$rename_0_canRename,
regRenamingTable$rename_1_canRename,
regRenamingTable$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule rf
reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data;
reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx;
wire [63 : 0] rf$read_0_rd1,
rf$read_0_rd2,
rf$read_1_rd1,
rf$read_1_rd2,
rf$read_2_rd1,
rf$read_2_rd2,
rf$read_2_rd3,
rf$read_3_rd1,
rf$read_3_rd2,
rf$read_4_rd1,
rf$write_0_wr_data,
rf$write_1_wr_data,
rf$write_4_wr_data;
wire [6 : 0] rf$read_0_rd1_rindx,
rf$read_0_rd2_rindx,
rf$read_0_rd3_rindx,
rf$read_1_rd1_rindx,
rf$read_1_rd2_rindx,
rf$read_1_rd3_rindx,
rf$read_2_rd1_rindx,
rf$read_2_rd2_rindx,
rf$read_2_rd3_rindx,
rf$read_3_rd1_rindx,
rf$read_3_rd2_rindx,
rf$read_3_rd3_rindx,
rf$read_4_rd1_rindx,
rf$read_4_rd2_rindx,
rf$read_4_rd3_rindx,
rf$write_0_wr_rindx,
rf$write_1_wr_rindx,
rf$write_4_wr_rindx;
wire rf$EN_write_0_wr,
rf$EN_write_1_wr,
rf$EN_write_2_wr,
rf$EN_write_3_wr,
rf$EN_write_4_wr;
// ports of submodule rob
reg [425 : 0] rob$enqPort_0_enq_x;
reg [63 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data,
rob$setExecuted_doFinishMem_RegData_dst_data;
reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x,
rob$setExecuted_doFinishMem_RegData_x,
rob$specUpdate_incorrectSpeculation_inst_tag;
reg [4 : 0] rob$setExecuted_deqLSQ_cause,
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags;
reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag;
wire [425 : 0] rob$deqPort_0_deq_data,
rob$deqPort_1_deq_data,
rob$enqPort_1_enq_x;
wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf,
rob$setExecuted_doFinishAlu_1_set_cf;
wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData,
rob$setExecuted_doFinishAlu_1_set_csrData;
wire [63 : 0] rob$getOrigPC_0_get,
rob$getOrigPC_1_get,
rob$getOrigPredPC_0_get,
rob$getOrigPredPC_1_get,
rob$setExecuted_doFinishAlu_0_set_dst_data,
rob$setExecuted_doFinishAlu_1_set_dst_data,
rob$setExecuted_doFinishMem_store_data,
rob$setExecuted_doFinishMem_vaddr;
wire [31 : 0] rob$getOrig_Inst_0_get, rob$getOrig_Inst_1_get;
wire [11 : 0] rob$deqPort_0_getDeqInstTag,
rob$enqPort_0_getEnqInstTag,
rob$enqPort_1_getEnqInstTag,
rob$getOrigPC_0_get_x,
rob$getOrigPC_1_get_x,
rob$getOrigPC_2_get_x,
rob$getOrigPredPC_0_get_x,
rob$getOrigPredPC_1_get_x,
rob$getOrig_Inst_0_get_x,
rob$getOrig_Inst_1_get_x,
rob$setExecuted_deqLSQ_x,
rob$setExecuted_doFinishAlu_0_set_x,
rob$setExecuted_doFinishAlu_1_set_x,
rob$setExecuted_doFinishMem_x,
rob$setLSQAtCommitNotified_x,
rob$specUpdate_correctSpeculation_mask;
wire [7 : 0] rob$setExecuted_doFinishMem_store_data_BE;
wire [5 : 0] rob$getEnqTime;
wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed;
wire rob$EN_deqPort_0_deq,
rob$EN_deqPort_1_deq,
rob$EN_enqPort_0_enq,
rob$EN_enqPort_1_enq,
rob$EN_setExecuted_deqLSQ,
rob$EN_setExecuted_doFinishAlu_0_set,
rob$EN_setExecuted_doFinishAlu_1_set,
rob$EN_setExecuted_doFinishFpuMulDiv_0_set,
rob$EN_setExecuted_doFinishMem,
rob$EN_setExecuted_doFinishMem_RegData,
rob$EN_setLSQAtCommitNotified,
rob$EN_specUpdate_correctSpeculation,
rob$EN_specUpdate_incorrectSpeculation,
rob$RDY_deqPort_0_deq,
rob$RDY_deqPort_0_deq_data,
rob$RDY_deqPort_1_deq,
rob$RDY_deqPort_1_deq_data,
rob$RDY_enqPort_0_enq,
rob$RDY_enqPort_1_enq,
rob$RDY_setExecuted_deqLSQ,
rob$RDY_setExecuted_doFinishAlu_0_set,
rob$RDY_setExecuted_doFinishAlu_1_set,
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set,
rob$RDY_setExecuted_doFinishMem,
rob$RDY_setLSQAtCommitNotified,
rob$deqPort_0_canDeq,
rob$deqPort_1_canDeq,
rob$enqPort_0_canEnq,
rob$enqPort_1_canEnq,
rob$isEmpty,
rob$setExecuted_doFinishMem_access_at_commit,
rob$setExecuted_doFinishMem_non_mmio_st_done,
rob$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule sbAggr
reg [6 : 0] sbAggr$setReady_2_put, sbAggr$setReady_4_put;
wire [32 : 0] sbAggr$eagerLookup_0_get_r, sbAggr$eagerLookup_1_get_r;
wire [8 : 0] sbAggr$setBusy_0_set_dst, sbAggr$setBusy_1_set_dst;
wire [6 : 0] sbAggr$setReady_0_put,
sbAggr$setReady_1_put,
sbAggr$setReady_3_put;
wire [3 : 0] sbAggr$eagerLookup_0_get, sbAggr$eagerLookup_1_get;
wire sbAggr$EN_setBusy_0_set,
sbAggr$EN_setBusy_1_set,
sbAggr$EN_setReady_0_put,
sbAggr$EN_setReady_1_put,
sbAggr$EN_setReady_2_put,
sbAggr$EN_setReady_3_put,
sbAggr$EN_setReady_4_put;
// ports of submodule sbCons
reg [6 : 0] sbCons$setReady_2_put, sbCons$setReady_3_put;
wire [32 : 0] sbCons$eagerLookup_0_get_r,
sbCons$eagerLookup_1_get_r,
sbCons$lazyLookup_0_get_r,
sbCons$lazyLookup_1_get_r,
sbCons$lazyLookup_2_get_r,
sbCons$lazyLookup_3_get_r,
sbCons$lazyLookup_4_get_r;
wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst;
wire [6 : 0] sbCons$setReady_0_put,
sbCons$setReady_1_put,
sbCons$setReady_4_put;
wire [3 : 0] sbCons$lazyLookup_0_get,
sbCons$lazyLookup_1_get,
sbCons$lazyLookup_2_get,
sbCons$lazyLookup_3_get;
wire sbCons$EN_setBusy_0_set,
sbCons$EN_setBusy_1_set,
sbCons$EN_setReady_0_put,
sbCons$EN_setReady_1_put,
sbCons$EN_setReady_2_put,
sbCons$EN_setReady_3_put,
sbCons$EN_setReady_4_put;
// ports of submodule specTagManager
reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag;
wire [11 : 0] specTagManager$currentSpecBits,
specTagManager$specUpdate_correctSpeculation_mask;
wire [3 : 0] specTagManager$nextSpecTag;
wire specTagManager$EN_claimSpecTag,
specTagManager$EN_specUpdate_correctSpeculation,
specTagManager$EN_specUpdate_incorrectSpeculation,
specTagManager$RDY_claimSpecTag,
specTagManager$RDY_nextSpecTag,
specTagManager$canClaim,
specTagManager$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule v_f_to_TV_0
reg [784 : 0] v_f_to_TV_0$D_IN;
wire [784 : 0] v_f_to_TV_0$D_OUT;
wire v_f_to_TV_0$CLR,
v_f_to_TV_0$DEQ,
v_f_to_TV_0$EMPTY_N,
v_f_to_TV_0$ENQ,
v_f_to_TV_0$FULL_N;
// ports of submodule v_f_to_TV_1
wire [784 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT;
wire v_f_to_TV_1$CLR,
v_f_to_TV_1$DEQ,
v_f_to_TV_1$EMPTY_N,
v_f_to_TV_1$ENQ,
v_f_to_TV_1$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_commitStage_doCommitKilledLd,
CAN_FIRE_RL_commitStage_doCommitNormalInst,
CAN_FIRE_RL_commitStage_doCommitSystemInst,
CAN_FIRE_RL_commitStage_doCommitTrap_flush,
CAN_FIRE_RL_commitStage_doCommitTrap_handle,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1,
CAN_FIRE_RL_commitStage_notifyLSQCommit,
CAN_FIRE_RL_commitStage_rl_send_tv_reset,
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
CAN_FIRE_RL_coreFix_doFetchTrainBP,
CAN_FIRE_RL_coreFix_doFetchTrainBP_1,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDispatchMem,
CAN_FIRE_RL_coreFix_memExe_doExeMem,
CAN_FIRE_RL_coreFix_memExe_doFinishMem,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
CAN_FIRE_RL_coreFix_memExe_doIssueSB,
CAN_FIRE_RL_coreFix_memExe_doRegReadMem,
CAN_FIRE_RL_coreFix_memExe_doRespLdForward,
CAN_FIRE_RL_coreFix_memExe_doRespLdMem,
CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_sendLdToMem,
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
CAN_FIRE_RL_coreFix_memExe_sendStToMem,
CAN_FIRE_RL_csrInstOrInterruptInflight_canon,
CAN_FIRE_RL_csrf_incCycle,
CAN_FIRE_RL_csrf_mcycle_ehr_data_canon,
CAN_FIRE_RL_csrf_mcycle_ehr_setRead,
CAN_FIRE_RL_csrf_minstret_ehr_data_canon,
CAN_FIRE_RL_csrf_minstret_ehr_setRead,
CAN_FIRE_RL_flushBrPred,
CAN_FIRE_RL_flushCaches,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_mkConnectionGetPut_1,
CAN_FIRE_RL_mmio_cRqQ_canonicalize,
CAN_FIRE_RL_mmio_cRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_canonicalize,
CAN_FIRE_RL_mmio_cRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_canonicalize,
CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_canonicalize,
CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_canonicalize,
CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon,
CAN_FIRE_RL_mmio_handlePRq,
CAN_FIRE_RL_mmio_pRqQ_canonicalize,
CAN_FIRE_RL_mmio_pRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_canonicalize,
CAN_FIRE_RL_mmio_pRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_sendDataReq,
CAN_FIRE_RL_mmio_sendDataResp,
CAN_FIRE_RL_mmio_sendInstReq,
CAN_FIRE_RL_mmio_sendInstResp,
CAN_FIRE_RL_prepareCachesAndTlbs,
CAN_FIRE_RL_readyToFetch,
CAN_FIRE_RL_renameStage_doRenaming,
CAN_FIRE_RL_renameStage_doRenaming_SystemInst,
CAN_FIRE_RL_renameStage_doRenaming_Trap,
CAN_FIRE_RL_renameStage_doRenaming_wrongPath,
CAN_FIRE_RL_rl_debug_csr_access_busy,
CAN_FIRE_RL_rl_debug_csr_read,
CAN_FIRE_RL_rl_debug_csr_write,
CAN_FIRE_RL_rl_debug_fpr_access_busy,
CAN_FIRE_RL_rl_debug_fpr_read,
CAN_FIRE_RL_rl_debug_fpr_write,
CAN_FIRE_RL_rl_debug_gpr_access_busy,
CAN_FIRE_RL_rl_debug_gpr_read,
CAN_FIRE_RL_rl_debug_gpr_write,
CAN_FIRE_RL_rl_debug_halt_req,
CAN_FIRE_RL_rl_debug_halt_req_already_halted,
CAN_FIRE_RL_rl_debug_halted,
CAN_FIRE_RL_rl_debug_resume,
CAN_FIRE_RL_rl_debug_run_redundant,
CAN_FIRE_RL_rl_outOfReset,
CAN_FIRE_RL_sendDTlbReq,
CAN_FIRE_RL_sendFlushDone,
CAN_FIRE_RL_sendITlbReq,
CAN_FIRE_RL_sendRobEnqTime,
CAN_FIRE_RL_sendRsToDTlb,
CAN_FIRE_RL_sendRsToITlb,
CAN_FIRE_RL_setDoFlushBrPred,
CAN_FIRE_RL_setDoFlushCaches,
CAN_FIRE_coreIndInv_perfResp,
CAN_FIRE_coreIndInv_terminate,
CAN_FIRE_coreReq_perfReq,
CAN_FIRE_coreReq_start,
CAN_FIRE_dCacheToParent_fromP_enq,
CAN_FIRE_dCacheToParent_rqToP_deq,
CAN_FIRE_dCacheToParent_rsToP_deq,
CAN_FIRE_deadlock_checkStarted_get,
CAN_FIRE_deadlock_commitInstStuck_get,
CAN_FIRE_deadlock_commitUserInstStuck_get,
CAN_FIRE_deadlock_dCacheCRqStuck_get,
CAN_FIRE_deadlock_dCachePRqStuck_get,
CAN_FIRE_deadlock_iCacheCRqStuck_get,
CAN_FIRE_deadlock_iCachePRqStuck_get,
CAN_FIRE_deadlock_renameCorrectPathStuck_get,
CAN_FIRE_deadlock_renameInstStuck_get,
CAN_FIRE_hart0_csr_mem_server_request_put,
CAN_FIRE_hart0_csr_mem_server_response_get,
CAN_FIRE_hart0_fpr_mem_server_request_put,
CAN_FIRE_hart0_fpr_mem_server_response_get,
CAN_FIRE_hart0_gpr_mem_server_request_put,
CAN_FIRE_hart0_gpr_mem_server_response_get,
CAN_FIRE_hart0_run_halt_server_request_put,
CAN_FIRE_hart0_run_halt_server_response_get,
CAN_FIRE_iCacheToParent_fromP_enq,
CAN_FIRE_iCacheToParent_rqToP_deq,
CAN_FIRE_iCacheToParent_rsToP_deq,
CAN_FIRE_mmioToPlatform_cRq_deq,
CAN_FIRE_mmioToPlatform_cRs_deq,
CAN_FIRE_mmioToPlatform_pRq_enq,
CAN_FIRE_mmioToPlatform_pRs_enq,
CAN_FIRE_mmioToPlatform_setTime,
CAN_FIRE_recvDoStats,
CAN_FIRE_renameDebug_renameErr_get,
CAN_FIRE_sendDoStats,
CAN_FIRE_setMEIP,
CAN_FIRE_setSEIP,
CAN_FIRE_tlbToMem_memReq_deq,
CAN_FIRE_tlbToMem_respLd_enq,
CAN_FIRE_v_to_TV_0_get,
CAN_FIRE_v_to_TV_1_get,
WILL_FIRE_RL_commitStage_doCommitKilledLd,
WILL_FIRE_RL_commitStage_doCommitNormalInst,
WILL_FIRE_RL_commitStage_doCommitSystemInst,
WILL_FIRE_RL_commitStage_doCommitTrap_flush,
WILL_FIRE_RL_commitStage_doCommitTrap_handle,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1,
WILL_FIRE_RL_commitStage_notifyLSQCommit,
WILL_FIRE_RL_commitStage_rl_send_tv_reset,
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
WILL_FIRE_RL_coreFix_doFetchTrainBP,
WILL_FIRE_RL_coreFix_doFetchTrainBP_1,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDispatchMem,
WILL_FIRE_RL_coreFix_memExe_doExeMem,
WILL_FIRE_RL_coreFix_memExe_doFinishMem,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
WILL_FIRE_RL_coreFix_memExe_doIssueSB,
WILL_FIRE_RL_coreFix_memExe_doRegReadMem,
WILL_FIRE_RL_coreFix_memExe_doRespLdForward,
WILL_FIRE_RL_coreFix_memExe_doRespLdMem,
WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_sendLdToMem,
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
WILL_FIRE_RL_coreFix_memExe_sendStToMem,
WILL_FIRE_RL_csrInstOrInterruptInflight_canon,
WILL_FIRE_RL_csrf_incCycle,
WILL_FIRE_RL_csrf_mcycle_ehr_data_canon,
WILL_FIRE_RL_csrf_mcycle_ehr_setRead,
WILL_FIRE_RL_csrf_minstret_ehr_data_canon,
WILL_FIRE_RL_csrf_minstret_ehr_setRead,
WILL_FIRE_RL_flushBrPred,
WILL_FIRE_RL_flushCaches,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_mkConnectionGetPut_1,
WILL_FIRE_RL_mmio_cRqQ_canonicalize,
WILL_FIRE_RL_mmio_cRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_canonicalize,
WILL_FIRE_RL_mmio_cRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_canonicalize,
WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_canonicalize,
WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_canonicalize,
WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon,
WILL_FIRE_RL_mmio_handlePRq,
WILL_FIRE_RL_mmio_pRqQ_canonicalize,
WILL_FIRE_RL_mmio_pRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_canonicalize,
WILL_FIRE_RL_mmio_pRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_sendDataReq,
WILL_FIRE_RL_mmio_sendDataResp,
WILL_FIRE_RL_mmio_sendInstReq,
WILL_FIRE_RL_mmio_sendInstResp,
WILL_FIRE_RL_prepareCachesAndTlbs,
WILL_FIRE_RL_readyToFetch,
WILL_FIRE_RL_renameStage_doRenaming,
WILL_FIRE_RL_renameStage_doRenaming_SystemInst,
WILL_FIRE_RL_renameStage_doRenaming_Trap,
WILL_FIRE_RL_renameStage_doRenaming_wrongPath,
WILL_FIRE_RL_rl_debug_csr_access_busy,
WILL_FIRE_RL_rl_debug_csr_read,
WILL_FIRE_RL_rl_debug_csr_write,
WILL_FIRE_RL_rl_debug_fpr_access_busy,
WILL_FIRE_RL_rl_debug_fpr_read,
WILL_FIRE_RL_rl_debug_fpr_write,
WILL_FIRE_RL_rl_debug_gpr_access_busy,
WILL_FIRE_RL_rl_debug_gpr_read,
WILL_FIRE_RL_rl_debug_gpr_write,
WILL_FIRE_RL_rl_debug_halt_req,
WILL_FIRE_RL_rl_debug_halt_req_already_halted,
WILL_FIRE_RL_rl_debug_halted,
WILL_FIRE_RL_rl_debug_resume,
WILL_FIRE_RL_rl_debug_run_redundant,
WILL_FIRE_RL_rl_outOfReset,
WILL_FIRE_RL_sendDTlbReq,
WILL_FIRE_RL_sendFlushDone,
WILL_FIRE_RL_sendITlbReq,
WILL_FIRE_RL_sendRobEnqTime,
WILL_FIRE_RL_sendRsToDTlb,
WILL_FIRE_RL_sendRsToITlb,
WILL_FIRE_RL_setDoFlushBrPred,
WILL_FIRE_RL_setDoFlushCaches,
WILL_FIRE_coreIndInv_perfResp,
WILL_FIRE_coreIndInv_terminate,
WILL_FIRE_coreReq_perfReq,
WILL_FIRE_coreReq_start,
WILL_FIRE_dCacheToParent_fromP_enq,
WILL_FIRE_dCacheToParent_rqToP_deq,
WILL_FIRE_dCacheToParent_rsToP_deq,
WILL_FIRE_deadlock_checkStarted_get,
WILL_FIRE_deadlock_commitInstStuck_get,
WILL_FIRE_deadlock_commitUserInstStuck_get,
WILL_FIRE_deadlock_dCacheCRqStuck_get,
WILL_FIRE_deadlock_dCachePRqStuck_get,
WILL_FIRE_deadlock_iCacheCRqStuck_get,
WILL_FIRE_deadlock_iCachePRqStuck_get,
WILL_FIRE_deadlock_renameCorrectPathStuck_get,
WILL_FIRE_deadlock_renameInstStuck_get,
WILL_FIRE_hart0_csr_mem_server_request_put,
WILL_FIRE_hart0_csr_mem_server_response_get,
WILL_FIRE_hart0_fpr_mem_server_request_put,
WILL_FIRE_hart0_fpr_mem_server_response_get,
WILL_FIRE_hart0_gpr_mem_server_request_put,
WILL_FIRE_hart0_gpr_mem_server_response_get,
WILL_FIRE_hart0_run_halt_server_request_put,
WILL_FIRE_hart0_run_halt_server_response_get,
WILL_FIRE_iCacheToParent_fromP_enq,
WILL_FIRE_iCacheToParent_rqToP_deq,
WILL_FIRE_iCacheToParent_rsToP_deq,
WILL_FIRE_mmioToPlatform_cRq_deq,
WILL_FIRE_mmioToPlatform_cRs_deq,
WILL_FIRE_mmioToPlatform_pRq_enq,
WILL_FIRE_mmioToPlatform_pRs_enq,
WILL_FIRE_mmioToPlatform_setTime,
WILL_FIRE_recvDoStats,
WILL_FIRE_renameDebug_renameErr_get,
WILL_FIRE_sendDoStats,
WILL_FIRE_setMEIP,
WILL_FIRE_setSEIP,
WILL_FIRE_tlbToMem_memReq_deq,
WILL_FIRE_tlbToMem_respLd_enq,
WILL_FIRE_v_to_TV_0_get,
WILL_FIRE_v_to_TV_1_get;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1,
MUX_coreFix_memExe_lsq$respLd_2__VAL_2,
MUX_fetchStage$redirect_1__VAL_6;
reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1,
MUX_coreFix_memExe_lsq$respLd_1__VAL_2;
reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3;
wire [784 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1,
MUX_v_f_to_TV_0$enq_1__VAL_2,
MUX_v_f_to_TV_0$enq_1__VAL_4;
wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
wire [425 : 0] MUX_rob$enqPort_0_enq_1__VAL_1,
MUX_rob$enqPort_0_enq_1__VAL_2,
MUX_rob$enqPort_0_enq_1__VAL_3;
wire [165 : 0] MUX_commitStage_commitTrap$write_1__VAL_2;
wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2;
wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
wire [159 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1,
MUX_coreFix_trainBPQ_0$enq_1__VAL_2,
MUX_coreFix_trainBPQ_1$enq_1__VAL_1,
MUX_coreFix_trainBPQ_1$enq_1__VAL_2;
wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2;
wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2;
wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1;
wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1;
wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3,
MUX_f_csr_rsps$enq_1__VAL_3,
MUX_f_fpr_rsps$enq_1__VAL_3;
wire [63 : 0] MUX_commitStage_rg_serial_num$write_1__VAL_1,
MUX_commitStage_rg_serial_num$write_1__VAL_3,
MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2,
MUX_csrf_mtval_csr$write_1__VAL_1,
MUX_csrf_rg_dcsr$write_1__VAL_2,
MUX_csrf_sepc_csr$write_1__VAL_1,
MUX_csrf_stval_csr$write_1__VAL_1,
MUX_rf$write_2_wr_2__VAL_2,
MUX_rf$write_2_wr_2__VAL_3,
MUX_rf$write_2_wr_2__VAL_4,
MUX_rf$write_2_wr_2__VAL_5,
MUX_rf$write_2_wr_2__VAL_6,
MUX_rf$write_3_wr_2__VAL_3,
MUX_rf$write_3_wr_2__VAL_4;
wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1,
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1;
wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1,
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2;
wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2,
MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1;
wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1,
MUX_rob$setExecuted_deqLSQ_2__VAL_3,
MUX_rob$setExecuted_deqLSQ_2__VAL_6,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2;
wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1,
MUX_csrf_frm_reg$write_1__VAL_1,
MUX_csrf_frm_reg$write_1__VAL_2;
wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__VAL_1;
wire MUX_commitStage_rg_run_state$write_1__SEL_1,
MUX_commitStage_rg_serial_num$write_1__SEL_1,
MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1,
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2,
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2,
MUX_coreFix_memExe_lsq$getHit_1__SEL_1,
MUX_coreFix_memExe_lsq$getHit_1__SEL_2,
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1,
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1,
MUX_coreFix_trainBPQ_0$enq_1__SEL_1,
MUX_coreFix_trainBPQ_1$enq_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2,
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1,
MUX_csrf_external_int_en_vec_1$write_1__SEL_1,
MUX_csrf_external_int_en_vec_3$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_1$write_1__SEL_2,
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2,
MUX_csrf_fflags_reg$write_1__SEL_1,
MUX_csrf_fflags_reg$write_1__SEL_2,
MUX_csrf_fflags_reg$write_1__SEL_3,
MUX_csrf_frm_reg$write_1__SEL_1,
MUX_csrf_fs_reg$write_1__SEL_2,
MUX_csrf_fs_reg$write_1__SEL_3,
MUX_csrf_ie_vec_0$write_1__SEL_1,
MUX_csrf_ie_vec_0$write_1__SEL_2,
MUX_csrf_ie_vec_1$write_1__SEL_1,
MUX_csrf_ie_vec_1$write_1__SEL_2,
MUX_csrf_ie_vec_1$write_1__VAL_1,
MUX_csrf_ie_vec_3$write_1__SEL_1,
MUX_csrf_ie_vec_3$write_1__SEL_2,
MUX_csrf_ie_vec_3$write_1__SEL_3,
MUX_csrf_ie_vec_3$write_1__VAL_1,
MUX_csrf_mcause_code_reg$write_1__SEL_1,
MUX_csrf_mcause_code_reg$write_1__SEL_3,
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1,
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1,
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2,
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1,
MUX_csrf_mepc_csr$write_1__SEL_1,
MUX_csrf_mepc_csr$write_1__SEL_3,
MUX_csrf_mideleg_11_reg$write_1__SEL_1,
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1,
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2,
MUX_csrf_mpp_reg$write_1__SEL_1,
MUX_csrf_mscratch_csr$write_1__SEL_1,
MUX_csrf_mtval_csr$write_1__SEL_1,
MUX_csrf_mtval_csr$write_1__SEL_3,
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1,
MUX_csrf_ppn_reg$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__VAL_1,
MUX_csrf_prev_ie_vec_3$write_1__SEL_1,
MUX_csrf_prev_ie_vec_3$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__SEL_1,
MUX_csrf_prv_reg$write_1__SEL_3,
MUX_csrf_rg_dcsr$write_1__SEL_1,
MUX_csrf_rg_dpc$write_1__SEL_1,
MUX_csrf_rg_dpc$write_1__SEL_3,
MUX_csrf_rg_dscratch0$write_1__SEL_1,
MUX_csrf_rg_dscratch1$write_1__SEL_1,
MUX_csrf_rg_tdata1_data$write_1__SEL_1,
MUX_csrf_rg_tdata2$write_1__SEL_1,
MUX_csrf_rg_tdata3$write_1__SEL_1,
MUX_csrf_rg_tselect$write_1__SEL_1,
MUX_csrf_scause_code_reg$write_1__SEL_1,
MUX_csrf_scause_code_reg$write_1__SEL_3,
MUX_csrf_scounteren_cy_reg$write_1__SEL_1,
MUX_csrf_sepc_csr$write_1__SEL_1,
MUX_csrf_sepc_csr$write_1__SEL_3,
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2,
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2,
MUX_csrf_spp_reg$write_1__SEL_1,
MUX_csrf_spp_reg$write_1__VAL_1,
MUX_csrf_sscratch_csr$write_1__SEL_1,
MUX_csrf_stats_module_writeQ$enq_1__SEL_1,
MUX_csrf_stval_csr$write_1__SEL_1,
MUX_csrf_stval_csr$write_1__SEL_3,
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1,
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2,
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2,
MUX_flush_reservation$write_1__SEL_2,
MUX_flush_tlbs$write_1__SEL_1,
MUX_regRenamingTable$rename_0_getRename_1__SEL_1,
MUX_regRenamingTable$rename_0_getRename_1__SEL_2,
MUX_regRenamingTable$rename_0_getRename_1__SEL_3,
MUX_renameStage_rg_m_halt_req$write_1__PSEL_1,
MUX_renameStage_rg_m_halt_req$write_1__SEL_1,
MUX_renameStage_rg_m_halt_req$write_1__SEL_2,
MUX_rf$write_3_wr_1__PSEL_5,
MUX_rf$write_3_wr_1__SEL_1,
MUX_rf$write_3_wr_1__SEL_2,
MUX_rf$write_3_wr_1__SEL_3,
MUX_rf$write_3_wr_1__SEL_4,
MUX_rf$write_3_wr_1__SEL_5,
MUX_rf$write_3_wr_2__SEL_5,
MUX_rg_core_run_state$write_1__SEL_4,
MUX_rob$setExecuted_deqLSQ_1__SEL_5,
MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5,
MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5,
MUX_sbAggr$setReady_4_put_1__SEL_1,
MUX_sbAggr$setReady_4_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_1,
MUX_sbCons$setReady_3_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_3,
MUX_started$write_1__SEL_1,
MUX_v_f_to_TV_0$enq_1__SEL_2;
// remaining internal signals
reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500;
reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875,
addr__h290066,
curData__h192915,
data_out__h736609,
data_warl_xformed__h721446,
rVal1__h609049,
rVal1__h633777,
trap_val__h709502,
x__h197125,
x__h722034;
reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19,
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217,
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218,
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219,
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220,
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205,
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206,
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207,
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208,
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209,
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210,
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221,
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222,
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223,
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224,
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225,
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226,
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215,
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874;
reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398;
reg [22 : 0] CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82,
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83,
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86,
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87,
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88,
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89,
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119,
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120,
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49,
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50,
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117,
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118,
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47,
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48,
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121,
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122,
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51,
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52,
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124,
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125,
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53,
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54,
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84,
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85,
_theResult___fst_sfd__h346067,
_theResult___fst_sfd__h354790,
_theResult___fst_sfd__h363372,
_theResult___fst_sfd__h372556,
_theResult___fst_sfd__h381192,
_theResult___fst_sfd__h391766,
_theResult___fst_sfd__h400487,
_theResult___fst_sfd__h409069,
_theResult___fst_sfd__h418253,
_theResult___fst_sfd__h426889,
_theResult___fst_sfd__h437461,
_theResult___fst_sfd__h446182,
_theResult___fst_sfd__h454764,
_theResult___fst_sfd__h463948,
_theResult___fst_sfd__h472584;
reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584;
reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407;
reg [11 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277,
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289,
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235,
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255,
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300,
CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5,
CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1,
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973;
reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18,
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211,
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212,
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213,
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214,
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183,
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184,
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185,
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186,
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187,
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188,
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160,
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161,
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189,
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190,
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191,
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192,
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143,
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803;
reg [7 : 0] CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67,
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68,
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75,
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76,
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80,
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81,
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104,
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105,
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34,
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35,
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102,
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103,
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32,
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33,
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110,
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111,
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40,
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41,
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115,
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116,
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45,
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46,
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69,
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420,
_theResult___fst_exp__h346066,
_theResult___fst_exp__h354789,
_theResult___fst_exp__h363371,
_theResult___fst_exp__h372555,
_theResult___fst_exp__h381191,
_theResult___fst_exp__h391765,
_theResult___fst_exp__h400486,
_theResult___fst_exp__h409068,
_theResult___fst_exp__h418252,
_theResult___fst_exp__h426888,
_theResult___fst_exp__h437460,
_theResult___fst_exp__h446181,
_theResult___fst_exp__h454763,
_theResult___fst_exp__h463947,
_theResult___fst_exp__h472583;
reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280,
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274,
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973;
reg [4 : 0] IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14128,
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14261;
reg [3 : 0] CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234,
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278,
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279,
CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20,
CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253,
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6,
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7,
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2,
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131,
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130,
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262,
i__h708478,
i__h708638;
reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269,
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717,
x__h285845,
x__h291615;
reg [1 : 0] CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263,
CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256,
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301,
CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8,
CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4;
reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264,
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244,
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243,
CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241,
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242,
CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93,
CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92,
CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145,
CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95,
CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94,
CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149,
CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97,
CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96,
CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203,
CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193,
CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126,
CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123,
CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199,
CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197,
CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56,
CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55,
CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128,
CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127,
CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201,
CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195,
CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58,
CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57,
CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130,
CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129,
CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60,
CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59,
CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132,
CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131,
CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172,
CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162,
CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62,
CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61,
CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168,
CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164,
CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170,
CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166,
CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91,
CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90,
CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147,
CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14122,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14125,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13465,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13524,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13850,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13872,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13945,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13961,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13968,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14044,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14056,
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259,
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14260,
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902,
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14041,
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14068,
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482,
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002,
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448,
SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772;
wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247;
wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2523,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2522;
wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945;
wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057;
wire [457 : 0] IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916;
wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008;
wire [393 : 0] IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281;
wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048;
wire [321 : 0] basicExec___d11943, basicExec___d12617;
wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003;
wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039;
wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998;
wire [144 : 0] coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706;
wire [68 : 0] execFpuSimple___d11056;
wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627,
IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501;
wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570;
wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12460,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11774,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11786,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8347,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8358,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1648,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1659,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660,
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567,
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377,
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424,
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378,
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425,
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8,
IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180,
_theResult___fst__h603369,
_theResult___snd__h603370,
a___1__h603088,
a___1__h603374,
a__h602947,
amoExec___d880,
b___1__h603089,
b___1__h603419,
b__h602948,
base__h711423,
base__h711443,
commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438,
data___1__h475007,
data___1__h475815,
data__h475281,
fcsr_csr__read__h609375,
fflags_csr__read__h609350,
frm_csr__read__h609361,
mcause_csr__read__h611017,
mcounteren_csr__read__h610762,
medeleg_csr__read__h610369,
mideleg_csr__read__h610464,
mie_csr__read__h610588,
mip_csr__read__h611250,
mstatus_csr__read__h610221,
mtvec_csr__read__h610670,
n___1__h198528,
n__h194453,
n__read__h611354,
n__read__h611545,
n__read__h6759,
n__read__h725937,
next_pc__h721469,
pc__h711407,
q___1__h475880,
rVal1__h481760,
rVal2__h481761,
r___1__h475906,
res_data__h337868,
res_data__h337873,
res_data__h383570,
res_data__h383575,
res_data__h429265,
res_data__h429270,
resp_addr__h291970,
rg_tdata1__read__h612205,
robdeqPort_0_deq_data_BITS_95_TO_32__q245,
satp_csr__read__h610078,
scause_csr__read__h609875,
scounteren_csr__read__h609737,
shiftData__h181566,
sie_csr__read__h609641,
sip_csr__read__h610015,
sstatus_csr__read__h609571,
stvec_csr__read__h609684,
trap_val__h708464,
upd__h3993,
upd__h5310,
upd__h6873,
upd__h726048,
v__h607933,
v__h632816,
x__h153730,
x__h157277,
x__h160091,
x__h161939,
x__h181475,
x__h181476,
x__h18384,
x__h183901,
x__h20922,
x__h287290,
x__h289144,
x__h46291,
x__h481669,
x__h481670,
x__h481671,
x__h48827,
x__h617230,
x__h617231,
x__h639739,
x__h639740,
x__h701397,
x__h713649,
x__h713841,
x__h725432,
x__h728883,
x__h732011,
x_addr__h314073,
x_quotient__h475195,
x_reg_ifc__read__h609480,
x_remainder__h475196,
y__h729714,
y__h732518,
y_avValue__h180563,
y_avValue__h181169,
y_avValue__h478805,
y_avValue__h479413,
y_avValue__h480015,
y_avValue__h608839,
y_avValue__h615055,
y_avValue__h633569,
y_avValue__h637574,
y_avValue_new_pc__h711199,
y_avValue_new_pc__h711385,
y_avValue_snd_snd_snd_snd_snd_fst__h729737,
y_avValue_snd_snd_snd_snd_snd_fst__h732579,
y_avValue_snd_snd_snd_snd_snd_fst__h732615,
y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993;
wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882,
IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909,
r1__read__h613048,
r1__read__h613452,
r1__read__h613962,
r1__read__h613967,
r1__read__h613986,
r1__read__h614219,
r1__read__h614385,
r1__read__h614478,
r1__read__h614483,
r1__read__h614502;
wire [61 : 0] r1__read__h613050,
r1__read__h613454,
r1__read__h613969,
r1__read__h613988,
r1__read__h614221,
r1__read__h614361,
r1__read__h614387,
r1__read__h614485,
r1__read__h614504;
wire [60 : 0] r1__read__h614223,
r1__read__h614363,
r1__read__h614389,
r1__read__h614506;
wire [59 : 0] r1__read__h613052,
r1__read__h613456,
r1__read__h613980,
r1__read__h613990,
r1__read__h614225,
r1__read__h614391,
r1__read__h614496,
r1__read__h614508;
wire [58 : 0] r1__read__h613054,
r1__read__h613458,
r1__read__h613992,
r1__read__h614227,
r1__read__h614393,
r1__read__h614510;
wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713,
r1__read__h613056,
r1__read__h613460,
r1__read__h613994,
r1__read__h614229,
r1__read__h614365,
r1__read__h614395,
r1__read__h614512,
y__h254802;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342,
_theResult____h346084,
_theResult____h363723,
_theResult____h391783,
_theResult____h409420,
_theResult____h437478,
_theResult____h455115,
_theResult____h502868,
_theResult____h541721,
_theResult____h581025,
_theResult___snd__h354206,
_theResult___snd__h354217,
_theResult___snd__h354219,
_theResult___snd__h354229,
_theResult___snd__h354235,
_theResult___snd__h354258,
_theResult___snd__h362802,
_theResult___snd__h362804,
_theResult___snd__h362811,
_theResult___snd__h362817,
_theResult___snd__h362840,
_theResult___snd__h371972,
_theResult___snd__h371983,
_theResult___snd__h371985,
_theResult___snd__h371995,
_theResult___snd__h372001,
_theResult___snd__h372024,
_theResult___snd__h380592,
_theResult___snd__h380606,
_theResult___snd__h380612,
_theResult___snd__h380630,
_theResult___snd__h399903,
_theResult___snd__h399914,
_theResult___snd__h399916,
_theResult___snd__h399926,
_theResult___snd__h399932,
_theResult___snd__h399955,
_theResult___snd__h408499,
_theResult___snd__h408501,
_theResult___snd__h408508,
_theResult___snd__h408514,
_theResult___snd__h408537,
_theResult___snd__h417669,
_theResult___snd__h417680,
_theResult___snd__h417682,
_theResult___snd__h417692,
_theResult___snd__h417698,
_theResult___snd__h417721,
_theResult___snd__h426289,
_theResult___snd__h426303,
_theResult___snd__h426309,
_theResult___snd__h426327,
_theResult___snd__h445598,
_theResult___snd__h445609,
_theResult___snd__h445611,
_theResult___snd__h445621,
_theResult___snd__h445627,
_theResult___snd__h445650,
_theResult___snd__h454194,
_theResult___snd__h454196,
_theResult___snd__h454203,
_theResult___snd__h454209,
_theResult___snd__h454232,
_theResult___snd__h463364,
_theResult___snd__h463375,
_theResult___snd__h463377,
_theResult___snd__h463387,
_theResult___snd__h463393,
_theResult___snd__h463416,
_theResult___snd__h471984,
_theResult___snd__h471998,
_theResult___snd__h472004,
_theResult___snd__h472022,
_theResult___snd__h501478,
_theResult___snd__h501480,
_theResult___snd__h501487,
_theResult___snd__h501493,
_theResult___snd__h501516,
_theResult___snd__h511115,
_theResult___snd__h511126,
_theResult___snd__h511128,
_theResult___snd__h511138,
_theResult___snd__h511144,
_theResult___snd__h511167,
_theResult___snd__h519883,
_theResult___snd__h519897,
_theResult___snd__h519903,
_theResult___snd__h519921,
_theResult___snd__h540331,
_theResult___snd__h540333,
_theResult___snd__h540340,
_theResult___snd__h540346,
_theResult___snd__h540369,
_theResult___snd__h549968,
_theResult___snd__h549979,
_theResult___snd__h549981,
_theResult___snd__h549991,
_theResult___snd__h549997,
_theResult___snd__h550020,
_theResult___snd__h558736,
_theResult___snd__h558750,
_theResult___snd__h558756,
_theResult___snd__h558774,
_theResult___snd__h579635,
_theResult___snd__h579637,
_theResult___snd__h579644,
_theResult___snd__h579650,
_theResult___snd__h579673,
_theResult___snd__h589272,
_theResult___snd__h589283,
_theResult___snd__h589285,
_theResult___snd__h589295,
_theResult___snd__h589301,
_theResult___snd__h589324,
_theResult___snd__h598040,
_theResult___snd__h598054,
_theResult___snd__h598060,
_theResult___snd__h598078,
r1__read__h614231,
r1__read__h614367,
r1__read__h614397,
r1__read__h614514,
result__h364336,
result__h410033,
result__h455728,
result__h503481,
result__h542334,
result__h581638,
sfd__h338479,
sfd__h384181,
sfd__h429876,
sfd__h482501,
sfd__h521495,
sfd__h560799,
sfdin__h354189,
sfdin__h371955,
sfdin__h399886,
sfdin__h417652,
sfdin__h445581,
sfdin__h463347,
sfdin__h511098,
sfdin__h549951,
sfdin__h589255,
x__h364433,
x__h410130,
x__h455825,
x__h503576,
x__h542429,
x__h581733;
wire [55 : 0] r1__read__h613058,
r1__read__h613462,
r1__read__h613996,
r1__read__h614233,
r1__read__h614399,
r1__read__h614516;
wire [54 : 0] r1__read__h613060,
r1__read__h613464,
r1__read__h613998,
r1__read__h614235,
r1__read__h614401,
r1__read__h614518;
wire [53 : 0] r1__read__h614344,
r1__read__h614369,
r1__read__h614403,
r1__read__h614520,
sfd__h501545,
sfd__h511196,
sfd__h519956,
sfd__h540398,
sfd__h550049,
sfd__h558809,
sfd__h579702,
sfd__h589353,
sfd__h598113,
value__h346706,
value__h392403,
value__h438098;
wire [52 : 0] r1__read__h614237,
r1__read__h614346,
r1__read__h614371,
r1__read__h614405,
r1__read__h614522;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881,
_theResult___fst_sfd__h486455,
_theResult___fst_sfd__h502283,
_theResult___fst_sfd__h502286,
_theResult___fst_sfd__h511934,
_theResult___fst_sfd__h511937,
_theResult___fst_sfd__h520718,
_theResult___fst_sfd__h520721,
_theResult___fst_sfd__h520730,
_theResult___fst_sfd__h520736,
_theResult___fst_sfd__h525308,
_theResult___fst_sfd__h541136,
_theResult___fst_sfd__h541139,
_theResult___fst_sfd__h550787,
_theResult___fst_sfd__h550790,
_theResult___fst_sfd__h559571,
_theResult___fst_sfd__h559574,
_theResult___fst_sfd__h559583,
_theResult___fst_sfd__h559589,
_theResult___fst_sfd__h564612,
_theResult___fst_sfd__h580440,
_theResult___fst_sfd__h580443,
_theResult___fst_sfd__h590091,
_theResult___fst_sfd__h590094,
_theResult___fst_sfd__h598875,
_theResult___fst_sfd__h598878,
_theResult___fst_sfd__h598887,
_theResult___fst_sfd__h598893,
_theResult___sfd__h502183,
_theResult___sfd__h511834,
_theResult___sfd__h520618,
_theResult___sfd__h541036,
_theResult___sfd__h550687,
_theResult___sfd__h559471,
_theResult___sfd__h580340,
_theResult___sfd__h589991,
_theResult___sfd__h598775,
_theResult___snd_fst_sfd__h482455,
_theResult___snd_fst_sfd__h502289,
_theResult___snd_fst_sfd__h520724,
_theResult___snd_fst_sfd__h521449,
_theResult___snd_fst_sfd__h541142,
_theResult___snd_fst_sfd__h559577,
_theResult___snd_fst_sfd__h560753,
_theResult___snd_fst_sfd__h580446,
_theResult___snd_fst_sfd__h598881,
out___1_sfd__h482203,
out___1_sfd__h521197,
out___1_sfd__h560501,
out_sfd__h502186,
out_sfd__h511837,
out_sfd__h520621,
out_sfd__h541039,
out_sfd__h550690,
out_sfd__h559474,
out_sfd__h580343,
out_sfd__h589994,
out_sfd__h598778;
wire [50 : 0] r1__read__h613062, r1__read__h614239;
wire [49 : 0] r1__read__h614348;
wire [48 : 0] r1__read_BITS_62_TO_14___h728903,
r1__read__h613064,
r1__read__h614350;
wire [46 : 0] r1__read__h613066, r1__read__h614243;
wire [45 : 0] r1__read__h613068, r1__read__h614245;
wire [44 : 0] r1__read__h613070, r1__read__h614247;
wire [43 : 0] r1__read__h613072, r1__read__h614249;
wire [42 : 0] r1__read__h614251;
wire [41 : 0] r1__read__h614253;
wire [40 : 0] r1__read__h614255;
wire [37 : 0] IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14134,
IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265;
wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11,
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10,
data75281_BITS_31_TO_0__q14,
imm__h655327,
r1__read__h613074,
r1__read__h614257,
x__h193678,
x__h337883,
x__h383585,
x__h429280,
x__h76236,
x_data__h66085,
x_data_imm__h676655,
x_data_imm__h692709;
wire [29 : 0] r1__read__h613076, r1__read__h614259;
wire [27 : 0] r1__read__h614261;
wire [24 : 0] NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14166,
sfd__h354287,
sfd__h362869,
sfd__h372053,
sfd__h380665,
sfd__h399984,
sfd__h408566,
sfd__h417750,
sfd__h426362,
sfd__h445679,
sfd__h454261,
sfd__h463445,
sfd__h472057,
value__h487084,
value__h525937,
value__h565241;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808,
_theResult___fst_sfd__h354793,
_theResult___fst_sfd__h363375,
_theResult___fst_sfd__h372559,
_theResult___fst_sfd__h381195,
_theResult___fst_sfd__h381204,
_theResult___fst_sfd__h381210,
_theResult___fst_sfd__h400490,
_theResult___fst_sfd__h409072,
_theResult___fst_sfd__h418256,
_theResult___fst_sfd__h426892,
_theResult___fst_sfd__h426901,
_theResult___fst_sfd__h426907,
_theResult___fst_sfd__h446185,
_theResult___fst_sfd__h454767,
_theResult___fst_sfd__h463951,
_theResult___fst_sfd__h472587,
_theResult___fst_sfd__h472596,
_theResult___fst_sfd__h472602,
_theResult___sfd__h354712,
_theResult___sfd__h363294,
_theResult___sfd__h372478,
_theResult___sfd__h381114,
_theResult___sfd__h381216,
_theResult___sfd__h400409,
_theResult___sfd__h408991,
_theResult___sfd__h418175,
_theResult___sfd__h426811,
_theResult___sfd__h426913,
_theResult___sfd__h446104,
_theResult___sfd__h454686,
_theResult___sfd__h463870,
_theResult___sfd__h472506,
_theResult___sfd__h472608,
_theResult___snd_fst_sfd__h338429,
_theResult___snd_fst_sfd__h363378,
_theResult___snd_fst_sfd__h381198,
_theResult___snd_fst_sfd__h384131,
_theResult___snd_fst_sfd__h409075,
_theResult___snd_fst_sfd__h426895,
_theResult___snd_fst_sfd__h429826,
_theResult___snd_fst_sfd__h454770,
_theResult___snd_fst_sfd__h472590,
f1_sfd__h482140,
f2_sfd__h521134,
f3_sfd__h560438,
out_f_sfd__h381493,
out_f_sfd__h427190,
out_f_sfd__h472885,
out_sfd__h354715,
out_sfd__h363297,
out_sfd__h372481,
out_sfd__h381117,
out_sfd__h400412,
out_sfd__h408994,
out_sfd__h418178,
out_sfd__h426814,
out_sfd__h446107,
out_sfd__h454689,
out_sfd__h463873,
out_sfd__h472509;
wire [19 : 0] r1__read__h614196;
wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824,
_theResult____h651116,
enabled_ints___1__h651641,
enabled_ints__h651687,
pend_ints__h651114,
y__h651653;
wire [13 : 0] r1__read_BITS_13_TO_0___h651663;
wire [12 : 0] IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271,
fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676,
rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494;
wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661,
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107,
_0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338,
csr_addr__h655325,
renaming_spec_bits__h685237,
result__h646693,
result__h646744,
spec_bits__h688396,
w__h646688,
x__h364466,
x__h410163,
x__h455858,
x__h503609,
x__h542462,
x__h581766,
x__h646692,
x__h646743,
y__h646722,
y__h688409,
y_avValue_fst__h681569,
y_avValue_fst__h681598,
y_avValue_fst__h681632;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180,
_theResult___exp__h502182,
_theResult___exp__h511833,
_theResult___exp__h520617,
_theResult___exp__h541035,
_theResult___exp__h550686,
_theResult___exp__h559470,
_theResult___exp__h580339,
_theResult___exp__h589990,
_theResult___exp__h598774,
_theResult___fst_exp__h486454,
_theResult___fst_exp__h501518,
_theResult___fst_exp__h501524,
_theResult___fst_exp__h501527,
_theResult___fst_exp__h502282,
_theResult___fst_exp__h502285,
_theResult___fst_exp__h511104,
_theResult___fst_exp__h511169,
_theResult___fst_exp__h511175,
_theResult___fst_exp__h511178,
_theResult___fst_exp__h511933,
_theResult___fst_exp__h511936,
_theResult___fst_exp__h519889,
_theResult___fst_exp__h519928,
_theResult___fst_exp__h519934,
_theResult___fst_exp__h519937,
_theResult___fst_exp__h520717,
_theResult___fst_exp__h520720,
_theResult___fst_exp__h520729,
_theResult___fst_exp__h520732,
_theResult___fst_exp__h525307,
_theResult___fst_exp__h540371,
_theResult___fst_exp__h540377,
_theResult___fst_exp__h540380,
_theResult___fst_exp__h541135,
_theResult___fst_exp__h541138,
_theResult___fst_exp__h549957,
_theResult___fst_exp__h550022,
_theResult___fst_exp__h550028,
_theResult___fst_exp__h550031,
_theResult___fst_exp__h550786,
_theResult___fst_exp__h550789,
_theResult___fst_exp__h558742,
_theResult___fst_exp__h558781,
_theResult___fst_exp__h558787,
_theResult___fst_exp__h558790,
_theResult___fst_exp__h559570,
_theResult___fst_exp__h559573,
_theResult___fst_exp__h559582,
_theResult___fst_exp__h559585,
_theResult___fst_exp__h564611,
_theResult___fst_exp__h579675,
_theResult___fst_exp__h579681,
_theResult___fst_exp__h579684,
_theResult___fst_exp__h580439,
_theResult___fst_exp__h580442,
_theResult___fst_exp__h589261,
_theResult___fst_exp__h589326,
_theResult___fst_exp__h589332,
_theResult___fst_exp__h589335,
_theResult___fst_exp__h590090,
_theResult___fst_exp__h590093,
_theResult___fst_exp__h598046,
_theResult___fst_exp__h598085,
_theResult___fst_exp__h598091,
_theResult___fst_exp__h598094,
_theResult___fst_exp__h598874,
_theResult___fst_exp__h598877,
_theResult___fst_exp__h598886,
_theResult___fst_exp__h598889,
_theResult___snd_fst_exp__h502288,
_theResult___snd_fst_exp__h520723,
_theResult___snd_fst_exp__h541141,
_theResult___snd_fst_exp__h559576,
_theResult___snd_fst_exp__h580445,
_theResult___snd_fst_exp__h598880,
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71,
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106,
din_inc___2_exp__h520777,
din_inc___2_exp__h520812,
din_inc___2_exp__h520838,
din_inc___2_exp__h559630,
din_inc___2_exp__h559665,
din_inc___2_exp__h559691,
din_inc___2_exp__h598934,
din_inc___2_exp__h598969,
din_inc___2_exp__h598995,
out_exp__h502185,
out_exp__h511836,
out_exp__h520620,
out_exp__h541038,
out_exp__h550689,
out_exp__h559473,
out_exp__h580342,
out_exp__h589993,
out_exp__h598777;
wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112,
_theResult___exp__h354711,
_theResult___exp__h363293,
_theResult___exp__h372477,
_theResult___exp__h381113,
_theResult___exp__h381215,
_theResult___exp__h400408,
_theResult___exp__h408990,
_theResult___exp__h418174,
_theResult___exp__h426810,
_theResult___exp__h426912,
_theResult___exp__h446103,
_theResult___exp__h454685,
_theResult___exp__h463869,
_theResult___exp__h472505,
_theResult___exp__h472607,
_theResult___fst_exp__h354195,
_theResult___fst_exp__h354260,
_theResult___fst_exp__h354266,
_theResult___fst_exp__h354269,
_theResult___fst_exp__h354792,
_theResult___fst_exp__h362842,
_theResult___fst_exp__h362848,
_theResult___fst_exp__h362851,
_theResult___fst_exp__h363374,
_theResult___fst_exp__h371961,
_theResult___fst_exp__h372026,
_theResult___fst_exp__h372032,
_theResult___fst_exp__h372035,
_theResult___fst_exp__h372558,
_theResult___fst_exp__h380598,
_theResult___fst_exp__h380637,
_theResult___fst_exp__h380643,
_theResult___fst_exp__h380646,
_theResult___fst_exp__h381194,
_theResult___fst_exp__h381203,
_theResult___fst_exp__h381206,
_theResult___fst_exp__h399892,
_theResult___fst_exp__h399957,
_theResult___fst_exp__h399963,
_theResult___fst_exp__h399966,
_theResult___fst_exp__h400489,
_theResult___fst_exp__h408539,
_theResult___fst_exp__h408545,
_theResult___fst_exp__h408548,
_theResult___fst_exp__h409071,
_theResult___fst_exp__h417658,
_theResult___fst_exp__h417723,
_theResult___fst_exp__h417729,
_theResult___fst_exp__h417732,
_theResult___fst_exp__h418255,
_theResult___fst_exp__h426295,
_theResult___fst_exp__h426334,
_theResult___fst_exp__h426340,
_theResult___fst_exp__h426343,
_theResult___fst_exp__h426891,
_theResult___fst_exp__h426900,
_theResult___fst_exp__h426903,
_theResult___fst_exp__h445587,
_theResult___fst_exp__h445652,
_theResult___fst_exp__h445658,
_theResult___fst_exp__h445661,
_theResult___fst_exp__h446184,
_theResult___fst_exp__h454234,
_theResult___fst_exp__h454240,
_theResult___fst_exp__h454243,
_theResult___fst_exp__h454766,
_theResult___fst_exp__h463353,
_theResult___fst_exp__h463418,
_theResult___fst_exp__h463424,
_theResult___fst_exp__h463427,
_theResult___fst_exp__h463950,
_theResult___fst_exp__h471990,
_theResult___fst_exp__h472029,
_theResult___fst_exp__h472035,
_theResult___fst_exp__h472038,
_theResult___fst_exp__h472586,
_theResult___fst_exp__h472595,
_theResult___fst_exp__h472598,
_theResult___snd_fst_exp__h363377,
_theResult___snd_fst_exp__h381197,
_theResult___snd_fst_exp__h409074,
_theResult___snd_fst_exp__h426894,
_theResult___snd_fst_exp__h454769,
_theResult___snd_fst_exp__h472589,
din_inc___2_exp__h381228,
din_inc___2_exp__h381252,
din_inc___2_exp__h381282,
din_inc___2_exp__h381306,
din_inc___2_exp__h426925,
din_inc___2_exp__h426949,
din_inc___2_exp__h426979,
din_inc___2_exp__h427003,
din_inc___2_exp__h472620,
din_inc___2_exp__h472644,
din_inc___2_exp__h472674,
din_inc___2_exp__h472698,
f1_exp82139_MINUS_127__q136,
f1_exp__h482139,
f2_exp21133_MINUS_127__q176,
f2_exp__h521133,
f3_exp60437_MINUS_127__q153,
f3_exp__h560437,
out_exp__h354714,
out_exp__h363296,
out_exp__h372480,
out_exp__h381116,
out_exp__h400411,
out_exp__h408993,
out_exp__h418177,
out_exp__h426813,
out_exp__h446106,
out_exp__h454688,
out_exp__h463872,
out_exp__h472508,
out_f_exp__h381492,
out_f_exp__h427189,
out_f_exp__h472884,
x__h613033;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313,
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083,
x__h181698,
x__h711438;
wire [4 : 0] IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306,
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965,
checkForException___d13008,
checkForException___d13698,
fflags__h727255,
fflags__h729891,
fflags__h732495,
old_fflags__h731983,
po_fflags__h727241,
po_fflags__h729877,
r1__read__h614599,
res_fflags__h337869,
res_fflags__h383571,
res_fflags__h429266,
rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393,
rs1__h655326,
x__h153724,
x__h157271,
x__h160087,
x__h287278,
y_avValue_fst__h729252,
y_avValue_fst__h732400,
y_avValue_fst__h732432;
wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851,
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853,
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855,
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1857,
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1859,
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1861,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13198,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13199,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13200,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13201,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13202,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13203,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13204,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13205,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13206,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13207,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13208,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13209,
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210,
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243,
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795,
IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283,
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836,
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
cause_code__h708463,
vm_mode_reg__read__h614202;
wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
_theResult_____2__h296520,
dcsr_cause__h707982,
next_deqP___1__h296799,
v__h295940,
v__h296171,
x__h302150,
x_decodeInfo_frm__h655010;
wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670,
IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139,
IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74,
IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99,
IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179,
IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29,
IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109,
IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39,
IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156,
IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64,
IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135,
IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66,
IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142,
IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79,
IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175,
IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101,
IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182,
IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31,
IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114,
IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152,
IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44,
IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159,
guard__h346094,
guard__h354803,
guard__h363733,
guard__h372569,
guard__h391793,
guard__h400500,
guard__h409430,
guard__h418266,
guard__h437488,
guard__h446195,
guard__h455125,
guard__h463961,
guard__h493566,
guard__h502878,
guard__h511947,
guard__h532419,
guard__h541731,
guard__h550800,
guard__h571723,
guard__h581035,
guard__h590104,
prv__h734164,
prv__h734208,
r1__read_BITS_13_TO_12___h655195,
sbIdx__h157150,
v__h603882,
v__h603892,
v__h604527,
x__h721573,
x__h732759,
x_prv__h711506,
x_prv__h722029,
y_avValue_snd_snd_snd_fst__h729727,
y_avValue_snd_snd_snd_fst__h732569,
y_avValue_snd_snd_snd_fst__h732605;
wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934,
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052,
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13756,
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13793,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12237,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12238,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12239,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12262,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12263,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12264,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11377,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11378,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11379,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11402,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11403,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11404,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8241,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8242,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8243,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8265,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8266,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8267,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8289,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8290,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8291,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1603,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1604,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1605,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1627,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1628,
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103,
IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13908,
IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13916,
IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13831,
IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13915,
IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12247,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11353,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11387,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8217,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8274,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6493,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6530,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6594,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6605,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6621,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6634,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5101,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5138,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5202,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5213,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5229,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5242,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7885,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7922,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7986,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7997,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8013,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8026,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8430,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2104,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2107,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2047,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2049,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2106,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2108,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2704,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1800,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1804,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1808,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1812,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1816,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1820,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1824,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1828,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1832,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1836,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1840,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1844,
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1848,
IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1579,
IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612,
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750,
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743,
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728,
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656,
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649,
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634,
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558,
IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435,
IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13833,
IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13905,
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13954,
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14084,
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339,
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783,
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46,
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201,
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642,
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491,
IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6641,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033,
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344,
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13422,
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725,
NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286,
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484,
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614,
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621,
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684,
NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995,
NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229,
NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257,
NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369,
NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207,
NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595,
NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2526,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3078,
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127,
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3183,
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2123,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2533,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2535,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2578,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2581,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2598,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2605,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2646,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2655,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2677,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3355,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3451,
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883,
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1927,
NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755,
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717,
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3772,
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623,
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3678,
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474,
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024,
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547,
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589,
NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082,
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337,
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420,
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723,
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13527,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13814,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13869,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13887,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14036,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14090,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14196,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14252,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253,
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14283,
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331,
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466,
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746,
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752,
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13913,
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097,
NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13477,
NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772,
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13500,
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13739,
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13856,
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205,
NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14202,
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431,
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452,
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823,
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844,
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091,
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390,
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325,
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140,
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161,
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241,
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262,
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734,
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755,
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593,
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614,
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13761,
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13837,
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d14184,
NOT_regRenamingTable_rename_1_canRename__3530__ETC___d13801,
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102,
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13427,
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13736,
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13878,
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13896,
NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345,
NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645,
NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983,
NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342,
NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14007,
NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14074,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657,
_0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928,
_0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829,
_0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14020,
_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705,
_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5209,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5236,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6576,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6601,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6628,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7968,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7993,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8020,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242,
_dfoo12,
_dfoo16,
_dfoo18,
_dfoo2,
_dfoo20,
_dfoo24,
_dfoo26,
_dfoo32,
_dfoo7,
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset,
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset,
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
_dor1coreFix_memExe_bypassWire_2$EN_wset,
_dor1coreFix_memExe_bypassWire_3$EN_wset,
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset,
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset,
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put,
_dor1rf$EN_write_0_wr,
_dor1rf$EN_write_1_wr,
_dor1sbAggr$EN_setReady_3_put,
_dor1sbCons$EN_setReady_0_put,
_dor1sbCons$EN_setReady_1_put,
_theResult_____2__h304516,
_theResult_____2__h310510,
_theResult_____2__h318364,
_theResult_____2__h328708,
_theResult_____2__h331933,
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644,
coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205,
coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244,
coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218,
coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250,
coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226,
coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254,
coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267,
coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680,
coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444,
coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345,
coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384,
coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358,
coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390,
coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366,
coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394,
coreFix_aluExe_1_dispToRegQ_first__1322_BIT_13_ETC___d11407,
coreFix_aluExe_1_exeToFinQ_RDY_first__1967_AND_ETC___d12007,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281,
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6664,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8056,
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852,
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888,
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936,
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978,
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020,
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14027,
coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571,
coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609,
coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584,
coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615,
coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592,
coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2577,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3170,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2531,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2619,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2649,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2805,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2814,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3341,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3437,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1911,
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726,
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727,
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731,
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734,
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735,
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3759,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574,
coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646,
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045,
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502,
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791,
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707,
csrf_prv_reg_read__2787_ULE_1___d14685,
csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040,
csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13876,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13894,
f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880,
fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078,
fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14018,
fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100,
fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176,
fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14088,
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14024,
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14031,
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14053,
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14065,
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14296,
fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14152,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13844,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13956,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13962,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13979,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998,
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14014,
fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13509,
fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13835,
fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13973,
fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13985,
guard__h364331,
guard__h410028,
guard__h455723,
guard__h503476,
guard__h542329,
guard__h581633,
idx__h685368,
k__h669623,
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444,
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836,
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312,
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153,
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14092,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14094,
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747,
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606,
msip__h76121,
next_deqP___1__h304795,
next_deqP___1__h311076,
next_deqP___1__h318930,
next_deqP___1__h328987,
next_deqP___1__h332212,
r1__read_BIT_20___h655891,
regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941,
regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13493,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13823,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13970,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14112,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14118,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146,
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14294,
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738,
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13880,
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13898,
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204,
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14248,
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068,
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299,
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13759,
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13799,
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840,
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920,
rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716,
rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988,
rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309,
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294,
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295,
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632,
tsr_val__h725552,
tvm_val__h725554,
v__h299285,
v__h299803,
v__h309799,
v__h310030,
v__h313675,
v__h313906,
v__h328276,
v__h328507,
v__h331501,
v__h331732,
value_BIT_23___h494224,
x__h603383;
// action method coreReq_start
assign RDY_coreReq_start = 1'd1 ;
assign CAN_FIRE_coreReq_start = 1'd1 ;
assign WILL_FIRE_coreReq_start = EN_coreReq_start ;
// action method coreReq_perfReq
assign RDY_coreReq_perfReq = perfReqQ$FULL_N ;
assign CAN_FIRE_coreReq_perfReq = perfReqQ$FULL_N ;
assign WILL_FIRE_coreReq_perfReq = EN_coreReq_perfReq ;
// actionvalue method coreIndInv_perfResp
assign coreIndInv_perfResp = { perfReqQ$D_OUT, 64'd0 } ;
assign RDY_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_perfResp = EN_coreIndInv_perfResp ;
// action method coreIndInv_terminate
assign RDY_coreIndInv_terminate = csrf_terminate_module_terminateQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_terminate =
csrf_terminate_module_terminateQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_terminate = EN_coreIndInv_terminate ;
// value method dCacheToParent_rsToP_notEmpty
assign dCacheToParent_rsToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign RDY_dCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rsToP_deq
assign RDY_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rsToP_deq = EN_dCacheToParent_rsToP_deq ;
// value method dCacheToParent_rsToP_first
assign dCacheToParent_rsToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057 } ;
assign RDY_dCacheToParent_rsToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
// value method dCacheToParent_rqToP_notEmpty
assign dCacheToParent_rqToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign RDY_dCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rqToP_deq
assign RDY_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rqToP_deq = EN_dCacheToParent_rqToP_deq ;
// value method dCacheToParent_rqToP_first
assign dCacheToParent_rqToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083 } ;
assign RDY_dCacheToParent_rqToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
// value method dCacheToParent_fromP_notFull
assign dCacheToParent_fromP_notFull =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign RDY_dCacheToParent_fromP_notFull = 1'd1 ;
// action method dCacheToParent_fromP_enq
assign RDY_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign CAN_FIRE_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign WILL_FIRE_dCacheToParent_fromP_enq = EN_dCacheToParent_fromP_enq ;
// value method iCacheToParent_rsToP_notEmpty
assign iCacheToParent_rsToP_notEmpty =
fetchStage$iMemIfc_to_parent_rsToP_notEmpty ;
assign RDY_iCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rsToP_deq
assign RDY_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign CAN_FIRE_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign WILL_FIRE_iCacheToParent_rsToP_deq = EN_iCacheToParent_rsToP_deq ;
// value method iCacheToParent_rsToP_first
assign iCacheToParent_rsToP_first =
fetchStage$iMemIfc_to_parent_rsToP_first ;
assign RDY_iCacheToParent_rsToP_first =
fetchStage$RDY_iMemIfc_to_parent_rsToP_first ;
// value method iCacheToParent_rqToP_notEmpty
assign iCacheToParent_rqToP_notEmpty =
fetchStage$iMemIfc_to_parent_rqToP_notEmpty ;
assign RDY_iCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rqToP_deq
assign RDY_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign CAN_FIRE_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign WILL_FIRE_iCacheToParent_rqToP_deq = EN_iCacheToParent_rqToP_deq ;
// value method iCacheToParent_rqToP_first
assign iCacheToParent_rqToP_first =
fetchStage$iMemIfc_to_parent_rqToP_first ;
assign RDY_iCacheToParent_rqToP_first =
fetchStage$RDY_iMemIfc_to_parent_rqToP_first ;
// value method iCacheToParent_fromP_notFull
assign iCacheToParent_fromP_notFull =
fetchStage$iMemIfc_to_parent_fromP_notFull ;
assign RDY_iCacheToParent_fromP_notFull = 1'd1 ;
// action method iCacheToParent_fromP_enq
assign RDY_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign CAN_FIRE_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign WILL_FIRE_iCacheToParent_fromP_enq = EN_iCacheToParent_fromP_enq ;
// value method tlbToMem_memReq_notEmpty
assign tlbToMem_memReq_notEmpty = l2Tlb$toMem_memReq_notEmpty ;
assign RDY_tlbToMem_memReq_notEmpty = 1'd1 ;
// action method tlbToMem_memReq_deq
assign RDY_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign CAN_FIRE_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign WILL_FIRE_tlbToMem_memReq_deq = EN_tlbToMem_memReq_deq ;
// value method tlbToMem_memReq_first
assign tlbToMem_memReq_first = l2Tlb$toMem_memReq_first ;
assign RDY_tlbToMem_memReq_first = l2Tlb$RDY_toMem_memReq_first ;
// value method tlbToMem_respLd_notFull
assign tlbToMem_respLd_notFull = l2Tlb$toMem_respLd_notFull ;
assign RDY_tlbToMem_respLd_notFull = 1'd1 ;
// action method tlbToMem_respLd_enq
assign RDY_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign CAN_FIRE_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign WILL_FIRE_tlbToMem_respLd_enq = EN_tlbToMem_respLd_enq ;
// value method mmioToPlatform_cRq_notEmpty
assign mmioToPlatform_cRq_notEmpty = !mmio_cRqQ_empty ;
assign RDY_mmioToPlatform_cRq_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRq_deq
assign RDY_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRq_deq = EN_mmioToPlatform_cRq_deq ;
// value method mmioToPlatform_cRq_first
assign mmioToPlatform_cRq_first =
{ mmio_cRqQ_data_0[141:78],
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
mmio_cRqQ_data_0[71:0] } ;
assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ;
// value method mmioToPlatform_pRs_notFull
assign mmioToPlatform_pRs_notFull = !mmio_pRsQ_full ;
assign RDY_mmioToPlatform_pRs_notFull = 1'd1 ;
// action method mmioToPlatform_pRs_enq
assign RDY_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign CAN_FIRE_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign WILL_FIRE_mmioToPlatform_pRs_enq = EN_mmioToPlatform_pRs_enq ;
// value method mmioToPlatform_pRq_notFull
assign mmioToPlatform_pRq_notFull = !mmio_pRqQ_full ;
assign RDY_mmioToPlatform_pRq_notFull = 1'd1 ;
// action method mmioToPlatform_pRq_enq
assign RDY_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign CAN_FIRE_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign WILL_FIRE_mmioToPlatform_pRq_enq = EN_mmioToPlatform_pRq_enq ;
// value method mmioToPlatform_cRs_notEmpty
assign mmioToPlatform_cRs_notEmpty = !mmio_cRsQ_empty ;
assign RDY_mmioToPlatform_cRs_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRs_deq
assign RDY_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRs_deq = EN_mmioToPlatform_cRs_deq ;
// value method mmioToPlatform_cRs_first
assign mmioToPlatform_cRs_first = mmio_cRsQ_data_0 ;
assign RDY_mmioToPlatform_cRs_first = !mmio_cRsQ_empty ;
// action method mmioToPlatform_setTime
assign RDY_mmioToPlatform_setTime = 1'd1 ;
assign CAN_FIRE_mmioToPlatform_setTime = 1'd1 ;
assign WILL_FIRE_mmioToPlatform_setTime = EN_mmioToPlatform_setTime ;
// actionvalue method sendDoStats
assign sendDoStats = csrf_stats_module_writeQ$D_OUT ;
assign RDY_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign CAN_FIRE_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign WILL_FIRE_sendDoStats = EN_sendDoStats ;
// action method recvDoStats
assign RDY_recvDoStats = 1'd1 ;
assign CAN_FIRE_recvDoStats = 1'd1 ;
assign WILL_FIRE_recvDoStats = EN_recvDoStats ;
// actionvalue method deadlock_dCacheCRqStuck_get
assign deadlock_dCacheCRqStuck_get = 73'h0AAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCacheCRqStuck_get =
EN_deadlock_dCacheCRqStuck_get ;
// actionvalue method deadlock_dCachePRqStuck_get
assign deadlock_dCachePRqStuck_get = 68'hAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCachePRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCachePRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCachePRqStuck_get =
EN_deadlock_dCachePRqStuck_get ;
// actionvalue method deadlock_iCacheCRqStuck_get
assign deadlock_iCacheCRqStuck_get = fetchStage$iMemIfc_cRqStuck_get ;
assign RDY_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign CAN_FIRE_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign WILL_FIRE_deadlock_iCacheCRqStuck_get =
EN_deadlock_iCacheCRqStuck_get ;
// actionvalue method deadlock_iCachePRqStuck_get
assign deadlock_iCachePRqStuck_get = fetchStage$iMemIfc_pRqStuck_get ;
assign RDY_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign CAN_FIRE_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign WILL_FIRE_deadlock_iCachePRqStuck_get =
EN_deadlock_iCachePRqStuck_get ;
// actionvalue method deadlock_renameInstStuck_get
assign deadlock_renameInstStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameInstStuck_get =
EN_deadlock_renameInstStuck_get ;
// actionvalue method deadlock_renameCorrectPathStuck_get
assign deadlock_renameCorrectPathStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameCorrectPathStuck_get =
EN_deadlock_renameCorrectPathStuck_get ;
// actionvalue method deadlock_commitInstStuck_get
assign deadlock_commitInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitInstStuck_get =
EN_deadlock_commitInstStuck_get ;
// actionvalue method deadlock_commitUserInstStuck_get
assign deadlock_commitUserInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitUserInstStuck_get =
EN_deadlock_commitUserInstStuck_get ;
// action method deadlock_checkStarted_get
assign RDY_deadlock_checkStarted_get = 1'd0 ;
assign CAN_FIRE_deadlock_checkStarted_get = 1'd0 ;
assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ;
// actionvalue method renameDebug_renameErr_get
assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_renameDebug_renameErr_get = 1'd0 ;
assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ;
assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ;
// action method setMEIP
assign RDY_setMEIP = 1'd1 ;
assign CAN_FIRE_setMEIP = 1'd1 ;
assign WILL_FIRE_setMEIP = EN_setMEIP ;
// action method setSEIP
assign RDY_setSEIP = 1'd1 ;
assign CAN_FIRE_setSEIP = 1'd1 ;
assign WILL_FIRE_setSEIP = EN_setSEIP ;
// action method hart0_run_halt_server_request_put
assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
assign WILL_FIRE_hart0_run_halt_server_request_put =
EN_hart0_run_halt_server_request_put ;
// actionvalue method hart0_run_halt_server_response_get
assign hart0_run_halt_server_response_get = f_run_halt_rsps$D_OUT ;
assign RDY_hart0_run_halt_server_response_get = f_run_halt_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_run_halt_server_response_get =
f_run_halt_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_run_halt_server_response_get =
EN_hart0_run_halt_server_response_get ;
// action method hart0_gpr_mem_server_request_put
assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_gpr_mem_server_request_put =
EN_hart0_gpr_mem_server_request_put ;
// actionvalue method hart0_gpr_mem_server_response_get
assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ;
assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_gpr_mem_server_response_get =
EN_hart0_gpr_mem_server_response_get ;
// action method hart0_fpr_mem_server_request_put
assign RDY_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_fpr_mem_server_request_put =
EN_hart0_fpr_mem_server_request_put ;
// actionvalue method hart0_fpr_mem_server_response_get
assign hart0_fpr_mem_server_response_get = f_fpr_rsps$D_OUT ;
assign RDY_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_fpr_mem_server_response_get =
EN_hart0_fpr_mem_server_response_get ;
// action method hart0_csr_mem_server_request_put
assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign WILL_FIRE_hart0_csr_mem_server_request_put =
EN_hart0_csr_mem_server_request_put ;
// actionvalue method hart0_csr_mem_server_response_get
assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ;
assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_csr_mem_server_response_get =
EN_hart0_csr_mem_server_response_get ;
// actionvalue method v_to_TV_0_get
assign v_to_TV_0_get =
{ v_f_to_TV_0$D_OUT[784:476],
CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5,
v_f_to_TV_0$D_OUT[463:462],
v_f_to_TV_0$D_OUT[462] ?
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 :
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7,
v_f_to_TV_0$D_OUT[457:394],
CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8,
v_f_to_TV_0$D_OUT[391:0] } ;
assign RDY_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
assign CAN_FIRE_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
assign WILL_FIRE_v_to_TV_0_get = EN_v_to_TV_0_get ;
// actionvalue method v_to_TV_1_get
assign v_to_TV_1_get =
{ v_f_to_TV_1$D_OUT[784:476],
CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1,
v_f_to_TV_1$D_OUT[463:462],
v_f_to_TV_1$D_OUT[462] ?
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 :
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3,
v_f_to_TV_1$D_OUT[457:394],
CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4,
v_f_to_TV_1$D_OUT[391:0] } ;
assign RDY_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
assign CAN_FIRE_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
assign WILL_FIRE_v_to_TV_1_get = EN_v_to_TV_1_get ;
// submodule commitStage_f_rob_data
FIFO2 #(.width(32'd426),
.guarded(32'd1)) commitStage_f_rob_data(.RST(RST_N),
.CLK(CLK),
.D_IN(commitStage_f_rob_data$D_IN),
.ENQ(commitStage_f_rob_data$ENQ),
.DEQ(commitStage_f_rob_data$DEQ),
.CLR(commitStage_f_rob_data$CLR),
.D_OUT(commitStage_f_rob_data$D_OUT),
.FULL_N(commitStage_f_rob_data$FULL_N),
.EMPTY_N(commitStage_f_rob_data$EMPTY_N));
// submodule coreFix_aluExe_0_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_0_dispToRegQ$first),
.RDY_first(coreFix_aluExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_0_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_0_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_0_exeToFinQ$first),
.RDY_first(coreFix_aluExe_0_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_regToExeQ$RDY_deq),
.first(coreFix_aluExe_0_regToExeQ$first),
.RDY_first(coreFix_aluExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_rsAlu
mkReservationStationAlu coreFix_aluExe_0_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_0_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_0_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_0_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_0_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_0_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_0_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_0_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_0_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_0_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_0_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_0_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_0_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_0_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_1_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_1_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_1_dispToRegQ$first),
.RDY_first(coreFix_aluExe_1_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_1_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_1_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_1_exeToFinQ$first),
.RDY_first(coreFix_aluExe_1_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_1_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_1_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_regToExeQ$RDY_deq),
.first(coreFix_aluExe_1_regToExeQ$first),
.RDY_first(coreFix_aluExe_1_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_rsAlu
mkReservationStationAlu coreFix_aluExe_1_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_1_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_1_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_1_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_1_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_1_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_1_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_1_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_1_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_1_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_1_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_1_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_1_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_1_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
mkFpuMulDivDispToRegFifo coreFix_fpuMulDivExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_dispToRegQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
mkDoubleDiv coreFix_fpuMulDivExe_0_fpuExec_double_div(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
mkDoubleFMA coreFix_fpuMulDivExe_0_fpuExec_double_fma(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
mkDoubleSqrt coreFix_fpuMulDivExe_0_fpuExec_double_sqrt(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
mkFmaExecQ coreFix_fpuMulDivExe_0_fpuExec_fmaQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
mkSimpleRespQ coreFix_fpuMulDivExe_0_fpuExec_simpleQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_sqrtQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
mkDivExecQ coreFix_fpuMulDivExe_0_mulDivExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
int_div_unsigned coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc(.aclk(CLK),
.s_axis_dividend_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata),
.s_axis_dividend_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser),
.s_axis_divisor_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata),
.s_axis_dividend_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid),
.s_axis_divisor_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid),
.m_axis_dout_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready),
.s_axis_dividend_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready),
.s_axis_divisor_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready),
.m_axis_dout_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid),
.m_axis_dout_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata),
.m_axis_dout_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
reset_guard coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg(.CLK(CLK),
.RST(RST_N),
.IS_READY(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
mkMulExecQ coreFix_fpuMulDivExe_0_mulDivExec_mulQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
int_mul_signed coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned(.CLK(CLK),
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A),
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B),
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
int_mul_signed_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned(.CLK(CLK),
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A),
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B),
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
int_mul_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned(.CLK(CLK),
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A),
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B),
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd0)) coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT),
.FULL_N(),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_regToExeQ
mkFpuMulDivRegToExeFifo coreFix_fpuMulDivExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_regToExeQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
mkReservationStationFpuMulDiv coreFix_fpuMulDivExe_0_rsFpuMulDiv(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x),
.setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put),
.setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put),
.setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put),
.setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put),
.setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put),
.setRobEnqTime_t(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq),
.EN_setRobEnqTime(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime),
.EN_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq),
.canEnq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData),
.RDY_dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData),
.RDY_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
mkDCRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_cRqMshr(.CLK(CLK),
.RST_N(RST_N),
.cRqTransfer_getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r),
.cRqTransfer_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n),
.pipelineResp_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n),
.pipelineResp_getSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_searchEndOfChain_addr(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr),
.pipelineResp_setData_d(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d),
.pipelineResp_setData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n),
.pipelineResp_setStateSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n),
.pipelineResp_setStateSlot_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot),
.pipelineResp_setStateSlot_state(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state),
.pipelineResp_setSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n),
.pipelineResp_setSucc_succ(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ),
.sendRqToP_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n),
.sendRqToP_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n),
.sendRsToP_cRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n),
.sendRsToP_cRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n),
.sendRsToP_cRq_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n),
.sendRsToP_cRq_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot),
.EN_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit),
.EN_sendRsToP_cRq_setWaitSt_setSlot_clearData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData),
.EN_pipelineResp_setStateSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot),
.EN_pipelineResp_setSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get),
.cRqTransfer_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq),
.RDY_cRqTransfer_getRq(),
.cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit),
.RDY_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit),
.sendRsToP_cRq_getState(),
.RDY_sendRsToP_cRq_getState(),
.sendRsToP_cRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq),
.RDY_sendRsToP_cRq_getRq(),
.sendRsToP_cRq_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot),
.RDY_sendRsToP_cRq_getSlot(),
.sendRsToP_cRq_getData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData),
.RDY_sendRsToP_cRq_getData(),
.RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData(),
.sendRqToP_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq),
.RDY_sendRqToP_getRq(),
.sendRqToP_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot),
.RDY_sendRqToP_getSlot(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry),
.pipelineResp_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState),
.RDY_pipelineResp_getState(),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getSlot(),
.RDY_pipelineResp_getSlot(),
.RDY_pipelineResp_setData(),
.RDY_pipelineResp_setStateSlot(),
.pipelineResp_getSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc),
.RDY_pipelineResp_getSucc(),
.RDY_pipelineResp_setSucc(),
.pipelineResp_searchEndOfChain(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain),
.RDY_pipelineResp_searchEndOfChain(),
.emptyForFlush(),
.RDY_emptyForFlush(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK),
.RST_N(RST_N),
.getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_setDone_setData_d(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d),
.pipelineResp_setDone_setData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n),
.sendRsToP_pRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n),
.sendRsToP_pRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n),
.sendRsToP_pRq_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n),
.EN_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit),
.EN_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setDone_setData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get),
.getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit),
.RDY_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit),
.sendRsToP_pRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq),
.RDY_sendRsToP_pRq_getRq(),
.sendRsToP_pRq_getData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData),
.RDY_sendRsToP_pRq_getData(),
.RDY_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getState(),
.RDY_pipelineResp_getState(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry),
.RDY_pipelineResp_setDone_setData(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
mkDPipeline coreFix_memExe_dMem_cache_m_banks_0_pipeline(.CLK(CLK),
.RST_N(RST_N),
.deqWrite_swapRq(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq),
.deqWrite_updateRep(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep),
.deqWrite_wrRam(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam),
.send_r(coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r),
.EN_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send),
.EN_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite),
.RDY_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send),
.first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first),
.RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first),
.RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
SizedFIFO #(.p1width(32'd3),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd12),
.p3cntr_width(32'd4),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dTlb
mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(coreFix_memExe_dTlb$perf_req_r),
.perf_setStatus_doStats(coreFix_memExe_dTlb$perf_setStatus_doStats),
.procReq_req(coreFix_memExe_dTlb$procReq_req),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag),
.toParent_ldTransRsFromP_enq_x(coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x),
.updateVMInfo_vm(coreFix_memExe_dTlb$updateVMInfo_vm),
.EN_flush(coreFix_memExe_dTlb$EN_flush),
.EN_updateVMInfo(coreFix_memExe_dTlb$EN_updateVMInfo),
.EN_procReq(coreFix_memExe_dTlb$EN_procReq),
.EN_deqProcResp(coreFix_memExe_dTlb$EN_deqProcResp),
.EN_toParent_rqToP_deq(coreFix_memExe_dTlb$EN_toParent_rqToP_deq),
.EN_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq),
.EN_toParent_flush_request_get(coreFix_memExe_dTlb$EN_toParent_flush_request_get),
.EN_toParent_flush_response_put(coreFix_memExe_dTlb$EN_toParent_flush_response_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation),
.EN_perf_setStatus(coreFix_memExe_dTlb$EN_perf_setStatus),
.EN_perf_req(coreFix_memExe_dTlb$EN_perf_req),
.EN_perf_resp(coreFix_memExe_dTlb$EN_perf_resp),
.flush_done(coreFix_memExe_dTlb$flush_done),
.RDY_flush_done(),
.RDY_flush(coreFix_memExe_dTlb$RDY_flush),
.RDY_updateVMInfo(),
.noPendingReq(coreFix_memExe_dTlb$noPendingReq),
.RDY_noPendingReq(),
.RDY_procReq(coreFix_memExe_dTlb$RDY_procReq),
.procResp(coreFix_memExe_dTlb$procResp),
.RDY_procResp(coreFix_memExe_dTlb$RDY_procResp),
.RDY_deqProcResp(coreFix_memExe_dTlb$RDY_deqProcResp),
.toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_deq(coreFix_memExe_dTlb$RDY_toParent_rqToP_deq),
.toParent_rqToP_first(coreFix_memExe_dTlb$toParent_rqToP_first),
.RDY_toParent_rqToP_first(coreFix_memExe_dTlb$RDY_toParent_rqToP_first),
.toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq),
.RDY_toParent_flush_request_get(coreFix_memExe_dTlb$RDY_toParent_flush_request_get),
.RDY_toParent_flush_response_put(coreFix_memExe_dTlb$RDY_toParent_flush_response_put),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule coreFix_memExe_dispToRegQ
mkMemDispToRegFifo coreFix_memExe_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_dispToRegQ$EN_enq),
.EN_deq(coreFix_memExe_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_memExe_dispToRegQ$RDY_deq),
.first(coreFix_memExe_dispToRegQ$first),
.RDY_first(coreFix_memExe_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_lsq
mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK),
.RST_N(RST_N),
.enqLd_dst(coreFix_memExe_lsq$enqLd_dst),
.enqLd_inst_tag(coreFix_memExe_lsq$enqLd_inst_tag),
.enqLd_mem_inst(coreFix_memExe_lsq$enqLd_mem_inst),
.enqLd_spec_bits(coreFix_memExe_lsq$enqLd_spec_bits),
.enqSt_dst(coreFix_memExe_lsq$enqSt_dst),
.enqSt_inst_tag(coreFix_memExe_lsq$enqSt_inst_tag),
.enqSt_mem_inst(coreFix_memExe_lsq$enqSt_mem_inst),
.enqSt_spec_bits(coreFix_memExe_lsq$enqSt_spec_bits),
.getHit_t(coreFix_memExe_lsq$getHit_t),
.getOrigBE_t(coreFix_memExe_lsq$getOrigBE_t),
.issueLd_lsqTag(coreFix_memExe_lsq$issueLd_lsqTag),
.issueLd_paddr(coreFix_memExe_lsq$issueLd_paddr),
.issueLd_sbRes(coreFix_memExe_lsq$issueLd_sbRes),
.issueLd_shiftedBE(coreFix_memExe_lsq$issueLd_shiftedBE),
.respLd_alignedData(coreFix_memExe_lsq$respLd_alignedData),
.respLd_t(coreFix_memExe_lsq$respLd_t),
.setAtCommit_0_put(coreFix_memExe_lsq$setAtCommit_0_put),
.setAtCommit_1_put(coreFix_memExe_lsq$setAtCommit_1_put),
.specUpdate_correctSpeculation_mask(coreFix_memExe_lsq$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag),
.updateAddr_fault(coreFix_memExe_lsq$updateAddr_fault),
.updateAddr_isMMIO(coreFix_memExe_lsq$updateAddr_isMMIO),
.updateAddr_lsqTag(coreFix_memExe_lsq$updateAddr_lsqTag),
.updateAddr_paddr(coreFix_memExe_lsq$updateAddr_paddr),
.updateAddr_shiftedBE(coreFix_memExe_lsq$updateAddr_shiftedBE),
.updateData_d(coreFix_memExe_lsq$updateData_d),
.updateData_t(coreFix_memExe_lsq$updateData_t),
.wakeupLdStalledBySB_sbIdx(coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx),
.EN_enqLd(coreFix_memExe_lsq$EN_enqLd),
.EN_enqSt(coreFix_memExe_lsq$EN_enqSt),
.EN_getHit(coreFix_memExe_lsq$EN_getHit),
.EN_updateData(coreFix_memExe_lsq$EN_updateData),
.EN_updateAddr(coreFix_memExe_lsq$EN_updateAddr),
.EN_issueLd(coreFix_memExe_lsq$EN_issueLd),
.EN_getIssueLd(coreFix_memExe_lsq$EN_getIssueLd),
.EN_respLd(coreFix_memExe_lsq$EN_respLd),
.EN_deqLd(coreFix_memExe_lsq$EN_deqLd),
.EN_deqSt(coreFix_memExe_lsq$EN_deqSt),
.EN_wakeupLdStalledBySB(coreFix_memExe_lsq$EN_wakeupLdStalledBySB),
.EN_setAtCommit_0_put(coreFix_memExe_lsq$EN_setAtCommit_0_put),
.EN_setAtCommit_1_put(coreFix_memExe_lsq$EN_setAtCommit_1_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_lsq$EN_specUpdate_correctSpeculation),
.enqLdTag(coreFix_memExe_lsq$enqLdTag),
.RDY_enqLdTag(),
.enqStTag(coreFix_memExe_lsq$enqStTag),
.RDY_enqStTag(),
.RDY_enqLd(coreFix_memExe_lsq$RDY_enqLd),
.RDY_enqSt(coreFix_memExe_lsq$RDY_enqSt),
.getOrigBE(coreFix_memExe_lsq$getOrigBE),
.RDY_getOrigBE(),
.getHit(coreFix_memExe_lsq$getHit),
.RDY_getHit(),
.RDY_updateData(),
.updateAddr(coreFix_memExe_lsq$updateAddr),
.RDY_updateAddr(),
.issueLd(coreFix_memExe_lsq$issueLd),
.RDY_issueLd(),
.getIssueLd(coreFix_memExe_lsq$getIssueLd),
.RDY_getIssueLd(coreFix_memExe_lsq$RDY_getIssueLd),
.respLd(coreFix_memExe_lsq$respLd),
.RDY_respLd(),
.firstLd(coreFix_memExe_lsq$firstLd),
.RDY_firstLd(coreFix_memExe_lsq$RDY_firstLd),
.RDY_deqLd(coreFix_memExe_lsq$RDY_deqLd),
.firstSt(coreFix_memExe_lsq$firstSt),
.RDY_firstSt(coreFix_memExe_lsq$RDY_firstSt),
.RDY_deqSt(coreFix_memExe_lsq$RDY_deqSt),
.RDY_wakeupLdStalledBySB(),
.stqEmpty(coreFix_memExe_lsq$stqEmpty),
.RDY_stqEmpty(),
.RDY_setAtCommit_0_put(),
.RDY_setAtCommit_1_put(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.stqFull_ehrPort0(),
.RDY_stqFull_ehrPort0(),
.ldqFull_ehrPort0(),
.RDY_ldqFull_ehrPort0(),
.noWrongPathLoads(coreFix_memExe_lsq$noWrongPathLoads),
.RDY_noWrongPathLoads());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_regToExeQ
mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_regToExeQ$EN_enq),
.EN_deq(coreFix_memExe_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_regToExeQ$RDY_enq),
.RDY_deq(coreFix_memExe_regToExeQ$RDY_deq),
.first(coreFix_memExe_regToExeQ$first),
.RDY_first(coreFix_memExe_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_rsMem
mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_rsMem$enq_x),
.setRegReady_0_put(coreFix_memExe_rsMem$setRegReady_0_put),
.setRegReady_1_put(coreFix_memExe_rsMem$setRegReady_1_put),
.setRegReady_2_put(coreFix_memExe_rsMem$setRegReady_2_put),
.setRegReady_3_put(coreFix_memExe_rsMem$setRegReady_3_put),
.setRegReady_4_put(coreFix_memExe_rsMem$setRegReady_4_put),
.setRobEnqTime_t(coreFix_memExe_rsMem$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_rsMem$EN_enq),
.EN_setRobEnqTime(coreFix_memExe_rsMem$EN_setRobEnqTime),
.EN_doDispatch(coreFix_memExe_rsMem$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_memExe_rsMem$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_memExe_rsMem$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_memExe_rsMem$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_memExe_rsMem$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_memExe_rsMem$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_rsMem$RDY_enq),
.canEnq(coreFix_memExe_rsMem$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_memExe_rsMem$dispatchData),
.RDY_dispatchData(coreFix_memExe_rsMem$RDY_dispatchData),
.RDY_doDispatch(coreFix_memExe_rsMem$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_stb
mkStoreBufferEhr coreFix_memExe_stb(.CLK(CLK),
.RST_N(RST_N),
.deq_idx(coreFix_memExe_stb$deq_idx),
.enq_be(coreFix_memExe_stb$enq_be),
.enq_data(coreFix_memExe_stb$enq_data),
.enq_idx(coreFix_memExe_stb$enq_idx),
.enq_paddr(coreFix_memExe_stb$enq_paddr),
.getEnqIndex_paddr(coreFix_memExe_stb$getEnqIndex_paddr),
.noMatchLdQ_be(coreFix_memExe_stb$noMatchLdQ_be),
.noMatchLdQ_paddr(coreFix_memExe_stb$noMatchLdQ_paddr),
.noMatchStQ_be(coreFix_memExe_stb$noMatchStQ_be),
.noMatchStQ_paddr(coreFix_memExe_stb$noMatchStQ_paddr),
.search_be(coreFix_memExe_stb$search_be),
.search_paddr(coreFix_memExe_stb$search_paddr),
.EN_enq(coreFix_memExe_stb$EN_enq),
.EN_deq(coreFix_memExe_stb$EN_deq),
.EN_issue(coreFix_memExe_stb$EN_issue),
.isEmpty(coreFix_memExe_stb$isEmpty),
.RDY_isEmpty(),
.getEnqIndex(coreFix_memExe_stb$getEnqIndex),
.RDY_getEnqIndex(),
.RDY_enq(coreFix_memExe_stb$RDY_enq),
.deq(coreFix_memExe_stb$deq),
.RDY_deq(coreFix_memExe_stb$RDY_deq),
.issue(coreFix_memExe_stb$issue),
.RDY_issue(coreFix_memExe_stb$RDY_issue),
.search(coreFix_memExe_stb$search),
.RDY_search(),
.noMatchLdQ(coreFix_memExe_stb$noMatchLdQ),
.RDY_noMatchLdQ(),
.noMatchStQ(coreFix_memExe_stb$noMatchStQ),
.RDY_noMatchStQ());
// submodule coreFix_trainBPQ_0
FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_0$D_IN),
.ENQ(coreFix_trainBPQ_0$ENQ),
.DEQ(coreFix_trainBPQ_0$DEQ),
.CLR(coreFix_trainBPQ_0$CLR),
.D_OUT(coreFix_trainBPQ_0$D_OUT),
.FULL_N(coreFix_trainBPQ_0$FULL_N),
.EMPTY_N(coreFix_trainBPQ_0$EMPTY_N));
// submodule coreFix_trainBPQ_1
FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_1$D_IN),
.ENQ(coreFix_trainBPQ_1$ENQ),
.DEQ(coreFix_trainBPQ_1$DEQ),
.CLR(coreFix_trainBPQ_1$CLR),
.D_OUT(coreFix_trainBPQ_1$D_OUT),
.FULL_N(coreFix_trainBPQ_1$FULL_N),
.EMPTY_N(coreFix_trainBPQ_1$EMPTY_N));
// submodule csrInstOrInterruptInflight_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_0$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT));
// submodule csrInstOrInterruptInflight_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_1$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_stats_module_writeQ
FIFO1 #(.width(32'd1),
.guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N),
.CLK(CLK),
.D_IN(csrf_stats_module_writeQ$D_IN),
.ENQ(csrf_stats_module_writeQ$ENQ),
.DEQ(csrf_stats_module_writeQ$DEQ),
.CLR(csrf_stats_module_writeQ$CLR),
.D_OUT(csrf_stats_module_writeQ$D_OUT),
.FULL_N(csrf_stats_module_writeQ$FULL_N),
.EMPTY_N(csrf_stats_module_writeQ$EMPTY_N));
// submodule csrf_terminate_module_terminateQ
FIFO10 #(.guarded(32'd1)) csrf_terminate_module_terminateQ(.RST(RST_N),
.CLK(CLK),
.ENQ(csrf_terminate_module_terminateQ$ENQ),
.DEQ(csrf_terminate_module_terminateQ$DEQ),
.CLR(csrf_terminate_module_terminateQ$CLR),
.FULL_N(csrf_terminate_module_terminateQ$FULL_N),
.EMPTY_N(csrf_terminate_module_terminateQ$EMPTY_N));
// submodule epochManager
mkEpochManager epochManager(.CLK(CLK),
.RST_N(RST_N),
.checkEpoch_0_check_e(epochManager$checkEpoch_0_check_e),
.checkEpoch_1_check_e(epochManager$checkEpoch_1_check_e),
.updatePrevEpoch_0_update_e(epochManager$updatePrevEpoch_0_update_e),
.updatePrevEpoch_1_update_e(epochManager$updatePrevEpoch_1_update_e),
.EN_updatePrevEpoch_0_update(epochManager$EN_updatePrevEpoch_0_update),
.EN_updatePrevEpoch_1_update(epochManager$EN_updatePrevEpoch_1_update),
.EN_incrementEpoch(epochManager$EN_incrementEpoch),
.checkEpoch_0_check(epochManager$checkEpoch_0_check),
.RDY_checkEpoch_0_check(),
.checkEpoch_1_check(epochManager$checkEpoch_1_check),
.RDY_checkEpoch_1_check(),
.RDY_updatePrevEpoch_0_update(),
.RDY_updatePrevEpoch_1_update(),
.getEpoch(),
.RDY_getEpoch(),
.RDY_incrementEpoch(epochManager$RDY_incrementEpoch),
.getEpochState(),
.RDY_getEpochState(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// submodule f_csr_reqs
FIFO1 #(.width(32'd77), .guarded(32'd1)) f_csr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_reqs$D_IN),
.ENQ(f_csr_reqs$ENQ),
.DEQ(f_csr_reqs$DEQ),
.CLR(f_csr_reqs$CLR),
.D_OUT(f_csr_reqs$D_OUT),
.FULL_N(f_csr_reqs$FULL_N),
.EMPTY_N(f_csr_reqs$EMPTY_N));
// submodule f_csr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_csr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_rsps$D_IN),
.ENQ(f_csr_rsps$ENQ),
.DEQ(f_csr_rsps$DEQ),
.CLR(f_csr_rsps$CLR),
.D_OUT(f_csr_rsps$D_OUT),
.FULL_N(f_csr_rsps$FULL_N),
.EMPTY_N(f_csr_rsps$EMPTY_N));
// submodule f_fpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_fpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_reqs$D_IN),
.ENQ(f_fpr_reqs$ENQ),
.DEQ(f_fpr_reqs$DEQ),
.CLR(f_fpr_reqs$CLR),
.D_OUT(f_fpr_reqs$D_OUT),
.FULL_N(f_fpr_reqs$FULL_N),
.EMPTY_N(f_fpr_reqs$EMPTY_N));
// submodule f_fpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_fpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_rsps$D_IN),
.ENQ(f_fpr_rsps$ENQ),
.DEQ(f_fpr_rsps$DEQ),
.CLR(f_fpr_rsps$CLR),
.D_OUT(f_fpr_rsps$D_OUT),
.FULL_N(f_fpr_rsps$FULL_N),
.EMPTY_N(f_fpr_rsps$EMPTY_N));
// submodule f_gpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_reqs$D_IN),
.ENQ(f_gpr_reqs$ENQ),
.DEQ(f_gpr_reqs$DEQ),
.CLR(f_gpr_reqs$CLR),
.D_OUT(f_gpr_reqs$D_OUT),
.FULL_N(f_gpr_reqs$FULL_N),
.EMPTY_N(f_gpr_reqs$EMPTY_N));
// submodule f_gpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_rsps$D_IN),
.ENQ(f_gpr_rsps$ENQ),
.DEQ(f_gpr_rsps$DEQ),
.CLR(f_gpr_rsps$CLR),
.D_OUT(f_gpr_rsps$D_OUT),
.FULL_N(f_gpr_rsps$FULL_N),
.EMPTY_N(f_gpr_rsps$EMPTY_N));
// submodule f_run_halt_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_reqs$D_IN),
.ENQ(f_run_halt_reqs$ENQ),
.DEQ(f_run_halt_reqs$DEQ),
.CLR(f_run_halt_reqs$CLR),
.D_OUT(f_run_halt_reqs$D_OUT),
.FULL_N(f_run_halt_reqs$FULL_N),
.EMPTY_N(f_run_halt_reqs$EMPTY_N));
// submodule f_run_halt_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_rsps$D_IN),
.ENQ(f_run_halt_rsps$ENQ),
.DEQ(f_run_halt_rsps$DEQ),
.CLR(f_run_halt_rsps$CLR),
.D_OUT(f_run_halt_rsps$D_OUT),
.FULL_N(f_run_halt_rsps$FULL_N),
.EMPTY_N(f_run_halt_rsps$EMPTY_N));
// submodule fetchStage
mkFetchStage fetchStage(.CLK(CLK),
.RST_N(RST_N),
.iMemIfc_perf_req_r(fetchStage$iMemIfc_perf_req_r),
.iMemIfc_perf_setStatus_doStats(fetchStage$iMemIfc_perf_setStatus_doStats),
.iMemIfc_to_parent_fromP_enq_x(fetchStage$iMemIfc_to_parent_fromP_enq_x),
.iMemIfc_to_proc_request_put(fetchStage$iMemIfc_to_proc_request_put),
.iTlbIfc_perf_req_r(fetchStage$iTlbIfc_perf_req_r),
.iTlbIfc_perf_setStatus_doStats(fetchStage$iTlbIfc_perf_setStatus_doStats),
.iTlbIfc_toParent_rsFromP_enq_x(fetchStage$iTlbIfc_toParent_rsFromP_enq_x),
.iTlbIfc_to_proc_request_put(fetchStage$iTlbIfc_to_proc_request_put),
.iTlbIfc_updateVMInfo_vm(fetchStage$iTlbIfc_updateVMInfo_vm),
.mmioIfc_instResp_enq_x(fetchStage$mmioIfc_instResp_enq_x),
.mmioIfc_setHtifAddrs_fromHost(fetchStage$mmioIfc_setHtifAddrs_fromHost),
.mmioIfc_setHtifAddrs_toHost(fetchStage$mmioIfc_setHtifAddrs_toHost),
.perf_req_r(fetchStage$perf_req_r),
.perf_setStatus_doStats(fetchStage$perf_setStatus_doStats),
.redirect_pc(fetchStage$redirect_pc),
.start_pc(fetchStage$start_pc),
.train_predictors_dpTrain(fetchStage$train_predictors_dpTrain),
.train_predictors_iType(fetchStage$train_predictors_iType),
.train_predictors_isCompressed(fetchStage$train_predictors_isCompressed),
.train_predictors_mispred(fetchStage$train_predictors_mispred),
.train_predictors_next_pc(fetchStage$train_predictors_next_pc),
.train_predictors_pc(fetchStage$train_predictors_pc),
.train_predictors_taken(fetchStage$train_predictors_taken),
.EN_pipelines_0_deq(fetchStage$EN_pipelines_0_deq),
.EN_pipelines_1_deq(fetchStage$EN_pipelines_1_deq),
.EN_iTlbIfc_flush(fetchStage$EN_iTlbIfc_flush),
.EN_iTlbIfc_updateVMInfo(fetchStage$EN_iTlbIfc_updateVMInfo),
.EN_iTlbIfc_to_proc_request_put(fetchStage$EN_iTlbIfc_to_proc_request_put),
.EN_iTlbIfc_to_proc_response_get(fetchStage$EN_iTlbIfc_to_proc_response_get),
.EN_iTlbIfc_toParent_rqToP_deq(fetchStage$EN_iTlbIfc_toParent_rqToP_deq),
.EN_iTlbIfc_toParent_rsFromP_enq(fetchStage$EN_iTlbIfc_toParent_rsFromP_enq),
.EN_iTlbIfc_toParent_flush_request_get(fetchStage$EN_iTlbIfc_toParent_flush_request_get),
.EN_iTlbIfc_toParent_flush_response_put(fetchStage$EN_iTlbIfc_toParent_flush_response_put),
.EN_iTlbIfc_perf_setStatus(fetchStage$EN_iTlbIfc_perf_setStatus),
.EN_iTlbIfc_perf_req(fetchStage$EN_iTlbIfc_perf_req),
.EN_iTlbIfc_perf_resp(fetchStage$EN_iTlbIfc_perf_resp),
.EN_iMemIfc_to_proc_request_put(fetchStage$EN_iMemIfc_to_proc_request_put),
.EN_iMemIfc_to_proc_response_get(fetchStage$EN_iMemIfc_to_proc_response_get),
.EN_iMemIfc_flush(fetchStage$EN_iMemIfc_flush),
.EN_iMemIfc_perf_setStatus(fetchStage$EN_iMemIfc_perf_setStatus),
.EN_iMemIfc_perf_req(fetchStage$EN_iMemIfc_perf_req),
.EN_iMemIfc_perf_resp(fetchStage$EN_iMemIfc_perf_resp),
.EN_iMemIfc_to_parent_rsToP_deq(fetchStage$EN_iMemIfc_to_parent_rsToP_deq),
.EN_iMemIfc_to_parent_rqToP_deq(fetchStage$EN_iMemIfc_to_parent_rqToP_deq),
.EN_iMemIfc_to_parent_fromP_enq(fetchStage$EN_iMemIfc_to_parent_fromP_enq),
.EN_iMemIfc_cRqStuck_get(fetchStage$EN_iMemIfc_cRqStuck_get),
.EN_iMemIfc_pRqStuck_get(fetchStage$EN_iMemIfc_pRqStuck_get),
.EN_mmioIfc_instReq_deq(fetchStage$EN_mmioIfc_instReq_deq),
.EN_mmioIfc_instResp_enq(fetchStage$EN_mmioIfc_instResp_enq),
.EN_mmioIfc_setHtifAddrs(fetchStage$EN_mmioIfc_setHtifAddrs),
.EN_start(fetchStage$EN_start),
.EN_stop(fetchStage$EN_stop),
.EN_setWaitRedirect(fetchStage$EN_setWaitRedirect),
.EN_redirect(fetchStage$EN_redirect),
.EN_setWaitFlush(fetchStage$EN_setWaitFlush),
.EN_done_flushing(fetchStage$EN_done_flushing),
.EN_train_predictors(fetchStage$EN_train_predictors),
.EN_flush_predictors(fetchStage$EN_flush_predictors),
.EN_perf_setStatus(fetchStage$EN_perf_setStatus),
.EN_perf_req(fetchStage$EN_perf_req),
.EN_perf_resp(fetchStage$EN_perf_resp),
.pipelines_0_canDeq(fetchStage$pipelines_0_canDeq),
.RDY_pipelines_0_canDeq(),
.RDY_pipelines_0_deq(fetchStage$RDY_pipelines_0_deq),
.pipelines_0_first(fetchStage$pipelines_0_first),
.RDY_pipelines_0_first(fetchStage$RDY_pipelines_0_first),
.pipelines_1_canDeq(fetchStage$pipelines_1_canDeq),
.RDY_pipelines_1_canDeq(),
.RDY_pipelines_1_deq(fetchStage$RDY_pipelines_1_deq),
.pipelines_1_first(fetchStage$pipelines_1_first),
.RDY_pipelines_1_first(fetchStage$RDY_pipelines_1_first),
.iTlbIfc_flush_done(fetchStage$iTlbIfc_flush_done),
.RDY_iTlbIfc_flush_done(),
.RDY_iTlbIfc_flush(fetchStage$RDY_iTlbIfc_flush),
.RDY_iTlbIfc_updateVMInfo(),
.iTlbIfc_noPendingReq(fetchStage$iTlbIfc_noPendingReq),
.RDY_iTlbIfc_noPendingReq(),
.RDY_iTlbIfc_to_proc_request_put(),
.iTlbIfc_to_proc_response_get(),
.RDY_iTlbIfc_to_proc_response_get(),
.iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_deq(fetchStage$RDY_iTlbIfc_toParent_rqToP_deq),
.iTlbIfc_toParent_rqToP_first(fetchStage$iTlbIfc_toParent_rqToP_first),
.RDY_iTlbIfc_toParent_rqToP_first(fetchStage$RDY_iTlbIfc_toParent_rqToP_first),
.iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_enq(fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq),
.RDY_iTlbIfc_toParent_flush_request_get(fetchStage$RDY_iTlbIfc_toParent_flush_request_get),
.RDY_iTlbIfc_toParent_flush_response_put(fetchStage$RDY_iTlbIfc_toParent_flush_response_put),
.RDY_iTlbIfc_perf_setStatus(),
.RDY_iTlbIfc_perf_req(),
.iTlbIfc_perf_resp(),
.RDY_iTlbIfc_perf_resp(),
.iTlbIfc_perf_respValid(),
.RDY_iTlbIfc_perf_respValid(),
.RDY_iMemIfc_to_proc_request_put(),
.iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_flush(),
.iMemIfc_flush_done(fetchStage$iMemIfc_flush_done),
.RDY_iMemIfc_flush_done(),
.RDY_iMemIfc_perf_setStatus(),
.RDY_iMemIfc_perf_req(),
.iMemIfc_perf_resp(),
.RDY_iMemIfc_perf_resp(),
.iMemIfc_perf_respValid(),
.RDY_iMemIfc_perf_respValid(),
.iMemIfc_to_parent_rsToP_notEmpty(fetchStage$iMemIfc_to_parent_rsToP_notEmpty),
.RDY_iMemIfc_to_parent_rsToP_notEmpty(),
.RDY_iMemIfc_to_parent_rsToP_deq(fetchStage$RDY_iMemIfc_to_parent_rsToP_deq),
.iMemIfc_to_parent_rsToP_first(fetchStage$iMemIfc_to_parent_rsToP_first),
.RDY_iMemIfc_to_parent_rsToP_first(fetchStage$RDY_iMemIfc_to_parent_rsToP_first),
.iMemIfc_to_parent_rqToP_notEmpty(fetchStage$iMemIfc_to_parent_rqToP_notEmpty),
.RDY_iMemIfc_to_parent_rqToP_notEmpty(),
.RDY_iMemIfc_to_parent_rqToP_deq(fetchStage$RDY_iMemIfc_to_parent_rqToP_deq),
.iMemIfc_to_parent_rqToP_first(fetchStage$iMemIfc_to_parent_rqToP_first),
.RDY_iMemIfc_to_parent_rqToP_first(fetchStage$RDY_iMemIfc_to_parent_rqToP_first),
.iMemIfc_to_parent_fromP_notFull(fetchStage$iMemIfc_to_parent_fromP_notFull),
.RDY_iMemIfc_to_parent_fromP_notFull(),
.RDY_iMemIfc_to_parent_fromP_enq(fetchStage$RDY_iMemIfc_to_parent_fromP_enq),
.iMemIfc_cRqStuck_get(fetchStage$iMemIfc_cRqStuck_get),
.RDY_iMemIfc_cRqStuck_get(fetchStage$RDY_iMemIfc_cRqStuck_get),
.iMemIfc_pRqStuck_get(fetchStage$iMemIfc_pRqStuck_get),
.RDY_iMemIfc_pRqStuck_get(fetchStage$RDY_iMemIfc_pRqStuck_get),
.mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_deq(fetchStage$RDY_mmioIfc_instReq_deq),
.mmioIfc_instReq_first_fst(fetchStage$mmioIfc_instReq_first_fst),
.RDY_mmioIfc_instReq_first_fst(fetchStage$RDY_mmioIfc_instReq_first_fst),
.mmioIfc_instReq_first_snd(fetchStage$mmioIfc_instReq_first_snd),
.RDY_mmioIfc_instReq_first_snd(fetchStage$RDY_mmioIfc_instReq_first_snd),
.mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_enq(fetchStage$RDY_mmioIfc_instResp_enq),
.RDY_mmioIfc_setHtifAddrs(),
.RDY_start(),
.RDY_stop(),
.RDY_setWaitRedirect(),
.RDY_redirect(),
.RDY_setWaitFlush(),
.RDY_done_flushing(fetchStage$RDY_done_flushing),
.RDY_train_predictors(),
.emptyForFlush(fetchStage$emptyForFlush),
.RDY_emptyForFlush(),
.RDY_flush_predictors(),
.flush_predictors_done(fetchStage$flush_predictors_done),
.RDY_flush_predictors_done(),
.getFetchState(),
.RDY_getFetchState(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule l2Tlb
mkL2Tlb l2Tlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(l2Tlb$perf_req_r),
.perf_setStatus_doStats(l2Tlb$perf_setStatus_doStats),
.toChildren_rqFromC_put(l2Tlb$toChildren_rqFromC_put),
.toMem_respLd_enq_x(l2Tlb$toMem_respLd_enq_x),
.updateVMInfo_vmD(l2Tlb$updateVMInfo_vmD),
.updateVMInfo_vmI(l2Tlb$updateVMInfo_vmI),
.EN_updateVMInfo(l2Tlb$EN_updateVMInfo),
.EN_toChildren_rqFromC_put(l2Tlb$EN_toChildren_rqFromC_put),
.EN_toChildren_rsToC_deq(l2Tlb$EN_toChildren_rsToC_deq),
.EN_toChildren_iTlbReqFlush_put(l2Tlb$EN_toChildren_iTlbReqFlush_put),
.EN_toChildren_dTlbReqFlush_put(l2Tlb$EN_toChildren_dTlbReqFlush_put),
.EN_toChildren_flushDone_get(l2Tlb$EN_toChildren_flushDone_get),
.EN_toMem_memReq_deq(l2Tlb$EN_toMem_memReq_deq),
.EN_toMem_respLd_enq(l2Tlb$EN_toMem_respLd_enq),
.EN_perf_setStatus(l2Tlb$EN_perf_setStatus),
.EN_perf_req(l2Tlb$EN_perf_req),
.EN_perf_resp(l2Tlb$EN_perf_resp),
.RDY_updateVMInfo(),
.RDY_toChildren_rqFromC_put(l2Tlb$RDY_toChildren_rqFromC_put),
.toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_deq(l2Tlb$RDY_toChildren_rsToC_deq),
.toChildren_rsToC_first(l2Tlb$toChildren_rsToC_first),
.RDY_toChildren_rsToC_first(l2Tlb$RDY_toChildren_rsToC_first),
.RDY_toChildren_iTlbReqFlush_put(l2Tlb$RDY_toChildren_iTlbReqFlush_put),
.RDY_toChildren_dTlbReqFlush_put(l2Tlb$RDY_toChildren_dTlbReqFlush_put),
.RDY_toChildren_flushDone_get(l2Tlb$RDY_toChildren_flushDone_get),
.toMem_memReq_notEmpty(l2Tlb$toMem_memReq_notEmpty),
.RDY_toMem_memReq_notEmpty(),
.RDY_toMem_memReq_deq(l2Tlb$RDY_toMem_memReq_deq),
.toMem_memReq_first(l2Tlb$toMem_memReq_first),
.RDY_toMem_memReq_first(l2Tlb$RDY_toMem_memReq_first),
.toMem_respLd_notFull(l2Tlb$toMem_respLd_notFull),
.RDY_toMem_respLd_notFull(),
.RDY_toMem_respLd_enq(l2Tlb$RDY_toMem_respLd_enq),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule mmio_cRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataPendQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataRespQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT));
// submodule perfReqQ
FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N),
.CLK(CLK),
.D_IN(perfReqQ$D_IN),
.ENQ(perfReqQ$ENQ),
.DEQ(perfReqQ$DEQ),
.CLR(perfReqQ$CLR),
.D_OUT(perfReqQ$D_OUT),
.FULL_N(perfReqQ$FULL_N),
.EMPTY_N(perfReqQ$EMPTY_N));
// submodule regRenamingTable
mkRegRenamingTable regRenamingTable(.CLK(CLK),
.RST_N(RST_N),
.rename_0_claimRename_r(regRenamingTable$rename_0_claimRename_r),
.rename_0_claimRename_sb(regRenamingTable$rename_0_claimRename_sb),
.rename_0_getRename_r(regRenamingTable$rename_0_getRename_r),
.rename_1_claimRename_r(regRenamingTable$rename_1_claimRename_r),
.rename_1_claimRename_sb(regRenamingTable$rename_1_claimRename_sb),
.rename_1_getRename_r(regRenamingTable$rename_1_getRename_r),
.specUpdate_correctSpeculation_mask(regRenamingTable$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(regRenamingTable$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(regRenamingTable$specUpdate_incorrectSpeculation_kill_tag),
.EN_rename_0_claimRename(regRenamingTable$EN_rename_0_claimRename),
.EN_rename_1_claimRename(regRenamingTable$EN_rename_1_claimRename),
.EN_commit_0_commit(regRenamingTable$EN_commit_0_commit),
.EN_commit_1_commit(regRenamingTable$EN_commit_1_commit),
.EN_specUpdate_incorrectSpeculation(regRenamingTable$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(regRenamingTable$EN_specUpdate_correctSpeculation),
.rename_0_getRename(regRenamingTable$rename_0_getRename),
.RDY_rename_0_getRename(regRenamingTable$RDY_rename_0_getRename),
.RDY_rename_0_claimRename(regRenamingTable$RDY_rename_0_claimRename),
.rename_0_canRename(regRenamingTable$rename_0_canRename),
.RDY_rename_0_canRename(),
.rename_1_getRename(regRenamingTable$rename_1_getRename),
.RDY_rename_1_getRename(regRenamingTable$RDY_rename_1_getRename),
.RDY_rename_1_claimRename(regRenamingTable$RDY_rename_1_claimRename),
.rename_1_canRename(regRenamingTable$rename_1_canRename),
.RDY_rename_1_canRename(),
.RDY_commit_0_commit(regRenamingTable$RDY_commit_0_commit),
.commit_0_canCommit(),
.RDY_commit_0_canCommit(),
.RDY_commit_1_commit(regRenamingTable$RDY_commit_1_commit),
.commit_1_canCommit(),
.RDY_commit_1_canCommit(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule rf
mkRFileSynth rf(.CLK(CLK),
.RST_N(RST_N),
.read_0_rd1_rindx(rf$read_0_rd1_rindx),
.read_0_rd2_rindx(rf$read_0_rd2_rindx),
.read_0_rd3_rindx(rf$read_0_rd3_rindx),
.read_1_rd1_rindx(rf$read_1_rd1_rindx),
.read_1_rd2_rindx(rf$read_1_rd2_rindx),
.read_1_rd3_rindx(rf$read_1_rd3_rindx),
.read_2_rd1_rindx(rf$read_2_rd1_rindx),
.read_2_rd2_rindx(rf$read_2_rd2_rindx),
.read_2_rd3_rindx(rf$read_2_rd3_rindx),
.read_3_rd1_rindx(rf$read_3_rd1_rindx),
.read_3_rd2_rindx(rf$read_3_rd2_rindx),
.read_3_rd3_rindx(rf$read_3_rd3_rindx),
.read_4_rd1_rindx(rf$read_4_rd1_rindx),
.read_4_rd2_rindx(rf$read_4_rd2_rindx),
.read_4_rd3_rindx(rf$read_4_rd3_rindx),
.write_0_wr_data(rf$write_0_wr_data),
.write_0_wr_rindx(rf$write_0_wr_rindx),
.write_1_wr_data(rf$write_1_wr_data),
.write_1_wr_rindx(rf$write_1_wr_rindx),
.write_2_wr_data(rf$write_2_wr_data),
.write_2_wr_rindx(rf$write_2_wr_rindx),
.write_3_wr_data(rf$write_3_wr_data),
.write_3_wr_rindx(rf$write_3_wr_rindx),
.write_4_wr_data(rf$write_4_wr_data),
.write_4_wr_rindx(rf$write_4_wr_rindx),
.EN_write_0_wr(rf$EN_write_0_wr),
.EN_write_1_wr(rf$EN_write_1_wr),
.EN_write_2_wr(rf$EN_write_2_wr),
.EN_write_3_wr(rf$EN_write_3_wr),
.EN_write_4_wr(rf$EN_write_4_wr),
.RDY_write_0_wr(),
.RDY_write_1_wr(),
.RDY_write_2_wr(),
.RDY_write_3_wr(),
.RDY_write_4_wr(),
.read_0_rd1(rf$read_0_rd1),
.RDY_read_0_rd1(),
.read_0_rd2(rf$read_0_rd2),
.RDY_read_0_rd2(),
.read_0_rd3(),
.RDY_read_0_rd3(),
.read_1_rd1(rf$read_1_rd1),
.RDY_read_1_rd1(),
.read_1_rd2(rf$read_1_rd2),
.RDY_read_1_rd2(),
.read_1_rd3(),
.RDY_read_1_rd3(),
.read_2_rd1(rf$read_2_rd1),
.RDY_read_2_rd1(),
.read_2_rd2(rf$read_2_rd2),
.RDY_read_2_rd2(),
.read_2_rd3(rf$read_2_rd3),
.RDY_read_2_rd3(),
.read_3_rd1(rf$read_3_rd1),
.RDY_read_3_rd1(),
.read_3_rd2(rf$read_3_rd2),
.RDY_read_3_rd2(),
.read_3_rd3(),
.RDY_read_3_rd3(),
.read_4_rd1(rf$read_4_rd1),
.RDY_read_4_rd1(),
.read_4_rd2(),
.RDY_read_4_rd2(),
.read_4_rd3(),
.RDY_read_4_rd3());
// submodule rob
mkReorderBufferSynth rob(.CLK(CLK),
.RST_N(RST_N),
.enqPort_0_enq_x(rob$enqPort_0_enq_x),
.enqPort_1_enq_x(rob$enqPort_1_enq_x),
.getOrigPC_0_get_x(rob$getOrigPC_0_get_x),
.getOrigPC_1_get_x(rob$getOrigPC_1_get_x),
.getOrigPC_2_get_x(rob$getOrigPC_2_get_x),
.getOrigPredPC_0_get_x(rob$getOrigPredPC_0_get_x),
.getOrigPredPC_1_get_x(rob$getOrigPredPC_1_get_x),
.getOrig_Inst_0_get_x(rob$getOrig_Inst_0_get_x),
.getOrig_Inst_1_get_x(rob$getOrig_Inst_1_get_x),
.setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause),
.setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed),
.setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x),
.setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf),
.setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData),
.setExecuted_doFinishAlu_0_set_dst_data(rob$setExecuted_doFinishAlu_0_set_dst_data),
.setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x),
.setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf),
.setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData),
.setExecuted_doFinishAlu_1_set_dst_data(rob$setExecuted_doFinishAlu_1_set_dst_data),
.setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x),
.setExecuted_doFinishFpuMulDiv_0_set_dst_data(rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data),
.setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags),
.setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x),
.setExecuted_doFinishMem_RegData_dst_data(rob$setExecuted_doFinishMem_RegData_dst_data),
.setExecuted_doFinishMem_RegData_x(rob$setExecuted_doFinishMem_RegData_x),
.setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit),
.setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done),
.setExecuted_doFinishMem_store_data(rob$setExecuted_doFinishMem_store_data),
.setExecuted_doFinishMem_store_data_BE(rob$setExecuted_doFinishMem_store_data_BE),
.setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr),
.setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x),
.setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x),
.specUpdate_correctSpeculation_mask(rob$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_inst_tag(rob$specUpdate_incorrectSpeculation_inst_tag),
.specUpdate_incorrectSpeculation_kill_all(rob$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_spec_tag(rob$specUpdate_incorrectSpeculation_spec_tag),
.EN_enqPort_0_enq(rob$EN_enqPort_0_enq),
.EN_enqPort_1_enq(rob$EN_enqPort_1_enq),
.EN_deqPort_0_deq(rob$EN_deqPort_0_deq),
.EN_deqPort_1_deq(rob$EN_deqPort_1_deq),
.EN_setLSQAtCommitNotified(rob$EN_setLSQAtCommitNotified),
.EN_setExecuted_deqLSQ(rob$EN_setExecuted_deqLSQ),
.EN_setExecuted_doFinishAlu_0_set(rob$EN_setExecuted_doFinishAlu_0_set),
.EN_setExecuted_doFinishAlu_1_set(rob$EN_setExecuted_doFinishAlu_1_set),
.EN_setExecuted_doFinishFpuMulDiv_0_set(rob$EN_setExecuted_doFinishFpuMulDiv_0_set),
.EN_setExecuted_doFinishMem(rob$EN_setExecuted_doFinishMem),
.EN_setExecuted_doFinishMem_RegData(rob$EN_setExecuted_doFinishMem_RegData),
.EN_specUpdate_incorrectSpeculation(rob$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(rob$EN_specUpdate_correctSpeculation),
.enqPort_0_canEnq(rob$enqPort_0_canEnq),
.RDY_enqPort_0_canEnq(),
.RDY_enqPort_0_enq(rob$RDY_enqPort_0_enq),
.enqPort_0_getEnqInstTag(rob$enqPort_0_getEnqInstTag),
.RDY_enqPort_0_getEnqInstTag(),
.enqPort_1_canEnq(rob$enqPort_1_canEnq),
.RDY_enqPort_1_canEnq(),
.RDY_enqPort_1_enq(rob$RDY_enqPort_1_enq),
.enqPort_1_getEnqInstTag(rob$enqPort_1_getEnqInstTag),
.RDY_enqPort_1_getEnqInstTag(),
.isEmpty(rob$isEmpty),
.RDY_isEmpty(),
.deqPort_0_canDeq(rob$deqPort_0_canDeq),
.RDY_deqPort_0_canDeq(),
.RDY_deqPort_0_deq(rob$RDY_deqPort_0_deq),
.deqPort_0_getDeqInstTag(rob$deqPort_0_getDeqInstTag),
.RDY_deqPort_0_getDeqInstTag(),
.deqPort_0_deq_data(rob$deqPort_0_deq_data),
.RDY_deqPort_0_deq_data(rob$RDY_deqPort_0_deq_data),
.deqPort_1_canDeq(rob$deqPort_1_canDeq),
.RDY_deqPort_1_canDeq(),
.RDY_deqPort_1_deq(rob$RDY_deqPort_1_deq),
.deqPort_1_getDeqInstTag(),
.RDY_deqPort_1_getDeqInstTag(),
.deqPort_1_deq_data(rob$deqPort_1_deq_data),
.RDY_deqPort_1_deq_data(rob$RDY_deqPort_1_deq_data),
.RDY_setLSQAtCommitNotified(rob$RDY_setLSQAtCommitNotified),
.RDY_setExecuted_deqLSQ(rob$RDY_setExecuted_deqLSQ),
.RDY_setExecuted_doFinishAlu_0_set(rob$RDY_setExecuted_doFinishAlu_0_set),
.RDY_setExecuted_doFinishAlu_1_set(rob$RDY_setExecuted_doFinishAlu_1_set),
.RDY_setExecuted_doFinishFpuMulDiv_0_set(rob$RDY_setExecuted_doFinishFpuMulDiv_0_set),
.RDY_setExecuted_doFinishMem(rob$RDY_setExecuted_doFinishMem),
.RDY_setExecuted_doFinishMem_RegData(),
.getOrigPC_0_get(rob$getOrigPC_0_get),
.RDY_getOrigPC_0_get(),
.getOrigPC_1_get(rob$getOrigPC_1_get),
.RDY_getOrigPC_1_get(),
.getOrigPC_2_get(),
.RDY_getOrigPC_2_get(),
.getOrigPredPC_0_get(rob$getOrigPredPC_0_get),
.RDY_getOrigPredPC_0_get(),
.getOrigPredPC_1_get(rob$getOrigPredPC_1_get),
.RDY_getOrigPredPC_1_get(),
.getOrig_Inst_0_get(rob$getOrig_Inst_0_get),
.RDY_getOrig_Inst_0_get(),
.getOrig_Inst_1_get(rob$getOrig_Inst_1_get),
.RDY_getOrig_Inst_1_get(),
.getEnqTime(rob$getEnqTime),
.RDY_getEnqTime(),
.isEmpty_ehrPort0(),
.RDY_isEmpty_ehrPort0(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule sbAggr
mkScoreboardAggr sbAggr(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbAggr$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbAggr$eagerLookup_1_get_r),
.setBusy_0_set_dst(sbAggr$setBusy_0_set_dst),
.setBusy_1_set_dst(sbAggr$setBusy_1_set_dst),
.setReady_0_put(sbAggr$setReady_0_put),
.setReady_1_put(sbAggr$setReady_1_put),
.setReady_2_put(sbAggr$setReady_2_put),
.setReady_3_put(sbAggr$setReady_3_put),
.setReady_4_put(sbAggr$setReady_4_put),
.EN_setBusy_0_set(sbAggr$EN_setBusy_0_set),
.EN_setBusy_1_set(sbAggr$EN_setBusy_1_set),
.EN_setReady_0_put(sbAggr$EN_setReady_0_put),
.EN_setReady_1_put(sbAggr$EN_setReady_1_put),
.EN_setReady_2_put(sbAggr$EN_setReady_2_put),
.EN_setReady_3_put(sbAggr$EN_setReady_3_put),
.EN_setReady_4_put(sbAggr$EN_setReady_4_put),
.eagerLookup_0_get(sbAggr$eagerLookup_0_get),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(sbAggr$eagerLookup_1_get),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.RDY_setReady_4_put());
// submodule sbCons
mkScoreboardCons sbCons(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbCons$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbCons$eagerLookup_1_get_r),
.lazyLookup_0_get_r(sbCons$lazyLookup_0_get_r),
.lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r),
.lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r),
.lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r),
.lazyLookup_4_get_r(sbCons$lazyLookup_4_get_r),
.setBusy_0_set_dst(sbCons$setBusy_0_set_dst),
.setBusy_1_set_dst(sbCons$setBusy_1_set_dst),
.setReady_0_put(sbCons$setReady_0_put),
.setReady_1_put(sbCons$setReady_1_put),
.setReady_2_put(sbCons$setReady_2_put),
.setReady_3_put(sbCons$setReady_3_put),
.setReady_4_put(sbCons$setReady_4_put),
.EN_setBusy_0_set(sbCons$EN_setBusy_0_set),
.EN_setBusy_1_set(sbCons$EN_setBusy_1_set),
.EN_setReady_0_put(sbCons$EN_setReady_0_put),
.EN_setReady_1_put(sbCons$EN_setReady_1_put),
.EN_setReady_2_put(sbCons$EN_setReady_2_put),
.EN_setReady_3_put(sbCons$EN_setReady_3_put),
.EN_setReady_4_put(sbCons$EN_setReady_4_put),
.eagerLookup_0_get(),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.RDY_setReady_4_put(),
.lazyLookup_0_get(sbCons$lazyLookup_0_get),
.RDY_lazyLookup_0_get(),
.lazyLookup_1_get(sbCons$lazyLookup_1_get),
.RDY_lazyLookup_1_get(),
.lazyLookup_2_get(sbCons$lazyLookup_2_get),
.RDY_lazyLookup_2_get(),
.lazyLookup_3_get(sbCons$lazyLookup_3_get),
.RDY_lazyLookup_3_get(),
.lazyLookup_4_get(),
.RDY_lazyLookup_4_get());
// submodule specTagManager
mkSpecTagManager specTagManager(.CLK(CLK),
.RST_N(RST_N),
.specUpdate_correctSpeculation_mask(specTagManager$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(specTagManager$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(specTagManager$specUpdate_incorrectSpeculation_kill_tag),
.EN_claimSpecTag(specTagManager$EN_claimSpecTag),
.EN_specUpdate_incorrectSpeculation(specTagManager$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(specTagManager$EN_specUpdate_correctSpeculation),
.currentSpecBits(specTagManager$currentSpecBits),
.RDY_currentSpecBits(),
.nextSpecTag(specTagManager$nextSpecTag),
.RDY_nextSpecTag(specTagManager$RDY_nextSpecTag),
.RDY_claimSpecTag(specTagManager$RDY_claimSpecTag),
.canClaim(specTagManager$canClaim),
.RDY_canClaim(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// submodule v_f_to_TV_0
FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N),
.CLK(CLK),
.D_IN(v_f_to_TV_0$D_IN),
.ENQ(v_f_to_TV_0$ENQ),
.DEQ(v_f_to_TV_0$DEQ),
.CLR(v_f_to_TV_0$CLR),
.D_OUT(v_f_to_TV_0$D_OUT),
.FULL_N(v_f_to_TV_0$FULL_N),
.EMPTY_N(v_f_to_TV_0$EMPTY_N));
// submodule v_f_to_TV_1
FIFO2 #(.width(32'd785), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N),
.CLK(CLK),
.D_IN(v_f_to_TV_1$D_IN),
.ENQ(v_f_to_TV_1$ENQ),
.DEQ(v_f_to_TV_1$DEQ),
.CLR(v_f_to_TV_1$CLR),
.D_OUT(v_f_to_TV_1$D_OUT),
.FULL_N(v_f_to_TV_1$FULL_N),
.EMPTY_N(v_f_to_TV_1$EMPTY_N));
// rule RL_rl_outOfReset
assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ;
assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ;
// rule RL_sendDTlbReq
assign CAN_FIRE_RL_sendDTlbReq =
coreFix_memExe_dTlb$RDY_toParent_rqToP_first &&
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq &&
l2Tlb$RDY_toChildren_rqFromC_put ;
assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ;
// rule RL_sendITlbReq
assign CAN_FIRE_RL_sendITlbReq =
l2Tlb$RDY_toChildren_rqFromC_put &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_first &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ;
assign WILL_FIRE_RL_sendITlbReq =
CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ;
// rule RL_sendRsToDTlb
assign CAN_FIRE_RL_sendRsToDTlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq &&
l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ;
// rule RL_sendRsToITlb
assign CAN_FIRE_RL_sendRsToITlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq &&
!l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ;
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
coreFix_memExe_dTlb$RDY_toParent_flush_request_get &&
l2Tlb$RDY_toChildren_dTlbReqFlush_put ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_mkConnectionGetPut_1
assign CAN_FIRE_RL_mkConnectionGetPut_1 =
l2Tlb$RDY_toChildren_iTlbReqFlush_put &&
fetchStage$RDY_iTlbIfc_toParent_flush_request_get ;
assign WILL_FIRE_RL_mkConnectionGetPut_1 =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
// rule RL_sendFlushDone
assign CAN_FIRE_RL_sendFlushDone =
coreFix_memExe_dTlb$RDY_toParent_flush_response_put &&
l2Tlb$RDY_toChildren_flushDone_get &&
fetchStage$RDY_iTlbIfc_toParent_flush_response_put ;
assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ;
// rule RL_sendRobEnqTime
assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ;
assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ;
// rule RL_setDoFlushCaches
assign CAN_FIRE_RL_setDoFlushCaches =
flush_caches && fetchStage$emptyForFlush &&
coreFix_memExe_lsq$noWrongPathLoads ;
assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ;
// rule RL_setDoFlushBrPred
assign CAN_FIRE_RL_setDoFlushBrPred =
flush_brpred && fetchStage$emptyForFlush ;
assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
// rule RL_readyToFetch
assign CAN_FIRE_RL_readyToFetch =
fetchStage$RDY_done_flushing &&
rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716 &&
!flush_brpred &&
fetchStage$iMemIfc_flush_done &&
fetchStage$flush_predictors_done ;
assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ;
// rule RL_flushCaches
assign CAN_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;
assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;
// rule RL_flushBrPred
assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
// rule RL_rl_debug_gpr_read
assign CAN_FIRE_RL_rl_debug_gpr_read =
regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_gpr_read = CAN_FIRE_RL_rl_debug_gpr_read ;
// rule RL_rl_debug_gpr_access_busy
assign CAN_FIRE_RL_rl_debug_gpr_access_busy =
f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_gpr_access_busy =
CAN_FIRE_RL_rl_debug_gpr_access_busy ;
// rule RL_rl_debug_fpr_read
assign CAN_FIRE_RL_rl_debug_fpr_read =
regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$EMPTY_N &&
!f_fpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_fpr_read = CAN_FIRE_RL_rl_debug_fpr_read ;
// rule RL_rl_debug_fpr_access_busy
assign CAN_FIRE_RL_rl_debug_fpr_access_busy =
f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_fpr_access_busy =
CAN_FIRE_RL_rl_debug_fpr_access_busy ;
// rule RL_rl_debug_csr_access_busy
assign CAN_FIRE_RL_rl_debug_csr_access_busy =
f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_csr_access_busy =
CAN_FIRE_RL_rl_debug_csr_access_busy ;
// rule RL_rl_debug_halt_req
assign CAN_FIRE_RL_rl_debug_halt_req =
f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] &&
rg_core_run_state == 2'd2 &&
!f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ;
// rule RL_rl_debug_halt_req_already_halted
assign CAN_FIRE_RL_rl_debug_halt_req_already_halted =
f_run_halt_reqs$EMPTY_N && rg_core_run_state != 2'd2 &&
!f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_halt_req_already_halted =
CAN_FIRE_RL_rl_debug_halt_req_already_halted ;
// rule RL_rl_debug_halted
assign CAN_FIRE_RL_rl_debug_halted =
f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ;
assign WILL_FIRE_RL_rl_debug_halted = CAN_FIRE_RL_rl_debug_halted ;
// rule RL_rl_debug_run_redundant
assign CAN_FIRE_RL_rl_debug_run_redundant =
f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N &&
rg_core_run_state == 2'd2 &&
f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_run_redundant =
CAN_FIRE_RL_rl_debug_run_redundant ;
// rule RL_csrf_minstret_ehr_setRead
assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
// rule RL_csrf_mcycle_ehr_setRead
assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
// rule RL_rl_debug_csr_read
assign CAN_FIRE_RL_rl_debug_csr_read =
f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_csr_reqs$D_OUT[76] ;
assign WILL_FIRE_RL_rl_debug_csr_read = CAN_FIRE_RL_rl_debug_csr_read ;
// rule RL_rl_debug_csr_write
assign CAN_FIRE_RL_rl_debug_csr_write =
f_csr_reqs$EMPTY_N &&
f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880 &&
rg_core_run_state == 2'd1 &&
f_csr_reqs$D_OUT[76] ;
assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ;
// rule RL_mmio_handlePRq
assign CAN_FIRE_RL_mmio_handlePRq =
!mmio_pRqQ_empty && !mmio_cRsQ_full &&
(!csrInstOrInterruptInflight_dummy2_0$Q_OUT ||
!csrInstOrInterruptInflight_dummy2_1$Q_OUT ||
!csrInstOrInterruptInflight_rl) ;
assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ;
// rule RL_mmio_sendDataReq
assign CAN_FIRE_RL_mmio_sendDataReq =
!mmio_dataReqQ_empty && !mmio_cRqQ_full ;
assign WILL_FIRE_RL_mmio_sendDataReq = CAN_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendInstReq
assign CAN_FIRE_RL_mmio_sendInstReq =
!mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd &&
fetchStage$RDY_mmioIfc_instReq_first_fst &&
fetchStage$RDY_mmioIfc_instReq_deq ;
assign WILL_FIRE_RL_mmio_sendInstReq =
CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendDataResp
assign CAN_FIRE_RL_mmio_sendDataResp =
!mmio_dataRespQ_full && !mmio_pRsQ_empty &&
mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ;
// rule RL_mmio_sendInstResp
assign CAN_FIRE_RL_mmio_sendInstResp =
!mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq &&
!mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ;
// rule RL_mmio_cRqQ_canonicalize
assign CAN_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_canonicalize
assign CAN_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_canonicalize
assign CAN_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_doFetchTrainBP
assign CAN_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_doFetchTrainBP_1
assign CAN_FIRE_RL_coreFix_doFetchTrainBP_1 = coreFix_trainBPQ_0$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP_1 =
coreFix_trainBPQ_0$EMPTY_N && !coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_memExe_doIssueSB
assign CAN_FIRE_RL_coreFix_memExe_doIssueSB =
(!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqStQ_full_rl) &&
coreFix_memExe_stb$RDY_issue ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueSB =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_lsq$firstLd[101] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchLdQ &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2704 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ;
// rule RL_renameStage_doRenaming_wrongPath
assign CAN_FIRE_RL_renameStage_doRenaming_wrongPath =
fetchStage$RDY_pipelines_0_first &&
(!fetchStage$pipelines_0_canDeq ||
epochManager$checkEpoch_0_check ||
fetchStage$RDY_pipelines_0_deq) &&
NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772 &&
!epochManager$checkEpoch_0_check ;
assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath =
CAN_FIRE_RL_renameStage_doRenaming_wrongPath ;
// rule RL_commitStage_doCommitTrap_flush
assign CAN_FIRE_RL_commitStage_doCommitTrap_flush =
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
commitStage_f_rob_data$FULL_N &&
(rob$deqPort_0_deq_data[12] ||
epochManager$RDY_incrementEpoch) &&
!commitStage_rg_run_state &&
!commitStage_commitTrap[165] &&
rob$deqPort_0_deq_data[167] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_flush =
CAN_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_rl_send_tv_reset
assign CAN_FIRE_RL_commitStage_rl_send_tv_reset =
v_f_to_TV_0$FULL_N && commitStage_rg_just_after_reset ;
assign WILL_FIRE_RL_commitStage_rl_send_tv_reset =
CAN_FIRE_RL_commitStage_rl_send_tv_reset ;
// rule RL_commitStage_doCommitTrap_handle
assign CAN_FIRE_RL_commitStage_doCommitTrap_handle =
commitStage_f_rob_data$EMPTY_N &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621 &&
(commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646) &&
!commitStage_rg_run_state &&
commitStage_commitTrap[165] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_handle =
CAN_FIRE_RL_commitStage_doCommitTrap_handle &&
!WILL_FIRE_RL_commitStage_rl_send_tv_reset &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_commitStage_doCommitKilledLd
assign CAN_FIRE_RL_commitStage_doCommitKilledLd =
epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data &&
rob$RDY_deqPort_0_deq &&
!commitStage_rg_run_state &&
!commitStage_commitTrap[165] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[18] ;
assign WILL_FIRE_RL_commitStage_doCommitKilledLd =
CAN_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_doCommitSystemInst
assign CAN_FIRE_RL_commitStage_doCommitSystemInst =
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988 &&
NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 &&
(rob$deqPort_0_deq_data[329:325] == 5'd0 ||
rob$deqPort_0_deq_data[329:325] == 5'd21 ||
rob$deqPort_0_deq_data[329:325] == 5'd17 ||
rob$deqPort_0_deq_data[329:325] == 5'd18 ||
rob$deqPort_0_deq_data[329:325] == 5'd13 ||
rob$deqPort_0_deq_data[329:325] == 5'd16 ||
rob$deqPort_0_deq_data[329:325] == 5'd15 ||
rob$deqPort_0_deq_data[329:325] == 5'd19 ||
rob$deqPort_0_deq_data[329:325] == 5'd20) ;
assign WILL_FIRE_RL_commitStage_doCommitSystemInst =
CAN_FIRE_RL_commitStage_doCommitSystemInst &&
!WILL_FIRE_RL_commitStage_rl_send_tv_reset &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_csr_write &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_csrf_incCycle
assign CAN_FIRE_RL_csrf_incCycle = 1'd1 ;
assign WILL_FIRE_RL_csrf_incCycle = 1'd1 ;
// rule RL_csrf_mcycle_ehr_data_canon
assign CAN_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
// rule RL_commitStage_notifyLSQCommit
assign CAN_FIRE_RL_commitStage_notifyLSQCommit =
rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data &&
!commitStage_commitTrap[165] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[25] &&
rob$deqPort_0_deq_data[15] &&
!rob$deqPort_0_deq_data[14] ;
assign WILL_FIRE_RL_commitStage_notifyLSQCommit =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
// rule RL_commitStage_doCommitNormalInst
assign CAN_FIRE_RL_commitStage_doCommitNormalInst =
rob$RDY_deqPort_0_deq_data &&
NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345 &&
NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 &&
rob$deqPort_0_deq_data[329:325] != 5'd0 &&
rob$deqPort_0_deq_data[329:325] != 5'd21 &&
rob$deqPort_0_deq_data[329:325] != 5'd17 &&
rob$deqPort_0_deq_data[329:325] != 5'd18 &&
rob$deqPort_0_deq_data[329:325] != 5'd13 &&
rob$deqPort_0_deq_data[329:325] != 5'd16 &&
rob$deqPort_0_deq_data[329:325] != 5'd15 &&
rob$deqPort_0_deq_data[329:325] != 5'd19 &&
rob$deqPort_0_deq_data[329:325] != 5'd20 ;
assign WILL_FIRE_RL_commitStage_doCommitNormalInst =
CAN_FIRE_RL_commitStage_doCommitNormalInst &&
!WILL_FIRE_RL_commitStage_rl_send_tv_reset ;
// rule RL_csrf_minstret_ehr_data_canon
assign CAN_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
// rule RL_coreFix_aluExe_1_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_1$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
!WILL_FIRE_RL_rl_debug_resume ;
// rule RL_coreFix_aluExe_0_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_0$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
!WILL_FIRE_RL_rl_debug_resume ;
// rule RL_coreFix_aluExe_0_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
!coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_aluExe_1_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
!coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ_RDY_first__1967_AND_ETC___d12007 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_aluExe_1_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu =
coreFix_aluExe_1_regToExeQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_enq &&
coreFix_aluExe_1_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu =
coreFix_aluExe_0_regToExeQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_enq &&
coreFix_aluExe_0_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
coreFix_aluExe_1_dispToRegQ$RDY_deq &&
coreFix_aluExe_1_regToExeQ$RDY_enq &&
coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_1_dispToRegQ_first__1322_BIT_13_ETC___d11407 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
coreFix_aluExe_0_dispToRegQ$RDY_deq &&
coreFix_aluExe_0_regToExeQ$RDY_enq &&
coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
coreFix_aluExe_0_dispToRegQ$RDY_enq &&
coreFix_aluExe_0_rsAlu$RDY_doDispatch &&
coreFix_aluExe_0_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
coreFix_aluExe_1_dispToRegQ$RDY_enq &&
coreFix_aluExe_1_rsAlu$RDY_doDispatch &&
coreFix_aluExe_1_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6664 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8056 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqLdQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_lsq$firstLd[7] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[101] &&
!coreFix_memExe_lsq$firstLd[16] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doFinishMem
assign CAN_FIRE_RL_coreFix_memExe_doFinishMem =
rob$RDY_setExecuted_doFinishMem &&
coreFix_memExe_dTlb$RDY_deqProcResp &&
coreFix_memExe_dTlb$RDY_procResp ;
assign WILL_FIRE_RL_coreFix_memExe_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
!coreFix_memExe_lsq$firstSt[77] &&
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1 ||
coreFix_memExe_lsq$firstSt[158:157] == 2'd2) &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchStQ &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd3 &&
coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_mmio_dataReqQ_canonicalize
assign CAN_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataReqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLrScAmoToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
(!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
!coreFix_memExe_reqLrScAmoQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_doIssueLdFromIssueQ
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
coreFix_memExe_lsq$RDY_getIssueLd &&
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474 ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doIssueLdFromUpdate
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474 &&
coreFix_memExe_issueLd$whas ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_lsq$firstSt[4] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_Fence
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd3 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_mmio_dataRespQ_canonicalize
assign CAN_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataRespQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_canonicalize
assign CAN_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataPendQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLdToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem =
(!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLdQ_empty_lat_0$whas ||
!coreFix_memExe_reqLdQ_empty_rl) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 ;
assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem =
CAN_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_sendStToMem
assign CAN_FIRE_RL_coreFix_memExe_sendStToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
(!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT ||
CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
!coreFix_memExe_reqStQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendStToMem =
CAN_FIRE_RL_coreFix_memExe_sendStToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2108 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2677 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd0 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_St_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd0 &&
!coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_stb$getEnqIndex[2] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doRespLdMem
assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem =
!coreFix_memExe_memRespLdQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem =
CAN_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doRespLdForward
assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward =
!coreFix_memExe_forwardQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward =
CAN_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_rl_debug_gpr_write
assign CAN_FIRE_RL_rl_debug_gpr_write =
regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
f_gpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_gpr_write = CAN_FIRE_RL_rl_debug_gpr_write ;
// rule RL_rl_debug_fpr_write
assign CAN_FIRE_RL_rl_debug_fpr_write =
regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$EMPTY_N &&
f_fpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_fpr_write = CAN_FIRE_RL_rl_debug_fpr_write ;
// rule RL_coreFix_memExe_doExeMem
assign CAN_FIRE_RL_coreFix_memExe_doExeMem =
coreFix_memExe_regToExeQ$RDY_deq &&
coreFix_memExe_regToExeQ$RDY_first &&
coreFix_memExe_dTlb$RDY_procReq ;
assign WILL_FIRE_RL_coreFix_memExe_doExeMem =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
// rule RL_prepareCachesAndTlbs
assign CAN_FIRE_RL_prepareCachesAndTlbs =
(!flush_tlbs ||
coreFix_memExe_dTlb$RDY_flush &&
fetchStage$RDY_iTlbIfc_flush) &&
(flush_reservation || flush_tlbs || update_vm_info) ;
assign WILL_FIRE_RL_prepareCachesAndTlbs =
CAN_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_rl_debug_resume
assign CAN_FIRE_RL_rl_debug_resume =
commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush &&
fetchStage$RDY_iTlbIfc_flush &&
f_run_halt_reqs$EMPTY_N &&
f_run_halt_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
f_run_halt_reqs$D_OUT &&
!f_gpr_reqs$EMPTY_N &&
!f_fpr_reqs$EMPTY_N &&
!f_csr_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ;
// rule RL_coreFix_memExe_doRegReadMem
assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem =
coreFix_memExe_dispToRegQ$RDY_deq &&
coreFix_memExe_regToExeQ$RDY_enq &&
coreFix_memExe_dispToRegQ$RDY_first &&
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632 ;
assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem =
CAN_FIRE_RL_coreFix_memExe_doRegReadMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doDispatchMem
assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem =
coreFix_memExe_dispToRegQ$RDY_enq &&
coreFix_memExe_rsMem$RDY_doDispatch &&
coreFix_memExe_rsMem$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem =
CAN_FIRE_RL_coreFix_memExe_doDispatchMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
(!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8430 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq &&
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
!coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
// rule RL_renameStage_doRenaming_Trap
assign CAN_FIRE_RL_renameStage_doRenaming_Trap =
epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 &&
rob$isEmpty &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_renameStage_doRenaming_Trap =
CAN_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_renameStage_doRenaming_SystemInst
assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst =
epochManager$RDY_incrementEpoch &&
rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst =
CAN_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_csrInstOrInterruptInflight_canon
assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
// rule RL_commitStage_doSetLSQAtCommit
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit =
MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 ||
WILL_FIRE_RL_commitStage_notifyLSQCommit ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
// rule RL_commitStage_doSetLSQAtCommit_1
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] != 5'd0 &&
rob$deqPort_1_deq_data[329:325] != 5'd21 &&
rob$deqPort_1_deq_data[329:325] != 5'd17 &&
rob$deqPort_1_deq_data[329:325] != 5'd18 &&
rob$deqPort_1_deq_data[329:325] != 5'd13 &&
rob$deqPort_1_deq_data[329:325] != 5'd16 &&
rob$deqPort_1_deq_data[329:325] != 5'd15 &&
rob$deqPort_1_deq_data[329:325] != 5'd19 &&
rob$deqPort_1_deq_data[329:325] != 5'd20 &&
rob$deqPort_1_deq_data[13] ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
// rule RL_renameStage_doRenaming
assign CAN_FIRE_RL_renameStage_doRenaming =
(!fetchStage$pipelines_0_canDeq ||
IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435) &&
IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13908 &&
IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13916 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14090 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14094 ;
assign WILL_FIRE_RL_renameStage_doRenaming =
CAN_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_mmio_pRqQ_canonicalize
assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_globalSpecUpdate_canon_correct_spec
assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_1 =
WILL_FIRE_RL_renameStage_doRenaming ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_2 =
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_3 =
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign MUX_commitStage_rg_run_state$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ;
assign MUX_commitStage_rg_serial_num$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ;
assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[13] ;
assign MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3 =
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2531 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2535) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017) ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2123) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666 ;
assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2605) ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630) ;
assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565 ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ;
assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
(commitStage_commitTrap[36] ||
commitStage_commitTrap[35:32] == 4'd3) ;
assign MUX_csrf_external_int_en_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd22) ;
assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ;
assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd16 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd29) ;
assign MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd29 ;
assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ;
assign MUX_csrf_fflags_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 ;
assign MUX_csrf_fflags_reg$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd2) ;
assign MUX_csrf_fflags_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
assign MUX_csrf_frm_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd2) ;
assign MUX_csrf_fs_reg$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd2 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18) ;
assign MUX_csrf_fs_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3 ||
f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
assign MUX_csrf_ie_vec_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18) ;
assign MUX_csrf_ie_vec_0$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
assign MUX_csrf_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_ie_vec_1$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ;
assign MUX_csrf_mcause_code_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd27 ;
assign MUX_csrf_mcause_code_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ;
assign MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ;
assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2816 ;
assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd30 ;
assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ;
assign MUX_csrf_mepc_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd26 ;
assign MUX_csrf_mepc_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd833 ;
assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ;
assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2818 ;
assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd31 ;
assign MUX_csrf_mpp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_mscratch_csr$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd832 ;
assign MUX_csrf_mtval_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd28 ;
assign MUX_csrf_mtval_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd835 ;
assign MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ;
assign MUX_csrf_ppn_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ;
assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_prv_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ;
assign MUX_csrf_prv_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ;
assign MUX_csrf_rg_dcsr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd40 ;
assign MUX_csrf_rg_dpc$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd41 ;
assign MUX_csrf_rg_dpc$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1969 ;
assign MUX_csrf_rg_dscratch0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1970 ;
assign MUX_csrf_rg_dscratch1$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1971 ;
assign MUX_csrf_rg_tdata1_data$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1953 ;
assign MUX_csrf_rg_tdata2$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1954 ;
assign MUX_csrf_rg_tdata3$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1955 ;
assign MUX_csrf_rg_tselect$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1952 ;
assign MUX_csrf_scause_code_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd14 ;
assign MUX_csrf_scause_code_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ;
assign MUX_csrf_scounteren_cy_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ;
assign MUX_csrf_sepc_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd13 ;
assign MUX_csrf_sepc_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd321 ;
assign MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd0 &&
mmio_pRqQ_data_0[37:36] != 2'd1 ;
assign MUX_csrf_spp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_sscratch_csr$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd320 ;
assign MUX_csrf_stats_module_writeQ$enq_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2049 ;
assign MUX_csrf_stval_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd15 ;
assign MUX_csrf_stval_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd323 ;
assign MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ;
assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ;
assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205 &&
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 ;
assign MUX_flush_reservation$write_1__SEL_2 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ;
assign MUX_flush_tlbs$write_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ;
assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 =
MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 &&
csrf_rg_dcsr[2] ;
assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
csrf_rg_dcsr[2] ;
assign MUX_rf$write_3_wr_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_1__PSEL_5 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
assign MUX_rf$write_3_wr_1__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_rf$write_3_wr_2__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_rg_core_run_state$write_1__SEL_4 =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ;
assign MUX_rob$setExecuted_deqLSQ_1__SEL_5 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ;
assign MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_sbAggr$setReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbAggr$setReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_sbCons$setReady_3_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbCons$setReady_3_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_sbCons$setReady_3_put_1__SEL_3 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[84] ;
assign MUX_started$write_1__SEL_1 =
CAN_FIRE_RL_rl_debug_resume &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
assign MUX_v_f_to_TV_0$enq_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ;
assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 =
{ 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ;
assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 =
{ 2'd3, f_fpr_reqs$D_OUT[68:64], 20'd345386 } ;
assign MUX_commitStage_commitTrap$write_1__VAL_2 =
{ 1'd1,
rob$deqPort_0_deq_data[425:362],
x__h701397,
rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393,
rob$deqPort_0_deq_data[361:330] } ;
assign MUX_commitStage_rg_serial_num$write_1__VAL_1 =
commitStage_rg_serial_num + 64'd1 ;
assign MUX_commitStage_rg_serial_num$write_1__VAL_3 =
commitStage_rg_serial_num + y__h732518 ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 =
(k__h669623 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584,
fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h685237,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
5'd10,
sbAggr$eagerLookup_0_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 =
{ 1'd1,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 =
{ 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 =
{ 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 =
{ 1'd1, coreFix_memExe_lsq$getHit[7:1] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
3'd3 :
3'd5) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 } :
58'h155555555555554) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
55'h15555555555555 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } :
{ (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2523 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 =
{ coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100],
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0],
IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd0) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) :
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2526 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84],
x__h285845 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
x__h287290,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 =
{ 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 =
{ 2'd2,
addr__h290066,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 =
{ x__h153724, x__h153730, 84'h82AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 =
{ x__h157271, x__h157277, 84'hCAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 =
{ x__h160087,
x__h160091,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
x__h161939,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
resp_addr__h291970,
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ;
assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 =
{ prv__h734208,
prv__h734208 != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$getIssueLd[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_issueLd$wget[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_lsq$getHit_1__VAL_1 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ;
assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 =
{ coreFix_memExe_stb$search[67],
coreFix_memExe_stb$search[67] ?
coreFix_memExe_stb$search[66:65] :
2'h2,
coreFix_memExe_stb$search[64],
coreFix_memExe_stb$search[64] ?
coreFix_memExe_stb$search[63:0] :
64'hAAAAAAAAAAAAAAAA } ;
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_1[63:0];
endcase
end
assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148],
x__h197125 } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 =
{ 5'd0,
coreFix_memExe_lsq$firstSt[141:78],
2'd3,
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4,
coreFix_memExe_lsq$firstSt[76:5],
coreFix_memExe_lsq$firstSt[156:153],
coreFix_memExe_lsq$firstSt[69] &&
coreFix_memExe_lsq$firstSt[70] &&
coreFix_memExe_lsq$firstSt[71] &&
coreFix_memExe_lsq$firstSt[72] &&
coreFix_memExe_lsq$firstSt[73] &&
coreFix_memExe_lsq$firstSt[74] &&
coreFix_memExe_lsq$firstSt[75] &&
coreFix_memExe_lsq$firstSt[76],
coreFix_memExe_lsq$firstSt[152:151] } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 =
{ 5'd0,
coreFix_memExe_lsq$firstLd[80:17],
84'h92AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 } :
65'h10000000000000001) :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ?
curData__h192915 :
{ {32{x__h193678[31]}}, x__h193678 } } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[326:322],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[300:277],
1'd0,
coreFix_aluExe_0_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[326:322],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[300:277],
1'd1,
coreFix_aluExe_0_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[326:322],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[300:277],
1'd0,
coreFix_aluExe_1_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[326:322],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[300:277],
1'd1,
coreFix_aluExe_1_exeToFinQ$first[276] } ;
assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 =
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 ||
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ;
assign MUX_csrf_fflags_reg$write_1__VAL_1 =
csrf_fflags_reg | fflags__h732495 ;
assign MUX_csrf_frm_reg$write_1__VAL_1 =
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd1) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] :
robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:5] ;
assign MUX_csrf_frm_reg$write_1__VAL_2 =
(f_csr_reqs$D_OUT[75:64] == 12'd2) ?
f_csr_reqs$D_OUT[2:0] :
f_csr_reqs$D_OUT[7:5] ;
always@(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 or
robdeqPort_0_deq_data_BITS_95_TO_32__q245)
begin
case (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973)
6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11;
default: MUX_csrf_fs_reg$write_1__VAL_2 =
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13];
endcase
end
always@(f_csr_reqs$D_OUT)
begin
case (f_csr_reqs$D_OUT[75:64])
12'd1, 12'd2, 12'd3: MUX_csrf_fs_reg$write_1__VAL_3 = 2'b11;
default: MUX_csrf_fs_reg$write_1__VAL_3 = f_csr_reqs$D_OUT[14:13];
endcase
end
assign MUX_csrf_ie_vec_1$write_1__VAL_1 =
(rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18)) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1] :
csrf_prev_ie_vec_1 ;
assign MUX_csrf_ie_vec_3$write_1__VAL_1 =
(rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q245[3] :
csrf_prev_ie_vec_3 ;
assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 =
rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 =
n__read__h725937 + 64'd1 ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 =
n__read__h725937 + { 62'd0, x__h732759 } ;
assign MUX_csrf_mpp_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18) ?
MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] :
2'd0 ;
assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 =
rob$deqPort_0_deq_data[329:325] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 !=
6'd8 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 !=
6'd18 ||
MUX_csrf_mtval_csr$write_1__VAL_1[5] ;
assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 =
rob$deqPort_0_deq_data[329:325] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 !=
6'd18 ||
MUX_csrf_mtval_csr$write_1__VAL_1[7] ;
assign MUX_csrf_prv_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd40) ?
MUX_csrf_mtval_csr$write_1__VAL_1[1:0] :
((rob$deqPort_0_deq_data[329:325] == 5'd19) ?
x__h721573 :
csrf_mpp_reg) ;
assign MUX_csrf_rg_dcsr$write_1__VAL_2 =
{ 32'b0,
csrf_rg_dcsr[31:9],
dcsr_cause__h707982,
csrf_rg_dcsr[5:2],
csrf_prv_reg } ;
assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 =
(mmio_pRqQ_data_0[37:36] == 2'd2) ?
mmio_pRqQ_data_0[0] :
amoExec___d880[0] ;
assign MUX_csrf_spp_reg$write_1__VAL_1 =
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18) &&
MUX_csrf_sepc_csr$write_1__VAL_1[8] ;
assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h736609 } ;
assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ;
assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 =
{ csrf_prv_reg,
csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
always@(rob$deqPort_0_deq_data or
next_pc__h721469 or csrf_sepc_csr or csrf_mepc_csr)
begin
case (rob$deqPort_0_deq_data[329:325])
5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr;
5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr;
default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h721469;
endcase
end
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dTlb$toParent_rqToP_first[1:0],
coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ;
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 =
{ 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
mmio_dataReqQ_data_0[141:78],
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274,
mmio_dataReqQ_data_0[71:0] } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
fetchStage$mmioIfc_instReq_first_fst,
5'd2,
fetchStage$mmioIfc_instReq_first_snd,
72'hAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$firstSt[141:78],
(coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ?
6'd42 :
{ 2'd3, coreFix_memExe_lsq$firstSt[156:153] },
coreFix_memExe_lsq$firstSt[76:5] } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_lsq$firstLd[80:17],
6'd26,
coreFix_memExe_lsq$firstLd[15:0],
56'hAAAAAAAAAAAAAA } ;
assign MUX_rf$write_2_wr_2__VAL_2 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
res_data__h337873 :
res_data__h337868 ;
assign MUX_rf$write_2_wr_2__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
res_data__h383575 :
res_data__h383570 ;
assign MUX_rf$write_2_wr_2__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
res_data__h429270 :
res_data__h429265 ;
assign MUX_rf$write_2_wr_2__VAL_5 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ?
data___1__h475007 :
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 ;
assign MUX_rf$write_2_wr_2__VAL_6 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ?
data___1__h475815 :
data__h475281 ;
assign MUX_rf$write_3_wr_2__VAL_3 =
coreFix_memExe_lsq$firstLd[100] ?
coreFix_memExe_respLrScAmoQ_data_0 :
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 ;
assign MUX_rf$write_3_wr_2__VAL_4 =
coreFix_memExe_lsq$firstLd[100] ?
mmio_dataRespQ_data_0[63:0] :
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 ;
assign MUX_rob$enqPort_0_enq_1__VAL_1 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[75:69],
136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 &&
fetchStage$pipelines_0_first[194:192] != 3'd2 &&
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4,
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14166 } ;
assign MUX_rob$enqPort_0_enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[75:69],
136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
2'd1,
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068,
IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283,
fetchStage$pipelines_0_first[63:0],
2'd0,
fetchStage$pipelines_0_first[323:260],
20'd13601,
specTagManager$currentSpecBits } ;
assign MUX_rob$enqPort_0_enq_1__VAL_3 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[75:69],
136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0,
13'h1521,
specTagManager$currentSpecBits } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_3 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 } ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] :
res_fflags__h337869 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] :
res_fflags__h383571 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] :
res_fflags__h429266 ;
assign MUX_v_f_to_TV_0$enq_1__VAL_1 =
{ commitStage_rg_serial_num,
commitStage_f_rob_data$D_OUT[425:181],
CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277,
commitStage_f_rob_data$D_OUT[167:166],
commitStage_f_rob_data$D_OUT[166] ?
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 :
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279,
IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916 } ;
assign MUX_v_f_to_TV_0$enq_1__VAL_2 =
{ commitStage_rg_serial_num,
rob$deqPort_0_deq_data[425:182],
rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494,
rob$deqPort_0_deq_data[167],
rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393,
rob$deqPort_0_deq_data[161:98],
IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501,
fflags__h727255,
rob$deqPort_0_deq_data[26],
x__h728883,
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_v_f_to_TV_0$enq_1__VAL_4 =
{ commitStage_rg_serial_num,
x__h722034,
rob$deqPort_0_deq_data[361:182],
rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494,
rob$deqPort_0_deq_data[167],
rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393,
rob$deqPort_0_deq_data[161:98],
IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281 } ;
// inlined wires
assign csrf_minstret_ehr_data_lat_0$whas =
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ||
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 ;
assign csrf_minstret_ehr_data_lat_1$whas =
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitNormalInst ;
assign csrf_minstret_ehr_data_dummy_1_0$whas =
WILL_FIRE_RL_commitStage_doCommitNormalInst ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign csrf_mcycle_ehr_data_lat_0$whas =
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ||
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 ;
assign csrInstOrInterruptInflight_lat_1$whas =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
WILL_FIRE_RL_renameStage_doRenaming_Trap &&
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299 ;
assign mmio_dataReqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ?
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_dataReqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ;
assign mmio_dataRespQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ;
assign mmio_dataPendQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ;
assign mmio_cRqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_mmio_sendDataReq ?
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_cRqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ;
assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ;
assign mmio_pRsQ_deqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendInstResp ||
WILL_FIRE_RL_mmio_sendDataResp ;
assign mmio_pRqQ_enqReq_lat_0$wget =
{ 1'd1,
mmioToPlatform_pRq_enq_x[38],
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280,
mmioToPlatform_pRq_enq_x[31:0] } ;
assign mmio_cRsQ_enqReq_lat_0$wget =
{ 1'd1, csrf_software_int_pend_vec_3 } ;
assign coreFix_globalSpecUpdate_correctSpecTag_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
coreFix_aluExe_0_exeToFinQ$first[16] ;
assign coreFix_globalSpecUpdate_correctSpecTag_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
coreFix_aluExe_1_exeToFinQ$first[16] ;
assign coreFix_aluExe_0_bypassWire_0$wget =
{ coreFix_aluExe_0_regToExeQ$first[348:342],
basicExec___d12617[321:258] } ;
assign coreFix_aluExe_0_bypassWire_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
coreFix_aluExe_0_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_1$wget =
{ coreFix_aluExe_1_regToExeQ$first[348:342],
basicExec___d11943[321:258] } ;
assign coreFix_aluExe_0_bypassWire_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
coreFix_aluExe_1_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_2$wget =
{ coreFix_aluExe_0_exeToFinQ$first[320:314],
coreFix_aluExe_0_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_2$whas =
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_aluExe_0_bypassWire_3$wget =
{ coreFix_aluExe_1_exeToFinQ$first[320:314],
coreFix_aluExe_1_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_3$whas =
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_aluExe_1_bypassWire_2$whas =
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_aluExe_1_bypassWire_3$whas =
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_fpuMulDivExe_0_bypassWire_3$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225])
2'd0, 2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget =
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225];
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget = 2'd2;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_memExe_bypassWire_2$whas =
_dor1coreFix_memExe_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_memExe_bypassWire_3$whas =
_dor1coreFix_memExe_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_memExe_issueLd$wget =
{ coreFix_memExe_dTlb$procResp[161:157],
coreFix_memExe_dTlb$procResp[246:183],
coreFix_memExe_dTlb$procResp[156:149] } ;
assign coreFix_memExe_issueLd$whas =
WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
coreFix_memExe_dTlb$procResp[177:175] == 3'd0 &&
NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755 &&
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 &&
!coreFix_memExe_lsq$updateAddr ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$wget =
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ?
coreFix_memExe_issueLd$wget[76:8] :
coreFix_memExe_lsq$getIssueLd[76:8] ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_empty_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_full_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ?
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
assign coreFix_memExe_reqStQ_data_0_lat_0$wget =
{ coreFix_memExe_stb$issue[635:576], 6'd0 } ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ?
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ||
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ;
always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_sendStToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_sendLdToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_sendStToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3;
default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget =
{ 1'd1, dCacheToParent_fromP_enq_x } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2649 ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// register commitStage_commitTrap
assign commitStage_commitTrap$D_IN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ?
166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_commitStage_commitTrap$write_1__VAL_2 ;
assign commitStage_commitTrap$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
// register commitStage_rg_just_after_reset
assign commitStage_rg_just_after_reset$D_IN = 1'd0 ;
assign commitStage_rg_just_after_reset$EN =
CAN_FIRE_RL_commitStage_rl_send_tv_reset ;
// register commitStage_rg_run_state
assign commitStage_rg_run_state$D_IN =
MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign commitStage_rg_run_state$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
WILL_FIRE_RL_rl_debug_resume ;
// register commitStage_rg_serial_num
always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
MUX_commitStage_rg_serial_num$write_1__VAL_1 or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
WILL_FIRE_RL_commitStage_doCommitNormalInst or
MUX_commitStage_rg_serial_num$write_1__VAL_3 or
WILL_FIRE_RL_commitStage_rl_send_tv_reset)
begin
case (1'b1) // synopsys parallel_case
MUX_commitStage_rg_serial_num$write_1__SEL_1:
commitStage_rg_serial_num$D_IN =
MUX_commitStage_rg_serial_num$write_1__VAL_1;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
commitStage_rg_serial_num$D_IN =
MUX_commitStage_rg_serial_num$write_1__VAL_1;
WILL_FIRE_RL_commitStage_doCommitNormalInst:
commitStage_rg_serial_num$D_IN =
MUX_commitStage_rg_serial_num$write_1__VAL_3;
WILL_FIRE_RL_commitStage_rl_send_tv_reset:
commitStage_rg_serial_num$D_IN = 64'd1;
default: commitStage_rg_serial_num$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign commitStage_rg_serial_num$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitNormalInst ||
WILL_FIRE_RL_commitStage_rl_send_tv_reset ;
// register coreFix_doStatsReg
assign coreFix_doStatsReg$D_IN = 1'b0 ;
assign coreFix_doStatsReg$EN = 1'b0 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt + 4'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN = 1'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt == 4'd15 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ?
v__h604527 :
v__h603882 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd2 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd4 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd5 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd6 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
_theResult_____2__h296520 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3078 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
v__h295940 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN =
4'b0010 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN =
{ !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]),
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
_theResult_____2__h304516 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3183 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
v__h299285 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN =
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3170 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas &&
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
_theResult_____2__h310510 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3355 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
v__h309799 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN =
73'h0AAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3341 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN =
{ x_addr__h314073,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513],
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 ||
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]),
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
_theResult_____2__h318364 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3451 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
v__h313675 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN =
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3437 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_data_0
assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN =
coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ;
assign coreFix_memExe_dMem_perfReqQ_data_0$EN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_empty
assign coreFix_memExe_dMem_perfReqQ_empty$D_IN =
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_clearReq_rl ||
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1927 ;
assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_full
assign coreFix_memExe_dMem_perfReqQ_full$D_IN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1911 ;
assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_clearReq_rl
assign coreFix_memExe_forwardQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_data_0
assign coreFix_memExe_forwardQ_data_0$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_0$EN =
coreFix_memExe_forwardQ_enqP == 1'd0 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 ;
// register coreFix_memExe_forwardQ_data_1
assign coreFix_memExe_forwardQ_data_1$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_1$EN =
coreFix_memExe_forwardQ_enqP == 1'd1 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 ;
// register coreFix_memExe_forwardQ_deqP
assign coreFix_memExe_forwardQ_deqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
_theResult_____2__h331933 ;
assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_deqReq_rl
assign coreFix_memExe_forwardQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_empty
assign coreFix_memExe_forwardQ_empty$D_IN =
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_forwardQ_clearReq_rl ||
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 &&
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3772 ;
assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqP
assign coreFix_memExe_forwardQ_enqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
v__h331501 ;
assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqReq_rl
assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_full
assign coreFix_memExe_forwardQ_full$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 &&
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3759 ;
assign coreFix_memExe_forwardQ_full$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_clearReq_rl
assign coreFix_memExe_memRespLdQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_data_0
assign coreFix_memExe_memRespLdQ_data_0$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_0$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd0 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 ;
// register coreFix_memExe_memRespLdQ_data_1
assign coreFix_memExe_memRespLdQ_data_1$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_1$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd1 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 ;
// register coreFix_memExe_memRespLdQ_deqP
assign coreFix_memExe_memRespLdQ_deqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
_theResult_____2__h328708 ;
assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_deqReq_rl
assign coreFix_memExe_memRespLdQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_empty
assign coreFix_memExe_memRespLdQ_empty$D_IN =
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_memRespLdQ_clearReq_rl ||
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 &&
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3678 ;
assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqP
assign coreFix_memExe_memRespLdQ_enqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
v__h328276 ;
assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqReq_rl
assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_full
assign coreFix_memExe_memRespLdQ_full$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 &&
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 ;
assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_data_0_rl
assign coreFix_memExe_reqLdQ_data_0_rl$D_IN =
coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget :
coreFix_memExe_reqLdQ_data_0_rl ;
assign coreFix_memExe_reqLdQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_empty_rl
assign coreFix_memExe_reqLdQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
!coreFix_memExe_reqLdQ_empty_lat_0$whas &&
coreFix_memExe_reqLdQ_empty_rl ;
assign coreFix_memExe_reqLdQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_full_rl
assign coreFix_memExe_reqLdQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
(coreFix_memExe_reqLdQ_full_lat_0$whas ||
coreFix_memExe_reqLdQ_full_rl) ;
assign coreFix_memExe_reqLdQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN =
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget :
coreFix_memExe_reqLrScAmoQ_data_0_rl ;
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
assign coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
!coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas &&
coreFix_memExe_reqLrScAmoQ_empty_rl ;
assign coreFix_memExe_reqLrScAmoQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_full_rl
assign coreFix_memExe_reqLrScAmoQ_full_rl$D_IN =
!CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem &&
(coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
coreFix_memExe_reqLrScAmoQ_full_rl) ;
assign coreFix_memExe_reqLrScAmoQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_data_0_rl
assign coreFix_memExe_reqStQ_data_0_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget :
coreFix_memExe_reqStQ_data_0_rl ;
assign coreFix_memExe_reqStQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_empty_rl
assign coreFix_memExe_reqStQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
!CAN_FIRE_RL_coreFix_memExe_doIssueSB &&
coreFix_memExe_reqStQ_empty_rl ;
assign coreFix_memExe_reqStQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_full_rl
assign coreFix_memExe_reqStQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendStToMem &&
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
coreFix_memExe_reqStQ_full_rl) ;
assign coreFix_memExe_reqStQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_data_0
assign coreFix_memExe_respLrScAmoQ_data_0$D_IN =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ;
assign coreFix_memExe_respLrScAmoQ_data_0$EN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558 ;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_empty
assign coreFix_memExe_respLrScAmoQ_empty$D_IN =
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_respLrScAmoQ_clearReq_rl ||
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589 ;
assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_full
assign coreFix_memExe_respLrScAmoQ_full$D_IN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574 ;
assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ;
// register coreFix_memExe_waitLrScAmoMMIOResp
always@(MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd0;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd4;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd2;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd6;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd7;
default: coreFix_memExe_waitLrScAmoMMIOResp$D_IN =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_waitLrScAmoMMIOResp$EN =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// register csrInstOrInterruptInflight_rl
assign csrInstOrInterruptInflight_rl$D_IN =
csrInstOrInterruptInflight_lat_1$whas ?
1'd1 :
(MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ?
1'd0 :
csrInstOrInterruptInflight_rl) ;
assign csrInstOrInterruptInflight_rl$EN = 1'd1 ;
// register csrf_external_int_en_vec_0
assign csrf_external_int_en_vec_0$D_IN = 1'b0 ;
assign csrf_external_int_en_vec_0$EN = 1'b0 ;
// register csrf_external_int_en_vec_1
assign csrf_external_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[9] :
f_csr_reqs$D_OUT[9] ;
assign csrf_external_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_external_int_en_vec_3
assign csrf_external_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[11] :
MUX_csrf_stval_csr$write_1__VAL_1[11] ;
assign csrf_external_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd22 ;
// register csrf_external_int_pend_vec_0
assign csrf_external_int_pend_vec_0$D_IN = 1'b0 ;
assign csrf_external_int_pend_vec_0$EN = 1'b0 ;
// register csrf_external_int_pend_vec_1
always@(MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_external_int_pend_vec_1$write_1__SEL_2 or
f_csr_reqs$D_OUT or EN_setSEIP or setSEIP_v)
case (1'b1)
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1:
csrf_external_int_pend_vec_1$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[9];
MUX_csrf_external_int_pend_vec_1$write_1__SEL_2:
csrf_external_int_pend_vec_1$D_IN = f_csr_reqs$D_OUT[9];
EN_setSEIP: csrf_external_int_pend_vec_1$D_IN = setSEIP_v;
default: csrf_external_int_pend_vec_1$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_external_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ||
EN_setSEIP ;
// register csrf_external_int_pend_vec_3
always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or
f_csr_reqs$D_OUT or EN_setMEIP or setMEIP_v)
case (1'b1)
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1:
csrf_external_int_pend_vec_3$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[11];
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2:
csrf_external_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[11];
EN_setMEIP: csrf_external_int_pend_vec_3$D_IN = setMEIP_v;
default: csrf_external_int_pend_vec_3$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_external_int_pend_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd29 ||
EN_setMEIP ;
// register csrf_fflags_reg
always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
MUX_csrf_fflags_reg$write_1__VAL_1 or
MUX_csrf_fflags_reg$write_1__SEL_2 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_fflags_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_fflags_reg$write_1__SEL_1:
csrf_fflags_reg$D_IN = MUX_csrf_fflags_reg$write_1__VAL_1;
MUX_csrf_fflags_reg$write_1__SEL_2:
csrf_fflags_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0];
MUX_csrf_fflags_reg$write_1__SEL_3:
csrf_fflags_reg$D_IN = f_csr_reqs$D_OUT[4:0];
default: csrf_fflags_reg$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign csrf_fflags_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd2) ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
// register csrf_frm_reg
assign csrf_frm_reg$D_IN =
MUX_csrf_frm_reg$write_1__SEL_1 ?
MUX_csrf_frm_reg$write_1__VAL_1 :
MUX_csrf_frm_reg$write_1__VAL_2 ;
assign csrf_frm_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd2) ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
// register csrf_fs_reg
always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
MUX_csrf_fs_reg$write_1__SEL_2 or
MUX_csrf_fs_reg$write_1__VAL_2 or
MUX_csrf_fs_reg$write_1__SEL_3 or MUX_csrf_fs_reg$write_1__VAL_3)
case (1'b1)
MUX_csrf_fflags_reg$write_1__SEL_1: csrf_fs_reg$D_IN = 2'b11;
MUX_csrf_fs_reg$write_1__SEL_2:
csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_2;
MUX_csrf_fs_reg$write_1__SEL_3:
csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_3;
default: csrf_fs_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_fs_reg$EN =
MUX_csrf_fs_reg$write_1__SEL_2 ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3 ||
f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_0
assign csrf_ie_vec_0$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[0] :
f_csr_reqs$D_OUT[0] ;
assign csrf_ie_vec_0$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_1
always@(MUX_csrf_ie_vec_1$write_1__SEL_1 or
MUX_csrf_ie_vec_1$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_ie_vec_1$write_1__SEL_1:
csrf_ie_vec_1$D_IN = MUX_csrf_ie_vec_1$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_ie_vec_1$D_IN = 1'd0;
MUX_csrf_ie_vec_0$write_1__SEL_2:
csrf_ie_vec_1$D_IN = f_csr_reqs$D_OUT[1];
default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_3
always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or
MUX_csrf_ie_vec_3$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_ie_vec_3$write_1__SEL_1:
csrf_ie_vec_3$D_IN = MUX_csrf_ie_vec_3$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_ie_vec_3$D_IN = 1'd0;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_ie_vec_3$D_IN = f_csr_reqs$D_OUT[3];
default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ;
// register csrf_mcause_code_reg
always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
cause_code__h708463 or
MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mcause_code_reg$write_1__SEL_1:
csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mcause_code_reg$D_IN = cause_code__h708463;
MUX_csrf_mcause_code_reg$write_1__SEL_3:
csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign csrf_mcause_code_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd27 ;
// register csrf_mcause_interrupt_reg
always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mcause_code_reg$write_1__SEL_1:
csrf_mcause_interrupt_reg$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[63];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mcause_interrupt_reg$D_IN = commitStage_commitTrap[36];
MUX_csrf_mcause_code_reg$write_1__SEL_3:
csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_mcause_interrupt_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd27 ;
// register csrf_mcounteren_cy_reg
assign csrf_mcounteren_cy_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_mcounteren_cy_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd24 ;
// register csrf_mcounteren_ir_reg
assign csrf_mcounteren_ir_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[2] :
MUX_csrf_stval_csr$write_1__VAL_1[2] ;
assign csrf_mcounteren_ir_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd24 ;
// register csrf_mcounteren_tm_reg
assign csrf_mcounteren_tm_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1] :
MUX_csrf_stval_csr$write_1__VAL_1[1] ;
assign csrf_mcounteren_tm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd24 ;
// register csrf_mcycle_ehr_data_rl
assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5310 ;
assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ;
// register csrf_medeleg_13_11_reg
assign csrf_medeleg_13_11_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[13:11] :
MUX_csrf_stval_csr$write_1__VAL_1[13:11] ;
assign csrf_medeleg_13_11_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd20 ;
// register csrf_medeleg_15_reg
assign csrf_medeleg_15_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[15] :
MUX_csrf_stval_csr$write_1__VAL_1[15] ;
assign csrf_medeleg_15_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd20 ;
// register csrf_medeleg_9_0_reg
assign csrf_medeleg_9_0_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[9:0] :
MUX_csrf_stval_csr$write_1__VAL_1[9:0] ;
assign csrf_medeleg_9_0_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd20 ;
// register csrf_mepc_csr
always@(MUX_csrf_mepc_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_mepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mepc_csr$write_1__SEL_1:
csrf_mepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mepc_csr$D_IN = commitStage_commitTrap[164:101];
MUX_csrf_mepc_csr$write_1__SEL_3:
csrf_mepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_mepc_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_mepc_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd833 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd26 ;
// register csrf_mideleg_11_reg
assign csrf_mideleg_11_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[11] :
MUX_csrf_stval_csr$write_1__VAL_1[11] ;
assign csrf_mideleg_11_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd21 ;
// register csrf_mideleg_1_0_reg
assign csrf_mideleg_1_0_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1:0] :
MUX_csrf_stval_csr$write_1__VAL_1[1:0] ;
assign csrf_mideleg_1_0_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd21 ;
// register csrf_mideleg_5_3_reg
assign csrf_mideleg_5_3_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[5:3] :
MUX_csrf_stval_csr$write_1__VAL_1[5:3] ;
assign csrf_mideleg_5_3_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd21 ;
// register csrf_mideleg_9_7_reg
assign csrf_mideleg_9_7_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[9:7] :
MUX_csrf_stval_csr$write_1__VAL_1[9:7] ;
assign csrf_mideleg_9_7_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd21 ;
// register csrf_minstret_ehr_data_rl
assign csrf_minstret_ehr_data_rl$D_IN =
csrf_minstret_ehr_data_lat_1$whas ?
upd__h3993 :
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ;
assign csrf_minstret_ehr_data_rl$EN = 1'd1 ;
// register csrf_mpp_reg
always@(MUX_csrf_mpp_reg$write_1__SEL_1 or
MUX_csrf_mpp_reg$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
csrf_prv_reg or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mpp_reg$write_1__SEL_1:
csrf_mpp_reg$D_IN = MUX_csrf_mpp_reg$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mpp_reg$D_IN = csrf_prv_reg;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_mpp_reg$D_IN = f_csr_reqs$D_OUT[12:11];
default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_mpp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ;
// register csrf_mprv_reg
assign csrf_mprv_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[17] :
MUX_csrf_stval_csr$write_1__VAL_1[17] ;
assign csrf_mprv_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18 ;
// register csrf_mscratch_csr
assign csrf_mscratch_csr$D_IN =
MUX_csrf_mscratch_csr$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_mscratch_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd832 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd25 ;
// register csrf_mtval_csr
always@(MUX_csrf_mtval_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
trap_val__h708464 or
MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mtval_csr$write_1__SEL_1:
csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mtval_csr$D_IN = trap_val__h708464;
MUX_csrf_mtval_csr$write_1__SEL_3:
csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_mtval_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_mtval_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd835 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd28 ;
// register csrf_mtvec_base_hi_reg
assign csrf_mtvec_base_hi_reg$D_IN =
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:2] :
MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
assign csrf_mtvec_base_hi_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd23 ;
// register csrf_mtvec_mode_low_reg
assign csrf_mtvec_mode_low_reg$D_IN =
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_mtvec_mode_low_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd23 ;
// register csrf_mxr_reg
assign csrf_mxr_reg$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[19] :
f_csr_reqs$D_OUT[19] ;
assign csrf_mxr_reg$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ppn_reg
assign csrf_ppn_reg$D_IN =
MUX_csrf_ppn_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[43:0] :
MUX_csrf_stval_csr$write_1__VAL_1[43:0] ;
assign csrf_ppn_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd17 ;
// register csrf_prev_ie_vec_0
assign csrf_prev_ie_vec_0$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[4] :
f_csr_reqs$D_OUT[4] ;
assign csrf_prev_ie_vec_0$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_prev_ie_vec_1
always@(MUX_csrf_prev_ie_vec_1$write_1__SEL_1 or
MUX_csrf_prev_ie_vec_1$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
csrf_ie_vec_1 or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prev_ie_vec_1$write_1__SEL_1:
csrf_prev_ie_vec_1$D_IN = MUX_csrf_prev_ie_vec_1$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_prev_ie_vec_1$D_IN = csrf_ie_vec_1;
MUX_csrf_ie_vec_0$write_1__SEL_2:
csrf_prev_ie_vec_1$D_IN = f_csr_reqs$D_OUT[5];
default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_prev_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_prev_ie_vec_3
always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or
MUX_csrf_prev_ie_vec_3$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
csrf_ie_vec_3 or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prev_ie_vec_3$write_1__SEL_1:
csrf_prev_ie_vec_3$D_IN = MUX_csrf_prev_ie_vec_3$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_prev_ie_vec_3$D_IN = csrf_ie_vec_3;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_prev_ie_vec_3$D_IN = f_csr_reqs$D_OUT[7];
default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_prev_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 ;
// register csrf_prv_reg
always@(MUX_csrf_prv_reg$write_1__SEL_1 or
MUX_csrf_prv_reg$write_1__VAL_1 or
MUX_commitStage_rg_serial_num$write_1__SEL_1 or
x_prv__h711506 or
MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prv_reg$write_1__SEL_1:
csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1;
MUX_commitStage_rg_serial_num$write_1__SEL_1:
csrf_prv_reg$D_IN = x_prv__h711506;
MUX_csrf_prv_reg$write_1__SEL_3:
csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0];
default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_prv_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ;
// register csrf_rg_dcsr
always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_commitStage_rg_run_state$write_1__SEL_1 or
MUX_csrf_rg_dcsr$write_1__VAL_2 or
MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_rg_dcsr$write_1__SEL_1:
csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_commitStage_rg_run_state$write_1__SEL_1:
csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2;
MUX_csrf_prv_reg$write_1__SEL_3:
csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_rg_dcsr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_rg_dcsr$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd40 ;
// register csrf_rg_dpc
always@(MUX_csrf_rg_dpc$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_commitStage_rg_run_state$write_1__SEL_1 or
commitStage_commitTrap or
MUX_csrf_rg_dpc$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_rg_dpc$write_1__SEL_1:
csrf_rg_dpc$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_commitStage_rg_run_state$write_1__SEL_1:
csrf_rg_dpc$D_IN = commitStage_commitTrap[164:101];
MUX_csrf_rg_dpc$write_1__SEL_3: csrf_rg_dpc$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_rg_dpc$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_rg_dpc$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1969 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd41 ;
// register csrf_rg_dscratch0
assign csrf_rg_dscratch0$D_IN =
MUX_csrf_rg_dscratch0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_dscratch0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1970 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd42 ;
// register csrf_rg_dscratch1
assign csrf_rg_dscratch1$D_IN =
MUX_csrf_rg_dscratch1$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_dscratch1$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1971 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd43 ;
// register csrf_rg_tdata1_data
assign csrf_rg_tdata1_data$D_IN =
MUX_csrf_rg_tdata1_data$write_1__SEL_1 ?
f_csr_reqs$D_OUT[58:0] :
MUX_csrf_stval_csr$write_1__VAL_1[58:0] ;
assign csrf_rg_tdata1_data$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1953 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd37 ;
// register csrf_rg_tdata1_dmode
assign csrf_rg_tdata1_dmode$D_IN =
MUX_csrf_rg_tdata1_data$write_1__SEL_1 ?
f_csr_reqs$D_OUT[59] :
MUX_csrf_stval_csr$write_1__VAL_1[59] ;
assign csrf_rg_tdata1_dmode$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1953 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd37 ;
// register csrf_rg_tdata2
assign csrf_rg_tdata2$D_IN =
MUX_csrf_rg_tdata2$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_tdata2$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1954 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd38 ;
// register csrf_rg_tdata3
assign csrf_rg_tdata3$D_IN =
MUX_csrf_rg_tdata3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_tdata3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1955 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd39 ;
// register csrf_rg_tselect
assign csrf_rg_tselect$D_IN =
MUX_csrf_rg_tselect$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_tselect$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1952 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd36 ;
// register csrf_scause_code_reg
always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
cause_code__h708463 or
MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_scause_code_reg$write_1__SEL_1:
csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_scause_code_reg$D_IN = cause_code__h708463;
MUX_csrf_scause_code_reg$write_1__SEL_3:
csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign csrf_scause_code_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd14 ;
// register csrf_scause_interrupt_reg
always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_scause_code_reg$write_1__SEL_1:
csrf_scause_interrupt_reg$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[63];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_scause_interrupt_reg$D_IN = commitStage_commitTrap[36];
MUX_csrf_scause_code_reg$write_1__SEL_3:
csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_scause_interrupt_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd14 ;
// register csrf_scounteren_cy_reg
assign csrf_scounteren_cy_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_scounteren_cy_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd11 ;
// register csrf_scounteren_ir_reg
assign csrf_scounteren_ir_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[2] :
MUX_csrf_stval_csr$write_1__VAL_1[2] ;
assign csrf_scounteren_ir_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd11 ;
// register csrf_scounteren_tm_reg
assign csrf_scounteren_tm_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1] :
MUX_csrf_stval_csr$write_1__VAL_1[1] ;
assign csrf_scounteren_tm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd11 ;
// register csrf_sepc_csr
always@(MUX_csrf_sepc_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_sepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_sepc_csr$write_1__SEL_1:
csrf_sepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_sepc_csr$D_IN = commitStage_commitTrap[164:101];
MUX_csrf_sepc_csr$write_1__SEL_3:
csrf_sepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_sepc_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_sepc_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd321 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd13 ;
// register csrf_software_int_en_vec_0
assign csrf_software_int_en_vec_0$D_IN = 1'b0 ;
assign csrf_software_int_en_vec_0$EN = 1'b0 ;
// register csrf_software_int_en_vec_1
assign csrf_software_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[1] :
f_csr_reqs$D_OUT[1] ;
assign csrf_software_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_software_int_en_vec_3
assign csrf_software_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[3] :
MUX_csrf_stval_csr$write_1__VAL_1[3] ;
assign csrf_software_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd22 ;
// register csrf_software_int_pend_vec_0
assign csrf_software_int_pend_vec_0$D_IN = 1'b0 ;
assign csrf_software_int_pend_vec_0$EN = 1'b0 ;
// register csrf_software_int_pend_vec_1
assign csrf_software_int_pend_vec_1$D_IN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[1] :
f_csr_reqs$D_OUT[1] ;
assign csrf_software_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_software_int_pend_vec_3
always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 or
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 or
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1:
csrf_software_int_pend_vec_3$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[3];
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2:
csrf_software_int_pend_vec_3$D_IN =
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2;
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2:
csrf_software_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[3];
default: csrf_software_int_pend_vec_3$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_software_int_pend_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ||
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd0 &&
mmio_pRqQ_data_0[37:36] != 2'd1 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd29 ;
// register csrf_spp_reg
always@(MUX_csrf_spp_reg$write_1__SEL_1 or
MUX_csrf_spp_reg$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
csrf_prv_reg or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_spp_reg$write_1__SEL_1:
csrf_spp_reg$D_IN = MUX_csrf_spp_reg$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_spp_reg$D_IN = csrf_prv_reg[0];
MUX_csrf_ie_vec_0$write_1__SEL_2: csrf_spp_reg$D_IN = f_csr_reqs$D_OUT[8];
default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_spp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_sscratch_csr
assign csrf_sscratch_csr$D_IN =
MUX_csrf_sscratch_csr$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_sscratch_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd320 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd12 ;
// register csrf_stats_module_doStats
assign csrf_stats_module_doStats$D_IN = recvDoStats_x ;
assign csrf_stats_module_doStats$EN = EN_recvDoStats ;
// register csrf_stval_csr
always@(MUX_csrf_stval_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
trap_val__h708464 or
MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_stval_csr$write_1__SEL_1:
csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_stval_csr$D_IN = trap_val__h708464;
MUX_csrf_stval_csr$write_1__SEL_3:
csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_stval_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_stval_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd323 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 &&
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd15 ;
// register csrf_stvec_base_hi_reg
assign csrf_stvec_base_hi_reg$D_IN =
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:2] :
MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
assign csrf_stvec_base_hi_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd10 ;
// register csrf_stvec_mode_low_reg
assign csrf_stvec_mode_low_reg$D_IN =
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_stvec_mode_low_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd10 ;
// register csrf_sum_reg
assign csrf_sum_reg$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[18] :
f_csr_reqs$D_OUT[18] ;
assign csrf_sum_reg$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_time_reg
assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ;
assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ;
// register csrf_timer_int_en_vec_0
assign csrf_timer_int_en_vec_0$D_IN = 1'b0 ;
assign csrf_timer_int_en_vec_0$EN = 1'b0 ;
// register csrf_timer_int_en_vec_1
assign csrf_timer_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[5] :
f_csr_reqs$D_OUT[5] ;
assign csrf_timer_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_1$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_timer_int_en_vec_3
assign csrf_timer_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[7] :
MUX_csrf_stval_csr$write_1__VAL_1[7] ;
assign csrf_timer_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd22 ;
// register csrf_timer_int_pend_vec_0
assign csrf_timer_int_pend_vec_0$D_IN = 1'b0 ;
assign csrf_timer_int_pend_vec_0$EN = 1'b0 ;
// register csrf_timer_int_pend_vec_1
assign csrf_timer_int_pend_vec_1$D_IN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[5] :
f_csr_reqs$D_OUT[5] ;
assign csrf_timer_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_1$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_timer_int_pend_vec_3
assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ;
assign csrf_timer_int_pend_vec_3$EN =
WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] == 2'd2 ;
// register csrf_tsr_reg
assign csrf_tsr_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[22] :
MUX_csrf_stval_csr$write_1__VAL_1[22] ;
assign csrf_tsr_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18 ;
// register csrf_tvm_reg
assign csrf_tvm_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[20] :
MUX_csrf_stval_csr$write_1__VAL_1[20] ;
assign csrf_tvm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18 ;
// register csrf_tw_reg
assign csrf_tw_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[21] :
MUX_csrf_stval_csr$write_1__VAL_1[21] ;
assign csrf_tw_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18 ;
// register csrf_vm_mode_sv39_reg
assign csrf_vm_mode_sv39_reg$D_IN =
MUX_csrf_ppn_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63] :
MUX_csrf_stval_csr$write_1__VAL_1[63] ;
assign csrf_vm_mode_sv39_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd17 ;
// register flush_brpred
assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign flush_brpred$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
WILL_FIRE_RL_flushBrPred ;
// register flush_caches
assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign flush_caches$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
WILL_FIRE_RL_flushCaches ;
// register flush_reservation
assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ;
assign flush_reservation$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
// register flush_tlbs
assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ;
assign flush_tlbs$EN =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[329:325] == 5'd16 ||
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd17) ;
// register mmio_cRqQ_clearReq_rl
assign mmio_cRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_data_0
assign mmio_cRqQ_data_0$D_IN =
{ x__h46291,
(mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[72] :
mmio_cRqQ_enqReq_rl[72] } :
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[71:64] :
mmio_cRqQ_enqReq_rl[71:64],
x__h48827 } ;
assign mmio_cRqQ_data_0$EN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ;
// register mmio_cRqQ_deqReq_rl
assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_empty
assign mmio_cRqQ_empty$D_IN =
mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl ||
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ;
assign mmio_cRqQ_empty$EN = 1'd1 ;
// register mmio_cRqQ_enqReq_rl
assign mmio_cRqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_full
assign mmio_cRqQ_full$D_IN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ;
assign mmio_cRqQ_full$EN = 1'd1 ;
// register mmio_cRsQ_clearReq_rl
assign mmio_cRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_data_0
assign mmio_cRsQ_data_0$D_IN =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[0] :
mmio_cRsQ_enqReq_rl[0] ;
assign mmio_cRsQ_data_0$EN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ;
// register mmio_cRsQ_deqReq_rl
assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_empty
assign mmio_cRsQ_empty$D_IN =
mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl ||
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ;
assign mmio_cRsQ_empty$EN = 1'd1 ;
// register mmio_cRsQ_enqReq_rl
assign mmio_cRsQ_enqReq_rl$D_IN = 2'b0 ;
assign mmio_cRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_full
assign mmio_cRsQ_full$D_IN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ;
assign mmio_cRsQ_full$EN = 1'd1 ;
// register mmio_dataPendQ_clearReq_rl
assign mmio_dataPendQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_deqReq_rl
assign mmio_dataPendQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_empty
assign mmio_dataPendQ_empty$D_IN =
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataPendQ_clearReq_rl ||
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ;
assign mmio_dataPendQ_empty$EN = 1'd1 ;
// register mmio_dataPendQ_enqReq_rl
assign mmio_dataPendQ_enqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_full
assign mmio_dataPendQ_full$D_IN =
(!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataPendQ_clearReq_rl) &&
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ;
assign mmio_dataPendQ_full$EN = 1'd1 ;
// register mmio_dataReqQ_clearReq_rl
assign mmio_dataReqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_data_0
assign mmio_dataReqQ_data_0$D_IN =
{ x__h18384,
(mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[72] :
mmio_dataReqQ_enqReq_rl[72] } :
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[71:64] :
mmio_dataReqQ_enqReq_rl[71:64],
x__h20922 } ;
assign mmio_dataReqQ_data_0$EN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ;
// register mmio_dataReqQ_deqReq_rl
assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_empty
assign mmio_dataReqQ_empty$D_IN =
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataReqQ_clearReq_rl ||
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ;
assign mmio_dataReqQ_empty$EN = 1'd1 ;
// register mmio_dataReqQ_enqReq_rl
assign mmio_dataReqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_full
assign mmio_dataReqQ_full$D_IN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ;
assign mmio_dataReqQ_full$EN = 1'd1 ;
// register mmio_dataRespQ_clearReq_rl
assign mmio_dataRespQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_data_0
assign mmio_dataRespQ_data_0$D_IN =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[64:0] :
mmio_dataRespQ_enqReq_rl[64:0] ;
assign mmio_dataRespQ_data_0$EN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ;
// register mmio_dataRespQ_deqReq_rl
assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_empty
assign mmio_dataRespQ_empty$D_IN =
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataRespQ_clearReq_rl ||
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ;
assign mmio_dataRespQ_empty$EN = 1'd1 ;
// register mmio_dataRespQ_enqReq_rl
assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_full
assign mmio_dataRespQ_full$D_IN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ;
assign mmio_dataRespQ_full$EN = 1'd1 ;
// register mmio_fromHostAddr
assign mmio_fromHostAddr$D_IN = coreReq_start_fromHostAddr[63:3] ;
assign mmio_fromHostAddr$EN = EN_coreReq_start ;
// register mmio_pRqQ_clearReq_rl
assign mmio_pRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_data_0
assign mmio_pRqQ_data_0$D_IN =
{ EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[38] :
mmio_pRqQ_enqReq_rl[38],
(EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd0 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd0) ?
{ 5'd2,
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[32] :
mmio_pRqQ_enqReq_rl[32] } :
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
x_data__h66085 } ;
assign mmio_pRqQ_data_0$EN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ;
// register mmio_pRqQ_deqReq_rl
assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_empty
assign mmio_pRqQ_empty$D_IN =
mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl ||
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ;
assign mmio_pRqQ_empty$EN = 1'd1 ;
// register mmio_pRqQ_enqReq_rl
assign mmio_pRqQ_enqReq_rl$D_IN = 40'h2AAAAAAAAA ;
assign mmio_pRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_full
assign mmio_pRqQ_full$D_IN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ;
assign mmio_pRqQ_full$EN = 1'd1 ;
// register mmio_pRsQ_clearReq_rl
assign mmio_pRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_data_0
assign mmio_pRsQ_data_0$D_IN =
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[66] :
mmio_pRsQ_enqReq_rl[66],
IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ;
assign mmio_pRsQ_data_0$EN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ;
// register mmio_pRsQ_deqReq_rl
assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_empty
assign mmio_pRsQ_empty$D_IN =
mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl ||
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ;
assign mmio_pRsQ_empty$EN = 1'd1 ;
// register mmio_pRsQ_enqReq_rl
assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ;
assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_full
assign mmio_pRsQ_full$D_IN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ;
assign mmio_pRsQ_full$EN = 1'd1 ;
// register mmio_toHostAddr
assign mmio_toHostAddr$D_IN = coreReq_start_toHostAddr[63:3] ;
assign mmio_toHostAddr$EN = EN_coreReq_start ;
// register outOfReset
assign outOfReset$D_IN = 1'd1 ;
assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ;
// register renameStage_rg_m_halt_req
always@(WILL_FIRE_RL_rl_debug_resume or
WILL_FIRE_RL_rl_debug_halt_req or
MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or
MUX_renameStage_rg_m_halt_req$write_1__SEL_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10;
WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30;
MUX_renameStage_rg_m_halt_req$write_1__SEL_1 ||
MUX_renameStage_rg_m_halt_req$write_1__SEL_2:
renameStage_rg_m_halt_req$D_IN = 5'd31;
default: renameStage_rg_m_halt_req$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign renameStage_rg_m_halt_req$EN =
(WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap) &&
csrf_rg_dcsr[2] ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
csrf_rg_dcsr[2] ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_rl_debug_halt_req ;
// register rg_core_run_state
always@(WILL_FIRE_RL_rl_debug_resume or
WILL_FIRE_RL_rl_debug_halted or
EN_coreReq_start or MUX_rg_core_run_state$write_1__SEL_4)
case (1'b1)
WILL_FIRE_RL_rl_debug_resume: rg_core_run_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_debug_halted: rg_core_run_state$D_IN = 2'd1;
EN_coreReq_start: rg_core_run_state$D_IN = 2'd2;
MUX_rg_core_run_state$write_1__SEL_4: rg_core_run_state$D_IN = 2'd0;
default: rg_core_run_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_core_run_state$EN =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
WILL_FIRE_RL_rl_debug_halted ||
WILL_FIRE_RL_rl_debug_resume ||
EN_coreReq_start ;
// register started
assign started$D_IN = WILL_FIRE_RL_rl_debug_resume || EN_coreReq_start ;
assign started$EN =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
WILL_FIRE_RL_rl_debug_resume ||
EN_coreReq_start ;
// register update_vm_info
assign update_vm_info$D_IN =
!MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ;
assign update_vm_info$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
// submodule commitStage_f_rob_data
assign commitStage_f_rob_data$D_IN =
{ rob$deqPort_0_deq_data[425:182],
rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494,
rob$deqPort_0_deq_data[168:167],
rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393,
rob$deqPort_0_deq_data[161:98],
IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501,
rob$deqPort_0_deq_data[31:0] } ;
assign commitStage_f_rob_data$ENQ =
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign commitStage_f_rob_data$DEQ =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ;
assign commitStage_f_rob_data$CLR = 1'b0 ;
// submodule coreFix_aluExe_0_dispToRegQ
assign coreFix_aluExe_0_dispToRegQ$enq_x =
{ coreFix_aluExe_0_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282,
coreFix_aluExe_0_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283,
coreFix_aluExe_0_rsAlu$dispatchData[122:90],
coreFix_aluExe_0_rsAlu$dispatchData[65:21],
coreFix_aluExe_0_rsAlu$dispatchData[89:66],
coreFix_aluExe_0_rsAlu$dispatchData[8:4],
coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_exeToFinQ
assign coreFix_aluExe_0_exeToFinQ$enq_x =
{ coreFix_aluExe_0_regToExeQ$first[421:417],
coreFix_aluExe_0_regToExeQ$first[349:305],
coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11,
basicExec___d12617[321:258],
coreFix_aluExe_0_regToExeQ$first[395],
basicExec___d12617[257:194],
basicExec___d12617[129:0],
coreFix_aluExe_0_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_regToExeQ
assign coreFix_aluExe_0_regToExeQ$enq_x =
{ coreFix_aluExe_0_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285,
coreFix_aluExe_0_dispToRegQ$first[131],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286,
coreFix_aluExe_0_dispToRegQ$first[118:86],
coreFix_aluExe_0_dispToRegQ$first[61:17],
x__h639739,
x__h639740,
rob$getOrigPC_0_get,
rob$getOrigPredPC_0_get,
rob$getOrig_Inst_0_get,
coreFix_aluExe_0_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_rsAlu
assign coreFix_aluExe_0_rsAlu$enq_x =
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 ?
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 :
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 ;
assign coreFix_aluExe_0_rsAlu$setRegReady_0_put =
{ 1'd1, coreFix_aluExe_0_rsAlu$dispatchData[40:34] } ;
assign coreFix_aluExe_0_rsAlu$setRegReady_1_put =
{ 1'd1, coreFix_aluExe_1_rsAlu$dispatchData[40:34] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_0_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRegReady_3_put =
{ 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_aluExe_0_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[194:192] == 3'd0 ;
assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_0_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_dispToRegQ
assign coreFix_aluExe_1_dispToRegQ$enq_x =
{ coreFix_aluExe_1_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288,
coreFix_aluExe_1_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289,
coreFix_aluExe_1_rsAlu$dispatchData[122:90],
coreFix_aluExe_1_rsAlu$dispatchData[65:21],
coreFix_aluExe_1_rsAlu$dispatchData[89:66],
coreFix_aluExe_1_rsAlu$dispatchData[8:4],
coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_exeToFinQ
assign coreFix_aluExe_1_exeToFinQ$enq_x =
{ coreFix_aluExe_1_regToExeQ$first[421:417],
coreFix_aluExe_1_regToExeQ$first[349:305],
coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11,
basicExec___d11943[321:258],
coreFix_aluExe_1_regToExeQ$first[395],
basicExec___d11943[257:194],
basicExec___d11943[129:0],
coreFix_aluExe_1_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_regToExeQ
assign coreFix_aluExe_1_regToExeQ$enq_x =
{ coreFix_aluExe_1_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291,
coreFix_aluExe_1_dispToRegQ$first[131],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292,
coreFix_aluExe_1_dispToRegQ$first[118:86],
coreFix_aluExe_1_dispToRegQ$first[61:17],
x__h617230,
x__h617231,
rob$getOrigPC_1_get,
rob$getOrigPredPC_1_get,
rob$getOrig_Inst_1_get,
coreFix_aluExe_1_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_rsAlu
assign coreFix_aluExe_1_rsAlu$enq_x =
(k__h669623 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584,
fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h685237,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_aluExe_1_rsAlu$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_aluExe_1_rsAlu$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_1_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_aluExe_1_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo16 ;
assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_1_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717,
coreFix_fpuMulDivExe_0_regToExeQ$first[225],
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022,
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x =
{ execFpuSimple___d11056,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd25 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd26 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd27 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___fst__h603369 :
a__h602947 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser =
{ b__h602948 == 64'd0,
a__h602947,
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0,
x__h603383,
a__h602947[63],
8'd0 } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___snd__h603370 :
b__h602948 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h602947 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h602948 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A =
a__h602947 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B =
b__h602948 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A =
a__h602947 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B =
b__h602948 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P)
begin
case (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[1:0])
2'd0:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[2] ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR = 1'b0 ;
// submodule coreFix_fpuMulDivExe_0_regToExeQ
assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298,
coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12],
x__h481669,
x__h481670,
x__h481671,
coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14112) ?
{ IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h685237,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14112 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14248) ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r =
{ x__h287278,
x__h287290,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2805,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2814,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828,
x__h289144,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n =
x__h285845 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] :
3'd0) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n =
3'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574];
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157];
default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 :
3'd3 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n =
3'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55],
55'h15555555555555 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN =
EN_dCacheToParent_fromP_enq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN =
MUX_flush_reservation$write_1__SEL_2 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n =
2'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d =
{ !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq = 4'd2;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
4'b1010 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd0;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd1;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'b0 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2655) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rqToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rsToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dTlb
assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ;
assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ;
assign coreFix_memExe_dTlb$procReq_req =
{ coreFix_memExe_regToExeQ$first[192:190],
coreFix_memExe_regToExeQ$first[157:140],
coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706,
coreFix_memExe_regToExeQ$first[11:0] } ;
assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x =
{ l2Tlb$toChildren_rsToC_first[80:0],
l2Tlb$toChildren_rsToC_first[82:81] } ;
assign coreFix_memExe_dTlb$updateVMInfo_vm =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
assign coreFix_memExe_dTlb$EN_flush =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_rl_debug_resume ;
assign coreFix_memExe_dTlb$EN_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign coreFix_memExe_dTlb$EN_procReq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_dTlb$EN_deqProcResp =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_dTlb$EN_toParent_rqToP_deq = CAN_FIRE_RL_sendDTlbReq ;
assign coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq =
CAN_FIRE_RL_sendRsToDTlb ;
assign coreFix_memExe_dTlb$EN_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut ;
assign coreFix_memExe_dTlb$EN_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation = 1'd1 ;
assign coreFix_memExe_dTlb$EN_perf_setStatus = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_req = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_resp = 1'b0 ;
// submodule coreFix_memExe_dispToRegQ
assign coreFix_memExe_dispToRegQ$enq_x =
{ coreFix_memExe_rsMem$dispatchData[106:72],
coreFix_memExe_rsMem$dispatchData[65:21],
coreFix_memExe_rsMem$dispatchData[71:66],
coreFix_memExe_rsMem$dispatchData[20:9] } ;
assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN =
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_lsq
assign coreFix_memExe_lsq$enqLd_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqLd_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqLd_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqLd_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h685237 ;
assign coreFix_memExe_lsq$enqSt_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqSt_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqSt_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqSt_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h685237 ;
assign coreFix_memExe_lsq$getHit_t =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 :
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 ;
assign coreFix_memExe_lsq$getOrigBE_t =
coreFix_memExe_regToExeQ$first[145:140] ;
assign coreFix_memExe_lsq$issueLd_lsqTag =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[76:72] :
coreFix_memExe_issueLd$wget[76:72] ;
assign coreFix_memExe_lsq$issueLd_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_lsq$issueLd_sbRes =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 :
coreFix_memExe_stb$search ;
assign coreFix_memExe_lsq$issueLd_shiftedBE =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_lsq$respLd_alignedData =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ;
assign coreFix_memExe_lsq$respLd_t =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ;
assign coreFix_memExe_lsq$setAtCommit_0_put =
rob$deqPort_0_deq_data[24:19] ;
assign coreFix_memExe_lsq$setAtCommit_1_put =
rob$deqPort_1_deq_data[24:19] ;
assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_lsq$updateAddr_fault =
{ (!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] == 3'd2 ||
coreFix_memExe_dTlb$procResp[177:175] == 3'd3 ||
coreFix_memExe_dTlb$procResp[12] :
coreFix_memExe_dTlb$procResp[12] ||
coreFix_memExe_dTlb$procResp[182],
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1861 } ;
assign coreFix_memExe_lsq$updateAddr_isMMIO =
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735 ;
assign coreFix_memExe_lsq$updateAddr_lsqTag =
coreFix_memExe_dTlb$procResp[162:157] ;
assign coreFix_memExe_lsq$updateAddr_paddr =
coreFix_memExe_dTlb$procResp[246:183] ;
assign coreFix_memExe_lsq$updateAddr_shiftedBE =
coreFix_memExe_dTlb$procResp[156:149] ;
assign coreFix_memExe_lsq$updateData_d =
(coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ?
coreFix_memExe_regToExeQ$first[75:12] :
shiftData__h181566 ;
assign coreFix_memExe_lsq$updateData_t =
coreFix_memExe_regToExeQ$first[143:140] ;
assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_lsq$EN_enqLd =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ;
assign coreFix_memExe_lsq$EN_enqSt =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo2 ;
assign coreFix_memExe_lsq$EN_getHit =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign coreFix_memExe_lsq$EN_updateData =
WILL_FIRE_RL_coreFix_memExe_doExeMem &&
coreFix_memExe_regToExeQ$first[145] ;
assign coreFix_memExe_lsq$EN_updateAddr =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_lsq$EN_issueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign coreFix_memExe_lsq$EN_getIssueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ;
assign coreFix_memExe_lsq$EN_respLd =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
assign coreFix_memExe_lsq$EN_deqLd =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign coreFix_memExe_lsq$EN_deqSt =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ;
assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_lsq$EN_setAtCommit_0_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
assign coreFix_memExe_lsq$EN_setAtCommit_1_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
assign coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_regToExeQ
assign coreFix_memExe_regToExeQ$enq_x =
{ coreFix_memExe_dispToRegQ$first[97:63],
coreFix_memExe_dispToRegQ$first[29:12],
x__h181475,
x__h181476,
coreFix_memExe_dispToRegQ$first[11:0] } ;
assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_regToExeQ$EN_deq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_full_dummy2_0
assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_full_dummy2_1
assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_full_dummy2_2
assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN =
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_rsMem
assign coreFix_memExe_rsMem$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14118) ?
{ fetchStage$pipelines_0_first[191:189],
IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14134,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[191:189],
IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h685237,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_memExe_rsMem$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_memExe_rsMem$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_memExe_rsMem$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_memExe_rsMem$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo12 ;
assign coreFix_memExe_rsMem$EN_setRobEnqTime = 1'd1 ;
assign coreFix_memExe_rsMem$EN_doDispatch =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_rsMem$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign coreFix_memExe_rsMem$EN_setRegReady_3_put =
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_memExe_rsMem$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_stb
assign coreFix_memExe_stb$deq_idx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ;
assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ;
assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$getEnqIndex_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ;
assign coreFix_memExe_stb$noMatchLdQ_paddr =
coreFix_memExe_lsq$firstLd[80:17] ;
assign coreFix_memExe_stb$noMatchStQ_be =
coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$noMatchStQ_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$search_be =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_stb$search_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_stb$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ;
assign coreFix_memExe_stb$EN_deq =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_trainBPQ_0
assign coreFix_trainBPQ_0$D_IN =
MUX_coreFix_trainBPQ_0$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_0$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ;
assign coreFix_trainBPQ_0$ENQ =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign coreFix_trainBPQ_0$CLR = 1'b0 ;
// submodule coreFix_trainBPQ_1
assign coreFix_trainBPQ_1$D_IN =
MUX_coreFix_trainBPQ_1$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_1$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ;
assign coreFix_trainBPQ_1$ENQ =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ;
assign coreFix_trainBPQ_1$CLR = 1'b0 ;
// submodule csrInstOrInterruptInflight_dummy2_0
assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
(commitStage_commitTrap[36] ||
commitStage_commitTrap[35:32] == 4'd3) ;
// submodule csrInstOrInterruptInflight_dummy2_1
assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_1$EN =
csrInstOrInterruptInflight_lat_1$whas ;
// submodule csrf_mcycle_ehr_data_dummy2_0
assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2816 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd30 ;
// submodule csrf_mcycle_ehr_data_dummy2_1
assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ;
// submodule csrf_minstret_ehr_data_dummy2_0
assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2818 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd31 ;
// submodule csrf_minstret_ehr_data_dummy2_1
assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_1$EN =
csrf_minstret_ehr_data_dummy_1_0$whas ;
// submodule csrf_stats_module_writeQ
assign csrf_stats_module_writeQ$D_IN =
MUX_csrf_stats_module_writeQ$enq_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_stats_module_writeQ$ENQ =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2049 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd7 ;
assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ;
assign csrf_stats_module_writeQ$CLR = 1'b0 ;
// submodule csrf_terminate_module_terminateQ
assign csrf_terminate_module_terminateQ$ENQ =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2048 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd6 ;
assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ;
assign csrf_terminate_module_terminateQ$CLR = 1'b0 ;
// submodule epochManager
assign epochManager$checkEpoch_0_check_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$checkEpoch_1_check_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$updatePrevEpoch_0_update_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$updatePrevEpoch_1_update_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$EN_updatePrevEpoch_0_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign epochManager$EN_updatePrevEpoch_1_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205 &&
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 ;
assign epochManager$EN_incrementEpoch =
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
// submodule f_csr_reqs
assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ;
assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ;
assign f_csr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_csr_access_busy ||
WILL_FIRE_RL_rl_debug_csr_write ||
WILL_FIRE_RL_rl_debug_csr_read ;
assign f_csr_reqs$CLR = 1'b0 ;
// submodule f_csr_rsps
always@(WILL_FIRE_RL_rl_debug_csr_access_busy or
WILL_FIRE_RL_rl_debug_csr_write or
WILL_FIRE_RL_rl_debug_csr_read or MUX_f_csr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_csr_access_busy:
f_csr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_csr_write:
f_csr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_csr_read:
f_csr_rsps$D_IN = MUX_f_csr_rsps$enq_1__VAL_3;
default: f_csr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_csr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_csr_access_busy ||
WILL_FIRE_RL_rl_debug_csr_write ||
WILL_FIRE_RL_rl_debug_csr_read ;
assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ;
assign f_csr_rsps$CLR = 1'b0 ;
// submodule f_fpr_reqs
assign f_fpr_reqs$D_IN = hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$ENQ = EN_hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_fpr_access_busy ||
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign f_fpr_reqs$CLR = 1'b0 ;
// submodule f_fpr_rsps
always@(WILL_FIRE_RL_rl_debug_fpr_access_busy or
WILL_FIRE_RL_rl_debug_fpr_write or
WILL_FIRE_RL_rl_debug_fpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_fpr_access_busy:
f_fpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_fpr_write:
f_fpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_fpr_read:
f_fpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
default: f_fpr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fpr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_fpr_access_busy ||
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign f_fpr_rsps$DEQ = EN_hart0_fpr_mem_server_response_get ;
assign f_fpr_rsps$CLR = 1'b0 ;
// submodule f_gpr_reqs
assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_gpr_access_busy ||
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign f_gpr_reqs$CLR = 1'b0 ;
// submodule f_gpr_rsps
always@(WILL_FIRE_RL_rl_debug_gpr_access_busy or
WILL_FIRE_RL_rl_debug_gpr_write or
WILL_FIRE_RL_rl_debug_gpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_gpr_access_busy:
f_gpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_gpr_write:
f_gpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_gpr_read:
f_gpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
default: f_gpr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_gpr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_gpr_access_busy ||
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ;
assign f_gpr_rsps$CLR = 1'b0 ;
// submodule f_run_halt_reqs
assign f_run_halt_reqs$D_IN = hart0_run_halt_server_request_put ;
assign f_run_halt_reqs$ENQ = EN_hart0_run_halt_server_request_put ;
assign f_run_halt_reqs$DEQ =
WILL_FIRE_RL_rl_debug_run_redundant ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_rl_debug_halt_req_already_halted ||
WILL_FIRE_RL_rl_debug_halt_req ;
assign f_run_halt_reqs$CLR = 1'b0 ;
// submodule f_run_halt_rsps
assign f_run_halt_rsps$D_IN = !WILL_FIRE_RL_rl_debug_halted ;
assign f_run_halt_rsps$ENQ =
WILL_FIRE_RL_rl_debug_halted ||
WILL_FIRE_RL_rl_debug_run_redundant ||
WILL_FIRE_RL_rl_debug_resume ;
assign f_run_halt_rsps$DEQ = EN_hart0_run_halt_server_response_get ;
assign f_run_halt_rsps$CLR = 1'b0 ;
// submodule fetchStage
assign fetchStage$iMemIfc_perf_req_r = 2'h0 ;
assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iMemIfc_to_parent_fromP_enq_x =
iCacheToParent_fromP_enq_x ;
assign fetchStage$iMemIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_perf_req_r = 3'h0 ;
assign fetchStage$iTlbIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iTlbIfc_toParent_rsFromP_enq_x =
l2Tlb$toChildren_rsToC_first[80:0] ;
assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_updateVMInfo_vm =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 :
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ;
assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ;
assign fetchStage$mmioIfc_setHtifAddrs_fromHost =
coreReq_start_fromHostAddr ;
assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ;
assign fetchStage$perf_req_r = 2'h0 ;
assign fetchStage$perf_setStatus_doStats = 1'b0 ;
always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
pc__h711407 or
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
WILL_FIRE_RL_commitStage_doCommitKilledLd or
rob$deqPort_0_deq_data or
WILL_FIRE_RL_rl_debug_resume or
csrf_rg_dpc or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
MUX_fetchStage$redirect_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_commitStage_rg_serial_num$write_1__SEL_1:
fetchStage$redirect_pc = pc__h711407;
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19];
WILL_FIRE_RL_commitStage_doCommitKilledLd:
fetchStage$redirect_pc = rob$deqPort_0_deq_data[425:362];
WILL_FIRE_RL_rl_debug_resume: fetchStage$redirect_pc = csrf_rg_dpc;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_6;
default: fetchStage$redirect_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fetchStage$start_pc = coreReq_start_startpc ;
assign fetchStage$train_predictors_dpTrain =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[25:2] :
coreFix_trainBPQ_0$D_OUT[25:2] ;
assign fetchStage$train_predictors_iType =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[31:27] :
coreFix_trainBPQ_0$D_OUT[31:27] ;
assign fetchStage$train_predictors_isCompressed =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[0] :
coreFix_trainBPQ_0$D_OUT[0] ;
assign fetchStage$train_predictors_mispred =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[1] :
coreFix_trainBPQ_0$D_OUT[1] ;
assign fetchStage$train_predictors_next_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[95:32] :
coreFix_trainBPQ_0$D_OUT[95:32] ;
assign fetchStage$train_predictors_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[159:96] :
coreFix_trainBPQ_0$D_OUT[159:96] ;
assign fetchStage$train_predictors_taken =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[26] :
coreFix_trainBPQ_0$D_OUT[26] ;
assign fetchStage$EN_pipelines_0_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_pipelines_1_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205 &&
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 ;
assign fetchStage$EN_iTlbIfc_flush =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_rl_debug_resume ;
assign fetchStage$EN_iTlbIfc_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ;
assign fetchStage$EN_iTlbIfc_toParent_rsFromP_enq =
CAN_FIRE_RL_sendRsToITlb ;
assign fetchStage$EN_iTlbIfc_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign fetchStage$EN_iTlbIfc_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign fetchStage$EN_iTlbIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iMemIfc_flush = CAN_FIRE_RL_setDoFlushCaches ;
assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_parent_rsToP_deq =
EN_iCacheToParent_rsToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_rqToP_deq =
EN_iCacheToParent_rqToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_fromP_enq =
EN_iCacheToParent_fromP_enq ;
assign fetchStage$EN_iMemIfc_cRqStuck_get = EN_deadlock_iCacheCRqStuck_get ;
assign fetchStage$EN_iMemIfc_pRqStuck_get = EN_deadlock_iCachePRqStuck_get ;
assign fetchStage$EN_mmioIfc_instReq_deq = WILL_FIRE_RL_mmio_sendInstReq ;
assign fetchStage$EN_mmioIfc_instResp_enq = CAN_FIRE_RL_mmio_sendInstResp ;
assign fetchStage$EN_mmioIfc_setHtifAddrs = EN_coreReq_start ;
assign fetchStage$EN_start = EN_coreReq_start ;
assign fetchStage$EN_stop = 1'b0 ;
assign fetchStage$EN_setWaitRedirect =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_redirect =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign fetchStage$EN_setWaitFlush =
MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ;
assign fetchStage$EN_train_predictors =
coreFix_trainBPQ_1$EMPTY_N ||
WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ;
assign fetchStage$EN_perf_setStatus = 1'b0 ;
assign fetchStage$EN_perf_req = 1'b0 ;
assign fetchStage$EN_perf_resp = 1'b0 ;
// submodule l2Tlb
assign l2Tlb$perf_req_r = 4'h0 ;
assign l2Tlb$perf_setStatus_doStats = 1'b0 ;
assign l2Tlb$toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq ?
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 :
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ;
assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ;
assign l2Tlb$updateVMInfo_vmD =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
assign l2Tlb$updateVMInfo_vmI =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 :
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ;
assign l2Tlb$EN_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign l2Tlb$EN_toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ;
assign l2Tlb$EN_toChildren_rsToC_deq =
WILL_FIRE_RL_sendRsToITlb || WILL_FIRE_RL_sendRsToDTlb ;
assign l2Tlb$EN_toChildren_iTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign l2Tlb$EN_toChildren_dTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut ;
assign l2Tlb$EN_toChildren_flushDone_get = CAN_FIRE_RL_sendFlushDone ;
assign l2Tlb$EN_toMem_memReq_deq = EN_tlbToMem_memReq_deq ;
assign l2Tlb$EN_toMem_respLd_enq = EN_tlbToMem_respLd_enq ;
assign l2Tlb$EN_perf_setStatus = 1'b0 ;
assign l2Tlb$EN_perf_req = 1'b0 ;
assign l2Tlb$EN_perf_resp = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_0
assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_1
assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRqQ_deqReq_dummy2_0
assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ;
// submodule mmio_cRqQ_deqReq_dummy2_1
assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_deqReq_dummy2_2
assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRqQ_enqReq_dummy2_0
assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_cRqQ_enqReq_dummy2_1
assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_enqReq_dummy2_2
assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_clearReq_dummy2_0
assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRsQ_clearReq_dummy2_1
assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRsQ_deqReq_dummy2_0
assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ;
// submodule mmio_cRsQ_deqReq_dummy2_1
assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_deqReq_dummy2_2
assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_enqReq_dummy2_0
assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_cRsQ_enqReq_dummy2_1
assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_enqReq_dummy2_2
assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_clearReq_dummy2_0
assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataPendQ_clearReq_dummy2_1
assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataPendQ_deqReq_dummy2_0
assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataPendQ_deqReq_dummy2_1
assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_deqReq_dummy2_2
assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_enqReq_dummy2_0
assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_0$EN =
mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataPendQ_enqReq_dummy2_1
assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_enqReq_dummy2_2
assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_clearReq_dummy2_0
assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataReqQ_clearReq_dummy2_1
assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataReqQ_deqReq_dummy2_0
assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_dataReqQ_deqReq_dummy2_1
assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_deqReq_dummy2_2
assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_enqReq_dummy2_0
assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataReqQ_enqReq_dummy2_1
assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_enqReq_dummy2_2
assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_clearReq_dummy2_0
assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataRespQ_clearReq_dummy2_1
assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataRespQ_deqReq_dummy2_0
assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataRespQ_deqReq_dummy2_1
assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_deqReq_dummy2_2
assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_enqReq_dummy2_0
assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ;
// submodule mmio_dataRespQ_enqReq_dummy2_1
assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_enqReq_dummy2_2
assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_clearReq_dummy2_0
assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRqQ_clearReq_dummy2_1
assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRqQ_deqReq_dummy2_0
assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_pRqQ_deqReq_dummy2_1
assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_deqReq_dummy2_2
assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_enqReq_dummy2_0
assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ;
// submodule mmio_pRqQ_enqReq_dummy2_1
assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_enqReq_dummy2_2
assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_clearReq_dummy2_0
assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRsQ_clearReq_dummy2_1
assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRsQ_deqReq_dummy2_0
assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_lat_0$whas ;
// submodule mmio_pRsQ_deqReq_dummy2_1
assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_deqReq_dummy2_2
assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_enqReq_dummy2_0
assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ;
// submodule mmio_pRsQ_enqReq_dummy2_1
assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_enqReq_dummy2_2
assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule perfReqQ
assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ;
assign perfReqQ$ENQ = EN_coreReq_perfReq ;
assign perfReqQ$DEQ = EN_coreIndInv_perfResp ;
assign perfReqQ$CLR = 1'b0 ;
// submodule regRenamingTable
assign regRenamingTable$rename_0_claimRename_r =
fetchStage$pipelines_0_first[95:69] ;
assign regRenamingTable$rename_0_claimRename_sb =
specTagManager$currentSpecBits ;
always@(MUX_regRenamingTable$rename_0_getRename_1__SEL_1 or
fetchStage$pipelines_0_first or
MUX_regRenamingTable$rename_0_getRename_1__SEL_2 or
MUX_regRenamingTable$rename_0_getRename_1__VAL_2 or
MUX_regRenamingTable$rename_0_getRename_1__SEL_3 or
MUX_regRenamingTable$rename_0_getRename_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_regRenamingTable$rename_0_getRename_1__SEL_1:
regRenamingTable$rename_0_getRename_r =
fetchStage$pipelines_0_first[95:69];
MUX_regRenamingTable$rename_0_getRename_1__SEL_2:
regRenamingTable$rename_0_getRename_r =
MUX_regRenamingTable$rename_0_getRename_1__VAL_2;
MUX_regRenamingTable$rename_0_getRename_1__SEL_3:
regRenamingTable$rename_0_getRename_r =
MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
default: regRenamingTable$rename_0_getRename_r =
27'b010101010101010101010101010 /* unspecified value */ ;
endcase
end
assign regRenamingTable$rename_1_claimRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$rename_1_claimRename_sb =
renaming_spec_bits__h685237 ;
assign regRenamingTable$rename_1_getRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign regRenamingTable$EN_rename_0_claimRename =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign regRenamingTable$EN_rename_1_claimRename =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign regRenamingTable$EN_commit_0_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign regRenamingTable$EN_commit_1_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] != 5'd0 &&
rob$deqPort_1_deq_data[329:325] != 5'd21 &&
rob$deqPort_1_deq_data[329:325] != 5'd17 &&
rob$deqPort_1_deq_data[329:325] != 5'd18 &&
rob$deqPort_1_deq_data[329:325] != 5'd13 &&
rob$deqPort_1_deq_data[329:325] != 5'd16 &&
rob$deqPort_1_deq_data[329:325] != 5'd15 &&
rob$deqPort_1_deq_data[329:325] != 5'd19 &&
rob$deqPort_1_deq_data[329:325] != 5'd20 ;
assign regRenamingTable$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign regRenamingTable$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule rf
assign rf$read_0_rd1_rindx = coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign rf$read_0_rd2_rindx = coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign rf$read_0_rd3_rindx = 7'h0 ;
assign rf$read_1_rd1_rindx = coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign rf$read_1_rd2_rindx = coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign rf$read_1_rd3_rindx = 7'h0 ;
assign rf$read_2_rd1_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign rf$read_2_rd2_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign rf$read_2_rd3_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ;
assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ;
assign rf$read_3_rd3_rindx = 7'h0 ;
assign rf$read_4_rd1_rindx = regRenamingTable$rename_0_getRename[31:25] ;
assign rf$read_4_rd2_rindx = 7'h0 ;
assign rf$read_4_rd3_rindx = 7'h0 ;
assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ;
assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ;
assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_rf$write_2_wr_2__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_rf$write_2_wr_2__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_rf$write_2_wr_2__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_rf$write_2_wr_2__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_rf$write_2_wr_2__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_data =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6;
default: rf$write_2_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_1 or
coreFix_memExe_respLrScAmoQ_data_0 or
MUX_rf$write_3_wr_1__SEL_2 or
mmio_dataRespQ_data_0 or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_2__VAL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_2__VAL_4 or
MUX_rf$write_3_wr_2__SEL_5 or coreFix_memExe_lsq$respLd)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_1:
rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0;
MUX_rf$write_3_wr_1__SEL_2:
rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0];
MUX_rf$write_3_wr_1__SEL_3:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_3;
MUX_rf$write_3_wr_1__SEL_4:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4;
MUX_rf$write_3_wr_2__SEL_5:
rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0];
default: rf$write_3_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_5 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
coreFix_memExe_lsq$firstLd or
MUX_rf$write_3_wr_1__SEL_1 or
MUX_rf$write_3_wr_1__SEL_2 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_5:
rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[83:77];
MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82];
MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143];
default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
assign rf$write_4_wr_data =
WILL_FIRE_RL_rl_debug_gpr_write ?
f_gpr_reqs$D_OUT[63:0] :
f_fpr_reqs$D_OUT[63:0] ;
assign rf$write_4_wr_rindx = regRenamingTable$rename_0_getRename[31:25] ;
assign rf$EN_write_0_wr =
_dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[321] ;
assign rf$EN_write_1_wr =
_dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[321] ;
assign rf$EN_write_2_wr =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign rf$EN_write_3_wr =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ||
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[84] ;
assign rf$EN_write_4_wr =
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_fpr_write ;
// submodule rob
always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or
MUX_rob$enqPort_0_enq_1__VAL_1 or
WILL_FIRE_RL_renameStage_doRenaming_Trap or
MUX_rob$enqPort_0_enq_1__VAL_2 or
WILL_FIRE_RL_renameStage_doRenaming_SystemInst or
MUX_rob$enqPort_0_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_1;
WILL_FIRE_RL_renameStage_doRenaming_Trap:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_2;
WILL_FIRE_RL_renameStage_doRenaming_SystemInst:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3;
default: rob$enqPort_0_enq_x =
426'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rob$enqPort_1_enq_x =
{ fetchStage$pipelines_1_first[387:324],
fetchStage$pipelines_1_first[127:96],
fetchStage$pipelines_1_first[199:195],
fetchStage$pipelines_1_first[75:69],
136'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676,
73'h1280000000000000000,
fetchStage$pipelines_1_first[323:260],
5'd0,
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74],
fetchStage$pipelines_1_first[194:192] != 3'd0 &&
fetchStage$pipelines_1_first[194:192] != 3'd1 &&
fetchStage$pipelines_1_first[194:192] != 3'd2 &&
fetchStage$pipelines_1_first[194:192] != 3'd3 &&
fetchStage$pipelines_1_first[194:192] != 3'd4,
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14296 ||
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259,
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306,
7'd32,
renaming_spec_bits__h685237 } ;
assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_2_get_x = 12'h0 ;
assign rob$getOrigPredPC_0_get_x =
coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPredPC_1_get_x =
coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
always@(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or
MUX_rob$setExecuted_deqLSQ_1__SEL_5 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_3;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
MUX_rob$setExecuted_deqLSQ_1__SEL_5:
rob$setExecuted_deqLSQ_cause = 5'd10;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd21;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd23;
default: rob$setExecuted_deqLSQ_cause =
5'b01010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_deqLSQ_ld_killed =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ?
coreFix_memExe_lsq$firstLd[2:0] :
3'd2 ;
assign rob$setExecuted_deqLSQ_x =
(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ?
coreFix_memExe_lsq$firstLd[113:102] :
coreFix_memExe_lsq$firstSt[170:159] ;
assign rob$setExecuted_doFinishAlu_0_set_cf =
coreFix_aluExe_0_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_0_set_csrData =
coreFix_aluExe_0_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_0_set_dst_data =
coreFix_aluExe_0_exeToFinQ$first[275:212] ;
assign rob$setExecuted_doFinishAlu_0_set_x =
coreFix_aluExe_0_exeToFinQ$first[312:301] ;
assign rob$setExecuted_doFinishAlu_1_set_cf =
coreFix_aluExe_1_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_1_set_csrData =
coreFix_aluExe_1_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_1_set_dst_data =
coreFix_aluExe_1_exeToFinQ$first[275:212] ;
assign rob$setExecuted_doFinishAlu_1_set_x =
coreFix_aluExe_1_exeToFinQ$first[312:301] ;
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
MUX_rf$write_2_wr_2__VAL_2 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
MUX_rf$write_2_wr_2__VAL_3 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
MUX_rf$write_2_wr_2__VAL_4 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
MUX_rf$write_2_wr_2__VAL_5 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
MUX_rf$write_2_wr_2__VAL_6)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_2;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_3;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_4;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_5;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
MUX_rf$write_2_wr_2__VAL_6;
default: rob$setExecuted_doFinishFpuMulDiv_0_set_dst_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_2;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_3;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_3__VAL_4;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0;
default: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
5'b01010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[23:12];
default: rob$setExecuted_doFinishFpuMulDiv_0_set_x =
12'b101010101010 /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_1 or
coreFix_memExe_respLrScAmoQ_data_0 or
MUX_rf$write_3_wr_1__SEL_2 or
mmio_dataRespQ_data_0 or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_2__VAL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_2__VAL_4 or
MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5 or
coreFix_memExe_lsq$respLd)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_1:
rob$setExecuted_doFinishMem_RegData_dst_data =
coreFix_memExe_respLrScAmoQ_data_0;
MUX_rf$write_3_wr_1__SEL_2:
rob$setExecuted_doFinishMem_RegData_dst_data =
mmio_dataRespQ_data_0[63:0];
MUX_rf$write_3_wr_1__SEL_3:
rob$setExecuted_doFinishMem_RegData_dst_data =
MUX_rf$write_3_wr_2__VAL_3;
MUX_rf$write_3_wr_1__SEL_4:
rob$setExecuted_doFinishMem_RegData_dst_data =
MUX_rf$write_3_wr_2__VAL_4;
MUX_rob$setExecuted_doFinishMem_RegData_2__SEL_5:
rob$setExecuted_doFinishMem_RegData_dst_data =
coreFix_memExe_lsq$respLd[63:0];
default: rob$setExecuted_doFinishMem_RegData_dst_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
coreFix_memExe_lsq$firstLd or
MUX_rf$write_3_wr_1__SEL_1 or
MUX_rf$write_3_wr_1__SEL_2 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_rob$setExecuted_doFinishMem_RegData_1__SEL_5:
rob$setExecuted_doFinishMem_RegData_x =
coreFix_memExe_lsq$respLd[75:64];
MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4:
rob$setExecuted_doFinishMem_RegData_x =
coreFix_memExe_lsq$firstLd[113:102];
MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2:
rob$setExecuted_doFinishMem_RegData_x =
coreFix_memExe_lsq$firstSt[170:159];
default: rob$setExecuted_doFinishMem_RegData_x =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_doFinishMem_access_at_commit =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 &&
(coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735 ||
coreFix_memExe_dTlb$procResp[177:175] == 3'd2 ||
coreFix_memExe_dTlb$procResp[177:175] == 3'd3 ||
coreFix_memExe_dTlb$procResp[177:175] == 3'd4) ;
assign rob$setExecuted_doFinishMem_non_mmio_st_done =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 &&
NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755 &&
coreFix_memExe_dTlb$procResp[177:175] == 3'd1 ;
assign rob$setExecuted_doFinishMem_store_data =
coreFix_memExe_dTlb$procResp[84:21] ;
assign rob$setExecuted_doFinishMem_store_data_BE =
coreFix_memExe_dTlb$procResp[20:13] ;
assign rob$setExecuted_doFinishMem_vaddr =
coreFix_memExe_dTlb$procResp[148:85] ;
assign rob$setExecuted_doFinishMem_x =
coreFix_memExe_dTlb$procResp[174:163] ;
assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ;
assign rob$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_1_exeToFinQ$first[312:301];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_0_exeToFinQ$first[312:301];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign rob$EN_enqPort_0_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign rob$EN_enqPort_1_enq =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign rob$EN_deqPort_0_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign rob$EN_deqPort_1_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] != 5'd0 &&
rob$deqPort_1_deq_data[329:325] != 5'd21 &&
rob$deqPort_1_deq_data[329:325] != 5'd17 &&
rob$deqPort_1_deq_data[329:325] != 5'd18 &&
rob$deqPort_1_deq_data[329:325] != 5'd13 &&
rob$deqPort_1_deq_data[329:325] != 5'd16 &&
rob$deqPort_1_deq_data[329:325] != 5'd15 &&
rob$deqPort_1_deq_data[329:325] != 5'd19 &&
rob$deqPort_1_deq_data[329:325] != 5'd20 ;
assign rob$EN_setLSQAtCommitNotified =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
assign rob$EN_setExecuted_deqLSQ =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ;
assign rob$EN_setExecuted_doFinishAlu_0_set =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishAlu_1_set =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishFpuMulDiv_0_set =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign rob$EN_setExecuted_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign rob$EN_setExecuted_doFinishMem_RegData =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ||
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[84] ;
assign rob$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign rob$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule sbAggr
assign sbAggr$eagerLookup_0_get_r = regRenamingTable$rename_0_getRename ;
assign sbAggr$eagerLookup_1_get_r = regRenamingTable$rename_1_getRename ;
assign sbAggr$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbAggr$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ;
assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or
coreFix_memExe_lsq$getHit or
MUX_sbAggr$setReady_4_put_1__SEL_2 or
coreFix_memExe_lsq$firstLd or
MUX_sbAggr$setReady_4_put_1__SEL_1 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 ||
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1];
MUX_sbAggr$setReady_4_put_1__SEL_2:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82];
MUX_sbAggr$setReady_4_put_1__SEL_1:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143];
default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbAggr$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbAggr$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign sbAggr$EN_setReady_3_put =
_dor1sbAggr$EN_setReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign sbAggr$EN_setReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
// submodule sbCons
assign sbCons$eagerLookup_0_get_r = 33'h0 ;
assign sbCons$eagerLookup_1_get_r = 33'h0 ;
assign sbCons$lazyLookup_0_get_r =
coreFix_aluExe_0_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_1_get_r =
coreFix_aluExe_1_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_2_get_r =
coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ;
assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ;
assign sbCons$lazyLookup_4_get_r = 33'h0 ;
assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_sbCons$setReady_3_put_1__SEL_1 or
coreFix_memExe_lsq$firstSt or
MUX_sbCons$setReady_3_put_1__SEL_2 or
coreFix_memExe_lsq$firstLd or
MUX_sbCons$setReady_3_put_1__SEL_3 or coreFix_memExe_lsq$respLd)
begin
case (1'b1) // synopsys parallel_case
MUX_sbCons$setReady_3_put_1__SEL_1:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143];
MUX_sbCons$setReady_3_put_1__SEL_2:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82];
MUX_sbCons$setReady_3_put_1__SEL_3:
sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[83:77];
default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbCons$setReady_4_put = 7'h0 ;
assign sbCons$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbCons$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbCons$EN_setReady_0_put =
_dor1sbCons$EN_setReady_0_put &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign sbCons$EN_setReady_1_put =
_dor1sbCons$EN_setReady_1_put &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign sbCons$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign sbCons$EN_setReady_3_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[84] ;
assign sbCons$EN_setReady_4_put = 1'b0 ;
// submodule specTagManager
assign specTagManager$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 ;
assign specTagManager$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign specTagManager$EN_claimSpecTag =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14152 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14283) ;
assign specTagManager$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule v_f_to_TV_0
always@(MUX_commitStage_rg_serial_num$write_1__SEL_1 or
MUX_v_f_to_TV_0$enq_1__VAL_1 or
MUX_v_f_to_TV_0$enq_1__SEL_2 or
MUX_v_f_to_TV_0$enq_1__VAL_2 or
WILL_FIRE_RL_commitStage_rl_send_tv_reset or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
MUX_v_f_to_TV_0$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_commitStage_rg_serial_num$write_1__SEL_1:
v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_1;
MUX_v_f_to_TV_0$enq_1__SEL_2:
v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_2;
WILL_FIRE_RL_commitStage_rl_send_tv_reset:
v_f_to_TV_0$D_IN =
785'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
v_f_to_TV_0$D_IN = MUX_v_f_to_TV_0$enq_1__VAL_4;
default: v_f_to_TV_0$D_IN =
785'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign v_f_to_TV_0$ENQ =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_rl_send_tv_reset ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ;
assign v_f_to_TV_0$CLR = 1'b0 ;
// submodule v_f_to_TV_1
assign v_f_to_TV_1$D_IN =
{ commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438,
rob$deqPort_1_deq_data[425:181],
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300,
6'd10,
rob$deqPort_1_deq_data[161:98],
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301,
rob$deqPort_1_deq_data[95:32],
fflags__h729891,
rob$deqPort_1_deq_data[26],
x__h732011,
258'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign v_f_to_TV_1$ENQ =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] != 5'd0 &&
rob$deqPort_1_deq_data[329:325] != 5'd21 &&
rob$deqPort_1_deq_data[329:325] != 5'd17 &&
rob$deqPort_1_deq_data[329:325] != 5'd18 &&
rob$deqPort_1_deq_data[329:325] != 5'd13 &&
rob$deqPort_1_deq_data[329:325] != 5'd16 &&
rob$deqPort_1_deq_data[329:325] != 5'd15 &&
rob$deqPort_1_deq_data[329:325] != 5'd19 &&
rob$deqPort_1_deq_data[329:325] != 5'd20 ;
assign v_f_to_TV_1$DEQ = EN_v_to_TV_1_get ;
assign v_f_to_TV_1$CLR = 1'b0 ;
// remaining internal signals
module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]),
.amoExec_current_data(curData__h192915),
.amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]),
.amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]),
.amoExec(n__h194453));
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32],
3'd0 }),
.amoExec_current_data({ 63'd0,
msip__h76121 }),
.amoExec_in_data({ 32'd0, x__h76236 }),
.amoExec_upper_32_bits(1'd0),
.amoExec(amoExec___d880));
module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228,
{ coreFix_aluExe_0_regToExeQ$first[395],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229,
coreFix_aluExe_0_regToExeQ$first[382],
coreFix_aluExe_0_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]),
.basicExec(basicExec___d12617));
module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231,
{ coreFix_aluExe_1_regToExeQ$first[395],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232,
coreFix_aluExe_1_regToExeQ$first[382],
coreFix_aluExe_1_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]),
.basicExec(basicExec___d11943));
module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883,
{ { fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 },
fetchStage$pipelines_0_first[160],
x_data_imm__h676655 } }),
.checkForException_regs({ fetchStage$pipelines_0_first[95],
fetchStage$pipelines_0_first[94:89],
{ fetchStage$pipelines_0_first[88],
fetchStage$pipelines_0_first[87:82] },
{ fetchStage$pipelines_0_first[81],
fetchStage$pipelines_0_first[80:76],
{ fetchStage$pipelines_0_first[75],
fetchStage$pipelines_0_first[74:69] } } }),
.checkForException_csrState({ x_decodeInfo_frm__h655010,
r1__read_BITS_13_TO_12___h655195 !=
2'd0,
{ prv__h734164,
tvm_val__h725554,
{ r1__read_BIT_20___h655891,
tsr_val__h725552,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d13008));
module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584,
{ fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676,
fetchStage$pipelines_1_first[160],
x_data_imm__h692709 } }),
.checkForException_regs({ fetchStage$pipelines_1_first[95],
fetchStage$pipelines_1_first[94:89],
{ fetchStage$pipelines_1_first[88],
fetchStage$pipelines_1_first[87:82] },
{ fetchStage$pipelines_1_first[81],
fetchStage$pipelines_1_first[80:76],
{ fetchStage$pipelines_1_first[75],
fetchStage$pipelines_1_first[74:69] } } }),
.checkForException_csrState({ x_decodeInfo_frm__h655010,
r1__read_BITS_13_TO_12___h655195 !=
2'd0,
{ prv__h734164,
tvm_val__h725554,
{ r1__read_BIT_20___h655891,
tsr_val__h725552,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d13698));
module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229],
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254,
coreFix_fpuMulDivExe_0_regToExeQ$first[225] }),
.execFpuSimple_rVal1(rVal1__h481760),
.execFpuSimple_rVal2(rVal2__h481761),
.execFpuSimple(execFpuSimple___d11056));
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 ?
_theResult___snd__h354258 :
_theResult____h346084 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 ?
_theResult___snd__h399955 :
_theResult____h391783 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 ?
_theResult___snd__h445650 :
_theResult____h437478 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 ?
_theResult___snd__h511167 :
_theResult____h502868 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 ?
_theResult___snd__h589324 :
_theResult____h581025 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 ?
_theResult___snd__h550020 :
_theResult____h541721 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 ?
_theResult___snd__h463416 :
_theResult____h455115 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 ?
_theResult___snd__h372024 :
_theResult____h363723 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 ?
_theResult___snd__h417721 :
_theResult____h409420 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 ?
_theResult___snd__h501516 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 ?
_theResult___snd__h501516 :
_theResult___snd__h519921 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 ?
_theResult___snd__h579673 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 ?
_theResult___snd__h579673 :
_theResult___snd__h598078 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 ?
_theResult___snd__h540369 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 ?
_theResult___snd__h540369 :
_theResult___snd__h558774 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 ?
_theResult___snd__h454232 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 ?
_theResult___snd__h454232 :
_theResult___snd__h472022 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 ?
_theResult___snd__h362840 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 ?
_theResult___snd__h362840 :
_theResult___snd__h380630 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 ?
_theResult___snd__h408537 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 ?
_theResult___snd__h408537 :
_theResult___snd__h426327 ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
((_theResult___fst_exp__h354195 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054) :
((_theResult___fst_exp__h362851 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
((_theResult___fst_exp__h354195 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110) :
((_theResult___fst_exp__h362851 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
((_theResult___fst_exp__h399892 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446) :
((_theResult___fst_exp__h408548 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
((_theResult___fst_exp__h399892 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502) :
((_theResult___fst_exp__h408548 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
((_theResult___fst_exp__h445587 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838) :
((_theResult___fst_exp__h454243 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
((_theResult___fst_exp__h445587 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894) :
((_theResult___fst_exp__h454243 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901) ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 =
(_theResult____h346084[56] ?
6'd0 :
(_theResult____h346084[55] ?
6'd1 :
(_theResult____h346084[54] ?
6'd2 :
(_theResult____h346084[53] ?
6'd3 :
(_theResult____h346084[52] ?
6'd4 :
(_theResult____h346084[51] ?
6'd5 :
(_theResult____h346084[50] ?
6'd6 :
(_theResult____h346084[49] ?
6'd7 :
(_theResult____h346084[48] ?
6'd8 :
(_theResult____h346084[47] ?
6'd9 :
(_theResult____h346084[46] ?
6'd10 :
(_theResult____h346084[45] ?
6'd11 :
(_theResult____h346084[44] ?
6'd12 :
(_theResult____h346084[43] ?
6'd13 :
(_theResult____h346084[42] ?
6'd14 :
(_theResult____h346084[41] ?
6'd15 :
(_theResult____h346084[40] ?
6'd16 :
(_theResult____h346084[39] ?
6'd17 :
(_theResult____h346084[38] ?
6'd18 :
(_theResult____h346084[37] ?
6'd19 :
(_theResult____h346084[36] ?
6'd20 :
(_theResult____h346084[35] ?
6'd21 :
(_theResult____h346084[34] ?
6'd22 :
(_theResult____h346084[33] ?
6'd23 :
(_theResult____h346084[32] ?
6'd24 :
(_theResult____h346084[31] ?
6'd25 :
(_theResult____h346084[30] ?
6'd26 :
(_theResult____h346084[29] ?
6'd27 :
(_theResult____h346084[28] ?
6'd28 :
(_theResult____h346084[27] ?
6'd29 :
(_theResult____h346084[26] ?
6'd30 :
(_theResult____h346084[25] ?
6'd31 :
(_theResult____h346084[24] ?
6'd32 :
(_theResult____h346084[23] ?
6'd33 :
(_theResult____h346084[22] ?
6'd34 :
(_theResult____h346084[21] ?
6'd35 :
(_theResult____h346084[20] ?
6'd36 :
(_theResult____h346084[19] ?
6'd37 :
(_theResult____h346084[18] ?
6'd38 :
(_theResult____h346084[17] ?
6'd39 :
(_theResult____h346084[16] ?
6'd40 :
(_theResult____h346084[15] ?
6'd41 :
(_theResult____h346084[14] ?
6'd42 :
(_theResult____h346084[13] ?
6'd43 :
(_theResult____h346084[12] ?
6'd44 :
(_theResult____h346084[11] ?
6'd45 :
(_theResult____h346084[10] ?
6'd46 :
(_theResult____h346084[9] ?
6'd47 :
(_theResult____h346084[8] ?
6'd48 :
(_theResult____h346084[7] ?
6'd49 :
(_theResult____h346084[6] ?
6'd50 :
(_theResult____h346084[5] ?
6'd51 :
(_theResult____h346084[4] ?
6'd52 :
(_theResult____h346084[3] ?
6'd53 :
(_theResult____h346084[2] ?
6'd54 :
(_theResult____h346084[1] ?
6'd55 :
(_theResult____h346084[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 =
(_theResult____h391783[56] ?
6'd0 :
(_theResult____h391783[55] ?
6'd1 :
(_theResult____h391783[54] ?
6'd2 :
(_theResult____h391783[53] ?
6'd3 :
(_theResult____h391783[52] ?
6'd4 :
(_theResult____h391783[51] ?
6'd5 :
(_theResult____h391783[50] ?
6'd6 :
(_theResult____h391783[49] ?
6'd7 :
(_theResult____h391783[48] ?
6'd8 :
(_theResult____h391783[47] ?
6'd9 :
(_theResult____h391783[46] ?
6'd10 :
(_theResult____h391783[45] ?
6'd11 :
(_theResult____h391783[44] ?
6'd12 :
(_theResult____h391783[43] ?
6'd13 :
(_theResult____h391783[42] ?
6'd14 :
(_theResult____h391783[41] ?
6'd15 :
(_theResult____h391783[40] ?
6'd16 :
(_theResult____h391783[39] ?
6'd17 :
(_theResult____h391783[38] ?
6'd18 :
(_theResult____h391783[37] ?
6'd19 :
(_theResult____h391783[36] ?
6'd20 :
(_theResult____h391783[35] ?
6'd21 :
(_theResult____h391783[34] ?
6'd22 :
(_theResult____h391783[33] ?
6'd23 :
(_theResult____h391783[32] ?
6'd24 :
(_theResult____h391783[31] ?
6'd25 :
(_theResult____h391783[30] ?
6'd26 :
(_theResult____h391783[29] ?
6'd27 :
(_theResult____h391783[28] ?
6'd28 :
(_theResult____h391783[27] ?
6'd29 :
(_theResult____h391783[26] ?
6'd30 :
(_theResult____h391783[25] ?
6'd31 :
(_theResult____h391783[24] ?
6'd32 :
(_theResult____h391783[23] ?
6'd33 :
(_theResult____h391783[22] ?
6'd34 :
(_theResult____h391783[21] ?
6'd35 :
(_theResult____h391783[20] ?
6'd36 :
(_theResult____h391783[19] ?
6'd37 :
(_theResult____h391783[18] ?
6'd38 :
(_theResult____h391783[17] ?
6'd39 :
(_theResult____h391783[16] ?
6'd40 :
(_theResult____h391783[15] ?
6'd41 :
(_theResult____h391783[14] ?
6'd42 :
(_theResult____h391783[13] ?
6'd43 :
(_theResult____h391783[12] ?
6'd44 :
(_theResult____h391783[11] ?
6'd45 :
(_theResult____h391783[10] ?
6'd46 :
(_theResult____h391783[9] ?
6'd47 :
(_theResult____h391783[8] ?
6'd48 :
(_theResult____h391783[7] ?
6'd49 :
(_theResult____h391783[6] ?
6'd50 :
(_theResult____h391783[5] ?
6'd51 :
(_theResult____h391783[4] ?
6'd52 :
(_theResult____h391783[3] ?
6'd53 :
(_theResult____h391783[2] ?
6'd54 :
(_theResult____h391783[1] ?
6'd55 :
(_theResult____h391783[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 =
(_theResult____h437478[56] ?
6'd0 :
(_theResult____h437478[55] ?
6'd1 :
(_theResult____h437478[54] ?
6'd2 :
(_theResult____h437478[53] ?
6'd3 :
(_theResult____h437478[52] ?
6'd4 :
(_theResult____h437478[51] ?
6'd5 :
(_theResult____h437478[50] ?
6'd6 :
(_theResult____h437478[49] ?
6'd7 :
(_theResult____h437478[48] ?
6'd8 :
(_theResult____h437478[47] ?
6'd9 :
(_theResult____h437478[46] ?
6'd10 :
(_theResult____h437478[45] ?
6'd11 :
(_theResult____h437478[44] ?
6'd12 :
(_theResult____h437478[43] ?
6'd13 :
(_theResult____h437478[42] ?
6'd14 :
(_theResult____h437478[41] ?
6'd15 :
(_theResult____h437478[40] ?
6'd16 :
(_theResult____h437478[39] ?
6'd17 :
(_theResult____h437478[38] ?
6'd18 :
(_theResult____h437478[37] ?
6'd19 :
(_theResult____h437478[36] ?
6'd20 :
(_theResult____h437478[35] ?
6'd21 :
(_theResult____h437478[34] ?
6'd22 :
(_theResult____h437478[33] ?
6'd23 :
(_theResult____h437478[32] ?
6'd24 :
(_theResult____h437478[31] ?
6'd25 :
(_theResult____h437478[30] ?
6'd26 :
(_theResult____h437478[29] ?
6'd27 :
(_theResult____h437478[28] ?
6'd28 :
(_theResult____h437478[27] ?
6'd29 :
(_theResult____h437478[26] ?
6'd30 :
(_theResult____h437478[25] ?
6'd31 :
(_theResult____h437478[24] ?
6'd32 :
(_theResult____h437478[23] ?
6'd33 :
(_theResult____h437478[22] ?
6'd34 :
(_theResult____h437478[21] ?
6'd35 :
(_theResult____h437478[20] ?
6'd36 :
(_theResult____h437478[19] ?
6'd37 :
(_theResult____h437478[18] ?
6'd38 :
(_theResult____h437478[17] ?
6'd39 :
(_theResult____h437478[16] ?
6'd40 :
(_theResult____h437478[15] ?
6'd41 :
(_theResult____h437478[14] ?
6'd42 :
(_theResult____h437478[13] ?
6'd43 :
(_theResult____h437478[12] ?
6'd44 :
(_theResult____h437478[11] ?
6'd45 :
(_theResult____h437478[10] ?
6'd46 :
(_theResult____h437478[9] ?
6'd47 :
(_theResult____h437478[8] ?
6'd48 :
(_theResult____h437478[7] ?
6'd49 :
(_theResult____h437478[6] ?
6'd50 :
(_theResult____h437478[5] ?
6'd51 :
(_theResult____h437478[4] ?
6'd52 :
(_theResult____h437478[3] ?
6'd53 :
(_theResult____h437478[2] ?
6'd54 :
(_theResult____h437478[1] ?
6'd55 :
(_theResult____h437478[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 =
(_theResult____h541721[56] ?
6'd0 :
(_theResult____h541721[55] ?
6'd1 :
(_theResult____h541721[54] ?
6'd2 :
(_theResult____h541721[53] ?
6'd3 :
(_theResult____h541721[52] ?
6'd4 :
(_theResult____h541721[51] ?
6'd5 :
(_theResult____h541721[50] ?
6'd6 :
(_theResult____h541721[49] ?
6'd7 :
(_theResult____h541721[48] ?
6'd8 :
(_theResult____h541721[47] ?
6'd9 :
(_theResult____h541721[46] ?
6'd10 :
(_theResult____h541721[45] ?
6'd11 :
(_theResult____h541721[44] ?
6'd12 :
(_theResult____h541721[43] ?
6'd13 :
(_theResult____h541721[42] ?
6'd14 :
(_theResult____h541721[41] ?
6'd15 :
(_theResult____h541721[40] ?
6'd16 :
(_theResult____h541721[39] ?
6'd17 :
(_theResult____h541721[38] ?
6'd18 :
(_theResult____h541721[37] ?
6'd19 :
(_theResult____h541721[36] ?
6'd20 :
(_theResult____h541721[35] ?
6'd21 :
(_theResult____h541721[34] ?
6'd22 :
(_theResult____h541721[33] ?
6'd23 :
(_theResult____h541721[32] ?
6'd24 :
(_theResult____h541721[31] ?
6'd25 :
(_theResult____h541721[30] ?
6'd26 :
(_theResult____h541721[29] ?
6'd27 :
(_theResult____h541721[28] ?
6'd28 :
(_theResult____h541721[27] ?
6'd29 :
(_theResult____h541721[26] ?
6'd30 :
(_theResult____h541721[25] ?
6'd31 :
(_theResult____h541721[24] ?
6'd32 :
(_theResult____h541721[23] ?
6'd33 :
(_theResult____h541721[22] ?
6'd34 :
(_theResult____h541721[21] ?
6'd35 :
(_theResult____h541721[20] ?
6'd36 :
(_theResult____h541721[19] ?
6'd37 :
(_theResult____h541721[18] ?
6'd38 :
(_theResult____h541721[17] ?
6'd39 :
(_theResult____h541721[16] ?
6'd40 :
(_theResult____h541721[15] ?
6'd41 :
(_theResult____h541721[14] ?
6'd42 :
(_theResult____h541721[13] ?
6'd43 :
(_theResult____h541721[12] ?
6'd44 :
(_theResult____h541721[11] ?
6'd45 :
(_theResult____h541721[10] ?
6'd46 :
(_theResult____h541721[9] ?
6'd47 :
(_theResult____h541721[8] ?
6'd48 :
(_theResult____h541721[7] ?
6'd49 :
(_theResult____h541721[6] ?
6'd50 :
(_theResult____h541721[5] ?
6'd51 :
(_theResult____h541721[4] ?
6'd52 :
(_theResult____h541721[3] ?
6'd53 :
(_theResult____h541721[2] ?
6'd54 :
(_theResult____h541721[1] ?
6'd55 :
(_theResult____h541721[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 =
(_theResult____h502868[56] ?
6'd0 :
(_theResult____h502868[55] ?
6'd1 :
(_theResult____h502868[54] ?
6'd2 :
(_theResult____h502868[53] ?
6'd3 :
(_theResult____h502868[52] ?
6'd4 :
(_theResult____h502868[51] ?
6'd5 :
(_theResult____h502868[50] ?
6'd6 :
(_theResult____h502868[49] ?
6'd7 :
(_theResult____h502868[48] ?
6'd8 :
(_theResult____h502868[47] ?
6'd9 :
(_theResult____h502868[46] ?
6'd10 :
(_theResult____h502868[45] ?
6'd11 :
(_theResult____h502868[44] ?
6'd12 :
(_theResult____h502868[43] ?
6'd13 :
(_theResult____h502868[42] ?
6'd14 :
(_theResult____h502868[41] ?
6'd15 :
(_theResult____h502868[40] ?
6'd16 :
(_theResult____h502868[39] ?
6'd17 :
(_theResult____h502868[38] ?
6'd18 :
(_theResult____h502868[37] ?
6'd19 :
(_theResult____h502868[36] ?
6'd20 :
(_theResult____h502868[35] ?
6'd21 :
(_theResult____h502868[34] ?
6'd22 :
(_theResult____h502868[33] ?
6'd23 :
(_theResult____h502868[32] ?
6'd24 :
(_theResult____h502868[31] ?
6'd25 :
(_theResult____h502868[30] ?
6'd26 :
(_theResult____h502868[29] ?
6'd27 :
(_theResult____h502868[28] ?
6'd28 :
(_theResult____h502868[27] ?
6'd29 :
(_theResult____h502868[26] ?
6'd30 :
(_theResult____h502868[25] ?
6'd31 :
(_theResult____h502868[24] ?
6'd32 :
(_theResult____h502868[23] ?
6'd33 :
(_theResult____h502868[22] ?
6'd34 :
(_theResult____h502868[21] ?
6'd35 :
(_theResult____h502868[20] ?
6'd36 :
(_theResult____h502868[19] ?
6'd37 :
(_theResult____h502868[18] ?
6'd38 :
(_theResult____h502868[17] ?
6'd39 :
(_theResult____h502868[16] ?
6'd40 :
(_theResult____h502868[15] ?
6'd41 :
(_theResult____h502868[14] ?
6'd42 :
(_theResult____h502868[13] ?
6'd43 :
(_theResult____h502868[12] ?
6'd44 :
(_theResult____h502868[11] ?
6'd45 :
(_theResult____h502868[10] ?
6'd46 :
(_theResult____h502868[9] ?
6'd47 :
(_theResult____h502868[8] ?
6'd48 :
(_theResult____h502868[7] ?
6'd49 :
(_theResult____h502868[6] ?
6'd50 :
(_theResult____h502868[5] ?
6'd51 :
(_theResult____h502868[4] ?
6'd52 :
(_theResult____h502868[3] ?
6'd53 :
(_theResult____h502868[2] ?
6'd54 :
(_theResult____h502868[1] ?
6'd55 :
(_theResult____h502868[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 =
(_theResult____h581025[56] ?
6'd0 :
(_theResult____h581025[55] ?
6'd1 :
(_theResult____h581025[54] ?
6'd2 :
(_theResult____h581025[53] ?
6'd3 :
(_theResult____h581025[52] ?
6'd4 :
(_theResult____h581025[51] ?
6'd5 :
(_theResult____h581025[50] ?
6'd6 :
(_theResult____h581025[49] ?
6'd7 :
(_theResult____h581025[48] ?
6'd8 :
(_theResult____h581025[47] ?
6'd9 :
(_theResult____h581025[46] ?
6'd10 :
(_theResult____h581025[45] ?
6'd11 :
(_theResult____h581025[44] ?
6'd12 :
(_theResult____h581025[43] ?
6'd13 :
(_theResult____h581025[42] ?
6'd14 :
(_theResult____h581025[41] ?
6'd15 :
(_theResult____h581025[40] ?
6'd16 :
(_theResult____h581025[39] ?
6'd17 :
(_theResult____h581025[38] ?
6'd18 :
(_theResult____h581025[37] ?
6'd19 :
(_theResult____h581025[36] ?
6'd20 :
(_theResult____h581025[35] ?
6'd21 :
(_theResult____h581025[34] ?
6'd22 :
(_theResult____h581025[33] ?
6'd23 :
(_theResult____h581025[32] ?
6'd24 :
(_theResult____h581025[31] ?
6'd25 :
(_theResult____h581025[30] ?
6'd26 :
(_theResult____h581025[29] ?
6'd27 :
(_theResult____h581025[28] ?
6'd28 :
(_theResult____h581025[27] ?
6'd29 :
(_theResult____h581025[26] ?
6'd30 :
(_theResult____h581025[25] ?
6'd31 :
(_theResult____h581025[24] ?
6'd32 :
(_theResult____h581025[23] ?
6'd33 :
(_theResult____h581025[22] ?
6'd34 :
(_theResult____h581025[21] ?
6'd35 :
(_theResult____h581025[20] ?
6'd36 :
(_theResult____h581025[19] ?
6'd37 :
(_theResult____h581025[18] ?
6'd38 :
(_theResult____h581025[17] ?
6'd39 :
(_theResult____h581025[16] ?
6'd40 :
(_theResult____h581025[15] ?
6'd41 :
(_theResult____h581025[14] ?
6'd42 :
(_theResult____h581025[13] ?
6'd43 :
(_theResult____h581025[12] ?
6'd44 :
(_theResult____h581025[11] ?
6'd45 :
(_theResult____h581025[10] ?
6'd46 :
(_theResult____h581025[9] ?
6'd47 :
(_theResult____h581025[8] ?
6'd48 :
(_theResult____h581025[7] ?
6'd49 :
(_theResult____h581025[6] ?
6'd50 :
(_theResult____h581025[5] ?
6'd51 :
(_theResult____h581025[4] ?
6'd52 :
(_theResult____h581025[3] ?
6'd53 :
(_theResult____h581025[2] ?
6'd54 :
(_theResult____h581025[1] ?
6'd55 :
(_theResult____h581025[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 =
(_theResult____h363723[56] ?
6'd0 :
(_theResult____h363723[55] ?
6'd1 :
(_theResult____h363723[54] ?
6'd2 :
(_theResult____h363723[53] ?
6'd3 :
(_theResult____h363723[52] ?
6'd4 :
(_theResult____h363723[51] ?
6'd5 :
(_theResult____h363723[50] ?
6'd6 :
(_theResult____h363723[49] ?
6'd7 :
(_theResult____h363723[48] ?
6'd8 :
(_theResult____h363723[47] ?
6'd9 :
(_theResult____h363723[46] ?
6'd10 :
(_theResult____h363723[45] ?
6'd11 :
(_theResult____h363723[44] ?
6'd12 :
(_theResult____h363723[43] ?
6'd13 :
(_theResult____h363723[42] ?
6'd14 :
(_theResult____h363723[41] ?
6'd15 :
(_theResult____h363723[40] ?
6'd16 :
(_theResult____h363723[39] ?
6'd17 :
(_theResult____h363723[38] ?
6'd18 :
(_theResult____h363723[37] ?
6'd19 :
(_theResult____h363723[36] ?
6'd20 :
(_theResult____h363723[35] ?
6'd21 :
(_theResult____h363723[34] ?
6'd22 :
(_theResult____h363723[33] ?
6'd23 :
(_theResult____h363723[32] ?
6'd24 :
(_theResult____h363723[31] ?
6'd25 :
(_theResult____h363723[30] ?
6'd26 :
(_theResult____h363723[29] ?
6'd27 :
(_theResult____h363723[28] ?
6'd28 :
(_theResult____h363723[27] ?
6'd29 :
(_theResult____h363723[26] ?
6'd30 :
(_theResult____h363723[25] ?
6'd31 :
(_theResult____h363723[24] ?
6'd32 :
(_theResult____h363723[23] ?
6'd33 :
(_theResult____h363723[22] ?
6'd34 :
(_theResult____h363723[21] ?
6'd35 :
(_theResult____h363723[20] ?
6'd36 :
(_theResult____h363723[19] ?
6'd37 :
(_theResult____h363723[18] ?
6'd38 :
(_theResult____h363723[17] ?
6'd39 :
(_theResult____h363723[16] ?
6'd40 :
(_theResult____h363723[15] ?
6'd41 :
(_theResult____h363723[14] ?
6'd42 :
(_theResult____h363723[13] ?
6'd43 :
(_theResult____h363723[12] ?
6'd44 :
(_theResult____h363723[11] ?
6'd45 :
(_theResult____h363723[10] ?
6'd46 :
(_theResult____h363723[9] ?
6'd47 :
(_theResult____h363723[8] ?
6'd48 :
(_theResult____h363723[7] ?
6'd49 :
(_theResult____h363723[6] ?
6'd50 :
(_theResult____h363723[5] ?
6'd51 :
(_theResult____h363723[4] ?
6'd52 :
(_theResult____h363723[3] ?
6'd53 :
(_theResult____h363723[2] ?
6'd54 :
(_theResult____h363723[1] ?
6'd55 :
(_theResult____h363723[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 =
(_theResult____h409420[56] ?
6'd0 :
(_theResult____h409420[55] ?
6'd1 :
(_theResult____h409420[54] ?
6'd2 :
(_theResult____h409420[53] ?
6'd3 :
(_theResult____h409420[52] ?
6'd4 :
(_theResult____h409420[51] ?
6'd5 :
(_theResult____h409420[50] ?
6'd6 :
(_theResult____h409420[49] ?
6'd7 :
(_theResult____h409420[48] ?
6'd8 :
(_theResult____h409420[47] ?
6'd9 :
(_theResult____h409420[46] ?
6'd10 :
(_theResult____h409420[45] ?
6'd11 :
(_theResult____h409420[44] ?
6'd12 :
(_theResult____h409420[43] ?
6'd13 :
(_theResult____h409420[42] ?
6'd14 :
(_theResult____h409420[41] ?
6'd15 :
(_theResult____h409420[40] ?
6'd16 :
(_theResult____h409420[39] ?
6'd17 :
(_theResult____h409420[38] ?
6'd18 :
(_theResult____h409420[37] ?
6'd19 :
(_theResult____h409420[36] ?
6'd20 :
(_theResult____h409420[35] ?
6'd21 :
(_theResult____h409420[34] ?
6'd22 :
(_theResult____h409420[33] ?
6'd23 :
(_theResult____h409420[32] ?
6'd24 :
(_theResult____h409420[31] ?
6'd25 :
(_theResult____h409420[30] ?
6'd26 :
(_theResult____h409420[29] ?
6'd27 :
(_theResult____h409420[28] ?
6'd28 :
(_theResult____h409420[27] ?
6'd29 :
(_theResult____h409420[26] ?
6'd30 :
(_theResult____h409420[25] ?
6'd31 :
(_theResult____h409420[24] ?
6'd32 :
(_theResult____h409420[23] ?
6'd33 :
(_theResult____h409420[22] ?
6'd34 :
(_theResult____h409420[21] ?
6'd35 :
(_theResult____h409420[20] ?
6'd36 :
(_theResult____h409420[19] ?
6'd37 :
(_theResult____h409420[18] ?
6'd38 :
(_theResult____h409420[17] ?
6'd39 :
(_theResult____h409420[16] ?
6'd40 :
(_theResult____h409420[15] ?
6'd41 :
(_theResult____h409420[14] ?
6'd42 :
(_theResult____h409420[13] ?
6'd43 :
(_theResult____h409420[12] ?
6'd44 :
(_theResult____h409420[11] ?
6'd45 :
(_theResult____h409420[10] ?
6'd46 :
(_theResult____h409420[9] ?
6'd47 :
(_theResult____h409420[8] ?
6'd48 :
(_theResult____h409420[7] ?
6'd49 :
(_theResult____h409420[6] ?
6'd50 :
(_theResult____h409420[5] ?
6'd51 :
(_theResult____h409420[4] ?
6'd52 :
(_theResult____h409420[3] ?
6'd53 :
(_theResult____h409420[2] ?
6'd54 :
(_theResult____h409420[1] ?
6'd55 :
(_theResult____h409420[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 =
(_theResult____h455115[56] ?
6'd0 :
(_theResult____h455115[55] ?
6'd1 :
(_theResult____h455115[54] ?
6'd2 :
(_theResult____h455115[53] ?
6'd3 :
(_theResult____h455115[52] ?
6'd4 :
(_theResult____h455115[51] ?
6'd5 :
(_theResult____h455115[50] ?
6'd6 :
(_theResult____h455115[49] ?
6'd7 :
(_theResult____h455115[48] ?
6'd8 :
(_theResult____h455115[47] ?
6'd9 :
(_theResult____h455115[46] ?
6'd10 :
(_theResult____h455115[45] ?
6'd11 :
(_theResult____h455115[44] ?
6'd12 :
(_theResult____h455115[43] ?
6'd13 :
(_theResult____h455115[42] ?
6'd14 :
(_theResult____h455115[41] ?
6'd15 :
(_theResult____h455115[40] ?
6'd16 :
(_theResult____h455115[39] ?
6'd17 :
(_theResult____h455115[38] ?
6'd18 :
(_theResult____h455115[37] ?
6'd19 :
(_theResult____h455115[36] ?
6'd20 :
(_theResult____h455115[35] ?
6'd21 :
(_theResult____h455115[34] ?
6'd22 :
(_theResult____h455115[33] ?
6'd23 :
(_theResult____h455115[32] ?
6'd24 :
(_theResult____h455115[31] ?
6'd25 :
(_theResult____h455115[30] ?
6'd26 :
(_theResult____h455115[29] ?
6'd27 :
(_theResult____h455115[28] ?
6'd28 :
(_theResult____h455115[27] ?
6'd29 :
(_theResult____h455115[26] ?
6'd30 :
(_theResult____h455115[25] ?
6'd31 :
(_theResult____h455115[24] ?
6'd32 :
(_theResult____h455115[23] ?
6'd33 :
(_theResult____h455115[22] ?
6'd34 :
(_theResult____h455115[21] ?
6'd35 :
(_theResult____h455115[20] ?
6'd36 :
(_theResult____h455115[19] ?
6'd37 :
(_theResult____h455115[18] ?
6'd38 :
(_theResult____h455115[17] ?
6'd39 :
(_theResult____h455115[16] ?
6'd40 :
(_theResult____h455115[15] ?
6'd41 :
(_theResult____h455115[14] ?
6'd42 :
(_theResult____h455115[13] ?
6'd43 :
(_theResult____h455115[12] ?
6'd44 :
(_theResult____h455115[11] ?
6'd45 :
(_theResult____h455115[10] ?
6'd46 :
(_theResult____h455115[9] ?
6'd47 :
(_theResult____h455115[8] ?
6'd48 :
(_theResult____h455115[7] ?
6'd49 :
(_theResult____h455115[6] ?
6'd50 :
(_theResult____h455115[5] ?
6'd51 :
(_theResult____h455115[4] ?
6'd52 :
(_theResult____h455115[3] ?
6'd53 :
(_theResult____h455115[2] ?
6'd54 :
(_theResult____h455115[1] ?
6'd55 :
(_theResult____h455115[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 =
(_theResult___fst_exp__h549957 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 =
(_theResult___fst_exp__h549957 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 =
(_theResult___fst_exp__h511104 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 =
(_theResult___fst_exp__h589261 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 =
(_theResult___fst_exp__h589261 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 =
(guard__h346094 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h354195 :
_theResult___exp__h354711 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 =
(guard__h346094 == 2'b0) ?
_theResult___fst_exp__h354195 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h354711 :
_theResult___fst_exp__h354195) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 =
(guard__h346094 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h354189[56:34] :
_theResult___sfd__h354712 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 =
(guard__h346094 == 2'b0) ?
sfdin__h354189[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h354712 :
sfdin__h354189[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 =
(guard__h391793 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h399892 :
_theResult___exp__h400408 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 =
(guard__h391793 == 2'b0) ?
_theResult___fst_exp__h399892 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h400408 :
_theResult___fst_exp__h399892) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 =
(guard__h391793 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h399886[56:34] :
_theResult___sfd__h400409 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 =
(guard__h391793 == 2'b0) ?
sfdin__h399886[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h400409 :
sfdin__h399886[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 =
(guard__h437488 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h445587 :
_theResult___exp__h446103 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 =
(guard__h437488 == 2'b0) ?
_theResult___fst_exp__h445587 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h446103 :
_theResult___fst_exp__h445587) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 =
(guard__h437488 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h445581[56:34] :
_theResult___sfd__h446104 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 =
(guard__h437488 == 2'b0) ?
sfdin__h445581[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h446104 :
sfdin__h445581[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 =
(guard__h541731 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h549957 :
_theResult___exp__h550686 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 =
(guard__h541731 == 2'b0) ?
_theResult___fst_exp__h549957 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h550686 :
_theResult___fst_exp__h549957) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 =
(guard__h541731 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
sfdin__h549951[56:5] :
_theResult___sfd__h550687 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 =
(guard__h541731 == 2'b0) ?
sfdin__h549951[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h550687 :
sfdin__h549951[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 =
(guard__h502878 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h511104 :
_theResult___exp__h511833 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 =
(guard__h502878 == 2'b0) ?
_theResult___fst_exp__h511104 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h511833 :
_theResult___fst_exp__h511104) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 =
(guard__h502878 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
sfdin__h511098[56:5] :
_theResult___sfd__h511834 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 =
(guard__h502878 == 2'b0) ?
sfdin__h511098[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h511834 :
sfdin__h511098[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 =
(guard__h581035 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h589261 :
_theResult___exp__h589990 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 =
(guard__h581035 == 2'b0) ?
_theResult___fst_exp__h589261 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h589990 :
_theResult___fst_exp__h589261) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 =
(guard__h581035 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
sfdin__h589255[56:5] :
_theResult___sfd__h589991 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 =
(guard__h581035 == 2'b0) ?
sfdin__h589255[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h589991 :
sfdin__h589255[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 =
(guard__h363733 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h371961 :
_theResult___exp__h372477 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 =
(guard__h363733 == 2'b0) ?
_theResult___fst_exp__h371961 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h372477 :
_theResult___fst_exp__h371961) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 =
(guard__h363733 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h371955[56:34] :
_theResult___sfd__h372478 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 =
(guard__h363733 == 2'b0) ?
sfdin__h371955[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h372478 :
sfdin__h371955[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 =
(guard__h409430 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h417658 :
_theResult___exp__h418174 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 =
(guard__h409430 == 2'b0) ?
_theResult___fst_exp__h417658 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h418174 :
_theResult___fst_exp__h417658) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 =
(guard__h409430 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h417652[56:34] :
_theResult___sfd__h418175 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 =
(guard__h409430 == 2'b0) ?
sfdin__h417652[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h418175 :
sfdin__h417652[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 =
(guard__h455125 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h463353 :
_theResult___exp__h463869 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 =
(guard__h455125 == 2'b0) ?
_theResult___fst_exp__h463353 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h463869 :
_theResult___fst_exp__h463353) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 =
(guard__h455125 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h463347[56:34] :
_theResult___sfd__h463870 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 =
(guard__h455125 == 2'b0) ?
sfdin__h463347[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h463870 :
sfdin__h463347[56:34]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 =
(guard__h532419 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h540380 :
_theResult___exp__h541035 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 =
(guard__h532419 == 2'b0) ?
_theResult___fst_exp__h540380 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h541035 :
_theResult___fst_exp__h540380) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 =
(guard__h550800 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h558790 :
_theResult___exp__h559470 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 =
(guard__h550800 == 2'b0) ?
_theResult___fst_exp__h558790 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h559470 :
_theResult___fst_exp__h558790) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 =
(guard__h532419 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h540331[56:5] :
_theResult___sfd__h541036 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 =
(guard__h532419 == 2'b0) ?
_theResult___snd__h540331[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h541036 :
_theResult___snd__h540331[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 =
(guard__h550800 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h558736[56:5] :
_theResult___sfd__h559471 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 =
(guard__h550800 == 2'b0) ?
_theResult___snd__h558736[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h559471 :
_theResult___snd__h558736[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 =
(guard__h493566 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h501527 :
_theResult___exp__h502182 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 =
(guard__h493566 == 2'b0) ?
_theResult___fst_exp__h501527 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h502182 :
_theResult___fst_exp__h501527) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 =
(guard__h511947 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h519937 :
_theResult___exp__h520617 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 =
(guard__h511947 == 2'b0) ?
_theResult___fst_exp__h519937 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h520617 :
_theResult___fst_exp__h519937) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 =
(guard__h493566 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h501478[56:5] :
_theResult___sfd__h502183 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 =
(guard__h493566 == 2'b0) ?
_theResult___snd__h501478[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h502183 :
_theResult___snd__h501478[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 =
(guard__h511947 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h519883[56:5] :
_theResult___sfd__h520618 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 =
(guard__h511947 == 2'b0) ?
_theResult___snd__h519883[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h520618 :
_theResult___snd__h519883[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 =
(guard__h571723 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h579684 :
_theResult___exp__h580339 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 =
(guard__h571723 == 2'b0) ?
_theResult___fst_exp__h579684 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h580339 :
_theResult___fst_exp__h579684) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 =
(guard__h590104 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h598094 :
_theResult___exp__h598774 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 =
(guard__h590104 == 2'b0) ?
_theResult___fst_exp__h598094 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h598774 :
_theResult___fst_exp__h598094) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 =
(guard__h571723 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h579635[56:5] :
_theResult___sfd__h580340 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 =
(guard__h571723 == 2'b0) ?
_theResult___snd__h579635[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h580340 :
_theResult___snd__h579635[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 =
(guard__h590104 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h598040[56:5] :
_theResult___sfd__h598775 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 =
(guard__h590104 == 2'b0) ?
_theResult___snd__h598040[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h598775 :
_theResult___snd__h598040[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 =
(guard__h354803 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h362851 :
_theResult___exp__h363293 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 =
(guard__h354803 == 2'b0) ?
_theResult___fst_exp__h362851 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h363293 :
_theResult___fst_exp__h362851) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 =
(guard__h372569 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h380646 :
_theResult___exp__h381113 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 =
(guard__h372569 == 2'b0) ?
_theResult___fst_exp__h380646 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h381113 :
_theResult___fst_exp__h380646) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 =
(guard__h354803 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h362802[56:34] :
_theResult___sfd__h363294 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 =
(guard__h354803 == 2'b0) ?
_theResult___snd__h362802[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h363294 :
_theResult___snd__h362802[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 =
(guard__h372569 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h380592[56:34] :
_theResult___sfd__h381114 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 =
(guard__h372569 == 2'b0) ?
_theResult___snd__h380592[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h381114 :
_theResult___snd__h380592[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 =
(guard__h400500 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h408548 :
_theResult___exp__h408990 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 =
(guard__h400500 == 2'b0) ?
_theResult___fst_exp__h408548 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h408990 :
_theResult___fst_exp__h408548) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 =
(guard__h418266 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h426343 :
_theResult___exp__h426810 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 =
(guard__h418266 == 2'b0) ?
_theResult___fst_exp__h426343 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h426810 :
_theResult___fst_exp__h426343) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 =
(guard__h400500 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h408499[56:34] :
_theResult___sfd__h408991 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 =
(guard__h400500 == 2'b0) ?
_theResult___snd__h408499[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h408991 :
_theResult___snd__h408499[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 =
(guard__h418266 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h426289[56:34] :
_theResult___sfd__h426811 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 =
(guard__h418266 == 2'b0) ?
_theResult___snd__h426289[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h426811 :
_theResult___snd__h426289[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 =
(guard__h446195 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h454243 :
_theResult___exp__h454685 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 =
(guard__h446195 == 2'b0) ?
_theResult___fst_exp__h454243 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h454685 :
_theResult___fst_exp__h454243) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 =
(guard__h463961 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h472038 :
_theResult___exp__h472505 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 =
(guard__h463961 == 2'b0) ?
_theResult___fst_exp__h472038 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h472505 :
_theResult___fst_exp__h472038) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 =
(guard__h446195 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h454194[56:34] :
_theResult___sfd__h454686 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 =
(guard__h446195 == 2'b0) ?
_theResult___snd__h454194[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h454686 :
_theResult___snd__h454194[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 =
(guard__h463961 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h471984[56:34] :
_theResult___sfd__h472506 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 =
(guard__h463961 == 2'b0) ?
_theResult___snd__h471984[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h472506 :
_theResult___snd__h471984[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470 =
(_theResult___fst_exp__h558790 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676 =
(_theResult___fst_exp__h540380 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703 =
(_theResult___fst_exp__h558790 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985 =
(_theResult___fst_exp__h519937 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700 =
(_theResult___fst_exp__h598094 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907 =
(_theResult___fst_exp__h579684 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934 =
(_theResult___fst_exp__h598094 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ;
assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824 =
(_theResult____h651116 == 16'd0 &&
(csrf_prv_reg == 2'd0 ||
csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ?
enabled_ints__h651687 :
_theResult____h651116 ;
assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052 =
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ||
checkForException___d13008[4] ||
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045 ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13756 =
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ||
checkForException___d13008[4] ||
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 ;
assign IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13793 =
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ||
checkForException___d13698[4] ||
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 =
((f2_exp__h521133 == 8'd0) ?
(f2_sfd__h521134[22] ?
6'd2 :
(f2_sfd__h521134[21] ?
6'd3 :
(f2_sfd__h521134[20] ?
6'd4 :
(f2_sfd__h521134[19] ?
6'd5 :
(f2_sfd__h521134[18] ?
6'd6 :
(f2_sfd__h521134[17] ?
6'd7 :
(f2_sfd__h521134[16] ?
6'd8 :
(f2_sfd__h521134[15] ?
6'd9 :
(f2_sfd__h521134[14] ?
6'd10 :
(f2_sfd__h521134[13] ?
6'd11 :
(f2_sfd__h521134[12] ?
6'd12 :
(f2_sfd__h521134[11] ?
6'd13 :
(f2_sfd__h521134[10] ?
6'd14 :
(f2_sfd__h521134[9] ?
6'd15 :
(f2_sfd__h521134[8] ?
6'd16 :
(f2_sfd__h521134[7] ?
6'd17 :
(f2_sfd__h521134[6] ?
6'd18 :
(f2_sfd__h521134[5] ?
6'd19 :
(f2_sfd__h521134[4] ?
6'd20 :
(f2_sfd__h521134[3] ?
6'd21 :
(f2_sfd__h521134[2] ?
6'd22 :
(f2_sfd__h521134[1] ?
6'd23 :
(f2_sfd__h521134[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474 =
(f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0 ||
(f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) &&
f2_sfd__h521134 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((f2_exp__h521133 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 =
(f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0) ?
_theResult___snd_fst_sfd__h521449 :
_theResult___fst_sfd__h559589 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 =
{ (f2_exp__h521133 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h559585,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10651 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 =
(f2_exp__h521133 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10676) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678) :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 =
(f2_exp__h521133 == 8'd255 && f2_sfd__h521134 != 23'd0 ||
(f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) &&
f2_sfd__h521134 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10706 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 =
(f1_exp__h482139 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803 =
(f2_exp__h521133 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847 =
(f3_exp__h560437 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 =
(f1_exp__h482139 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872 =
(f2_exp__h521133 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883 =
(f3_exp__h560437 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 =
(f1_exp__h482139 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916 =
(f2_exp__h521133 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931 =
(f3_exp__h560437 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 =
(f1_exp__h482139 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960 =
(f2_exp__h521133 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973 =
(f3_exp__h560437 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 =
(f1_exp__h482139 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002 =
(f2_exp__h521133 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015 =
(f3_exp__h560437 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 =
((f1_exp__h482139 == 8'd0) ?
(f1_sfd__h482140[22] ?
6'd2 :
(f1_sfd__h482140[21] ?
6'd3 :
(f1_sfd__h482140[20] ?
6'd4 :
(f1_sfd__h482140[19] ?
6'd5 :
(f1_sfd__h482140[18] ?
6'd6 :
(f1_sfd__h482140[17] ?
6'd7 :
(f1_sfd__h482140[16] ?
6'd8 :
(f1_sfd__h482140[15] ?
6'd9 :
(f1_sfd__h482140[14] ?
6'd10 :
(f1_sfd__h482140[13] ?
6'd11 :
(f1_sfd__h482140[12] ?
6'd12 :
(f1_sfd__h482140[11] ?
6'd13 :
(f1_sfd__h482140[10] ?
6'd14 :
(f1_sfd__h482140[9] ?
6'd15 :
(f1_sfd__h482140[8] ?
6'd16 :
(f1_sfd__h482140[7] ?
6'd17 :
(f1_sfd__h482140[6] ?
6'd18 :
(f1_sfd__h482140[5] ?
6'd19 :
(f1_sfd__h482140[4] ?
6'd20 :
(f1_sfd__h482140[3] ?
6'd21 :
(f1_sfd__h482140[2] ?
6'd22 :
(f1_sfd__h482140[1] ?
6'd23 :
(f1_sfd__h482140[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989 =
(f1_exp__h482139 == 8'd255 && f1_sfd__h482140 != 23'd0 ||
(f1_exp__h482139 == 8'd255 || f1_exp__h482139 == 8'd0) &&
f1_sfd__h482140 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((f1_exp__h482139 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 =
(f1_exp__h482139 == 8'd255 && f1_sfd__h482140 != 23'd0) ?
_theResult___snd_fst_sfd__h482455 :
_theResult___fst_sfd__h520736 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 =
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8989,
(f1_exp__h482139 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h520732,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9172 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 =
((f3_exp__h560437 == 8'd0) ?
(f3_sfd__h560438[22] ?
6'd2 :
(f3_sfd__h560438[21] ?
6'd3 :
(f3_sfd__h560438[20] ?
6'd4 :
(f3_sfd__h560438[19] ?
6'd5 :
(f3_sfd__h560438[18] ?
6'd6 :
(f3_sfd__h560438[17] ?
6'd7 :
(f3_sfd__h560438[16] ?
6'd8 :
(f3_sfd__h560438[15] ?
6'd9 :
(f3_sfd__h560438[14] ?
6'd10 :
(f3_sfd__h560438[13] ?
6'd11 :
(f3_sfd__h560438[12] ?
6'd12 :
(f3_sfd__h560438[11] ?
6'd13 :
(f3_sfd__h560438[10] ?
6'd14 :
(f3_sfd__h560438[9] ?
6'd15 :
(f3_sfd__h560438[8] ?
6'd16 :
(f3_sfd__h560438[7] ?
6'd17 :
(f3_sfd__h560438[6] ?
6'd18 :
(f3_sfd__h560438[5] ?
6'd19 :
(f3_sfd__h560438[4] ?
6'd20 :
(f3_sfd__h560438[3] ?
6'd21 :
(f3_sfd__h560438[2] ?
6'd22 :
(f3_sfd__h560438[1] ?
6'd23 :
(f3_sfd__h560438[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704 =
(f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0 ||
(f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) &&
f3_sfd__h560438 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((f3_exp__h560437 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 =
(f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0) ?
_theResult___snd_fst_sfd__h560753 :
_theResult___fst_sfd__h598893 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 =
{ (f3_exp__h560437 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h598889,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9881 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 =
(f3_exp__h560437 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9907) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909) :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938 =
(f3_exp__h560437 == 8'd255 && f3_sfd__h560438 != 23'd0 ||
(f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) &&
f3_sfd__h560438 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9937 ;
assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851 =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1840 ?
4'd11 :
(IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1844 ?
4'd12 :
(IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1848 ?
4'd13 :
4'd15)) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853 =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1832 ?
4'd8 :
(IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1836 ?
4'd9 :
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1851) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855 =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1824 ?
4'd6 :
(IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1828 ?
4'd7 :
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1853) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1857 =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1816 ?
4'd4 :
(IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1820 ?
4'd5 :
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1855) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1859 =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1808 ?
4'd2 :
(IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1812 ?
4'd3 :
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1857) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1861 =
IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1800 ?
4'd0 :
(IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1804 ?
4'd1 :
IF_IF_coreFix_memExe_dTlb_procResp__714_BIT_18_ETC___d1859) ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13198 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd12 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd12) ?
4'd13 :
4'd15 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13199 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd11 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd11) ?
4'd12 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13198 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13200 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd10 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd10) ?
4'd11 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13199 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13201 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd9 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd9) ?
4'd9 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13200 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13202 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd8 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd8) ?
4'd8 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13201 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13203 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd7 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd7) ?
4'd7 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13202 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13204 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd6 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd6) ?
4'd6 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13203 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13205 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd5 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd5) ?
4'd5 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13204 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13206 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd4 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd4) ?
4'd4 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13205 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13207 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd3 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd3) ?
4'd3 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13206 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13208 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd2 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd2) ?
4'd2 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13207 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13209 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd1 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd1) ?
4'd1 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13208 ;
assign IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 ==
4'd0 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 ==
4'd0) ?
4'd0 :
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13209 ;
assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 =
{ (mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[75:72] :
mmio_cRqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 =
{ (mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[75:72] :
mmio_dataReqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 =
{ (EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ?
2'd1 :
((EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd2 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd2) ?
2'd2 :
2'd3),
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[35:32] :
mmio_pRqQ_enqReq_rl[35:32] } ;
assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 =
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[66] :
!mmio_pRsQ_enqReq_rl[66]) ?
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[65] :
mmio_pRsQ_enqReq_rl[65],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:33] :
mmio_pRsQ_enqReq_rl[64:33],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[32] :
mmio_pRsQ_enqReq_rl[32],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[31:0] :
mmio_pRsQ_enqReq_rl[31:0] } :
{ 1'h0,
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:0] :
mmio_pRsQ_enqReq_rl[64:0] } ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10129 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ||
_theResult___fst_exp__h540380 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8644 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ||
_theResult___fst_exp__h501527 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9359 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ||
_theResult___fst_exp__h579684 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ;
assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 =
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ?
4'd0 :
(IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ?
4'd1 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2]) ?
4'd2 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3]) ?
4'd3 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4]) ?
4'd4 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6]) ?
4'd5 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7]) ?
4'd6 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8]) ?
4'd7 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10]) ?
4'd8 :
((IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13]) ?
4'd9 :
4'd10))))))))) ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12237 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12238 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12237 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12239 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12238 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12262 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12263 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12262 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12264 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12263 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12448 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12460 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12460 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11377 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11378 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11377 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11379 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11378 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11402 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11403 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11402 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11404 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11403 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11774 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11774 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11786 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11786 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8241 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8242 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8241 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8243 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8242 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8265 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8266 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8265 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8267 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8266 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8289 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8290 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8289 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8291 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8290 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8336 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8347 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8347 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8358 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8358 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1603 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1604 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1603 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1605 =
NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1604 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1627 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1628 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1627 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629 =
NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1628 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1648 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1648 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1659 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1659 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2510 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 } :
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2 } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 =
(!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb$procResp[12]) ?
CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 :
CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13908 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466) &&
fetchStage$pipelines_1_canDeq) ?
fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13905 :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2755_275_ETC___d13916 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466) &&
fetchStage$pipelines_1_canDeq) ?
IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13915 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13913 ;
assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13831 =
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) ?
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13814 :
((fetchStage$pipelines_1_first[194:192] == 3'd2) ?
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3403_AND__ETC___d13823 ||
NOT_regRenamingTable_rename_1_canRename__3530__ETC___d13801) :
_0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829) ;
assign IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13915 =
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13739 ?
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13913 ;
assign IF_NOT_renameStage_rg_m_halt_req_2784_BIT_4_27_ETC___d13283 =
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 ?
IF_IF_fetchStage_pipelines_0_first__2757_BIT_6_ETC___d13210 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd0 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd0) ?
4'd0 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd1 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd1) ?
4'd1 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd3 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd2) ?
4'd3 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd4 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd3) ?
4'd4 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd5 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd4) ?
4'd5 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd7 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd5) ?
4'd7 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd8 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd6) ?
4'd8 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd9 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd7) ?
4'd9 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd11 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd8) ?
4'd11 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd14 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3__ETC___d13243 ==
4'd9) ?
4'd14 :
4'd15)))))))))) ;
assign IF_NOT_rob_deqPort_0_deq_data__4328_BITS_329_T_ETC___d15281 =
{ (rob$deqPort_0_deq_data[329:325] != 5'd13 &&
rob$deqPort_0_deq_data[97:96] == 2'd0) ?
{ 2'd0, rob$deqPort_0_deq_data[95:32] } :
((rob$deqPort_0_deq_data[329:325] != 5'd13 &&
rob$deqPort_0_deq_data[97:96] == 2'd1) ?
{ 2'd1, rob$deqPort_0_deq_data[95:32] } :
{ 2'd2,
(rob$deqPort_0_deq_data[329:325] == 5'd13) ?
data_warl_xformed__h721446 :
rob$deqPort_0_deq_data[95:32] }),
5'h0A,
rob$deqPort_0_deq_data[26],
64'hAAAAAAAAAAAAAAAA,
x_prv__h722029,
64'hAAAAAAAAAAAAAAAA,
x__h725432,
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[329:325] == 5'd0 ||
rob$deqPort_1_deq_data[329:325] == 5'd21 ||
rob$deqPort_1_deq_data[329:325] == 5'd17 ||
rob$deqPort_1_deq_data[329:325] == 5'd18 ||
rob$deqPort_1_deq_data[329:325] == 5'd13 ||
rob$deqPort_1_deq_data[329:325] == 5'd16 ||
rob$deqPort_1_deq_data[329:325] == 5'd15 ||
rob$deqPort_1_deq_data[329:325] == 5'd19 ||
rob$deqPort_1_deq_data[329:325] == 5'd20) ?
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ||
rob$deqPort_1_deq_data[26] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10472 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10424 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10470) :
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10705 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10691 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10703) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10900 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[2] :
_theResult___fst_exp__h520720 == 11'd2047 &&
_theResult___fst_sfd__h520721 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10914 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[2] :
_theResult___fst_exp__h559573 == 11'd2047 &&
_theResult___fst_sfd__h559574 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10929 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[2] :
_theResult___fst_exp__h598877 == 11'd2047 &&
_theResult___fst_sfd__h598878 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10946 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[1] :
_theResult___fst_exp__h519937 == 11'd0 &&
guard__h511947 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10958 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[1] :
_theResult___fst_exp__h558790 == 11'd0 &&
guard__h550800 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10971 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[1] :
_theResult___fst_exp__h598094 == 11'd0 &&
guard__h590104 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10988 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758[0] :
_theResult___fst_exp__h519937 != 11'd2047 &&
guard__h511947 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11000 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799[0] :
_theResult___fst_exp__h558790 != 11'd2047 &&
guard__h550800 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11013 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843[0] :
_theResult___fst_exp__h598094 != 11'd2047 &&
guard__h590104 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8987 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8939 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8985) :
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9702 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9654 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9700) :
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9936 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9922 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9934) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
((_theResult___fst_exp__h371961 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084) :
((_theResult___fst_exp__h380646 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
((_theResult___fst_exp__h371961 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127) :
((_theResult___fst_exp__h380646 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[2] :
_theResult___fst_exp__h381194 == 8'd255 &&
_theResult___fst_sfd__h381195 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[1] :
_theResult___fst_exp__h380646 == 8'd0 &&
guard__h372569 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[0] :
_theResult___fst_exp__h380646 != 8'd255 &&
guard__h372569 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
((_theResult___fst_exp__h417658 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476) :
((_theResult___fst_exp__h426343 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
((_theResult___fst_exp__h417658 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519) :
((_theResult___fst_exp__h426343 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[2] :
_theResult___fst_exp__h426891 == 8'd255 &&
_theResult___fst_sfd__h426892 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[1] :
_theResult___fst_exp__h426343 == 8'd0 &&
guard__h418266 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[0] :
_theResult___fst_exp__h426343 != 8'd255 &&
guard__h418266 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
((_theResult___fst_exp__h463353 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868) :
((_theResult___fst_exp__h472038 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
((_theResult___fst_exp__h463353 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911) :
((_theResult___fst_exp__h472038 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[2] :
_theResult___fst_exp__h472586 == 8'd255 &&
_theResult___fst_sfd__h472587 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[1] :
_theResult___fst_exp__h472038 == 8'd0 &&
guard__h463961 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[0] :
_theResult___fst_exp__h472038 != 8'd255 &&
guard__h463961 != 2'b0 ;
assign IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159 =
checkForException___d13008[4] ?
CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 :
4'd2 ;
assign IF_commitStage_commitTrap_4336_BIT_36_4579_THE_ETC___d14916 =
{ trap_val__h708464,
CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257,
commitStage_f_rob_data$D_OUT[95:32],
5'h0A,
commitStage_f_rob_data$D_OUT[26],
64'hAAAAAAAAAAAAAAAA,
x_prv__h711506,
pc__h711407,
x__h713649,
x__h713841,
commitStage_commitTrap[164:101] } ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12247 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11353 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11387 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8217 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8274 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6493) :
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6530) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6493 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6461 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6491 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6530 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6511 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6528 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6594 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6576 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6605 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6601 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6621 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6619 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6634 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6628 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6632 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6641 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6645 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5101 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5069 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5099 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5138 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5119 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5136 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5202 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5213 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5209 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5229 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5227 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5242 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5236 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5240 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5253 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7885 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7853 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7883 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7922 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7903 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7920 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7986 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7968 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7997 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7993 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8013 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8011 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8026 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8020 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8024 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8037 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5101) :
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5138) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7885) :
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7922) ;
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070 =
(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] ==
2'd0) ?
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ;
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 =
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8070[31:0] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10474,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10678 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8430 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ?
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 :
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 ||
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9173 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9704,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9909 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[75],
coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9938,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9882 } ;
assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12698 =
coreFix_globalSpecUpdate_correctSpecTag_1$whas ?
result__h646693 :
w__h646688 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2084 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2104 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082 :
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2103 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2107 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2106 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198 =
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd7) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd6) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd5) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd4) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2198,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd3) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd2) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2203,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd1) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd0) ?
n___1__h198528 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
{ 3'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2523 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2522 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2539 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
3'd5 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
3'd2 :
3'd3) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2550 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
58'h155555555555554 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
1'd0 } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 }) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
x__h197125 :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ?
64'd0 :
64'd1) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3058 =
_theResult_____2__h296520 == v__h295940 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3160 =
_theResult_____2__h304516 == v__h299285 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 =
EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3247 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 &&
(EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ?
{ 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } :
{ EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518],
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516],
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]),
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3],
x__h302150 } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3004 =
!MUX_flush_reservation$write_1__SEL_2 &&
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3012 =
MUX_flush_reservation$write_1__SEL_2 ?
58'h2AAAAAAAAAAAAAA :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2047 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ?
!coreFix_memExe_respLrScAmoQ_full :
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2049 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
!coreFix_memExe_respLrScAmoQ_full :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2047 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0) ?
!coreFix_memExe_memRespLdQ_full :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2049 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058 =
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2106 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027)) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2058 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2104 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2108 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2086 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2107 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144 =
{ (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2522 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027)) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2144,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 } :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2521 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2570 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027)) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2567 } :
65'h10000000000000001 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2704 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700) ?
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry :
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2713 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
2'd0 :
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998 =
{ (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd7) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd6) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd5) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1998,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd4) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd3) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2008 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2003,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd2) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd1) ?
n__h194453 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2793 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2836 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324 =
EN_dCacheToParent_rqToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3332 =
_theResult_____2__h310510 == v__h309799 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420 =
EN_dCacheToParent_rsToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3428 =
_theResult_____2__h318364 == v__h313675 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 =
(coreFix_memExe_dTlb$procResp[177:175] == 3'd3) ?
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1744 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
coreFix_memExe_dTlb$procResp[177:175] != 3'd3 &&
!coreFix_memExe_dTlb$procResp[12] :
!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1800 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd0 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd0 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1804 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd1 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd1 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1808 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd2 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd2 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1812 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd3 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd3 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1816 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd4 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd4 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1820 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] == 3'd2 ||
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd5 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd5 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1824 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd6 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd6 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1828 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd7 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1832 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd8 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd8 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1836 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd9 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd9 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1840 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd10 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd10 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1844 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd11 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd11 ;
assign IF_coreFix_memExe_dTlb_procResp__714_BIT_182_7_ETC___d1848 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[182] &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735) ?
coreFix_memExe_dTlb$procResp[177:175] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__714_BITS_177__ETC___d1796 ==
4'd12 :
IF_NOT_coreFix_memExe_dTlb_procResp__714_BIT_1_ETC___d1795 ==
4'd12 ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1579 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3750 =
_theResult_____2__h331933 == v__h331501 ;
assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
coreFix_memExe_forwardQ_deqReq_rl ;
assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
coreFix_memExe_forwardQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 } :
{ {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359[15]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 } :
{ {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373[7]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 }) ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 } :
{ {48{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407[15]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 } :
{ {56{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420[7]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 }) ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 } :
{ {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348[31]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 }) :
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 } :
{ {32{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398[31]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) :
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3656 =
_theResult_____2__h328708 == v__h328276 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
coreFix_memExe_memRespLdQ_deqReq_rl ;
assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
coreFix_memExe_memRespLdQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558 =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ;
assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 =
csrf_minstret_ehr_data_lat_0$whas ?
upd__h726048 :
csrf_minstret_ehr_data_rl ;
assign IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909 =
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ?
{ 43'd8192,
csrf_mxr_reg,
csrf_sum_reg,
3'd0,
csrf_fs_reg,
4'b0,
csrf_prv_reg[0],
2'b0,
csrf_ie_vec_1,
csrf_prev_ie_vec_0,
3'd0,
csrf_ie_vec_0 } :
{ 40'd5120,
csrf_tsr_reg,
csrf_tw_reg,
csrf_tvm_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_mprv_reg,
2'd0,
csrf_fs_reg,
csrf_prv_reg,
2'b0,
csrf_spp_reg,
csrf_ie_vec_3,
1'b0,
csrf_prev_ie_vec_1,
csrf_prev_ie_vec_0,
2'd0,
csrf_ie_vec_1,
csrf_ie_vec_0 } ;
assign IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435 =
(fetchStage$RDY_pipelines_0_first &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429) ?
fetchStage$RDY_pipelines_0_first :
!regRenamingTable$rename_0_canRename ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13833 =
(fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1)) ?
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 ||
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13493 ||
NOT_regRenamingTable_rename_1_canRename__3530__ETC___d13801) :
fetchStage$RDY_pipelines_1_first &&
IF_NOT_fetchStage_pipelines_1_first__2766_BITS_ETC___d13831 ;
assign IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13905 =
(fetchStage$RDY_pipelines_1_first &&
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13500 &&
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13739) ?
IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13833 &&
(IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13954 =
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 ||
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign IF_fetchStage_pipelines_0_first__2757_BIT_160__ETC___d14134 =
{ fetchStage$pipelines_0_first[159:128],
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14122,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14125 ?
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14128 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131 } } ;
assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14084 =
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14041 &&
IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13833 &&
(IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14068 ||
rob$RDY_enqPort_1_enq &&
regRenamingTable$RDY_rename_1_claimRename &&
regRenamingTable$RDY_rename_1_getRename &&
fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078) ;
assign IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14306 =
(fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 &&
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14260) ?
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14261 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262 } ;
assign IF_fetchStage_pipelines_1_first__2766_BIT_160__ETC___d14265 =
{ fetchStage$pipelines_1_first[159:128],
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259,
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14260 ?
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14261 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262 } } ;
assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[142] :
mmio_cRqQ_enqReq_rl[142] ;
assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[1] :
mmio_cRsQ_enqReq_rl[1] ;
assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[142] :
mmio_dataReqQ_enqReq_rl[142] ;
assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[65] :
mmio_dataRespQ_enqReq_rl[65] ;
assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[39] :
mmio_pRqQ_enqReq_rl[39] ;
assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 =
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[67] :
mmio_pRsQ_enqReq_rl[67] ;
assign IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 =
rob$deqPort_0_canDeq ? y_avValue_fst__h729252 : 5'd0 ;
assign IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_fst__h729727 :
2'd0 ;
assign IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180 =
(rob$deqPort_0_deq_data[329:325] == 5'd19) ?
csrf_sepc_csr :
csrf_mepc_csr ;
assign IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271 =
(rob$deqPort_0_deq_data[329:325] == 5'd19) ?
{ csrf_mpp_reg,
3'd0,
csrf_prev_ie_vec_3,
2'd1,
csrf_prev_ie_vec_0,
csrf_ie_vec_3,
1'b0,
csrf_prev_ie_vec_1,
csrf_ie_vec_0 } :
{ 4'd0,
csrf_spp_reg,
2'd2,
csrf_prev_ie_vec_1,
csrf_prev_ie_vec_0,
csrf_prev_ie_vec_3,
1'b0,
csrf_ie_vec_1,
csrf_ie_vec_0 } ;
assign IF_rob_deqPort_0_deq_data__4328_BITS_97_TO_96__ETC___d14501 =
{ CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256,
rob$deqPort_0_deq_data[95:32] } ;
assign IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662 =
rob$deqPort_1_canDeq ?
IF_NOT_rob_deqPort_1_deq_data__5311_BIT_25_531_ETC___d15661 :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ;
assign IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139 =
sfdin__h511098[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74 =
sfdin__h417652[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99 =
sfdin__h445581[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179 =
sfdin__h549951[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29 =
sfdin__h354189[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109 =
sfdin__h463347[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39 =
sfdin__h371955[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156 =
sfdin__h589255[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64 =
sfdin__h399886[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135 =
_theResult___snd__h501478[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66 =
_theResult___snd__h408499[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142 =
_theResult___snd__h519883[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79 =
_theResult___snd__h426289[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175 =
_theResult___snd__h540331[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101 =
_theResult___snd__h454194[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182 =
_theResult___snd__h558736[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31 =
_theResult___snd__h362802[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114 =
_theResult___snd__h471984[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152 =
_theResult___snd__h579635[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44 =
_theResult___snd__h380592[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159 =
_theResult___snd__h598040[4] ? 2'd2 : 2'd0 ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5221 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5249 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6613 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6641 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8005 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8033 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[0]) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344 =
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] &&
!checkForException___d13008[4] &&
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337 &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13422 =
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] &&
!checkForException___d13008[4] &&
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420 ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725 =
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] &&
!checkForException___d13698[4] &&
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723 ;
assign NOT_IF_NOT_rob_deqPort_0_canDeq__5303_5304_OR__ETC___d15667 =
(fflags__h732495 & csrf_fflags_reg) != fflags__h732495 ||
csrf_fs_reg != 2'b11 &&
(IF_rob_deqPort_1_canDeq__5308_THEN_IF_NOT_rob__ETC___d15662 ||
fflags__h732495 != 5'd0) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 =
!f2_sfd__h521134[21] && !f2_sfd__h521134[20] &&
!f2_sfd__h521134[19] &&
!f2_sfd__h521134[18] &&
!f2_sfd__h521134[17] &&
!f2_sfd__h521134[16] &&
!f2_sfd__h521134[15] &&
!f2_sfd__h521134[14] &&
!f2_sfd__h521134[13] &&
!f2_sfd__h521134[12] &&
!f2_sfd__h521134[11] &&
!f2_sfd__h521134[10] &&
!f2_sfd__h521134[9] &&
!f2_sfd__h521134[8] &&
!f2_sfd__h521134[7] &&
!f2_sfd__h521134[6] &&
!f2_sfd__h521134[5] &&
!f2_sfd__h521134[4] &&
!f2_sfd__h521134[3] &&
!f2_sfd__h521134[2] &&
!f2_sfd__h521134[1] &&
!f2_sfd__h521134[0] ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) &&
(value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10762 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 =
((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764) |
((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) &&
(f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) &&
(f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10803) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) &&
(value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10862 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 =
((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864) |
((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) &&
(f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) &&
(f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10872) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) &&
(value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10902 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 =
((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904) |
((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) &&
(f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) &&
(f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10916) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) &&
(value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10948 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 =
((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950) |
((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) &&
(f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) &&
(f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10960) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 != 23'd0) &&
(value_BIT_23___h494224 || f1_sfd__h482140 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10990 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 =
((f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992) |
((f2_exp__h521133 != 8'd255 || f2_sfd__h521134 == 23'd0) &&
(f2_exp__h521133 != 8'd255 || f2_sfd__h521134 != 23'd0) &&
(f2_exp__h521133 != 8'd0 || f2_sfd__h521134 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11002) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 =
!f1_sfd__h482140[21] && !f1_sfd__h482140[20] &&
!f1_sfd__h482140[19] &&
!f1_sfd__h482140[18] &&
!f1_sfd__h482140[17] &&
!f1_sfd__h482140[16] &&
!f1_sfd__h482140[15] &&
!f1_sfd__h482140[14] &&
!f1_sfd__h482140[13] &&
!f1_sfd__h482140[12] &&
!f1_sfd__h482140[11] &&
!f1_sfd__h482140[10] &&
!f1_sfd__h482140[9] &&
!f1_sfd__h482140[8] &&
!f1_sfd__h482140[7] &&
!f1_sfd__h482140[6] &&
!f1_sfd__h482140[5] &&
!f1_sfd__h482140[4] &&
!f1_sfd__h482140[3] &&
!f1_sfd__h482140[2] &&
!f1_sfd__h482140[1] &&
!f1_sfd__h482140[0] ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 =
!f3_sfd__h560438[21] && !f3_sfd__h560438[20] &&
!f3_sfd__h560438[19] &&
!f3_sfd__h560438[18] &&
!f3_sfd__h560438[17] &&
!f3_sfd__h560438[16] &&
!f3_sfd__h560438[15] &&
!f3_sfd__h560438[14] &&
!f3_sfd__h560438[13] &&
!f3_sfd__h560438[12] &&
!f3_sfd__h560438[11] &&
!f3_sfd__h560438[10] &&
!f3_sfd__h560438[9] &&
!f3_sfd__h560438[8] &&
!f3_sfd__h560438[7] &&
!f3_sfd__h560438[6] &&
!f3_sfd__h560438[5] &&
!f3_sfd__h560438[4] &&
!f3_sfd__h560438[3] &&
!f3_sfd__h560438[2] &&
!f3_sfd__h560438[1] &&
!f3_sfd__h560438[0] ;
assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 ;
assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614 =
(!commitStage_commitTrap[36] ||
commitStage_commitTrap[35:32] == 4'd0 ||
commitStage_commitTrap[35:32] == 4'd1 ||
commitStage_commitTrap[35:32] == 4'd3 ||
commitStage_commitTrap[35:32] == 4'd4 ||
commitStage_commitTrap[35:32] == 4'd5 ||
commitStage_commitTrap[35:32] == 4'd7 ||
commitStage_commitTrap[35:32] == 4'd8 ||
commitStage_commitTrap[35:32] == 4'd9 ||
commitStage_commitTrap[35:32] == 4'd11) &&
(commitStage_commitTrap[36] ||
commitStage_commitTrap[35:32] != 4'd3 ||
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ;
assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14621 =
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14614 ||
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq ;
assign NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 =
(!commitStage_commitTrap[36] ||
commitStage_commitTrap[35:32] != 4'd14) &&
(!commitStage_commitTrap[36] ||
commitStage_commitTrap[35:32] == 4'd0 ||
commitStage_commitTrap[35:32] == 4'd1 ||
commitStage_commitTrap[35:32] == 4'd3 ||
commitStage_commitTrap[35:32] == 4'd4 ||
commitStage_commitTrap[35:32] == 4'd5 ||
commitStage_commitTrap[35:32] == 4'd7 ||
commitStage_commitTrap[35:32] == 4'd8 ||
commitStage_commitTrap[35:32] == 4'd9 ||
commitStage_commitTrap[35:32] == 4'd11 ||
commitStage_commitTrap[35:32] == 4'd14) &&
(commitStage_commitTrap[36] ||
commitStage_commitTrap[35:32] != 4'd3 ||
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244) ;
assign NOT_commitStage_rg_run_state_4334_4335_AND_NOT_ETC___d14995 =
!commitStage_rg_run_state && !commitStage_commitTrap[165] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
rob$deqPort_0_deq_data[25] ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226) ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281) ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ;
assign NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592) ;
assign NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2526 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2666 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3057 =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3078 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3127 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3183 =
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3180) &&
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153 ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 =
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2123 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2533 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2535 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2533) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2578 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2577 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2581 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2578) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2598 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2561) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2605 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2630 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2638 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2646 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2655 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2677 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2050 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 =
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3298 =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3355 =
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) &&
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324 ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3394 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3451 =
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3447) &&
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420 ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1883 =
!coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1927 =
(!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) &&
(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_deqReq_rl ||
coreFix_memExe_dMem_perfReqQ_empty) ;
assign NOT_coreFix_memExe_dTlb_procResp__714_BITS_246_ETC___d1755 =
!coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726 &&
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727 &&
!coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731 &&
!coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734 ;
assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3717 =
!coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_forwardQ_clearReq_rl ;
assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3772 =
(!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
!coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_forwardQ_enqReq_rl[69])) &&
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743 ||
coreFix_memExe_forwardQ_empty) ;
assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3623 =
!coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_memRespLdQ_clearReq_rl ;
assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3678 =
(!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
!coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_memRespLdQ_enqReq_rl[69])) &&
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649 ||
coreFix_memExe_memRespLdQ_empty) ;
assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1474 =
!coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLdQ_full_rl ;
assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 =
!coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3547 =
!coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_clearReq_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3589 =
(!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
!coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
!coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) &&
(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT &&
(coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ||
coreFix_memExe_respLrScAmoQ_deqReq_rl) ||
coreFix_memExe_respLrScAmoQ_empty) ;
assign NOT_coreFix_memExe_respLrScAmoQ_full_952_953_A_ETC___d2082 =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ;
assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13337 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[199:195] != 5'd13 ||
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 &&
!csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 &&
csr_addr__h655325 != 12'h8FF) ;
assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_1_first[95] ||
!fetchStage$pipelines_1_first[94]) &&
(!fetchStage$pipelines_1_first[88] ||
!fetchStage$pipelines_1_first[87]) &&
!fetchStage$pipelines_1_first[81] &&
(!fetchStage$pipelines_1_first[75] ||
!fetchStage$pipelines_1_first[74])) &&
(fetchStage$pipelines_1_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_prv_reg_read__2787_ULE_1_4685_4727_OR_ETC___d14731 =
!csrf_prv_reg_read__2787_ULE_1___d14685 ||
(commitStage_commitTrap[36] ?
!_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 :
!_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705) ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13527 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13509 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13524 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13761 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13814 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
NOT_regRenamingTable_rename_1_canRename__3530__ETC___d13801) ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13869 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13509 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13887 =
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13837 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519) &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14036 =
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14007) &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 &&
(fetchStage$pipelines_1_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14090 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13956 &&
IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435) &&
fetchStage$RDY_pipelines_0_first &&
fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14088 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d14184 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 =
(!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13465) &&
fetchStage$pipelines_1_canDeq ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14196 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13524 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208 =
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205 &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1) &&
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14252 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 =
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14252 &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
assign NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14283 =
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14196 &&
specTagManager$canClaim &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204 &&
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 &&
fetchStage$pipelines_1_first[194:192] == 3'd1 ;
assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13331 =
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
fetchStage$pipelines_0_first[178:174] != 5'd15) &&
rs1__h655326 == 5'd0 &&
imm__h655327 == 32'd0 ||
csr_addr__h655325[11:10] != 2'b11 ;
assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13466 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13465 ;
assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 &&
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 ;
assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 &&
(!coreFix_aluExe_0_rsAlu$canEnq ||
!coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444) ;
assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13913 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ;
assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq ;
assign NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14166 =
{ fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14122,
(fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14125) ?
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14128 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131 },
7'd32,
specTagManager$currentSpecBits } ;
assign NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13477 =
!fetchStage$pipelines_0_first[68] &&
!checkForException___d13008[4] &&
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13420 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_fetchStage_pipelines_1_canDeq__2763_2764_O_ETC___d12772 =
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(epochManager$checkEpoch_1_check ||
fetchStage$RDY_pipelines_1_deq) ;
assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13500 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13493 ||
csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498) ;
assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13739 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13527 &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738 ;
assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13856 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13837 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13850 ||
fetchStage$pipelines_0_first[194:192] != 3'd1) &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738 ;
assign NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d14205 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14196 &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204 ;
assign NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14202 =
!fetchStage$pipelines_1_first[68] &&
!checkForException___d13698[4] &&
NOT_csrf_fs_reg_read__1546_EQ_0_2997_2998_OR_N_ETC___d13723 &&
rob$enqPort_1_canEnq &&
epochManager$checkEpoch_1_check &&
!csrf_rg_dcsr[2] ;
assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 =
!mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ;
assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 =
(!mmio_cRqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_cRqQ_enqReq_lat_0$whas ?
!mmio_cRqQ_enqReq_lat_0$wget[142] :
!mmio_cRqQ_enqReq_rl[142])) &&
(mmio_cRqQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) ||
mmio_cRqQ_empty) ;
assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 =
!mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ;
assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 =
(!mmio_cRsQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_handlePRq ?
!mmio_cRsQ_enqReq_lat_0$wget[1] :
!mmio_cRsQ_enqReq_rl[1])) &&
(mmio_cRsQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) ||
mmio_cRsQ_empty) ;
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt ;
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd ;
assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 =
(!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT ||
!mmio_dataPendQ_enqReq_lat_0$whas &&
!mmio_dataPendQ_enqReq_rl) &&
(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataPendQ_deqReq_rl) ||
mmio_dataPendQ_empty) ;
assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 =
!mmio_dataReqQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataReqQ_clearReq_rl ;
assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 =
(!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_dataReqQ_enqReq_lat_0$whas ?
!mmio_dataReqQ_enqReq_lat_0$wget[142] :
!mmio_dataReqQ_enqReq_rl[142])) &&
(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) ||
mmio_dataReqQ_empty) ;
assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 =
!mmio_dataRespQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataRespQ_clearReq_rl ;
assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 =
(!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_sendDataResp ?
!mmio_dataRespQ_enqReq_lat_0$wget[65] :
!mmio_dataRespQ_enqReq_rl[65])) &&
(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataRespQ_deqReq_rl) ||
mmio_dataRespQ_empty) ;
assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 =
!mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ;
assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 =
(!mmio_pRqQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRq_enq ?
!mmio_pRqQ_enqReq_lat_0$wget[39] :
!mmio_pRqQ_enqReq_rl[39])) &&
(mmio_pRqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) ||
mmio_pRqQ_empty) ;
assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 =
!mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ;
assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 =
(!mmio_pRsQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[67] :
!mmio_pRsQ_enqReq_rl[67])) &&
(mmio_pRsQ_deqReq_dummy2_2$Q_OUT &&
(mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) ||
mmio_pRsQ_empty) ;
assign NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13761 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13759 ;
assign NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13837 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13835 ;
assign NOT_regRenamingTable_rename_0_canRename__3403__ETC___d14184 =
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13008[4] ||
!rob$enqPort_0_canEnq ;
assign NOT_regRenamingTable_rename_1_canRename__3530__ETC___d13801 =
!regRenamingTable$rename_1_canRename ||
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13799 ;
assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13102 =
!renameStage_rg_m_halt_req[4] &&
(fetchStage$pipelines_0_first[68] ||
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15]) ;
assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13427 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13422 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13736 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734 ;
assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13878 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13876 ;
assign NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13896 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13725 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13894 ;
assign NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_RDY_ETC___d15345 =
(!rob$deqPort_0_canDeq ||
rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit &&
v_f_to_TV_0$FULL_N) &&
(!rob$deqPort_1_canDeq ||
rob$RDY_deqPort_1_deq_data &&
NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342) ;
assign NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 =
(!rob$deqPort_0_canDeq ||
rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[329:325] != 5'd0 &&
rob$deqPort_0_deq_data[329:325] != 5'd21 &&
rob$deqPort_0_deq_data[329:325] != 5'd17 &&
rob$deqPort_0_deq_data[329:325] != 5'd18 &&
rob$deqPort_0_deq_data[329:325] != 5'd13 &&
rob$deqPort_0_deq_data[329:325] != 5'd16 &&
rob$deqPort_0_deq_data[329:325] != 5'd15 &&
rob$deqPort_0_deq_data[329:325] != 5'd19 &&
rob$deqPort_0_deq_data[329:325] != 5'd20) &&
rob$deqPort_1_canDeq ;
assign NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983 =
rob$deqPort_0_deq_data[329:325] != 5'd13 ||
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 !=
6'd7 ||
csrf_stats_module_writeQ$FULL_N) &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 !=
6'd6 ||
csrf_terminate_module_terminateQ$FULL_N) ;
assign NOT_rob_deqPort_1_deq_data__5311_BIT_25_5312_5_ETC___d15342 =
!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[329:325] == 5'd0 ||
rob$deqPort_1_deq_data[329:325] == 5'd21 ||
rob$deqPort_1_deq_data[329:325] == 5'd17 ||
rob$deqPort_1_deq_data[329:325] == 5'd18 ||
rob$deqPort_1_deq_data[329:325] == 5'd13 ||
rob$deqPort_1_deq_data[329:325] == 5'd16 ||
rob$deqPort_1_deq_data[329:325] == 5'd15 ||
rob$deqPort_1_deq_data[329:325] == 5'd19 ||
rob$deqPort_1_deq_data[329:325] == 5'd20 ||
rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit &&
v_f_to_TV_1$FULL_N ;
assign NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14007 =
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13509 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14074 =
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2920,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2929,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2945 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2938,
x__h291615 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d16083 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16039,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16057 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d16048,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 =
{ {4{f2_exp21133_MINUS_127__q176[7]}},
f2_exp21133_MINUS_127__q176 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 =
{ {4{f1_exp82139_MINUS_127__q136[7]}},
f1_exp82139_MINUS_127__q136 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 =
{ {4{f3_exp60437_MINUS_127__q153[7]}},
f3_exp60437_MINUS_127__q153 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
11'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
11'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
11'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71[10],
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36[10],
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106[10],
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169 =
{ 3'd0,
_theResult___fst_exp__h354195 == 8'd0 &&
(sfdin__h354189[56:34] == 23'd0 || guard__h346094 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h354792 == 8'd255 &&
_theResult___fst_sfd__h354793 == 23'd0,
1'd0,
_theResult___fst_exp__h354195 != 8'd255 &&
guard__h346094 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561 =
{ 3'd0,
_theResult___fst_exp__h399892 == 8'd0 &&
(sfdin__h399886[56:34] == 23'd0 || guard__h391793 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h400489 == 8'd255 &&
_theResult___fst_sfd__h400490 == 23'd0,
1'd0,
_theResult___fst_exp__h399892 != 8'd255 &&
guard__h391793 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953 =
{ 3'd0,
_theResult___fst_exp__h445587 == 8'd0 &&
(sfdin__h445581[56:34] == 23'd0 || guard__h437488 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h446184 == 8'd255 &&
_theResult___fst_sfd__h446185 == 23'd0,
1'd0,
_theResult___fst_exp__h445587 != 8'd255 &&
guard__h437488 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10758 =
{ 3'd0,
_theResult___fst_exp__h511104 == 11'd0 &&
(sfdin__h511098[56:5] == 52'd0 || guard__h502878 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h511936 == 11'd2047 &&
_theResult___fst_sfd__h511937 == 52'd0,
1'd0,
_theResult___fst_exp__h511104 != 11'd2047 &&
guard__h502878 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10799 =
{ 3'd0,
_theResult___fst_exp__h549957 == 11'd0 &&
(sfdin__h549951[56:5] == 52'd0 || guard__h541731 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h550789 == 11'd2047 &&
_theResult___fst_sfd__h550790 == 52'd0,
1'd0,
_theResult___fst_exp__h549957 != 11'd2047 &&
guard__h541731 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10843 =
{ 3'd0,
_theResult___fst_exp__h589261 == 11'd0 &&
(sfdin__h589255[56:5] == 52'd0 || guard__h581035 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h590093 == 11'd2047 &&
_theResult___fst_sfd__h590094 == 52'd0,
1'd0,
_theResult___fst_exp__h589261 != 11'd2047 &&
guard__h581035 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5198 =
{ 3'd0,
_theResult___fst_exp__h371961 == 8'd0 &&
(sfdin__h371955[56:34] == 23'd0 || guard__h363733 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h372558 == 8'd255 &&
_theResult___fst_sfd__h372559 == 23'd0,
1'd0,
_theResult___fst_exp__h371961 != 8'd255 &&
guard__h363733 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6590 =
{ 3'd0,
_theResult___fst_exp__h417658 == 8'd0 &&
(sfdin__h417652[56:34] == 23'd0 || guard__h409430 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h418255 == 8'd255 &&
_theResult___fst_sfd__h418256 == 23'd0,
1'd0,
_theResult___fst_exp__h417658 != 8'd255 &&
guard__h409430 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7982 =
{ 3'd0,
_theResult___fst_exp__h463353 == 8'd0 &&
(sfdin__h463347[56:34] == 23'd0 || guard__h455125 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h463950 == 8'd255 &&
_theResult___fst_sfd__h463951 == 23'd0,
1'd0,
_theResult___fst_exp__h463353 != 8'd255 &&
guard__h455125 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ^
12'h800) ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10741 =
{ 3'd0,
_theResult___fst_exp__h501527 == 11'd0 &&
guard__h493566 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h502285 == 11'd2047 &&
_theResult___fst_sfd__h502286 == 52'd0,
1'd0,
_theResult___fst_exp__h501527 != 11'd2047 &&
guard__h493566 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10782 =
{ 3'd0,
_theResult___fst_exp__h540380 == 11'd0 &&
guard__h532419 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h541138 == 11'd2047 &&
_theResult___fst_sfd__h541139 == 52'd0,
1'd0,
_theResult___fst_exp__h540380 != 11'd2047 &&
guard__h532419 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10826 =
{ 3'd0,
_theResult___fst_exp__h579684 == 11'd0 &&
guard__h571723 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h580442 == 11'd2047 &&
_theResult___fst_sfd__h580443 == 52'd0,
1'd0,
_theResult___fst_exp__h579684 != 11'd2047 &&
guard__h571723 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ^
12'h800) ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ^
12'h800) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181 =
{ 3'd0,
_theResult___fst_exp__h362851 == 8'd0 &&
guard__h354803 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h363374 == 8'd255 &&
_theResult___fst_sfd__h363375 == 23'd0,
1'd0,
_theResult___fst_exp__h362851 != 8'd255 &&
guard__h354803 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573 =
{ 3'd0,
_theResult___fst_exp__h408548 == 8'd0 &&
guard__h400500 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h409071 == 8'd255 &&
_theResult___fst_sfd__h409072 == 23'd0,
1'd0,
_theResult___fst_exp__h408548 != 8'd255 &&
guard__h400500 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965 =
{ 3'd0,
_theResult___fst_exp__h454243 == 8'd0 &&
guard__h446195 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h454766 == 8'd255 &&
_theResult___fst_sfd__h454767 == 23'd0,
1'd0,
_theResult___fst_exp__h454243 != 8'd255 &&
guard__h446195 != 2'b0 } ;
assign _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798 =
{ 4'd0,
csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3,
1'd0,
csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1,
1'd0,
csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3,
1'd0,
csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1,
1'd0 } ;
assign _0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ;
assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d13829 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13493 ||
NOT_regRenamingTable_rename_1_canRename__3530__ETC___d13801) ;
assign _0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14020 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138 =
sfd__h521495 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653 =
sfd__h482501 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368 =
sfd__h560799 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558 =
sfd__h338479 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950 =
sfd__h384181 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342 =
sfd__h429876 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338) ;
assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705 =
medeleg_csr__read__h610369[i__h708478] ;
assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 =
mideleg_csr__read__h610464[i__h708638] ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4011 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5184 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5209 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5236 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5169[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5181[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5403 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6576 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6601 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6628 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6561[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6573[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6795 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7968 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7993 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8020 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7953[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7965[1]) ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10131 ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8646 ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9361 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 =
12'd3970 -
{ 7'd0,
f2_sfd__h521134[22] ?
5'd0 :
(f2_sfd__h521134[21] ?
5'd1 :
(f2_sfd__h521134[20] ?
5'd2 :
(f2_sfd__h521134[19] ?
5'd3 :
(f2_sfd__h521134[18] ?
5'd4 :
(f2_sfd__h521134[17] ?
5'd5 :
(f2_sfd__h521134[16] ?
5'd6 :
(f2_sfd__h521134[15] ?
5'd7 :
(f2_sfd__h521134[14] ?
5'd8 :
(f2_sfd__h521134[13] ?
5'd9 :
(f2_sfd__h521134[12] ?
5'd10 :
(f2_sfd__h521134[11] ?
5'd11 :
(f2_sfd__h521134[10] ?
5'd12 :
(f2_sfd__h521134[9] ?
5'd13 :
(f2_sfd__h521134[8] ?
5'd14 :
(f2_sfd__h521134[7] ?
5'd15 :
(f2_sfd__h521134[6] ?
5'd16 :
(f2_sfd__h521134[5] ?
5'd17 :
(f2_sfd__h521134[4] ?
5'd18 :
(f2_sfd__h521134[3] ?
5'd19 :
(f2_sfd__h521134[2] ?
5'd20 :
(f2_sfd__h521134[1] ?
5'd21 :
(f2_sfd__h521134[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 =
12'd3970 -
{ 7'd0,
f1_sfd__h482140[22] ?
5'd0 :
(f1_sfd__h482140[21] ?
5'd1 :
(f1_sfd__h482140[20] ?
5'd2 :
(f1_sfd__h482140[19] ?
5'd3 :
(f1_sfd__h482140[18] ?
5'd4 :
(f1_sfd__h482140[17] ?
5'd5 :
(f1_sfd__h482140[16] ?
5'd6 :
(f1_sfd__h482140[15] ?
5'd7 :
(f1_sfd__h482140[14] ?
5'd8 :
(f1_sfd__h482140[13] ?
5'd9 :
(f1_sfd__h482140[12] ?
5'd10 :
(f1_sfd__h482140[11] ?
5'd11 :
(f1_sfd__h482140[10] ?
5'd12 :
(f1_sfd__h482140[9] ?
5'd13 :
(f1_sfd__h482140[8] ?
5'd14 :
(f1_sfd__h482140[7] ?
5'd15 :
(f1_sfd__h482140[6] ?
5'd16 :
(f1_sfd__h482140[5] ?
5'd17 :
(f1_sfd__h482140[4] ?
5'd18 :
(f1_sfd__h482140[3] ?
5'd19 :
(f1_sfd__h482140[2] ?
5'd20 :
(f1_sfd__h482140[1] ?
5'd21 :
(f1_sfd__h482140[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 =
12'd3970 -
{ 7'd0,
f3_sfd__h560438[22] ?
5'd0 :
(f3_sfd__h560438[21] ?
5'd1 :
(f3_sfd__h560438[20] ?
5'd2 :
(f3_sfd__h560438[19] ?
5'd3 :
(f3_sfd__h560438[18] ?
5'd4 :
(f3_sfd__h560438[17] ?
5'd5 :
(f3_sfd__h560438[16] ?
5'd6 :
(f3_sfd__h560438[15] ?
5'd7 :
(f3_sfd__h560438[14] ?
5'd8 :
(f3_sfd__h560438[13] ?
5'd9 :
(f3_sfd__h560438[12] ?
5'd10 :
(f3_sfd__h560438[11] ?
5'd11 :
(f3_sfd__h560438[10] ?
5'd12 :
(f3_sfd__h560438[9] ?
5'd13 :
(f3_sfd__h560438[8] ?
5'd14 :
(f3_sfd__h560438[7] ?
5'd15 :
(f3_sfd__h560438[6] ?
5'd16 :
(f3_sfd__h560438[5] ?
5'd17 :
(f3_sfd__h560438[4] ?
5'd18 :
(f3_sfd__h560438[3] ?
5'd19 :
(f3_sfd__h560438[2] ?
5'd20 :
(f3_sfd__h560438[1] ?
5'd21 :
(f3_sfd__h560438[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4551 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5943 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7335 ;
assign _dfoo12 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14118 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 &&
fetchStage$pipelines_1_first[199:195] != 5'd14 ;
assign _dfoo16 =
k__h669623 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 ||
(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) ==
1'd1 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208 ;
assign _dfoo18 =
k__h669623 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 ||
(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14189) ==
1'd0 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14208 ;
assign _dfoo2 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 &&
fetchStage$pipelines_1_first[191:189] != 3'd0 &&
fetchStage$pipelines_1_first[191:189] != 3'd2 ;
assign _dfoo20 =
commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 ||
NOT_commitStage_commitTrap_4336_BIT_36_4579_45_ETC___d14684 ;
assign _dfoo24 =
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd40 ||
rob$deqPort_0_deq_data[329:325] == 5'd19 ||
rob$deqPort_0_deq_data[329:325] == 5'd20 ;
assign _dfoo26 =
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18 ||
rob$deqPort_0_deq_data[329:325] == 5'd20 ;
assign _dfoo32 =
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 ==
6'd18) ||
rob$deqPort_0_deq_data[329:325] == 5'd19 ;
assign _dfoo7 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138 ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14194 &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14253 &&
(fetchStage$pipelines_1_first[191:189] == 3'd0 ||
fetchStage$pipelines_1_first[191:189] == 3'd2) ;
assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_aluExe_1_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_memExe_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1rf$EN_write_0_wr =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1rf$EN_write_1_wr =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1sbAggr$EN_setReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1sbCons$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1sbCons$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _theResult_____2__h296520 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3046) ?
next_deqP___1__h296799 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ;
assign _theResult_____2__h304516 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3153) ?
next_deqP___1__h304795 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ;
assign _theResult_____2__h310510 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3324) ?
next_deqP___1__h311076 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ;
assign _theResult_____2__h318364 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3420) ?
next_deqP___1__h318930 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ;
assign _theResult_____2__h328708 =
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3649) ?
next_deqP___1__h328987 :
coreFix_memExe_memRespLdQ_deqP ;
assign _theResult_____2__h331933 =
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3743) ?
next_deqP___1__h332212 :
coreFix_memExe_forwardQ_deqP ;
assign _theResult____h346084 =
(value__h346706 == 54'd0) ? sfd__h338479 : 57'd1 ;
assign _theResult____h363723 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ^
12'h800) <
12'd2105) ?
result__h364336 :
_theResult____h346084 ;
assign _theResult____h391783 =
(value__h392403 == 54'd0) ? sfd__h384181 : 57'd1 ;
assign _theResult____h409420 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ^
12'h800) <
12'd2105) ?
result__h410033 :
_theResult____h391783 ;
assign _theResult____h437478 =
(value__h438098 == 54'd0) ? sfd__h429876 : 57'd1 ;
assign _theResult____h455115 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ^
12'h800) <
12'd2105) ?
result__h455728 :
_theResult____h437478 ;
assign _theResult____h502868 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ^
12'h800) <
12'd2105) ?
result__h503481 :
((value__h487084 == 25'd0) ? sfd__h482501 : 57'd1) ;
assign _theResult____h541721 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ^
12'h800) <
12'd2105) ?
result__h542334 :
((value__h525937 == 25'd0) ? sfd__h521495 : 57'd1) ;
assign _theResult____h581025 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ^
12'h800) <
12'd2105) ?
result__h581638 :
((value__h565241 == 25'd0) ? sfd__h560799 : 57'd1) ;
assign _theResult____h651116 =
(csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ?
enabled_ints___1__h651641 :
16'd0 ;
assign _theResult___exp__h354711 =
sfd__h354287[24] ?
((_theResult___fst_exp__h354195 == 8'd254) ?
8'd255 :
din_inc___2_exp__h381228) :
((_theResult___fst_exp__h354195 == 8'd0 &&
sfd__h354287[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h354195) ;
assign _theResult___exp__h363293 =
sfd__h362869[24] ?
((_theResult___fst_exp__h362851 == 8'd254) ?
8'd255 :
din_inc___2_exp__h381252) :
((_theResult___fst_exp__h362851 == 8'd0 &&
sfd__h362869[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h362851) ;
assign _theResult___exp__h372477 =
sfd__h372053[24] ?
((_theResult___fst_exp__h371961 == 8'd254) ?
8'd255 :
din_inc___2_exp__h381282) :
((_theResult___fst_exp__h371961 == 8'd0 &&
sfd__h372053[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h371961) ;
assign _theResult___exp__h381113 =
sfd__h380665[24] ?
((_theResult___fst_exp__h380646 == 8'd254) ?
8'd255 :
din_inc___2_exp__h381306) :
((_theResult___fst_exp__h380646 == 8'd0 &&
sfd__h380665[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h380646) ;
assign _theResult___exp__h381215 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h381206 ;
assign _theResult___exp__h400408 =
sfd__h399984[24] ?
((_theResult___fst_exp__h399892 == 8'd254) ?
8'd255 :
din_inc___2_exp__h426925) :
((_theResult___fst_exp__h399892 == 8'd0 &&
sfd__h399984[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h399892) ;
assign _theResult___exp__h408990 =
sfd__h408566[24] ?
((_theResult___fst_exp__h408548 == 8'd254) ?
8'd255 :
din_inc___2_exp__h426949) :
((_theResult___fst_exp__h408548 == 8'd0 &&
sfd__h408566[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h408548) ;
assign _theResult___exp__h418174 =
sfd__h417750[24] ?
((_theResult___fst_exp__h417658 == 8'd254) ?
8'd255 :
din_inc___2_exp__h426979) :
((_theResult___fst_exp__h417658 == 8'd0 &&
sfd__h417750[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h417658) ;
assign _theResult___exp__h426810 =
sfd__h426362[24] ?
((_theResult___fst_exp__h426343 == 8'd254) ?
8'd255 :
din_inc___2_exp__h427003) :
((_theResult___fst_exp__h426343 == 8'd0 &&
sfd__h426362[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h426343) ;
assign _theResult___exp__h426912 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h426903 ;
assign _theResult___exp__h446103 =
sfd__h445679[24] ?
((_theResult___fst_exp__h445587 == 8'd254) ?
8'd255 :
din_inc___2_exp__h472620) :
((_theResult___fst_exp__h445587 == 8'd0 &&
sfd__h445679[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h445587) ;
assign _theResult___exp__h454685 =
sfd__h454261[24] ?
((_theResult___fst_exp__h454243 == 8'd254) ?
8'd255 :
din_inc___2_exp__h472644) :
((_theResult___fst_exp__h454243 == 8'd0 &&
sfd__h454261[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h454243) ;
assign _theResult___exp__h463869 =
sfd__h463445[24] ?
((_theResult___fst_exp__h463353 == 8'd254) ?
8'd255 :
din_inc___2_exp__h472674) :
((_theResult___fst_exp__h463353 == 8'd0 &&
sfd__h463445[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h463353) ;
assign _theResult___exp__h472505 =
sfd__h472057[24] ?
((_theResult___fst_exp__h472038 == 8'd254) ?
8'd255 :
din_inc___2_exp__h472698) :
((_theResult___fst_exp__h472038 == 8'd0 &&
sfd__h472057[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h472038) ;
assign _theResult___exp__h472607 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h472598 ;
assign _theResult___exp__h502182 =
sfd__h501545[53] ?
((_theResult___fst_exp__h501527 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h520777) :
((_theResult___fst_exp__h501527 == 11'd0 &&
sfd__h501545[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h501527) ;
assign _theResult___exp__h511833 =
sfd__h511196[53] ?
((_theResult___fst_exp__h511104 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h520812) :
((_theResult___fst_exp__h511104 == 11'd0 &&
sfd__h511196[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h511104) ;
assign _theResult___exp__h520617 =
sfd__h519956[53] ?
((_theResult___fst_exp__h519937 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h520838) :
((_theResult___fst_exp__h519937 == 11'd0 &&
sfd__h519956[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h519937) ;
assign _theResult___exp__h541035 =
sfd__h540398[53] ?
((_theResult___fst_exp__h540380 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h559630) :
((_theResult___fst_exp__h540380 == 11'd0 &&
sfd__h540398[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h540380) ;
assign _theResult___exp__h550686 =
sfd__h550049[53] ?
((_theResult___fst_exp__h549957 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h559665) :
((_theResult___fst_exp__h549957 == 11'd0 &&
sfd__h550049[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h549957) ;
assign _theResult___exp__h559470 =
sfd__h558809[53] ?
((_theResult___fst_exp__h558790 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h559691) :
((_theResult___fst_exp__h558790 == 11'd0 &&
sfd__h558809[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h558790) ;
assign _theResult___exp__h580339 =
sfd__h579702[53] ?
((_theResult___fst_exp__h579684 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h598934) :
((_theResult___fst_exp__h579684 == 11'd0 &&
sfd__h579702[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h579684) ;
assign _theResult___exp__h589990 =
sfd__h589353[53] ?
((_theResult___fst_exp__h589261 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h598969) :
((_theResult___fst_exp__h589261 == 11'd0 &&
sfd__h589353[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h589261) ;
assign _theResult___exp__h598774 =
sfd__h598113[53] ?
((_theResult___fst_exp__h598094 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h598995) :
((_theResult___fst_exp__h598094 == 11'd0 &&
sfd__h598113[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h598094) ;
assign _theResult___fst__h603369 =
a__h602947[63] ? a___1__h603374 : a__h602947 ;
assign _theResult___fst_exp__h354195 =
_theResult____h346084[56] ?
8'd2 :
_theResult___fst_exp__h354269 ;
assign _theResult___fst_exp__h354260 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 } ;
assign _theResult___fst_exp__h354266 =
(!_theResult____h346084[56] && !_theResult____h346084[55] &&
!_theResult____h346084[54] &&
!_theResult____h346084[53] &&
!_theResult____h346084[52] &&
!_theResult____h346084[51] &&
!_theResult____h346084[50] &&
!_theResult____h346084[49] &&
!_theResult____h346084[48] &&
!_theResult____h346084[47] &&
!_theResult____h346084[46] &&
!_theResult____h346084[45] &&
!_theResult____h346084[44] &&
!_theResult____h346084[43] &&
!_theResult____h346084[42] &&
!_theResult____h346084[41] &&
!_theResult____h346084[40] &&
!_theResult____h346084[39] &&
!_theResult____h346084[38] &&
!_theResult____h346084[37] &&
!_theResult____h346084[36] &&
!_theResult____h346084[35] &&
!_theResult____h346084[34] &&
!_theResult____h346084[33] &&
!_theResult____h346084[32] &&
!_theResult____h346084[31] &&
!_theResult____h346084[30] &&
!_theResult____h346084[29] &&
!_theResult____h346084[28] &&
!_theResult____h346084[27] &&
!_theResult____h346084[26] &&
!_theResult____h346084[25] &&
!_theResult____h346084[24] &&
!_theResult____h346084[23] &&
!_theResult____h346084[22] &&
!_theResult____h346084[21] &&
!_theResult____h346084[20] &&
!_theResult____h346084[19] &&
!_theResult____h346084[18] &&
!_theResult____h346084[17] &&
!_theResult____h346084[16] &&
!_theResult____h346084[15] &&
!_theResult____h346084[14] &&
!_theResult____h346084[13] &&
!_theResult____h346084[12] &&
!_theResult____h346084[11] &&
!_theResult____h346084[10] &&
!_theResult____h346084[9] &&
!_theResult____h346084[8] &&
!_theResult____h346084[7] &&
!_theResult____h346084[6] &&
!_theResult____h346084[5] &&
!_theResult____h346084[4] &&
!_theResult____h346084[3] &&
!_theResult____h346084[2] &&
!_theResult____h346084[1] &&
!_theResult____h346084[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4249) ?
8'd0 :
_theResult___fst_exp__h354260 ;
assign _theResult___fst_exp__h354269 =
(!_theResult____h346084[56] && _theResult____h346084[55]) ?
8'd1 :
_theResult___fst_exp__h354266 ;
assign _theResult___fst_exp__h354792 =
(_theResult___fst_exp__h354195 == 8'd255) ?
_theResult___fst_exp__h354195 :
_theResult___fst_exp__h354789 ;
assign _theResult___fst_exp__h362842 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ;
assign _theResult___fst_exp__h362848 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4480) ?
8'd0 :
_theResult___fst_exp__h362842 ;
assign _theResult___fst_exp__h362851 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h362848 :
8'd129 ;
assign _theResult___fst_exp__h363374 =
(_theResult___fst_exp__h362851 == 8'd255) ?
_theResult___fst_exp__h362851 :
_theResult___fst_exp__h363371 ;
assign _theResult___fst_exp__h371961 =
_theResult____h363723[56] ?
8'd2 :
_theResult___fst_exp__h372035 ;
assign _theResult___fst_exp__h372026 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 } ;
assign _theResult___fst_exp__h372032 =
(!_theResult____h363723[56] && !_theResult____h363723[55] &&
!_theResult____h363723[54] &&
!_theResult____h363723[53] &&
!_theResult____h363723[52] &&
!_theResult____h363723[51] &&
!_theResult____h363723[50] &&
!_theResult____h363723[49] &&
!_theResult____h363723[48] &&
!_theResult____h363723[47] &&
!_theResult____h363723[46] &&
!_theResult____h363723[45] &&
!_theResult____h363723[44] &&
!_theResult____h363723[43] &&
!_theResult____h363723[42] &&
!_theResult____h363723[41] &&
!_theResult____h363723[40] &&
!_theResult____h363723[39] &&
!_theResult____h363723[38] &&
!_theResult____h363723[37] &&
!_theResult____h363723[36] &&
!_theResult____h363723[35] &&
!_theResult____h363723[34] &&
!_theResult____h363723[33] &&
!_theResult____h363723[32] &&
!_theResult____h363723[31] &&
!_theResult____h363723[30] &&
!_theResult____h363723[29] &&
!_theResult____h363723[28] &&
!_theResult____h363723[27] &&
!_theResult____h363723[26] &&
!_theResult____h363723[25] &&
!_theResult____h363723[24] &&
!_theResult____h363723[23] &&
!_theResult____h363723[22] &&
!_theResult____h363723[21] &&
!_theResult____h363723[20] &&
!_theResult____h363723[19] &&
!_theResult____h363723[18] &&
!_theResult____h363723[17] &&
!_theResult____h363723[16] &&
!_theResult____h363723[15] &&
!_theResult____h363723[14] &&
!_theResult____h363723[13] &&
!_theResult____h363723[12] &&
!_theResult____h363723[11] &&
!_theResult____h363723[10] &&
!_theResult____h363723[9] &&
!_theResult____h363723[8] &&
!_theResult____h363723[7] &&
!_theResult____h363723[6] &&
!_theResult____h363723[5] &&
!_theResult____h363723[4] &&
!_theResult____h363723[3] &&
!_theResult____h363723[2] &&
!_theResult____h363723[1] &&
!_theResult____h363723[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4800) ?
8'd0 :
_theResult___fst_exp__h372026 ;
assign _theResult___fst_exp__h372035 =
(!_theResult____h363723[56] && _theResult____h363723[55]) ?
8'd1 :
_theResult___fst_exp__h372032 ;
assign _theResult___fst_exp__h372558 =
(_theResult___fst_exp__h371961 == 8'd255) ?
_theResult___fst_exp__h371961 :
_theResult___fst_exp__h372555 ;
assign _theResult___fst_exp__h380598 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ;
assign _theResult___fst_exp__h380637 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 } ;
assign _theResult___fst_exp__h380643 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4873) ?
8'd0 :
_theResult___fst_exp__h380637 ;
assign _theResult___fst_exp__h380646 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h380643 :
_theResult___fst_exp__h380598 ;
assign _theResult___fst_exp__h381194 =
(_theResult___fst_exp__h380646 == 8'd255) ?
_theResult___fst_exp__h380646 :
_theResult___fst_exp__h381191 ;
assign _theResult___fst_exp__h381203 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
_theResult___snd_fst_exp__h363377 :
_theResult___fst_exp__h346066) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
_theResult___snd_fst_exp__h381197 :
_theResult___fst_exp__h346066) ;
assign _theResult___fst_exp__h381206 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h381203 ;
assign _theResult___fst_exp__h399892 =
_theResult____h391783[56] ?
8'd2 :
_theResult___fst_exp__h399966 ;
assign _theResult___fst_exp__h399957 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 } ;
assign _theResult___fst_exp__h399963 =
(!_theResult____h391783[56] && !_theResult____h391783[55] &&
!_theResult____h391783[54] &&
!_theResult____h391783[53] &&
!_theResult____h391783[52] &&
!_theResult____h391783[51] &&
!_theResult____h391783[50] &&
!_theResult____h391783[49] &&
!_theResult____h391783[48] &&
!_theResult____h391783[47] &&
!_theResult____h391783[46] &&
!_theResult____h391783[45] &&
!_theResult____h391783[44] &&
!_theResult____h391783[43] &&
!_theResult____h391783[42] &&
!_theResult____h391783[41] &&
!_theResult____h391783[40] &&
!_theResult____h391783[39] &&
!_theResult____h391783[38] &&
!_theResult____h391783[37] &&
!_theResult____h391783[36] &&
!_theResult____h391783[35] &&
!_theResult____h391783[34] &&
!_theResult____h391783[33] &&
!_theResult____h391783[32] &&
!_theResult____h391783[31] &&
!_theResult____h391783[30] &&
!_theResult____h391783[29] &&
!_theResult____h391783[28] &&
!_theResult____h391783[27] &&
!_theResult____h391783[26] &&
!_theResult____h391783[25] &&
!_theResult____h391783[24] &&
!_theResult____h391783[23] &&
!_theResult____h391783[22] &&
!_theResult____h391783[21] &&
!_theResult____h391783[20] &&
!_theResult____h391783[19] &&
!_theResult____h391783[18] &&
!_theResult____h391783[17] &&
!_theResult____h391783[16] &&
!_theResult____h391783[15] &&
!_theResult____h391783[14] &&
!_theResult____h391783[13] &&
!_theResult____h391783[12] &&
!_theResult____h391783[11] &&
!_theResult____h391783[10] &&
!_theResult____h391783[9] &&
!_theResult____h391783[8] &&
!_theResult____h391783[7] &&
!_theResult____h391783[6] &&
!_theResult____h391783[5] &&
!_theResult____h391783[4] &&
!_theResult____h391783[3] &&
!_theResult____h391783[2] &&
!_theResult____h391783[1] &&
!_theResult____h391783[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5641) ?
8'd0 :
_theResult___fst_exp__h399957 ;
assign _theResult___fst_exp__h399966 =
(!_theResult____h391783[56] && _theResult____h391783[55]) ?
8'd1 :
_theResult___fst_exp__h399963 ;
assign _theResult___fst_exp__h400489 =
(_theResult___fst_exp__h399892 == 8'd255) ?
_theResult___fst_exp__h399892 :
_theResult___fst_exp__h400486 ;
assign _theResult___fst_exp__h408539 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ;
assign _theResult___fst_exp__h408545 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5872) ?
8'd0 :
_theResult___fst_exp__h408539 ;
assign _theResult___fst_exp__h408548 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h408545 :
8'd129 ;
assign _theResult___fst_exp__h409071 =
(_theResult___fst_exp__h408548 == 8'd255) ?
_theResult___fst_exp__h408548 :
_theResult___fst_exp__h409068 ;
assign _theResult___fst_exp__h417658 =
_theResult____h409420[56] ?
8'd2 :
_theResult___fst_exp__h417732 ;
assign _theResult___fst_exp__h417723 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 } ;
assign _theResult___fst_exp__h417729 =
(!_theResult____h409420[56] && !_theResult____h409420[55] &&
!_theResult____h409420[54] &&
!_theResult____h409420[53] &&
!_theResult____h409420[52] &&
!_theResult____h409420[51] &&
!_theResult____h409420[50] &&
!_theResult____h409420[49] &&
!_theResult____h409420[48] &&
!_theResult____h409420[47] &&
!_theResult____h409420[46] &&
!_theResult____h409420[45] &&
!_theResult____h409420[44] &&
!_theResult____h409420[43] &&
!_theResult____h409420[42] &&
!_theResult____h409420[41] &&
!_theResult____h409420[40] &&
!_theResult____h409420[39] &&
!_theResult____h409420[38] &&
!_theResult____h409420[37] &&
!_theResult____h409420[36] &&
!_theResult____h409420[35] &&
!_theResult____h409420[34] &&
!_theResult____h409420[33] &&
!_theResult____h409420[32] &&
!_theResult____h409420[31] &&
!_theResult____h409420[30] &&
!_theResult____h409420[29] &&
!_theResult____h409420[28] &&
!_theResult____h409420[27] &&
!_theResult____h409420[26] &&
!_theResult____h409420[25] &&
!_theResult____h409420[24] &&
!_theResult____h409420[23] &&
!_theResult____h409420[22] &&
!_theResult____h409420[21] &&
!_theResult____h409420[20] &&
!_theResult____h409420[19] &&
!_theResult____h409420[18] &&
!_theResult____h409420[17] &&
!_theResult____h409420[16] &&
!_theResult____h409420[15] &&
!_theResult____h409420[14] &&
!_theResult____h409420[13] &&
!_theResult____h409420[12] &&
!_theResult____h409420[11] &&
!_theResult____h409420[10] &&
!_theResult____h409420[9] &&
!_theResult____h409420[8] &&
!_theResult____h409420[7] &&
!_theResult____h409420[6] &&
!_theResult____h409420[5] &&
!_theResult____h409420[4] &&
!_theResult____h409420[3] &&
!_theResult____h409420[2] &&
!_theResult____h409420[1] &&
!_theResult____h409420[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6192) ?
8'd0 :
_theResult___fst_exp__h417723 ;
assign _theResult___fst_exp__h417732 =
(!_theResult____h409420[56] && _theResult____h409420[55]) ?
8'd1 :
_theResult___fst_exp__h417729 ;
assign _theResult___fst_exp__h418255 =
(_theResult___fst_exp__h417658 == 8'd255) ?
_theResult___fst_exp__h417658 :
_theResult___fst_exp__h418252 ;
assign _theResult___fst_exp__h426295 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ;
assign _theResult___fst_exp__h426334 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 } ;
assign _theResult___fst_exp__h426340 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6265) ?
8'd0 :
_theResult___fst_exp__h426334 ;
assign _theResult___fst_exp__h426343 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h426340 :
_theResult___fst_exp__h426295 ;
assign _theResult___fst_exp__h426891 =
(_theResult___fst_exp__h426343 == 8'd255) ?
_theResult___fst_exp__h426343 :
_theResult___fst_exp__h426888 ;
assign _theResult___fst_exp__h426900 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
_theResult___snd_fst_exp__h409074 :
_theResult___fst_exp__h391765) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
_theResult___snd_fst_exp__h426894 :
_theResult___fst_exp__h391765) ;
assign _theResult___fst_exp__h426903 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h426900 ;
assign _theResult___fst_exp__h445587 =
_theResult____h437478[56] ?
8'd2 :
_theResult___fst_exp__h445661 ;
assign _theResult___fst_exp__h445652 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 } ;
assign _theResult___fst_exp__h445658 =
(!_theResult____h437478[56] && !_theResult____h437478[55] &&
!_theResult____h437478[54] &&
!_theResult____h437478[53] &&
!_theResult____h437478[52] &&
!_theResult____h437478[51] &&
!_theResult____h437478[50] &&
!_theResult____h437478[49] &&
!_theResult____h437478[48] &&
!_theResult____h437478[47] &&
!_theResult____h437478[46] &&
!_theResult____h437478[45] &&
!_theResult____h437478[44] &&
!_theResult____h437478[43] &&
!_theResult____h437478[42] &&
!_theResult____h437478[41] &&
!_theResult____h437478[40] &&
!_theResult____h437478[39] &&
!_theResult____h437478[38] &&
!_theResult____h437478[37] &&
!_theResult____h437478[36] &&
!_theResult____h437478[35] &&
!_theResult____h437478[34] &&
!_theResult____h437478[33] &&
!_theResult____h437478[32] &&
!_theResult____h437478[31] &&
!_theResult____h437478[30] &&
!_theResult____h437478[29] &&
!_theResult____h437478[28] &&
!_theResult____h437478[27] &&
!_theResult____h437478[26] &&
!_theResult____h437478[25] &&
!_theResult____h437478[24] &&
!_theResult____h437478[23] &&
!_theResult____h437478[22] &&
!_theResult____h437478[21] &&
!_theResult____h437478[20] &&
!_theResult____h437478[19] &&
!_theResult____h437478[18] &&
!_theResult____h437478[17] &&
!_theResult____h437478[16] &&
!_theResult____h437478[15] &&
!_theResult____h437478[14] &&
!_theResult____h437478[13] &&
!_theResult____h437478[12] &&
!_theResult____h437478[11] &&
!_theResult____h437478[10] &&
!_theResult____h437478[9] &&
!_theResult____h437478[8] &&
!_theResult____h437478[7] &&
!_theResult____h437478[6] &&
!_theResult____h437478[5] &&
!_theResult____h437478[4] &&
!_theResult____h437478[3] &&
!_theResult____h437478[2] &&
!_theResult____h437478[1] &&
!_theResult____h437478[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7033) ?
8'd0 :
_theResult___fst_exp__h445652 ;
assign _theResult___fst_exp__h445661 =
(!_theResult____h437478[56] && _theResult____h437478[55]) ?
8'd1 :
_theResult___fst_exp__h445658 ;
assign _theResult___fst_exp__h446184 =
(_theResult___fst_exp__h445587 == 8'd255) ?
_theResult___fst_exp__h445587 :
_theResult___fst_exp__h446181 ;
assign _theResult___fst_exp__h454234 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ;
assign _theResult___fst_exp__h454240 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7264) ?
8'd0 :
_theResult___fst_exp__h454234 ;
assign _theResult___fst_exp__h454243 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h454240 :
8'd129 ;
assign _theResult___fst_exp__h454766 =
(_theResult___fst_exp__h454243 == 8'd255) ?
_theResult___fst_exp__h454243 :
_theResult___fst_exp__h454763 ;
assign _theResult___fst_exp__h463353 =
_theResult____h455115[56] ?
8'd2 :
_theResult___fst_exp__h463427 ;
assign _theResult___fst_exp__h463418 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 } ;
assign _theResult___fst_exp__h463424 =
(!_theResult____h455115[56] && !_theResult____h455115[55] &&
!_theResult____h455115[54] &&
!_theResult____h455115[53] &&
!_theResult____h455115[52] &&
!_theResult____h455115[51] &&
!_theResult____h455115[50] &&
!_theResult____h455115[49] &&
!_theResult____h455115[48] &&
!_theResult____h455115[47] &&
!_theResult____h455115[46] &&
!_theResult____h455115[45] &&
!_theResult____h455115[44] &&
!_theResult____h455115[43] &&
!_theResult____h455115[42] &&
!_theResult____h455115[41] &&
!_theResult____h455115[40] &&
!_theResult____h455115[39] &&
!_theResult____h455115[38] &&
!_theResult____h455115[37] &&
!_theResult____h455115[36] &&
!_theResult____h455115[35] &&
!_theResult____h455115[34] &&
!_theResult____h455115[33] &&
!_theResult____h455115[32] &&
!_theResult____h455115[31] &&
!_theResult____h455115[30] &&
!_theResult____h455115[29] &&
!_theResult____h455115[28] &&
!_theResult____h455115[27] &&
!_theResult____h455115[26] &&
!_theResult____h455115[25] &&
!_theResult____h455115[24] &&
!_theResult____h455115[23] &&
!_theResult____h455115[22] &&
!_theResult____h455115[21] &&
!_theResult____h455115[20] &&
!_theResult____h455115[19] &&
!_theResult____h455115[18] &&
!_theResult____h455115[17] &&
!_theResult____h455115[16] &&
!_theResult____h455115[15] &&
!_theResult____h455115[14] &&
!_theResult____h455115[13] &&
!_theResult____h455115[12] &&
!_theResult____h455115[11] &&
!_theResult____h455115[10] &&
!_theResult____h455115[9] &&
!_theResult____h455115[8] &&
!_theResult____h455115[7] &&
!_theResult____h455115[6] &&
!_theResult____h455115[5] &&
!_theResult____h455115[4] &&
!_theResult____h455115[3] &&
!_theResult____h455115[2] &&
!_theResult____h455115[1] &&
!_theResult____h455115[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7584) ?
8'd0 :
_theResult___fst_exp__h463418 ;
assign _theResult___fst_exp__h463427 =
(!_theResult____h455115[56] && _theResult____h455115[55]) ?
8'd1 :
_theResult___fst_exp__h463424 ;
assign _theResult___fst_exp__h463950 =
(_theResult___fst_exp__h463353 == 8'd255) ?
_theResult___fst_exp__h463353 :
_theResult___fst_exp__h463947 ;
assign _theResult___fst_exp__h471990 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ;
assign _theResult___fst_exp__h472029 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 } ;
assign _theResult___fst_exp__h472035 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7657) ?
8'd0 :
_theResult___fst_exp__h472029 ;
assign _theResult___fst_exp__h472038 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h472035 :
_theResult___fst_exp__h471990 ;
assign _theResult___fst_exp__h472586 =
(_theResult___fst_exp__h472038 == 8'd255) ?
_theResult___fst_exp__h472038 :
_theResult___fst_exp__h472583 ;
assign _theResult___fst_exp__h472595 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
_theResult___snd_fst_exp__h454769 :
_theResult___fst_exp__h437460) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
_theResult___snd_fst_exp__h472589 :
_theResult___fst_exp__h437460) ;
assign _theResult___fst_exp__h472598 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h472595 ;
assign _theResult___fst_exp__h486454 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ;
assign _theResult___fst_exp__h501518 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ;
assign _theResult___fst_exp__h501524 =
(f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8585) ?
11'd0 :
_theResult___fst_exp__h501518 ;
assign _theResult___fst_exp__h501527 =
(f1_exp__h482139 == 8'd0) ?
_theResult___fst_exp__h501524 :
11'd897 ;
assign _theResult___fst_exp__h502282 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 ;
assign _theResult___fst_exp__h502285 =
(_theResult___fst_exp__h501527 == 11'd2047) ?
_theResult___fst_exp__h501527 :
_theResult___fst_exp__h502282 ;
assign _theResult___fst_exp__h511104 =
_theResult____h502868[56] ?
11'd2 :
_theResult___fst_exp__h511178 ;
assign _theResult___fst_exp__h511169 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 } ;
assign _theResult___fst_exp__h511175 =
(!_theResult____h502868[56] && !_theResult____h502868[55] &&
!_theResult____h502868[54] &&
!_theResult____h502868[53] &&
!_theResult____h502868[52] &&
!_theResult____h502868[51] &&
!_theResult____h502868[50] &&
!_theResult____h502868[49] &&
!_theResult____h502868[48] &&
!_theResult____h502868[47] &&
!_theResult____h502868[46] &&
!_theResult____h502868[45] &&
!_theResult____h502868[44] &&
!_theResult____h502868[43] &&
!_theResult____h502868[42] &&
!_theResult____h502868[41] &&
!_theResult____h502868[40] &&
!_theResult____h502868[39] &&
!_theResult____h502868[38] &&
!_theResult____h502868[37] &&
!_theResult____h502868[36] &&
!_theResult____h502868[35] &&
!_theResult____h502868[34] &&
!_theResult____h502868[33] &&
!_theResult____h502868[32] &&
!_theResult____h502868[31] &&
!_theResult____h502868[30] &&
!_theResult____h502868[29] &&
!_theResult____h502868[28] &&
!_theResult____h502868[27] &&
!_theResult____h502868[26] &&
!_theResult____h502868[25] &&
!_theResult____h502868[24] &&
!_theResult____h502868[23] &&
!_theResult____h502868[22] &&
!_theResult____h502868[21] &&
!_theResult____h502868[20] &&
!_theResult____h502868[19] &&
!_theResult____h502868[18] &&
!_theResult____h502868[17] &&
!_theResult____h502868[16] &&
!_theResult____h502868[15] &&
!_theResult____h502868[14] &&
!_theResult____h502868[13] &&
!_theResult____h502868[12] &&
!_theResult____h502868[11] &&
!_theResult____h502868[10] &&
!_theResult____h502868[9] &&
!_theResult____h502868[8] &&
!_theResult____h502868[7] &&
!_theResult____h502868[6] &&
!_theResult____h502868[5] &&
!_theResult____h502868[4] &&
!_theResult____h502868[3] &&
!_theResult____h502868[2] &&
!_theResult____h502868[1] &&
!_theResult____h502868[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8897) ?
11'd0 :
_theResult___fst_exp__h511169 ;
assign _theResult___fst_exp__h511178 =
(!_theResult____h502868[56] && _theResult____h502868[55]) ?
11'd1 :
_theResult___fst_exp__h511175 ;
assign _theResult___fst_exp__h511933 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 ;
assign _theResult___fst_exp__h511936 =
(_theResult___fst_exp__h511104 == 11'd2047) ?
_theResult___fst_exp__h511104 :
_theResult___fst_exp__h511933 ;
assign _theResult___fst_exp__h519889 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ;
assign _theResult___fst_exp__h519928 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 } ;
assign _theResult___fst_exp__h519934 =
(f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8947) ?
11'd0 :
_theResult___fst_exp__h519928 ;
assign _theResult___fst_exp__h519937 =
(f1_exp__h482139 == 8'd0) ?
_theResult___fst_exp__h519934 :
_theResult___fst_exp__h519889 ;
assign _theResult___fst_exp__h520717 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 ;
assign _theResult___fst_exp__h520720 =
(_theResult___fst_exp__h519937 == 11'd2047) ?
_theResult___fst_exp__h519937 :
_theResult___fst_exp__h520717 ;
assign _theResult___fst_exp__h520729 =
(f1_exp__h482139 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ?
_theResult___snd_fst_exp__h502288 :
_theResult___fst_exp__h486454) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ?
_theResult___snd_fst_exp__h520723 :
_theResult___fst_exp__h486454) ;
assign _theResult___fst_exp__h520732 =
(f1_exp__h482139 == 8'd0 && f1_sfd__h482140 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h520729 ;
assign _theResult___fst_exp__h525307 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 ;
assign _theResult___fst_exp__h540371 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ;
assign _theResult___fst_exp__h540377 =
(f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10085) ?
11'd0 :
_theResult___fst_exp__h540371 ;
assign _theResult___fst_exp__h540380 =
(f2_exp__h521133 == 8'd0) ?
_theResult___fst_exp__h540377 :
11'd897 ;
assign _theResult___fst_exp__h541135 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 ;
assign _theResult___fst_exp__h541138 =
(_theResult___fst_exp__h540380 == 11'd2047) ?
_theResult___fst_exp__h540380 :
_theResult___fst_exp__h541135 ;
assign _theResult___fst_exp__h549957 =
_theResult____h541721[56] ?
11'd2 :
_theResult___fst_exp__h550031 ;
assign _theResult___fst_exp__h550022 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 } ;
assign _theResult___fst_exp__h550028 =
(!_theResult____h541721[56] && !_theResult____h541721[55] &&
!_theResult____h541721[54] &&
!_theResult____h541721[53] &&
!_theResult____h541721[52] &&
!_theResult____h541721[51] &&
!_theResult____h541721[50] &&
!_theResult____h541721[49] &&
!_theResult____h541721[48] &&
!_theResult____h541721[47] &&
!_theResult____h541721[46] &&
!_theResult____h541721[45] &&
!_theResult____h541721[44] &&
!_theResult____h541721[43] &&
!_theResult____h541721[42] &&
!_theResult____h541721[41] &&
!_theResult____h541721[40] &&
!_theResult____h541721[39] &&
!_theResult____h541721[38] &&
!_theResult____h541721[37] &&
!_theResult____h541721[36] &&
!_theResult____h541721[35] &&
!_theResult____h541721[34] &&
!_theResult____h541721[33] &&
!_theResult____h541721[32] &&
!_theResult____h541721[31] &&
!_theResult____h541721[30] &&
!_theResult____h541721[29] &&
!_theResult____h541721[28] &&
!_theResult____h541721[27] &&
!_theResult____h541721[26] &&
!_theResult____h541721[25] &&
!_theResult____h541721[24] &&
!_theResult____h541721[23] &&
!_theResult____h541721[22] &&
!_theResult____h541721[21] &&
!_theResult____h541721[20] &&
!_theResult____h541721[19] &&
!_theResult____h541721[18] &&
!_theResult____h541721[17] &&
!_theResult____h541721[16] &&
!_theResult____h541721[15] &&
!_theResult____h541721[14] &&
!_theResult____h541721[13] &&
!_theResult____h541721[12] &&
!_theResult____h541721[11] &&
!_theResult____h541721[10] &&
!_theResult____h541721[9] &&
!_theResult____h541721[8] &&
!_theResult____h541721[7] &&
!_theResult____h541721[6] &&
!_theResult____h541721[5] &&
!_theResult____h541721[4] &&
!_theResult____h541721[3] &&
!_theResult____h541721[2] &&
!_theResult____h541721[1] &&
!_theResult____h541721[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10382) ?
11'd0 :
_theResult___fst_exp__h550022 ;
assign _theResult___fst_exp__h550031 =
(!_theResult____h541721[56] && _theResult____h541721[55]) ?
11'd1 :
_theResult___fst_exp__h550028 ;
assign _theResult___fst_exp__h550786 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 ;
assign _theResult___fst_exp__h550789 =
(_theResult___fst_exp__h549957 == 11'd2047) ?
_theResult___fst_exp__h549957 :
_theResult___fst_exp__h550786 ;
assign _theResult___fst_exp__h558742 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ;
assign _theResult___fst_exp__h558781 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 } ;
assign _theResult___fst_exp__h558787 =
(f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10432) ?
11'd0 :
_theResult___fst_exp__h558781 ;
assign _theResult___fst_exp__h558790 =
(f2_exp__h521133 == 8'd0) ?
_theResult___fst_exp__h558787 :
_theResult___fst_exp__h558742 ;
assign _theResult___fst_exp__h559570 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 ;
assign _theResult___fst_exp__h559573 =
(_theResult___fst_exp__h558790 == 11'd2047) ?
_theResult___fst_exp__h558790 :
_theResult___fst_exp__h559570 ;
assign _theResult___fst_exp__h559582 =
(f2_exp__h521133 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ?
_theResult___snd_fst_exp__h541141 :
_theResult___fst_exp__h525307) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
_theResult___snd_fst_exp__h559576 :
_theResult___fst_exp__h525307) ;
assign _theResult___fst_exp__h559585 =
(f2_exp__h521133 == 8'd0 && f2_sfd__h521134 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h559582 ;
assign _theResult___fst_exp__h564611 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ;
assign _theResult___fst_exp__h579675 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ;
assign _theResult___fst_exp__h579681 =
(f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9315) ?
11'd0 :
_theResult___fst_exp__h579675 ;
assign _theResult___fst_exp__h579684 =
(f3_exp__h560437 == 8'd0) ?
_theResult___fst_exp__h579681 :
11'd897 ;
assign _theResult___fst_exp__h580439 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 ;
assign _theResult___fst_exp__h580442 =
(_theResult___fst_exp__h579684 == 11'd2047) ?
_theResult___fst_exp__h579684 :
_theResult___fst_exp__h580439 ;
assign _theResult___fst_exp__h589261 =
_theResult____h581025[56] ?
11'd2 :
_theResult___fst_exp__h589335 ;
assign _theResult___fst_exp__h589326 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 } ;
assign _theResult___fst_exp__h589332 =
(!_theResult____h581025[56] && !_theResult____h581025[55] &&
!_theResult____h581025[54] &&
!_theResult____h581025[53] &&
!_theResult____h581025[52] &&
!_theResult____h581025[51] &&
!_theResult____h581025[50] &&
!_theResult____h581025[49] &&
!_theResult____h581025[48] &&
!_theResult____h581025[47] &&
!_theResult____h581025[46] &&
!_theResult____h581025[45] &&
!_theResult____h581025[44] &&
!_theResult____h581025[43] &&
!_theResult____h581025[42] &&
!_theResult____h581025[41] &&
!_theResult____h581025[40] &&
!_theResult____h581025[39] &&
!_theResult____h581025[38] &&
!_theResult____h581025[37] &&
!_theResult____h581025[36] &&
!_theResult____h581025[35] &&
!_theResult____h581025[34] &&
!_theResult____h581025[33] &&
!_theResult____h581025[32] &&
!_theResult____h581025[31] &&
!_theResult____h581025[30] &&
!_theResult____h581025[29] &&
!_theResult____h581025[28] &&
!_theResult____h581025[27] &&
!_theResult____h581025[26] &&
!_theResult____h581025[25] &&
!_theResult____h581025[24] &&
!_theResult____h581025[23] &&
!_theResult____h581025[22] &&
!_theResult____h581025[21] &&
!_theResult____h581025[20] &&
!_theResult____h581025[19] &&
!_theResult____h581025[18] &&
!_theResult____h581025[17] &&
!_theResult____h581025[16] &&
!_theResult____h581025[15] &&
!_theResult____h581025[14] &&
!_theResult____h581025[13] &&
!_theResult____h581025[12] &&
!_theResult____h581025[11] &&
!_theResult____h581025[10] &&
!_theResult____h581025[9] &&
!_theResult____h581025[8] &&
!_theResult____h581025[7] &&
!_theResult____h581025[6] &&
!_theResult____h581025[5] &&
!_theResult____h581025[4] &&
!_theResult____h581025[3] &&
!_theResult____h581025[2] &&
!_theResult____h581025[1] &&
!_theResult____h581025[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9612) ?
11'd0 :
_theResult___fst_exp__h589326 ;
assign _theResult___fst_exp__h589335 =
(!_theResult____h581025[56] && _theResult____h581025[55]) ?
11'd1 :
_theResult___fst_exp__h589332 ;
assign _theResult___fst_exp__h590090 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 ;
assign _theResult___fst_exp__h590093 =
(_theResult___fst_exp__h589261 == 11'd2047) ?
_theResult___fst_exp__h589261 :
_theResult___fst_exp__h590090 ;
assign _theResult___fst_exp__h598046 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ;
assign _theResult___fst_exp__h598085 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 } ;
assign _theResult___fst_exp__h598091 =
(f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9662) ?
11'd0 :
_theResult___fst_exp__h598085 ;
assign _theResult___fst_exp__h598094 =
(f3_exp__h560437 == 8'd0) ?
_theResult___fst_exp__h598091 :
_theResult___fst_exp__h598046 ;
assign _theResult___fst_exp__h598874 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 ;
assign _theResult___fst_exp__h598877 =
(_theResult___fst_exp__h598094 == 11'd2047) ?
_theResult___fst_exp__h598094 :
_theResult___fst_exp__h598874 ;
assign _theResult___fst_exp__h598886 =
(f3_exp__h560437 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ?
_theResult___snd_fst_exp__h580445 :
_theResult___fst_exp__h564611) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
_theResult___snd_fst_exp__h598880 :
_theResult___fst_exp__h564611) ;
assign _theResult___fst_exp__h598889 =
(f3_exp__h560437 == 8'd0 && f3_sfd__h560438 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h598886 ;
assign _theResult___fst_sfd__h354793 =
(_theResult___fst_exp__h354195 == 8'd255) ?
sfdin__h354189[56:34] :
_theResult___fst_sfd__h354790 ;
assign _theResult___fst_sfd__h363375 =
(_theResult___fst_exp__h362851 == 8'd255) ?
_theResult___snd__h362802[56:34] :
_theResult___fst_sfd__h363372 ;
assign _theResult___fst_sfd__h372559 =
(_theResult___fst_exp__h371961 == 8'd255) ?
sfdin__h371955[56:34] :
_theResult___fst_sfd__h372556 ;
assign _theResult___fst_sfd__h381195 =
(_theResult___fst_exp__h380646 == 8'd255) ?
_theResult___snd__h380592[56:34] :
_theResult___fst_sfd__h381192 ;
assign _theResult___fst_sfd__h381204 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4012 ?
_theResult___snd_fst_sfd__h363378 :
_theResult___fst_sfd__h346067) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4552 ?
_theResult___snd_fst_sfd__h381198 :
_theResult___fst_sfd__h346067) ;
assign _theResult___fst_sfd__h381210 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h381204 ;
assign _theResult___fst_sfd__h400490 =
(_theResult___fst_exp__h399892 == 8'd255) ?
sfdin__h399886[56:34] :
_theResult___fst_sfd__h400487 ;
assign _theResult___fst_sfd__h409072 =
(_theResult___fst_exp__h408548 == 8'd255) ?
_theResult___snd__h408499[56:34] :
_theResult___fst_sfd__h409069 ;
assign _theResult___fst_sfd__h418256 =
(_theResult___fst_exp__h417658 == 8'd255) ?
sfdin__h417652[56:34] :
_theResult___fst_sfd__h418253 ;
assign _theResult___fst_sfd__h426892 =
(_theResult___fst_exp__h426343 == 8'd255) ?
_theResult___snd__h426289[56:34] :
_theResult___fst_sfd__h426889 ;
assign _theResult___fst_sfd__h426901 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5404 ?
_theResult___snd_fst_sfd__h409075 :
_theResult___fst_sfd__h391766) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5944 ?
_theResult___snd_fst_sfd__h426895 :
_theResult___fst_sfd__h391766) ;
assign _theResult___fst_sfd__h426907 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h426901 ;
assign _theResult___fst_sfd__h446185 =
(_theResult___fst_exp__h445587 == 8'd255) ?
sfdin__h445581[56:34] :
_theResult___fst_sfd__h446182 ;
assign _theResult___fst_sfd__h454767 =
(_theResult___fst_exp__h454243 == 8'd255) ?
_theResult___snd__h454194[56:34] :
_theResult___fst_sfd__h454764 ;
assign _theResult___fst_sfd__h463951 =
(_theResult___fst_exp__h463353 == 8'd255) ?
sfdin__h463347[56:34] :
_theResult___fst_sfd__h463948 ;
assign _theResult___fst_sfd__h472587 =
(_theResult___fst_exp__h472038 == 8'd255) ?
_theResult___snd__h471984[56:34] :
_theResult___fst_sfd__h472584 ;
assign _theResult___fst_sfd__h472596 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6796 ?
_theResult___snd_fst_sfd__h454770 :
_theResult___fst_sfd__h437461) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7336 ?
_theResult___snd_fst_sfd__h472590 :
_theResult___fst_sfd__h437461) ;
assign _theResult___fst_sfd__h472602 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h472596 ;
assign _theResult___fst_sfd__h486455 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ;
assign _theResult___fst_sfd__h502283 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 ;
assign _theResult___fst_sfd__h502286 =
(_theResult___fst_exp__h501527 == 11'd2047) ?
_theResult___snd__h501478[56:5] :
_theResult___fst_sfd__h502283 ;
assign _theResult___fst_sfd__h511934 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 ;
assign _theResult___fst_sfd__h511937 =
(_theResult___fst_exp__h511104 == 11'd2047) ?
sfdin__h511098[56:5] :
_theResult___fst_sfd__h511934 ;
assign _theResult___fst_sfd__h520718 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 ;
assign _theResult___fst_sfd__h520721 =
(_theResult___fst_exp__h519937 == 11'd2047) ?
_theResult___snd__h519883[56:5] :
_theResult___fst_sfd__h520718 ;
assign _theResult___fst_sfd__h520730 =
(f1_exp__h482139 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8510 ?
_theResult___snd_fst_sfd__h502289 :
_theResult___fst_sfd__h486455) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8647 ?
_theResult___snd_fst_sfd__h520724 :
_theResult___fst_sfd__h486455) ;
assign _theResult___fst_sfd__h520736 =
((f1_exp__h482139 == 8'd255 || f1_exp__h482139 == 8'd0) &&
f1_sfd__h482140 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h520730 ;
assign _theResult___fst_sfd__h525308 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ;
assign _theResult___fst_sfd__h541136 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 ;
assign _theResult___fst_sfd__h541139 =
(_theResult___fst_exp__h540380 == 11'd2047) ?
_theResult___snd__h540331[56:5] :
_theResult___fst_sfd__h541136 ;
assign _theResult___fst_sfd__h550787 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 ;
assign _theResult___fst_sfd__h550790 =
(_theResult___fst_exp__h549957 == 11'd2047) ?
sfdin__h549951[56:5] :
_theResult___fst_sfd__h550787 ;
assign _theResult___fst_sfd__h559571 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 ;
assign _theResult___fst_sfd__h559574 =
(_theResult___fst_exp__h558790 == 11'd2047) ?
_theResult___snd__h558736[56:5] :
_theResult___fst_sfd__h559571 ;
assign _theResult___fst_sfd__h559583 =
(f2_exp__h521133 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10010 ?
_theResult___snd_fst_sfd__h541142 :
_theResult___fst_sfd__h525308) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10132 ?
_theResult___snd_fst_sfd__h559577 :
_theResult___fst_sfd__h525308) ;
assign _theResult___fst_sfd__h559589 =
((f2_exp__h521133 == 8'd255 || f2_exp__h521133 == 8'd0) &&
f2_sfd__h521134 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h559583 ;
assign _theResult___fst_sfd__h564612 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ;
assign _theResult___fst_sfd__h580440 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 ;
assign _theResult___fst_sfd__h580443 =
(_theResult___fst_exp__h579684 == 11'd2047) ?
_theResult___snd__h579635[56:5] :
_theResult___fst_sfd__h580440 ;
assign _theResult___fst_sfd__h590091 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 ;
assign _theResult___fst_sfd__h590094 =
(_theResult___fst_exp__h589261 == 11'd2047) ?
sfdin__h589255[56:5] :
_theResult___fst_sfd__h590091 ;
assign _theResult___fst_sfd__h598875 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 ;
assign _theResult___fst_sfd__h598878 =
(_theResult___fst_exp__h598094 == 11'd2047) ?
_theResult___snd__h598040[56:5] :
_theResult___fst_sfd__h598875 ;
assign _theResult___fst_sfd__h598887 =
(f3_exp__h560437 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9240 ?
_theResult___snd_fst_sfd__h580446 :
_theResult___fst_sfd__h564612) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9362 ?
_theResult___snd_fst_sfd__h598881 :
_theResult___fst_sfd__h564612) ;
assign _theResult___fst_sfd__h598893 =
((f3_exp__h560437 == 8'd255 || f3_exp__h560437 == 8'd0) &&
f3_sfd__h560438 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h598887 ;
assign _theResult___sfd__h354712 =
sfd__h354287[24] ?
((_theResult___fst_exp__h354195 == 8'd254) ?
23'd0 :
sfd__h354287[23:1]) :
sfd__h354287[22:0] ;
assign _theResult___sfd__h363294 =
sfd__h362869[24] ?
((_theResult___fst_exp__h362851 == 8'd254) ?
23'd0 :
sfd__h362869[23:1]) :
sfd__h362869[22:0] ;
assign _theResult___sfd__h372478 =
sfd__h372053[24] ?
((_theResult___fst_exp__h371961 == 8'd254) ?
23'd0 :
sfd__h372053[23:1]) :
sfd__h372053[22:0] ;
assign _theResult___sfd__h381114 =
sfd__h380665[24] ?
((_theResult___fst_exp__h380646 == 8'd254) ?
23'd0 :
sfd__h380665[23:1]) :
sfd__h380665[22:0] ;
assign _theResult___sfd__h381216 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h338429 :
_theResult___fst_sfd__h381210 ;
assign _theResult___sfd__h400409 =
sfd__h399984[24] ?
((_theResult___fst_exp__h399892 == 8'd254) ?
23'd0 :
sfd__h399984[23:1]) :
sfd__h399984[22:0] ;
assign _theResult___sfd__h408991 =
sfd__h408566[24] ?
((_theResult___fst_exp__h408548 == 8'd254) ?
23'd0 :
sfd__h408566[23:1]) :
sfd__h408566[22:0] ;
assign _theResult___sfd__h418175 =
sfd__h417750[24] ?
((_theResult___fst_exp__h417658 == 8'd254) ?
23'd0 :
sfd__h417750[23:1]) :
sfd__h417750[22:0] ;
assign _theResult___sfd__h426811 =
sfd__h426362[24] ?
((_theResult___fst_exp__h426343 == 8'd254) ?
23'd0 :
sfd__h426362[23:1]) :
sfd__h426362[22:0] ;
assign _theResult___sfd__h426913 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h384131 :
_theResult___fst_sfd__h426907 ;
assign _theResult___sfd__h446104 =
sfd__h445679[24] ?
((_theResult___fst_exp__h445587 == 8'd254) ?
23'd0 :
sfd__h445679[23:1]) :
sfd__h445679[22:0] ;
assign _theResult___sfd__h454686 =
sfd__h454261[24] ?
((_theResult___fst_exp__h454243 == 8'd254) ?
23'd0 :
sfd__h454261[23:1]) :
sfd__h454261[22:0] ;
assign _theResult___sfd__h463870 =
sfd__h463445[24] ?
((_theResult___fst_exp__h463353 == 8'd254) ?
23'd0 :
sfd__h463445[23:1]) :
sfd__h463445[22:0] ;
assign _theResult___sfd__h472506 =
sfd__h472057[24] ?
((_theResult___fst_exp__h472038 == 8'd254) ?
23'd0 :
sfd__h472057[23:1]) :
sfd__h472057[22:0] ;
assign _theResult___sfd__h472608 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h429826 :
_theResult___fst_sfd__h472602 ;
assign _theResult___sfd__h502183 =
sfd__h501545[53] ?
((_theResult___fst_exp__h501527 == 11'd2046) ?
52'd0 :
sfd__h501545[52:1]) :
sfd__h501545[51:0] ;
assign _theResult___sfd__h511834 =
sfd__h511196[53] ?
((_theResult___fst_exp__h511104 == 11'd2046) ?
52'd0 :
sfd__h511196[52:1]) :
sfd__h511196[51:0] ;
assign _theResult___sfd__h520618 =
sfd__h519956[53] ?
((_theResult___fst_exp__h519937 == 11'd2046) ?
52'd0 :
sfd__h519956[52:1]) :
sfd__h519956[51:0] ;
assign _theResult___sfd__h541036 =
sfd__h540398[53] ?
((_theResult___fst_exp__h540380 == 11'd2046) ?
52'd0 :
sfd__h540398[52:1]) :
sfd__h540398[51:0] ;
assign _theResult___sfd__h550687 =
sfd__h550049[53] ?
((_theResult___fst_exp__h549957 == 11'd2046) ?
52'd0 :
sfd__h550049[52:1]) :
sfd__h550049[51:0] ;
assign _theResult___sfd__h559471 =
sfd__h558809[53] ?
((_theResult___fst_exp__h558790 == 11'd2046) ?
52'd0 :
sfd__h558809[52:1]) :
sfd__h558809[51:0] ;
assign _theResult___sfd__h580340 =
sfd__h579702[53] ?
((_theResult___fst_exp__h579684 == 11'd2046) ?
52'd0 :
sfd__h579702[52:1]) :
sfd__h579702[51:0] ;
assign _theResult___sfd__h589991 =
sfd__h589353[53] ?
((_theResult___fst_exp__h589261 == 11'd2046) ?
52'd0 :
sfd__h589353[52:1]) :
sfd__h589353[51:0] ;
assign _theResult___sfd__h598775 =
sfd__h598113[53] ?
((_theResult___fst_exp__h598094 == 11'd2046) ?
52'd0 :
sfd__h598113[52:1]) :
sfd__h598113[51:0] ;
assign _theResult___snd__h354206 = { _theResult____h346084[55:0], 1'd0 } ;
assign _theResult___snd__h354217 =
(!_theResult____h346084[56] && _theResult____h346084[55]) ?
_theResult___snd__h354219 :
_theResult___snd__h354229 ;
assign _theResult___snd__h354219 = { _theResult____h346084[54:0], 2'd0 } ;
assign _theResult___snd__h354229 =
(!_theResult____h346084[56] && !_theResult____h346084[55] &&
!_theResult____h346084[54] &&
!_theResult____h346084[53] &&
!_theResult____h346084[52] &&
!_theResult____h346084[51] &&
!_theResult____h346084[50] &&
!_theResult____h346084[49] &&
!_theResult____h346084[48] &&
!_theResult____h346084[47] &&
!_theResult____h346084[46] &&
!_theResult____h346084[45] &&
!_theResult____h346084[44] &&
!_theResult____h346084[43] &&
!_theResult____h346084[42] &&
!_theResult____h346084[41] &&
!_theResult____h346084[40] &&
!_theResult____h346084[39] &&
!_theResult____h346084[38] &&
!_theResult____h346084[37] &&
!_theResult____h346084[36] &&
!_theResult____h346084[35] &&
!_theResult____h346084[34] &&
!_theResult____h346084[33] &&
!_theResult____h346084[32] &&
!_theResult____h346084[31] &&
!_theResult____h346084[30] &&
!_theResult____h346084[29] &&
!_theResult____h346084[28] &&
!_theResult____h346084[27] &&
!_theResult____h346084[26] &&
!_theResult____h346084[25] &&
!_theResult____h346084[24] &&
!_theResult____h346084[23] &&
!_theResult____h346084[22] &&
!_theResult____h346084[21] &&
!_theResult____h346084[20] &&
!_theResult____h346084[19] &&
!_theResult____h346084[18] &&
!_theResult____h346084[17] &&
!_theResult____h346084[16] &&
!_theResult____h346084[15] &&
!_theResult____h346084[14] &&
!_theResult____h346084[13] &&
!_theResult____h346084[12] &&
!_theResult____h346084[11] &&
!_theResult____h346084[10] &&
!_theResult____h346084[9] &&
!_theResult____h346084[8] &&
!_theResult____h346084[7] &&
!_theResult____h346084[6] &&
!_theResult____h346084[5] &&
!_theResult____h346084[4] &&
!_theResult____h346084[3] &&
!_theResult____h346084[2] &&
!_theResult____h346084[1] &&
!_theResult____h346084[0]) ?
_theResult____h346084 :
_theResult___snd__h354235 ;
assign _theResult___snd__h354235 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0],
2'd0 } ;
assign _theResult___snd__h354258 =
_theResult____h346084 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4247 ;
assign _theResult___snd__h362802 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h362811 :
_theResult___snd__h362804 ;
assign _theResult___snd__h362804 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h362811 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ?
sfd__h338479 :
_theResult___snd__h362817 ;
assign _theResult___snd__h362817 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0],
2'd0 } ;
assign _theResult___snd__h362840 =
sfd__h338479 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4478 ;
assign _theResult___snd__h371972 = { _theResult____h363723[55:0], 1'd0 } ;
assign _theResult___snd__h371983 =
(!_theResult____h363723[56] && _theResult____h363723[55]) ?
_theResult___snd__h371985 :
_theResult___snd__h371995 ;
assign _theResult___snd__h371985 = { _theResult____h363723[54:0], 2'd0 } ;
assign _theResult___snd__h371995 =
(!_theResult____h363723[56] && !_theResult____h363723[55] &&
!_theResult____h363723[54] &&
!_theResult____h363723[53] &&
!_theResult____h363723[52] &&
!_theResult____h363723[51] &&
!_theResult____h363723[50] &&
!_theResult____h363723[49] &&
!_theResult____h363723[48] &&
!_theResult____h363723[47] &&
!_theResult____h363723[46] &&
!_theResult____h363723[45] &&
!_theResult____h363723[44] &&
!_theResult____h363723[43] &&
!_theResult____h363723[42] &&
!_theResult____h363723[41] &&
!_theResult____h363723[40] &&
!_theResult____h363723[39] &&
!_theResult____h363723[38] &&
!_theResult____h363723[37] &&
!_theResult____h363723[36] &&
!_theResult____h363723[35] &&
!_theResult____h363723[34] &&
!_theResult____h363723[33] &&
!_theResult____h363723[32] &&
!_theResult____h363723[31] &&
!_theResult____h363723[30] &&
!_theResult____h363723[29] &&
!_theResult____h363723[28] &&
!_theResult____h363723[27] &&
!_theResult____h363723[26] &&
!_theResult____h363723[25] &&
!_theResult____h363723[24] &&
!_theResult____h363723[23] &&
!_theResult____h363723[22] &&
!_theResult____h363723[21] &&
!_theResult____h363723[20] &&
!_theResult____h363723[19] &&
!_theResult____h363723[18] &&
!_theResult____h363723[17] &&
!_theResult____h363723[16] &&
!_theResult____h363723[15] &&
!_theResult____h363723[14] &&
!_theResult____h363723[13] &&
!_theResult____h363723[12] &&
!_theResult____h363723[11] &&
!_theResult____h363723[10] &&
!_theResult____h363723[9] &&
!_theResult____h363723[8] &&
!_theResult____h363723[7] &&
!_theResult____h363723[6] &&
!_theResult____h363723[5] &&
!_theResult____h363723[4] &&
!_theResult____h363723[3] &&
!_theResult____h363723[2] &&
!_theResult____h363723[1] &&
!_theResult____h363723[0]) ?
_theResult____h363723 :
_theResult___snd__h372001 ;
assign _theResult___snd__h372001 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0],
2'd0 } ;
assign _theResult___snd__h372024 =
_theResult____h363723 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4798 ;
assign _theResult___snd__h380592 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h380606 :
_theResult___snd__h362804 ;
assign _theResult___snd__h380606 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4423) ?
sfd__h338479 :
_theResult___snd__h380612 ;
assign _theResult___snd__h380612 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0],
2'd0 } ;
assign _theResult___snd__h380630 =
sfd__h338479 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4872) ;
assign _theResult___snd__h399903 = { _theResult____h391783[55:0], 1'd0 } ;
assign _theResult___snd__h399914 =
(!_theResult____h391783[56] && _theResult____h391783[55]) ?
_theResult___snd__h399916 :
_theResult___snd__h399926 ;
assign _theResult___snd__h399916 = { _theResult____h391783[54:0], 2'd0 } ;
assign _theResult___snd__h399926 =
(!_theResult____h391783[56] && !_theResult____h391783[55] &&
!_theResult____h391783[54] &&
!_theResult____h391783[53] &&
!_theResult____h391783[52] &&
!_theResult____h391783[51] &&
!_theResult____h391783[50] &&
!_theResult____h391783[49] &&
!_theResult____h391783[48] &&
!_theResult____h391783[47] &&
!_theResult____h391783[46] &&
!_theResult____h391783[45] &&
!_theResult____h391783[44] &&
!_theResult____h391783[43] &&
!_theResult____h391783[42] &&
!_theResult____h391783[41] &&
!_theResult____h391783[40] &&
!_theResult____h391783[39] &&
!_theResult____h391783[38] &&
!_theResult____h391783[37] &&
!_theResult____h391783[36] &&
!_theResult____h391783[35] &&
!_theResult____h391783[34] &&
!_theResult____h391783[33] &&
!_theResult____h391783[32] &&
!_theResult____h391783[31] &&
!_theResult____h391783[30] &&
!_theResult____h391783[29] &&
!_theResult____h391783[28] &&
!_theResult____h391783[27] &&
!_theResult____h391783[26] &&
!_theResult____h391783[25] &&
!_theResult____h391783[24] &&
!_theResult____h391783[23] &&
!_theResult____h391783[22] &&
!_theResult____h391783[21] &&
!_theResult____h391783[20] &&
!_theResult____h391783[19] &&
!_theResult____h391783[18] &&
!_theResult____h391783[17] &&
!_theResult____h391783[16] &&
!_theResult____h391783[15] &&
!_theResult____h391783[14] &&
!_theResult____h391783[13] &&
!_theResult____h391783[12] &&
!_theResult____h391783[11] &&
!_theResult____h391783[10] &&
!_theResult____h391783[9] &&
!_theResult____h391783[8] &&
!_theResult____h391783[7] &&
!_theResult____h391783[6] &&
!_theResult____h391783[5] &&
!_theResult____h391783[4] &&
!_theResult____h391783[3] &&
!_theResult____h391783[2] &&
!_theResult____h391783[1] &&
!_theResult____h391783[0]) ?
_theResult____h391783 :
_theResult___snd__h399932 ;
assign _theResult___snd__h399932 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0],
2'd0 } ;
assign _theResult___snd__h399955 =
_theResult____h391783 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5639 ;
assign _theResult___snd__h408499 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h408508 :
_theResult___snd__h408501 ;
assign _theResult___snd__h408501 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h408508 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ?
sfd__h384181 :
_theResult___snd__h408514 ;
assign _theResult___snd__h408514 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0],
2'd0 } ;
assign _theResult___snd__h408537 =
sfd__h384181 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5870 ;
assign _theResult___snd__h417669 = { _theResult____h409420[55:0], 1'd0 } ;
assign _theResult___snd__h417680 =
(!_theResult____h409420[56] && _theResult____h409420[55]) ?
_theResult___snd__h417682 :
_theResult___snd__h417692 ;
assign _theResult___snd__h417682 = { _theResult____h409420[54:0], 2'd0 } ;
assign _theResult___snd__h417692 =
(!_theResult____h409420[56] && !_theResult____h409420[55] &&
!_theResult____h409420[54] &&
!_theResult____h409420[53] &&
!_theResult____h409420[52] &&
!_theResult____h409420[51] &&
!_theResult____h409420[50] &&
!_theResult____h409420[49] &&
!_theResult____h409420[48] &&
!_theResult____h409420[47] &&
!_theResult____h409420[46] &&
!_theResult____h409420[45] &&
!_theResult____h409420[44] &&
!_theResult____h409420[43] &&
!_theResult____h409420[42] &&
!_theResult____h409420[41] &&
!_theResult____h409420[40] &&
!_theResult____h409420[39] &&
!_theResult____h409420[38] &&
!_theResult____h409420[37] &&
!_theResult____h409420[36] &&
!_theResult____h409420[35] &&
!_theResult____h409420[34] &&
!_theResult____h409420[33] &&
!_theResult____h409420[32] &&
!_theResult____h409420[31] &&
!_theResult____h409420[30] &&
!_theResult____h409420[29] &&
!_theResult____h409420[28] &&
!_theResult____h409420[27] &&
!_theResult____h409420[26] &&
!_theResult____h409420[25] &&
!_theResult____h409420[24] &&
!_theResult____h409420[23] &&
!_theResult____h409420[22] &&
!_theResult____h409420[21] &&
!_theResult____h409420[20] &&
!_theResult____h409420[19] &&
!_theResult____h409420[18] &&
!_theResult____h409420[17] &&
!_theResult____h409420[16] &&
!_theResult____h409420[15] &&
!_theResult____h409420[14] &&
!_theResult____h409420[13] &&
!_theResult____h409420[12] &&
!_theResult____h409420[11] &&
!_theResult____h409420[10] &&
!_theResult____h409420[9] &&
!_theResult____h409420[8] &&
!_theResult____h409420[7] &&
!_theResult____h409420[6] &&
!_theResult____h409420[5] &&
!_theResult____h409420[4] &&
!_theResult____h409420[3] &&
!_theResult____h409420[2] &&
!_theResult____h409420[1] &&
!_theResult____h409420[0]) ?
_theResult____h409420 :
_theResult___snd__h417698 ;
assign _theResult___snd__h417698 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0],
2'd0 } ;
assign _theResult___snd__h417721 =
_theResult____h409420 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6190 ;
assign _theResult___snd__h426289 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h426303 :
_theResult___snd__h408501 ;
assign _theResult___snd__h426303 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5815) ?
sfd__h384181 :
_theResult___snd__h426309 ;
assign _theResult___snd__h426309 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0],
2'd0 } ;
assign _theResult___snd__h426327 =
sfd__h384181 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6264) ;
assign _theResult___snd__h445598 = { _theResult____h437478[55:0], 1'd0 } ;
assign _theResult___snd__h445609 =
(!_theResult____h437478[56] && _theResult____h437478[55]) ?
_theResult___snd__h445611 :
_theResult___snd__h445621 ;
assign _theResult___snd__h445611 = { _theResult____h437478[54:0], 2'd0 } ;
assign _theResult___snd__h445621 =
(!_theResult____h437478[56] && !_theResult____h437478[55] &&
!_theResult____h437478[54] &&
!_theResult____h437478[53] &&
!_theResult____h437478[52] &&
!_theResult____h437478[51] &&
!_theResult____h437478[50] &&
!_theResult____h437478[49] &&
!_theResult____h437478[48] &&
!_theResult____h437478[47] &&
!_theResult____h437478[46] &&
!_theResult____h437478[45] &&
!_theResult____h437478[44] &&
!_theResult____h437478[43] &&
!_theResult____h437478[42] &&
!_theResult____h437478[41] &&
!_theResult____h437478[40] &&
!_theResult____h437478[39] &&
!_theResult____h437478[38] &&
!_theResult____h437478[37] &&
!_theResult____h437478[36] &&
!_theResult____h437478[35] &&
!_theResult____h437478[34] &&
!_theResult____h437478[33] &&
!_theResult____h437478[32] &&
!_theResult____h437478[31] &&
!_theResult____h437478[30] &&
!_theResult____h437478[29] &&
!_theResult____h437478[28] &&
!_theResult____h437478[27] &&
!_theResult____h437478[26] &&
!_theResult____h437478[25] &&
!_theResult____h437478[24] &&
!_theResult____h437478[23] &&
!_theResult____h437478[22] &&
!_theResult____h437478[21] &&
!_theResult____h437478[20] &&
!_theResult____h437478[19] &&
!_theResult____h437478[18] &&
!_theResult____h437478[17] &&
!_theResult____h437478[16] &&
!_theResult____h437478[15] &&
!_theResult____h437478[14] &&
!_theResult____h437478[13] &&
!_theResult____h437478[12] &&
!_theResult____h437478[11] &&
!_theResult____h437478[10] &&
!_theResult____h437478[9] &&
!_theResult____h437478[8] &&
!_theResult____h437478[7] &&
!_theResult____h437478[6] &&
!_theResult____h437478[5] &&
!_theResult____h437478[4] &&
!_theResult____h437478[3] &&
!_theResult____h437478[2] &&
!_theResult____h437478[1] &&
!_theResult____h437478[0]) ?
_theResult____h437478 :
_theResult___snd__h445627 ;
assign _theResult___snd__h445627 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0],
2'd0 } ;
assign _theResult___snd__h445650 =
_theResult____h437478 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7031 ;
assign _theResult___snd__h454194 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h454203 :
_theResult___snd__h454196 ;
assign _theResult___snd__h454196 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h454203 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ?
sfd__h429876 :
_theResult___snd__h454209 ;
assign _theResult___snd__h454209 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0],
2'd0 } ;
assign _theResult___snd__h454232 =
sfd__h429876 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7262 ;
assign _theResult___snd__h463364 = { _theResult____h455115[55:0], 1'd0 } ;
assign _theResult___snd__h463375 =
(!_theResult____h455115[56] && _theResult____h455115[55]) ?
_theResult___snd__h463377 :
_theResult___snd__h463387 ;
assign _theResult___snd__h463377 = { _theResult____h455115[54:0], 2'd0 } ;
assign _theResult___snd__h463387 =
(!_theResult____h455115[56] && !_theResult____h455115[55] &&
!_theResult____h455115[54] &&
!_theResult____h455115[53] &&
!_theResult____h455115[52] &&
!_theResult____h455115[51] &&
!_theResult____h455115[50] &&
!_theResult____h455115[49] &&
!_theResult____h455115[48] &&
!_theResult____h455115[47] &&
!_theResult____h455115[46] &&
!_theResult____h455115[45] &&
!_theResult____h455115[44] &&
!_theResult____h455115[43] &&
!_theResult____h455115[42] &&
!_theResult____h455115[41] &&
!_theResult____h455115[40] &&
!_theResult____h455115[39] &&
!_theResult____h455115[38] &&
!_theResult____h455115[37] &&
!_theResult____h455115[36] &&
!_theResult____h455115[35] &&
!_theResult____h455115[34] &&
!_theResult____h455115[33] &&
!_theResult____h455115[32] &&
!_theResult____h455115[31] &&
!_theResult____h455115[30] &&
!_theResult____h455115[29] &&
!_theResult____h455115[28] &&
!_theResult____h455115[27] &&
!_theResult____h455115[26] &&
!_theResult____h455115[25] &&
!_theResult____h455115[24] &&
!_theResult____h455115[23] &&
!_theResult____h455115[22] &&
!_theResult____h455115[21] &&
!_theResult____h455115[20] &&
!_theResult____h455115[19] &&
!_theResult____h455115[18] &&
!_theResult____h455115[17] &&
!_theResult____h455115[16] &&
!_theResult____h455115[15] &&
!_theResult____h455115[14] &&
!_theResult____h455115[13] &&
!_theResult____h455115[12] &&
!_theResult____h455115[11] &&
!_theResult____h455115[10] &&
!_theResult____h455115[9] &&
!_theResult____h455115[8] &&
!_theResult____h455115[7] &&
!_theResult____h455115[6] &&
!_theResult____h455115[5] &&
!_theResult____h455115[4] &&
!_theResult____h455115[3] &&
!_theResult____h455115[2] &&
!_theResult____h455115[1] &&
!_theResult____h455115[0]) ?
_theResult____h455115 :
_theResult___snd__h463393 ;
assign _theResult___snd__h463393 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0],
2'd0 } ;
assign _theResult___snd__h463416 =
_theResult____h455115 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7582 ;
assign _theResult___snd__h471984 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h471998 :
_theResult___snd__h454196 ;
assign _theResult___snd__h471998 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7207) ?
sfd__h429876 :
_theResult___snd__h472004 ;
assign _theResult___snd__h472004 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0],
2'd0 } ;
assign _theResult___snd__h472022 =
sfd__h429876 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7656) ;
assign _theResult___snd__h501478 =
(f1_exp__h482139 == 8'd0) ?
_theResult___snd__h501487 :
_theResult___snd__h501480 ;
assign _theResult___snd__h501480 = { f1_sfd__h482140, 34'd0 } ;
assign _theResult___snd__h501487 =
(f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ?
sfd__h482501 :
_theResult___snd__h501493 ;
assign _theResult___snd__h501493 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0],
2'd0 } ;
assign _theResult___snd__h501516 =
sfd__h482501 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8583 ;
assign _theResult___snd__h511115 = { _theResult____h502868[55:0], 1'd0 } ;
assign _theResult___snd__h511126 =
(!_theResult____h502868[56] && _theResult____h502868[55]) ?
_theResult___snd__h511128 :
_theResult___snd__h511138 ;
assign _theResult___snd__h511128 = { _theResult____h502868[54:0], 2'd0 } ;
assign _theResult___snd__h511138 =
(!_theResult____h502868[56] && !_theResult____h502868[55] &&
!_theResult____h502868[54] &&
!_theResult____h502868[53] &&
!_theResult____h502868[52] &&
!_theResult____h502868[51] &&
!_theResult____h502868[50] &&
!_theResult____h502868[49] &&
!_theResult____h502868[48] &&
!_theResult____h502868[47] &&
!_theResult____h502868[46] &&
!_theResult____h502868[45] &&
!_theResult____h502868[44] &&
!_theResult____h502868[43] &&
!_theResult____h502868[42] &&
!_theResult____h502868[41] &&
!_theResult____h502868[40] &&
!_theResult____h502868[39] &&
!_theResult____h502868[38] &&
!_theResult____h502868[37] &&
!_theResult____h502868[36] &&
!_theResult____h502868[35] &&
!_theResult____h502868[34] &&
!_theResult____h502868[33] &&
!_theResult____h502868[32] &&
!_theResult____h502868[31] &&
!_theResult____h502868[30] &&
!_theResult____h502868[29] &&
!_theResult____h502868[28] &&
!_theResult____h502868[27] &&
!_theResult____h502868[26] &&
!_theResult____h502868[25] &&
!_theResult____h502868[24] &&
!_theResult____h502868[23] &&
!_theResult____h502868[22] &&
!_theResult____h502868[21] &&
!_theResult____h502868[20] &&
!_theResult____h502868[19] &&
!_theResult____h502868[18] &&
!_theResult____h502868[17] &&
!_theResult____h502868[16] &&
!_theResult____h502868[15] &&
!_theResult____h502868[14] &&
!_theResult____h502868[13] &&
!_theResult____h502868[12] &&
!_theResult____h502868[11] &&
!_theResult____h502868[10] &&
!_theResult____h502868[9] &&
!_theResult____h502868[8] &&
!_theResult____h502868[7] &&
!_theResult____h502868[6] &&
!_theResult____h502868[5] &&
!_theResult____h502868[4] &&
!_theResult____h502868[3] &&
!_theResult____h502868[2] &&
!_theResult____h502868[1] &&
!_theResult____h502868[0]) ?
_theResult____h502868 :
_theResult___snd__h511144 ;
assign _theResult___snd__h511144 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0],
2'd0 } ;
assign _theResult___snd__h511167 =
_theResult____h502868 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8895 ;
assign _theResult___snd__h519883 =
(f1_exp__h482139 == 8'd0) ?
_theResult___snd__h519897 :
_theResult___snd__h501480 ;
assign _theResult___snd__h519897 =
(f1_exp__h482139 == 8'd0 && !f1_sfd__h482140[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8556) ?
sfd__h482501 :
_theResult___snd__h519903 ;
assign _theResult___snd__h519903 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0],
2'd0 } ;
assign _theResult___snd__h519921 =
sfd__h482501 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8946 ;
assign _theResult___snd__h540331 =
(f2_exp__h521133 == 8'd0) ?
_theResult___snd__h540340 :
_theResult___snd__h540333 ;
assign _theResult___snd__h540333 = { f2_sfd__h521134, 34'd0 } ;
assign _theResult___snd__h540340 =
(f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ?
sfd__h521495 :
_theResult___snd__h540346 ;
assign _theResult___snd__h540346 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0],
2'd0 } ;
assign _theResult___snd__h540369 =
sfd__h521495 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10083 ;
assign _theResult___snd__h549968 = { _theResult____h541721[55:0], 1'd0 } ;
assign _theResult___snd__h549979 =
(!_theResult____h541721[56] && _theResult____h541721[55]) ?
_theResult___snd__h549981 :
_theResult___snd__h549991 ;
assign _theResult___snd__h549981 = { _theResult____h541721[54:0], 2'd0 } ;
assign _theResult___snd__h549991 =
(!_theResult____h541721[56] && !_theResult____h541721[55] &&
!_theResult____h541721[54] &&
!_theResult____h541721[53] &&
!_theResult____h541721[52] &&
!_theResult____h541721[51] &&
!_theResult____h541721[50] &&
!_theResult____h541721[49] &&
!_theResult____h541721[48] &&
!_theResult____h541721[47] &&
!_theResult____h541721[46] &&
!_theResult____h541721[45] &&
!_theResult____h541721[44] &&
!_theResult____h541721[43] &&
!_theResult____h541721[42] &&
!_theResult____h541721[41] &&
!_theResult____h541721[40] &&
!_theResult____h541721[39] &&
!_theResult____h541721[38] &&
!_theResult____h541721[37] &&
!_theResult____h541721[36] &&
!_theResult____h541721[35] &&
!_theResult____h541721[34] &&
!_theResult____h541721[33] &&
!_theResult____h541721[32] &&
!_theResult____h541721[31] &&
!_theResult____h541721[30] &&
!_theResult____h541721[29] &&
!_theResult____h541721[28] &&
!_theResult____h541721[27] &&
!_theResult____h541721[26] &&
!_theResult____h541721[25] &&
!_theResult____h541721[24] &&
!_theResult____h541721[23] &&
!_theResult____h541721[22] &&
!_theResult____h541721[21] &&
!_theResult____h541721[20] &&
!_theResult____h541721[19] &&
!_theResult____h541721[18] &&
!_theResult____h541721[17] &&
!_theResult____h541721[16] &&
!_theResult____h541721[15] &&
!_theResult____h541721[14] &&
!_theResult____h541721[13] &&
!_theResult____h541721[12] &&
!_theResult____h541721[11] &&
!_theResult____h541721[10] &&
!_theResult____h541721[9] &&
!_theResult____h541721[8] &&
!_theResult____h541721[7] &&
!_theResult____h541721[6] &&
!_theResult____h541721[5] &&
!_theResult____h541721[4] &&
!_theResult____h541721[3] &&
!_theResult____h541721[2] &&
!_theResult____h541721[1] &&
!_theResult____h541721[0]) ?
_theResult____h541721 :
_theResult___snd__h549997 ;
assign _theResult___snd__h549997 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0],
2'd0 } ;
assign _theResult___snd__h550020 =
_theResult____h541721 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10380 ;
assign _theResult___snd__h558736 =
(f2_exp__h521133 == 8'd0) ?
_theResult___snd__h558750 :
_theResult___snd__h540333 ;
assign _theResult___snd__h558750 =
(f2_exp__h521133 == 8'd0 && !f2_sfd__h521134[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10056) ?
sfd__h521495 :
_theResult___snd__h558756 ;
assign _theResult___snd__h558756 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0],
2'd0 } ;
assign _theResult___snd__h558774 =
sfd__h521495 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10431 ;
assign _theResult___snd__h579635 =
(f3_exp__h560437 == 8'd0) ?
_theResult___snd__h579644 :
_theResult___snd__h579637 ;
assign _theResult___snd__h579637 = { f3_sfd__h560438, 34'd0 } ;
assign _theResult___snd__h579644 =
(f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ?
sfd__h560799 :
_theResult___snd__h579650 ;
assign _theResult___snd__h579650 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0],
2'd0 } ;
assign _theResult___snd__h579673 =
sfd__h560799 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9313 ;
assign _theResult___snd__h589272 = { _theResult____h581025[55:0], 1'd0 } ;
assign _theResult___snd__h589283 =
(!_theResult____h581025[56] && _theResult____h581025[55]) ?
_theResult___snd__h589285 :
_theResult___snd__h589295 ;
assign _theResult___snd__h589285 = { _theResult____h581025[54:0], 2'd0 } ;
assign _theResult___snd__h589295 =
(!_theResult____h581025[56] && !_theResult____h581025[55] &&
!_theResult____h581025[54] &&
!_theResult____h581025[53] &&
!_theResult____h581025[52] &&
!_theResult____h581025[51] &&
!_theResult____h581025[50] &&
!_theResult____h581025[49] &&
!_theResult____h581025[48] &&
!_theResult____h581025[47] &&
!_theResult____h581025[46] &&
!_theResult____h581025[45] &&
!_theResult____h581025[44] &&
!_theResult____h581025[43] &&
!_theResult____h581025[42] &&
!_theResult____h581025[41] &&
!_theResult____h581025[40] &&
!_theResult____h581025[39] &&
!_theResult____h581025[38] &&
!_theResult____h581025[37] &&
!_theResult____h581025[36] &&
!_theResult____h581025[35] &&
!_theResult____h581025[34] &&
!_theResult____h581025[33] &&
!_theResult____h581025[32] &&
!_theResult____h581025[31] &&
!_theResult____h581025[30] &&
!_theResult____h581025[29] &&
!_theResult____h581025[28] &&
!_theResult____h581025[27] &&
!_theResult____h581025[26] &&
!_theResult____h581025[25] &&
!_theResult____h581025[24] &&
!_theResult____h581025[23] &&
!_theResult____h581025[22] &&
!_theResult____h581025[21] &&
!_theResult____h581025[20] &&
!_theResult____h581025[19] &&
!_theResult____h581025[18] &&
!_theResult____h581025[17] &&
!_theResult____h581025[16] &&
!_theResult____h581025[15] &&
!_theResult____h581025[14] &&
!_theResult____h581025[13] &&
!_theResult____h581025[12] &&
!_theResult____h581025[11] &&
!_theResult____h581025[10] &&
!_theResult____h581025[9] &&
!_theResult____h581025[8] &&
!_theResult____h581025[7] &&
!_theResult____h581025[6] &&
!_theResult____h581025[5] &&
!_theResult____h581025[4] &&
!_theResult____h581025[3] &&
!_theResult____h581025[2] &&
!_theResult____h581025[1] &&
!_theResult____h581025[0]) ?
_theResult____h581025 :
_theResult___snd__h589301 ;
assign _theResult___snd__h589301 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0],
2'd0 } ;
assign _theResult___snd__h589324 =
_theResult____h581025 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9610 ;
assign _theResult___snd__h598040 =
(f3_exp__h560437 == 8'd0) ?
_theResult___snd__h598054 :
_theResult___snd__h579637 ;
assign _theResult___snd__h598054 =
(f3_exp__h560437 == 8'd0 && !f3_sfd__h560438[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9286) ?
sfd__h560799 :
_theResult___snd__h598060 ;
assign _theResult___snd__h598060 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0],
2'd0 } ;
assign _theResult___snd__h598078 =
sfd__h560799 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9661 ;
assign _theResult___snd__h603370 =
b__h602948[63] ? b___1__h603419 : b__h602948 ;
assign _theResult___snd_fst_exp__h363377 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
_theResult___fst_exp__h354792 :
_theResult___fst_exp__h363374 ;
assign _theResult___snd_fst_exp__h381197 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
_theResult___fst_exp__h372558 :
_theResult___fst_exp__h381194 ;
assign _theResult___snd_fst_exp__h409074 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
_theResult___fst_exp__h400489 :
_theResult___fst_exp__h409071 ;
assign _theResult___snd_fst_exp__h426894 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
_theResult___fst_exp__h418255 :
_theResult___fst_exp__h426891 ;
assign _theResult___snd_fst_exp__h454769 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
_theResult___fst_exp__h446184 :
_theResult___fst_exp__h454766 ;
assign _theResult___snd_fst_exp__h472589 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
_theResult___fst_exp__h463950 :
_theResult___fst_exp__h472586 ;
assign _theResult___snd_fst_exp__h502288 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ?
11'd0 :
_theResult___fst_exp__h502285 ;
assign _theResult___snd_fst_exp__h520723 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
_theResult___fst_exp__h511936 :
_theResult___fst_exp__h520720 ;
assign _theResult___snd_fst_exp__h541141 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ?
11'd0 :
_theResult___fst_exp__h541138 ;
assign _theResult___snd_fst_exp__h559576 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
_theResult___fst_exp__h550789 :
_theResult___fst_exp__h559573 ;
assign _theResult___snd_fst_exp__h580445 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ?
11'd0 :
_theResult___fst_exp__h580442 ;
assign _theResult___snd_fst_exp__h598880 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
_theResult___fst_exp__h590093 :
_theResult___fst_exp__h598877 ;
assign _theResult___snd_fst_sfd__h338429 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h363378 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4013 ?
_theResult___fst_sfd__h354793 :
_theResult___fst_sfd__h363375 ;
assign _theResult___snd_fst_sfd__h381198 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4553 ?
_theResult___fst_sfd__h372559 :
_theResult___fst_sfd__h381195 ;
assign _theResult___snd_fst_sfd__h384131 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h409075 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5405 ?
_theResult___fst_sfd__h400490 :
_theResult___fst_sfd__h409072 ;
assign _theResult___snd_fst_sfd__h426895 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5945 ?
_theResult___fst_sfd__h418256 :
_theResult___fst_sfd__h426892 ;
assign _theResult___snd_fst_sfd__h429826 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h454770 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6797 ?
_theResult___fst_sfd__h446185 :
_theResult___fst_sfd__h454767 ;
assign _theResult___snd_fst_sfd__h472590 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7337 ?
_theResult___fst_sfd__h463951 :
_theResult___fst_sfd__h472587 ;
assign _theResult___snd_fst_sfd__h482455 =
(f1_sfd__h482140 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h482203 ;
assign _theResult___snd_fst_sfd__h502289 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8512 ?
52'd0 :
_theResult___fst_sfd__h502286 ;
assign _theResult___snd_fst_sfd__h520724 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8648 ?
_theResult___fst_sfd__h511937 :
_theResult___fst_sfd__h520721 ;
assign _theResult___snd_fst_sfd__h521449 =
(f2_sfd__h521134 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h521197 ;
assign _theResult___snd_fst_sfd__h541142 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10012 ?
52'd0 :
_theResult___fst_sfd__h541139 ;
assign _theResult___snd_fst_sfd__h559577 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10133 ?
_theResult___fst_sfd__h550790 :
_theResult___fst_sfd__h559574 ;
assign _theResult___snd_fst_sfd__h560753 =
(f3_sfd__h560438 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h560501 ;
assign _theResult___snd_fst_sfd__h580446 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9242 ?
52'd0 :
_theResult___fst_sfd__h580443 ;
assign _theResult___snd_fst_sfd__h598881 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9363 ?
_theResult___fst_sfd__h590094 :
_theResult___fst_sfd__h598878 ;
assign a___1__h603088 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ?
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } :
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 } ;
assign a___1__h603374 = 64'd0 - a__h602947 ;
assign a__h602947 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
a___1__h603088 :
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign b___1__h603089 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 } :
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ;
assign b___1__h603419 = 64'd0 - b__h602948 ;
assign b__h602948 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
b___1__h603089 :
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign base__h711423 = { csrf_stvec_base_hi_reg, 2'b0 } ;
assign base__h711443 = { csrf_mtvec_base_hi_reg, 2'b0 } ;
assign cause_code__h708463 =
commitStage_commitTrap[36] ? i__h708638 : i__h708478 ;
assign commitStage_commitTrap_4336_BIT_36_4579_AND_co_ETC___d14644 =
commitStage_commitTrap[36] &&
commitStage_commitTrap[35:32] != 4'd0 &&
commitStage_commitTrap[35:32] != 4'd1 &&
commitStage_commitTrap[35:32] != 4'd3 &&
commitStage_commitTrap[35:32] != 4'd4 &&
commitStage_commitTrap[35:32] != 4'd5 &&
commitStage_commitTrap[35:32] != 4'd7 &&
commitStage_commitTrap[35:32] != 4'd8 &&
commitStage_commitTrap[35:32] != 4'd9 &&
commitStage_commitTrap[35:32] != 4'd11 ||
!commitStage_commitTrap[36] &&
commitStage_commitTrap[35:32] == 4'd3 &&
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 ;
assign commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438 =
commitStage_rg_serial_num + y__h729714 ;
assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12205 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_0_wget__2203_BITS__ETC___d12244 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12218 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2216_BITS__ETC___d12250 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12226 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2224_BITS__ETC___d12254 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_dispToRegQ_first__2182_BIT_13_ETC___d12267 =
(coreFix_aluExe_0_dispToRegQ$first[131] ||
sbCons$lazyLookup_0_get[3] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12213 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12239) &&
(sbCons$lazyLookup_0_get[2] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2181_ETC___d12247 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12264) ;
assign coreFix_aluExe_0_exeToFinQ_RDY_first__2641_AND_ETC___d12680 =
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 ||
coreFix_trainBPQ_0$FULL_N) ;
assign coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 =
coreFix_aluExe_0_rsAlu$approximateCount <
coreFix_aluExe_1_rsAlu$approximateCount ;
assign coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11345 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_0_wget__1343_BITS__ETC___d11384 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11358 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1356_BITS__ETC___d11390 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11366 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1364_BITS__ETC___d11394 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_dispToRegQ_first__1322_BIT_13_ETC___d11407 =
(coreFix_aluExe_1_dispToRegQ$first[131] ||
sbCons$lazyLookup_1_get[3] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11353 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11379) &&
(sbCons$lazyLookup_1_get[2] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1321_ETC___d11387 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11404) ;
assign coreFix_aluExe_1_exeToFinQ_RDY_first__1967_AND_ETC___d12007 =
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10 ||
coreFix_trainBPQ_1$FULL_N) ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8209 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8247 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__207__ETC___d8271 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8222 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8253 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__220__ETC___d8277 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8230 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8257 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__228__ETC___d8281 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5272 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3880 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6664 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8103 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
((coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
2'd2) ?
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid :
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] !=
2'd3 ||
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid) ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8056 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 |
((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) &&
(f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) &&
(f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10847) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 |
((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) &&
(f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) &&
(f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10883) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 |
((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) &&
(f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) &&
(f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10931) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 |
((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) &&
(f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) &&
(f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10973) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 |
((f3_exp__h560437 != 8'd255 || f3_sfd__h560438 == 23'd0) &&
(f3_exp__h560437 != 8'd255 || f3_sfd__h560438 != 23'd0) &&
(f3_exp__h560437 != 8'd0 || f3_sfd__h560438 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11015) ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q12 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q11 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14027 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14007) ;
assign coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1571 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_0_wget__569_BITS_70__ETC___d1609 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1584 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_1_wget__582_BITS_70__ETC___d1615 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1592 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_2_wget__590_BITS_70__ETC___d1619 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2577 =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
y__h254802 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3067 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031 ||
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3170 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138 ||
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas &&
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2070 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2727 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ==
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
2'd2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2531 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2560 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2565 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2564 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2582 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2581 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2599 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2592 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2598 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2619 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2096 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2622 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2619 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2072 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2649 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2643 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2646 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2651 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2017 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2025 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2027 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2697 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2700 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2805 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2814 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2823 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2828 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2848 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3341 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rqToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3437 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rsToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1911 =
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ||
(!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_deqReq_rl) &&
coreFix_memExe_dMem_perfReqQ_full ;
assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726 =
coreFix_memExe_dTlb$procResp[246:186] < 61'd402653184 ;
assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727 =
coreFix_memExe_dTlb$procResp[246:186] < 61'd536870912 ;
assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731 =
coreFix_memExe_dTlb$procResp[246:186] == mmio_toHostAddr ;
assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734 =
coreFix_memExe_dTlb$procResp[246:186] == mmio_fromHostAddr ;
assign coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1735 =
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1726 ||
!coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1727 ||
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1731 ||
coreFix_memExe_dTlb_procResp__714_BITS_246_TO__ETC___d1734 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3759 =
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728 ||
(!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!coreFix_memExe_forwardQ_deqReq_rl) &&
coreFix_memExe_forwardQ_full ;
assign coreFix_memExe_lsq_getOrigBE_coreFix_memExe_re_ETC___d1706 =
{ coreFix_memExe_lsq$getOrigBE << x__h183901[2:0],
x__h183901,
coreFix_memExe_regToExeQ$first[75:12],
coreFix_memExe_lsq$getOrigBE,
coreFix_memExe_lsq$getOrigBE[7] ?
x__h183901[2:0] != 3'd0 :
(coreFix_memExe_lsq$getOrigBE[3] ?
x__h183901[1:0] != 2'd0 :
coreFix_memExe_lsq$getOrigBE[1] && x__h183901[0]) } ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3665 =
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634 ||
(!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!coreFix_memExe_memRespLdQ_deqReq_rl) &&
coreFix_memExe_memRespLdQ_full ;
assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 =
coreFix_memExe_regToExeQ$first[189:158] ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3574 =
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3558 ||
(!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas &&
!coreFix_memExe_respLrScAmoQ_deqReq_rl) &&
coreFix_memExe_respLrScAmoQ_full ;
assign coreFix_memExe_stb_isEmpty__009_AND_coreFix_me_ETC___d14646 =
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
v_f_to_TV_0$FULL_N &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq ;
assign csr_addr__h655325 =
fetchStage$pipelines_0_first[173] ?
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 :
12'hCFF ;
assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13045 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[199:195] == 5'd13 &&
(fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 ||
csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 ||
csr_addr__h655325 == 12'h8FF) ;
assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_1_first[95] &&
fetchStage$pipelines_1_first[94] ||
fetchStage$pipelines_1_first[88] &&
fetchStage$pipelines_1_first[87] ||
fetchStage$pipelines_1_first[81] ||
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74]) ||
fetchStage$pipelines_1_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 =
csrf_prv_reg_read__2787_ULE_1___d14685 &&
(commitStage_commitTrap[36] ?
_0b0_CONCAT_csrf_mideleg_11_reg_read__1653_1654_ETC___d14687 :
_0b0_CONCAT_csrf_medeleg_15_reg_read__1645_1646_ETC___d14705) ;
assign csrf_prv_reg_read__2787_ULE_1___d14685 = csrf_prv_reg <= 2'd1 ;
assign csrf_prv_reg_read__2787_ULT_IF_fetchStage_pipe_ETC___d13040 =
csrf_prv_reg < csr_addr__h655325[9:8] ;
assign csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498 =
csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first &&
IF_fetchStage_RDY_pipelines_0_first__2754_AND__ETC___d13435 ;
assign data75281_BITS_31_TO_0__q14 = data__h475281[31:0] ;
assign data___1__h475007 =
{ {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}},
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ;
assign data___1__h475815 =
{ {32{data75281_BITS_31_TO_0__q14[31]}},
data75281_BITS_31_TO_0__q14 } ;
assign data__h475281 =
(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
2'd2) ?
x_quotient__h475195 :
x_remainder__h475196 ;
assign dcsr_cause__h707982 =
(commitStage_commitTrap[36] &&
commitStage_commitTrap[35:32] == 4'd14) ?
3'd3 :
((commitStage_commitTrap[36] &&
commitStage_commitTrap[35:32] != 4'd0 &&
commitStage_commitTrap[35:32] != 4'd1 &&
commitStage_commitTrap[35:32] != 4'd3 &&
commitStage_commitTrap[35:32] != 4'd4 &&
commitStage_commitTrap[35:32] != 4'd5 &&
commitStage_commitTrap[35:32] != 4'd7 &&
commitStage_commitTrap[35:32] != 4'd8 &&
commitStage_commitTrap[35:32] != 4'd9 &&
commitStage_commitTrap[35:32] != 4'd11 &&
commitStage_commitTrap[35:32] != 4'd14) ?
3'd4 :
3'd1) ;
assign din_inc___2_exp__h381228 = _theResult___fst_exp__h354195 + 8'd1 ;
assign din_inc___2_exp__h381252 = _theResult___fst_exp__h362851 + 8'd1 ;
assign din_inc___2_exp__h381282 = _theResult___fst_exp__h371961 + 8'd1 ;
assign din_inc___2_exp__h381306 = _theResult___fst_exp__h380646 + 8'd1 ;
assign din_inc___2_exp__h426925 = _theResult___fst_exp__h399892 + 8'd1 ;
assign din_inc___2_exp__h426949 = _theResult___fst_exp__h408548 + 8'd1 ;
assign din_inc___2_exp__h426979 = _theResult___fst_exp__h417658 + 8'd1 ;
assign din_inc___2_exp__h427003 = _theResult___fst_exp__h426343 + 8'd1 ;
assign din_inc___2_exp__h472620 = _theResult___fst_exp__h445587 + 8'd1 ;
assign din_inc___2_exp__h472644 = _theResult___fst_exp__h454243 + 8'd1 ;
assign din_inc___2_exp__h472674 = _theResult___fst_exp__h463353 + 8'd1 ;
assign din_inc___2_exp__h472698 = _theResult___fst_exp__h472038 + 8'd1 ;
assign din_inc___2_exp__h520777 = _theResult___fst_exp__h501527 + 11'd1 ;
assign din_inc___2_exp__h520812 = _theResult___fst_exp__h511104 + 11'd1 ;
assign din_inc___2_exp__h520838 = _theResult___fst_exp__h519937 + 11'd1 ;
assign din_inc___2_exp__h559630 = _theResult___fst_exp__h540380 + 11'd1 ;
assign din_inc___2_exp__h559665 = _theResult___fst_exp__h549957 + 11'd1 ;
assign din_inc___2_exp__h559691 = _theResult___fst_exp__h558790 + 11'd1 ;
assign din_inc___2_exp__h598934 = _theResult___fst_exp__h579684 + 11'd1 ;
assign din_inc___2_exp__h598969 = _theResult___fst_exp__h589261 + 11'd1 ;
assign din_inc___2_exp__h598995 = _theResult___fst_exp__h598094 + 11'd1 ;
assign enabled_ints___1__h651641 = pend_ints__h651114 & y__h651653 ;
assign enabled_ints__h651687 =
pend_ints__h651114 &
{ r1__read_BITS_13_TO_0___h651663, csrf_mideleg_1_0_reg } ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13734 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13465) ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13876 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13872) ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13894 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890) ;
assign f1_exp82139_MINUS_127__q136 = f1_exp__h482139 - 8'd127 ;
assign f1_exp__h482139 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] :
8'd255 ;
assign f1_sfd__h482140 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] :
23'd4194304 ;
assign f2_exp21133_MINUS_127__q176 = f2_exp__h521133 - 8'd127 ;
assign f2_exp__h521133 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] :
8'd255 ;
assign f2_sfd__h521134 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] :
23'd4194304 ;
assign f3_exp60437_MINUS_127__q153 = f3_exp__h560437 - 8'd127 ;
assign f3_exp__h560437 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] :
8'd255 ;
assign f3_sfd__h560438 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] :
23'd4194304 ;
assign f_csr_rsps_i_notFull__5777_AND_f_csr_reqs_firs_ETC___d15880 =
f_csr_rsps$FULL_N &&
(f_csr_reqs$D_OUT[75:64] != 12'd2049 ||
csrf_stats_module_writeQ$FULL_N) &&
(f_csr_reqs$D_OUT[75:64] != 12'd2048 ||
csrf_terminate_module_terminateQ$FULL_N) ;
assign fcsr_csr__read__h609375 = { 56'd0, x__h613033 } ;
assign fetchStage_RDY_pipelines_1_deq__2769_AND_NOT_f_ETC___d14078 =
fetchStage$RDY_pipelines_1_deq &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14074) &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14018 =
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14014) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ;
assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14100 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 ;
assign fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14176 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d14097 &&
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 ||
!coreFix_aluExe_0_rsAlu$canEnq ;
assign fetchStage_pipelines_0_canDeq__2755_AND_fetchS_ETC___d14088 =
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13962 ||
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13973 ||
!regRenamingTable$rename_1_canRename ||
fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13985 ||
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14084) &&
IF_fetchStage_RDY_pipelines_1_first__2765_AND__ETC___d13905 ;
assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14024 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ;
assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14031 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14053 =
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14024 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13837 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14044) ;
assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14065 =
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14031 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13837 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14056) ;
assign fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14296 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d14294 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign fetchStage_pipelines_0_canDeq__2755_AND_specTa_ETC___d14152 =
fetchStage$pipelines_0_canDeq && specTagManager$canClaim &&
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13038 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 &&
fetchStage$pipelines_0_first[178:174] == 5'd15 ||
rs1__h655326 != 5'd0 ||
imm__h655327 != 32'd0) &&
csr_addr__h655325[11:10] == 2'b11 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13745 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 &&
(!coreFix_aluExe_1_rsAlu$canEnq ||
coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444) ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13844 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13956 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13945 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13954 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13962 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920 ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13961 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13979 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13008[4] ||
!rob$enqPort_0_canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13961 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13761 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3403__ETC___d13761 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 ||
coreFix_aluExe_0_rsAlu$canEnq &&
coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ;
assign fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d14014 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13509 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 ;
assign fetchStage_pipelines_0_first__2757_BITS_199_TO_ETC___d13509 =
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13008[4] ||
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_0_first__2757_BIT_68_2786_ETC___d13835 =
fetchStage$pipelines_0_first[68] ||
checkForException___d13008[4] ||
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13502 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_1_first__2766_BITS_194_TO_ETC___d13973 =
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13970 ||
!specTagManager$canClaim) ;
assign fetchStage_pipelines_1_first__2766_BITS_199_TO_ETC___d13985 =
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_1_first[68] ||
checkForException___d13698[4] ||
csrf_fs_reg_read__1546_EQ_0_2997_AND_fetchStag_ETC___d13791 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
csrf_rg_dcsr[2] ||
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13979 ;
assign fetchStage_pipelines_1_first__2766_BIT_173_358_ETC___d13676 =
{ fetchStage$pipelines_1_first[173],
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ;
assign fflags__h727255 =
({ rob$deqPort_0_deq_data[361:356],
1'd0,
rob$deqPort_0_deq_data[354:350],
5'd0,
rob$deqPort_0_deq_data[344:342],
5'd0,
rob$deqPort_0_deq_data[336:330] } ==
32'hE0000053) ?
5'b0 :
po_fflags__h727241 ;
assign fflags__h729891 =
({ rob$deqPort_1_deq_data[361:356],
1'd0,
rob$deqPort_1_deq_data[354:350],
5'd0,
rob$deqPort_1_deq_data[344:342],
5'd0,
rob$deqPort_1_deq_data[336:330] } ==
32'hE0000053) ?
5'b0 :
po_fflags__h729877 ;
assign fflags__h732495 =
NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ?
y_avValue_fst__h732432 :
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 ;
assign fflags_csr__read__h609350 = { 59'd0, csrf_fflags_reg } ;
assign frm_csr__read__h609361 = { 61'd0, csrf_frm_reg } ;
assign guard__h346094 =
{ IF_sfdin54189_BIT_33_THEN_2_ELSE_0__q29[1],
{ sfdin__h354189[32:0], 23'd0 } != 56'd0 } ;
assign guard__h354803 =
{ IF_theResult___snd62802_BIT_33_THEN_2_ELSE_0__q31[1],
{ _theResult___snd__h362802[32:0], 23'd0 } != 56'd0 } ;
assign guard__h363733 =
{ IF_sfdin71955_BIT_33_THEN_2_ELSE_0__q39[1],
{ sfdin__h371955[32:0], 23'd0 } != 56'd0 } ;
assign guard__h364331 = x__h364433 != 57'd0 ;
assign guard__h372569 =
{ IF_theResult___snd80592_BIT_33_THEN_2_ELSE_0__q44[1],
{ _theResult___snd__h380592[32:0], 23'd0 } != 56'd0 } ;
assign guard__h391793 =
{ IF_sfdin99886_BIT_33_THEN_2_ELSE_0__q64[1],
{ sfdin__h399886[32:0], 23'd0 } != 56'd0 } ;
assign guard__h400500 =
{ IF_theResult___snd08499_BIT_33_THEN_2_ELSE_0__q66[1],
{ _theResult___snd__h408499[32:0], 23'd0 } != 56'd0 } ;
assign guard__h409430 =
{ IF_sfdin17652_BIT_33_THEN_2_ELSE_0__q74[1],
{ sfdin__h417652[32:0], 23'd0 } != 56'd0 } ;
assign guard__h410028 = x__h410130 != 57'd0 ;
assign guard__h418266 =
{ IF_theResult___snd26289_BIT_33_THEN_2_ELSE_0__q79[1],
{ _theResult___snd__h426289[32:0], 23'd0 } != 56'd0 } ;
assign guard__h437488 =
{ IF_sfdin45581_BIT_33_THEN_2_ELSE_0__q99[1],
{ sfdin__h445581[32:0], 23'd0 } != 56'd0 } ;
assign guard__h446195 =
{ IF_theResult___snd54194_BIT_33_THEN_2_ELSE_0__q101[1],
{ _theResult___snd__h454194[32:0], 23'd0 } != 56'd0 } ;
assign guard__h455125 =
{ IF_sfdin63347_BIT_33_THEN_2_ELSE_0__q109[1],
{ sfdin__h463347[32:0], 23'd0 } != 56'd0 } ;
assign guard__h455723 = x__h455825 != 57'd0 ;
assign guard__h463961 =
{ IF_theResult___snd71984_BIT_33_THEN_2_ELSE_0__q114[1],
{ _theResult___snd__h471984[32:0], 23'd0 } != 56'd0 } ;
assign guard__h493566 =
{ IF_theResult___snd01478_BIT_4_THEN_2_ELSE_0__q135[1],
{ _theResult___snd__h501478[3:0], 52'd0 } != 56'd0 } ;
assign guard__h502878 =
{ IF_sfdin11098_BIT_4_THEN_2_ELSE_0__q139[1],
{ sfdin__h511098[3:0], 52'd0 } != 56'd0 } ;
assign guard__h503476 = x__h503576 != 57'd0 ;
assign guard__h511947 =
{ IF_theResult___snd19883_BIT_4_THEN_2_ELSE_0__q142[1],
{ _theResult___snd__h519883[3:0], 52'd0 } != 56'd0 } ;
assign guard__h532419 =
{ IF_theResult___snd40331_BIT_4_THEN_2_ELSE_0__q175[1],
{ _theResult___snd__h540331[3:0], 52'd0 } != 56'd0 } ;
assign guard__h541731 =
{ IF_sfdin49951_BIT_4_THEN_2_ELSE_0__q179[1],
{ sfdin__h549951[3:0], 52'd0 } != 56'd0 } ;
assign guard__h542329 = x__h542429 != 57'd0 ;
assign guard__h550800 =
{ IF_theResult___snd58736_BIT_4_THEN_2_ELSE_0__q182[1],
{ _theResult___snd__h558736[3:0], 52'd0 } != 56'd0 } ;
assign guard__h571723 =
{ IF_theResult___snd79635_BIT_4_THEN_2_ELSE_0__q152[1],
{ _theResult___snd__h579635[3:0], 52'd0 } != 56'd0 } ;
assign guard__h581035 =
{ IF_sfdin89255_BIT_4_THEN_2_ELSE_0__q156[1],
{ sfdin__h589255[3:0], 52'd0 } != 56'd0 } ;
assign guard__h581633 = x__h581733 != 57'd0 ;
assign guard__h590104 =
{ IF_theResult___snd98040_BIT_4_THEN_2_ELSE_0__q159[1],
{ _theResult___snd__h598040[3:0], 52'd0 } != 56'd0 } ;
assign idx__h685368 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13770 ;
assign imm__h655327 =
fetchStage$pipelines_0_first[160] ?
fetchStage$pipelines_0_first[159:128] :
32'd0 ;
assign k__h669623 =
!coreFix_aluExe_0_rsAlu$canEnq ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3442__ETC___d13444 ;
assign mcause_csr__read__h611017 =
{ r1__read__h614496, csrf_mcause_code_reg } ;
assign mcounteren_csr__read__h610762 =
{ r1__read__h614483, csrf_mcounteren_cy_reg } ;
assign medeleg_csr__read__h610369 =
{ r1__read__h614344, csrf_medeleg_9_0_reg } ;
assign mideleg_csr__read__h610464 =
{ r1__read__h614361, csrf_mideleg_1_0_reg } ;
assign mie_csr__read__h610588 = { r1__read__h614385, 1'b0 } ;
assign mip_csr__read__h611250 = { r1__read__h614502, 1'b0 } ;
assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 =
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ||
(!mmio_cRqQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) &&
mmio_cRqQ_full ;
assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 =
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ||
(!mmio_cRsQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) &&
mmio_cRsQ_full ;
assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 =
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT &&
(mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) ||
(!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataPendQ_deqReq_rl) &&
mmio_dataPendQ_full ;
assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 =
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ||
(!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) &&
mmio_dataReqQ_full ;
assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 =
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ||
(!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataRespQ_deqReq_rl) &&
mmio_dataRespQ_full ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13055 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
(renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13052) ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13344 ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13365 =
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13347 &&
(fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20) &&
rob$isEmpty ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14092 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_278_ETC___d13422 ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14094 =
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14092 &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
rg_core_run_state == 2'd2 ;
assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 =
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ||
(!mmio_pRqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) &&
mmio_pRqQ_full ;
assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 =
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ||
(!mmio_pRsQ_deqReq_dummy2_2$Q_OUT ||
!mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) &&
mmio_pRsQ_full ;
assign msip__h76121 = csrf_software_int_pend_vec_3 ;
assign mstatus_csr__read__h610221 = { r1__read__h614219, csrf_ie_vec_0 } ;
assign mtvec_csr__read__h610670 =
{ r1__read__h614478, csrf_mtvec_mode_low_reg } ;
assign n___1__h198528 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] :
x__h197125[63:56],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] :
x__h197125[55:48],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] :
x__h197125[47:40],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] :
x__h197125[39:32],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] :
x__h197125[31:24],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] :
x__h197125[23:16],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] :
x__h197125[15:8],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] :
x__h197125[7:0] } ;
assign n__read__h611354 =
(csrf_mcycle_ehr_data_dummy2_0$Q_OUT &&
csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ?
csrf_mcycle_ehr_data_rl :
64'd0 ;
assign n__read__h611545 =
(csrf_minstret_ehr_data_dummy2_0$Q_OUT &&
csrf_minstret_ehr_data_dummy2_1$Q_OUT) ?
csrf_minstret_ehr_data_rl :
64'd0 ;
assign n__read__h6759 =
csrf_mcycle_ehr_data_dummy2_1$Q_OUT ?
(csrf_mcycle_ehr_data_lat_0$whas ?
upd__h6873 :
csrf_mcycle_ehr_data_rl) :
64'd0 ;
assign n__read__h725937 =
csrf_minstret_ehr_data_dummy2_1$Q_OUT ?
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 :
64'd0 ;
assign next_deqP___1__h296799 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP +
3'd1 ;
assign next_deqP___1__h304795 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ;
assign next_deqP___1__h311076 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ;
assign next_deqP___1__h318930 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ;
assign next_deqP___1__h328987 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ;
assign next_deqP___1__h332212 = coreFix_memExe_forwardQ_deqP + 1'd1 ;
assign next_pc__h721469 =
(rob$deqPort_0_deq_data[329:325] != 5'd13 &&
rob$deqPort_0_deq_data[97:96] == 2'd0) ?
rob$deqPort_0_deq_data[95:32] :
rob$deqPort_0_deq_data[425:362] + 64'd4 ;
assign old_fflags__h731983 =
csrf_fflags_reg | rob$deqPort_0_deq_data[31:27] ;
assign out___1_sfd__h482203 = { f1_sfd__h482140, 29'd0 } ;
assign out___1_sfd__h521197 = { f2_sfd__h521134, 29'd0 } ;
assign out___1_sfd__h560501 = { f3_sfd__h560438, 29'd0 } ;
assign out_exp__h354714 =
sfdin__h354189[34] ?
_theResult___exp__h354711 :
_theResult___fst_exp__h354195 ;
assign out_exp__h363296 =
_theResult___snd__h362802[34] ?
_theResult___exp__h363293 :
_theResult___fst_exp__h362851 ;
assign out_exp__h372480 =
sfdin__h371955[34] ?
_theResult___exp__h372477 :
_theResult___fst_exp__h371961 ;
assign out_exp__h381116 =
_theResult___snd__h380592[34] ?
_theResult___exp__h381113 :
_theResult___fst_exp__h380646 ;
assign out_exp__h400411 =
sfdin__h399886[34] ?
_theResult___exp__h400408 :
_theResult___fst_exp__h399892 ;
assign out_exp__h408993 =
_theResult___snd__h408499[34] ?
_theResult___exp__h408990 :
_theResult___fst_exp__h408548 ;
assign out_exp__h418177 =
sfdin__h417652[34] ?
_theResult___exp__h418174 :
_theResult___fst_exp__h417658 ;
assign out_exp__h426813 =
_theResult___snd__h426289[34] ?
_theResult___exp__h426810 :
_theResult___fst_exp__h426343 ;
assign out_exp__h446106 =
sfdin__h445581[34] ?
_theResult___exp__h446103 :
_theResult___fst_exp__h445587 ;
assign out_exp__h454688 =
_theResult___snd__h454194[34] ?
_theResult___exp__h454685 :
_theResult___fst_exp__h454243 ;
assign out_exp__h463872 =
sfdin__h463347[34] ?
_theResult___exp__h463869 :
_theResult___fst_exp__h463353 ;
assign out_exp__h472508 =
_theResult___snd__h471984[34] ?
_theResult___exp__h472505 :
_theResult___fst_exp__h472038 ;
assign out_exp__h502185 =
_theResult___snd__h501478[5] ?
_theResult___exp__h502182 :
_theResult___fst_exp__h501527 ;
assign out_exp__h511836 =
sfdin__h511098[5] ?
_theResult___exp__h511833 :
_theResult___fst_exp__h511104 ;
assign out_exp__h520620 =
_theResult___snd__h519883[5] ?
_theResult___exp__h520617 :
_theResult___fst_exp__h519937 ;
assign out_exp__h541038 =
_theResult___snd__h540331[5] ?
_theResult___exp__h541035 :
_theResult___fst_exp__h540380 ;
assign out_exp__h550689 =
sfdin__h549951[5] ?
_theResult___exp__h550686 :
_theResult___fst_exp__h549957 ;
assign out_exp__h559473 =
_theResult___snd__h558736[5] ?
_theResult___exp__h559470 :
_theResult___fst_exp__h558790 ;
assign out_exp__h580342 =
_theResult___snd__h579635[5] ?
_theResult___exp__h580339 :
_theResult___fst_exp__h579684 ;
assign out_exp__h589993 =
sfdin__h589255[5] ?
_theResult___exp__h589990 :
_theResult___fst_exp__h589261 ;
assign out_exp__h598777 =
_theResult___snd__h598040[5] ?
_theResult___exp__h598774 :
_theResult___fst_exp__h598094 ;
assign out_f_exp__h381492 =
(_theResult___exp__h381215 == 8'd255 &&
_theResult___sfd__h381216 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h381206 ;
assign out_f_exp__h427189 =
(_theResult___exp__h426912 == 8'd255 &&
_theResult___sfd__h426913 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h426903 ;
assign out_f_exp__h472884 =
(_theResult___exp__h472607 == 8'd255 &&
_theResult___sfd__h472608 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h472598 ;
assign out_f_sfd__h381493 =
(_theResult___exp__h381215 == 8'd255 &&
_theResult___sfd__h381216 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h381216 ;
assign out_f_sfd__h427190 =
(_theResult___exp__h426912 == 8'd255 &&
_theResult___sfd__h426913 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h426913 ;
assign out_f_sfd__h472885 =
(_theResult___exp__h472607 == 8'd255 &&
_theResult___sfd__h472608 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h472608 ;
assign out_sfd__h354715 =
sfdin__h354189[34] ?
_theResult___sfd__h354712 :
sfdin__h354189[56:34] ;
assign out_sfd__h363297 =
_theResult___snd__h362802[34] ?
_theResult___sfd__h363294 :
_theResult___snd__h362802[56:34] ;
assign out_sfd__h372481 =
sfdin__h371955[34] ?
_theResult___sfd__h372478 :
sfdin__h371955[56:34] ;
assign out_sfd__h381117 =
_theResult___snd__h380592[34] ?
_theResult___sfd__h381114 :
_theResult___snd__h380592[56:34] ;
assign out_sfd__h400412 =
sfdin__h399886[34] ?
_theResult___sfd__h400409 :
sfdin__h399886[56:34] ;
assign out_sfd__h408994 =
_theResult___snd__h408499[34] ?
_theResult___sfd__h408991 :
_theResult___snd__h408499[56:34] ;
assign out_sfd__h418178 =
sfdin__h417652[34] ?
_theResult___sfd__h418175 :
sfdin__h417652[56:34] ;
assign out_sfd__h426814 =
_theResult___snd__h426289[34] ?
_theResult___sfd__h426811 :
_theResult___snd__h426289[56:34] ;
assign out_sfd__h446107 =
sfdin__h445581[34] ?
_theResult___sfd__h446104 :
sfdin__h445581[56:34] ;
assign out_sfd__h454689 =
_theResult___snd__h454194[34] ?
_theResult___sfd__h454686 :
_theResult___snd__h454194[56:34] ;
assign out_sfd__h463873 =
sfdin__h463347[34] ?
_theResult___sfd__h463870 :
sfdin__h463347[56:34] ;
assign out_sfd__h472509 =
_theResult___snd__h471984[34] ?
_theResult___sfd__h472506 :
_theResult___snd__h471984[56:34] ;
assign out_sfd__h502186 =
_theResult___snd__h501478[5] ?
_theResult___sfd__h502183 :
_theResult___snd__h501478[56:5] ;
assign out_sfd__h511837 =
sfdin__h511098[5] ?
_theResult___sfd__h511834 :
sfdin__h511098[56:5] ;
assign out_sfd__h520621 =
_theResult___snd__h519883[5] ?
_theResult___sfd__h520618 :
_theResult___snd__h519883[56:5] ;
assign out_sfd__h541039 =
_theResult___snd__h540331[5] ?
_theResult___sfd__h541036 :
_theResult___snd__h540331[56:5] ;
assign out_sfd__h550690 =
sfdin__h549951[5] ?
_theResult___sfd__h550687 :
sfdin__h549951[56:5] ;
assign out_sfd__h559474 =
_theResult___snd__h558736[5] ?
_theResult___sfd__h559471 :
_theResult___snd__h558736[56:5] ;
assign out_sfd__h580343 =
_theResult___snd__h579635[5] ?
_theResult___sfd__h580340 :
_theResult___snd__h579635[56:5] ;
assign out_sfd__h589994 =
sfdin__h589255[5] ?
_theResult___sfd__h589991 :
sfdin__h589255[56:5] ;
assign out_sfd__h598778 =
_theResult___snd__h598040[5] ?
_theResult___sfd__h598775 :
_theResult___snd__h598040[56:5] ;
assign pc__h711407 =
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ?
y_avValue_new_pc__h711199 :
y_avValue_new_pc__h711385 ;
assign pend_ints__h651114 =
{ _0_CONCAT_csrf_external_int_en_vec_3_read__1664_ETC___d12798,
csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3,
1'd0,
csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1,
1'd0 } ;
assign po_fflags__h727241 = old_fflags__h731983 ;
assign po_fflags__h729877 =
old_fflags__h731983 | rob$deqPort_1_deq_data[31:27] ;
assign prv__h734164 = csrf_prv_reg ;
assign prv__h734208 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ;
assign q___1__h475880 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ;
assign r1__read_BITS_13_TO_0___h651663 =
{ 4'd0,
csrf_mideleg_11_reg,
1'b0,
csrf_mideleg_9_7_reg,
1'b0,
csrf_mideleg_5_3_reg,
1'b0 } ;
assign r1__read_BITS_13_TO_12___h655195 = csrf_fs_reg ;
assign r1__read_BITS_62_TO_14___h728903 = { r1__read__h614243, 2'd0 } ;
assign r1__read_BIT_20___h655891 = csrf_tw_reg ;
assign r1__read__h613048 = { r1__read__h613050, csrf_ie_vec_1 } ;
assign r1__read__h613050 = { r1__read__h613052, 2'b0 } ;
assign r1__read__h613052 = { r1__read__h613054, csrf_prev_ie_vec_0 } ;
assign r1__read__h613054 = { r1__read__h613056, csrf_prev_ie_vec_1 } ;
assign r1__read__h613056 = { r1__read__h613058, 2'b0 } ;
assign r1__read__h613058 = { r1__read__h613060, csrf_spp_reg } ;
assign r1__read__h613060 = { r1__read__h613062, 4'b0 } ;
assign r1__read__h613062 = { r1__read__h613064, csrf_fs_reg } ;
assign r1__read__h613064 = { r1__read__h613066, 2'd0 } ;
assign r1__read__h613066 = { r1__read__h613068, 1'b0 } ;
assign r1__read__h613068 = { r1__read__h613070, csrf_sum_reg } ;
assign r1__read__h613070 = { r1__read__h613072, csrf_mxr_reg } ;
assign r1__read__h613072 = { r1__read__h613074, 12'b0 } ;
assign r1__read__h613074 = { r1__read__h613076, 2'b10 } ;
assign r1__read__h613076 = { csrf_fs_reg == 2'b11, 29'b0 } ;
assign r1__read__h613452 =
{ r1__read__h613454, csrf_software_int_en_vec_1 } ;
assign r1__read__h613454 = { r1__read__h613456, 2'b0 } ;
assign r1__read__h613456 = { r1__read__h613458, 1'b0 } ;
assign r1__read__h613458 = { r1__read__h613460, csrf_timer_int_en_vec_1 } ;
assign r1__read__h613460 = { r1__read__h613462, 2'b0 } ;
assign r1__read__h613462 = { r1__read__h613464, 1'b0 } ;
assign r1__read__h613464 = { 54'b0, csrf_external_int_en_vec_1 } ;
assign r1__read__h613962 = { csrf_stvec_base_hi_reg, 1'b0 } ;
assign r1__read__h613967 = { r1__read__h613969, csrf_scounteren_tm_reg } ;
assign r1__read__h613969 = { 61'd0, csrf_scounteren_ir_reg } ;
assign r1__read__h613980 = { csrf_scause_interrupt_reg, 59'b0 } ;
assign r1__read__h613986 =
{ r1__read__h613988, csrf_software_int_pend_vec_1 } ;
assign r1__read__h613988 = { r1__read__h613990, 2'b0 } ;
assign r1__read__h613990 = { r1__read__h613992, 1'b0 } ;
assign r1__read__h613992 =
{ r1__read__h613994, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h613994 = { r1__read__h613996, 2'b0 } ;
assign r1__read__h613996 = { r1__read__h613998, 1'b0 } ;
assign r1__read__h613998 = { 54'b0, csrf_external_int_pend_vec_1 } ;
assign r1__read__h614196 = { vm_mode_reg__read__h614202, 16'd0 } ;
assign r1__read__h614219 = { r1__read__h614221, csrf_ie_vec_1 } ;
assign r1__read__h614221 = { r1__read__h614223, 1'b0 } ;
assign r1__read__h614223 = { r1__read__h614225, csrf_ie_vec_3 } ;
assign r1__read__h614225 = { r1__read__h614227, csrf_prev_ie_vec_0 } ;
assign r1__read__h614227 = { r1__read__h614229, csrf_prev_ie_vec_1 } ;
assign r1__read__h614229 = { r1__read__h614231, 1'b0 } ;
assign r1__read__h614231 = { r1__read__h614233, csrf_prev_ie_vec_3 } ;
assign r1__read__h614233 = { r1__read__h614235, csrf_spp_reg } ;
assign r1__read__h614235 = { r1__read__h614237, 2'b0 } ;
assign r1__read__h614237 = { r1__read__h614239, csrf_mpp_reg } ;
assign r1__read__h614239 =
{ r1__read_BITS_62_TO_14___h728903, csrf_fs_reg } ;
assign r1__read__h614243 = { r1__read__h614245, csrf_mprv_reg } ;
assign r1__read__h614245 = { r1__read__h614247, csrf_sum_reg } ;
assign r1__read__h614247 = { r1__read__h614249, csrf_mxr_reg } ;
assign r1__read__h614249 = { r1__read__h614251, csrf_tvm_reg } ;
assign r1__read__h614251 = { r1__read__h614253, csrf_tw_reg } ;
assign r1__read__h614253 = { r1__read__h614255, csrf_tsr_reg } ;
assign r1__read__h614255 = { r1__read__h614257, 9'b0 } ;
assign r1__read__h614257 = { r1__read__h614259, 2'b10 } ;
assign r1__read__h614259 = { r1__read__h614261, 2'b10 } ;
assign r1__read__h614261 = { csrf_fs_reg == 2'b11, 27'b0 } ;
assign r1__read__h614344 = { r1__read__h614346, 1'b0 } ;
assign r1__read__h614346 = { r1__read__h614348, csrf_medeleg_13_11_reg } ;
assign r1__read__h614348 = { r1__read__h614350, 1'b0 } ;
assign r1__read__h614350 = { 48'b0, csrf_medeleg_15_reg } ;
assign r1__read__h614361 = { r1__read__h614363, 1'b0 } ;
assign r1__read__h614363 = { r1__read__h614365, csrf_mideleg_5_3_reg } ;
assign r1__read__h614365 = { r1__read__h614367, 1'b0 } ;
assign r1__read__h614367 = { r1__read__h614369, csrf_mideleg_9_7_reg } ;
assign r1__read__h614369 = { r1__read__h614371, 1'b0 } ;
assign r1__read__h614371 = { 52'b0, csrf_mideleg_11_reg } ;
assign r1__read__h614385 =
{ r1__read__h614387, csrf_software_int_en_vec_1 } ;
assign r1__read__h614387 = { r1__read__h614389, 1'b0 } ;
assign r1__read__h614389 =
{ r1__read__h614391, csrf_software_int_en_vec_3 } ;
assign r1__read__h614391 = { r1__read__h614393, 1'b0 } ;
assign r1__read__h614393 = { r1__read__h614395, csrf_timer_int_en_vec_1 } ;
assign r1__read__h614395 = { r1__read__h614397, 1'b0 } ;
assign r1__read__h614397 = { r1__read__h614399, csrf_timer_int_en_vec_3 } ;
assign r1__read__h614399 = { r1__read__h614401, 1'b0 } ;
assign r1__read__h614401 =
{ r1__read__h614403, csrf_external_int_en_vec_1 } ;
assign r1__read__h614403 = { r1__read__h614405, 1'b0 } ;
assign r1__read__h614405 = { 52'b0, csrf_external_int_en_vec_3 } ;
assign r1__read__h614478 = { csrf_mtvec_base_hi_reg, 1'b0 } ;
assign r1__read__h614483 = { r1__read__h614485, csrf_mcounteren_tm_reg } ;
assign r1__read__h614485 = { 61'd0, csrf_mcounteren_ir_reg } ;
assign r1__read__h614496 = { csrf_mcause_interrupt_reg, 59'b0 } ;
assign r1__read__h614502 =
{ r1__read__h614504, csrf_software_int_pend_vec_1 } ;
assign r1__read__h614504 = { r1__read__h614506, 1'b0 } ;
assign r1__read__h614506 =
{ r1__read__h614508, csrf_software_int_pend_vec_3 } ;
assign r1__read__h614508 = { r1__read__h614510, 1'b0 } ;
assign r1__read__h614510 =
{ r1__read__h614512, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h614512 = { r1__read__h614514, 1'b0 } ;
assign r1__read__h614514 =
{ r1__read__h614516, csrf_timer_int_pend_vec_3 } ;
assign r1__read__h614516 = { r1__read__h614518, 1'b0 } ;
assign r1__read__h614518 =
{ r1__read__h614520, csrf_external_int_pend_vec_1 } ;
assign r1__read__h614520 = { r1__read__h614522, 1'b0 } ;
assign r1__read__h614522 = { 52'b0, csrf_external_int_pend_vec_3 } ;
assign r1__read__h614599 = { 4'd0, csrf_rg_tdata1_dmode } ;
assign rVal1__h481760 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign rVal2__h481761 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign r___1__h475906 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ;
assign regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941 =
regRenamingTable$RDY_rename_0_getRename &&
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 &&
(fetchStage$pipelines_0_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022 =
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3401_3492_OR_NOT__ETC___d14007) &&
_0_OR_NOT_fetchStage_pipelines_1_first__2766_BI_ETC___d14020 ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 =
regRenamingTable$rename_0_canRename &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13427 ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 =
regRenamingTable$rename_0_canRename &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_0_first__2757_BIT_68__ETC___d13477 ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d13493 =
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ||
!specTagManager$canClaim ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d13823 =
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13479 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d13970 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13968 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d14112 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d14118 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 &&
fetchStage$pipelines_0_first[199:195] != 5'd14 ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d14138 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 &&
(fetchStage$pipelines_0_first[191:189] == 3'd0 ||
fetchStage$pipelines_0_first[191:189] == 3'd2) ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d14146 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 &&
fetchStage$pipelines_0_first[191:189] != 3'd0 &&
fetchStage$pipelines_0_first[191:189] != 3'd2 ;
assign regRenamingTable_rename_0_canRename__3403_AND__ETC___d14294 =
regRenamingTable$rename_0_canRename &&
!checkForException___d13008[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 ;
assign regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13736 ;
assign regRenamingTable_rename_1_canRename__3530_AND__ETC___d13880 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13878 ;
assign regRenamingTable_rename_1_canRename__3530_AND__ETC___d13898 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2784_BIT_4_2785__ETC___d13896 ;
assign regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_1_first__2766_BIT_68__ETC___d14202 ;
assign regRenamingTable_rename_1_canRename__3530_AND__ETC___d14248 =
regRenamingTable_rename_1_canRename__3530_AND__ETC___d14204 &&
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) &&
(!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068 =
renameStage_rg_m_halt_req[4] ||
!fetchStage$pipelines_0_first[68] &&
(IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15]) ;
assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13299 =
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_N_ETC___d13068 ||
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 :
IF_checkForException_3008_BIT_4_3009_THEN_IF_c_ETC___d13159) ==
4'd3 ;
assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13759 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13756 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13799 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_1_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d13793 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
csrf_rg_dcsr_read__1720_BIT_2_3062_OR_NOT_fetc_ETC___d13498 ;
assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[0] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[1] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[2] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[3] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[4] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[5] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[6] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[7] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[8] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[9] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[10] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[11] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[12] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[13] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[14] ||
IF_IF_NOT_csrf_prv_reg_read__2787_EQ_3_2788_27_ETC___d12824[15] ;
assign renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13920 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d13008[4] ||
!rob$enqPort_0_canEnq ;
assign renaming_spec_bits__h685237 =
fetchStage$pipelines_0_canDeq ?
y_avValue_fst__h681632 :
specTagManager$currentSpecBits ;
assign res_data__h337868 = { 32'hFFFFFFFF, x__h337883 } ;
assign res_data__h337873 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ;
assign res_data__h383570 = { 32'hFFFFFFFF, x__h383585 } ;
assign res_data__h383575 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ;
assign res_data__h429265 = { 32'hFFFFFFFF, x__h429280 } ;
assign res_data__h429270 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ;
assign res_fflags__h337869 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5202,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5213,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5229,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5242,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5255 } ;
assign res_fflags__h383571 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6594,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6605,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6621,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6634,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6647 } ;
assign res_fflags__h429266 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7986,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7997,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8013,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8026,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8039 } ;
assign resp_addr__h291970 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ;
assign result__h364336 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4558[0] |
guard__h364331 } ;
assign result__h410033 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5950[0] |
guard__h410028 } ;
assign result__h455728 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7342[0] |
guard__h455723 } ;
assign result__h503481 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8653[0] |
guard__h503476 } ;
assign result__h542334 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10138[0] |
guard__h542329 } ;
assign result__h581638 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9368[0] |
guard__h581633 } ;
assign result__h646693 = w__h646688 & y__h646722 ;
assign result__h646744 = ~x__h646743 ;
assign rg_core_run_state_read__3058_EQ_2_3059_AND_NOT_ETC___d15716 =
rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs &&
!update_vm_info &&
fetchStage$iTlbIfc_flush_done &&
coreFix_memExe_dTlb$flush_done &&
!flush_caches ;
assign rg_tdata1__read__h612205 =
{ r1__read__h614599, csrf_rg_tdata1_data } ;
assign rob_RDY_deqPort_0_deq_data__4325_AND_rob_RDY_d_ETC___d14988 =
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
regRenamingTable$RDY_commit_0_commit &&
v_f_to_TV_0$FULL_N &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq &&
NOT_rob_deqPort_0_deq_data__4328_BITS_329_TO_3_ETC___d14983 ;
assign rob_RDY_enqPort_0_enq__2779_AND_regRenamingTab_ETC___d13309 =
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
coreFix_aluExe_0_rsAlu$RDY_enq) ;
assign rob_deqPort_0_deq_data__4328_BIT_166_4344_CONC_ETC___d14393 =
{ rob$deqPort_0_deq_data[166],
rob$deqPort_0_deq_data[166] ?
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 :
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 } ;
assign rob_deqPort_0_deq_data__4328_BIT_181_4403_CONC_ETC___d14494 =
{ rob$deqPort_0_deq_data[181],
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 } ;
assign robdeqPort_0_deq_data_BITS_95_TO_32__q245 =
rob$deqPort_0_deq_data[95:32] ;
assign rs1__h655326 =
(fetchStage$pipelines_0_first[88] &&
!fetchStage$pipelines_0_first[87]) ?
fetchStage$pipelines_0_first[86:82] :
5'd0 ;
assign satp_csr__read__h610078 = { r1__read__h614196, csrf_ppn_reg } ;
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 =
(sbCons$lazyLookup_2_get[2] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8250 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8267) &&
(sbCons$lazyLookup_2_get[1] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8274 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8291) ;
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8295 =
(sbCons$lazyLookup_2_get[3] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8217 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8243) &&
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8294 ;
assign sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1632 =
(sbCons$lazyLookup_3_get[3] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1579 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1605) &&
(sbCons$lazyLookup_3_get[2] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__549_AN_ETC___d1612 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1629) ;
assign sbIdx__h157150 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] :
coreFix_memExe_reqStQ_data_0_rl[65:64]) :
2'd0 ;
assign scause_csr__read__h609875 =
{ r1__read__h613980, csrf_scause_code_reg } ;
assign scounteren_csr__read__h609737 =
{ r1__read__h613967, csrf_scounteren_cy_reg } ;
assign sfd__h338479 = { value__h346706, 3'd0 } ;
assign sfd__h354287 =
{ 1'b0,
_theResult___fst_exp__h354195 != 8'd0,
sfdin__h354189[56:34] } +
25'd1 ;
assign sfd__h362869 =
{ 1'b0,
_theResult___fst_exp__h362851 != 8'd0,
_theResult___snd__h362802[56:34] } +
25'd1 ;
assign sfd__h372053 =
{ 1'b0,
_theResult___fst_exp__h371961 != 8'd0,
sfdin__h371955[56:34] } +
25'd1 ;
assign sfd__h380665 =
{ 1'b0,
_theResult___fst_exp__h380646 != 8'd0,
_theResult___snd__h380592[56:34] } +
25'd1 ;
assign sfd__h384181 = { value__h392403, 3'd0 } ;
assign sfd__h399984 =
{ 1'b0,
_theResult___fst_exp__h399892 != 8'd0,
sfdin__h399886[56:34] } +
25'd1 ;
assign sfd__h408566 =
{ 1'b0,
_theResult___fst_exp__h408548 != 8'd0,
_theResult___snd__h408499[56:34] } +
25'd1 ;
assign sfd__h417750 =
{ 1'b0,
_theResult___fst_exp__h417658 != 8'd0,
sfdin__h417652[56:34] } +
25'd1 ;
assign sfd__h426362 =
{ 1'b0,
_theResult___fst_exp__h426343 != 8'd0,
_theResult___snd__h426289[56:34] } +
25'd1 ;
assign sfd__h429876 = { value__h438098, 3'd0 } ;
assign sfd__h445679 =
{ 1'b0,
_theResult___fst_exp__h445587 != 8'd0,
sfdin__h445581[56:34] } +
25'd1 ;
assign sfd__h454261 =
{ 1'b0,
_theResult___fst_exp__h454243 != 8'd0,
_theResult___snd__h454194[56:34] } +
25'd1 ;
assign sfd__h463445 =
{ 1'b0,
_theResult___fst_exp__h463353 != 8'd0,
sfdin__h463347[56:34] } +
25'd1 ;
assign sfd__h472057 =
{ 1'b0,
_theResult___fst_exp__h472038 != 8'd0,
_theResult___snd__h471984[56:34] } +
25'd1 ;
assign sfd__h482501 = { value__h487084, 32'd0 } ;
assign sfd__h501545 =
{ 1'b0,
_theResult___fst_exp__h501527 != 11'd0,
_theResult___snd__h501478[56:5] } +
54'd1 ;
assign sfd__h511196 =
{ 1'b0,
_theResult___fst_exp__h511104 != 11'd0,
sfdin__h511098[56:5] } +
54'd1 ;
assign sfd__h519956 =
{ 1'b0,
_theResult___fst_exp__h519937 != 11'd0,
_theResult___snd__h519883[56:5] } +
54'd1 ;
assign sfd__h521495 = { value__h525937, 32'd0 } ;
assign sfd__h540398 =
{ 1'b0,
_theResult___fst_exp__h540380 != 11'd0,
_theResult___snd__h540331[56:5] } +
54'd1 ;
assign sfd__h550049 =
{ 1'b0,
_theResult___fst_exp__h549957 != 11'd0,
sfdin__h549951[56:5] } +
54'd1 ;
assign sfd__h558809 =
{ 1'b0,
_theResult___fst_exp__h558790 != 11'd0,
_theResult___snd__h558736[56:5] } +
54'd1 ;
assign sfd__h560799 = { value__h565241, 32'd0 } ;
assign sfd__h579702 =
{ 1'b0,
_theResult___fst_exp__h579684 != 11'd0,
_theResult___snd__h579635[56:5] } +
54'd1 ;
assign sfd__h589353 =
{ 1'b0,
_theResult___fst_exp__h589261 != 11'd0,
sfdin__h589255[56:5] } +
54'd1 ;
assign sfd__h598113 =
{ 1'b0,
_theResult___fst_exp__h598094 != 11'd0,
_theResult___snd__h598040[56:5] } +
54'd1 ;
assign sfdin__h354189 =
_theResult____h346084[56] ?
_theResult___snd__h354206 :
_theResult___snd__h354217 ;
assign sfdin__h371955 =
_theResult____h363723[56] ?
_theResult___snd__h371972 :
_theResult___snd__h371983 ;
assign sfdin__h399886 =
_theResult____h391783[56] ?
_theResult___snd__h399903 :
_theResult___snd__h399914 ;
assign sfdin__h417652 =
_theResult____h409420[56] ?
_theResult___snd__h417669 :
_theResult___snd__h417680 ;
assign sfdin__h445581 =
_theResult____h437478[56] ?
_theResult___snd__h445598 :
_theResult___snd__h445609 ;
assign sfdin__h463347 =
_theResult____h455115[56] ?
_theResult___snd__h463364 :
_theResult___snd__h463375 ;
assign sfdin__h511098 =
_theResult____h502868[56] ?
_theResult___snd__h511115 :
_theResult___snd__h511126 ;
assign sfdin__h549951 =
_theResult____h541721[56] ?
_theResult___snd__h549968 :
_theResult___snd__h549979 ;
assign sfdin__h589255 =
_theResult____h581025[56] ?
_theResult___snd__h589272 :
_theResult___snd__h589283 ;
assign shiftData__h181566 =
coreFix_memExe_regToExeQ$first[75:12] << x__h181698 ;
assign sie_csr__read__h609641 = { r1__read__h613452, 1'b0 } ;
assign sip_csr__read__h610015 = { r1__read__h613986, 1'b0 } ;
assign spec_bits__h688396 = specTagManager$currentSpecBits | y__h688409 ;
assign sstatus_csr__read__h609571 = { r1__read__h613048, csrf_ie_vec_0 } ;
assign stvec_csr__read__h609684 =
{ r1__read__h613962, csrf_stvec_mode_low_reg } ;
assign trap_val__h708464 =
commitStage_commitTrap[36] ? 64'd0 : trap_val__h709502 ;
assign tsr_val__h725552 = csrf_tsr_reg ;
assign tvm_val__h725554 = csrf_tvm_reg ;
assign upd__h3993 =
WILL_FIRE_RL_commitStage_doCommitSystemInst ?
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 :
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ;
assign upd__h5310 = n__read__h6759 + 64'd1 ;
assign upd__h6873 =
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign upd__h726048 =
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign v__h295940 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3031) ?
v__h296171 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ;
assign v__h296171 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP +
3'd1 ;
assign v__h299285 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3138) ?
v__h299803 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ;
assign v__h299803 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ;
assign v__h309799 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3309) ?
v__h310030 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ;
assign v__h310030 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ;
assign v__h313675 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3405) ?
v__h313906 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ;
assign v__h313906 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ;
assign v__h328276 =
(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3634) ?
v__h328507 :
coreFix_memExe_memRespLdQ_enqP ;
assign v__h328507 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ;
assign v__h331501 =
(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3728) ?
v__h331732 :
coreFix_memExe_forwardQ_enqP ;
assign v__h331732 = coreFix_memExe_forwardQ_enqP + 1'd1 ;
assign v__h603882 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ?
v__h603892 :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ;
assign v__h603892 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ;
assign v__h604527 = v__h603882 - 2'd1 ;
assign v__h607933 =
sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h608839 ;
assign v__h632816 =
sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h633569 ;
assign value_BIT_23___h494224 = f1_exp__h482139 != 8'd0 ;
assign value__h346706 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ;
assign value__h392403 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ;
assign value__h438098 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ;
assign value__h487084 = { 1'b0, value_BIT_23___h494224, f1_sfd__h482140 } ;
assign value__h525937 = { 1'b0, f2_exp__h521133 != 8'd0, f2_sfd__h521134 } ;
assign value__h565241 = { 1'b0, f3_exp__h560437 != 8'd0, f3_sfd__h560438 } ;
assign vm_mode_reg__read__h614202 = { csrf_vm_mode_sv39_reg, 3'b0 } ;
assign w__h646688 =
coreFix_globalSpecUpdate_correctSpecTag_0$whas ?
result__h646744 :
12'd4095 ;
assign x__h153724 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] :
coreFix_memExe_reqLdQ_data_0_rl[68:64]) :
5'd0 ;
assign x__h153730 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqLdQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h157271 = { 3'd0, sbIdx__h157150 } ;
assign x__h157277 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqStQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h160087 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h160091 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h161939 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h181475 =
sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180563 ;
assign x__h181476 =
sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h181169 ;
assign x__h181698 = { x__h183901[2:0], 3'b0 } ;
assign x__h18384 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[141:78] :
mmio_dataReqQ_enqReq_rl[141:78] ;
assign x__h183901 =
coreFix_memExe_regToExeQ$first[139:76] +
{ {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10[31]}},
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q10 } ;
assign x__h193678 =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ?
curData__h192915[63:32] :
curData__h192915[31:0] ;
assign x__h20922 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[63:0] :
mmio_dataReqQ_enqReq_rl[63:0] ;
assign x__h287278 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h287290 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h289144 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h302150 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ;
assign x__h337883 =
{ (_theResult___exp__h381215 != 8'd255 ||
_theResult___sfd__h381216 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5140,
out_f_exp__h381492,
out_f_sfd__h381493 } ;
assign x__h364433 =
sfd__h338479 << (x__h364466[11] ? 12'hAAA : x__h364466) ;
assign x__h364466 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4554 ;
assign x__h383585 =
{ (_theResult___exp__h426912 != 8'd255 ||
_theResult___sfd__h426913 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6532,
out_f_exp__h427189,
out_f_sfd__h427190 } ;
assign x__h410130 =
sfd__h384181 << (x__h410163[11] ? 12'hAAA : x__h410163) ;
assign x__h410163 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5946 ;
assign x__h429280 =
{ (_theResult___exp__h472607 != 8'd255 ||
_theResult___sfd__h472608 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7924,
out_f_exp__h472884,
out_f_sfd__h472885 } ;
assign x__h455825 =
sfd__h429876 << (x__h455858[11] ? 12'hAAA : x__h455858) ;
assign x__h455858 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7338 ;
assign x__h46291 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[141:78] :
mmio_cRqQ_enqReq_rl[141:78] ;
assign x__h481669 =
sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h478805 ;
assign x__h481670 =
sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h479413 ;
assign x__h481671 =
sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h480015 ;
assign x__h48827 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[63:0] :
mmio_cRqQ_enqReq_rl[63:0] ;
assign x__h503576 = sfd__h482501 << x__h503609 ;
assign x__h503609 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8649 ;
assign x__h542429 = sfd__h521495 << x__h542462 ;
assign x__h542462 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10134 ;
assign x__h581733 = sfd__h560799 << x__h581766 ;
assign x__h581766 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9364 ;
assign x__h603383 = a__h602947[63] ^ b__h602948[63] ;
assign x__h613033 = { csrf_frm_reg, csrf_fflags_reg } ;
assign x__h617230 =
coreFix_aluExe_1_dispToRegQ$first[131] ?
rVal1__h609049 :
v__h607933 ;
assign x__h617231 =
sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h615055 ;
assign x__h639739 =
coreFix_aluExe_0_dispToRegQ$first[131] ?
rVal1__h633777 :
v__h632816 ;
assign x__h639740 =
sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h637574 ;
assign x__h646692 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ;
assign x__h646743 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ;
assign x__h701397 =
(!rob$deqPort_0_deq_data[166] &&
(rob$deqPort_0_deq_data[165:162] == 4'd1 ||
rob$deqPort_0_deq_data[165:162] == 4'd12)) ?
rob$deqPort_0_deq_data[161:98] :
rob$deqPort_0_deq_data[95:32] ;
assign x__h711438 = { cause_code__h708463, 2'b0 } ;
assign x__h713649 =
{ csrf_fs_reg == 2'b11,
IF_csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_c_ETC___d14909 } ;
assign x__h713841 =
{ commitStage_commitTrap[36], 59'b0, cause_code__h708463 } ;
assign x__h721573 = { 1'b0, csrf_spp_reg } ;
assign x__h725432 =
{ csrf_fs_reg == 2'b11,
40'd5120,
csrf_tsr_reg,
csrf_tw_reg,
csrf_tvm_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_mprv_reg,
2'd0,
csrf_fs_reg,
IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15271 } ;
assign x__h728883 =
{ r1__read_BITS_62_TO_14___h728903,
2'b11,
csrf_mpp_reg,
2'b0,
csrf_spp_reg,
csrf_prev_ie_vec_3,
1'b0,
csrf_prev_ie_vec_1,
csrf_prev_ie_vec_0,
csrf_ie_vec_3,
1'b0,
csrf_ie_vec_1,
csrf_ie_vec_0 } ;
assign x__h732011 =
{ y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993[63:15],
2'b11,
y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993[12:0] } ;
assign x__h732759 =
NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ?
y_avValue_snd_snd_snd_fst__h732569 :
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 ;
assign x__h76236 = mmio_pRqQ_data_0[31:0] ;
assign x_addr__h314073 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ;
assign x_data__h66085 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[31:0] :
mmio_pRqQ_enqReq_rl[31:0] ;
assign x_data_imm__h676655 = fetchStage$pipelines_0_first[159:128] ;
assign x_data_imm__h692709 = fetchStage$pipelines_1_first[159:128] ;
assign x_decodeInfo_frm__h655010 = csrf_frm_reg ;
assign x_prv__h711506 =
csrf_prv_reg_read__2787_ULE_1_4685_AND_IF_comm_ETC___d14707 ?
2'd1 :
2'd3 ;
assign x_prv__h722029 =
(rob$deqPort_0_deq_data[329:325] == 5'd19) ?
x__h721573 :
csrf_mpp_reg ;
assign x_quotient__h475195 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
64'hFFFFFFFFFFFFFFFF :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ?
q___1__h475880 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ;
assign x_reg_ifc__read__h609480 = { 63'd0, csrf_stats_module_doStats } ;
assign x_remainder__h475196 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ?
r___1__h475906 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ;
assign y__h254802 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ;
assign y__h646722 = ~x__h646692 ;
assign y__h651653 =
{ 4'd15,
~csrf_mideleg_11_reg,
1'd1,
~csrf_mideleg_9_7_reg,
1'd1,
~csrf_mideleg_5_3_reg,
1'd1,
~csrf_mideleg_1_0_reg } ;
assign y__h688409 = 12'd1 << specTagManager$nextSpecTag ;
assign y__h729714 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_snd_snd_fst__h729737 :
64'd0 ;
assign y__h732518 =
NOT_rob_deqPort_0_canDeq__5303_5304_OR_rob_deq_ETC___d15645 ?
y_avValue_snd_snd_snd_snd_snd_fst__h732579 :
y__h729714 ;
assign y_avValue__h180563 =
NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1595 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1649 ;
assign y_avValue__h181169 =
NOT_coreFix_memExe_bypassWire_0_whas__568_574__ETC___d1622 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__568_5_ETC___d1660 ;
assign y_avValue__h478805 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8233 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8337 ;
assign y_avValue__h479413 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8260 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8348 ;
assign y_avValue__h480015 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8284 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8359 ;
assign y_avValue__h608839 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11369 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11775 ;
assign y_avValue__h615055 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1342_1_ETC___d11397 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__134_ETC___d11787 ;
assign y_avValue__h633569 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12229 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12449 ;
assign y_avValue__h637574 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2202_2_ETC___d12257 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__220_ETC___d12461 ;
assign y_avValue_fst__h681569 =
(fetchStage$pipelines_0_first[194:192] == 3'd1) ?
spec_bits__h688396 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h681598 =
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 ?
y_avValue_fst__h681569 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h681632 =
((fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429) ?
y_avValue_fst__h681598 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h729252 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[329:325] == 5'd0 ||
rob$deqPort_0_deq_data[329:325] == 5'd21 ||
rob$deqPort_0_deq_data[329:325] == 5'd17 ||
rob$deqPort_0_deq_data[329:325] == 5'd18 ||
rob$deqPort_0_deq_data[329:325] == 5'd13 ||
rob$deqPort_0_deq_data[329:325] == 5'd16 ||
rob$deqPort_0_deq_data[329:325] == 5'd15 ||
rob$deqPort_0_deq_data[329:325] == 5'd19 ||
rob$deqPort_0_deq_data[329:325] == 5'd20) ?
5'd0 :
rob$deqPort_0_deq_data[31:27] ;
assign y_avValue_fst__h732400 =
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 |
rob$deqPort_1_deq_data[31:27] ;
assign y_avValue_fst__h732432 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[329:325] == 5'd0 ||
rob$deqPort_1_deq_data[329:325] == 5'd21 ||
rob$deqPort_1_deq_data[329:325] == 5'd17 ||
rob$deqPort_1_deq_data[329:325] == 5'd18 ||
rob$deqPort_1_deq_data[329:325] == 5'd13 ||
rob$deqPort_1_deq_data[329:325] == 5'd16 ||
rob$deqPort_1_deq_data[329:325] == 5'd15 ||
rob$deqPort_1_deq_data[329:325] == 5'd19 ||
rob$deqPort_1_deq_data[329:325] == 5'd20) ?
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15651 :
y_avValue_fst__h732400 ;
assign y_avValue_new_pc__h711199 =
(csrf_stvec_mode_low_reg && commitStage_commitTrap[36]) ?
base__h711423 + { 58'd0, x__h711438 } :
base__h711423 ;
assign y_avValue_new_pc__h711385 =
(csrf_mtvec_mode_low_reg && commitStage_commitTrap[36]) ?
base__h711443 + { 58'd0, x__h711438 } :
base__h711443 ;
assign y_avValue_snd_snd_snd_fst__h729727 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[329:325] == 5'd0 ||
rob$deqPort_0_deq_data[329:325] == 5'd21 ||
rob$deqPort_0_deq_data[329:325] == 5'd17 ||
rob$deqPort_0_deq_data[329:325] == 5'd18 ||
rob$deqPort_0_deq_data[329:325] == 5'd13 ||
rob$deqPort_0_deq_data[329:325] == 5'd16 ||
rob$deqPort_0_deq_data[329:325] == 5'd15 ||
rob$deqPort_0_deq_data[329:325] == 5'd19 ||
rob$deqPort_0_deq_data[329:325] == 5'd20) ?
2'd0 :
2'd1 ;
assign y_avValue_snd_snd_snd_fst__h732569 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[329:325] == 5'd0 ||
rob$deqPort_1_deq_data[329:325] == 5'd21 ||
rob$deqPort_1_deq_data[329:325] == 5'd17 ||
rob$deqPort_1_deq_data[329:325] == 5'd18 ||
rob$deqPort_1_deq_data[329:325] == 5'd13 ||
rob$deqPort_1_deq_data[329:325] == 5'd16 ||
rob$deqPort_1_deq_data[329:325] == 5'd15 ||
rob$deqPort_1_deq_data[329:325] == 5'd19 ||
rob$deqPort_1_deq_data[329:325] == 5'd20) ?
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 :
y_avValue_snd_snd_snd_fst__h732605 ;
assign y_avValue_snd_snd_snd_fst__h732605 =
IF_rob_deqPort_0_canDeq__5303_THEN_IF_NOT_rob__ETC___d15670 +
2'd1 ;
assign y_avValue_snd_snd_snd_snd_snd_fst__h729737 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[329:325] == 5'd0 ||
rob$deqPort_0_deq_data[329:325] == 5'd21 ||
rob$deqPort_0_deq_data[329:325] == 5'd17 ||
rob$deqPort_0_deq_data[329:325] == 5'd18 ||
rob$deqPort_0_deq_data[329:325] == 5'd13 ||
rob$deqPort_0_deq_data[329:325] == 5'd16 ||
rob$deqPort_0_deq_data[329:325] == 5'd15 ||
rob$deqPort_0_deq_data[329:325] == 5'd19 ||
rob$deqPort_0_deq_data[329:325] == 5'd20) ?
64'd0 :
64'd1 ;
assign y_avValue_snd_snd_snd_snd_snd_fst__h732579 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[329:325] == 5'd0 ||
rob$deqPort_1_deq_data[329:325] == 5'd21 ||
rob$deqPort_1_deq_data[329:325] == 5'd17 ||
rob$deqPort_1_deq_data[329:325] == 5'd18 ||
rob$deqPort_1_deq_data[329:325] == 5'd13 ||
rob$deqPort_1_deq_data[329:325] == 5'd16 ||
rob$deqPort_1_deq_data[329:325] == 5'd15 ||
rob$deqPort_1_deq_data[329:325] == 5'd19 ||
rob$deqPort_1_deq_data[329:325] == 5'd20) ?
y__h729714 :
y_avValue_snd_snd_snd_snd_snd_fst__h732615 ;
assign y_avValue_snd_snd_snd_snd_snd_fst__h732615 = y__h729714 + 64'd1 ;
assign y_avValue_snd_snd_snd_snd_snd_snd_snd__h731993 = x__h728883 ;
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[475:464])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1 =
v_f_to_TV_1$D_OUT[475:464];
default: CASE_v_f_to_TV_1D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q1 =
12'd2303;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[461:458])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 =
v_f_to_TV_1$D_OUT[461:458];
default: CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q2 = 4'd15;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[461:458])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3 =
v_f_to_TV_1$D_OUT[461:458];
default: CASE_v_f_to_TV_1D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q3 = 4'd15;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[393:392])
2'd0, 2'd1:
CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4 =
v_f_to_TV_1$D_OUT[393:392];
default: CASE_v_f_to_TV_1D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q4 = 2'd2;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[475:464])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5 =
v_f_to_TV_0$D_OUT[475:464];
default: CASE_v_f_to_TV_0D_OUT_BITS_475_TO_464_1_v_f_t_ETC__q5 =
12'd2303;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[461:458])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 =
v_f_to_TV_0$D_OUT[461:458];
default: CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q6 = 4'd15;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[461:458])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7 =
v_f_to_TV_0$D_OUT[461:458];
default: CASE_v_f_to_TV_0D_OUT_BITS_461_TO_458_0_v_f_t_ETC__q7 = 4'd15;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[393:392])
2'd0, 2'd1:
CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8 =
v_f_to_TV_0$D_OUT[393:392];
default: CASE_v_f_to_TV_0D_OUT_BITS_393_TO_392_0_v_f_t_ETC__q8 = 2'd2;
endcase
end
always@(mmio_cRqQ_data_0)
begin
case (mmio_cRqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
mmio_cRqQ_data_0[77:72];
2'd3:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
{ 2'd3, mmio_cRqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87])
3'd0:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
x__h197125 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP)
3'd0:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
3'd1:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
3'd2:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
3'd3:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
3'd4:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
3'd5:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
3'd6:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
3'd7:
x__h285845 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
addr__h290066 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518];
1'd1:
addr__h290066 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91])
3'd0:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
curData__h192915 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[35:32])
4'd0, 4'd3: trap_val__h709502 = commitStage_commitTrap[164:101];
4'd2: trap_val__h709502 = { 32'd0, commitStage_commitTrap[31:0] };
default: trap_val__h709502 =
(commitStage_commitTrap[35:32] != 4'd8 &&
commitStage_commitTrap[35:32] != 4'd9 &&
commitStage_commitTrap[35:32] != 4'd11) ?
commitStage_commitTrap[100:37] :
64'd0;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
x__h291615 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0];
1'd1:
x__h291615 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0];
endcase
end
always@(f_csr_reqs$D_OUT or
fflags_csr__read__h609350 or
frm_csr__read__h609361 or
fcsr_csr__read__h609375 or
sstatus_csr__read__h609571 or
sie_csr__read__h609641 or
stvec_csr__read__h609684 or
scounteren_csr__read__h609737 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h609875 or
csrf_stval_csr or
sip_csr__read__h610015 or
satp_csr__read__h610078 or
mstatus_csr__read__h610221 or
medeleg_csr__read__h610369 or
mideleg_csr__read__h610464 or
mie_csr__read__h610588 or
mtvec_csr__read__h610670 or
mcounteren_csr__read__h610762 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h611017 or
csrf_mtval_csr or
mip_csr__read__h611250 or
csrf_rg_tselect or
rg_tdata1__read__h612205 or
csrf_rg_tdata2 or
csrf_rg_tdata3 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h609480 or
n__read__h611354 or n__read__h611545 or csrf_time_reg)
begin
case (f_csr_reqs$D_OUT[75:64])
12'd1: data_out__h736609 = fflags_csr__read__h609350;
12'd2: data_out__h736609 = frm_csr__read__h609361;
12'd3: data_out__h736609 = fcsr_csr__read__h609375;
12'd256: data_out__h736609 = sstatus_csr__read__h609571;
12'd260: data_out__h736609 = sie_csr__read__h609641;
12'd261: data_out__h736609 = stvec_csr__read__h609684;
12'd262: data_out__h736609 = scounteren_csr__read__h609737;
12'd320: data_out__h736609 = csrf_sscratch_csr;
12'd321: data_out__h736609 = csrf_sepc_csr;
12'd322: data_out__h736609 = scause_csr__read__h609875;
12'd323: data_out__h736609 = csrf_stval_csr;
12'd324: data_out__h736609 = sip_csr__read__h610015;
12'd384: data_out__h736609 = satp_csr__read__h610078;
12'd768: data_out__h736609 = mstatus_csr__read__h610221;
12'd769: data_out__h736609 = 64'h800000000014112D;
12'd770: data_out__h736609 = medeleg_csr__read__h610369;
12'd771: data_out__h736609 = mideleg_csr__read__h610464;
12'd772: data_out__h736609 = mie_csr__read__h610588;
12'd773: data_out__h736609 = mtvec_csr__read__h610670;
12'd774: data_out__h736609 = mcounteren_csr__read__h610762;
12'd832: data_out__h736609 = csrf_mscratch_csr;
12'd833: data_out__h736609 = csrf_mepc_csr;
12'd834: data_out__h736609 = mcause_csr__read__h611017;
12'd835: data_out__h736609 = csrf_mtval_csr;
12'd836: data_out__h736609 = mip_csr__read__h611250;
12'd1952: data_out__h736609 = csrf_rg_tselect;
12'd1953: data_out__h736609 = rg_tdata1__read__h612205;
12'd1954: data_out__h736609 = csrf_rg_tdata2;
12'd1955: data_out__h736609 = csrf_rg_tdata3;
12'd1968: data_out__h736609 = csrf_rg_dcsr;
12'd1969: data_out__h736609 = csrf_rg_dpc;
12'd1970: data_out__h736609 = csrf_rg_dscratch0;
12'd1971: data_out__h736609 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
data_out__h736609 = 64'd0;
12'd2049: data_out__h736609 = x_reg_ifc__read__h609480;
12'd2816, 12'd3072: data_out__h736609 = n__read__h611354;
12'd2818, 12'd3074: data_out__h736609 = n__read__h611545;
12'd3073: data_out__h736609 = csrf_time_reg;
default: data_out__h736609 = 64'b0;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
fflags_csr__read__h609350 or
frm_csr__read__h609361 or
fcsr_csr__read__h609375 or
sstatus_csr__read__h609571 or
sie_csr__read__h609641 or
stvec_csr__read__h609684 or
scounteren_csr__read__h609737 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h609875 or
csrf_stval_csr or
sip_csr__read__h610015 or
satp_csr__read__h610078 or
mstatus_csr__read__h610221 or
medeleg_csr__read__h610369 or
mideleg_csr__read__h610464 or
mie_csr__read__h610588 or
mtvec_csr__read__h610670 or
mcounteren_csr__read__h610762 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h611017 or
csrf_mtval_csr or
mip_csr__read__h611250 or
csrf_rg_tselect or
rg_tdata1__read__h612205 or
csrf_rg_tdata2 or
csrf_rg_tdata3 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h609480 or
n__read__h611354 or n__read__h611545 or csrf_time_reg)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1: rVal1__h609049 = fflags_csr__read__h609350;
12'd2: rVal1__h609049 = frm_csr__read__h609361;
12'd3: rVal1__h609049 = fcsr_csr__read__h609375;
12'd256: rVal1__h609049 = sstatus_csr__read__h609571;
12'd260: rVal1__h609049 = sie_csr__read__h609641;
12'd261: rVal1__h609049 = stvec_csr__read__h609684;
12'd262: rVal1__h609049 = scounteren_csr__read__h609737;
12'd320: rVal1__h609049 = csrf_sscratch_csr;
12'd321: rVal1__h609049 = csrf_sepc_csr;
12'd322: rVal1__h609049 = scause_csr__read__h609875;
12'd323: rVal1__h609049 = csrf_stval_csr;
12'd324: rVal1__h609049 = sip_csr__read__h610015;
12'd384: rVal1__h609049 = satp_csr__read__h610078;
12'd768: rVal1__h609049 = mstatus_csr__read__h610221;
12'd769: rVal1__h609049 = 64'h800000000014112D;
12'd770: rVal1__h609049 = medeleg_csr__read__h610369;
12'd771: rVal1__h609049 = mideleg_csr__read__h610464;
12'd772: rVal1__h609049 = mie_csr__read__h610588;
12'd773: rVal1__h609049 = mtvec_csr__read__h610670;
12'd774: rVal1__h609049 = mcounteren_csr__read__h610762;
12'd832: rVal1__h609049 = csrf_mscratch_csr;
12'd833: rVal1__h609049 = csrf_mepc_csr;
12'd834: rVal1__h609049 = mcause_csr__read__h611017;
12'd835: rVal1__h609049 = csrf_mtval_csr;
12'd836: rVal1__h609049 = mip_csr__read__h611250;
12'd1952: rVal1__h609049 = csrf_rg_tselect;
12'd1953: rVal1__h609049 = rg_tdata1__read__h612205;
12'd1954: rVal1__h609049 = csrf_rg_tdata2;
12'd1955: rVal1__h609049 = csrf_rg_tdata3;
12'd1968: rVal1__h609049 = csrf_rg_dcsr;
12'd1969: rVal1__h609049 = csrf_rg_dpc;
12'd1970: rVal1__h609049 = csrf_rg_dscratch0;
12'd1971: rVal1__h609049 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
rVal1__h609049 = 64'd0;
12'd2049: rVal1__h609049 = x_reg_ifc__read__h609480;
12'd2816, 12'd3072: rVal1__h609049 = n__read__h611354;
12'd2818, 12'd3074: rVal1__h609049 = n__read__h611545;
12'd3073: rVal1__h609049 = csrf_time_reg;
default: rVal1__h609049 = 64'b0;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
fflags_csr__read__h609350 or
frm_csr__read__h609361 or
fcsr_csr__read__h609375 or
sstatus_csr__read__h609571 or
sie_csr__read__h609641 or
stvec_csr__read__h609684 or
scounteren_csr__read__h609737 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h609875 or
csrf_stval_csr or
sip_csr__read__h610015 or
satp_csr__read__h610078 or
mstatus_csr__read__h610221 or
medeleg_csr__read__h610369 or
mideleg_csr__read__h610464 or
mie_csr__read__h610588 or
mtvec_csr__read__h610670 or
mcounteren_csr__read__h610762 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h611017 or
csrf_mtval_csr or
mip_csr__read__h611250 or
csrf_rg_tselect or
rg_tdata1__read__h612205 or
csrf_rg_tdata2 or
csrf_rg_tdata3 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h609480 or
n__read__h611354 or n__read__h611545 or csrf_time_reg)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1: rVal1__h633777 = fflags_csr__read__h609350;
12'd2: rVal1__h633777 = frm_csr__read__h609361;
12'd3: rVal1__h633777 = fcsr_csr__read__h609375;
12'd256: rVal1__h633777 = sstatus_csr__read__h609571;
12'd260: rVal1__h633777 = sie_csr__read__h609641;
12'd261: rVal1__h633777 = stvec_csr__read__h609684;
12'd262: rVal1__h633777 = scounteren_csr__read__h609737;
12'd320: rVal1__h633777 = csrf_sscratch_csr;
12'd321: rVal1__h633777 = csrf_sepc_csr;
12'd322: rVal1__h633777 = scause_csr__read__h609875;
12'd323: rVal1__h633777 = csrf_stval_csr;
12'd324: rVal1__h633777 = sip_csr__read__h610015;
12'd384: rVal1__h633777 = satp_csr__read__h610078;
12'd768: rVal1__h633777 = mstatus_csr__read__h610221;
12'd769: rVal1__h633777 = 64'h800000000014112D;
12'd770: rVal1__h633777 = medeleg_csr__read__h610369;
12'd771: rVal1__h633777 = mideleg_csr__read__h610464;
12'd772: rVal1__h633777 = mie_csr__read__h610588;
12'd773: rVal1__h633777 = mtvec_csr__read__h610670;
12'd774: rVal1__h633777 = mcounteren_csr__read__h610762;
12'd832: rVal1__h633777 = csrf_mscratch_csr;
12'd833: rVal1__h633777 = csrf_mepc_csr;
12'd834: rVal1__h633777 = mcause_csr__read__h611017;
12'd835: rVal1__h633777 = csrf_mtval_csr;
12'd836: rVal1__h633777 = mip_csr__read__h611250;
12'd1952: rVal1__h633777 = csrf_rg_tselect;
12'd1953: rVal1__h633777 = rg_tdata1__read__h612205;
12'd1954: rVal1__h633777 = csrf_rg_tdata2;
12'd1955: rVal1__h633777 = csrf_rg_tdata3;
12'd1968: rVal1__h633777 = csrf_rg_dcsr;
12'd1969: rVal1__h633777 = csrf_rg_dpc;
12'd1970: rVal1__h633777 = csrf_rg_dscratch0;
12'd1971: rVal1__h633777 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
rVal1__h633777 = 64'd0;
12'd2049: rVal1__h633777 = x_reg_ifc__read__h609480;
12'd2816, 12'd3072: rVal1__h633777 = n__read__h611354;
12'd2818, 12'd3074: rVal1__h633777 = n__read__h611545;
12'd3073: rVal1__h633777 = csrf_time_reg;
default: rVal1__h633777 = 64'b0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q13 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h346066 = 8'd255;
3'd2:
_theResult___fst_exp__h346066 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h346066 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h346066 = 8'd254;
default: _theResult___fst_exp__h346066 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h346067 = 23'd0;
3'd2:
_theResult___fst_sfd__h346067 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h346067 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h346067 = 23'd8388607;
default: _theResult___fst_sfd__h346067 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h391765 = 8'd255;
3'd2:
_theResult___fst_exp__h391765 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h391765 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h391765 = 8'd254;
default: _theResult___fst_exp__h391765 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h391766 = 23'd0;
3'd2:
_theResult___fst_sfd__h391766 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h391766 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h391766 = 23'd8388607;
default: _theResult___fst_sfd__h391766 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h437460 = 8'd255;
3'd2:
_theResult___fst_exp__h437460 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h437460 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h437460 = 8'd254;
default: _theResult___fst_exp__h437460 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h437461 = 23'd0;
3'd2:
_theResult___fst_sfd__h437461 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h437461 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h437461 = 23'd8388607;
default: _theResult___fst_sfd__h437461 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = 52'd0;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[35:32])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
i__h708478 = commitStage_commitTrap[35:32];
default: i__h708478 = 4'd15;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[35:32])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
i__h708638 = commitStage_commitTrap[35:32];
default: i__h708638 = 4'd15;
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
coreFix_memExe_respLrScAmoQ_data_0[31:0];
1'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
coreFix_memExe_respLrScAmoQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[15:0];
2'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[31:16];
2'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[47:32];
2'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[7:0];
3'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[15:8];
3'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[23:16];
3'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[31:24];
3'd4:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[39:32];
3'd5:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[47:40];
3'd6:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[55:48];
3'd7:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
mmio_dataRespQ_data_0[31:0];
1'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
mmio_dataRespQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[15:0];
2'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[31:16];
2'd2:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[47:32];
2'd3:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[7:0];
3'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[15:8];
3'd2:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[23:16];
3'd3:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[31:24];
3'd4:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[39:32];
3'd5:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[47:40];
3'd6:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[55:48];
3'd7:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[177:175])
3'd0, 3'd2:
CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 = 4'd4;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_177_TO__ETC__q20 = 4'd6;
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[181:178])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 =
coreFix_memExe_dTlb$procResp[181:178];
4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd10;
4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd11;
4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd12;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_181_TO__ETC__q21 = 4'd13;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2];
1'd1:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2875 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131];
endcase
end
always@(guard__h354803 or
_theResult___fst_exp__h362851 or
out_exp__h363296 or _theResult___exp__h363293)
begin
case (guard__h354803)
2'b0, 2'b01:
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 =
_theResult___fst_exp__h362851;
2'b10:
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 =
out_exp__h363296;
2'b11:
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 =
_theResult___exp__h363293;
endcase
end
always@(guard__h354803 or
_theResult___fst_exp__h362851 or _theResult___exp__h363293)
begin
case (guard__h354803)
2'b0:
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 =
_theResult___fst_exp__h362851;
2'b01, 2'b10, 2'b11:
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 =
_theResult___exp__h363293;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32 or
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534 or
_theResult___fst_exp__h362851)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h363371 =
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q32;
3'd1:
_theResult___fst_exp__h363371 =
CASE_guard54803_0b0_theResult___fst_exp62851_0_ETC__q33;
3'd2:
_theResult___fst_exp__h363371 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4532;
3'd3:
_theResult___fst_exp__h363371 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4534;
3'd4: _theResult___fst_exp__h363371 = _theResult___fst_exp__h362851;
default: _theResult___fst_exp__h363371 = 8'd0;
endcase
end
always@(guard__h346094 or
_theResult___fst_exp__h354195 or
out_exp__h354714 or _theResult___exp__h354711)
begin
case (guard__h346094)
2'b0, 2'b01:
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 =
_theResult___fst_exp__h354195;
2'b10:
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 =
out_exp__h354714;
2'b11:
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 =
_theResult___exp__h354711;
endcase
end
always@(guard__h346094 or
_theResult___fst_exp__h354195 or _theResult___exp__h354711)
begin
case (guard__h346094)
2'b0:
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 =
_theResult___fst_exp__h354195;
2'b01, 2'b10, 2'b11:
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 =
_theResult___exp__h354711;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34 or
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313 or
_theResult___fst_exp__h354195)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h354789 =
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q34;
3'd1:
_theResult___fst_exp__h354789 =
CASE_guard46094_0b0_theResult___fst_exp54195_0_ETC__q35;
3'd2:
_theResult___fst_exp__h354789 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4310;
3'd3:
_theResult___fst_exp__h354789 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4313;
3'd4: _theResult___fst_exp__h354789 = _theResult___fst_exp__h354195;
default: _theResult___fst_exp__h354789 = 8'd0;
endcase
end
always@(guard__h363733 or
_theResult___fst_exp__h371961 or
out_exp__h372480 or _theResult___exp__h372477)
begin
case (guard__h363733)
2'b0, 2'b01:
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 =
_theResult___fst_exp__h371961;
2'b10:
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 =
out_exp__h372480;
2'b11:
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 =
_theResult___exp__h372477;
endcase
end
always@(guard__h363733 or
_theResult___fst_exp__h371961 or _theResult___exp__h372477)
begin
case (guard__h363733)
2'b0:
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 =
_theResult___fst_exp__h371961;
2'b01, 2'b10, 2'b11:
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 =
_theResult___exp__h372477;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40 or
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859 or
_theResult___fst_exp__h371961)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h372555 =
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q40;
3'd1:
_theResult___fst_exp__h372555 =
CASE_guard63733_0b0_theResult___fst_exp71961_0_ETC__q41;
3'd2:
_theResult___fst_exp__h372555 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4857;
3'd3:
_theResult___fst_exp__h372555 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4859;
3'd4: _theResult___fst_exp__h372555 = _theResult___fst_exp__h371961;
default: _theResult___fst_exp__h372555 = 8'd0;
endcase
end
always@(guard__h372569 or
_theResult___fst_exp__h380646 or
out_exp__h381116 or _theResult___exp__h381113)
begin
case (guard__h372569)
2'b0, 2'b01:
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 =
_theResult___fst_exp__h380646;
2'b10:
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 =
out_exp__h381116;
2'b11:
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 =
_theResult___exp__h381113;
endcase
end
always@(guard__h372569 or
_theResult___fst_exp__h380646 or _theResult___exp__h381113)
begin
case (guard__h372569)
2'b0:
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 =
_theResult___fst_exp__h380646;
2'b01, 2'b10, 2'b11:
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 =
_theResult___exp__h381113;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45 or
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928 or
_theResult___fst_exp__h380646)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h381191 =
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q45;
3'd1:
_theResult___fst_exp__h381191 =
CASE_guard72569_0b0_theResult___fst_exp80646_0_ETC__q46;
3'd2:
_theResult___fst_exp__h381191 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4926;
3'd3:
_theResult___fst_exp__h381191 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4928;
3'd4: _theResult___fst_exp__h381191 = _theResult___fst_exp__h380646;
default: _theResult___fst_exp__h381191 = 8'd0;
endcase
end
always@(guard__h354803 or
_theResult___snd__h362802 or
out_sfd__h363297 or _theResult___sfd__h363294)
begin
case (guard__h354803)
2'b0, 2'b01:
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 =
_theResult___snd__h362802[56:34];
2'b10:
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 =
out_sfd__h363297;
2'b11:
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 =
_theResult___sfd__h363294;
endcase
end
always@(guard__h354803 or
_theResult___snd__h362802 or _theResult___sfd__h363294)
begin
case (guard__h354803)
2'b0:
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 =
_theResult___snd__h362802[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 =
_theResult___sfd__h363294;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47 or
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978 or
_theResult___snd__h362802)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h363372 =
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q47;
3'd1:
_theResult___fst_sfd__h363372 =
CASE_guard54803_0b0_theResult___snd62802_BITS__ETC__q48;
3'd2:
_theResult___fst_sfd__h363372 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4976;
3'd3:
_theResult___fst_sfd__h363372 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4978;
3'd4: _theResult___fst_sfd__h363372 = _theResult___snd__h362802[56:34];
default: _theResult___fst_sfd__h363372 = 23'd0;
endcase
end
always@(guard__h346094 or
sfdin__h354189 or out_sfd__h354715 or _theResult___sfd__h354712)
begin
case (guard__h346094)
2'b0, 2'b01:
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 =
sfdin__h354189[56:34];
2'b10:
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 =
out_sfd__h354715;
2'b11:
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 =
_theResult___sfd__h354712;
endcase
end
always@(guard__h346094 or sfdin__h354189 or _theResult___sfd__h354712)
begin
case (guard__h346094)
2'b0:
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 =
sfdin__h354189[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 =
_theResult___sfd__h354712;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49 or
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959 or
sfdin__h354189)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h354790 =
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q49;
3'd1:
_theResult___fst_sfd__h354790 =
CASE_guard46094_0b0_sfdin54189_BITS_56_TO_34_0_ETC__q50;
3'd2:
_theResult___fst_sfd__h354790 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4957;
3'd3:
_theResult___fst_sfd__h354790 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4959;
3'd4: _theResult___fst_sfd__h354790 = sfdin__h354189[56:34];
default: _theResult___fst_sfd__h354790 = 23'd0;
endcase
end
always@(guard__h363733 or
sfdin__h371955 or out_sfd__h372481 or _theResult___sfd__h372478)
begin
case (guard__h363733)
2'b0, 2'b01:
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 =
sfdin__h371955[56:34];
2'b10:
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 =
out_sfd__h372481;
2'b11:
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 =
_theResult___sfd__h372478;
endcase
end
always@(guard__h363733 or sfdin__h371955 or _theResult___sfd__h372478)
begin
case (guard__h363733)
2'b0:
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 =
sfdin__h371955[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 =
_theResult___sfd__h372478;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51 or
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005 or
sfdin__h371955)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h372556 =
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q51;
3'd1:
_theResult___fst_sfd__h372556 =
CASE_guard63733_0b0_sfdin71955_BITS_56_TO_34_0_ETC__q52;
3'd2:
_theResult___fst_sfd__h372556 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5003;
3'd3:
_theResult___fst_sfd__h372556 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5005;
3'd4: _theResult___fst_sfd__h372556 = sfdin__h371955[56:34];
default: _theResult___fst_sfd__h372556 = 23'd0;
endcase
end
always@(guard__h372569 or
_theResult___snd__h380592 or
out_sfd__h381117 or _theResult___sfd__h381114)
begin
case (guard__h372569)
2'b0, 2'b01:
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 =
_theResult___snd__h380592[56:34];
2'b10:
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 =
out_sfd__h381117;
2'b11:
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 =
_theResult___sfd__h381114;
endcase
end
always@(guard__h372569 or
_theResult___snd__h380592 or _theResult___sfd__h381114)
begin
case (guard__h372569)
2'b0:
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 =
_theResult___snd__h380592[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 =
_theResult___sfd__h381114;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53 or
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024 or
_theResult___snd__h380592)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h381192 =
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q53;
3'd1:
_theResult___fst_sfd__h381192 =
CASE_guard72569_0b0_theResult___snd80592_BITS__ETC__q54;
3'd2:
_theResult___fst_sfd__h381192 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5022;
3'd3:
_theResult___fst_sfd__h381192 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5024;
3'd4: _theResult___fst_sfd__h381192 = _theResult___snd__h380592[56:34];
default: _theResult___fst_sfd__h381192 = 23'd0;
endcase
end
always@(guard__h346094 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h346094)
2'b0, 2'b01, 2'b10:
CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 =
guard__h346094 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55 or
guard__h346094)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
CASE_guard46094_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q55;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
(guard__h346094 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h346094 == 2'b01 || guard__h346094 == 2'b10 ||
guard__h346094 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5110 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h346094 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h346094)
2'b0, 2'b01, 2'b10:
CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 =
guard__h346094 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or
guard__h346094)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
CASE_guard46094_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
(guard__h346094 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h346094 != 2'b01 && guard__h346094 != 2'b10 &&
guard__h346094 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5054 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h354803 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h354803)
2'b0, 2'b01, 2'b10:
CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 =
guard__h354803 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or
guard__h354803)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
CASE_guard54803_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
(guard__h354803 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h354803 == 2'b01 || guard__h354803 == 2'b10 ||
guard__h354803 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5117 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h354803 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h354803)
2'b0, 2'b01, 2'b10:
CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 =
guard__h354803 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or
guard__h354803)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
CASE_guard54803_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
(guard__h354803 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h354803 != 2'b01 && guard__h354803 != 2'b10 &&
guard__h354803 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h363733 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h363733)
2'b0, 2'b01, 2'b10:
CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 =
guard__h363733 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or
guard__h363733)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
CASE_guard63733_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
(guard__h363733 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h363733 == 2'b01 || guard__h363733 == 2'b10 ||
guard__h363733 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5127 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h363733 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h363733)
2'b0, 2'b01, 2'b10:
CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 =
guard__h363733 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or
guard__h363733)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
CASE_guard63733_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
(guard__h363733 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h363733 != 2'b01 && guard__h363733 != 2'b10 &&
guard__h363733 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5084 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h372569 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h372569)
2'b0, 2'b01, 2'b10:
CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 =
guard__h372569 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or
guard__h372569)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
CASE_guard72569_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
(guard__h372569 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h372569 == 2'b01 || guard__h372569 == 2'b10 ||
guard__h372569 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5134 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h372569 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h372569)
2'b0, 2'b01, 2'b10:
CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 =
guard__h372569 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or
guard__h372569)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
CASE_guard72569_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
(guard__h372569 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h372569 != 2'b01 && guard__h372569 != 2'b10 &&
guard__h372569 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5097 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5120 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5071 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h400500 or
_theResult___fst_exp__h408548 or
out_exp__h408993 or _theResult___exp__h408990)
begin
case (guard__h400500)
2'b0, 2'b01:
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 =
_theResult___fst_exp__h408548;
2'b10:
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 =
out_exp__h408993;
2'b11:
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 =
_theResult___exp__h408990;
endcase
end
always@(guard__h400500 or
_theResult___fst_exp__h408548 or _theResult___exp__h408990)
begin
case (guard__h400500)
2'b0:
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 =
_theResult___fst_exp__h408548;
2'b01, 2'b10, 2'b11:
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 =
_theResult___exp__h408990;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67 or
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926 or
_theResult___fst_exp__h408548)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h409068 =
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q67;
3'd1:
_theResult___fst_exp__h409068 =
CASE_guard00500_0b0_theResult___fst_exp08548_0_ETC__q68;
3'd2:
_theResult___fst_exp__h409068 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5924;
3'd3:
_theResult___fst_exp__h409068 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5926;
3'd4: _theResult___fst_exp__h409068 = _theResult___fst_exp__h408548;
default: _theResult___fst_exp__h409068 = 8'd0;
endcase
end
always@(guard__h391793 or
_theResult___fst_exp__h399892 or
out_exp__h400411 or _theResult___exp__h400408)
begin
case (guard__h391793)
2'b0, 2'b01:
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 =
_theResult___fst_exp__h399892;
2'b10:
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 =
out_exp__h400411;
2'b11:
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 =
_theResult___exp__h400408;
endcase
end
always@(guard__h391793 or
_theResult___fst_exp__h399892 or _theResult___exp__h400408)
begin
case (guard__h391793)
2'b0:
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 =
_theResult___fst_exp__h399892;
2'b01, 2'b10, 2'b11:
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 =
_theResult___exp__h400408;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69 or
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705 or
_theResult___fst_exp__h399892)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h400486 =
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q69;
3'd1:
_theResult___fst_exp__h400486 =
CASE_guard91793_0b0_theResult___fst_exp99892_0_ETC__q70;
3'd2:
_theResult___fst_exp__h400486 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5702;
3'd3:
_theResult___fst_exp__h400486 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5705;
3'd4: _theResult___fst_exp__h400486 = _theResult___fst_exp__h399892;
default: _theResult___fst_exp__h400486 = 8'd0;
endcase
end
always@(guard__h409430 or
_theResult___fst_exp__h417658 or
out_exp__h418177 or _theResult___exp__h418174)
begin
case (guard__h409430)
2'b0, 2'b01:
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 =
_theResult___fst_exp__h417658;
2'b10:
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 =
out_exp__h418177;
2'b11:
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 =
_theResult___exp__h418174;
endcase
end
always@(guard__h409430 or
_theResult___fst_exp__h417658 or _theResult___exp__h418174)
begin
case (guard__h409430)
2'b0:
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 =
_theResult___fst_exp__h417658;
2'b01, 2'b10, 2'b11:
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 =
_theResult___exp__h418174;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75 or
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251 or
_theResult___fst_exp__h417658)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h418252 =
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q75;
3'd1:
_theResult___fst_exp__h418252 =
CASE_guard09430_0b0_theResult___fst_exp17658_0_ETC__q76;
3'd2:
_theResult___fst_exp__h418252 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6249;
3'd3:
_theResult___fst_exp__h418252 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6251;
3'd4: _theResult___fst_exp__h418252 = _theResult___fst_exp__h417658;
default: _theResult___fst_exp__h418252 = 8'd0;
endcase
end
always@(guard__h418266 or
_theResult___fst_exp__h426343 or
out_exp__h426813 or _theResult___exp__h426810)
begin
case (guard__h418266)
2'b0, 2'b01:
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 =
_theResult___fst_exp__h426343;
2'b10:
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 =
out_exp__h426813;
2'b11:
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 =
_theResult___exp__h426810;
endcase
end
always@(guard__h418266 or
_theResult___fst_exp__h426343 or _theResult___exp__h426810)
begin
case (guard__h418266)
2'b0:
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 =
_theResult___fst_exp__h426343;
2'b01, 2'b10, 2'b11:
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 =
_theResult___exp__h426810;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80 or
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320 or
_theResult___fst_exp__h426343)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h426888 =
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q80;
3'd1:
_theResult___fst_exp__h426888 =
CASE_guard18266_0b0_theResult___fst_exp26343_0_ETC__q81;
3'd2:
_theResult___fst_exp__h426888 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6318;
3'd3:
_theResult___fst_exp__h426888 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6320;
3'd4: _theResult___fst_exp__h426888 = _theResult___fst_exp__h426343;
default: _theResult___fst_exp__h426888 = 8'd0;
endcase
end
always@(guard__h400500 or
_theResult___snd__h408499 or
out_sfd__h408994 or _theResult___sfd__h408991)
begin
case (guard__h400500)
2'b0, 2'b01:
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 =
_theResult___snd__h408499[56:34];
2'b10:
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 =
out_sfd__h408994;
2'b11:
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 =
_theResult___sfd__h408991;
endcase
end
always@(guard__h400500 or
_theResult___snd__h408499 or _theResult___sfd__h408991)
begin
case (guard__h400500)
2'b0:
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 =
_theResult___snd__h408499[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 =
_theResult___sfd__h408991;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82 or
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370 or
_theResult___snd__h408499)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h409069 =
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q82;
3'd1:
_theResult___fst_sfd__h409069 =
CASE_guard00500_0b0_theResult___snd08499_BITS__ETC__q83;
3'd2:
_theResult___fst_sfd__h409069 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6368;
3'd3:
_theResult___fst_sfd__h409069 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6370;
3'd4: _theResult___fst_sfd__h409069 = _theResult___snd__h408499[56:34];
default: _theResult___fst_sfd__h409069 = 23'd0;
endcase
end
always@(guard__h391793 or
sfdin__h399886 or out_sfd__h400412 or _theResult___sfd__h400409)
begin
case (guard__h391793)
2'b0, 2'b01:
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 =
sfdin__h399886[56:34];
2'b10:
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 =
out_sfd__h400412;
2'b11:
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 =
_theResult___sfd__h400409;
endcase
end
always@(guard__h391793 or sfdin__h399886 or _theResult___sfd__h400409)
begin
case (guard__h391793)
2'b0:
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 =
sfdin__h399886[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 =
_theResult___sfd__h400409;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84 or
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351 or
sfdin__h399886)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h400487 =
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q84;
3'd1:
_theResult___fst_sfd__h400487 =
CASE_guard91793_0b0_sfdin99886_BITS_56_TO_34_0_ETC__q85;
3'd2:
_theResult___fst_sfd__h400487 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6349;
3'd3:
_theResult___fst_sfd__h400487 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6351;
3'd4: _theResult___fst_sfd__h400487 = sfdin__h399886[56:34];
default: _theResult___fst_sfd__h400487 = 23'd0;
endcase
end
always@(guard__h409430 or
sfdin__h417652 or out_sfd__h418178 or _theResult___sfd__h418175)
begin
case (guard__h409430)
2'b0, 2'b01:
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 =
sfdin__h417652[56:34];
2'b10:
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 =
out_sfd__h418178;
2'b11:
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 =
_theResult___sfd__h418175;
endcase
end
always@(guard__h409430 or sfdin__h417652 or _theResult___sfd__h418175)
begin
case (guard__h409430)
2'b0:
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 =
sfdin__h417652[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 =
_theResult___sfd__h418175;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86 or
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397 or
sfdin__h417652)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h418253 =
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q86;
3'd1:
_theResult___fst_sfd__h418253 =
CASE_guard09430_0b0_sfdin17652_BITS_56_TO_34_0_ETC__q87;
3'd2:
_theResult___fst_sfd__h418253 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6395;
3'd3:
_theResult___fst_sfd__h418253 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6397;
3'd4: _theResult___fst_sfd__h418253 = sfdin__h417652[56:34];
default: _theResult___fst_sfd__h418253 = 23'd0;
endcase
end
always@(guard__h418266 or
_theResult___snd__h426289 or
out_sfd__h426814 or _theResult___sfd__h426811)
begin
case (guard__h418266)
2'b0, 2'b01:
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 =
_theResult___snd__h426289[56:34];
2'b10:
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 =
out_sfd__h426814;
2'b11:
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 =
_theResult___sfd__h426811;
endcase
end
always@(guard__h418266 or
_theResult___snd__h426289 or _theResult___sfd__h426811)
begin
case (guard__h418266)
2'b0:
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 =
_theResult___snd__h426289[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 =
_theResult___sfd__h426811;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88 or
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416 or
_theResult___snd__h426289)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h426889 =
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q88;
3'd1:
_theResult___fst_sfd__h426889 =
CASE_guard18266_0b0_theResult___snd26289_BITS__ETC__q89;
3'd2:
_theResult___fst_sfd__h426889 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6414;
3'd3:
_theResult___fst_sfd__h426889 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6416;
3'd4: _theResult___fst_sfd__h426889 = _theResult___snd__h426289[56:34];
default: _theResult___fst_sfd__h426889 = 23'd0;
endcase
end
always@(guard__h391793 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h391793)
2'b0, 2'b01, 2'b10:
CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 =
guard__h391793 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or
guard__h391793)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
CASE_guard91793_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
(guard__h391793 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h391793 == 2'b01 || guard__h391793 == 2'b10 ||
guard__h391793 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6502 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h391793 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h391793)
2'b0, 2'b01, 2'b10:
CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 =
guard__h391793 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or
guard__h391793)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
CASE_guard91793_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
(guard__h391793 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h391793 != 2'b01 && guard__h391793 != 2'b10 &&
guard__h391793 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6446 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h400500 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h400500)
2'b0, 2'b01, 2'b10:
CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 =
guard__h400500 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or
guard__h400500)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
CASE_guard00500_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
(guard__h400500 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h400500 == 2'b01 || guard__h400500 == 2'b10 ||
guard__h400500 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6509 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h400500 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h400500)
2'b0, 2'b01, 2'b10:
CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 =
guard__h400500 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or
guard__h400500)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
CASE_guard00500_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
(guard__h400500 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h400500 != 2'b01 && guard__h400500 != 2'b10 &&
guard__h400500 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h409430 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h409430)
2'b0, 2'b01, 2'b10:
CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 =
guard__h409430 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or
guard__h409430)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
CASE_guard09430_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
(guard__h409430 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h409430 == 2'b01 || guard__h409430 == 2'b10 ||
guard__h409430 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6519 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h409430 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h409430)
2'b0, 2'b01, 2'b10:
CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 =
guard__h409430 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or
guard__h409430)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
CASE_guard09430_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
(guard__h409430 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h409430 != 2'b01 && guard__h409430 != 2'b10 &&
guard__h409430 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6476 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h418266 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h418266)
2'b0, 2'b01, 2'b10:
CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 =
guard__h418266 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or
guard__h418266)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
CASE_guard18266_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
(guard__h418266 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h418266 == 2'b01 || guard__h418266 == 2'b10 ||
guard__h418266 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6526 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h418266 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h418266)
2'b0, 2'b01, 2'b10:
CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 =
guard__h418266 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or
guard__h418266)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
CASE_guard18266_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
(guard__h418266 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h418266 != 2'b01 && guard__h418266 != 2'b10 &&
guard__h418266 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6489 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6512 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6463 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h446195 or
_theResult___fst_exp__h454243 or
out_exp__h454688 or _theResult___exp__h454685)
begin
case (guard__h446195)
2'b0, 2'b01:
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 =
_theResult___fst_exp__h454243;
2'b10:
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 =
out_exp__h454688;
2'b11:
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 =
_theResult___exp__h454685;
endcase
end
always@(guard__h446195 or
_theResult___fst_exp__h454243 or _theResult___exp__h454685)
begin
case (guard__h446195)
2'b0:
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 =
_theResult___fst_exp__h454243;
2'b01, 2'b10, 2'b11:
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 =
_theResult___exp__h454685;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102 or
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318 or
_theResult___fst_exp__h454243)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h454763 =
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q102;
3'd1:
_theResult___fst_exp__h454763 =
CASE_guard46195_0b0_theResult___fst_exp54243_0_ETC__q103;
3'd2:
_theResult___fst_exp__h454763 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7316;
3'd3:
_theResult___fst_exp__h454763 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7318;
3'd4: _theResult___fst_exp__h454763 = _theResult___fst_exp__h454243;
default: _theResult___fst_exp__h454763 = 8'd0;
endcase
end
always@(guard__h437488 or
_theResult___fst_exp__h445587 or
out_exp__h446106 or _theResult___exp__h446103)
begin
case (guard__h437488)
2'b0, 2'b01:
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 =
_theResult___fst_exp__h445587;
2'b10:
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 =
out_exp__h446106;
2'b11:
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 =
_theResult___exp__h446103;
endcase
end
always@(guard__h437488 or
_theResult___fst_exp__h445587 or _theResult___exp__h446103)
begin
case (guard__h437488)
2'b0:
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 =
_theResult___fst_exp__h445587;
2'b01, 2'b10, 2'b11:
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 =
_theResult___exp__h446103;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104 or
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097 or
_theResult___fst_exp__h445587)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h446181 =
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q104;
3'd1:
_theResult___fst_exp__h446181 =
CASE_guard37488_0b0_theResult___fst_exp45587_0_ETC__q105;
3'd2:
_theResult___fst_exp__h446181 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7094;
3'd3:
_theResult___fst_exp__h446181 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7097;
3'd4: _theResult___fst_exp__h446181 = _theResult___fst_exp__h445587;
default: _theResult___fst_exp__h446181 = 8'd0;
endcase
end
always@(guard__h455125 or
_theResult___fst_exp__h463353 or
out_exp__h463872 or _theResult___exp__h463869)
begin
case (guard__h455125)
2'b0, 2'b01:
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 =
_theResult___fst_exp__h463353;
2'b10:
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 =
out_exp__h463872;
2'b11:
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 =
_theResult___exp__h463869;
endcase
end
always@(guard__h455125 or
_theResult___fst_exp__h463353 or _theResult___exp__h463869)
begin
case (guard__h455125)
2'b0:
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 =
_theResult___fst_exp__h463353;
2'b01, 2'b10, 2'b11:
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 =
_theResult___exp__h463869;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110 or
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643 or
_theResult___fst_exp__h463353)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h463947 =
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q110;
3'd1:
_theResult___fst_exp__h463947 =
CASE_guard55125_0b0_theResult___fst_exp63353_0_ETC__q111;
3'd2:
_theResult___fst_exp__h463947 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7641;
3'd3:
_theResult___fst_exp__h463947 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7643;
3'd4: _theResult___fst_exp__h463947 = _theResult___fst_exp__h463353;
default: _theResult___fst_exp__h463947 = 8'd0;
endcase
end
always@(guard__h463961 or
_theResult___fst_exp__h472038 or
out_exp__h472508 or _theResult___exp__h472505)
begin
case (guard__h463961)
2'b0, 2'b01:
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 =
_theResult___fst_exp__h472038;
2'b10:
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 =
out_exp__h472508;
2'b11:
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 =
_theResult___exp__h472505;
endcase
end
always@(guard__h463961 or
_theResult___fst_exp__h472038 or _theResult___exp__h472505)
begin
case (guard__h463961)
2'b0:
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 =
_theResult___fst_exp__h472038;
2'b01, 2'b10, 2'b11:
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 =
_theResult___exp__h472505;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115 or
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712 or
_theResult___fst_exp__h472038)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h472583 =
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q115;
3'd1:
_theResult___fst_exp__h472583 =
CASE_guard63961_0b0_theResult___fst_exp72038_0_ETC__q116;
3'd2:
_theResult___fst_exp__h472583 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7710;
3'd3:
_theResult___fst_exp__h472583 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7712;
3'd4: _theResult___fst_exp__h472583 = _theResult___fst_exp__h472038;
default: _theResult___fst_exp__h472583 = 8'd0;
endcase
end
always@(guard__h446195 or
_theResult___snd__h454194 or
out_sfd__h454689 or _theResult___sfd__h454686)
begin
case (guard__h446195)
2'b0, 2'b01:
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 =
_theResult___snd__h454194[56:34];
2'b10:
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 =
out_sfd__h454689;
2'b11:
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 =
_theResult___sfd__h454686;
endcase
end
always@(guard__h446195 or
_theResult___snd__h454194 or _theResult___sfd__h454686)
begin
case (guard__h446195)
2'b0:
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 =
_theResult___snd__h454194[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 =
_theResult___sfd__h454686;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117 or
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762 or
_theResult___snd__h454194)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h454764 =
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q117;
3'd1:
_theResult___fst_sfd__h454764 =
CASE_guard46195_0b0_theResult___snd54194_BITS__ETC__q118;
3'd2:
_theResult___fst_sfd__h454764 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7760;
3'd3:
_theResult___fst_sfd__h454764 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7762;
3'd4: _theResult___fst_sfd__h454764 = _theResult___snd__h454194[56:34];
default: _theResult___fst_sfd__h454764 = 23'd0;
endcase
end
always@(guard__h437488 or
sfdin__h445581 or out_sfd__h446107 or _theResult___sfd__h446104)
begin
case (guard__h437488)
2'b0, 2'b01:
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 =
sfdin__h445581[56:34];
2'b10:
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 =
out_sfd__h446107;
2'b11:
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 =
_theResult___sfd__h446104;
endcase
end
always@(guard__h437488 or sfdin__h445581 or _theResult___sfd__h446104)
begin
case (guard__h437488)
2'b0:
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 =
sfdin__h445581[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 =
_theResult___sfd__h446104;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119 or
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743 or
sfdin__h445581)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h446182 =
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q119;
3'd1:
_theResult___fst_sfd__h446182 =
CASE_guard37488_0b0_sfdin45581_BITS_56_TO_34_0_ETC__q120;
3'd2:
_theResult___fst_sfd__h446182 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7741;
3'd3:
_theResult___fst_sfd__h446182 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7743;
3'd4: _theResult___fst_sfd__h446182 = sfdin__h445581[56:34];
default: _theResult___fst_sfd__h446182 = 23'd0;
endcase
end
always@(guard__h455125 or
sfdin__h463347 or out_sfd__h463873 or _theResult___sfd__h463870)
begin
case (guard__h455125)
2'b0, 2'b01:
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 =
sfdin__h463347[56:34];
2'b10:
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 =
out_sfd__h463873;
2'b11:
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 =
_theResult___sfd__h463870;
endcase
end
always@(guard__h455125 or sfdin__h463347 or _theResult___sfd__h463870)
begin
case (guard__h455125)
2'b0:
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 =
sfdin__h463347[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 =
_theResult___sfd__h463870;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121 or
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789 or
sfdin__h463347)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h463948 =
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q121;
3'd1:
_theResult___fst_sfd__h463948 =
CASE_guard55125_0b0_sfdin63347_BITS_56_TO_34_0_ETC__q122;
3'd2:
_theResult___fst_sfd__h463948 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7787;
3'd3:
_theResult___fst_sfd__h463948 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7789;
3'd4: _theResult___fst_sfd__h463948 = sfdin__h463347[56:34];
default: _theResult___fst_sfd__h463948 = 23'd0;
endcase
end
always@(guard__h437488 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h437488)
2'b0, 2'b01, 2'b10:
CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 =
guard__h437488 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123 or
guard__h437488)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
CASE_guard37488_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q123;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
(guard__h437488 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h437488 == 2'b01 || guard__h437488 == 2'b10 ||
guard__h437488 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7894 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h463961 or
_theResult___snd__h471984 or
out_sfd__h472509 or _theResult___sfd__h472506)
begin
case (guard__h463961)
2'b0, 2'b01:
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 =
_theResult___snd__h471984[56:34];
2'b10:
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 =
out_sfd__h472509;
2'b11:
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 =
_theResult___sfd__h472506;
endcase
end
always@(guard__h463961 or
_theResult___snd__h471984 or _theResult___sfd__h472506)
begin
case (guard__h463961)
2'b0:
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 =
_theResult___snd__h471984[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 =
_theResult___sfd__h472506;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124 or
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808 or
_theResult___snd__h471984)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h472584 =
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q124;
3'd1:
_theResult___fst_sfd__h472584 =
CASE_guard63961_0b0_theResult___snd71984_BITS__ETC__q125;
3'd2:
_theResult___fst_sfd__h472584 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7806;
3'd3:
_theResult___fst_sfd__h472584 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7808;
3'd4: _theResult___fst_sfd__h472584 = _theResult___snd__h471984[56:34];
default: _theResult___fst_sfd__h472584 = 23'd0;
endcase
end
always@(guard__h437488 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h437488)
2'b0, 2'b01, 2'b10:
CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 =
guard__h437488 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126 or
guard__h437488)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
CASE_guard37488_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q126;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
(guard__h437488 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h437488 != 2'b01 && guard__h437488 != 2'b10 &&
guard__h437488 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7838 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h446195 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h446195)
2'b0, 2'b01, 2'b10:
CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 =
guard__h446195 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or
guard__h446195)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
CASE_guard46195_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
(guard__h446195 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h446195 == 2'b01 || guard__h446195 == 2'b10 ||
guard__h446195 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7901 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h446195 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h446195)
2'b0, 2'b01, 2'b10:
CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 =
guard__h446195 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or
guard__h446195)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
CASE_guard46195_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
(guard__h446195 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h446195 != 2'b01 && guard__h446195 != 2'b10 &&
guard__h446195 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h455125 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h455125)
2'b0, 2'b01, 2'b10:
CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 =
guard__h455125 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or
guard__h455125)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
CASE_guard55125_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
(guard__h455125 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h455125 == 2'b01 || guard__h455125 == 2'b10 ||
guard__h455125 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7911 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h455125 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h455125)
2'b0, 2'b01, 2'b10:
CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 =
guard__h455125 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130 or
guard__h455125)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
CASE_guard55125_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q130;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
(guard__h455125 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h455125 != 2'b01 && guard__h455125 != 2'b10 &&
guard__h455125 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7868 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h463961 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h463961)
2'b0, 2'b01, 2'b10:
CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 =
guard__h463961 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131 or
guard__h463961)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
CASE_guard63961_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q131;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
(guard__h463961 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h463961 == 2'b01 || guard__h463961 == 2'b10 ||
guard__h463961 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7918 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h463961 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h463961)
2'b0, 2'b01, 2'b10:
CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 =
guard__h463961 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or
guard__h463961)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
CASE_guard63961_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
(guard__h463961 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h463961 != 2'b01 && guard__h463961 != 2'b10 &&
guard__h463961 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7881 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7904 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7855 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8396 =
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
endcase
end
always@(guard__h493566 or
_theResult___fst_exp__h501527 or _theResult___exp__h502182)
begin
case (guard__h493566)
2'b0:
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143 =
_theResult___fst_exp__h501527;
2'b01, 2'b10, 2'b11:
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143 =
_theResult___exp__h502182;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h501527 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013 or
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
_theResult___fst_exp__h501527;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9015;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9013;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q143;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9019 =
11'd0;
endcase
end
always@(guard__h493566 or
_theResult___fst_exp__h501527 or
out_exp__h502185 or _theResult___exp__h502182)
begin
case (guard__h493566)
2'b0, 2'b01:
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 =
_theResult___fst_exp__h501527;
2'b10:
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 =
out_exp__h502185;
2'b11:
CASE_guard93566_0b0_theResult___fst_exp01527_0_ETC__q144 =
_theResult___exp__h502182;
endcase
end
always@(guard__h502878 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h502878)
2'b0, 2'b01, 2'b10:
CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard02878_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
guard__h502878 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h502878)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
(guard__h502878 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h502878 == 2'b01 || guard__h502878 == 2'b10 ||
guard__h502878 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h493566 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h493566)
2'b0, 2'b01, 2'b10:
CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard93566_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
guard__h493566 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h493566)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
(guard__h493566 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h493566 == 2'b01 || guard__h493566 == 2'b10 ||
guard__h493566 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h511947 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h511947)
2'b0, 2'b01, 2'b10:
CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard11947_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
guard__h511947 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h511947)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
(guard__h511947 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h511947 == 2'b01 || guard__h511947 == 2'b10 ||
guard__h511947 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h571723 or
_theResult___fst_exp__h579684 or _theResult___exp__h580339)
begin
case (guard__h571723)
2'b0:
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160 =
_theResult___fst_exp__h579684;
2'b01, 2'b10, 2'b11:
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160 =
_theResult___exp__h580339;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h579684 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728 or
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
_theResult___fst_exp__h579684;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9730;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9728;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q160;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9734 =
11'd0;
endcase
end
always@(guard__h571723 or
_theResult___fst_exp__h579684 or
out_exp__h580342 or _theResult___exp__h580339)
begin
case (guard__h571723)
2'b0, 2'b01:
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 =
_theResult___fst_exp__h579684;
2'b10:
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 =
out_exp__h580342;
2'b11:
CASE_guard71723_0b0_theResult___fst_exp79684_0_ETC__q161 =
_theResult___exp__h580339;
endcase
end
always@(guard__h571723 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h571723)
2'b0, 2'b01, 2'b10:
CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard71723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
guard__h571723 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571723)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
(guard__h571723 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h571723 == 2'b01 || guard__h571723 == 2'b10 ||
guard__h571723 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h581035 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h581035)
2'b0, 2'b01, 2'b10:
CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard81035_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
guard__h581035 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581035)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
(guard__h581035 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h581035 == 2'b01 || guard__h581035 == 2'b10 ||
guard__h581035 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h590104 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h590104)
2'b0, 2'b01, 2'b10:
CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard90104_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
guard__h590104 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590104)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
(guard__h590104 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h590104 == 2'b01 || guard__h590104 == 2'b10 ||
guard__h590104 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h581035 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h581035)
2'b0, 2'b01, 2'b10:
CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard81035_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
guard__h581035 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h581035)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
(guard__h581035 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h581035 != 2'b01 && guard__h581035 != 2'b10 &&
guard__h581035 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h590104 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h590104)
2'b0, 2'b01, 2'b10:
CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard90104_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
guard__h590104 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h590104)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
(guard__h590104 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h590104 != 2'b01 && guard__h590104 != 2'b10 &&
guard__h590104 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h571723 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h571723)
2'b0, 2'b01, 2'b10:
CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard71723_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
guard__h571723 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h571723)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
(guard__h571723 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h571723 != 2'b01 && guard__h571723 != 2'b10 &&
guard__h571723 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h532419 or
_theResult___fst_exp__h540380 or _theResult___exp__h541035)
begin
case (guard__h532419)
2'b0:
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183 =
_theResult___fst_exp__h540380;
2'b01, 2'b10, 2'b11:
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183 =
_theResult___exp__h541035;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h540380 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498 or
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
_theResult___fst_exp__h540380;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10500;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10498;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q183;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10504 =
11'd0;
endcase
end
always@(guard__h532419 or
_theResult___fst_exp__h540380 or
out_exp__h541038 or _theResult___exp__h541035)
begin
case (guard__h532419)
2'b0, 2'b01:
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 =
_theResult___fst_exp__h540380;
2'b10:
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 =
out_exp__h541038;
2'b11:
CASE_guard32419_0b0_theResult___fst_exp40380_0_ETC__q184 =
_theResult___exp__h541035;
endcase
end
always@(guard__h541731 or
_theResult___fst_exp__h549957 or _theResult___exp__h550686)
begin
case (guard__h541731)
2'b0:
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185 =
_theResult___fst_exp__h549957;
2'b01, 2'b10, 2'b11:
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185 =
_theResult___exp__h550686;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h549957 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536 or
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
_theResult___fst_exp__h549957;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10538;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10536;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q185;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10542 =
11'd0;
endcase
end
always@(guard__h541731 or
_theResult___fst_exp__h549957 or
out_exp__h550689 or _theResult___exp__h550686)
begin
case (guard__h541731)
2'b0, 2'b01:
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 =
_theResult___fst_exp__h549957;
2'b10:
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 =
out_exp__h550689;
2'b11:
CASE_guard41731_0b0_theResult___fst_exp49957_0_ETC__q186 =
_theResult___exp__h550686;
endcase
end
always@(guard__h550800 or
_theResult___fst_exp__h558790 or _theResult___exp__h559470)
begin
case (guard__h550800)
2'b0:
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187 =
_theResult___fst_exp__h558790;
2'b01, 2'b10, 2'b11:
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187 =
_theResult___exp__h559470;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h558790 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567 or
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
_theResult___fst_exp__h558790;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10569;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10567;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q187;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10573 =
11'd0;
endcase
end
always@(guard__h550800 or
_theResult___fst_exp__h558790 or
out_exp__h559473 or _theResult___exp__h559470)
begin
case (guard__h550800)
2'b0, 2'b01:
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 =
_theResult___fst_exp__h558790;
2'b10:
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 =
out_exp__h559473;
2'b11:
CASE_guard50800_0b0_theResult___fst_exp58790_0_ETC__q188 =
_theResult___exp__h559470;
endcase
end
always@(guard__h581035 or
_theResult___fst_exp__h589261 or _theResult___exp__h589990)
begin
case (guard__h581035)
2'b0:
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189 =
_theResult___fst_exp__h589261;
2'b01, 2'b10, 2'b11:
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189 =
_theResult___exp__h589990;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h589261 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766 or
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
_theResult___fst_exp__h589261;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9768;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9766;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q189;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9772 =
11'd0;
endcase
end
always@(guard__h581035 or
_theResult___fst_exp__h589261 or
out_exp__h589993 or _theResult___exp__h589990)
begin
case (guard__h581035)
2'b0, 2'b01:
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 =
_theResult___fst_exp__h589261;
2'b10:
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 =
out_exp__h589993;
2'b11:
CASE_guard81035_0b0_theResult___fst_exp89261_0_ETC__q190 =
_theResult___exp__h589990;
endcase
end
always@(guard__h590104 or
_theResult___fst_exp__h598094 or _theResult___exp__h598774)
begin
case (guard__h590104)
2'b0:
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191 =
_theResult___fst_exp__h598094;
2'b01, 2'b10, 2'b11:
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191 =
_theResult___exp__h598774;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h598094 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797 or
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
_theResult___fst_exp__h598094;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9799;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9797;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q191;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9803 =
11'd0;
endcase
end
always@(guard__h590104 or
_theResult___fst_exp__h598094 or
out_exp__h598777 or _theResult___exp__h598774)
begin
case (guard__h590104)
2'b0, 2'b01:
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 =
_theResult___fst_exp__h598094;
2'b10:
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 =
out_exp__h598777;
2'b11:
CASE_guard90104_0b0_theResult___fst_exp98094_0_ETC__q192 =
_theResult___exp__h598774;
endcase
end
always@(guard__h532419 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h532419)
2'b0, 2'b01, 2'b10:
CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard32419_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
guard__h532419 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532419)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
(guard__h532419 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h532419 == 2'b01 || guard__h532419 == 2'b10 ||
guard__h532419 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h550800 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h550800)
2'b0, 2'b01, 2'b10:
CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard50800_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
guard__h550800 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550800)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
(guard__h550800 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h550800 == 2'b01 || guard__h550800 == 2'b10 ||
guard__h550800 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h541731 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h541731)
2'b0, 2'b01, 2'b10:
CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard41731_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
guard__h541731 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541731)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
(guard__h541731 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h541731 == 2'b01 || guard__h541731 == 2'b10 ||
guard__h541731 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h541731 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h541731)
2'b0, 2'b01, 2'b10:
CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard41731_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
guard__h541731 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h541731)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
(guard__h541731 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h541731 != 2'b01 && guard__h541731 != 2'b10 &&
guard__h541731 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h550800 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h550800)
2'b0, 2'b01, 2'b10:
CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard50800_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
guard__h550800 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h550800)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
(guard__h550800 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h550800 != 2'b01 && guard__h550800 != 2'b10 &&
guard__h550800 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h532419 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h532419)
2'b0, 2'b01, 2'b10:
CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard32419_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
guard__h532419 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h532419)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
(guard__h532419 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h532419 != 2'b01 && guard__h532419 != 2'b10 &&
guard__h532419 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h532419 or
_theResult___snd__h540331 or _theResult___sfd__h541036)
begin
case (guard__h532419)
2'b0:
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205 =
_theResult___snd__h540331[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205 =
_theResult___sfd__h541036;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h540331 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593 or
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
_theResult___snd__h540331[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10595;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10593;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q205;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10599 =
52'd0;
endcase
end
always@(guard__h532419 or
_theResult___snd__h540331 or
out_sfd__h541039 or _theResult___sfd__h541036)
begin
case (guard__h532419)
2'b0, 2'b01:
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 =
_theResult___snd__h540331[56:5];
2'b10:
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 =
out_sfd__h541039;
2'b11:
CASE_guard32419_0b0_theResult___snd40331_BITS__ETC__q206 =
_theResult___sfd__h541036;
endcase
end
always@(guard__h541731 or sfdin__h549951 or _theResult___sfd__h550687)
begin
case (guard__h541731)
2'b0:
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207 =
sfdin__h549951[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207 =
_theResult___sfd__h550687;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h549951 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619 or
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
sfdin__h549951[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10621;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10619;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q207;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10625 =
52'd0;
endcase
end
always@(guard__h541731 or
sfdin__h549951 or out_sfd__h550690 or _theResult___sfd__h550687)
begin
case (guard__h541731)
2'b0, 2'b01:
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 =
sfdin__h549951[56:5];
2'b10:
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 =
out_sfd__h550690;
2'b11:
CASE_guard41731_0b0_sfdin49951_BITS_56_TO_5_0b_ETC__q208 =
_theResult___sfd__h550687;
endcase
end
always@(guard__h550800 or
_theResult___snd__h558736 or _theResult___sfd__h559471)
begin
case (guard__h550800)
2'b0:
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209 =
_theResult___snd__h558736[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209 =
_theResult___sfd__h559471;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h558736 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638 or
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
_theResult___snd__h558736[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10640;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10638;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q209;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10644 =
52'd0;
endcase
end
always@(guard__h550800 or
_theResult___snd__h558736 or
out_sfd__h559474 or _theResult___sfd__h559471)
begin
case (guard__h550800)
2'b0, 2'b01:
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 =
_theResult___snd__h558736[56:5];
2'b10:
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 =
out_sfd__h559474;
2'b11:
CASE_guard50800_0b0_theResult___snd58736_BITS__ETC__q210 =
_theResult___sfd__h559471;
endcase
end
always@(guard__h502878 or
_theResult___fst_exp__h511104 or _theResult___exp__h511833)
begin
case (guard__h502878)
2'b0:
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211 =
_theResult___fst_exp__h511104;
2'b01, 2'b10, 2'b11:
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211 =
_theResult___exp__h511833;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h511104 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056 or
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
_theResult___fst_exp__h511104;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9058;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9056;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q211;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9062 =
11'd0;
endcase
end
always@(guard__h502878 or
_theResult___fst_exp__h511104 or
out_exp__h511836 or _theResult___exp__h511833)
begin
case (guard__h502878)
2'b0, 2'b01:
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 =
_theResult___fst_exp__h511104;
2'b10:
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 =
out_exp__h511836;
2'b11:
CASE_guard02878_0b0_theResult___fst_exp11104_0_ETC__q212 =
_theResult___exp__h511833;
endcase
end
always@(guard__h511947 or
_theResult___fst_exp__h519937 or _theResult___exp__h520617)
begin
case (guard__h511947)
2'b0:
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213 =
_theResult___fst_exp__h519937;
2'b01, 2'b10, 2'b11:
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213 =
_theResult___exp__h520617;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h519937 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087 or
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
_theResult___fst_exp__h519937;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9089;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9087;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q213;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9093 =
11'd0;
endcase
end
always@(guard__h511947 or
_theResult___fst_exp__h519937 or
out_exp__h520620 or _theResult___exp__h520617)
begin
case (guard__h511947)
2'b0, 2'b01:
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 =
_theResult___fst_exp__h519937;
2'b10:
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 =
out_exp__h520620;
2'b11:
CASE_guard11947_0b0_theResult___fst_exp19937_0_ETC__q214 =
_theResult___exp__h520617;
endcase
end
always@(guard__h493566 or
_theResult___snd__h501478 or _theResult___sfd__h502183)
begin
case (guard__h493566)
2'b0:
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215 =
_theResult___snd__h501478[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215 =
_theResult___sfd__h502183;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h501478 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113 or
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
_theResult___snd__h501478[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9115;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9113;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q215;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9119 =
52'd0;
endcase
end
always@(guard__h493566 or
_theResult___snd__h501478 or
out_sfd__h502186 or _theResult___sfd__h502183)
begin
case (guard__h493566)
2'b0, 2'b01:
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 =
_theResult___snd__h501478[56:5];
2'b10:
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 =
out_sfd__h502186;
2'b11:
CASE_guard93566_0b0_theResult___snd01478_BITS__ETC__q216 =
_theResult___sfd__h502183;
endcase
end
always@(guard__h502878 or sfdin__h511098 or _theResult___sfd__h511834)
begin
case (guard__h502878)
2'b0:
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217 =
sfdin__h511098[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217 =
_theResult___sfd__h511834;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h511098 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140 or
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
sfdin__h511098[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9142;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9140;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q217;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9146 =
52'd0;
endcase
end
always@(guard__h502878 or
sfdin__h511098 or out_sfd__h511837 or _theResult___sfd__h511834)
begin
case (guard__h502878)
2'b0, 2'b01:
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 =
sfdin__h511098[56:5];
2'b10:
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 =
out_sfd__h511837;
2'b11:
CASE_guard02878_0b0_sfdin11098_BITS_56_TO_5_0b_ETC__q218 =
_theResult___sfd__h511834;
endcase
end
always@(guard__h511947 or
_theResult___snd__h519883 or _theResult___sfd__h520618)
begin
case (guard__h511947)
2'b0:
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219 =
_theResult___snd__h519883[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219 =
_theResult___sfd__h520618;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h519883 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159 or
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
_theResult___snd__h519883[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9161;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9159;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q219;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9165 =
52'd0;
endcase
end
always@(guard__h511947 or
_theResult___snd__h519883 or
out_sfd__h520621 or _theResult___sfd__h520618)
begin
case (guard__h511947)
2'b0, 2'b01:
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 =
_theResult___snd__h519883[56:5];
2'b10:
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 =
out_sfd__h520621;
2'b11:
CASE_guard11947_0b0_theResult___snd19883_BITS__ETC__q220 =
_theResult___sfd__h520618;
endcase
end
always@(guard__h571723 or
_theResult___snd__h579635 or _theResult___sfd__h580340)
begin
case (guard__h571723)
2'b0:
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221 =
_theResult___snd__h579635[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221 =
_theResult___sfd__h580340;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h579635 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823 or
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
_theResult___snd__h579635[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9825;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9823;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q221;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9829 =
52'd0;
endcase
end
always@(guard__h571723 or
_theResult___snd__h579635 or
out_sfd__h580343 or _theResult___sfd__h580340)
begin
case (guard__h571723)
2'b0, 2'b01:
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 =
_theResult___snd__h579635[56:5];
2'b10:
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 =
out_sfd__h580343;
2'b11:
CASE_guard71723_0b0_theResult___snd79635_BITS__ETC__q222 =
_theResult___sfd__h580340;
endcase
end
always@(guard__h581035 or sfdin__h589255 or _theResult___sfd__h589991)
begin
case (guard__h581035)
2'b0:
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223 =
sfdin__h589255[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223 =
_theResult___sfd__h589991;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h589255 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849 or
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
sfdin__h589255[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9851;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9849;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q223;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9855 =
52'd0;
endcase
end
always@(guard__h581035 or
sfdin__h589255 or out_sfd__h589994 or _theResult___sfd__h589991)
begin
case (guard__h581035)
2'b0, 2'b01:
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 =
sfdin__h589255[56:5];
2'b10:
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 =
out_sfd__h589994;
2'b11:
CASE_guard81035_0b0_sfdin89255_BITS_56_TO_5_0b_ETC__q224 =
_theResult___sfd__h589991;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876 or
f1_exp__h482139 or
f1_sfd__h482140 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10876;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10864;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10890 =
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10888;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807 or
f1_exp__h482139 or
f1_sfd__h482140 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10807;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10764;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10854 =
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10852;
endcase
end
always@(guard__h590104 or
_theResult___snd__h598040 or _theResult___sfd__h598775)
begin
case (guard__h590104)
2'b0:
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225 =
_theResult___snd__h598040[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225 =
_theResult___sfd__h598775;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h598040 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868 or
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
_theResult___snd__h598040[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9870;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9868;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q225;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9874 =
52'd0;
endcase
end
always@(guard__h590104 or
_theResult___snd__h598040 or
out_sfd__h598778 or _theResult___sfd__h598775)
begin
case (guard__h590104)
2'b0, 2'b01:
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 =
_theResult___snd__h598040[56:5];
2'b10:
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 =
out_sfd__h598778;
2'b11:
CASE_guard90104_0b0_theResult___snd98040_BITS__ETC__q226 =
_theResult___sfd__h598775;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920 or
f1_exp__h482139 or
f1_sfd__h482140 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10920;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10904;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10938 =
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10936;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964 or
f1_exp__h482139 or
f1_sfd__h482140 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10964;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10950;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10980 =
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d10978;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006 or
f1_exp__h482139 or
f1_sfd__h482140 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11006;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 =
(f1_exp__h482139 != 8'd255 || f1_sfd__h482140 == 23'd0) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10992;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d11022 =
coreFix_fpuMulDivExe_0_regToExeQ_first__371_BI_ETC___d11020;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 =
coreFix_aluExe_0_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first or
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227)
begin
case (coreFix_aluExe_0_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 =
coreFix_aluExe_0_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 =
{ coreFix_aluExe_0_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_0_regToExeQ$first[404:400],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q227,
coreFix_aluExe_0_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q228 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[394:383])
12'd1971,
12'd1970,
12'd1969,
12'd1968,
12'd1955,
12'd1954,
12'd1953,
12'd1952,
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 =
coreFix_aluExe_0_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q229 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 =
coreFix_aluExe_1_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first or
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230)
begin
case (coreFix_aluExe_1_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 =
coreFix_aluExe_1_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 =
{ coreFix_aluExe_1_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_1_regToExeQ$first[404:400],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q230,
coreFix_aluExe_1_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q231 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[394:383])
12'd1971,
12'd1970,
12'd1969,
12'd1968,
12'd1955,
12'd1954,
12'd1953,
12'd1952,
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 =
coreFix_aluExe_1_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q232 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 =
fetchStage$pipelines_0_first[172:161];
default: IF_fetchStage_pipelines_0_first__2757_BITS_172_ETC___d12973 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[67:64])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 =
fetchStage$pipelines_0_first[67:64];
4'd11:
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 = 4'd10;
4'd12:
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 = 4'd11;
4'd13:
IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 = 4'd12;
default: IF_fetchStage_pipelines_0_first__2757_BIT_68_2_ETC___d13130 =
4'd13;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 =
fetchStage$pipelines_0_first[177:175];
default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 = 3'd7;
endcase
end
always@(fetchStage$pipelines_0_first or
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883 =
fetchStage$pipelines_0_first[194:174];
3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883 =
{ fetchStage$pipelines_0_first[194:192],
9'h0AA,
fetchStage$pipelines_0_first[182:178],
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
fetchStage$pipelines_0_first[174] };
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d12883 =
21'd1485482;
endcase
end
always@(checkForException___d13008)
begin
case (checkForException___d13008[3:0])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 =
checkForException___d13008[3:0];
4'd11: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10;
4'd12: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11;
4'd13: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12;
default: CASE_checkForException_3008_BITS_3_TO_0_0_chec_ETC__q234 =
4'd13;
endcase
end
always@(k__h669623 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h669623)
1'd0:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 =
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 =
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 =
coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13465 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13465 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13465 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461;
endcase
end
always@(k__h669623 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h669623)
1'd0:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 =
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 =
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429 or
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484 or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 =
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13484;
3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 =
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13489 =
regRenamingTable_rename_0_canRename__3403_AND__ETC___d13429;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 =
!coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13524 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13524 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13524 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519);
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
fetchStage$pipelines_1_first[172:161];
default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 =
fetchStage$pipelines_1_first[177:175];
default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 = 3'd7;
endcase
end
always@(fetchStage$pipelines_1_first or
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584 =
fetchStage$pipelines_1_first[194:174];
3'd4:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584 =
{ fetchStage$pipelines_1_first[194:192],
9'h0AA,
fetchStage$pipelines_1_first[182:178],
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
fetchStage$pipelines_1_first[174] };
default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13584 =
21'd1485482;
endcase
end
always@(idx__h685368 or
fetchStage$pipelines_0_canDeq or
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 or
coreFix_aluExe_0_rsAlu$canEnq or
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h685368)
1'd0:
SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13746 ||
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2757_BITS_19_ETC___d13752 ||
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
!coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 or
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13844 or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13850 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 ||
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13844;
3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13850 =
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13850 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13850 =
renameStage_rg_m_halt_req_2784_BIT_4_2785_OR_f_ETC___d13840;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13872 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13872 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461;
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13890 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_1_first or
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 or
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13856 or
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13887 or
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13898 or
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13869 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13880)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 =
!SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 &&
NOT_fetchStage_pipelines_1_first__2766_BITS_19_ETC___d13856;
3'd2:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 =
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13887 &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13898;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 =
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d13869 &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13880;
default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d13902 =
regRenamingTable_rename_1_canRename__3530_AND__ETC___d13738;
endcase
end
always@(k__h669623 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (k__h669623)
1'd0:
CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_k69623_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13947 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or
regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 or
regRenamingTable$RDY_rename_0_getRename or
_0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13945 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 ||
regRenamingTable$RDY_rename_0_getRename &&
_0_OR_NOT_fetchStage_pipelines_0_first__2757_BI_ETC___d13928;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13945 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_0_getRename;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13945 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 ||
regRenamingTable_RDY_rename_0_getRename__3301__ETC___d13941;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13961 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13961 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13961 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13968 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__343_ETC___d13482 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim);
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13968 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d13968 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13461;
endcase
end
always@(idx__h685368 or
fetchStage$pipelines_0_canDeq or
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991 or
coreFix_aluExe_0_rsAlu$canEnq or
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h685368)
1'd0:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13991) &&
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2757_BITS_194_TO_ETC___d13998) &&
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14018 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (fetchStage_pipelines_0_canDeq__2755_AND_NOT_fe_ETC___d14018)
1'd0:
CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_fetchStage_pipelines_0_canDeq__2755_AND_N_ETC__q241 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14044 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14044 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519);
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14056 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3438_co_ETC___d13448;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14056 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2757_BITS_194_ETC___d14056 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d13519;
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14065 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772 or
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14053)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14068 =
SEL_ARR_fetchStage_pipelines_0_canDeq__2755_AN_ETC___d13772;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14068 =
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14053;
default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14068 =
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14065;
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14031 or
regRenamingTable$RDY_rename_1_getRename or
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14036 or
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 or
regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022 or
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14024 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14027)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14041 =
!SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__275_ETC___d14002 ||
regRenamingTable_RDY_rename_1_getRename__4004__ETC___d14022;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14041 =
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14024 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__39_ETC___d14027;
default: IF_fetchStage_pipelines_1_first__2766_BITS_194_ETC___d14041 =
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2755_AND_regRen_ETC___d14031 ||
regRenamingTable$RDY_rename_1_getRename &&
NOT_fetchStage_pipelines_0_canDeq__2755_2756_O_ETC___d14036;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14125 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14125 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14122 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14122 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14131 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14128 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_0_first__2757_BITS_191_ETC___d14128 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14262 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14260 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14260 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14259 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14261 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_1_first__2766_BITS_191_ETC___d14261 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(csrf_prv_reg or csrf_rg_dcsr)
begin
case (csrf_prv_reg)
2'd1:
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 =
csrf_rg_dcsr[13];
2'd3:
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 =
csrf_rg_dcsr[15];
default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q243 =
csrf_rg_dcsr[12];
endcase
end
always@(csrf_prv_reg or csrf_rg_dcsr)
begin
case (csrf_prv_reg)
2'd1:
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 =
!csrf_rg_dcsr[13];
2'd3:
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 =
!csrf_rg_dcsr[15];
default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q244 =
!csrf_rg_dcsr[12];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[180:169])
12'd1:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd0;
12'd2:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd1;
12'd3:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd2;
12'd256:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd8;
12'd260:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd9;
12'd261:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd10;
12'd262:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd11;
12'd320:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd12;
12'd321:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd13;
12'd322:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd14;
12'd323:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd15;
12'd324:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd16;
12'd384:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd17;
12'd768:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd18;
12'd769:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd19;
12'd770:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd20;
12'd771:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd21;
12'd772:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd22;
12'd773:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd23;
12'd774:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd24;
12'd832:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd25;
12'd833:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd26;
12'd834:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd27;
12'd835:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd28;
12'd836:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd29;
12'd1952:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd36;
12'd1953:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd37;
12'd1954:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd38;
12'd1955:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd39;
12'd1968:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd40;
12'd1969:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd41;
12'd1970:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd42;
12'd1971:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd43;
12'd2048:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd6;
12'd2049:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd7;
12'd2816:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd30;
12'd2818:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd31;
12'd3072:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd3;
12'd3073:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd4;
12'd3074:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd5;
12'd3857:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd32;
12'd3858:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd33;
12'd3859:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd34;
12'd3860:
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 = 6'd35;
default: IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 =
6'd44;
endcase
end
always@(IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 or
rob$deqPort_0_deq_data or robdeqPort_0_deq_data_BITS_95_TO_32__q245)
begin
case (IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973)
6'd0:
data_warl_xformed__h721446 =
{ 59'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] };
6'd1, 6'd11, 6'd24:
data_warl_xformed__h721446 =
{ 61'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[2:0] };
6'd2:
data_warl_xformed__h721446 =
{ 56'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[7:0] };
6'd8:
data_warl_xformed__h721446 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11,
43'd8192,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[19:18],
3'd0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13],
4'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[8],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd9, 6'd16:
data_warl_xformed__h721446 =
{ 54'd0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:8],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:4],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd10, 6'd23:
data_warl_xformed__h721446 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[63:2],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[0] };
6'd14, 6'd27:
data_warl_xformed__h721446 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[63],
59'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[3:0] };
6'd17:
data_warl_xformed__h721446 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[63],
19'd0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[43:0] };
6'd18:
data_warl_xformed__h721446 =
{ robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:13] == 2'b11,
40'd5120,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[22:17],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14:11],
2'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[8:7],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd19: data_warl_xformed__h721446 = 64'h800000000014112D;
6'd20:
data_warl_xformed__h721446 =
{ 48'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[15],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:11],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:0] };
6'd21, 6'd22, 6'd29:
data_warl_xformed__h721446 =
{ 52'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[11],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[9:7],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[5:3],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[1:0] };
6'd32, 6'd33, 6'd34, 6'd35: data_warl_xformed__h721446 = 64'd0;
6'd37:
data_warl_xformed__h721446 =
{ 4'b0, robdeqPort_0_deq_data_BITS_95_TO_32__q245[59:0] };
6'd40:
data_warl_xformed__h721446 =
{ 32'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[31:28],
12'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[14],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[13:6],
1'b0,
robdeqPort_0_deq_data_BITS_95_TO_32__q245[4:0] };
default: data_warl_xformed__h721446 = rob$deqPort_0_deq_data[95:32];
endcase
end
always@(rob$deqPort_0_deq_data or
IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180)
begin
case (rob$deqPort_0_deq_data[329:325])
5'd19, 5'd20:
x__h722034 =
IF_rob_deqPort_0_deq_data__4328_BITS_329_TO_32_ETC___d15180;
default: x__h722034 = rob$deqPort_0_deq_data[425:362];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q251 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
coreFix_memExe_stb$deq or
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 or
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79])
3'd0, 3'd2, 3'd4:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
3'd1:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
{ coreFix_memExe_stb$deq[575] ?
coreFix_memExe_stb$deq[511:504] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504],
coreFix_memExe_stb$deq[574] ?
coreFix_memExe_stb$deq[503:496] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496],
coreFix_memExe_stb$deq[573] ?
coreFix_memExe_stb$deq[495:488] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488],
coreFix_memExe_stb$deq[572] ?
coreFix_memExe_stb$deq[487:480] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480],
coreFix_memExe_stb$deq[571] ?
coreFix_memExe_stb$deq[479:472] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472],
coreFix_memExe_stb$deq[570] ?
coreFix_memExe_stb$deq[471:464] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464],
coreFix_memExe_stb$deq[569] ?
coreFix_memExe_stb$deq[463:456] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456],
coreFix_memExe_stb$deq[568] ?
coreFix_memExe_stb$deq[455:448] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448],
coreFix_memExe_stb$deq[567] ?
coreFix_memExe_stb$deq[447:440] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440],
coreFix_memExe_stb$deq[566] ?
coreFix_memExe_stb$deq[439:432] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432],
coreFix_memExe_stb$deq[565] ?
coreFix_memExe_stb$deq[431:424] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424],
coreFix_memExe_stb$deq[564] ?
coreFix_memExe_stb$deq[423:416] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416],
coreFix_memExe_stb$deq[563] ?
coreFix_memExe_stb$deq[415:408] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408],
coreFix_memExe_stb$deq[562] ?
coreFix_memExe_stb$deq[407:400] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400],
coreFix_memExe_stb$deq[561] ?
coreFix_memExe_stb$deq[399:392] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392],
coreFix_memExe_stb$deq[560] ?
coreFix_memExe_stb$deq[391:384] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384],
coreFix_memExe_stb$deq[559] ?
coreFix_memExe_stb$deq[383:376] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376],
coreFix_memExe_stb$deq[558] ?
coreFix_memExe_stb$deq[375:368] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368],
coreFix_memExe_stb$deq[557] ?
coreFix_memExe_stb$deq[367:360] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360],
coreFix_memExe_stb$deq[556] ?
coreFix_memExe_stb$deq[359:352] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352],
coreFix_memExe_stb$deq[555] ?
coreFix_memExe_stb$deq[351:344] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344],
coreFix_memExe_stb$deq[554] ?
coreFix_memExe_stb$deq[343:336] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336],
coreFix_memExe_stb$deq[553] ?
coreFix_memExe_stb$deq[335:328] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328],
coreFix_memExe_stb$deq[552] ?
coreFix_memExe_stb$deq[327:320] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320],
coreFix_memExe_stb$deq[551] ?
coreFix_memExe_stb$deq[319:312] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312],
coreFix_memExe_stb$deq[550] ?
coreFix_memExe_stb$deq[311:304] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304],
coreFix_memExe_stb$deq[549] ?
coreFix_memExe_stb$deq[303:296] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296],
coreFix_memExe_stb$deq[548] ?
coreFix_memExe_stb$deq[295:288] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288],
coreFix_memExe_stb$deq[547] ?
coreFix_memExe_stb$deq[287:280] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280],
coreFix_memExe_stb$deq[546] ?
coreFix_memExe_stb$deq[279:272] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272],
coreFix_memExe_stb$deq[545] ?
coreFix_memExe_stb$deq[271:264] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264],
coreFix_memExe_stb$deq[544] ?
coreFix_memExe_stb$deq[263:256] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256],
coreFix_memExe_stb$deq[543] ?
coreFix_memExe_stb$deq[255:248] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248],
coreFix_memExe_stb$deq[542] ?
coreFix_memExe_stb$deq[247:240] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240],
coreFix_memExe_stb$deq[541] ?
coreFix_memExe_stb$deq[239:232] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232],
coreFix_memExe_stb$deq[540] ?
coreFix_memExe_stb$deq[231:224] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224],
coreFix_memExe_stb$deq[539] ?
coreFix_memExe_stb$deq[223:216] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216],
coreFix_memExe_stb$deq[538] ?
coreFix_memExe_stb$deq[215:208] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208],
coreFix_memExe_stb$deq[537] ?
coreFix_memExe_stb$deq[207:200] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200],
coreFix_memExe_stb$deq[536] ?
coreFix_memExe_stb$deq[199:192] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192],
coreFix_memExe_stb$deq[535] ?
coreFix_memExe_stb$deq[191:184] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184],
coreFix_memExe_stb$deq[534] ?
coreFix_memExe_stb$deq[183:176] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176],
coreFix_memExe_stb$deq[533] ?
coreFix_memExe_stb$deq[175:168] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168],
coreFix_memExe_stb$deq[532] ?
coreFix_memExe_stb$deq[167:160] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160],
coreFix_memExe_stb$deq[531] ?
coreFix_memExe_stb$deq[159:152] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152],
coreFix_memExe_stb$deq[530] ?
coreFix_memExe_stb$deq[151:144] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144],
coreFix_memExe_stb$deq[529] ?
coreFix_memExe_stb$deq[143:136] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136],
coreFix_memExe_stb$deq[528] ?
coreFix_memExe_stb$deq[135:128] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128],
coreFix_memExe_stb$deq[527] ?
coreFix_memExe_stb$deq[127:120] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120],
coreFix_memExe_stb$deq[526] ?
coreFix_memExe_stb$deq[119:112] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112],
coreFix_memExe_stb$deq[525] ?
coreFix_memExe_stb$deq[111:104] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104],
coreFix_memExe_stb$deq[524] ?
coreFix_memExe_stb$deq[103:96] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96],
coreFix_memExe_stb$deq[523] ?
coreFix_memExe_stb$deq[95:88] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88],
coreFix_memExe_stb$deq[522] ?
coreFix_memExe_stb$deq[87:80] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80],
coreFix_memExe_stb$deq[521] ?
coreFix_memExe_stb$deq[79:72] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72],
coreFix_memExe_stb$deq[520] ?
coreFix_memExe_stb$deq[71:64] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64],
coreFix_memExe_stb$deq[519] ?
coreFix_memExe_stb$deq[63:56] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56],
coreFix_memExe_stb$deq[518] ?
coreFix_memExe_stb$deq[55:48] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48],
coreFix_memExe_stb$deq[517] ?
coreFix_memExe_stb$deq[47:40] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40],
coreFix_memExe_stb$deq[516] ?
coreFix_memExe_stb$deq[39:32] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32],
coreFix_memExe_stb$deq[515] ?
coreFix_memExe_stb$deq[31:24] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24],
coreFix_memExe_stb$deq[514] ?
coreFix_memExe_stb$deq[23:16] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16],
coreFix_memExe_stb$deq[513] ?
coreFix_memExe_stb$deq[15:8] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8],
coreFix_memExe_stb$deq[512] ?
coreFix_memExe_stb$deq[7:0] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] };
3'd3:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2150 ?
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2208 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2500 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 =
4'd15;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q253 =
4'd15;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd4, 3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q254 = 3'd7;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 =
rob$deqPort_0_deq_data[180:169];
default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q255 =
12'd2303;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd0:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd4;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd3;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd2;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 = 3'd1;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10717 =
3'd0;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[97:96])
2'd0, 2'd1:
CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 =
rob$deqPort_0_deq_data[97:96];
default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q256 = 2'd2;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174;
5'd25:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884;
5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9940;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9944 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9884;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[97:96])
2'd0, 2'd1:
CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 =
commitStage_f_rob_data$D_OUT[97:96];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_97_TO_9_ETC__q257 = 2'd2;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q259 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q261 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q262 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q263 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q264 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q265 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q266 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228])
2'd0, 2'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8428 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d8409 =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q268 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q269 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q270 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q271 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q272 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q273 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(mmio_dataReqQ_data_0)
begin
case (mmio_dataReqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274 =
mmio_dataReqQ_data_0[77:72];
2'd3:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q274 =
{ 2'd3, mmio_dataReqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_lsq$firstLd)
begin
case (coreFix_memExe_lsq$firstLd[6:3])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 =
coreFix_memExe_lsq$firstLd[6:3];
default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q275 =
4'd15;
endcase
end
always@(coreFix_memExe_lsq$firstSt)
begin
case (coreFix_memExe_lsq$firstSt[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 =
coreFix_memExe_lsq$firstSt[3:0];
default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q276 =
4'd15;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277 =
commitStage_f_rob_data$D_OUT[180:169];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_180_TO__ETC__q277 =
12'd2303;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[165:162])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 =
commitStage_f_rob_data$D_OUT[165:162];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q278 =
4'd15;
endcase
end
always@(commitStage_f_rob_data$D_OUT)
begin
case (commitStage_f_rob_data$D_OUT[165:162])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 =
commitStage_f_rob_data$D_OUT[165:162];
default: CASE_commitStage_f_rob_dataD_OUT_BITS_165_TO__ETC__q279 =
4'd15;
endcase
end
always@(mmioToPlatform_pRq_enq_x)
begin
case (mmioToPlatform_pRq_enq_x[37:36])
2'd0, 2'd1, 2'd2:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280 =
mmioToPlatform_pRq_enq_x[37:32];
2'd3:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q280 =
{ 2'd3, mmioToPlatform_pRq_enq_x[35:32] };
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281 =
coreFix_aluExe_0_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData or
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 =
coreFix_aluExe_0_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 =
{ coreFix_aluExe_0_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_0_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q281,
coreFix_aluExe_0_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q282 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283 =
coreFix_aluExe_0_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q283 =
12'd2303;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284 =
coreFix_aluExe_0_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284)
begin
case (coreFix_aluExe_0_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285 =
coreFix_aluExe_0_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285 =
{ coreFix_aluExe_0_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_0_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q284,
coreFix_aluExe_0_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q285 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286 =
coreFix_aluExe_0_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q286 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287 =
coreFix_aluExe_1_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData or
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 =
coreFix_aluExe_1_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 =
{ coreFix_aluExe_1_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_1_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q287,
coreFix_aluExe_1_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q288 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289 =
coreFix_aluExe_1_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q289 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290 =
coreFix_aluExe_1_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290)
begin
case (coreFix_aluExe_1_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291 =
coreFix_aluExe_1_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291 =
{ coreFix_aluExe_1_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_1_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q290,
coreFix_aluExe_1_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q291 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292 =
coreFix_aluExe_1_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q292 =
12'd2303;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67];
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66];
3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 =
{ coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84],
9'h0AA,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70],
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q293,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] };
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q294 =
21'd1485482;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654 or
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707 or
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654;
5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[139],
coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10707,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10652 };
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q295 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d9174;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296 =
64'h3FF0000000000000;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q296 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__371_ETC___d10654;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58];
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57];
3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 =
{ coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75],
9'h0AA,
coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61],
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q297,
coreFix_fpuMulDivExe_0_dispToRegQ$first[57] };
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q298 =
21'd1485482;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q299 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0];
endcase
end
always@(rob$deqPort_1_deq_data)
begin
case (rob$deqPort_1_deq_data[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1952,
12'd1953,
12'd1954,
12'd1955,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300 =
rob$deqPort_1_deq_data[180:169];
default: CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q300 =
12'd2303;
endcase
end
always@(rob$deqPort_1_deq_data)
begin
case (rob$deqPort_1_deq_data[97:96])
2'd0, 2'd1:
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301 =
rob$deqPort_1_deq_data[97:96];
default: CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q301 = 2'd2;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
166'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
4'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
2'd3;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
4'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0;
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'b01;
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0;
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0;
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3;
csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY 64'd1073741843;
csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY 64'd1879048192;
csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY 59'd0;
csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_brpred <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_caches <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
66'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 39'h0400000000;
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA;
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA;
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY 5'd10;
rg_core_run_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
started <= `BSV_ASSIGNMENT_DELAY 1'd0;
update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (commitStage_commitTrap$EN)
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
commitStage_commitTrap$D_IN;
if (commitStage_rg_just_after_reset$EN)
commitStage_rg_just_after_reset <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_just_after_reset$D_IN;
if (commitStage_rg_run_state$EN)
commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_run_state$D_IN;
if (commitStage_rg_serial_num$EN)
commitStage_rg_serial_num <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_serial_num$D_IN;
if (coreFix_doStatsReg$EN)
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN)
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN;
if (coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_data_0$EN)
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
if (coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_empty$EN)
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_empty$D_IN;
if (coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_full$EN)
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_full$D_IN;
if (coreFix_memExe_forwardQ_clearReq_rl$EN)
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_clearReq_rl$D_IN;
if (coreFix_memExe_forwardQ_data_0$EN)
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_0$D_IN;
if (coreFix_memExe_forwardQ_data_1$EN)
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_1$D_IN;
if (coreFix_memExe_forwardQ_deqP$EN)
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqP$D_IN;
if (coreFix_memExe_forwardQ_deqReq_rl$EN)
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_empty$EN)
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_empty$D_IN;
if (coreFix_memExe_forwardQ_enqP$EN)
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqP$D_IN;
if (coreFix_memExe_forwardQ_enqReq_rl$EN)
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_full$EN)
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_full$D_IN;
if (coreFix_memExe_memRespLdQ_clearReq_rl$EN)
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_clearReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_data_0$EN)
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_0$D_IN;
if (coreFix_memExe_memRespLdQ_data_1$EN)
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_1$D_IN;
if (coreFix_memExe_memRespLdQ_deqP$EN)
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqP$D_IN;
if (coreFix_memExe_memRespLdQ_deqReq_rl$EN)
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_empty$EN)
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_empty$D_IN;
if (coreFix_memExe_memRespLdQ_enqP$EN)
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqP$D_IN;
if (coreFix_memExe_memRespLdQ_enqReq_rl$EN)
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_full$EN)
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_full$D_IN;
if (coreFix_memExe_reqLdQ_data_0_rl$EN)
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLdQ_empty_rl$EN)
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_empty_rl$D_IN;
if (coreFix_memExe_reqLdQ_full_rl$EN)
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_full_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_data_0_rl$EN)
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_empty_rl$EN)
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_full_rl$EN)
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_full_rl$D_IN;
if (coreFix_memExe_reqStQ_data_0_rl$EN)
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_data_0_rl$D_IN;
if (coreFix_memExe_reqStQ_empty_rl$EN)
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_empty_rl$D_IN;
if (coreFix_memExe_reqStQ_full_rl$EN)
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_full_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_clearReq_rl$EN)
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_data_0$EN)
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_data_0$D_IN;
if (coreFix_memExe_respLrScAmoQ_deqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_empty$EN)
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_empty$D_IN;
if (coreFix_memExe_respLrScAmoQ_enqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_full$EN)
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_full$D_IN;
if (coreFix_memExe_waitLrScAmoMMIOResp$EN)
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
if (csrInstOrInterruptInflight_rl$EN)
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY
csrInstOrInterruptInflight_rl$D_IN;
if (csrf_external_int_en_vec_0$EN)
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_0$D_IN;
if (csrf_external_int_en_vec_1$EN)
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_1$D_IN;
if (csrf_external_int_en_vec_3$EN)
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_3$D_IN;
if (csrf_external_int_pend_vec_0$EN)
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_0$D_IN;
if (csrf_external_int_pend_vec_1$EN)
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_1$D_IN;
if (csrf_external_int_pend_vec_3$EN)
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_3$D_IN;
if (csrf_fflags_reg$EN)
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY csrf_fflags_reg$D_IN;
if (csrf_frm_reg$EN)
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY csrf_frm_reg$D_IN;
if (csrf_fs_reg$EN)
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY csrf_fs_reg$D_IN;
if (csrf_ie_vec_0$EN)
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_0$D_IN;
if (csrf_ie_vec_1$EN)
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN;
if (csrf_ie_vec_3$EN)
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN;
if (csrf_mcause_code_reg$EN)
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_code_reg$D_IN;
if (csrf_mcause_interrupt_reg$EN)
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_interrupt_reg$D_IN;
if (csrf_mcounteren_cy_reg$EN)
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_cy_reg$D_IN;
if (csrf_mcounteren_ir_reg$EN)
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_ir_reg$D_IN;
if (csrf_mcounteren_tm_reg$EN)
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_tm_reg$D_IN;
if (csrf_mcycle_ehr_data_rl$EN)
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_mcycle_ehr_data_rl$D_IN;
if (csrf_medeleg_13_11_reg$EN)
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_13_11_reg$D_IN;
if (csrf_medeleg_15_reg$EN)
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_15_reg$D_IN;
if (csrf_medeleg_9_0_reg$EN)
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_9_0_reg$D_IN;
if (csrf_mepc_csr$EN)
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN;
if (csrf_mideleg_11_reg$EN)
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_11_reg$D_IN;
if (csrf_mideleg_1_0_reg$EN)
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_1_0_reg$D_IN;
if (csrf_mideleg_5_3_reg$EN)
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_5_3_reg$D_IN;
if (csrf_mideleg_9_7_reg$EN)
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_9_7_reg$D_IN;
if (csrf_minstret_ehr_data_rl$EN)
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_minstret_ehr_data_rl$D_IN;
if (csrf_mpp_reg$EN)
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY csrf_mpp_reg$D_IN;
if (csrf_mprv_reg$EN)
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN;
if (csrf_mscratch_csr$EN)
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN;
if (csrf_mtval_csr$EN)
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN;
if (csrf_mtvec_base_hi_reg$EN)
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_base_hi_reg$D_IN;
if (csrf_mtvec_mode_low_reg$EN)
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_mode_low_reg$D_IN;
if (csrf_mxr_reg$EN)
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN;
if (csrf_ppn_reg$EN)
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY csrf_ppn_reg$D_IN;
if (csrf_prev_ie_vec_0$EN)
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_0$D_IN;
if (csrf_prev_ie_vec_1$EN)
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_1$D_IN;
if (csrf_prev_ie_vec_3$EN)
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN;
if (csrf_prv_reg$EN)
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN;
if (csrf_rg_dcsr$EN)
csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY csrf_rg_dcsr$D_IN;
if (csrf_rg_dpc$EN)
csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY csrf_rg_dpc$D_IN;
if (csrf_rg_tdata1_data$EN)
csrf_rg_tdata1_data <= `BSV_ASSIGNMENT_DELAY
csrf_rg_tdata1_data$D_IN;
if (csrf_rg_tdata1_dmode$EN)
csrf_rg_tdata1_dmode <= `BSV_ASSIGNMENT_DELAY
csrf_rg_tdata1_dmode$D_IN;
if (csrf_rg_tselect$EN)
csrf_rg_tselect <= `BSV_ASSIGNMENT_DELAY csrf_rg_tselect$D_IN;
if (csrf_scause_code_reg$EN)
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_code_reg$D_IN;
if (csrf_scause_interrupt_reg$EN)
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_interrupt_reg$D_IN;
if (csrf_scounteren_cy_reg$EN)
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_cy_reg$D_IN;
if (csrf_scounteren_ir_reg$EN)
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_ir_reg$D_IN;
if (csrf_scounteren_tm_reg$EN)
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_tm_reg$D_IN;
if (csrf_sepc_csr$EN)
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN;
if (csrf_software_int_en_vec_0$EN)
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_0$D_IN;
if (csrf_software_int_en_vec_1$EN)
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_1$D_IN;
if (csrf_software_int_en_vec_3$EN)
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_3$D_IN;
if (csrf_software_int_pend_vec_0$EN)
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_0$D_IN;
if (csrf_software_int_pend_vec_1$EN)
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_1$D_IN;
if (csrf_software_int_pend_vec_3$EN)
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_3$D_IN;
if (csrf_spp_reg$EN)
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY csrf_spp_reg$D_IN;
if (csrf_sscratch_csr$EN)
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_sscratch_csr$D_IN;
if (csrf_stats_module_doStats$EN)
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY
csrf_stats_module_doStats$D_IN;
if (csrf_stval_csr$EN)
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN;
if (csrf_stvec_base_hi_reg$EN)
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_base_hi_reg$D_IN;
if (csrf_stvec_mode_low_reg$EN)
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_mode_low_reg$D_IN;
if (csrf_sum_reg$EN)
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN;
if (csrf_time_reg$EN)
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY csrf_time_reg$D_IN;
if (csrf_timer_int_en_vec_0$EN)
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_0$D_IN;
if (csrf_timer_int_en_vec_1$EN)
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_1$D_IN;
if (csrf_timer_int_en_vec_3$EN)
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_3$D_IN;
if (csrf_timer_int_pend_vec_0$EN)
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_0$D_IN;
if (csrf_timer_int_pend_vec_1$EN)
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_1$D_IN;
if (csrf_timer_int_pend_vec_3$EN)
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_3$D_IN;
if (csrf_tsr_reg$EN)
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_tsr_reg$D_IN;
if (csrf_tvm_reg$EN)
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY csrf_tvm_reg$D_IN;
if (csrf_tw_reg$EN)
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY csrf_tw_reg$D_IN;
if (csrf_vm_mode_sv39_reg$EN)
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY
csrf_vm_mode_sv39_reg$D_IN;
if (flush_brpred$EN)
flush_brpred <= `BSV_ASSIGNMENT_DELAY flush_brpred$D_IN;
if (flush_caches$EN)
flush_caches <= `BSV_ASSIGNMENT_DELAY flush_caches$D_IN;
if (flush_reservation$EN)
flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN;
if (flush_tlbs$EN)
flush_tlbs <= `BSV_ASSIGNMENT_DELAY flush_tlbs$D_IN;
if (mmio_cRqQ_clearReq_rl$EN)
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_clearReq_rl$D_IN;
if (mmio_cRqQ_data_0$EN)
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_data_0$D_IN;
if (mmio_cRqQ_deqReq_rl$EN)
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_deqReq_rl$D_IN;
if (mmio_cRqQ_empty$EN)
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_empty$D_IN;
if (mmio_cRqQ_enqReq_rl$EN)
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_enqReq_rl$D_IN;
if (mmio_cRqQ_full$EN)
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_full$D_IN;
if (mmio_cRsQ_clearReq_rl$EN)
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_clearReq_rl$D_IN;
if (mmio_cRsQ_data_0$EN)
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_data_0$D_IN;
if (mmio_cRsQ_deqReq_rl$EN)
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_deqReq_rl$D_IN;
if (mmio_cRsQ_empty$EN)
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_empty$D_IN;
if (mmio_cRsQ_enqReq_rl$EN)
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_enqReq_rl$D_IN;
if (mmio_cRsQ_full$EN)
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_full$D_IN;
if (mmio_dataPendQ_clearReq_rl$EN)
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_clearReq_rl$D_IN;
if (mmio_dataPendQ_deqReq_rl$EN)
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_deqReq_rl$D_IN;
if (mmio_dataPendQ_empty$EN)
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_empty$D_IN;
if (mmio_dataPendQ_enqReq_rl$EN)
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_enqReq_rl$D_IN;
if (mmio_dataPendQ_full$EN)
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_full$D_IN;
if (mmio_dataReqQ_clearReq_rl$EN)
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_clearReq_rl$D_IN;
if (mmio_dataReqQ_data_0$EN)
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_data_0$D_IN;
if (mmio_dataReqQ_deqReq_rl$EN)
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_deqReq_rl$D_IN;
if (mmio_dataReqQ_empty$EN)
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_empty$D_IN;
if (mmio_dataReqQ_enqReq_rl$EN)
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_enqReq_rl$D_IN;
if (mmio_dataReqQ_full$EN)
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_dataReqQ_full$D_IN;
if (mmio_dataRespQ_clearReq_rl$EN)
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_clearReq_rl$D_IN;
if (mmio_dataRespQ_data_0$EN)
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_data_0$D_IN;
if (mmio_dataRespQ_deqReq_rl$EN)
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_deqReq_rl$D_IN;
if (mmio_dataRespQ_empty$EN)
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_empty$D_IN;
if (mmio_dataRespQ_enqReq_rl$EN)
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_enqReq_rl$D_IN;
if (mmio_dataRespQ_full$EN)
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_full$D_IN;
if (mmio_fromHostAddr$EN)
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_fromHostAddr$D_IN;
if (mmio_pRqQ_clearReq_rl$EN)
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_clearReq_rl$D_IN;
if (mmio_pRqQ_data_0$EN)
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_data_0$D_IN;
if (mmio_pRqQ_deqReq_rl$EN)
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_deqReq_rl$D_IN;
if (mmio_pRqQ_empty$EN)
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_empty$D_IN;
if (mmio_pRqQ_enqReq_rl$EN)
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_enqReq_rl$D_IN;
if (mmio_pRqQ_full$EN)
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_full$D_IN;
if (mmio_pRsQ_clearReq_rl$EN)
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_clearReq_rl$D_IN;
if (mmio_pRsQ_data_0$EN)
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_data_0$D_IN;
if (mmio_pRsQ_deqReq_rl$EN)
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_deqReq_rl$D_IN;
if (mmio_pRsQ_empty$EN)
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_empty$D_IN;
if (mmio_pRsQ_enqReq_rl$EN)
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_enqReq_rl$D_IN;
if (mmio_pRsQ_full$EN)
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_full$D_IN;
if (mmio_toHostAddr$EN)
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN;
if (outOfReset$EN)
outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN;
if (renameStage_rg_m_halt_req$EN)
renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY
renameStage_rg_m_halt_req$D_IN;
if (rg_core_run_state$EN)
rg_core_run_state <= `BSV_ASSIGNMENT_DELAY rg_core_run_state$D_IN;
if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN;
if (update_vm_info$EN)
update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN;
end
if (csrf_rg_dscratch0$EN)
csrf_rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch0$D_IN;
if (csrf_rg_dscratch1$EN)
csrf_rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch1$D_IN;
if (csrf_rg_tdata2$EN)
csrf_rg_tdata2 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata2$D_IN;
if (csrf_rg_tdata3$EN)
csrf_rg_tdata3 <= `BSV_ASSIGNMENT_DELAY csrf_rg_tdata3$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
commitStage_commitTrap = 166'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_just_after_reset = 1'h0;
commitStage_rg_run_state = 1'h0;
commitStage_rg_serial_num = 64'hAAAAAAAAAAAAAAAA;
coreFix_doStatsReg = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit = 2'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 = 3'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl = 4'hA;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl =
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl =
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA;
coreFix_memExe_dMem_perfReqQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_empty = 1'h0;
coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A;
coreFix_memExe_dMem_perfReqQ_full = 1'h0;
coreFix_memExe_forwardQ_clearReq_rl = 1'h0;
coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_deqP = 1'h0;
coreFix_memExe_forwardQ_deqReq_rl = 1'h0;
coreFix_memExe_forwardQ_empty = 1'h0;
coreFix_memExe_forwardQ_enqP = 1'h0;
coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full = 1'h0;
coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_deqP = 1'h0;
coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_empty = 1'h0;
coreFix_memExe_memRespLdQ_enqP = 1'h0;
coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full = 1'h0;
coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl = 1'h0;
coreFix_memExe_reqLdQ_full_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0;
coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl = 1'h0;
coreFix_memExe_reqStQ_full_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_empty = 1'h0;
coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full = 1'h0;
coreFix_memExe_waitLrScAmoMMIOResp = 3'h2;
csrInstOrInterruptInflight_rl = 1'h0;
csrf_external_int_en_vec_0 = 1'h0;
csrf_external_int_en_vec_1 = 1'h0;
csrf_external_int_en_vec_3 = 1'h0;
csrf_external_int_pend_vec_0 = 1'h0;
csrf_external_int_pend_vec_1 = 1'h0;
csrf_external_int_pend_vec_3 = 1'h0;
csrf_fflags_reg = 5'h0A;
csrf_frm_reg = 3'h2;
csrf_fs_reg = 2'h2;
csrf_ie_vec_0 = 1'h0;
csrf_ie_vec_1 = 1'h0;
csrf_ie_vec_3 = 1'h0;
csrf_mcause_code_reg = 4'hA;
csrf_mcause_interrupt_reg = 1'h0;
csrf_mcounteren_cy_reg = 1'h0;
csrf_mcounteren_ir_reg = 1'h0;
csrf_mcounteren_tm_reg = 1'h0;
csrf_mcycle_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_medeleg_13_11_reg = 3'h2;
csrf_medeleg_15_reg = 1'h0;
csrf_medeleg_9_0_reg = 10'h2AA;
csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mideleg_11_reg = 1'h0;
csrf_mideleg_1_0_reg = 2'h2;
csrf_mideleg_5_3_reg = 3'h2;
csrf_mideleg_9_7_reg = 3'h2;
csrf_minstret_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_mpp_reg = 2'h2;
csrf_mprv_reg = 1'h0;
csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_mtvec_mode_low_reg = 1'h0;
csrf_mxr_reg = 1'h0;
csrf_ppn_reg = 44'hAAAAAAAAAAA;
csrf_prev_ie_vec_0 = 1'h0;
csrf_prev_ie_vec_1 = 1'h0;
csrf_prev_ie_vec_3 = 1'h0;
csrf_prv_reg = 2'h2;
csrf_rg_dcsr = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dpc = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_tdata1_data = 59'h2AAAAAAAAAAAAAA;
csrf_rg_tdata1_dmode = 1'h0;
csrf_rg_tdata2 = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_tdata3 = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_tselect = 64'hAAAAAAAAAAAAAAAA;
csrf_scause_code_reg = 4'hA;
csrf_scause_interrupt_reg = 1'h0;
csrf_scounteren_cy_reg = 1'h0;
csrf_scounteren_ir_reg = 1'h0;
csrf_scounteren_tm_reg = 1'h0;
csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_software_int_en_vec_0 = 1'h0;
csrf_software_int_en_vec_1 = 1'h0;
csrf_software_int_en_vec_3 = 1'h0;
csrf_software_int_pend_vec_0 = 1'h0;
csrf_software_int_pend_vec_1 = 1'h0;
csrf_software_int_pend_vec_3 = 1'h0;
csrf_spp_reg = 1'h0;
csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stats_module_doStats = 1'h0;
csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_stvec_mode_low_reg = 1'h0;
csrf_sum_reg = 1'h0;
csrf_time_reg = 64'hAAAAAAAAAAAAAAAA;
csrf_timer_int_en_vec_0 = 1'h0;
csrf_timer_int_en_vec_1 = 1'h0;
csrf_timer_int_en_vec_3 = 1'h0;
csrf_timer_int_pend_vec_0 = 1'h0;
csrf_timer_int_pend_vec_1 = 1'h0;
csrf_timer_int_pend_vec_3 = 1'h0;
csrf_tsr_reg = 1'h0;
csrf_tvm_reg = 1'h0;
csrf_tw_reg = 1'h0;
csrf_vm_mode_sv39_reg = 1'h0;
flush_brpred = 1'h0;
flush_caches = 1'h0;
flush_reservation = 1'h0;
flush_tlbs = 1'h0;
mmio_cRqQ_clearReq_rl = 1'h0;
mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_deqReq_rl = 1'h0;
mmio_cRqQ_empty = 1'h0;
mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full = 1'h0;
mmio_cRsQ_clearReq_rl = 1'h0;
mmio_cRsQ_data_0 = 1'h0;
mmio_cRsQ_deqReq_rl = 1'h0;
mmio_cRsQ_empty = 1'h0;
mmio_cRsQ_enqReq_rl = 2'h2;
mmio_cRsQ_full = 1'h0;
mmio_dataPendQ_clearReq_rl = 1'h0;
mmio_dataPendQ_deqReq_rl = 1'h0;
mmio_dataPendQ_empty = 1'h0;
mmio_dataPendQ_enqReq_rl = 1'h0;
mmio_dataPendQ_full = 1'h0;
mmio_dataReqQ_clearReq_rl = 1'h0;
mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_deqReq_rl = 1'h0;
mmio_dataReqQ_empty = 1'h0;
mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full = 1'h0;
mmio_dataRespQ_clearReq_rl = 1'h0;
mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_deqReq_rl = 1'h0;
mmio_dataRespQ_empty = 1'h0;
mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full = 1'h0;
mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmio_pRqQ_clearReq_rl = 1'h0;
mmio_pRqQ_data_0 = 39'h2AAAAAAAAA;
mmio_pRqQ_deqReq_rl = 1'h0;
mmio_pRqQ_empty = 1'h0;
mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA;
mmio_pRqQ_full = 1'h0;
mmio_pRsQ_clearReq_rl = 1'h0;
mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_deqReq_rl = 1'h0;
mmio_pRsQ_empty = 1'h0;
mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA;
mmio_pRsQ_full = 1'h0;
mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
outOfReset = 1'h0;
renameStage_rg_m_halt_req = 5'h0A;
rg_core_run_state = 2'h2;
started = 1'h0;
update_vm_info = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_outOfReset)
$fwrite(32'h80000002, "mkProc came out of reset\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2048)
$display("[Terminate CSR] being written (val = %x), ",
"send terminate signal to host",
f_csr_reqs$D_OUT[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num,
rob$deqPort_0_deq_data[425:362],
rob$deqPort_0_deq_data[361:330],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[329:325] != 5'd0 &&
rob$deqPort_0_deq_data[329:325] != 5'd1 &&
rob$deqPort_0_deq_data[329:325] != 5'd2 &&
rob$deqPort_0_deq_data[329:325] != 5'd3 &&
rob$deqPort_0_deq_data[329:325] != 5'd4 &&
rob$deqPort_0_deq_data[329:325] != 5'd5 &&
rob$deqPort_0_deq_data[329:325] != 5'd6 &&
rob$deqPort_0_deq_data[329:325] != 5'd7 &&
rob$deqPort_0_deq_data[329:325] != 5'd8 &&
rob$deqPort_0_deq_data[329:325] != 5'd9 &&
rob$deqPort_0_deq_data[329:325] != 5'd10 &&
rob$deqPort_0_deq_data[329:325] != 5'd11 &&
rob$deqPort_0_deq_data[329:325] != 5'd12 &&
rob$deqPort_0_deq_data[329:325] != 5'd13 &&
rob$deqPort_0_deq_data[329:325] != 5'd14 &&
rob$deqPort_0_deq_data[329:325] != 5'd15 &&
rob$deqPort_0_deq_data[329:325] != 5'd16 &&
rob$deqPort_0_deq_data[329:325] != 5'd17 &&
rob$deqPort_0_deq_data[329:325] != 5'd18 &&
rob$deqPort_0_deq_data[329:325] != 5'd19 &&
rob$deqPort_0_deq_data[329:325] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write(" [doCommitTrap]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num,
rob$deqPort_0_deq_data[425:362],
rob$deqPort_0_deq_data[361:330],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] != 5'd0 &&
rob$deqPort_0_deq_data[329:325] != 5'd1 &&
rob$deqPort_0_deq_data[329:325] != 5'd2 &&
rob$deqPort_0_deq_data[329:325] != 5'd3 &&
rob$deqPort_0_deq_data[329:325] != 5'd4 &&
rob$deqPort_0_deq_data[329:325] != 5'd5 &&
rob$deqPort_0_deq_data[329:325] != 5'd6 &&
rob$deqPort_0_deq_data[329:325] != 5'd7 &&
rob$deqPort_0_deq_data[329:325] != 5'd8 &&
rob$deqPort_0_deq_data[329:325] != 5'd9 &&
rob$deqPort_0_deq_data[329:325] != 5'd10 &&
rob$deqPort_0_deq_data[329:325] != 5'd11 &&
rob$deqPort_0_deq_data[329:325] != 5'd12 &&
rob$deqPort_0_deq_data[329:325] != 5'd13 &&
rob$deqPort_0_deq_data[329:325] != 5'd14 &&
rob$deqPort_0_deq_data[329:325] != 5'd15 &&
rob$deqPort_0_deq_data[329:325] != 5'd16 &&
rob$deqPort_0_deq_data[329:325] != 5'd17 &&
rob$deqPort_0_deq_data[329:325] != 5'd18 &&
rob$deqPort_0_deq_data[329:325] != 5'd19 &&
rob$deqPort_0_deq_data[329:325] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write(" [doCommitSystemInst]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[329:325] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4328_BIT_181_4403_T_ETC___d14973 == 6'd6)
$display("[Terminate CSR] being written (val = %x), ",
"send terminate signal to host",
rob$deqPort_0_deq_data[95:32]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num,
rob$deqPort_0_deq_data[425:362],
rob$deqPort_0_deq_data[361:330],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[329:325] != 5'd1 &&
rob$deqPort_0_deq_data[329:325] != 5'd2 &&
rob$deqPort_0_deq_data[329:325] != 5'd3 &&
rob$deqPort_0_deq_data[329:325] != 5'd4 &&
rob$deqPort_0_deq_data[329:325] != 5'd5 &&
rob$deqPort_0_deq_data[329:325] != 5'd6 &&
rob$deqPort_0_deq_data[329:325] != 5'd7 &&
rob$deqPort_0_deq_data[329:325] != 5'd8 &&
rob$deqPort_0_deq_data[329:325] != 5'd9 &&
rob$deqPort_0_deq_data[329:325] != 5'd10 &&
rob$deqPort_0_deq_data[329:325] != 5'd11 &&
rob$deqPort_0_deq_data[329:325] != 5'd12 &&
rob$deqPort_0_deq_data[329:325] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd0), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] != 5'd0 &&
rob$deqPort_1_deq_data[329:325] != 5'd21 &&
rob$deqPort_1_deq_data[329:325] != 5'd17 &&
rob$deqPort_1_deq_data[329:325] != 5'd18 &&
rob$deqPort_1_deq_data[329:325] != 5'd13 &&
rob$deqPort_1_deq_data[329:325] != 5'd16 &&
rob$deqPort_1_deq_data[329:325] != 5'd15 &&
rob$deqPort_1_deq_data[329:325] != 5'd19 &&
rob$deqPort_1_deq_data[329:325] != 5'd20)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serial_num_4513_PLUS_IF_rob_deq_ETC___d15438,
rob$deqPort_1_deq_data[425:362],
rob$deqPort_1_deq_data[361:330],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] != 5'd0 &&
rob$deqPort_1_deq_data[329:325] != 5'd21 &&
rob$deqPort_1_deq_data[329:325] != 5'd17 &&
rob$deqPort_1_deq_data[329:325] != 5'd18 &&
rob$deqPort_1_deq_data[329:325] != 5'd13 &&
rob$deqPort_1_deq_data[329:325] != 5'd16 &&
rob$deqPort_1_deq_data[329:325] != 5'd15 &&
rob$deqPort_1_deq_data[329:325] != 5'd19 &&
rob$deqPort_1_deq_data[329:325] != 5'd20 &&
rob$deqPort_1_deq_data[329:325] != 5'd1 &&
rob$deqPort_1_deq_data[329:325] != 5'd2 &&
rob$deqPort_1_deq_data[329:325] != 5'd3 &&
rob$deqPort_1_deq_data[329:325] != 5'd4 &&
rob$deqPort_1_deq_data[329:325] != 5'd5 &&
rob$deqPort_1_deq_data[329:325] != 5'd6 &&
rob$deqPort_1_deq_data[329:325] != 5'd7 &&
rob$deqPort_1_deq_data[329:325] != 5'd8 &&
rob$deqPort_1_deq_data[329:325] != 5'd9 &&
rob$deqPort_1_deq_data[329:325] != 5'd10 &&
rob$deqPort_1_deq_data[329:325] != 5'd11 &&
rob$deqPort_1_deq_data[329:325] != 5'd12 &&
rob$deqPort_1_deq_data[329:325] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[329:325] != 5'd0 &&
rob$deqPort_1_deq_data[329:325] != 5'd21 &&
rob$deqPort_1_deq_data[329:325] != 5'd17 &&
rob$deqPort_1_deq_data[329:325] != 5'd18 &&
rob$deqPort_1_deq_data[329:325] != 5'd13 &&
rob$deqPort_1_deq_data[329:325] != 5'd16 &&
rob$deqPort_1_deq_data[329:325] != 5'd15 &&
rob$deqPort_1_deq_data[329:325] != 5'd19 &&
rob$deqPort_1_deq_data[329:325] != 5'd20)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd1), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
v__h603882 == 2'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
end
// synopsys translate_on
endmodule // mkCore
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