Darius Rad af887627ee Update Verilog files for synthesis. ...

This mostly removes unnecessary files.  A few are updated from
bsc Verilog library files.

2019-04-09 17:45:27 -04:00

..

hdl

Update Verilog files for synthesis.

2019-04-09 17:45:27 -04:00

src

Add files for GFE integration.

2019-04-09 14:08:36 -04:00

xgui

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

component.xml

Add files for GFE integration.

2019-04-09 14:08:36 -04:00