311 lines
11 KiB
Plaintext
311 lines
11 KiB
Plaintext
// Copyright (c) 2019-2020 Bluespec, Inc.
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package MMIO_AXI4_Adapter;
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// ================================================================
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// This is an adapter to connect MIT's RISCY-OOO to an AXI4 fabric in
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// Bluespec's Toooba setup. All IO traffic to the fabric flows through
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// this. Note: a few IO addresses (e.g., MTIME, MTIMECMP, MSIP,
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// TOHOST, FROMHOST are intercepted and handled before they reach this
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// adapter).
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// ================================================================
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// BSV lib imports
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import Assert :: *;
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import ConfigReg :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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// ----------------
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// BSV additional libs
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import GetPut_Aux :: *;
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import Cur_Cycle :: *;
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import Semi_FIFOF :: *;
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import CreditCounter :: *;
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// ================================================================
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// Project imports
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// ----------------
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// From MIT RISCY-OOO
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import ProcTypes :: *;
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// ----------------
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// From Bluespec Pipes
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import AXI4 :: *;
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import SourceSink :: *;
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import Fabric_Defs :: *;
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import SoC_Map :: *;
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// ================================================================
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interface MMIO_AXI4_Adapter_IFC;
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method Action reset;
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interface Server #(MMIOCRq, MMIODataPRs) core_side;
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// Fabric master interface for IO
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interface AXI4_Master_Synth #(Wd_MId_2x3, Wd_Addr, Wd_Data,
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Wd_AW_User, Wd_W_User, Wd_B_User,
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Wd_AR_User, Wd_R_User) mmio_master;
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endinterface
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// ================================================================
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module mkMMIO_AXI4_Adapter (MMIO_AXI4_Adapter_IFC);
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// Verbosity: 0: quiet; 1: transactions
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Integer verbosity = 0;
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
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// ================================================================
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// Requests from and responses to core
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FIFOF #(MMIOCRq) f_reqs_from_core <- mkFIFOF;
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FIFOF #(MMIODataPRs) f_rsps_to_core <- mkFIFOF;
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SoC_Map_IFC soc_map <- mkSoC_Map; // for m_is_IO_addr
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// ================================================================
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// Fabric request/response
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let master_xactor <- mkAXI4_Master_Xactor;
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// For discarding write-responses
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CreditCounter_IFC #(4) ctr_wr_rsps_pending <- mkCreditCounter; // Max 15 writes outstanding
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// ================================================================
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// Functions to interact with the fabric
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// Send a read-request into the fabric
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function Action fa_fabric_send_read_req (Fabric_Addr addr);
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action
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AXI4_Size size = 8;
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let mem_req_rd_addr = AXI4_ARFlit {arid: fabric_2x3_default_mid,
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araddr: addr,
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arlen: 0, // burst len = arlen+1
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arsize: size,
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arburst: fabric_default_burst,
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arlock: fabric_default_lock,
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arcache: fabric_default_arcache,
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arprot: fabric_default_prot,
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arqos: fabric_default_qos,
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arregion: fabric_default_region,
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aruser: fabric_default_aruser};
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master_xactor.slave.ar.put(mem_req_rd_addr);
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// Debugging
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if (cfg_verbosity > 0) begin
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$display (" ", fshow (mem_req_rd_addr));
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end
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endaction
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endfunction
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// Send a write-request into the fabric
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function Action fa_fabric_send_write_req (Fabric_Addr addr, Fabric_Strb strb, Bit #(64) st_val);
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action
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AXI4_Size size = 8;
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let mem_req_wr_addr = AXI4_AWFlit {awid: fabric_2x3_default_mid,
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awaddr: addr,
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awlen: 0, // burst len = awlen+1
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awsize: size,
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awburst: fabric_default_burst,
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awlock: fabric_default_lock,
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awcache: fabric_default_awcache,
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awprot: fabric_default_prot,
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awqos: fabric_default_qos,
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awregion: fabric_default_region,
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awuser: 0};
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let mem_req_wr_data = AXI4_WFlit {wdata: st_val,
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wstrb: strb,
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wlast: True,
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wuser: 0};
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`ifdef FABRIC64
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// Work-around for a misbehavior on Xilinx UART and its
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// Xilinx AXI4 adapter. On 64-bit fabrics, for a write where
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// axsize says '8 bytes' but wstrb is for <= 4 bytes, the
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// adapter converts it two 32-bit writes, one of which has
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// wstrb=4'b0000. The Xilinx UART, in turn ignores wstrb and
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// therefore performs a spurious write. This workaround
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// changes axsize for such writes to '4 bytes', avoiding this
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// problem.
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if (strb [7:4] == 0 || strb [3:0] == 0) begin
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mem_req_wr_addr.awsize = 4;
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end
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`endif
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master_xactor.slave.aw.put (mem_req_wr_addr);
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master_xactor.slave.w.put (mem_req_wr_data);
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// Expect a fabric response
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ctr_wr_rsps_pending.incr;
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// Debugging
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/*
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if (cfg_verbosity > 0) begin
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$display (" To fabric: ", fshow (mem_req_wr_addr));
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$display (" ", fshow (mem_req_wr_data));
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end
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*/
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endaction
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endfunction
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// ================================================================
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// Handle read requests and responses.
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// Don't do a read while a write is outstanding.
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// This is just an adapter from MMIOCRq/MMIODataPRs to AXI4
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rule rl_handle_read_req (f_reqs_from_core.first.func matches Ld
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&&& (ctr_wr_rsps_pending.value == 0));
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let req <- pop (f_reqs_from_core);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_read_req: Ld request", cur_cycle);
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$display (" ", fshow (req));
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end
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// Technically the following check for legal IO addrs is not
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// necessary; the AXI4 fabric should return a DECERR for illegal
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// addrs; but not all AXI4 fabrics do the right thing.
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if (soc_map.m_is_IO_addr (req.addr))
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fa_fabric_send_read_req (req.addr);
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else begin
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let rsp = MMIODataPRs {valid: False,
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data: req.addr}; // For debugging convenience only
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f_rsps_to_core.enq (rsp);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response",
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cur_cycle);
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$display (" ", fshow (req));
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end
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end
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endrule
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// ----------------
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rule rl_handle_read_rsps;
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let mem_rsp <- get(master_xactor.slave.r);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_read_rsps ", cur_cycle);
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$display (" ", fshow (mem_rsp));
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end
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if ((cfg_verbosity > 0) && (mem_rsp.rresp != OKAY)) begin
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$display ("%0d: %m.rl_handle_read_rsp: fabric response error", cur_cycle);
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$display (" ", fshow (mem_rsp));
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end
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let rsp = MMIODataPRs {valid: (mem_rsp.rresp == OKAY),
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data: mem_rsp.rdata};
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f_rsps_to_core.enq (rsp);
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if (cfg_verbosity > 0)
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$display (" Response MMIO to core: ", fshow (rsp));
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endrule
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// ================================================================
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// Handle write requests and responses
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rule rl_handle_write_req (f_reqs_from_core.first.func matches St);
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let req <- pop (f_reqs_from_core);
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if (cfg_verbosity > 0) begin
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$display ("%d: %m.rl_handle_write_req: St request:", cur_cycle);
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$display (" ", fshow (req));
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end
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// Technically the following check for legal IO addrs is not
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// necessary; the AXI4 fabric should return a DECERR for illegal
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// addrs; but not all AXI4 fabrics do the right thing.
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if (soc_map.m_is_IO_addr (req.addr))
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fa_fabric_send_write_req (req.addr, pack (req.byteEn), req.data);
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else begin
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let rsp = MMIODataPRs {valid: False,
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data: req.addr}; // For debugging convenience only
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f_rsps_to_core.enq (rsp);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response",
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cur_cycle);
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$display (" ", fshow (req));
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end
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end
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endrule
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// ----------------
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// Discard write-responses from the fabric
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rule rl_discard_write_rsp;
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let wr_resp <- get(master_xactor.slave.b);
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if (cfg_verbosity > 0) begin
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$display ("%0d: %m.rl_discard_write_rsp", cur_cycle);
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$display (" ", fshow (wr_resp));
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end
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if (ctr_wr_rsps_pending.value == 0) begin
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$display ("%0d:%m.rl_discard_write_rsp: ERROR:unexpected Wr response (ctr_wr_rsps_pending.value == 0)",
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cur_cycle);
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$display (" ", fshow (wr_resp));
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$finish (1); // Assertion failure
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end
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ctr_wr_rsps_pending.decr;
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if (wr_resp.bresp != OKAY) begin
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// TODO: need to raise a non-maskable interrupt (NMI) here
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$display ("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.", cur_cycle);
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$display (" ", fshow (wr_resp));
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$finish (1);
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end
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else begin
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let rsp = MMIODataPRs {valid: True, data: 0};
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f_rsps_to_core.enq (rsp);
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end
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endrule
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// ================================================================
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// This adapter should only receive Ld/St requests, no Inst or AMO reqs.
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function Bool fn_is_Ld_or_St (MMIOCRq req);
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return case (req.func) matches
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Ld : True;
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St : True;
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default: False;
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endcase;
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endfunction
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rule rl_handle_non_Ld_St (! fn_is_Ld_or_St (f_reqs_from_core.first));
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let req <- pop (f_reqs_from_core);
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$display ("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.", cur_cycle);
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$display (" ", fshow (req));
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$finish (1); // Assertion failure
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endrule
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// ================================================================
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// INTERFACE
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method Action reset;
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ctr_wr_rsps_pending.clear;
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endmethod
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interface Server core_side = toGPServer (f_reqs_from_core, f_rsps_to_core);
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// Fabric master interface for IO
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interface mmio_master = master_xactor.masterSynth;
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endmodule
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// ================================================================
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endpackage
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