333 lines
11 KiB
Plaintext
333 lines
11 KiB
Plaintext
// Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved.
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//-
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// RVFI_DII modifications:
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// Copyright (c) 2018 Peter Rugg
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//-
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package Top_HW_Side;
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// ================================================================
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// mkTop_HW_Side is the top-level system for simulation.
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// mkMem_Model is a memory model.
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// **** CAVEAT FOR IVERILOG USERS: The 'C_Imports' sections below are
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// disabled for IVerilog until we find a clean solution. They depend
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// on imported C which is non-trivial in IVerilog because IVerilog
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// still depends on the older Verilog VPI standard instead of the
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// newer DPI-C standard. C-imported functions are used for:
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// UART input polling and character-reading
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// Writing tandem-verfication encoded trace data
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// (Note: UART output does not depend on C-imported functions and so
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// will work ok even in IVerilog)
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// ================================================================
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// BSV lib imports
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import GetPut :: *;
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import ClientServer :: *;
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import Connectable :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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// ================================================================
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// Project imports
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import ISA_Decls :: *;
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import TV_Info :: *;
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import SoC_Top :: *;
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import Mem_Controller :: *;
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import Mem_Model :: *;
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import Fabric_Defs :: *;
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import PLIC :: *;
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`ifndef IVERILOG
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import C_Imports :: *;
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`endif
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`ifdef INCLUDE_GDB_CONTROL
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import External_Control :: *;
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`endif
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`ifdef RVFI_DII
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import RVFI_DII :: *;
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import Types :: *;
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`endif
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// ================================================================
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// Top-level module.
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// Instantiates the SoC.
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// Instantiates a memory model.
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`ifndef RVFI_DII
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(* synthesize *)
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module mkTop_HW_Side (Empty);
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`else
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module mkPre_Top_HW_Side (Toooba_RVFI_DII_Server);
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`endif
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SoC_Top_IFC soc_top <- mkSoC_Top;
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Mem_Model_IFC mem_model <- mkMem_Model;
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// Connect SoC to raw memory
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let memCnx <- mkConnection (soc_top.to_raw_mem, mem_model.mem_server);
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// ================================================================
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// BEHAVIOR
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`ifndef RVFI_DII
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Reg #(Bool) rg_banner_printed <- mkReg (False);
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// Display a banner
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rule rl_step0 (! rg_banner_printed);
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$display ("================================================================");
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$display ("Bluespec RISC-V standalone system simulation v1.2");
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$display ("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.");
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$display ("================================================================");
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rg_banner_printed <= True;
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// Set CPU verbosity and logdelay (simulation only)
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Bool v1 <- $test$plusargs ("v1");
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Bool v2 <- $test$plusargs ("v2");
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Bit #(4) verbosity = ((v2 ? 2 : (v1 ? 1 : 0)));
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Bit #(64) logdelay = 0; // # of instructions after which to set verbosity
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soc_top.set_verbosity (verbosity, logdelay);
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// ----------------
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// Load tohost addr from symbol-table file
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`ifndef IVERILOG
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// Note: see 'CAVEAT FOR IVERILOG USERS' above
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Bool watch_tohost <- $test$plusargs ("tohost");
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let tha <- c_get_symbol_val ("tohost");
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Fabric_Addr tohost_addr = truncate (tha);
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$display ("INFO: watch_tohost = %0d, tohost_addr = 0x%0h",
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pack (watch_tohost), tohost_addr);
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soc_top.set_watch_tohost (watch_tohost, tohost_addr);
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`endif
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// ----------------
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// Open file for Tandem Verification trace output
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`ifdef INCLUDE_TANDEM_VERIF
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`ifndef IVERILOG
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// Note: see 'CAVEAT FOR IVERILOG USERS' above
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let success <- c_trace_file_open ('h_AA);
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if (success == 0) begin
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$display ("ERROR: Top_HW_Side.rl_step0: error opening trace file.");
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$display (" Aborting.");
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$finish (1);
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end
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else
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$display ("Top_HW_Side.rl_step0: opened trace file.");
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`else
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$display ("Warning: tandem verification output logs not available in IVerilog");
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`endif
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`endif
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// ----------------
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// Open connection to remote debug client
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`ifdef INCLUDE_GDB_CONTROL
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`ifndef IVERILOG
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// Note: see 'CAVEAT FOR IVERILOG USERS' above
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let dmi_status <- c_debug_client_connect (dmi_default_tcp_port);
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if (dmi_status != dmi_status_ok) begin
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$display ("ERROR: Top_HW_Side.rl_step0: error opening debug client connection.");
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$display (" Aborting.");
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$finish (1);
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end
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`else
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$display ("Warning: Debug client connection not available in IVerilog");
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`endif
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`endif
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endrule
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`endif
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// ================================================================
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// Tandem verifier: drain and output vectors of bytes
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`ifdef INCLUDE_TANDEM_VERIF
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rule rl_tv_vb_out;
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let tv_info <- soc_top.tv_verifier_info_get.get;
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let n = tv_info.num_bytes;
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let vb = tv_info.vec_bytes;
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`ifndef IVERILOG
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Bit #(32) success = 1;
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for (Bit #(32) j = 0; j < fromInteger (valueOf (TV_VB_SIZE)); j = j + 8) begin
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Bit #(64) w64 = { vb [j+7], vb [j+6], vb [j+5], vb [j+4], vb [j+3], vb [j+2], vb [j+1], vb [j] };
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let success1 <- c_trace_file_load_word64_in_buffer (j, w64);
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end
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if (success == 0)
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$display ("ERROR: Top_HW_Side.rl_tv_vb_out: error loading %0d bytes into buffer", n);
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else begin
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// Send the data
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success <- c_trace_file_write_buffer (n);
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if (success == 0)
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$display ("ERROR: Top_HW_Side.rl_tv_vb_out: error writing out bytevec data buffer (%0d bytes)", n);
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end
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if (success == 0) begin
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$finish (1);
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end
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`endif
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endrule
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`endif
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// ================================================================
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// UART console I/O
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// Relay system console output to terminal
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rule rl_relay_console_out;
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let ch <- soc_top.get_to_console.get;
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$write ("%c", ch);
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$fflush (stdout);
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endrule
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// Poll terminal input and relay any chars into system console input.
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// Note: rg_console_in_poll is used to poll only every N cycles, whenever it wraps around to 0.
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// Note: see 'CAVEAT FOR IVERILOG USERS' above for why this is ifdef'd out for iVerilog users.
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`ifndef IVERILOG
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Reg #(Bit #(12)) rg_console_in_poll <- mkReg (0);
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rule rl_relay_console_in;
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if (rg_console_in_poll == 0) begin
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Bit #(8) ch <- c_trygetchar (?);
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if (ch != 0) begin
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soc_top.put_from_console.put (ch);
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/*
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$write ("%0d: Top_HW_Side.bsv.rl_relay_console: ch = 0x%0h", cur_cycle, ch);
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if (ch >= 'h20) $write (" ('%c')", ch);
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$display ("");
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*/
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end
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end
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rg_console_in_poll <= rg_console_in_poll + 1;
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endrule
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`endif
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// ================================================================
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// Interaction with remote debug client
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`ifdef INCLUDE_GDB_CONTROL
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rule rl_debug_client_request_recv;
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Bit #(64) req <- c_debug_client_request_recv ('hAA);
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Bit #(8) status = req [63:56];
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Bit #(32) data = req [55:24];
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Bit #(16) addr = req [23:8];
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Bit #(8) op = req [7:0];
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if (status == dmi_status_err) begin
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$display ("%0d: Top_HW_Side.rl_debug_client_request_recv: receive error; aborting",
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cur_cycle);
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$finish (1);
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end
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else if (status == dmi_status_ok) begin
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// $write ("%0d: Top_HW_Side.rl_debug_client_request_recv:", cur_cycle);
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if (op == dmi_op_read) begin
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// $display (" READ 0x%0h", addr);
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let control_req = Control_Req {op: external_control_req_op_read_control_fabric,
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arg1: zeroExtend (addr),
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arg2: 0};
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soc_top.server_external_control.request.put (control_req);
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end
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else if (op == dmi_op_write) begin
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// $display (" WRITE 0x%0h 0x%0h", addr, data);
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let control_req = Control_Req {op: external_control_req_op_write_control_fabric,
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arg1: zeroExtend (addr),
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arg2: zeroExtend (data)};
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soc_top.server_external_control.request.put (control_req);
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end
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else if (op == dmi_op_shutdown) begin
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$display ("Top_HW_Side.rl_debug_client_request_recv: SHUTDOWN");
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$finish (0);
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end
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else if (op == dmi_op_start_command) begin // For debugging only
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// $display (" START COMMAND ================================");
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end
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else
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$display (" Top_HW_Side.rl_debug_client_request_recv: UNRECOGNIZED OP %0d; ignoring", op);
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end
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endrule
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rule rl_debug_client_response_send;
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let control_rsp <- soc_top.server_external_control.response.get;
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// $display ("Top_HW_Side.rl_debug_client_response_send: 0x%0h", control_rsp.result);
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let status <- c_debug_client_response_send (truncate (control_rsp.result));
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if (status == dmi_status_err) begin
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$display ("%0d: Top_HW_Side.rl_debug_client_response_send: send error; aborting",
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cur_cycle);
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$finish (1);
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end
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endrule
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`endif
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// ================================================================
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// INTERFACE
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// None (this is top-level)
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// Except RVFI_DII interface if enabled
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`ifdef RVFI_DII
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return soc_top.rvfi_dii_server;
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`endif
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endmodule
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// ================================================================
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`ifdef RVFI_DII
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// ================================================================
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// mkPiccolo_RVFI_DII instantiates the toplevel with the RVFI_DII
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// interfaces enabled, allowing testing with directly
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// ================================================================
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(* synthesize *)
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module mkTop_HW_Side(Empty)
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provisos (Add#(a__, TDiv#(DataSz,8), 8), Add#(b__, DataSz, 64), Add#(c__, TDiv#(DataSz,8), 8), Add#(d__, DataSz, 64));
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Reg #(Bool) rg_banner_printed <- mkReg (False);
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// Display a banner
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rule rl_step0 (! rg_banner_printed);
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$display ("================================================================");
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$display ("Bluespec RISC-V standalone system simulation v1.2");
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$display ("Copyright (c) 2017-2018 Bluespec, Inc. All Rights Reserved.");
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$display ("================================================================");
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rg_banner_printed <= True;
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endrule
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RVFI_DII_Bridge #(DataSz, DataSz, SEQ_LEN) bridge <- mkRVFI_DII_Bridge("", 5001);
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let dut <- mkPre_Top_HW_Side(reset_by bridge.new_rst);
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mkConnection(bridge.client.report, dut.trace_report);
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(* descending_urgency = "bridge.handleReset, rl_provide_instr" *)
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rule rl_provide_instr;
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Dii_Id req <- dut.seqReq.get;
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Bit#(32) inst <- bridge.client.getInst(req);
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dut.inst.put(tuple2(inst, req));
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endrule
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endmodule
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`endif
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// ================================================================
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endpackage: Top_HW_Side
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