0b0b863baa
This one has the advantage of being able to be called with the same flags as bsc, rather than needing to pass things through special environment variables. As a result, revert all our changes to dealing with BSC_COMPILATION_FLAGS (some of this diff therefore looks strangely formatted, but it's to match upstream verbatim, and should be left that way to minimise diffs and avoid conflicts).
92 lines
2.4 KiB
Makefile
92 lines
2.4 KiB
Makefile
### -*-Makefile-*-
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# Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
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# ================================================================
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# Macros from RISCY_HOME/procs/RV64G_OOO/Makefile
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PROC := RV64G_OOO
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# core size
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CORE_SIZE ?= SMALL
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# cache size
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CACHE_SIZE ?= SMALL
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# always include perf counter
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PERF_COUNT := true
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# dram type in simulation: VC707 or AWSF1
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SIM_DRAM_TYPE := AWSF1
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# use Xilinx FPU IP cores
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USE_XILINX_FPU ?= false
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# default 1 core
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CORE_NUM ?= 1
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# TSO or WEAK
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TSO_MM ?= false
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# Lr upgrades line to E (no forward progress guarantee)
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LR_UP_TO_E ?= false
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# Forbid LLC from respoding a load (toS) request with E state
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NO_LOAD_RESP_E ?= false
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# Use self inv cache? (only for WEAK mm), value is the max hits in D$
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SELF_INV_CACHE ?=
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# self inv D$ in case of system inst or trap
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SYSTEM_SELF_INV_L1D ?= false
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# security
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SECURITY ?= false
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SECURE_LLC ?= false
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SECURE_FLUSH ?= false
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SECURE_NONE ?= false
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SECURE_MSHR ?= false
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SECURE_ARBITER ?= false
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DISABLE_SECURE_BW ?= false
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SIM_LOG_LLC_PARTITION_NUM ?=
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SIM_LOG_LLC_MSHR_BANK_NUM ?=
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SIM_LLC_ARBITER_NUM ?=
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SIM_LLC_ARBITER_LAT ?=
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# default check cache deadlock and rename error
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CHECK_DEADLOCK ?= true
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RENAME_DEBUG ?= false
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# clk frequency depends on core size
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ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))
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USER_CLK_PERIOD ?= 24
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else ifneq (,$(filter $(CORE_SIZE),SMALL_WIDE LARGE))
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USER_CLK_PERIOD ?= 32
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else ifneq (,$(filter $(CORE_SIZE),LARGE_WIDE))
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USER_CLK_PERIOD ?= 40
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else
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$(error unsupported CORE_SIZE)
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endif
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ifeq (,$(filter $(CACHE_SIZE),TEST SMALL LARGE MC_1MB MC_2MB))
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$(error unsupported CACHE_SIZE)
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endif
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# ================================================================
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# These are taken from: RISCY_HOME/procs/scripts/Makefile.common
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XILINX_FP_FMA_LATENCY = 3
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XILINX_INT_MUL_LATENCY = 2
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BSC_COMPILATION_FLAGS += \
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-D CORE_$(CORE_SIZE) \
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-D NUM_CORES=$(CORE_NUM) \
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-D CACHE_$(CACHE_SIZE) \
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-D XILINX_FP_FMA_LATENCY=$(XILINX_FP_FMA_LATENCY) \
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-D XILINX_INT_MUL_LATENCY=$(XILINX_INT_MUL_LATENCY) \
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-D USE_BSV_BRAM_SYNC_FIFO \
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# TODO:
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# -D SELF_INV_CACHE -D L1D_MAX_HITS=$(SELF_INV_CACHE)
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# -D SYSTEM_SELF_INV_L1D
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# -D LR_UP_TO_E
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# -D NO_LOAD_RESP_E
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# various SECURITY related flags
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# -D PERF_COUNT -D CHECK_DEADLOCK -D RENAME_DEBUG ...
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# +RTS -K1G -RTS " --bscflags=" -steps-max-intervals 200 -check-assert
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# ================================================================
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