rsnikhil c278e4fe68 Fixed a bug, and a related Tandem-Verification bug, re. CSR MIP MEIP/MTIP/MSIP. ...

Two of these were not properly restricted as read-only from CSRRX instructions,
and there was a bug in the WARL function for writing MIP,
and there was a bug in the TV-reporting of MIP updates.

2020-03-12 21:44:00 -04:00

..

BSV_Additional_Libs

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00

Core

Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR.

2020-03-08 21:29:30 -04:00

CPU

Fixed a bug, and a related Tandem-Verification bug, re. CSR MIP MEIP/MTIP/MSIP.

2020-03-12 21:44:00 -04:00

Debug_Module

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

ISA

Fixed a Tandem Verification trace generation bug for FMV.X.F and FMV.X.D

2020-03-09 14:47:20 -04:00

PLIC

Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below)

2020-03-08 15:39:57 -04:00

RISCY_OOO

Improved avoidance of initial timer interrupt in MMIOPlatform; removed spurios MSTATUS TV report on CSRRS/C with rs1==0

2020-03-11 22:42:18 -04:00