Jessica Clarke c7bd60b47e CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING ...

They always exist, just WARL so can be hard-wired.

2021-02-28 01:11:39 +00:00

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BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Adapt the PLIC instantiation and wiring to support multiple cores

2021-01-31 17:54:43 +00:00

CPU

Fix AXI_Size=16 for MMIO of caps

2021-02-19 17:19:47 +00:00

Debug_Module

Multicore debug cleanups

2021-01-21 20:51:02 +00:00

ISA

Add CSetEqualExact

2021-02-22 17:44:36 +00:00

PLIC

Adapt the PLIC instantiation and wiring to support multiple cores

2021-01-31 17:54:43 +00:00

RISCY_OOO

CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING

2021-02-28 01:11:39 +00:00