251 lines
7.9 KiB
Plaintext
251 lines
7.9 KiB
Plaintext
// Copyright (c) 2018-2020 Bluespec, Inc. All Rights Reserved.
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package TV_Taps;
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// ================================================================
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// This package defines 'taps' on connections between
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// - DM and CPU, on which DM accesses CPU GPRs, FPRs and CSRs
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// - DM and memory bus, on which DM accesses memory
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// Each tap snoops 'writes', and produces a corresponsing Trace_Data
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// write-memory command for the Tandem Verifier, so that it keeps its
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// GPRs, FPRs, CSRs and memories in sync.
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// ================================================================
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// BSV library imports
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import Assert :: *;
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import BUtils :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Connectable :: *;
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// ----------------
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// BSV additional libs
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import Semi_FIFOF :: *;
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import GetPut_Aux :: *;
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// ================================================================
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// Project imports
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import ISA_Decls :: *;
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import DM_CPU_Req_Rsp :: *;
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import TV_Info :: *;
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import AXI4_Types :: *;
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import Fabric_Defs :: *;
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// ================================================================
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// DM-to-memory tap
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interface DM_Mem_Tap_IFC;
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interface AXI4_Slave_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave;
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interface AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master;
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interface Get #(Trace_Data) trace_data_out;
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endinterface
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(* synthesize *)
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module mkDM_Mem_Tap (DM_Mem_Tap_IFC);
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// Transactor facing DM
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AXI4_Slave_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) slave_xactor <- mkAXI4_Slave_Xactor;
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// Transactor facing memory bus
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AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor;
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// Tap output
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FIFOF #(Trace_Data) f_trace_data <- mkFIFOF;
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// ----------------
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// AXI requests
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// Snoop write requests
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rule write_reqs;
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let wr_addr = slave_xactor.o_wr_addr.first;
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slave_xactor.o_wr_addr.deq;
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let wr_data = slave_xactor.o_wr_data.first;
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slave_xactor.o_wr_data.deq;
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// Pass-through
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master_xactor.i_wr_addr.enq (wr_addr);
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master_xactor.i_wr_data.enq (wr_data);
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// Tap
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Bit #(64) paddr = ?;
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Bit #(64) stval = ?;
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Integer sh = 0;
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Fabric_Data mask = 0;
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MemReqSize sz = ?;
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case (wr_data.wstrb)
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`ifdef FABRIC64
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'hFF: begin sh= 0; mask = 'hFFFF_FFFF_FFFF_FFFF; sz=f3_SIZE_D; end
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'hF0: begin sh=32; mask = 'hFFFF_FFFF; sz=f3_SIZE_W; end
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'hC0: begin sh=48; mask = 'hFFFF; sz=f3_SIZE_H; end
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'h30: begin sh=32; mask = 'hFFFF; sz=f3_SIZE_H; end
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'h80: begin sh=56; mask = 'hFF; sz=f3_SIZE_B; end
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'h40: begin sh=48; mask = 'hFF; sz=f3_SIZE_B; end
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'h20: begin sh=40; mask = 'hFF; sz=f3_SIZE_B; end
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'h10: begin sh=32; mask = 'hFF; sz=f3_SIZE_B; end
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`endif
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'hF: begin sh= 0; mask = 'hFFFF_FFFF; sz=f3_SIZE_W; end
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'hC: begin sh=16; mask = 'hFFFF; sz=f3_SIZE_H; end
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'h3: begin sh= 0; mask = 'hFFFF; sz=f3_SIZE_H; end
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'h8: begin sh=24; mask = 'hFF; sz=f3_SIZE_B; end
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'h4: begin sh=16; mask = 'hFF; sz=f3_SIZE_B; end
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'h2: begin sh= 8; mask = 'hFF; sz=f3_SIZE_B; end
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'h1: begin sh= 0; mask = 'hFF; sz=f3_SIZE_B; end
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default: dynamicAssert(False, "mkDM_Mem_Tap: unsupported byte enables");
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endcase
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paddr = zeroExtend (wr_addr.awaddr);
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stval = ((zeroExtend (wr_data.wdata) >> sh) & mask);
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Trace_Data td = mkTrace_MEM_WRITE (sz, truncate (stval), paddr);
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f_trace_data.enq (td);
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endrule
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// Read requests, write responses and read responses are not snooped
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mkConnection (slave_xactor.o_rd_addr, master_xactor.i_rd_addr);
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mkConnection (slave_xactor.i_wr_resp, master_xactor.o_wr_resp);
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mkConnection (slave_xactor.i_rd_data, master_xactor.o_rd_data);
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// ================================================================
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// INTERFACE
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// Facing DM
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interface slave = slave_xactor.axi_side;
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// Facing bus
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interface master = master_xactor.axi_side;
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// Tap towards verifier
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interface Get trace_data_out = toGet (f_trace_data);
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endmodule: mkDM_Mem_Tap
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// ================================================================
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// DM-to-CPU GPR tap (for writes to GPRs)
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interface DM_GPR_Tap_IFC;
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interface Client #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) client;
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interface Server #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) server;
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interface Get #(Trace_Data) trace_data_out;
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endinterface
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(* synthesize *)
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module mkDM_GPR_Tap (DM_GPR_Tap_IFC);
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// req from DM
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FIFOF #(DM_CPU_Req #(5, XLEN)) f_req_in <- mkFIFOF;
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// req to CPU
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FIFOF #(DM_CPU_Req #(5, XLEN)) f_req_out <- mkFIFOF;
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// resp CPU->DM
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FIFOF #(DM_CPU_Rsp #(XLEN)) f_rsp <- mkFIFOF;
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// Tap to TV
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FIFOF #(Trace_Data) f_trace_data <- mkFIFOF;
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rule request;
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let req <- pop (f_req_in);
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// Pass-through to CPU
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f_req_out.enq(req);
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// Snoop writes and send trace data to TV
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if (req.write) begin
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Trace_Data td;
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td = mkTrace_GPR_WRITE (req.address, req.data);
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f_trace_data.enq (td);
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end
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endrule
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interface Client client = toGPClient (f_req_out, f_rsp);
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interface Server server = toGPServer (f_req_in, f_rsp);
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interface Get trace_data_out = toGet (f_trace_data);
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endmodule: mkDM_GPR_Tap
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// ================================================================
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// DM-to-CPU FPR tap (for writes to FPRs)
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`ifdef ISA_F_OR_D
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interface DM_FPR_Tap_IFC;
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interface Client #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) client;
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interface Server #(DM_CPU_Req #(5, XLEN), DM_CPU_Rsp #(XLEN)) server;
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interface Get #(Trace_Data) trace_data_out;
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endinterface
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(* synthesize *)
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module mkDM_FPR_Tap (DM_FPR_Tap_IFC);
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// req from DM
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FIFOF #(DM_CPU_Req #(5, XLEN)) f_req_in <- mkFIFOF;
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// req to CPU
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FIFOF #(DM_CPU_Req #(5, XLEN)) f_req_out <- mkFIFOF;
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// resp CPU->DM
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FIFOF #(DM_CPU_Rsp #(XLEN)) f_rsp <- mkFIFOF;
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// Tap to TV
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FIFOF #(Trace_Data) f_trace_data <- mkFIFOF;
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rule request;
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let req <- pop (f_req_in);
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// Pass-through to CPU
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f_req_out.enq(req);
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// Snoop writes and send trace data to TV
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if (req.write) begin
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Trace_Data td;
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td = mkTrace_FPR_WRITE (req.address, req.data);
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f_trace_data.enq (td);
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end
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endrule
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interface Client client = toGPClient (f_req_out, f_rsp);
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interface Server server = toGPServer (f_req_in, f_rsp);
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interface Get trace_data_out = toGet (f_trace_data);
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endmodule: mkDM_FPR_Tap
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`endif
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// ================================================================
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// DM-to-CPU CSR tap (for writes to CSRs)
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interface DM_CSR_Tap_IFC;
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interface Client #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) client;
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interface Server #(DM_CPU_Req #(12, XLEN), DM_CPU_Rsp #(XLEN)) server;
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interface Get #(Trace_Data) trace_data_out;
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endinterface
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(* synthesize *)
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module mkDM_CSR_Tap (DM_CSR_Tap_IFC);
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// req from DM
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FIFOF #(DM_CPU_Req #(12, XLEN)) f_req_in <- mkFIFOF;
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// req to CPU
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FIFOF #(DM_CPU_Req #(12, XLEN)) f_req_out <- mkFIFOF;
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// resp CPU->DM
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FIFOF #(DM_CPU_Rsp #(XLEN)) f_rsp <- mkFIFOF;
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// Tap to TV
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FIFOF #(Trace_Data) f_trace_data <- mkFIFOF;
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rule request;
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let req <- pop (f_req_in);
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// Pass-through to CPU
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f_req_out.enq(req);
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// Snoop writes and send trace data to TV
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if (req.write) begin
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Trace_Data td = mkTrace_CSR_WRITE (req.address, req.data);
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f_trace_data.enq (td);
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end
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endrule
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interface Client client = toGPClient (f_req_out, f_rsp);
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interface Server server = toGPServer (f_req_in, f_rsp);
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interface Get trace_data_out = toGet (f_trace_data);
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endmodule: mkDM_CSR_Tap
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// ================================================================
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endpackage
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