2430 lines
98 KiB
Verilog
2430 lines
98 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// mmio_req O 65
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// RDY_mmio_req O 1
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// to_mem_memReq_notEmpty O 1
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// RDY_to_mem_memReq_notEmpty O 1 const
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// RDY_to_mem_memReq_deq O 1
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// to_mem_memReq_first O 640 reg
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// RDY_to_mem_memReq_first O 1
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// to_mem_respSt_notFull O 1
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// RDY_to_mem_respSt_notFull O 1 const
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// RDY_to_mem_respSt_enq O 1
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// RDY_hostReq_wrAddr O 1
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// RDY_hostReq_wrData O 1
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// hostIndInv_start O 64
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// RDY_hostIndInv_start O 1
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// RDY_hostIndInv_wrDone O 1
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// CLK_portalClk I 1 clock
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// RST_N_portalRst I 1 reset
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// CLK I 1 clock
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// RST_N I 1 reset
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// mmio_req_offset I 1
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// mmio_req_wrBE I 8
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// mmio_req_wrData I 64
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// hostReq_wrAddr_valid I 1
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// hostReq_wrAddr_addr I 64
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// hostReq_wrData_data I 64
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// hostReq_wrData_byteEn I 8
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// hostReq_wrData_last I 1
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// EN_to_mem_memReq_deq I 1
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// EN_to_mem_respSt_enq I 1
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// EN_hostReq_wrAddr I 1
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// EN_hostReq_wrData I 1
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// EN_hostIndInv_wrDone I 1
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// EN_mmio_req I 1
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// EN_hostIndInv_start I 1
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//
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// Combinational paths from inputs to outputs:
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// (mmio_req_offset, mmio_req_wrBE) -> mmio_req
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkMemLoader(CLK_portalClk,
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RST_N_portalRst,
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CLK,
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RST_N,
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mmio_req_offset,
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mmio_req_wrBE,
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mmio_req_wrData,
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EN_mmio_req,
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mmio_req,
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RDY_mmio_req,
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to_mem_memReq_notEmpty,
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RDY_to_mem_memReq_notEmpty,
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EN_to_mem_memReq_deq,
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RDY_to_mem_memReq_deq,
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to_mem_memReq_first,
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RDY_to_mem_memReq_first,
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to_mem_respSt_notFull,
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RDY_to_mem_respSt_notFull,
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EN_to_mem_respSt_enq,
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RDY_to_mem_respSt_enq,
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hostReq_wrAddr_valid,
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hostReq_wrAddr_addr,
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EN_hostReq_wrAddr,
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RDY_hostReq_wrAddr,
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hostReq_wrData_data,
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hostReq_wrData_byteEn,
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hostReq_wrData_last,
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EN_hostReq_wrData,
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RDY_hostReq_wrData,
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EN_hostIndInv_start,
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hostIndInv_start,
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RDY_hostIndInv_start,
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EN_hostIndInv_wrDone,
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RDY_hostIndInv_wrDone);
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input CLK_portalClk;
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input RST_N_portalRst;
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input CLK;
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input RST_N;
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// actionvalue method mmio_req
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input mmio_req_offset;
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input [7 : 0] mmio_req_wrBE;
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input [63 : 0] mmio_req_wrData;
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input EN_mmio_req;
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output [64 : 0] mmio_req;
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output RDY_mmio_req;
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// value method to_mem_memReq_notEmpty
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output to_mem_memReq_notEmpty;
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output RDY_to_mem_memReq_notEmpty;
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// action method to_mem_memReq_deq
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input EN_to_mem_memReq_deq;
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output RDY_to_mem_memReq_deq;
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// value method to_mem_memReq_first
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output [639 : 0] to_mem_memReq_first;
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output RDY_to_mem_memReq_first;
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// value method to_mem_respSt_notFull
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output to_mem_respSt_notFull;
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output RDY_to_mem_respSt_notFull;
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// action method to_mem_respSt_enq
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input EN_to_mem_respSt_enq;
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output RDY_to_mem_respSt_enq;
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// action method hostReq_wrAddr
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input hostReq_wrAddr_valid;
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input [63 : 0] hostReq_wrAddr_addr;
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input EN_hostReq_wrAddr;
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output RDY_hostReq_wrAddr;
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// action method hostReq_wrData
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input [63 : 0] hostReq_wrData_data;
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input [7 : 0] hostReq_wrData_byteEn;
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input hostReq_wrData_last;
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input EN_hostReq_wrData;
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output RDY_hostReq_wrData;
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// actionvalue method hostIndInv_start
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input EN_hostIndInv_start;
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output [63 : 0] hostIndInv_start;
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output RDY_hostIndInv_start;
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// action method hostIndInv_wrDone
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input EN_hostIndInv_wrDone;
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output RDY_hostIndInv_wrDone;
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// signals for module outputs
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wire [639 : 0] to_mem_memReq_first;
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wire [64 : 0] mmio_req;
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wire [63 : 0] hostIndInv_start;
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wire RDY_hostIndInv_start,
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RDY_hostIndInv_wrDone,
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RDY_hostReq_wrAddr,
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RDY_hostReq_wrData,
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RDY_mmio_req,
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RDY_to_mem_memReq_deq,
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RDY_to_mem_memReq_first,
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RDY_to_mem_memReq_notEmpty,
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RDY_to_mem_respSt_enq,
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RDY_to_mem_respSt_notFull,
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to_mem_memReq_notEmpty,
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to_mem_respSt_notFull;
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// inlined wires
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wire [640 : 0] memReqQ_enqReq_lat_0$wget;
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wire memReqQ_enqReq_lat_0$whas;
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// register busy
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reg busy;
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wire busy$D_IN, busy$EN;
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// register expectWrData
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reg expectWrData;
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wire expectWrData$D_IN, expectWrData$EN;
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// register hostStartQ_q_rRdPtr_rdCounter
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reg [1 : 0] hostStartQ_q_rRdPtr_rdCounter;
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wire [1 : 0] hostStartQ_q_rRdPtr_rdCounter$D_IN;
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wire hostStartQ_q_rRdPtr_rdCounter$EN;
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// register hostStartQ_q_rRdPtr_rdCounterPre
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reg [1 : 0] hostStartQ_q_rRdPtr_rdCounterPre;
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wire [1 : 0] hostStartQ_q_rRdPtr_rdCounterPre$D_IN;
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wire hostStartQ_q_rRdPtr_rdCounterPre$EN;
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// register hostStartQ_q_rRdPtr_rsCounter
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reg [1 : 0] hostStartQ_q_rRdPtr_rsCounter;
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wire [1 : 0] hostStartQ_q_rRdPtr_rsCounter$D_IN;
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wire hostStartQ_q_rRdPtr_rsCounter$EN;
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// register hostStartQ_q_rWrPtr_rdCounter
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reg [1 : 0] hostStartQ_q_rWrPtr_rdCounter;
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wire [1 : 0] hostStartQ_q_rWrPtr_rdCounter$D_IN;
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wire hostStartQ_q_rWrPtr_rdCounter$EN;
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// register hostStartQ_q_rWrPtr_rdCounterPre
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reg [1 : 0] hostStartQ_q_rWrPtr_rdCounterPre;
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wire [1 : 0] hostStartQ_q_rWrPtr_rdCounterPre$D_IN;
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wire hostStartQ_q_rWrPtr_rdCounterPre$EN;
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// register hostStartQ_q_rWrPtr_rsCounter
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reg [1 : 0] hostStartQ_q_rWrPtr_rsCounter;
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wire [1 : 0] hostStartQ_q_rWrPtr_rsCounter$D_IN;
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wire hostStartQ_q_rWrPtr_rsCounter$EN;
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// register hostWrAddrQ_q_rRdPtr_rdCounter
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reg [1 : 0] hostWrAddrQ_q_rRdPtr_rdCounter;
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wire [1 : 0] hostWrAddrQ_q_rRdPtr_rdCounter$D_IN;
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wire hostWrAddrQ_q_rRdPtr_rdCounter$EN;
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// register hostWrAddrQ_q_rRdPtr_rdCounterPre
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reg [1 : 0] hostWrAddrQ_q_rRdPtr_rdCounterPre;
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wire [1 : 0] hostWrAddrQ_q_rRdPtr_rdCounterPre$D_IN;
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wire hostWrAddrQ_q_rRdPtr_rdCounterPre$EN;
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// register hostWrAddrQ_q_rRdPtr_rsCounter
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reg [1 : 0] hostWrAddrQ_q_rRdPtr_rsCounter;
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wire [1 : 0] hostWrAddrQ_q_rRdPtr_rsCounter$D_IN;
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wire hostWrAddrQ_q_rRdPtr_rsCounter$EN;
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// register hostWrAddrQ_q_rWrPtr_rdCounter
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reg [1 : 0] hostWrAddrQ_q_rWrPtr_rdCounter;
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wire [1 : 0] hostWrAddrQ_q_rWrPtr_rdCounter$D_IN;
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wire hostWrAddrQ_q_rWrPtr_rdCounter$EN;
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// register hostWrAddrQ_q_rWrPtr_rdCounterPre
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reg [1 : 0] hostWrAddrQ_q_rWrPtr_rdCounterPre;
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wire [1 : 0] hostWrAddrQ_q_rWrPtr_rdCounterPre$D_IN;
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wire hostWrAddrQ_q_rWrPtr_rdCounterPre$EN;
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// register hostWrAddrQ_q_rWrPtr_rsCounter
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reg [1 : 0] hostWrAddrQ_q_rWrPtr_rsCounter;
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wire [1 : 0] hostWrAddrQ_q_rWrPtr_rsCounter$D_IN;
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wire hostWrAddrQ_q_rWrPtr_rsCounter$EN;
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// register hostWrDataQ_q_rRdPtr_rdCounter
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reg [1 : 0] hostWrDataQ_q_rRdPtr_rdCounter;
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wire [1 : 0] hostWrDataQ_q_rRdPtr_rdCounter$D_IN;
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wire hostWrDataQ_q_rRdPtr_rdCounter$EN;
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// register hostWrDataQ_q_rRdPtr_rdCounterPre
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reg [1 : 0] hostWrDataQ_q_rRdPtr_rdCounterPre;
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wire [1 : 0] hostWrDataQ_q_rRdPtr_rdCounterPre$D_IN;
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wire hostWrDataQ_q_rRdPtr_rdCounterPre$EN;
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// register hostWrDataQ_q_rRdPtr_rsCounter
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reg [1 : 0] hostWrDataQ_q_rRdPtr_rsCounter;
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wire [1 : 0] hostWrDataQ_q_rRdPtr_rsCounter$D_IN;
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wire hostWrDataQ_q_rRdPtr_rsCounter$EN;
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// register hostWrDataQ_q_rWrPtr_rdCounter
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reg [1 : 0] hostWrDataQ_q_rWrPtr_rdCounter;
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wire [1 : 0] hostWrDataQ_q_rWrPtr_rdCounter$D_IN;
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wire hostWrDataQ_q_rWrPtr_rdCounter$EN;
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// register hostWrDataQ_q_rWrPtr_rdCounterPre
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reg [1 : 0] hostWrDataQ_q_rWrPtr_rdCounterPre;
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wire [1 : 0] hostWrDataQ_q_rWrPtr_rdCounterPre$D_IN;
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wire hostWrDataQ_q_rWrPtr_rdCounterPre$EN;
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// register hostWrDataQ_q_rWrPtr_rsCounter
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reg [1 : 0] hostWrDataQ_q_rWrPtr_rsCounter;
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wire [1 : 0] hostWrDataQ_q_rWrPtr_rsCounter$D_IN;
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wire hostWrDataQ_q_rWrPtr_rsCounter$EN;
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// register hostWrDoneQ_q_rRdPtr_rdCounter
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reg [1 : 0] hostWrDoneQ_q_rRdPtr_rdCounter;
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wire [1 : 0] hostWrDoneQ_q_rRdPtr_rdCounter$D_IN;
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wire hostWrDoneQ_q_rRdPtr_rdCounter$EN;
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// register hostWrDoneQ_q_rRdPtr_rdCounterPre
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reg [1 : 0] hostWrDoneQ_q_rRdPtr_rdCounterPre;
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wire [1 : 0] hostWrDoneQ_q_rRdPtr_rdCounterPre$D_IN;
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wire hostWrDoneQ_q_rRdPtr_rdCounterPre$EN;
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// register hostWrDoneQ_q_rRdPtr_rsCounter
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reg [1 : 0] hostWrDoneQ_q_rRdPtr_rsCounter;
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wire [1 : 0] hostWrDoneQ_q_rRdPtr_rsCounter$D_IN;
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wire hostWrDoneQ_q_rRdPtr_rsCounter$EN;
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// register hostWrDoneQ_q_rWrPtr_rdCounter
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reg [1 : 0] hostWrDoneQ_q_rWrPtr_rdCounter;
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wire [1 : 0] hostWrDoneQ_q_rWrPtr_rdCounter$D_IN;
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wire hostWrDoneQ_q_rWrPtr_rdCounter$EN;
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// register hostWrDoneQ_q_rWrPtr_rdCounterPre
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reg [1 : 0] hostWrDoneQ_q_rWrPtr_rdCounterPre;
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wire [1 : 0] hostWrDoneQ_q_rWrPtr_rdCounterPre$D_IN;
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wire hostWrDoneQ_q_rWrPtr_rdCounterPre$EN;
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// register hostWrDoneQ_q_rWrPtr_rsCounter
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reg [1 : 0] hostWrDoneQ_q_rWrPtr_rsCounter;
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wire [1 : 0] hostWrDoneQ_q_rWrPtr_rsCounter$D_IN;
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wire hostWrDoneQ_q_rWrPtr_rsCounter$EN;
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// register memReqQ_clearReq_rl
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reg memReqQ_clearReq_rl;
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wire memReqQ_clearReq_rl$D_IN, memReqQ_clearReq_rl$EN;
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// register memReqQ_data_0
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reg [639 : 0] memReqQ_data_0;
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wire [639 : 0] memReqQ_data_0$D_IN;
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wire memReqQ_data_0$EN;
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// register memReqQ_deqReq_rl
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reg memReqQ_deqReq_rl;
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wire memReqQ_deqReq_rl$D_IN, memReqQ_deqReq_rl$EN;
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// register memReqQ_empty
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reg memReqQ_empty;
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wire memReqQ_empty$D_IN, memReqQ_empty$EN;
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// register memReqQ_enqReq_rl
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reg [640 : 0] memReqQ_enqReq_rl;
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wire [640 : 0] memReqQ_enqReq_rl$D_IN;
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wire memReqQ_enqReq_rl$EN;
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// register memReqQ_full
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reg memReqQ_full;
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wire memReqQ_full$D_IN, memReqQ_full$EN;
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// register memStartAddr
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reg [63 : 0] memStartAddr;
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wire [63 : 0] memStartAddr$D_IN;
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wire memStartAddr$EN;
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// register pendStCnt
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reg [7 : 0] pendStCnt;
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reg [7 : 0] pendStCnt$D_IN;
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wire pendStCnt$EN;
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// register reqAddr
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reg [57 : 0] reqAddr;
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wire [57 : 0] reqAddr$D_IN;
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wire reqAddr$EN;
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// register reqBE
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reg [63 : 0] reqBE;
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wire [63 : 0] reqBE$D_IN;
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wire reqBE$EN;
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// register reqData
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reg [511 : 0] reqData;
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wire [511 : 0] reqData$D_IN;
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wire reqData$EN;
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// register reqSel
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reg [2 : 0] reqSel;
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wire [2 : 0] reqSel$D_IN;
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wire reqSel$EN;
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// register respStQ_clearReq_rl
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reg respStQ_clearReq_rl;
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wire respStQ_clearReq_rl$D_IN, respStQ_clearReq_rl$EN;
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// register respStQ_deqReq_rl
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reg respStQ_deqReq_rl;
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wire respStQ_deqReq_rl$D_IN, respStQ_deqReq_rl$EN;
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// register respStQ_empty
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reg respStQ_empty;
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wire respStQ_empty$D_IN, respStQ_empty$EN;
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// register respStQ_enqReq_rl
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reg respStQ_enqReq_rl;
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wire respStQ_enqReq_rl$D_IN, respStQ_enqReq_rl$EN;
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// register respStQ_full
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reg respStQ_full;
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wire respStQ_full$D_IN, respStQ_full$EN;
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// register writing
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reg writing;
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wire writing$D_IN, writing$EN;
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// ports of submodule hostStartQ_dstGuard
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wire hostStartQ_dstGuard$IS_READY;
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// ports of submodule hostStartQ_q_memory
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wire [63 : 0] hostStartQ_q_memory$DIA,
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hostStartQ_q_memory$DIB,
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hostStartQ_q_memory$DOB;
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wire hostStartQ_q_memory$ADDRA,
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hostStartQ_q_memory$ADDRB,
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hostStartQ_q_memory$ENA,
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hostStartQ_q_memory$ENB,
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hostStartQ_q_memory$WEA,
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hostStartQ_q_memory$WEB;
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// ports of submodule hostStartQ_srcGuard
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wire hostStartQ_srcGuard$IS_READY;
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// ports of submodule hostWrAddrQ_dstGuard
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wire hostWrAddrQ_dstGuard$IS_READY;
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// ports of submodule hostWrAddrQ_q_memory
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wire [64 : 0] hostWrAddrQ_q_memory$DIA,
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hostWrAddrQ_q_memory$DIB,
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hostWrAddrQ_q_memory$DOB;
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wire hostWrAddrQ_q_memory$ADDRA,
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hostWrAddrQ_q_memory$ADDRB,
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hostWrAddrQ_q_memory$ENA,
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hostWrAddrQ_q_memory$ENB,
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hostWrAddrQ_q_memory$WEA,
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hostWrAddrQ_q_memory$WEB;
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// ports of submodule hostWrAddrQ_srcGuard
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wire hostWrAddrQ_srcGuard$IS_READY;
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// ports of submodule hostWrDataQ_dstGuard
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wire hostWrDataQ_dstGuard$IS_READY;
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// ports of submodule hostWrDataQ_q_memory
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wire [72 : 0] hostWrDataQ_q_memory$DIA,
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hostWrDataQ_q_memory$DIB,
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hostWrDataQ_q_memory$DOB;
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wire hostWrDataQ_q_memory$ADDRA,
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hostWrDataQ_q_memory$ADDRB,
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hostWrDataQ_q_memory$ENA,
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hostWrDataQ_q_memory$ENB,
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hostWrDataQ_q_memory$WEA,
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hostWrDataQ_q_memory$WEB;
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// ports of submodule hostWrDataQ_srcGuard
|
|
wire hostWrDataQ_srcGuard$IS_READY;
|
|
|
|
// ports of submodule hostWrDoneQ_dstGuard
|
|
wire hostWrDoneQ_dstGuard$IS_READY;
|
|
|
|
// ports of submodule hostWrDoneQ_q_memory
|
|
wire hostWrDoneQ_q_memory$ADDRA,
|
|
hostWrDoneQ_q_memory$ADDRB,
|
|
hostWrDoneQ_q_memory$DIA,
|
|
hostWrDoneQ_q_memory$DIB,
|
|
hostWrDoneQ_q_memory$ENA,
|
|
hostWrDoneQ_q_memory$ENB,
|
|
hostWrDoneQ_q_memory$WEA,
|
|
hostWrDoneQ_q_memory$WEB;
|
|
|
|
// ports of submodule hostWrDoneQ_srcGuard
|
|
wire hostWrDoneQ_srcGuard$IS_READY;
|
|
|
|
// ports of submodule memReqQ_clearReq_dummy2_0
|
|
wire memReqQ_clearReq_dummy2_0$D_IN, memReqQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule memReqQ_clearReq_dummy2_1
|
|
wire memReqQ_clearReq_dummy2_1$D_IN,
|
|
memReqQ_clearReq_dummy2_1$EN,
|
|
memReqQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule memReqQ_deqReq_dummy2_0
|
|
wire memReqQ_deqReq_dummy2_0$D_IN, memReqQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule memReqQ_deqReq_dummy2_1
|
|
wire memReqQ_deqReq_dummy2_1$D_IN, memReqQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule memReqQ_deqReq_dummy2_2
|
|
wire memReqQ_deqReq_dummy2_2$D_IN,
|
|
memReqQ_deqReq_dummy2_2$EN,
|
|
memReqQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule memReqQ_enqReq_dummy2_0
|
|
wire memReqQ_enqReq_dummy2_0$D_IN, memReqQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule memReqQ_enqReq_dummy2_1
|
|
wire memReqQ_enqReq_dummy2_1$D_IN, memReqQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule memReqQ_enqReq_dummy2_2
|
|
wire memReqQ_enqReq_dummy2_2$D_IN,
|
|
memReqQ_enqReq_dummy2_2$EN,
|
|
memReqQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule respStQ_clearReq_dummy2_0
|
|
wire respStQ_clearReq_dummy2_0$D_IN, respStQ_clearReq_dummy2_0$EN;
|
|
|
|
// ports of submodule respStQ_clearReq_dummy2_1
|
|
wire respStQ_clearReq_dummy2_1$D_IN,
|
|
respStQ_clearReq_dummy2_1$EN,
|
|
respStQ_clearReq_dummy2_1$Q_OUT;
|
|
|
|
// ports of submodule respStQ_deqReq_dummy2_0
|
|
wire respStQ_deqReq_dummy2_0$D_IN, respStQ_deqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule respStQ_deqReq_dummy2_1
|
|
wire respStQ_deqReq_dummy2_1$D_IN, respStQ_deqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule respStQ_deqReq_dummy2_2
|
|
wire respStQ_deqReq_dummy2_2$D_IN,
|
|
respStQ_deqReq_dummy2_2$EN,
|
|
respStQ_deqReq_dummy2_2$Q_OUT;
|
|
|
|
// ports of submodule respStQ_enqReq_dummy2_0
|
|
wire respStQ_enqReq_dummy2_0$D_IN, respStQ_enqReq_dummy2_0$EN;
|
|
|
|
// ports of submodule respStQ_enqReq_dummy2_1
|
|
wire respStQ_enqReq_dummy2_1$D_IN, respStQ_enqReq_dummy2_1$EN;
|
|
|
|
// ports of submodule respStQ_enqReq_dummy2_2
|
|
wire respStQ_enqReq_dummy2_2$D_IN,
|
|
respStQ_enqReq_dummy2_2$EN,
|
|
respStQ_enqReq_dummy2_2$Q_OUT;
|
|
|
|
// rule scheduling signals
|
|
wire CAN_FIRE_RL_doNewWrite,
|
|
CAN_FIRE_RL_doStReq,
|
|
CAN_FIRE_RL_doStResp,
|
|
CAN_FIRE_RL_hostStartQ_q_portA,
|
|
CAN_FIRE_RL_hostStartQ_q_portB,
|
|
CAN_FIRE_RL_hostStartQ_q_portB_read_data,
|
|
CAN_FIRE_RL_hostStartQ_q_rRdPtr_do_decrement,
|
|
CAN_FIRE_RL_hostStartQ_q_rRdPtr_do_increment,
|
|
CAN_FIRE_RL_hostStartQ_q_rRdPtr_synchronizer,
|
|
CAN_FIRE_RL_hostStartQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_hostStartQ_q_rWrPtr_do_decrement,
|
|
CAN_FIRE_RL_hostStartQ_q_rWrPtr_do_increment,
|
|
CAN_FIRE_RL_hostStartQ_q_rWrPtr_synchronizer,
|
|
CAN_FIRE_RL_hostStartQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_portA,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_portB,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_portB_read_data,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_decrement,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_increment,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_synchronizer,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_decrement,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_increment,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_synchronizer,
|
|
CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_hostWrDataQ_q_portA,
|
|
CAN_FIRE_RL_hostWrDataQ_q_portB,
|
|
CAN_FIRE_RL_hostWrDataQ_q_portB_read_data,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_do_decrement,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_do_increment,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_synchronizer,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_do_decrement,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_do_increment,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_synchronizer,
|
|
CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_portA,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_portB,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_portB_read_data,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_decrement,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_increment,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_synchronizer,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_decrement,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_increment,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_synchronizer,
|
|
CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
CAN_FIRE_RL_memReqQ_canonicalize,
|
|
CAN_FIRE_RL_memReqQ_clearReq_canon,
|
|
CAN_FIRE_RL_memReqQ_deqReq_canon,
|
|
CAN_FIRE_RL_memReqQ_enqReq_canon,
|
|
CAN_FIRE_RL_respStQ_canonicalize,
|
|
CAN_FIRE_RL_respStQ_clearReq_canon,
|
|
CAN_FIRE_RL_respStQ_deqReq_canon,
|
|
CAN_FIRE_RL_respStQ_enqReq_canon,
|
|
CAN_FIRE_hostIndInv_start,
|
|
CAN_FIRE_hostIndInv_wrDone,
|
|
CAN_FIRE_hostReq_wrAddr,
|
|
CAN_FIRE_hostReq_wrData,
|
|
CAN_FIRE_mmio_req,
|
|
CAN_FIRE_to_mem_memReq_deq,
|
|
CAN_FIRE_to_mem_respSt_enq,
|
|
WILL_FIRE_RL_doNewWrite,
|
|
WILL_FIRE_RL_doStReq,
|
|
WILL_FIRE_RL_doStResp,
|
|
WILL_FIRE_RL_hostStartQ_q_portA,
|
|
WILL_FIRE_RL_hostStartQ_q_portB,
|
|
WILL_FIRE_RL_hostStartQ_q_portB_read_data,
|
|
WILL_FIRE_RL_hostStartQ_q_rRdPtr_do_decrement,
|
|
WILL_FIRE_RL_hostStartQ_q_rRdPtr_do_increment,
|
|
WILL_FIRE_RL_hostStartQ_q_rRdPtr_synchronizer,
|
|
WILL_FIRE_RL_hostStartQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_hostStartQ_q_rWrPtr_do_decrement,
|
|
WILL_FIRE_RL_hostStartQ_q_rWrPtr_do_increment,
|
|
WILL_FIRE_RL_hostStartQ_q_rWrPtr_synchronizer,
|
|
WILL_FIRE_RL_hostStartQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_portA,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_portB,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_portB_read_data,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_decrement,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_increment,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_synchronizer,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_decrement,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_increment,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_synchronizer,
|
|
WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_hostWrDataQ_q_portA,
|
|
WILL_FIRE_RL_hostWrDataQ_q_portB,
|
|
WILL_FIRE_RL_hostWrDataQ_q_portB_read_data,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_do_decrement,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_do_increment,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_synchronizer,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_do_decrement,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_do_increment,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_synchronizer,
|
|
WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_portA,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_portB,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_portB_read_data,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_decrement,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_increment,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_synchronizer,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_decrement,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_increment,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_synchronizer,
|
|
WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing,
|
|
WILL_FIRE_RL_memReqQ_canonicalize,
|
|
WILL_FIRE_RL_memReqQ_clearReq_canon,
|
|
WILL_FIRE_RL_memReqQ_deqReq_canon,
|
|
WILL_FIRE_RL_memReqQ_enqReq_canon,
|
|
WILL_FIRE_RL_respStQ_canonicalize,
|
|
WILL_FIRE_RL_respStQ_clearReq_canon,
|
|
WILL_FIRE_RL_respStQ_deqReq_canon,
|
|
WILL_FIRE_RL_respStQ_enqReq_canon,
|
|
WILL_FIRE_hostIndInv_start,
|
|
WILL_FIRE_hostIndInv_wrDone,
|
|
WILL_FIRE_hostReq_wrAddr,
|
|
WILL_FIRE_hostReq_wrData,
|
|
WILL_FIRE_mmio_req,
|
|
WILL_FIRE_to_mem_memReq_deq,
|
|
WILL_FIRE_to_mem_respSt_enq;
|
|
|
|
// inputs to muxes for submodule ports
|
|
wire [63 : 0] MUX_reqBE$write_1__VAL_2;
|
|
wire [57 : 0] MUX_reqAddr$write_1__VAL_2;
|
|
wire [7 : 0] MUX_pendStCnt$write_1__VAL_2, MUX_pendStCnt$write_1__VAL_3;
|
|
wire [2 : 0] MUX_reqSel$write_1__VAL_2;
|
|
wire [1 : 0] MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1,
|
|
MUX_hostStartQ_q_rWrPtr_rsCounter$write_1__VAL_1,
|
|
MUX_hostWrAddrQ_q_rRdPtr_rsCounter$write_1__VAL_1,
|
|
MUX_hostWrAddrQ_q_rWrPtr_rsCounter$write_1__VAL_1,
|
|
MUX_hostWrDataQ_q_rRdPtr_rsCounter$write_1__VAL_1,
|
|
MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1,
|
|
MUX_hostWrDoneQ_q_rRdPtr_rsCounter$write_1__VAL_1,
|
|
MUX_hostWrDoneQ_q_rWrPtr_rsCounter$write_1__VAL_1;
|
|
wire MUX_busy$write_1__SEL_1,
|
|
MUX_busy$write_1__SEL_2,
|
|
MUX_expectWrData$write_1__SEL_1,
|
|
MUX_writing$write_1__SEL_2;
|
|
|
|
// remaining internal signals
|
|
wire [511 : 0] IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d722;
|
|
wire [383 : 0] IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d717;
|
|
wire [255 : 0] IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d712;
|
|
wire [72 : 0] x_wget__h5086;
|
|
wire [64 : 0] x_wget__h2376;
|
|
wire [63 : 0] av_avValue_data__h91897,
|
|
req_addr__h75332,
|
|
x_addr__h43806,
|
|
x_wget__h7793;
|
|
wire [47 : 0] IF_mmio_req_wrBE_BIT_7_32_THEN_mmio_req_wrData_ETC___d865;
|
|
wire [31 : 0] IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187,
|
|
IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41,
|
|
IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11,
|
|
IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84,
|
|
IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260,
|
|
IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230,
|
|
IF_mmio_req_wrBE_BIT_7_32_THEN_mmio_req_wrData_ETC___d858,
|
|
x__h4676,
|
|
x__h6528;
|
|
wire [7 : 0] IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476,
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495,
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514,
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533,
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552,
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571,
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590,
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608;
|
|
wire [1 : 0] hostStartQ_q_rRdPtr_rdCounter_92_BIT_1_93_CONC_ETC___d897,
|
|
hostWrAddrQ_q_rRdPtr_rdCounter_10_BIT_1_11_CON_ETC___d915,
|
|
hostWrDataQ_q_rRdPtr_rdCounter_24_BIT_1_25_CON_ETC___d929,
|
|
hostWrDoneQ_q_rRdPtr_rdCounter_05_BIT_1_06_CON_ETC___d810,
|
|
x__h10885,
|
|
x__h1801,
|
|
x__h2762,
|
|
x__h3656,
|
|
x__h4511,
|
|
x__h5470,
|
|
x__h6363,
|
|
x__h7218,
|
|
x__h8177,
|
|
x__h9070,
|
|
x__h938,
|
|
x__h9925,
|
|
x_dReadBin__h10337,
|
|
x_dReadBin__h2213,
|
|
x_dReadBin__h4923,
|
|
x_dReadBin__h7630,
|
|
x_sReadBin__h10334,
|
|
x_sReadBin__h2210,
|
|
x_sReadBin__h4920,
|
|
x_sReadBin__h7627,
|
|
y__h10112,
|
|
y__h1133,
|
|
y__h1988,
|
|
y__h3843,
|
|
y__h4698,
|
|
y__h6550,
|
|
y__h7405,
|
|
y__h9257;
|
|
wire IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305,
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d788,
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d780,
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d772,
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d764,
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d756,
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d748,
|
|
NOT_IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wD_ETC___d680,
|
|
NOT_IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wD_ETC___d689,
|
|
NOT_IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wD_ETC___d672,
|
|
NOT_IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wD_ETC___d664,
|
|
NOT_IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wD_ETC___d656,
|
|
NOT_IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wD_ETC___d648,
|
|
NOT_IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wD_ETC___d640,
|
|
NOT_hostStartQ_q_rWrPtr_rsCounter_47_EQ_hostSt_ETC___d905,
|
|
NOT_hostWrDoneQ_q_rWrPtr_rsCounter_20_EQ_hostW_ETC___d818,
|
|
NOT_memReqQ_clearReq_dummy2_1_read__40_41_OR_I_ETC___d345,
|
|
NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366,
|
|
NOT_respStQ_enqReq_dummy2_2_read__16_31_OR_IF__ETC___d441,
|
|
hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_XOR__ETC___d186,
|
|
hostStartQ_q_rRdPtr_rsCounter_77_BIT_1_85_XOR__ETC___d214,
|
|
hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_XOR__ETC___d156,
|
|
hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XOR_h_ETC___d40,
|
|
hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_1_9_XOR_h_ETC___d68,
|
|
hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10,
|
|
hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113,
|
|
hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_1_12_XOR_ETC___d141,
|
|
hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83,
|
|
hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259,
|
|
hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_1_58_XOR_ETC___d287,
|
|
hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27_XOR_ETC___d229,
|
|
memReqQ_enqReq_dummy2_2_read__46_AND_IF_memReq_ETC___d358,
|
|
mmio_req_wrBE_BIT_0_25_OR_mmio_req_wrBE_BIT_1__ETC___d843,
|
|
reqSel_65_EQ_7_66_OR_hostWrDataQ_q_wDataOut_wg_ETC___d796,
|
|
respStQ_enqReq_dummy2_2_read__16_AND_IF_respSt_ETC___d428;
|
|
|
|
// actionvalue method mmio_req
|
|
assign mmio_req =
|
|
{ !mmio_req_wrBE[0] && !mmio_req_wrBE[1] && !mmio_req_wrBE[2] &&
|
|
!mmio_req_wrBE[3] &&
|
|
!mmio_req_wrBE[4] &&
|
|
!mmio_req_wrBE[5] &&
|
|
!mmio_req_wrBE[6] &&
|
|
!mmio_req_wrBE[7] ||
|
|
!mmio_req_offset,
|
|
av_avValue_data__h91897 } ;
|
|
assign RDY_mmio_req =
|
|
busy ||
|
|
NOT_hostStartQ_q_rWrPtr_rsCounter_47_EQ_hostSt_ETC___d905 ;
|
|
assign CAN_FIRE_mmio_req =
|
|
busy ||
|
|
NOT_hostStartQ_q_rWrPtr_rsCounter_47_EQ_hostSt_ETC___d905 ;
|
|
assign WILL_FIRE_mmio_req = EN_mmio_req ;
|
|
|
|
// value method to_mem_memReq_notEmpty
|
|
assign to_mem_memReq_notEmpty = !memReqQ_empty ;
|
|
assign RDY_to_mem_memReq_notEmpty = 1'd1 ;
|
|
|
|
// action method to_mem_memReq_deq
|
|
assign RDY_to_mem_memReq_deq = !memReqQ_empty ;
|
|
assign CAN_FIRE_to_mem_memReq_deq = !memReqQ_empty ;
|
|
assign WILL_FIRE_to_mem_memReq_deq = EN_to_mem_memReq_deq ;
|
|
|
|
// value method to_mem_memReq_first
|
|
assign to_mem_memReq_first = memReqQ_data_0 ;
|
|
assign RDY_to_mem_memReq_first = !memReqQ_empty ;
|
|
|
|
// value method to_mem_respSt_notFull
|
|
assign to_mem_respSt_notFull = !respStQ_full ;
|
|
assign RDY_to_mem_respSt_notFull = 1'd1 ;
|
|
|
|
// action method to_mem_respSt_enq
|
|
assign RDY_to_mem_respSt_enq = !respStQ_full ;
|
|
assign CAN_FIRE_to_mem_respSt_enq = !respStQ_full ;
|
|
assign WILL_FIRE_to_mem_respSt_enq = EN_to_mem_respSt_enq ;
|
|
|
|
// action method hostReq_wrAddr
|
|
assign RDY_hostReq_wrAddr =
|
|
hostWrAddrQ_q_rWrPtr_rsCounter !=
|
|
{ hostWrAddrQ_q_rRdPtr_rdCounter_10_BIT_1_11_CON_ETC___d915[1],
|
|
hostWrAddrQ_q_rRdPtr_rdCounter_10_BIT_1_11_CON_ETC___d915[1] ^
|
|
hostWrAddrQ_q_rRdPtr_rdCounter_10_BIT_1_11_CON_ETC___d915[0] } &&
|
|
hostWrAddrQ_srcGuard$IS_READY ;
|
|
assign CAN_FIRE_hostReq_wrAddr = RDY_hostReq_wrAddr ;
|
|
assign WILL_FIRE_hostReq_wrAddr = EN_hostReq_wrAddr ;
|
|
|
|
// action method hostReq_wrData
|
|
assign RDY_hostReq_wrData =
|
|
hostWrDataQ_q_rWrPtr_rsCounter !=
|
|
{ hostWrDataQ_q_rRdPtr_rdCounter_24_BIT_1_25_CON_ETC___d929[1],
|
|
hostWrDataQ_q_rRdPtr_rdCounter_24_BIT_1_25_CON_ETC___d929[1] ^
|
|
hostWrDataQ_q_rRdPtr_rdCounter_24_BIT_1_25_CON_ETC___d929[0] } &&
|
|
hostWrDataQ_srcGuard$IS_READY ;
|
|
assign CAN_FIRE_hostReq_wrData = RDY_hostReq_wrData ;
|
|
assign WILL_FIRE_hostReq_wrData = EN_hostReq_wrData ;
|
|
|
|
// actionvalue method hostIndInv_start
|
|
assign hostIndInv_start = hostStartQ_q_memory$DOB ;
|
|
assign RDY_hostIndInv_start =
|
|
hostStartQ_q_rRdPtr_rsCounter != hostStartQ_q_rWrPtr_rdCounter &&
|
|
hostStartQ_dstGuard$IS_READY ;
|
|
assign CAN_FIRE_hostIndInv_start =
|
|
hostStartQ_q_rRdPtr_rsCounter != hostStartQ_q_rWrPtr_rdCounter &&
|
|
hostStartQ_dstGuard$IS_READY ;
|
|
assign WILL_FIRE_hostIndInv_start = EN_hostIndInv_start ;
|
|
|
|
// action method hostIndInv_wrDone
|
|
assign RDY_hostIndInv_wrDone =
|
|
hostWrDoneQ_q_rRdPtr_rsCounter !=
|
|
hostWrDoneQ_q_rWrPtr_rdCounter &&
|
|
hostWrDoneQ_dstGuard$IS_READY ;
|
|
assign CAN_FIRE_hostIndInv_wrDone =
|
|
hostWrDoneQ_q_rRdPtr_rsCounter !=
|
|
hostWrDoneQ_q_rWrPtr_rdCounter &&
|
|
hostWrDoneQ_dstGuard$IS_READY ;
|
|
assign WILL_FIRE_hostIndInv_wrDone = EN_hostIndInv_wrDone ;
|
|
|
|
// submodule hostStartQ_dstGuard
|
|
reset_guard hostStartQ_dstGuard(.CLK(CLK_portalClk),
|
|
.RST(RST_N_portalRst),
|
|
.IS_READY(hostStartQ_dstGuard$IS_READY));
|
|
|
|
// submodule hostStartQ_q_memory
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd1),
|
|
.DATA_WIDTH(32'd64),
|
|
.MEMSIZE(2'd2)) hostStartQ_q_memory(.CLKA(CLK),
|
|
.CLKB(CLK_portalClk),
|
|
.ADDRA(hostStartQ_q_memory$ADDRA),
|
|
.ADDRB(hostStartQ_q_memory$ADDRB),
|
|
.DIA(hostStartQ_q_memory$DIA),
|
|
.DIB(hostStartQ_q_memory$DIB),
|
|
.WEA(hostStartQ_q_memory$WEA),
|
|
.WEB(hostStartQ_q_memory$WEB),
|
|
.ENA(hostStartQ_q_memory$ENA),
|
|
.ENB(hostStartQ_q_memory$ENB),
|
|
.DOA(),
|
|
.DOB(hostStartQ_q_memory$DOB));
|
|
|
|
// submodule hostStartQ_srcGuard
|
|
reset_guard hostStartQ_srcGuard(.CLK(CLK),
|
|
.RST(RST_N),
|
|
.IS_READY(hostStartQ_srcGuard$IS_READY));
|
|
|
|
// submodule hostWrAddrQ_dstGuard
|
|
reset_guard hostWrAddrQ_dstGuard(.CLK(CLK),
|
|
.RST(RST_N),
|
|
.IS_READY(hostWrAddrQ_dstGuard$IS_READY));
|
|
|
|
// submodule hostWrAddrQ_q_memory
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd1),
|
|
.DATA_WIDTH(32'd65),
|
|
.MEMSIZE(2'd2)) hostWrAddrQ_q_memory(.CLKA(CLK_portalClk),
|
|
.CLKB(CLK),
|
|
.ADDRA(hostWrAddrQ_q_memory$ADDRA),
|
|
.ADDRB(hostWrAddrQ_q_memory$ADDRB),
|
|
.DIA(hostWrAddrQ_q_memory$DIA),
|
|
.DIB(hostWrAddrQ_q_memory$DIB),
|
|
.WEA(hostWrAddrQ_q_memory$WEA),
|
|
.WEB(hostWrAddrQ_q_memory$WEB),
|
|
.ENA(hostWrAddrQ_q_memory$ENA),
|
|
.ENB(hostWrAddrQ_q_memory$ENB),
|
|
.DOA(),
|
|
.DOB(hostWrAddrQ_q_memory$DOB));
|
|
|
|
// submodule hostWrAddrQ_srcGuard
|
|
reset_guard hostWrAddrQ_srcGuard(.CLK(CLK_portalClk),
|
|
.RST(RST_N_portalRst),
|
|
.IS_READY(hostWrAddrQ_srcGuard$IS_READY));
|
|
|
|
// submodule hostWrDataQ_dstGuard
|
|
reset_guard hostWrDataQ_dstGuard(.CLK(CLK),
|
|
.RST(RST_N),
|
|
.IS_READY(hostWrDataQ_dstGuard$IS_READY));
|
|
|
|
// submodule hostWrDataQ_q_memory
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd1),
|
|
.DATA_WIDTH(32'd73),
|
|
.MEMSIZE(2'd2)) hostWrDataQ_q_memory(.CLKA(CLK_portalClk),
|
|
.CLKB(CLK),
|
|
.ADDRA(hostWrDataQ_q_memory$ADDRA),
|
|
.ADDRB(hostWrDataQ_q_memory$ADDRB),
|
|
.DIA(hostWrDataQ_q_memory$DIA),
|
|
.DIB(hostWrDataQ_q_memory$DIB),
|
|
.WEA(hostWrDataQ_q_memory$WEA),
|
|
.WEB(hostWrDataQ_q_memory$WEB),
|
|
.ENA(hostWrDataQ_q_memory$ENA),
|
|
.ENB(hostWrDataQ_q_memory$ENB),
|
|
.DOA(),
|
|
.DOB(hostWrDataQ_q_memory$DOB));
|
|
|
|
// submodule hostWrDataQ_srcGuard
|
|
reset_guard hostWrDataQ_srcGuard(.CLK(CLK_portalClk),
|
|
.RST(RST_N_portalRst),
|
|
.IS_READY(hostWrDataQ_srcGuard$IS_READY));
|
|
|
|
// submodule hostWrDoneQ_dstGuard
|
|
reset_guard hostWrDoneQ_dstGuard(.CLK(CLK_portalClk),
|
|
.RST(RST_N_portalRst),
|
|
.IS_READY(hostWrDoneQ_dstGuard$IS_READY));
|
|
|
|
// submodule hostWrDoneQ_q_memory
|
|
BRAM2 #(.PIPELINED(1'd0),
|
|
.ADDR_WIDTH(32'd1),
|
|
.DATA_WIDTH(32'd1),
|
|
.MEMSIZE(2'd2)) hostWrDoneQ_q_memory(.CLKA(CLK),
|
|
.CLKB(CLK_portalClk),
|
|
.ADDRA(hostWrDoneQ_q_memory$ADDRA),
|
|
.ADDRB(hostWrDoneQ_q_memory$ADDRB),
|
|
.DIA(hostWrDoneQ_q_memory$DIA),
|
|
.DIB(hostWrDoneQ_q_memory$DIB),
|
|
.WEA(hostWrDoneQ_q_memory$WEA),
|
|
.WEB(hostWrDoneQ_q_memory$WEB),
|
|
.ENA(hostWrDoneQ_q_memory$ENA),
|
|
.ENB(hostWrDoneQ_q_memory$ENB),
|
|
.DOA(),
|
|
.DOB());
|
|
|
|
// submodule hostWrDoneQ_srcGuard
|
|
reset_guard hostWrDoneQ_srcGuard(.CLK(CLK),
|
|
.RST(RST_N),
|
|
.IS_READY(hostWrDoneQ_srcGuard$IS_READY));
|
|
|
|
// submodule memReqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(memReqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(memReqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(memReqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(memReqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(memReqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule memReqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(memReqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(memReqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(memReqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(memReqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(memReqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(memReqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(memReqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule memReqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(memReqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(memReqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(memReqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(memReqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule memReqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) memReqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(memReqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(memReqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(memReqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule respStQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respStQ_clearReq_dummy2_0$D_IN),
|
|
.EN(respStQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respStQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respStQ_clearReq_dummy2_1$D_IN),
|
|
.EN(respStQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(respStQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule respStQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respStQ_deqReq_dummy2_0$D_IN),
|
|
.EN(respStQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respStQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respStQ_deqReq_dummy2_1$D_IN),
|
|
.EN(respStQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respStQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(respStQ_deqReq_dummy2_2$D_IN),
|
|
.EN(respStQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(respStQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule respStQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respStQ_enqReq_dummy2_0$D_IN),
|
|
.EN(respStQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respStQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respStQ_enqReq_dummy2_1$D_IN),
|
|
.EN(respStQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respStQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respStQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(respStQ_enqReq_dummy2_2$D_IN),
|
|
.EN(respStQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(respStQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// rule RL_doStResp
|
|
assign CAN_FIRE_RL_doStResp =
|
|
!respStQ_empty &&
|
|
(pendStCnt != 8'd1 || expectWrData ||
|
|
NOT_hostWrDoneQ_q_rWrPtr_rsCounter_20_EQ_hostW_ETC___d818) &&
|
|
writing ;
|
|
assign WILL_FIRE_RL_doStResp = CAN_FIRE_RL_doStResp ;
|
|
|
|
// rule RL_hostWrAddrQ_q_portA
|
|
assign CAN_FIRE_RL_hostWrAddrQ_q_portA = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrAddrQ_q_portA = 1'd1 ;
|
|
|
|
// rule RL_hostWrAddrQ_q_portB_read_data
|
|
assign CAN_FIRE_RL_hostWrAddrQ_q_portB_read_data = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrAddrQ_q_portB_read_data = 1'd1 ;
|
|
|
|
// rule RL_doNewWrite
|
|
assign CAN_FIRE_RL_doNewWrite =
|
|
hostWrAddrQ_q_rRdPtr_rsCounter !=
|
|
hostWrAddrQ_q_rWrPtr_rdCounter &&
|
|
hostWrAddrQ_dstGuard$IS_READY &&
|
|
busy &&
|
|
!writing ;
|
|
assign WILL_FIRE_RL_doNewWrite = CAN_FIRE_RL_doNewWrite && !EN_mmio_req ;
|
|
|
|
// rule RL_hostWrAddrQ_q_portB
|
|
assign CAN_FIRE_RL_hostWrAddrQ_q_portB = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrAddrQ_q_portB = 1'd1 ;
|
|
|
|
// rule RL_hostWrAddrQ_q_rWrPtr_synchronizer
|
|
assign CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_synchronizer = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_synchronizer = 1'd1 ;
|
|
|
|
// rule RL_hostWrAddrQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing
|
|
assign CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
|
|
// rule RL_hostWrAddrQ_q_rWrPtr_do_increment
|
|
assign CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_increment = EN_hostReq_wrAddr ;
|
|
assign WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_increment = EN_hostReq_wrAddr ;
|
|
|
|
// rule RL_hostWrAddrQ_q_rWrPtr_do_decrement
|
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assign CAN_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_decrement = 1'b0 ;
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assign WILL_FIRE_RL_hostWrAddrQ_q_rWrPtr_do_decrement = 1'b0 ;
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// rule RL_hostWrAddrQ_q_rRdPtr_synchronizer
|
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assign CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_synchronizer = 1'd1 ;
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assign WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_synchronizer = 1'd1 ;
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// rule RL_hostWrAddrQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing
|
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assign CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
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assign WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
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1'd1 ;
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// rule RL_hostWrAddrQ_q_rRdPtr_do_increment
|
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assign CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_increment =
|
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WILL_FIRE_RL_doNewWrite ;
|
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assign WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_increment =
|
|
WILL_FIRE_RL_doNewWrite ;
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// rule RL_hostWrAddrQ_q_rRdPtr_do_decrement
|
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assign CAN_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_decrement = 1'b0 ;
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assign WILL_FIRE_RL_hostWrAddrQ_q_rRdPtr_do_decrement = 1'b0 ;
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// rule RL_hostWrDataQ_q_portA
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assign CAN_FIRE_RL_hostWrDataQ_q_portA = 1'd1 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_portA = 1'd1 ;
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// rule RL_hostWrDataQ_q_portB_read_data
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assign CAN_FIRE_RL_hostWrDataQ_q_portB_read_data = 1'd1 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_portB_read_data = 1'd1 ;
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// rule RL_doStReq
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assign CAN_FIRE_RL_doStReq =
|
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hostWrDataQ_q_rRdPtr_rsCounter !=
|
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hostWrDataQ_q_rWrPtr_rdCounter &&
|
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hostWrDataQ_dstGuard$IS_READY &&
|
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(reqSel != 3'd7 && !hostWrDataQ_q_memory$DOB[0] ||
|
|
NOT_IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wD_ETC___d689) &&
|
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writing &&
|
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expectWrData &&
|
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pendStCnt != 8'd255 ;
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assign WILL_FIRE_RL_doStReq =
|
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CAN_FIRE_RL_doStReq && !WILL_FIRE_RL_doStResp ;
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// rule RL_hostWrDataQ_q_portB
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assign CAN_FIRE_RL_hostWrDataQ_q_portB = 1'd1 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_portB = 1'd1 ;
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// rule RL_hostWrDataQ_q_rWrPtr_synchronizer
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assign CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_synchronizer = 1'd1 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_synchronizer = 1'd1 ;
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// rule RL_hostWrDataQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing
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assign CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
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1'd1 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
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1'd1 ;
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// rule RL_hostWrDataQ_q_rWrPtr_do_increment
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assign CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_do_increment = EN_hostReq_wrData ;
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assign WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_do_increment = EN_hostReq_wrData ;
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// rule RL_hostWrDataQ_q_rWrPtr_do_decrement
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assign CAN_FIRE_RL_hostWrDataQ_q_rWrPtr_do_decrement = 1'b0 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_rWrPtr_do_decrement = 1'b0 ;
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// rule RL_hostWrDataQ_q_rRdPtr_synchronizer
|
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assign CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_synchronizer = 1'd1 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_synchronizer = 1'd1 ;
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// rule RL_hostWrDataQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing
|
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assign CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
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1'd1 ;
|
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assign WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
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1'd1 ;
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// rule RL_hostWrDataQ_q_rRdPtr_do_increment
|
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assign CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_do_increment =
|
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WILL_FIRE_RL_doStReq ;
|
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assign WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_do_increment =
|
|
WILL_FIRE_RL_doStReq ;
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|
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// rule RL_hostWrDataQ_q_rRdPtr_do_decrement
|
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assign CAN_FIRE_RL_hostWrDataQ_q_rRdPtr_do_decrement = 1'b0 ;
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assign WILL_FIRE_RL_hostWrDataQ_q_rRdPtr_do_decrement = 1'b0 ;
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|
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// rule RL_hostStartQ_q_portA
|
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assign CAN_FIRE_RL_hostStartQ_q_portA = 1'd1 ;
|
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assign WILL_FIRE_RL_hostStartQ_q_portA = 1'd1 ;
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|
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// rule RL_hostStartQ_q_portB_read_data
|
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assign CAN_FIRE_RL_hostStartQ_q_portB_read_data = 1'd1 ;
|
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assign WILL_FIRE_RL_hostStartQ_q_portB_read_data = 1'd1 ;
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|
|
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// rule RL_hostStartQ_q_portB
|
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assign CAN_FIRE_RL_hostStartQ_q_portB = 1'd1 ;
|
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assign WILL_FIRE_RL_hostStartQ_q_portB = 1'd1 ;
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|
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// rule RL_hostStartQ_q_rWrPtr_synchronizer
|
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assign CAN_FIRE_RL_hostStartQ_q_rWrPtr_synchronizer = 1'd1 ;
|
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assign WILL_FIRE_RL_hostStartQ_q_rWrPtr_synchronizer = 1'd1 ;
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|
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// rule RL_hostStartQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing
|
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assign CAN_FIRE_RL_hostStartQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_hostStartQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
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|
|
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// rule RL_hostStartQ_q_rWrPtr_do_increment
|
|
assign CAN_FIRE_RL_hostStartQ_q_rWrPtr_do_increment =
|
|
MUX_busy$write_1__SEL_2 ;
|
|
assign WILL_FIRE_RL_hostStartQ_q_rWrPtr_do_increment =
|
|
MUX_busy$write_1__SEL_2 ;
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|
|
|
// rule RL_hostStartQ_q_rWrPtr_do_decrement
|
|
assign CAN_FIRE_RL_hostStartQ_q_rWrPtr_do_decrement = 1'b0 ;
|
|
assign WILL_FIRE_RL_hostStartQ_q_rWrPtr_do_decrement = 1'b0 ;
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|
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// rule RL_hostStartQ_q_rRdPtr_synchronizer
|
|
assign CAN_FIRE_RL_hostStartQ_q_rRdPtr_synchronizer = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostStartQ_q_rRdPtr_synchronizer = 1'd1 ;
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|
|
// rule RL_hostStartQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing
|
|
assign CAN_FIRE_RL_hostStartQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_hostStartQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
|
|
// rule RL_hostStartQ_q_rRdPtr_do_increment
|
|
assign CAN_FIRE_RL_hostStartQ_q_rRdPtr_do_increment = EN_hostIndInv_start ;
|
|
assign WILL_FIRE_RL_hostStartQ_q_rRdPtr_do_increment = EN_hostIndInv_start ;
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|
|
|
// rule RL_hostStartQ_q_rRdPtr_do_decrement
|
|
assign CAN_FIRE_RL_hostStartQ_q_rRdPtr_do_decrement = 1'b0 ;
|
|
assign WILL_FIRE_RL_hostStartQ_q_rRdPtr_do_decrement = 1'b0 ;
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|
|
|
// rule RL_hostWrDoneQ_q_portA
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_portA = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_portA = 1'd1 ;
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|
|
|
// rule RL_hostWrDoneQ_q_portB
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_portB = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_portB = 1'd1 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_portB_read_data
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_portB_read_data = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_portB_read_data = 1'd1 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rWrPtr_synchronizer
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_synchronizer = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_synchronizer = 1'd1 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rWrPtr_do_increment
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_increment =
|
|
MUX_writing$write_1__SEL_2 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_increment =
|
|
MUX_writing$write_1__SEL_2 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rWrPtr_do_decrement
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_decrement = 1'b0 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rWrPtr_do_decrement = 1'b0 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rRdPtr_synchronizer
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_synchronizer = 1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_synchronizer = 1'd1 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_wdCounterCrossing_clock_domain_crossing =
|
|
1'd1 ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rRdPtr_do_increment
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_increment =
|
|
EN_hostIndInv_wrDone ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_increment =
|
|
EN_hostIndInv_wrDone ;
|
|
|
|
// rule RL_hostWrDoneQ_q_rRdPtr_do_decrement
|
|
assign CAN_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_decrement = 1'b0 ;
|
|
assign WILL_FIRE_RL_hostWrDoneQ_q_rRdPtr_do_decrement = 1'b0 ;
|
|
|
|
// rule RL_memReqQ_canonicalize
|
|
assign CAN_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_memReqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_memReqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respStQ_canonicalize
|
|
assign CAN_FIRE_RL_respStQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_respStQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_respStQ_enqReq_canon
|
|
assign CAN_FIRE_RL_respStQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respStQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respStQ_deqReq_canon
|
|
assign CAN_FIRE_RL_respStQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respStQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respStQ_clearReq_canon
|
|
assign CAN_FIRE_RL_respStQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respStQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_busy$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doNewWrite && !hostWrAddrQ_q_memory$DOB[64] ;
|
|
assign MUX_busy$write_1__SEL_2 =
|
|
EN_mmio_req &&
|
|
mmio_req_wrBE_BIT_0_25_OR_mmio_req_wrBE_BIT_1__ETC___d843 ;
|
|
assign MUX_expectWrData$write_1__SEL_1 =
|
|
WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ;
|
|
assign MUX_writing$write_1__SEL_2 =
|
|
WILL_FIRE_RL_doStResp && pendStCnt == 8'd1 && !expectWrData ;
|
|
assign MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostStartQ_q_rRdPtr_rsCounter[IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187[0]]) ?
|
|
hostStartQ_q_rRdPtr_rsCounter | x__h7218 :
|
|
hostStartQ_q_rRdPtr_rsCounter & y__h7405 ;
|
|
assign MUX_hostStartQ_q_rWrPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostStartQ_q_rWrPtr_rsCounter[x__h6528[0]]) ?
|
|
hostStartQ_q_rWrPtr_rsCounter | x__h6363 :
|
|
hostStartQ_q_rWrPtr_rsCounter & y__h6550 ;
|
|
assign MUX_hostWrAddrQ_q_rRdPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostWrAddrQ_q_rRdPtr_rsCounter[IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41[0]]) ?
|
|
hostWrAddrQ_q_rRdPtr_rsCounter | x__h1801 :
|
|
hostWrAddrQ_q_rRdPtr_rsCounter & y__h1988 ;
|
|
assign MUX_hostWrAddrQ_q_rWrPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostWrAddrQ_q_rWrPtr_rsCounter[IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11[0]]) ?
|
|
hostWrAddrQ_q_rWrPtr_rsCounter | x__h938 :
|
|
hostWrAddrQ_q_rWrPtr_rsCounter & y__h1133 ;
|
|
assign MUX_hostWrDataQ_q_rRdPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostWrDataQ_q_rRdPtr_rsCounter[x__h4676[0]]) ?
|
|
hostWrDataQ_q_rRdPtr_rsCounter | x__h4511 :
|
|
hostWrDataQ_q_rRdPtr_rsCounter & y__h4698 ;
|
|
assign MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostWrDataQ_q_rWrPtr_rsCounter[IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84[0]]) ?
|
|
hostWrDataQ_q_rWrPtr_rsCounter | x__h3656 :
|
|
hostWrDataQ_q_rWrPtr_rsCounter & y__h3843 ;
|
|
assign MUX_hostWrDoneQ_q_rRdPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostWrDoneQ_q_rRdPtr_rsCounter[IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260[0]]) ?
|
|
hostWrDoneQ_q_rRdPtr_rsCounter | x__h9925 :
|
|
hostWrDoneQ_q_rRdPtr_rsCounter & y__h10112 ;
|
|
assign MUX_hostWrDoneQ_q_rWrPtr_rsCounter$write_1__VAL_1 =
|
|
(~hostWrDoneQ_q_rWrPtr_rsCounter[IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230[0]]) ?
|
|
hostWrDoneQ_q_rWrPtr_rsCounter | x__h9070 :
|
|
hostWrDoneQ_q_rWrPtr_rsCounter & y__h9257 ;
|
|
assign MUX_pendStCnt$write_1__VAL_2 = pendStCnt + 8'd1 ;
|
|
assign MUX_pendStCnt$write_1__VAL_3 = pendStCnt - 8'd1 ;
|
|
assign MUX_reqAddr$write_1__VAL_2 =
|
|
(reqSel == 3'd7) ? reqAddr + 58'd1 : reqAddr ;
|
|
assign MUX_reqBE$write_1__VAL_2 =
|
|
(reqSel == 3'd7 || hostWrDataQ_q_memory$DOB[0]) ?
|
|
64'd0 :
|
|
{ IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608,
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590,
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571,
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552,
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533,
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514,
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495,
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476 } ;
|
|
assign MUX_reqSel$write_1__VAL_2 = reqSel + 3'd1 ;
|
|
|
|
// inlined wires
|
|
assign memReqQ_enqReq_lat_0$wget =
|
|
{ 1'd1,
|
|
req_addr__h75332,
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608,
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590,
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571,
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552,
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533,
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514,
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495,
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476,
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d722 } ;
|
|
assign memReqQ_enqReq_lat_0$whas =
|
|
WILL_FIRE_RL_doStReq &&
|
|
reqSel_65_EQ_7_66_OR_hostWrDataQ_q_wDataOut_wg_ETC___d796 ;
|
|
|
|
// register busy
|
|
assign busy$D_IN = !MUX_busy$write_1__SEL_1 ;
|
|
assign busy$EN =
|
|
WILL_FIRE_RL_doNewWrite && !hostWrAddrQ_q_memory$DOB[64] ||
|
|
EN_mmio_req &&
|
|
mmio_req_wrBE_BIT_0_25_OR_mmio_req_wrBE_BIT_1__ETC___d843 ;
|
|
|
|
// register expectWrData
|
|
assign expectWrData$D_IN =
|
|
MUX_expectWrData$write_1__SEL_1 || !hostWrDataQ_q_memory$DOB[0] ;
|
|
assign expectWrData$EN =
|
|
WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ||
|
|
WILL_FIRE_RL_doStReq ;
|
|
|
|
// register hostStartQ_q_rRdPtr_rdCounter
|
|
assign hostStartQ_q_rRdPtr_rdCounter$D_IN =
|
|
hostStartQ_q_rRdPtr_rdCounterPre ;
|
|
assign hostStartQ_q_rRdPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostStartQ_q_rRdPtr_rdCounterPre
|
|
assign hostStartQ_q_rRdPtr_rdCounterPre$D_IN =
|
|
hostStartQ_q_rRdPtr_rsCounter ;
|
|
assign hostStartQ_q_rRdPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostStartQ_q_rRdPtr_rsCounter
|
|
assign hostStartQ_q_rRdPtr_rsCounter$D_IN =
|
|
MUX_hostStartQ_q_rRdPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostStartQ_q_rRdPtr_rsCounter$EN = EN_hostIndInv_start ;
|
|
|
|
// register hostStartQ_q_rWrPtr_rdCounter
|
|
assign hostStartQ_q_rWrPtr_rdCounter$D_IN =
|
|
hostStartQ_q_rWrPtr_rdCounterPre ;
|
|
assign hostStartQ_q_rWrPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostStartQ_q_rWrPtr_rdCounterPre
|
|
assign hostStartQ_q_rWrPtr_rdCounterPre$D_IN =
|
|
hostStartQ_q_rWrPtr_rsCounter ;
|
|
assign hostStartQ_q_rWrPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostStartQ_q_rWrPtr_rsCounter
|
|
assign hostStartQ_q_rWrPtr_rsCounter$D_IN =
|
|
MUX_hostStartQ_q_rWrPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostStartQ_q_rWrPtr_rsCounter$EN = MUX_busy$write_1__SEL_2 ;
|
|
|
|
// register hostWrAddrQ_q_rRdPtr_rdCounter
|
|
assign hostWrAddrQ_q_rRdPtr_rdCounter$D_IN =
|
|
hostWrAddrQ_q_rRdPtr_rdCounterPre ;
|
|
assign hostWrAddrQ_q_rRdPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostWrAddrQ_q_rRdPtr_rdCounterPre
|
|
assign hostWrAddrQ_q_rRdPtr_rdCounterPre$D_IN =
|
|
hostWrAddrQ_q_rRdPtr_rsCounter ;
|
|
assign hostWrAddrQ_q_rRdPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostWrAddrQ_q_rRdPtr_rsCounter
|
|
assign hostWrAddrQ_q_rRdPtr_rsCounter$D_IN =
|
|
MUX_hostWrAddrQ_q_rRdPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostWrAddrQ_q_rRdPtr_rsCounter$EN = WILL_FIRE_RL_doNewWrite ;
|
|
|
|
// register hostWrAddrQ_q_rWrPtr_rdCounter
|
|
assign hostWrAddrQ_q_rWrPtr_rdCounter$D_IN =
|
|
hostWrAddrQ_q_rWrPtr_rdCounterPre ;
|
|
assign hostWrAddrQ_q_rWrPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostWrAddrQ_q_rWrPtr_rdCounterPre
|
|
assign hostWrAddrQ_q_rWrPtr_rdCounterPre$D_IN =
|
|
hostWrAddrQ_q_rWrPtr_rsCounter ;
|
|
assign hostWrAddrQ_q_rWrPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostWrAddrQ_q_rWrPtr_rsCounter
|
|
assign hostWrAddrQ_q_rWrPtr_rsCounter$D_IN =
|
|
MUX_hostWrAddrQ_q_rWrPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostWrAddrQ_q_rWrPtr_rsCounter$EN = EN_hostReq_wrAddr ;
|
|
|
|
// register hostWrDataQ_q_rRdPtr_rdCounter
|
|
assign hostWrDataQ_q_rRdPtr_rdCounter$D_IN =
|
|
hostWrDataQ_q_rRdPtr_rdCounterPre ;
|
|
assign hostWrDataQ_q_rRdPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostWrDataQ_q_rRdPtr_rdCounterPre
|
|
assign hostWrDataQ_q_rRdPtr_rdCounterPre$D_IN =
|
|
hostWrDataQ_q_rRdPtr_rsCounter ;
|
|
assign hostWrDataQ_q_rRdPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostWrDataQ_q_rRdPtr_rsCounter
|
|
assign hostWrDataQ_q_rRdPtr_rsCounter$D_IN =
|
|
MUX_hostWrDataQ_q_rRdPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostWrDataQ_q_rRdPtr_rsCounter$EN = WILL_FIRE_RL_doStReq ;
|
|
|
|
// register hostWrDataQ_q_rWrPtr_rdCounter
|
|
assign hostWrDataQ_q_rWrPtr_rdCounter$D_IN =
|
|
hostWrDataQ_q_rWrPtr_rdCounterPre ;
|
|
assign hostWrDataQ_q_rWrPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostWrDataQ_q_rWrPtr_rdCounterPre
|
|
assign hostWrDataQ_q_rWrPtr_rdCounterPre$D_IN =
|
|
hostWrDataQ_q_rWrPtr_rsCounter ;
|
|
assign hostWrDataQ_q_rWrPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostWrDataQ_q_rWrPtr_rsCounter
|
|
assign hostWrDataQ_q_rWrPtr_rsCounter$D_IN =
|
|
MUX_hostWrDataQ_q_rWrPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostWrDataQ_q_rWrPtr_rsCounter$EN = EN_hostReq_wrData ;
|
|
|
|
// register hostWrDoneQ_q_rRdPtr_rdCounter
|
|
assign hostWrDoneQ_q_rRdPtr_rdCounter$D_IN =
|
|
hostWrDoneQ_q_rRdPtr_rdCounterPre ;
|
|
assign hostWrDoneQ_q_rRdPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostWrDoneQ_q_rRdPtr_rdCounterPre
|
|
assign hostWrDoneQ_q_rRdPtr_rdCounterPre$D_IN =
|
|
hostWrDoneQ_q_rRdPtr_rsCounter ;
|
|
assign hostWrDoneQ_q_rRdPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostWrDoneQ_q_rRdPtr_rsCounter
|
|
assign hostWrDoneQ_q_rRdPtr_rsCounter$D_IN =
|
|
MUX_hostWrDoneQ_q_rRdPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostWrDoneQ_q_rRdPtr_rsCounter$EN = EN_hostIndInv_wrDone ;
|
|
|
|
// register hostWrDoneQ_q_rWrPtr_rdCounter
|
|
assign hostWrDoneQ_q_rWrPtr_rdCounter$D_IN =
|
|
hostWrDoneQ_q_rWrPtr_rdCounterPre ;
|
|
assign hostWrDoneQ_q_rWrPtr_rdCounter$EN = 1'd1 ;
|
|
|
|
// register hostWrDoneQ_q_rWrPtr_rdCounterPre
|
|
assign hostWrDoneQ_q_rWrPtr_rdCounterPre$D_IN =
|
|
hostWrDoneQ_q_rWrPtr_rsCounter ;
|
|
assign hostWrDoneQ_q_rWrPtr_rdCounterPre$EN = 1'd1 ;
|
|
|
|
// register hostWrDoneQ_q_rWrPtr_rsCounter
|
|
assign hostWrDoneQ_q_rWrPtr_rsCounter$D_IN =
|
|
MUX_hostWrDoneQ_q_rWrPtr_rsCounter$write_1__VAL_1 ;
|
|
assign hostWrDoneQ_q_rWrPtr_rsCounter$EN = MUX_writing$write_1__SEL_2 ;
|
|
|
|
// register memReqQ_clearReq_rl
|
|
assign memReqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign memReqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_data_0
|
|
assign memReqQ_data_0$D_IN =
|
|
{ x_addr__h43806,
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[575:0] :
|
|
memReqQ_enqReq_rl[575:0] } ;
|
|
assign memReqQ_data_0$EN =
|
|
NOT_memReqQ_clearReq_dummy2_1_read__40_41_OR_I_ETC___d345 &&
|
|
memReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 ;
|
|
|
|
// register memReqQ_deqReq_rl
|
|
assign memReqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign memReqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_empty
|
|
assign memReqQ_empty$D_IN =
|
|
memReqQ_clearReq_dummy2_1$Q_OUT && memReqQ_clearReq_rl ||
|
|
NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366 ;
|
|
assign memReqQ_empty$EN = 1'd1 ;
|
|
|
|
// register memReqQ_enqReq_rl
|
|
assign memReqQ_enqReq_rl$D_IN =
|
|
641'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
|
|
assign memReqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register memReqQ_full
|
|
assign memReqQ_full$D_IN =
|
|
NOT_memReqQ_clearReq_dummy2_1_read__40_41_OR_I_ETC___d345 &&
|
|
memReqQ_enqReq_dummy2_2_read__46_AND_IF_memReq_ETC___d358 ;
|
|
assign memReqQ_full$EN = 1'd1 ;
|
|
|
|
// register memStartAddr
|
|
assign memStartAddr$D_IN = x_wget__h7793 ;
|
|
assign memStartAddr$EN = MUX_busy$write_1__SEL_2 ;
|
|
|
|
// register pendStCnt
|
|
always@(MUX_expectWrData$write_1__SEL_1 or
|
|
memReqQ_enqReq_lat_0$whas or
|
|
MUX_pendStCnt$write_1__VAL_2 or
|
|
WILL_FIRE_RL_doStResp or MUX_pendStCnt$write_1__VAL_3)
|
|
begin
|
|
case (1'b1) // synopsys parallel_case
|
|
MUX_expectWrData$write_1__SEL_1: pendStCnt$D_IN = 8'd0;
|
|
memReqQ_enqReq_lat_0$whas:
|
|
pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_2;
|
|
WILL_FIRE_RL_doStResp: pendStCnt$D_IN = MUX_pendStCnt$write_1__VAL_3;
|
|
default: pendStCnt$D_IN = 8'b10101010 /* unspecified value */ ;
|
|
endcase
|
|
end
|
|
assign pendStCnt$EN =
|
|
WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ||
|
|
WILL_FIRE_RL_doStReq &&
|
|
reqSel_65_EQ_7_66_OR_hostWrDataQ_q_wDataOut_wg_ETC___d796 ||
|
|
WILL_FIRE_RL_doStResp ;
|
|
|
|
// register reqAddr
|
|
assign reqAddr$D_IN =
|
|
MUX_expectWrData$write_1__SEL_1 ?
|
|
hostWrAddrQ_q_memory$DOB[63:6] :
|
|
MUX_reqAddr$write_1__VAL_2 ;
|
|
assign reqAddr$EN =
|
|
WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ||
|
|
WILL_FIRE_RL_doStReq ;
|
|
|
|
// register reqBE
|
|
assign reqBE$D_IN =
|
|
MUX_expectWrData$write_1__SEL_1 ?
|
|
64'd0 :
|
|
MUX_reqBE$write_1__VAL_2 ;
|
|
assign reqBE$EN =
|
|
WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ||
|
|
WILL_FIRE_RL_doStReq ;
|
|
|
|
// register reqData
|
|
assign reqData$D_IN =
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d722 ;
|
|
assign reqData$EN = WILL_FIRE_RL_doStReq ;
|
|
|
|
// register reqSel
|
|
assign reqSel$D_IN =
|
|
MUX_expectWrData$write_1__SEL_1 ?
|
|
hostWrAddrQ_q_memory$DOB[5:3] :
|
|
MUX_reqSel$write_1__VAL_2 ;
|
|
assign reqSel$EN =
|
|
WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ||
|
|
WILL_FIRE_RL_doStReq ;
|
|
|
|
// register respStQ_clearReq_rl
|
|
assign respStQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign respStQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register respStQ_deqReq_rl
|
|
assign respStQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign respStQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respStQ_empty
|
|
assign respStQ_empty$D_IN =
|
|
respStQ_clearReq_dummy2_1$Q_OUT && respStQ_clearReq_rl ||
|
|
NOT_respStQ_enqReq_dummy2_2_read__16_31_OR_IF__ETC___d441 ;
|
|
assign respStQ_empty$EN = 1'd1 ;
|
|
|
|
// register respStQ_enqReq_rl
|
|
assign respStQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign respStQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respStQ_full
|
|
assign respStQ_full$D_IN =
|
|
(!respStQ_clearReq_dummy2_1$Q_OUT || !respStQ_clearReq_rl) &&
|
|
respStQ_enqReq_dummy2_2_read__16_AND_IF_respSt_ETC___d428 ;
|
|
assign respStQ_full$EN = 1'd1 ;
|
|
|
|
// register writing
|
|
assign writing$D_IN = MUX_expectWrData$write_1__SEL_1 ;
|
|
assign writing$EN =
|
|
WILL_FIRE_RL_doNewWrite && hostWrAddrQ_q_memory$DOB[64] ||
|
|
WILL_FIRE_RL_doStResp && pendStCnt == 8'd1 && !expectWrData ;
|
|
|
|
// submodule hostStartQ_q_memory
|
|
assign hostStartQ_q_memory$ADDRA =
|
|
hostStartQ_q_rWrPtr_rsCounter[1] ^
|
|
hostStartQ_q_rWrPtr_rsCounter[0] ;
|
|
assign hostStartQ_q_memory$ADDRB =
|
|
EN_hostIndInv_start ?
|
|
x__h8177[0] :
|
|
hostStartQ_q_rRdPtr_rsCounter_77_BIT_1_85_XOR__ETC___d214 ;
|
|
assign hostStartQ_q_memory$DIA =
|
|
MUX_busy$write_1__SEL_2 ? x_wget__h7793 : 64'd0 ;
|
|
assign hostStartQ_q_memory$DIB =
|
|
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
assign hostStartQ_q_memory$WEA = MUX_busy$write_1__SEL_2 ;
|
|
assign hostStartQ_q_memory$WEB = 1'd0 ;
|
|
assign hostStartQ_q_memory$ENA = 1'd1 ;
|
|
assign hostStartQ_q_memory$ENB = 1'd1 ;
|
|
|
|
// submodule hostWrAddrQ_q_memory
|
|
assign hostWrAddrQ_q_memory$ADDRA =
|
|
hostWrAddrQ_q_rWrPtr_rsCounter[1] ^
|
|
hostWrAddrQ_q_rWrPtr_rsCounter[0] ;
|
|
assign hostWrAddrQ_q_memory$ADDRB =
|
|
WILL_FIRE_RL_doNewWrite ?
|
|
x__h2762[0] :
|
|
hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_1_9_XOR_h_ETC___d68 ;
|
|
assign hostWrAddrQ_q_memory$DIA =
|
|
EN_hostReq_wrAddr ? x_wget__h2376 : 65'd0 ;
|
|
assign hostWrAddrQ_q_memory$DIB =
|
|
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
assign hostWrAddrQ_q_memory$WEA = EN_hostReq_wrAddr ;
|
|
assign hostWrAddrQ_q_memory$WEB = 1'd0 ;
|
|
assign hostWrAddrQ_q_memory$ENA = 1'd1 ;
|
|
assign hostWrAddrQ_q_memory$ENB = 1'd1 ;
|
|
|
|
// submodule hostWrDataQ_q_memory
|
|
assign hostWrDataQ_q_memory$ADDRA =
|
|
hostWrDataQ_q_rWrPtr_rsCounter[1] ^
|
|
hostWrDataQ_q_rWrPtr_rsCounter[0] ;
|
|
assign hostWrDataQ_q_memory$ADDRB =
|
|
WILL_FIRE_RL_doStReq ?
|
|
x__h5470[0] :
|
|
hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_1_12_XOR_ETC___d141 ;
|
|
assign hostWrDataQ_q_memory$DIA =
|
|
EN_hostReq_wrData ? x_wget__h5086 : 73'd0 ;
|
|
assign hostWrDataQ_q_memory$DIB =
|
|
73'h0AAAAAAAAAAAAAAAAAA /* unspecified value */ ;
|
|
assign hostWrDataQ_q_memory$WEA = EN_hostReq_wrData ;
|
|
assign hostWrDataQ_q_memory$WEB = 1'd0 ;
|
|
assign hostWrDataQ_q_memory$ENA = 1'd1 ;
|
|
assign hostWrDataQ_q_memory$ENB = 1'd1 ;
|
|
|
|
// submodule hostWrDoneQ_q_memory
|
|
assign hostWrDoneQ_q_memory$ADDRA =
|
|
hostWrDoneQ_q_rWrPtr_rsCounter[1] ^
|
|
hostWrDoneQ_q_rWrPtr_rsCounter[0] ;
|
|
assign hostWrDoneQ_q_memory$ADDRB =
|
|
EN_hostIndInv_wrDone ?
|
|
x__h10885[0] :
|
|
hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_1_58_XOR_ETC___d287 ;
|
|
assign hostWrDoneQ_q_memory$DIA = 1'b0 ;
|
|
assign hostWrDoneQ_q_memory$DIB = 1'b0 /* unspecified value */ ;
|
|
assign hostWrDoneQ_q_memory$WEA = MUX_writing$write_1__SEL_2 ;
|
|
assign hostWrDoneQ_q_memory$WEB = 1'd0 ;
|
|
assign hostWrDoneQ_q_memory$ENA = 1'd1 ;
|
|
assign hostWrDoneQ_q_memory$ENB = 1'd1 ;
|
|
|
|
// submodule memReqQ_clearReq_dummy2_0
|
|
assign memReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign memReqQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule memReqQ_clearReq_dummy2_1
|
|
assign memReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign memReqQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule memReqQ_deqReq_dummy2_0
|
|
assign memReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign memReqQ_deqReq_dummy2_0$EN = EN_to_mem_memReq_deq ;
|
|
|
|
// submodule memReqQ_deqReq_dummy2_1
|
|
assign memReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign memReqQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule memReqQ_deqReq_dummy2_2
|
|
assign memReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign memReqQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule memReqQ_enqReq_dummy2_0
|
|
assign memReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign memReqQ_enqReq_dummy2_0$EN = memReqQ_enqReq_lat_0$whas ;
|
|
|
|
// submodule memReqQ_enqReq_dummy2_1
|
|
assign memReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign memReqQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule memReqQ_enqReq_dummy2_2
|
|
assign memReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign memReqQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule respStQ_clearReq_dummy2_0
|
|
assign respStQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign respStQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule respStQ_clearReq_dummy2_1
|
|
assign respStQ_clearReq_dummy2_1$D_IN = 1'd1 ;
|
|
assign respStQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule respStQ_deqReq_dummy2_0
|
|
assign respStQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign respStQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_doStResp ;
|
|
|
|
// submodule respStQ_deqReq_dummy2_1
|
|
assign respStQ_deqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign respStQ_deqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule respStQ_deqReq_dummy2_2
|
|
assign respStQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign respStQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule respStQ_enqReq_dummy2_0
|
|
assign respStQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign respStQ_enqReq_dummy2_0$EN = EN_to_mem_respSt_enq ;
|
|
|
|
// submodule respStQ_enqReq_dummy2_1
|
|
assign respStQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign respStQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule respStQ_enqReq_dummy2_2
|
|
assign respStQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign respStQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187 =
|
|
hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_XOR__ETC___d186 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 =
|
|
hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XOR_h_ETC___d40 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 =
|
|
hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 =
|
|
hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 =
|
|
hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230 =
|
|
hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27_XOR_ETC___d229 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[640] :
|
|
memReqQ_enqReq_rl[640] ;
|
|
assign IF_mmio_req_wrBE_BIT_7_32_THEN_mmio_req_wrData_ETC___d858 =
|
|
{ mmio_req_wrBE[7] ?
|
|
mmio_req_wrData[63:56] :
|
|
memStartAddr[63:56],
|
|
mmio_req_wrBE[6] ?
|
|
mmio_req_wrData[55:48] :
|
|
memStartAddr[55:48],
|
|
mmio_req_wrBE[5] ?
|
|
mmio_req_wrData[47:40] :
|
|
memStartAddr[47:40],
|
|
mmio_req_wrBE[4] ?
|
|
mmio_req_wrData[39:32] :
|
|
memStartAddr[39:32] } ;
|
|
assign IF_mmio_req_wrBE_BIT_7_32_THEN_mmio_req_wrData_ETC___d865 =
|
|
{ IF_mmio_req_wrBE_BIT_7_32_THEN_mmio_req_wrData_ETC___d858,
|
|
mmio_req_wrBE[3] ?
|
|
mmio_req_wrData[31:24] :
|
|
memStartAddr[31:24],
|
|
mmio_req_wrBE[2] ?
|
|
mmio_req_wrData[23:16] :
|
|
memStartAddr[23:16] } ;
|
|
assign IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476 =
|
|
(reqSel == 3'd0) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[7:0] ;
|
|
assign IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d788 =
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[7] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[0] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[1] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[2] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[3] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[4] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[5] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[6] ||
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d780 ;
|
|
assign IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495 =
|
|
(reqSel == 3'd1) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[15:8] ;
|
|
assign IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d780 =
|
|
IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[7] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[0] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[1] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[2] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[3] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[4] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[5] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[6] ||
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d772 ;
|
|
assign IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514 =
|
|
(reqSel == 3'd2) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[23:16] ;
|
|
assign IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d772 =
|
|
IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[7] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[0] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[1] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[2] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[3] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[4] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[5] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[6] ||
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d764 ;
|
|
assign IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533 =
|
|
(reqSel == 3'd3) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[31:24] ;
|
|
assign IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d764 =
|
|
IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[7] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[0] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[1] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[2] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[3] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[4] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[5] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[6] ||
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d756 ;
|
|
assign IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552 =
|
|
(reqSel == 3'd4) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[39:32] ;
|
|
assign IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d756 =
|
|
IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[7] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[0] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[1] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[2] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[3] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[4] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[5] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[6] ||
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d748 ;
|
|
assign IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571 =
|
|
(reqSel == 3'd5) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[47:40] ;
|
|
assign IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d748 =
|
|
IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[7] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[0] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[1] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[2] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[3] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[4] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[5] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[6] ||
|
|
IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[7] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[0] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[1] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[2] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[3] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[4] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[5] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[6] ||
|
|
IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[7] ;
|
|
assign IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590 =
|
|
(reqSel == 3'd6) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[55:48] ;
|
|
assign IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608 =
|
|
(reqSel == 3'd7) ? hostWrDataQ_q_memory$DOB[8:1] : reqBE[63:56] ;
|
|
assign IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d712 =
|
|
{ (reqSel == 3'd7) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[511:448],
|
|
(reqSel == 3'd6) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[447:384],
|
|
(reqSel == 3'd5) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[383:320],
|
|
(reqSel == 3'd4) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[319:256] } ;
|
|
assign IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d717 =
|
|
{ IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d712,
|
|
(reqSel == 3'd3) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[255:192],
|
|
(reqSel == 3'd2) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[191:128] } ;
|
|
assign IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d722 =
|
|
{ IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d717,
|
|
(reqSel == 3'd1) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[127:64],
|
|
(reqSel == 3'd0) ?
|
|
hostWrDataQ_q_memory$DOB[72:9] :
|
|
reqData[63:0] } ;
|
|
assign NOT_IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wD_ETC___d680 =
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[7] &&
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[0] &&
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[1] &&
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[2] &&
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[3] &&
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[4] &&
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[5] &&
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[6] &&
|
|
NOT_IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wD_ETC___d672 ;
|
|
assign NOT_IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wD_ETC___d689 =
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[0] &&
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[1] &&
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[2] &&
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[3] &&
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[4] &&
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[5] &&
|
|
!IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[6] &&
|
|
NOT_IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wD_ETC___d680 ||
|
|
!memReqQ_full ;
|
|
assign NOT_IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wD_ETC___d672 =
|
|
!IF_reqSel_65_EQ_1_93_THEN_hostWrDataQ_q_wDataO_ETC___d495[7] &&
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[0] &&
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[1] &&
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[2] &&
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[3] &&
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[4] &&
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[5] &&
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[6] &&
|
|
NOT_IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wD_ETC___d664 ;
|
|
assign NOT_IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wD_ETC___d664 =
|
|
!IF_reqSel_65_EQ_2_12_THEN_hostWrDataQ_q_wDataO_ETC___d514[7] &&
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[0] &&
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[1] &&
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[2] &&
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[3] &&
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[4] &&
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[5] &&
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[6] &&
|
|
NOT_IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wD_ETC___d656 ;
|
|
assign NOT_IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wD_ETC___d656 =
|
|
!IF_reqSel_65_EQ_3_31_THEN_hostWrDataQ_q_wDataO_ETC___d533[7] &&
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[0] &&
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[1] &&
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[2] &&
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[3] &&
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[4] &&
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[5] &&
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[6] &&
|
|
NOT_IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wD_ETC___d648 ;
|
|
assign NOT_IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wD_ETC___d648 =
|
|
!IF_reqSel_65_EQ_4_50_THEN_hostWrDataQ_q_wDataO_ETC___d552[7] &&
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[0] &&
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[1] &&
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[2] &&
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[3] &&
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[4] &&
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[5] &&
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[6] &&
|
|
NOT_IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wD_ETC___d640 ;
|
|
assign NOT_IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wD_ETC___d640 =
|
|
!IF_reqSel_65_EQ_5_69_THEN_hostWrDataQ_q_wDataO_ETC___d571[7] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[0] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[1] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[2] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[3] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[4] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[5] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[6] &&
|
|
!IF_reqSel_65_EQ_6_88_THEN_hostWrDataQ_q_wDataO_ETC___d590[7] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[0] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[1] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[2] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[3] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[4] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[5] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[6] &&
|
|
!IF_reqSel_65_EQ_7_66_THEN_hostWrDataQ_q_wDataO_ETC___d608[7] ;
|
|
assign NOT_hostStartQ_q_rWrPtr_rsCounter_47_EQ_hostSt_ETC___d905 =
|
|
hostStartQ_q_rWrPtr_rsCounter !=
|
|
{ hostStartQ_q_rRdPtr_rdCounter_92_BIT_1_93_CONC_ETC___d897[1],
|
|
hostStartQ_q_rRdPtr_rdCounter_92_BIT_1_93_CONC_ETC___d897[1] ^
|
|
hostStartQ_q_rRdPtr_rdCounter_92_BIT_1_93_CONC_ETC___d897[0] } &&
|
|
hostStartQ_srcGuard$IS_READY ;
|
|
assign NOT_hostWrDoneQ_q_rWrPtr_rsCounter_20_EQ_hostW_ETC___d818 =
|
|
hostWrDoneQ_q_rWrPtr_rsCounter !=
|
|
{ hostWrDoneQ_q_rRdPtr_rdCounter_05_BIT_1_06_CON_ETC___d810[1],
|
|
hostWrDoneQ_q_rRdPtr_rdCounter_05_BIT_1_06_CON_ETC___d810[1] ^
|
|
hostWrDoneQ_q_rRdPtr_rdCounter_05_BIT_1_06_CON_ETC___d810[0] } &&
|
|
hostWrDoneQ_srcGuard$IS_READY ;
|
|
assign NOT_memReqQ_clearReq_dummy2_1_read__40_41_OR_I_ETC___d345 =
|
|
!memReqQ_clearReq_dummy2_1$Q_OUT || !memReqQ_clearReq_rl ;
|
|
assign NOT_memReqQ_enqReq_dummy2_2_read__46_61_OR_IF__ETC___d366 =
|
|
(!memReqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(memReqQ_enqReq_lat_0$whas ?
|
|
!memReqQ_enqReq_lat_0$wget[640] :
|
|
!memReqQ_enqReq_rl[640])) &&
|
|
(memReqQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_to_mem_memReq_deq || memReqQ_deqReq_rl) ||
|
|
memReqQ_empty) ;
|
|
assign NOT_respStQ_enqReq_dummy2_2_read__16_31_OR_IF__ETC___d441 =
|
|
(!respStQ_enqReq_dummy2_2$Q_OUT ||
|
|
!EN_to_mem_respSt_enq && !respStQ_enqReq_rl) &&
|
|
(respStQ_deqReq_dummy2_2$Q_OUT &&
|
|
(CAN_FIRE_RL_doStResp || respStQ_deqReq_rl) ||
|
|
respStQ_empty) ;
|
|
assign av_avValue_data__h91897 =
|
|
mmio_req_offset ? { 63'd0, busy } : memStartAddr ;
|
|
assign hostStartQ_q_rRdPtr_rdCounter_92_BIT_1_93_CONC_ETC___d897 =
|
|
x_dReadBin__h7630 + 2'd1 ;
|
|
assign hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_XOR__ETC___d186 =
|
|
hostStartQ_q_rRdPtr_rsCounter[0] ^
|
|
hostStartQ_q_rRdPtr_rsCounter[1] ;
|
|
assign hostStartQ_q_rRdPtr_rsCounter_77_BIT_1_85_XOR__ETC___d214 =
|
|
hostStartQ_q_rRdPtr_rsCounter[1] ^
|
|
hostStartQ_q_rRdPtr_rsCounter[0] ;
|
|
assign hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_XOR__ETC___d156 =
|
|
hostStartQ_q_rWrPtr_rsCounter[0] ^
|
|
hostStartQ_q_rWrPtr_rsCounter[1] ;
|
|
assign hostWrAddrQ_q_rRdPtr_rdCounter_10_BIT_1_11_CON_ETC___d915 =
|
|
x_dReadBin__h2213 + 2'd1 ;
|
|
assign hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XOR_h_ETC___d40 =
|
|
hostWrAddrQ_q_rRdPtr_rsCounter[0] ^
|
|
hostWrAddrQ_q_rRdPtr_rsCounter[1] ;
|
|
assign hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_1_9_XOR_h_ETC___d68 =
|
|
hostWrAddrQ_q_rRdPtr_rsCounter[1] ^
|
|
hostWrAddrQ_q_rRdPtr_rsCounter[0] ;
|
|
assign hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_hostW_ETC___d10 =
|
|
hostWrAddrQ_q_rWrPtr_rsCounter[0] ^
|
|
hostWrAddrQ_q_rWrPtr_rsCounter[1] ;
|
|
assign hostWrDataQ_q_rRdPtr_rdCounter_24_BIT_1_25_CON_ETC___d929 =
|
|
x_dReadBin__h4923 + 2'd1 ;
|
|
assign hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 =
|
|
hostWrDataQ_q_rRdPtr_rsCounter[0] ^
|
|
hostWrDataQ_q_rRdPtr_rsCounter[1] ;
|
|
assign hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_1_12_XOR_ETC___d141 =
|
|
hostWrDataQ_q_rRdPtr_rsCounter[1] ^
|
|
hostWrDataQ_q_rRdPtr_rsCounter[0] ;
|
|
assign hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XOR_h_ETC___d83 =
|
|
hostWrDataQ_q_rWrPtr_rsCounter[0] ^
|
|
hostWrDataQ_q_rWrPtr_rsCounter[1] ;
|
|
assign hostWrDoneQ_q_rRdPtr_rdCounter_05_BIT_1_06_CON_ETC___d810 =
|
|
x_dReadBin__h10337 + 2'd1 ;
|
|
assign hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57_XOR_ETC___d259 =
|
|
hostWrDoneQ_q_rRdPtr_rsCounter[0] ^
|
|
hostWrDoneQ_q_rRdPtr_rsCounter[1] ;
|
|
assign hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_1_58_XOR_ETC___d287 =
|
|
hostWrDoneQ_q_rRdPtr_rsCounter[1] ^
|
|
hostWrDoneQ_q_rRdPtr_rsCounter[0] ;
|
|
assign hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27_XOR_ETC___d229 =
|
|
hostWrDoneQ_q_rWrPtr_rsCounter[0] ^
|
|
hostWrDoneQ_q_rWrPtr_rsCounter[1] ;
|
|
assign memReqQ_enqReq_dummy2_2_read__46_AND_IF_memReq_ETC___d358 =
|
|
memReqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_memReqQ_enqReq_lat_1_whas__96_THEN_memReqQ__ETC___d305 ||
|
|
(!memReqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_to_mem_memReq_deq && !memReqQ_deqReq_rl) &&
|
|
memReqQ_full ;
|
|
assign mmio_req_wrBE_BIT_0_25_OR_mmio_req_wrBE_BIT_1__ETC___d843 =
|
|
(mmio_req_wrBE[0] || mmio_req_wrBE[1] || mmio_req_wrBE[2] ||
|
|
mmio_req_wrBE[3] ||
|
|
mmio_req_wrBE[4] ||
|
|
mmio_req_wrBE[5] ||
|
|
mmio_req_wrBE[6] ||
|
|
mmio_req_wrBE[7]) &&
|
|
!mmio_req_offset &&
|
|
!busy ;
|
|
assign reqSel_65_EQ_7_66_OR_hostWrDataQ_q_wDataOut_wg_ETC___d796 =
|
|
(reqSel == 3'd7 || hostWrDataQ_q_memory$DOB[0]) &&
|
|
(IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[0] ||
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[1] ||
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[2] ||
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[3] ||
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[4] ||
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[5] ||
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d476[6] ||
|
|
IF_reqSel_65_EQ_0_72_THEN_hostWrDataQ_q_wDataO_ETC___d788) ;
|
|
assign req_addr__h75332 = { reqAddr, 6'd0 } ;
|
|
assign respStQ_enqReq_dummy2_2_read__16_AND_IF_respSt_ETC___d428 =
|
|
respStQ_enqReq_dummy2_2$Q_OUT &&
|
|
(EN_to_mem_respSt_enq || respStQ_enqReq_rl) ||
|
|
(!respStQ_deqReq_dummy2_2$Q_OUT ||
|
|
!CAN_FIRE_RL_doStResp && !respStQ_deqReq_rl) &&
|
|
respStQ_full ;
|
|
assign x__h10885 = x_sReadBin__h10334 + 2'd1 ;
|
|
assign x__h1801 =
|
|
2'd1 <<
|
|
IF_hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_0_8_XO_ETC___d41 ;
|
|
assign x__h2762 = x_sReadBin__h2210 + 2'd1 ;
|
|
assign x__h3656 =
|
|
2'd1 <<
|
|
IF_hostWrDataQ_q_rWrPtr_rsCounter_4_BIT_0_1_XO_ETC___d84 ;
|
|
assign x__h4511 = 2'd1 << x__h4676 ;
|
|
assign x__h4676 =
|
|
hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_0_11_XOR_ETC___d113 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign x__h5470 = x_sReadBin__h4920 + 2'd1 ;
|
|
assign x__h6363 = 2'd1 << x__h6528 ;
|
|
assign x__h6528 =
|
|
hostStartQ_q_rWrPtr_rsCounter_47_BIT_0_54_XOR__ETC___d156 ?
|
|
32'd1 :
|
|
32'd0 ;
|
|
assign x__h7218 =
|
|
2'd1 <<
|
|
IF_hostStartQ_q_rRdPtr_rsCounter_77_BIT_0_84_X_ETC___d187 ;
|
|
assign x__h8177 = x_sReadBin__h7627 + 2'd1 ;
|
|
assign x__h9070 =
|
|
2'd1 <<
|
|
IF_hostWrDoneQ_q_rWrPtr_rsCounter_20_BIT_0_27__ETC___d230 ;
|
|
assign x__h938 =
|
|
2'd1 <<
|
|
IF_hostWrAddrQ_q_rWrPtr_rsCounter_BIT_0_XOR_ho_ETC___d11 ;
|
|
assign x__h9925 =
|
|
2'd1 <<
|
|
IF_hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_0_57__ETC___d260 ;
|
|
assign x_addr__h43806 =
|
|
memReqQ_enqReq_lat_0$whas ?
|
|
memReqQ_enqReq_lat_0$wget[639:576] :
|
|
memReqQ_enqReq_rl[639:576] ;
|
|
assign x_dReadBin__h10337 =
|
|
{ hostWrDoneQ_q_rRdPtr_rdCounter[1],
|
|
hostWrDoneQ_q_rRdPtr_rdCounter[1] ^
|
|
hostWrDoneQ_q_rRdPtr_rdCounter[0] } ;
|
|
assign x_dReadBin__h2213 =
|
|
{ hostWrAddrQ_q_rRdPtr_rdCounter[1],
|
|
hostWrAddrQ_q_rRdPtr_rdCounter[1] ^
|
|
hostWrAddrQ_q_rRdPtr_rdCounter[0] } ;
|
|
assign x_dReadBin__h4923 =
|
|
{ hostWrDataQ_q_rRdPtr_rdCounter[1],
|
|
hostWrDataQ_q_rRdPtr_rdCounter[1] ^
|
|
hostWrDataQ_q_rRdPtr_rdCounter[0] } ;
|
|
assign x_dReadBin__h7630 =
|
|
{ hostStartQ_q_rRdPtr_rdCounter[1],
|
|
hostStartQ_q_rRdPtr_rdCounter[1] ^
|
|
hostStartQ_q_rRdPtr_rdCounter[0] } ;
|
|
assign x_sReadBin__h10334 =
|
|
{ hostWrDoneQ_q_rRdPtr_rsCounter[1],
|
|
hostWrDoneQ_q_rRdPtr_rsCounter_50_BIT_1_58_XOR_ETC___d287 } ;
|
|
assign x_sReadBin__h2210 =
|
|
{ hostWrAddrQ_q_rRdPtr_rsCounter[1],
|
|
hostWrAddrQ_q_rRdPtr_rsCounter_1_BIT_1_9_XOR_h_ETC___d68 } ;
|
|
assign x_sReadBin__h4920 =
|
|
{ hostWrDataQ_q_rRdPtr_rsCounter[1],
|
|
hostWrDataQ_q_rRdPtr_rsCounter_04_BIT_1_12_XOR_ETC___d141 } ;
|
|
assign x_sReadBin__h7627 =
|
|
{ hostStartQ_q_rRdPtr_rsCounter[1],
|
|
hostStartQ_q_rRdPtr_rsCounter_77_BIT_1_85_XOR__ETC___d214 } ;
|
|
assign x_wget__h2376 = { hostReq_wrAddr_valid, hostReq_wrAddr_addr } ;
|
|
assign x_wget__h5086 =
|
|
{ hostReq_wrData_data,
|
|
hostReq_wrData_byteEn,
|
|
hostReq_wrData_last } ;
|
|
assign x_wget__h7793 =
|
|
{ IF_mmio_req_wrBE_BIT_7_32_THEN_mmio_req_wrData_ETC___d865,
|
|
mmio_req_wrBE[1] ? mmio_req_wrData[15:8] : memStartAddr[15:8],
|
|
mmio_req_wrBE[0] ? mmio_req_wrData[7:0] : memStartAddr[7:0] } ;
|
|
assign y__h10112 = ~x__h9925 ;
|
|
assign y__h1133 = ~x__h938 ;
|
|
assign y__h1988 = ~x__h1801 ;
|
|
assign y__h3843 = ~x__h3656 ;
|
|
assign y__h4698 = ~x__h4511 ;
|
|
assign y__h6550 = ~x__h6363 ;
|
|
assign y__h7405 = ~x__h7218 ;
|
|
assign y__h9257 = ~x__h9070 ;
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
busy <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
expectWrData <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 640'd0;
|
|
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
641'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
memReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
memStartAddr <= `BSV_ASSIGNMENT_DELAY 64'd0;
|
|
pendStCnt <= `BSV_ASSIGNMENT_DELAY 8'd0;
|
|
respStQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respStQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respStQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
respStQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respStQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
writing <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (busy$EN) busy <= `BSV_ASSIGNMENT_DELAY busy$D_IN;
|
|
if (expectWrData$EN)
|
|
expectWrData <= `BSV_ASSIGNMENT_DELAY expectWrData$D_IN;
|
|
if (memReqQ_clearReq_rl$EN)
|
|
memReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
memReqQ_clearReq_rl$D_IN;
|
|
if (memReqQ_data_0$EN)
|
|
memReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY memReqQ_data_0$D_IN;
|
|
if (memReqQ_deqReq_rl$EN)
|
|
memReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_deqReq_rl$D_IN;
|
|
if (memReqQ_empty$EN)
|
|
memReqQ_empty <= `BSV_ASSIGNMENT_DELAY memReqQ_empty$D_IN;
|
|
if (memReqQ_enqReq_rl$EN)
|
|
memReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY memReqQ_enqReq_rl$D_IN;
|
|
if (memReqQ_full$EN)
|
|
memReqQ_full <= `BSV_ASSIGNMENT_DELAY memReqQ_full$D_IN;
|
|
if (memStartAddr$EN)
|
|
memStartAddr <= `BSV_ASSIGNMENT_DELAY memStartAddr$D_IN;
|
|
if (pendStCnt$EN) pendStCnt <= `BSV_ASSIGNMENT_DELAY pendStCnt$D_IN;
|
|
if (respStQ_clearReq_rl$EN)
|
|
respStQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
|
|
respStQ_clearReq_rl$D_IN;
|
|
if (respStQ_deqReq_rl$EN)
|
|
respStQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY respStQ_deqReq_rl$D_IN;
|
|
if (respStQ_empty$EN)
|
|
respStQ_empty <= `BSV_ASSIGNMENT_DELAY respStQ_empty$D_IN;
|
|
if (respStQ_enqReq_rl$EN)
|
|
respStQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY respStQ_enqReq_rl$D_IN;
|
|
if (respStQ_full$EN)
|
|
respStQ_full <= `BSV_ASSIGNMENT_DELAY respStQ_full$D_IN;
|
|
if (writing$EN) writing <= `BSV_ASSIGNMENT_DELAY writing$D_IN;
|
|
end
|
|
if (reqAddr$EN) reqAddr <= `BSV_ASSIGNMENT_DELAY reqAddr$D_IN;
|
|
if (reqBE$EN) reqBE <= `BSV_ASSIGNMENT_DELAY reqBE$D_IN;
|
|
if (reqData$EN) reqData <= `BSV_ASSIGNMENT_DELAY reqData$D_IN;
|
|
if (reqSel$EN) reqSel <= `BSV_ASSIGNMENT_DELAY reqSel$D_IN;
|
|
end
|
|
|
|
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
hostStartQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostStartQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostStartQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrAddrQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrAddrQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrAddrQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDataQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDataQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDataQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDoneQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDoneQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDoneQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (hostStartQ_q_rRdPtr_rdCounter$EN)
|
|
hostStartQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostStartQ_q_rRdPtr_rdCounter$D_IN;
|
|
if (hostStartQ_q_rRdPtr_rdCounterPre$EN)
|
|
hostStartQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostStartQ_q_rRdPtr_rdCounterPre$D_IN;
|
|
if (hostStartQ_q_rWrPtr_rsCounter$EN)
|
|
hostStartQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostStartQ_q_rWrPtr_rsCounter$D_IN;
|
|
if (hostWrAddrQ_q_rRdPtr_rsCounter$EN)
|
|
hostWrAddrQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrAddrQ_q_rRdPtr_rsCounter$D_IN;
|
|
if (hostWrAddrQ_q_rWrPtr_rdCounter$EN)
|
|
hostWrAddrQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrAddrQ_q_rWrPtr_rdCounter$D_IN;
|
|
if (hostWrAddrQ_q_rWrPtr_rdCounterPre$EN)
|
|
hostWrAddrQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrAddrQ_q_rWrPtr_rdCounterPre$D_IN;
|
|
if (hostWrDataQ_q_rRdPtr_rsCounter$EN)
|
|
hostWrDataQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDataQ_q_rRdPtr_rsCounter$D_IN;
|
|
if (hostWrDataQ_q_rWrPtr_rdCounter$EN)
|
|
hostWrDataQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDataQ_q_rWrPtr_rdCounter$D_IN;
|
|
if (hostWrDataQ_q_rWrPtr_rdCounterPre$EN)
|
|
hostWrDataQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDataQ_q_rWrPtr_rdCounterPre$D_IN;
|
|
if (hostWrDoneQ_q_rRdPtr_rdCounter$EN)
|
|
hostWrDoneQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDoneQ_q_rRdPtr_rdCounter$D_IN;
|
|
if (hostWrDoneQ_q_rRdPtr_rdCounterPre$EN)
|
|
hostWrDoneQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDoneQ_q_rRdPtr_rdCounterPre$D_IN;
|
|
if (hostWrDoneQ_q_rWrPtr_rsCounter$EN)
|
|
hostWrDoneQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDoneQ_q_rWrPtr_rsCounter$D_IN;
|
|
end
|
|
|
|
always@(posedge CLK_portalClk or `BSV_RESET_EDGE RST_N_portalRst)
|
|
if (RST_N_portalRst == `BSV_RESET_VALUE)
|
|
begin
|
|
hostStartQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostStartQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostStartQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrAddrQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrAddrQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrAddrQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDataQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDataQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDataQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDoneQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDoneQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
hostWrDoneQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 2'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (hostStartQ_q_rRdPtr_rsCounter$EN)
|
|
hostStartQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostStartQ_q_rRdPtr_rsCounter$D_IN;
|
|
if (hostStartQ_q_rWrPtr_rdCounter$EN)
|
|
hostStartQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostStartQ_q_rWrPtr_rdCounter$D_IN;
|
|
if (hostStartQ_q_rWrPtr_rdCounterPre$EN)
|
|
hostStartQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostStartQ_q_rWrPtr_rdCounterPre$D_IN;
|
|
if (hostWrAddrQ_q_rRdPtr_rdCounter$EN)
|
|
hostWrAddrQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrAddrQ_q_rRdPtr_rdCounter$D_IN;
|
|
if (hostWrAddrQ_q_rRdPtr_rdCounterPre$EN)
|
|
hostWrAddrQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrAddrQ_q_rRdPtr_rdCounterPre$D_IN;
|
|
if (hostWrAddrQ_q_rWrPtr_rsCounter$EN)
|
|
hostWrAddrQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrAddrQ_q_rWrPtr_rsCounter$D_IN;
|
|
if (hostWrDataQ_q_rRdPtr_rdCounter$EN)
|
|
hostWrDataQ_q_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDataQ_q_rRdPtr_rdCounter$D_IN;
|
|
if (hostWrDataQ_q_rRdPtr_rdCounterPre$EN)
|
|
hostWrDataQ_q_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDataQ_q_rRdPtr_rdCounterPre$D_IN;
|
|
if (hostWrDataQ_q_rWrPtr_rsCounter$EN)
|
|
hostWrDataQ_q_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDataQ_q_rWrPtr_rsCounter$D_IN;
|
|
if (hostWrDoneQ_q_rRdPtr_rsCounter$EN)
|
|
hostWrDoneQ_q_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDoneQ_q_rRdPtr_rsCounter$D_IN;
|
|
if (hostWrDoneQ_q_rWrPtr_rdCounter$EN)
|
|
hostWrDoneQ_q_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDoneQ_q_rWrPtr_rdCounter$D_IN;
|
|
if (hostWrDoneQ_q_rWrPtr_rdCounterPre$EN)
|
|
hostWrDoneQ_q_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
|
|
hostWrDoneQ_q_rWrPtr_rdCounterPre$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
busy = 1'h0;
|
|
expectWrData = 1'h0;
|
|
hostStartQ_q_rRdPtr_rdCounter = 2'h2;
|
|
hostStartQ_q_rRdPtr_rdCounterPre = 2'h2;
|
|
hostStartQ_q_rRdPtr_rsCounter = 2'h2;
|
|
hostStartQ_q_rWrPtr_rdCounter = 2'h2;
|
|
hostStartQ_q_rWrPtr_rdCounterPre = 2'h2;
|
|
hostStartQ_q_rWrPtr_rsCounter = 2'h2;
|
|
hostWrAddrQ_q_rRdPtr_rdCounter = 2'h2;
|
|
hostWrAddrQ_q_rRdPtr_rdCounterPre = 2'h2;
|
|
hostWrAddrQ_q_rRdPtr_rsCounter = 2'h2;
|
|
hostWrAddrQ_q_rWrPtr_rdCounter = 2'h2;
|
|
hostWrAddrQ_q_rWrPtr_rdCounterPre = 2'h2;
|
|
hostWrAddrQ_q_rWrPtr_rsCounter = 2'h2;
|
|
hostWrDataQ_q_rRdPtr_rdCounter = 2'h2;
|
|
hostWrDataQ_q_rRdPtr_rdCounterPre = 2'h2;
|
|
hostWrDataQ_q_rRdPtr_rsCounter = 2'h2;
|
|
hostWrDataQ_q_rWrPtr_rdCounter = 2'h2;
|
|
hostWrDataQ_q_rWrPtr_rdCounterPre = 2'h2;
|
|
hostWrDataQ_q_rWrPtr_rsCounter = 2'h2;
|
|
hostWrDoneQ_q_rRdPtr_rdCounter = 2'h2;
|
|
hostWrDoneQ_q_rRdPtr_rdCounterPre = 2'h2;
|
|
hostWrDoneQ_q_rRdPtr_rsCounter = 2'h2;
|
|
hostWrDoneQ_q_rWrPtr_rdCounter = 2'h2;
|
|
hostWrDoneQ_q_rWrPtr_rdCounterPre = 2'h2;
|
|
hostWrDoneQ_q_rWrPtr_rsCounter = 2'h2;
|
|
memReqQ_clearReq_rl = 1'h0;
|
|
memReqQ_data_0 =
|
|
640'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
memReqQ_deqReq_rl = 1'h0;
|
|
memReqQ_empty = 1'h0;
|
|
memReqQ_enqReq_rl =
|
|
641'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
memReqQ_full = 1'h0;
|
|
memStartAddr = 64'hAAAAAAAAAAAAAAAA;
|
|
pendStCnt = 8'hAA;
|
|
reqAddr = 58'h2AAAAAAAAAAAAAA;
|
|
reqBE = 64'hAAAAAAAAAAAAAAAA;
|
|
reqData =
|
|
512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
|
|
reqSel = 3'h2;
|
|
respStQ_clearReq_rl = 1'h0;
|
|
respStQ_deqReq_rl = 1'h0;
|
|
respStQ_empty = 1'h0;
|
|
respStQ_enqReq_rl = 1'h0;
|
|
respStQ_full = 1'h0;
|
|
writing = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkMemLoader
|
|
|