111 lines
2.7 KiB
Verilog
111 lines
2.7 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_request_put O 1 reg
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// response_get O 69 reg
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// RDY_response_get O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// request_put I 131
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// EN_request_put I 1
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// EN_response_get I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkXilinxFpDivSim(CLK,
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RST_N,
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request_put,
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EN_request_put,
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RDY_request_put,
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EN_response_get,
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response_get,
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RDY_response_get);
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input CLK;
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input RST_N;
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// action method request_put
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input [130 : 0] request_put;
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input EN_request_put;
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output RDY_request_put;
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// actionvalue method response_get
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input EN_response_get;
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output [68 : 0] response_get;
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output RDY_response_get;
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// signals for module outputs
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wire [68 : 0] response_get;
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wire RDY_request_put, RDY_response_get;
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// ports of submodule fpDiv
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wire [63 : 0] fpDiv$A, fpDiv$B, fpDiv$RES;
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// ports of submodule respQ
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wire [68 : 0] respQ$D_IN, respQ$D_OUT;
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wire respQ$CLR, respQ$DEQ, respQ$EMPTY_N, respQ$ENQ, respQ$FULL_N;
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// rule scheduling signals
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wire CAN_FIRE_request_put,
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CAN_FIRE_response_get,
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WILL_FIRE_request_put,
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WILL_FIRE_response_get;
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// action method request_put
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assign RDY_request_put = respQ$FULL_N ;
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assign CAN_FIRE_request_put = respQ$FULL_N ;
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assign WILL_FIRE_request_put = EN_request_put ;
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// actionvalue method response_get
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assign response_get = respQ$D_OUT ;
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assign RDY_response_get = respQ$EMPTY_N ;
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assign CAN_FIRE_response_get = respQ$EMPTY_N ;
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assign WILL_FIRE_response_get = EN_response_get ;
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// submodule fpDiv
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fp_div_sim fpDiv(.A(fpDiv$A), .B(fpDiv$B), .RES(fpDiv$RES));
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// submodule respQ
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FIFO2 #(.width(32'd69), .guarded(32'd1)) respQ(.RST(RST_N),
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.CLK(CLK),
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.D_IN(respQ$D_IN),
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.ENQ(respQ$ENQ),
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.DEQ(respQ$DEQ),
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.CLR(respQ$CLR),
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.D_OUT(respQ$D_OUT),
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.FULL_N(respQ$FULL_N),
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.EMPTY_N(respQ$EMPTY_N));
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// submodule fpDiv
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assign fpDiv$A = request_put[130:67] ;
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assign fpDiv$B = request_put[66:3] ;
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// submodule respQ
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assign respQ$D_IN = { fpDiv$RES, 5'd0 } ;
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assign respQ$ENQ = EN_request_put ;
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assign respQ$DEQ = EN_response_get ;
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assign respQ$CLR = 1'b0 ;
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endmodule // mkXilinxFpDivSim
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