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Toooba/src_SSITH_P3/xilinx_ip/hdl
History
Niraj Sharma e35c48efff Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
..
BRAM2.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
FIFO1.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO2.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO10.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
FIFO20.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFOL1.v
Add missing module (FIFOL1) to Xilinx import.
2019-04-24 21:34:52 -04:00
MakeClock.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
MakeResetA.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
mkAluDispToRegFifo.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkAluExeToFinFifo.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkAluRegToExeFifo.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkBht.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkCore.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkCoreW.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDCRqMshrWrapper.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDebug_Module.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDirPredictor.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDivExecQ.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDM_Abstract_Commands.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDM_CSR_Tap.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkDM_GPR_Tap.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkDM_Mem_Tap.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkDM_Run_Control.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDM_System_Bus.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDoubleDiv.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDoubleFMA.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDoubleSqrt.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDPipeline.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDPRqMshrWrapper.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDTlbSynth.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkDummyStoreBuffer.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkEpochManager.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkFabric_2x3.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkFetchStage.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkFmaExecQ.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkFpuMulDivDispToRegFifo.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkFpuMulDivRegToExeFifo.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkGSelectGHistReg.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkGSelectPred.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkGShareGHistReg.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkGSharePred.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkIBankWrapper.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkICoCache.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkICRqMshrWrapper.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkIPipeline.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkIPRqMshrWrapper.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkITlb.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkJtagTap.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkL2Tlb.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkLastLvCRqMshr.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkLLCache.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkLLPipeline.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkLSQIssueLdQ.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkMemDispToRegFifo.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkMemLoader.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkMemRegToExeFifo.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkMinimumExecQ.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkMMIOInst.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkMulExecQ.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkNullTransCache.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkP3_Core.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkPLIC_16_2_7.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkProc.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkRas.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkRegRenamingTable.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkReorderBufferSynth.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkReservationStationAlu.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkReservationStationFpuMulDiv.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkReservationStationMem.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkRFileSynth.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkRobRowSynth.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkScoreboardAggr.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkScoreboardCons.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkSimpleRespQ.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkSoC_Map.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkSpecTagManager.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkSplitLSQ.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkSplitTransCache.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkStoreBufferEhr.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkSyncBramFifo_w36_d512.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkSyncFifo_w32_d16.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkTourGHistReg.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkTourPred.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkTourPredSecure.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkTV_Encode.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkTV_Xactor.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkXilinxFpDiv.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpDivIP.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpDivSim.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpFma.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpFmaIP.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpFmaSim.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpSqrt.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpSqrtIP.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
mkXilinxFpSqrtSim.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_alu.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_aluBr.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_amoExec.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_basicExec.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_brAddrCalc.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_checkForException.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_decode.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_decodeBrPred.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_execFpuSimple.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
module_getControlFlow.v
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
RegFile.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
reset_guard.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
ResetEither.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
RevertReg.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
SizedFIFO0.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SizedFIFO.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
SyncFIFOLevel.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncHandshake.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncResetA.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00