1721 lines
61 KiB
Verilog
1721 lines
61 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta1 (build b38abf678, 2019-05-06)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_reset O 1 const
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// av_read O 32
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// RDY_av_read O 1
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// RDY_write O 1
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// master_awvalid O 1
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// master_awid O 4 reg
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// master_awaddr O 64 reg
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// master_awlen O 8 reg
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// master_awsize O 3 reg
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// master_awburst O 2 reg
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// master_awlock O 1 reg
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// master_awcache O 4 reg
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// master_awprot O 3 reg
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// master_awqos O 4 reg
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// master_awregion O 4 reg
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// master_wvalid O 1
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// master_wid O 4 reg
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// master_wdata O 64 reg
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// master_wstrb O 8 reg
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// master_wlast O 1 reg
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// master_bready O 1 const
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// master_arvalid O 1
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// master_arid O 4 reg
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// master_araddr O 64 reg
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// master_arlen O 8 reg
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// master_arsize O 3 reg
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// master_arburst O 2 reg
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// master_arlock O 1 reg
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// master_arcache O 4 reg
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// master_arprot O 3 reg
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// master_arqos O 4 reg
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// master_arregion O 4 reg
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// master_rready O 1
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// CLK I 1 clock
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// RST_N I 1 reset
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// av_read_dm_addr I 7
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// write_dm_addr I 7
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// write_dm_word I 32
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// master_awready I 1
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// master_wready I 1
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// master_bvalid I 1
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// master_bid I 4 reg
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// master_bresp I 2 reg
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// master_arready I 1
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// master_rvalid I 1
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// master_rid I 4 reg
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// master_rdata I 64 reg
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// master_rresp I 2 reg
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// master_rlast I 1 reg
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// EN_reset I 1
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// EN_write I 1
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// EN_av_read I 1
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//
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// Combinational paths from inputs to outputs:
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// (master_awready, master_wready, master_arready) -> RDY_write
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// master_arready -> RDY_av_read
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// (master_arready, av_read_dm_addr) -> av_read
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDM_System_Bus(CLK,
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RST_N,
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EN_reset,
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RDY_reset,
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av_read_dm_addr,
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EN_av_read,
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av_read,
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RDY_av_read,
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write_dm_addr,
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write_dm_word,
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EN_write,
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RDY_write,
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master_awvalid,
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master_awid,
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master_awaddr,
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master_awlen,
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master_awsize,
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master_awburst,
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master_awlock,
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master_awcache,
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master_awprot,
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master_awqos,
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master_awregion,
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master_awready,
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master_wvalid,
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master_wid,
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master_wdata,
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master_wstrb,
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master_wlast,
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master_wready,
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master_bvalid,
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master_bid,
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master_bresp,
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master_bready,
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master_arvalid,
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master_arid,
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master_araddr,
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master_arlen,
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master_arsize,
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master_arburst,
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master_arlock,
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master_arcache,
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master_arprot,
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master_arqos,
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master_arregion,
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master_arready,
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master_rvalid,
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master_rid,
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master_rdata,
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master_rresp,
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master_rlast,
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master_rready);
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input CLK;
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input RST_N;
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// action method reset
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input EN_reset;
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output RDY_reset;
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// actionvalue method av_read
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input [6 : 0] av_read_dm_addr;
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input EN_av_read;
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output [31 : 0] av_read;
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output RDY_av_read;
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// action method write
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input [6 : 0] write_dm_addr;
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input [31 : 0] write_dm_word;
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input EN_write;
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output RDY_write;
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// value method master_m_awvalid
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output master_awvalid;
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// value method master_m_awid
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output [3 : 0] master_awid;
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// value method master_m_awaddr
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output [63 : 0] master_awaddr;
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// value method master_m_awlen
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output [7 : 0] master_awlen;
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// value method master_m_awsize
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output [2 : 0] master_awsize;
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// value method master_m_awburst
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output [1 : 0] master_awburst;
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// value method master_m_awlock
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output master_awlock;
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// value method master_m_awcache
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output [3 : 0] master_awcache;
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// value method master_m_awprot
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output [2 : 0] master_awprot;
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// value method master_m_awqos
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output [3 : 0] master_awqos;
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// value method master_m_awregion
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output [3 : 0] master_awregion;
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// value method master_m_awuser
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// action method master_m_awready
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input master_awready;
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// value method master_m_wvalid
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output master_wvalid;
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// value method master_m_wid
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output [3 : 0] master_wid;
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// value method master_m_wdata
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output [63 : 0] master_wdata;
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// value method master_m_wstrb
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output [7 : 0] master_wstrb;
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// value method master_m_wlast
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output master_wlast;
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// value method master_m_wuser
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// action method master_m_wready
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input master_wready;
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// action method master_m_bvalid
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input master_bvalid;
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input [3 : 0] master_bid;
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input [1 : 0] master_bresp;
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// value method master_m_bready
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output master_bready;
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// value method master_m_arvalid
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output master_arvalid;
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// value method master_m_arid
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output [3 : 0] master_arid;
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// value method master_m_araddr
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output [63 : 0] master_araddr;
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// value method master_m_arlen
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output [7 : 0] master_arlen;
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// value method master_m_arsize
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output [2 : 0] master_arsize;
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// value method master_m_arburst
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output [1 : 0] master_arburst;
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// value method master_m_arlock
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output master_arlock;
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// value method master_m_arcache
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output [3 : 0] master_arcache;
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// value method master_m_arprot
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output [2 : 0] master_arprot;
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// value method master_m_arqos
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output [3 : 0] master_arqos;
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// value method master_m_arregion
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output [3 : 0] master_arregion;
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// value method master_m_aruser
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// action method master_m_arready
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input master_arready;
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// action method master_m_rvalid
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input master_rvalid;
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input [3 : 0] master_rid;
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input [63 : 0] master_rdata;
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input [1 : 0] master_rresp;
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input master_rlast;
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// value method master_m_rready
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output master_rready;
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// signals for module outputs
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reg [31 : 0] av_read;
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wire [63 : 0] master_araddr, master_awaddr, master_wdata;
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wire [7 : 0] master_arlen, master_awlen, master_wstrb;
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wire [3 : 0] master_arcache,
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master_arid,
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master_arqos,
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master_arregion,
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master_awcache,
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master_awid,
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master_awqos,
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master_awregion,
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master_wid;
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wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize;
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wire [1 : 0] master_arburst, master_awburst;
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wire RDY_av_read,
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RDY_reset,
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RDY_write,
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master_arlock,
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master_arvalid,
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master_awlock,
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master_awvalid,
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master_bready,
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master_rready,
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master_wlast,
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master_wvalid;
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// inlined wires
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wire master_xactor_crg_rd_addr_full$EN_port1__write,
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master_xactor_crg_rd_addr_full$EN_port2__write,
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master_xactor_crg_rd_addr_full$port2__read,
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master_xactor_crg_rd_addr_full$port3__read,
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master_xactor_crg_rd_data_full$EN_port2__write,
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master_xactor_crg_rd_data_full$port2__read,
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master_xactor_crg_rd_data_full$port3__read,
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master_xactor_crg_wr_addr_full$EN_port1__write,
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master_xactor_crg_wr_addr_full$port2__read,
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master_xactor_crg_wr_addr_full$port3__read,
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master_xactor_crg_wr_data_full$EN_port1__write,
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master_xactor_crg_wr_data_full$port2__read,
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master_xactor_crg_wr_data_full$port3__read;
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// register master_xactor_crg_rd_addr_full
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reg master_xactor_crg_rd_addr_full;
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wire master_xactor_crg_rd_addr_full$D_IN, master_xactor_crg_rd_addr_full$EN;
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// register master_xactor_crg_rd_data_full
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reg master_xactor_crg_rd_data_full;
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wire master_xactor_crg_rd_data_full$D_IN, master_xactor_crg_rd_data_full$EN;
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// register master_xactor_crg_wr_addr_full
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reg master_xactor_crg_wr_addr_full;
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wire master_xactor_crg_wr_addr_full$D_IN, master_xactor_crg_wr_addr_full$EN;
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// register master_xactor_crg_wr_data_full
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reg master_xactor_crg_wr_data_full;
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wire master_xactor_crg_wr_data_full$D_IN, master_xactor_crg_wr_data_full$EN;
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// register master_xactor_crg_wr_resp_full
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reg master_xactor_crg_wr_resp_full;
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wire master_xactor_crg_wr_resp_full$D_IN, master_xactor_crg_wr_resp_full$EN;
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// register master_xactor_rg_rd_addr
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reg [96 : 0] master_xactor_rg_rd_addr;
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wire [96 : 0] master_xactor_rg_rd_addr$D_IN;
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wire master_xactor_rg_rd_addr$EN;
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// register master_xactor_rg_rd_data
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reg [70 : 0] master_xactor_rg_rd_data;
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wire [70 : 0] master_xactor_rg_rd_data$D_IN;
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wire master_xactor_rg_rd_data$EN;
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// register master_xactor_rg_wr_addr
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reg [96 : 0] master_xactor_rg_wr_addr;
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wire [96 : 0] master_xactor_rg_wr_addr$D_IN;
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wire master_xactor_rg_wr_addr$EN;
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// register master_xactor_rg_wr_data
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reg [76 : 0] master_xactor_rg_wr_data;
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wire [76 : 0] master_xactor_rg_wr_data$D_IN;
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wire master_xactor_rg_wr_data$EN;
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// register master_xactor_rg_wr_resp
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reg [5 : 0] master_xactor_rg_wr_resp;
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wire [5 : 0] master_xactor_rg_wr_resp$D_IN;
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wire master_xactor_rg_wr_resp$EN;
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// register rg_sb_state
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reg [1 : 0] rg_sb_state;
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wire [1 : 0] rg_sb_state$D_IN;
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wire rg_sb_state$EN;
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// register rg_sbaddress0
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reg [31 : 0] rg_sbaddress0;
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reg [31 : 0] rg_sbaddress0$D_IN;
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wire rg_sbaddress0$EN;
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// register rg_sbaddress1
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reg [31 : 0] rg_sbaddress1;
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reg [31 : 0] rg_sbaddress1$D_IN;
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wire rg_sbaddress1$EN;
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// register rg_sbaddress_reading
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reg [63 : 0] rg_sbaddress_reading;
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wire [63 : 0] rg_sbaddress_reading$D_IN;
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wire rg_sbaddress_reading$EN;
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// register rg_sbcs_sbaccess
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reg [2 : 0] rg_sbcs_sbaccess;
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wire [2 : 0] rg_sbcs_sbaccess$D_IN;
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wire rg_sbcs_sbaccess$EN;
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// register rg_sbcs_sbautoincrement
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reg rg_sbcs_sbautoincrement;
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wire rg_sbcs_sbautoincrement$D_IN, rg_sbcs_sbautoincrement$EN;
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// register rg_sbcs_sbbusyerror
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reg rg_sbcs_sbbusyerror;
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reg rg_sbcs_sbbusyerror$D_IN;
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wire rg_sbcs_sbbusyerror$EN;
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// register rg_sbcs_sberror
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reg [2 : 0] rg_sbcs_sberror;
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reg [2 : 0] rg_sbcs_sberror$D_IN;
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wire rg_sbcs_sberror$EN;
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// register rg_sbcs_sbreadonaddr
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reg rg_sbcs_sbreadonaddr;
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wire rg_sbcs_sbreadonaddr$D_IN, rg_sbcs_sbreadonaddr$EN;
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// register rg_sbcs_sbreadondata
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reg rg_sbcs_sbreadondata;
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wire rg_sbcs_sbreadondata$D_IN, rg_sbcs_sbreadondata$EN;
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// register rg_sbdata0
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reg [31 : 0] rg_sbdata0;
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reg [31 : 0] rg_sbdata0$D_IN;
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wire rg_sbdata0$EN;
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// rule scheduling signals
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wire CAN_FIRE_RL_rl_sb_read_finish,
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CAN_FIRE_RL_rl_sb_write_response,
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CAN_FIRE_av_read,
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CAN_FIRE_master_m_arready,
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CAN_FIRE_master_m_awready,
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CAN_FIRE_master_m_bvalid,
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CAN_FIRE_master_m_rvalid,
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CAN_FIRE_master_m_wready,
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CAN_FIRE_reset,
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CAN_FIRE_write,
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WILL_FIRE_RL_rl_sb_read_finish,
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WILL_FIRE_RL_rl_sb_write_response,
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WILL_FIRE_av_read,
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WILL_FIRE_master_m_arready,
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WILL_FIRE_master_m_awready,
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WILL_FIRE_master_m_bvalid,
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WILL_FIRE_master_m_rvalid,
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WILL_FIRE_master_m_wready,
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WILL_FIRE_reset,
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WILL_FIRE_write;
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// inputs to muxes for submodule ports
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reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2,
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MUX_rg_sbaddress1$write_1__VAL_2;
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reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4;
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wire [96 : 0] MUX_master_xactor_rg_rd_addr$write_1__VAL_1,
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MUX_master_xactor_rg_rd_addr$write_1__VAL_2;
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wire MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1,
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MUX_rg_sbaddress0$write_1__SEL_2,
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MUX_rg_sbaddress0$write_1__SEL_3,
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MUX_rg_sbaddress1$write_1__SEL_2,
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MUX_rg_sbcs_sbbusyerror$write_1__SEL_2,
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MUX_rg_sbcs_sbbusyerror$write_1__SEL_3,
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MUX_rg_sbcs_sberror$write_1__SEL_1,
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MUX_rg_sbcs_sberror$write_1__SEL_3,
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MUX_rg_sbcs_sberror$write_1__SEL_4,
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MUX_rg_sbdata0$write_1__SEL_3;
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// remaining internal signals
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reg [63 : 0] CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1,
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IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53,
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IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66,
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IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103,
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IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79,
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wrd_wdata__h5118;
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reg [7 : 0] wrd_wstrb__h5119;
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reg [2 : 0] x__h3284, x__h4989;
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wire [63 : 0] _theResult___fst__h5027,
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addr64__h4331,
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result__h1836,
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result__h1866,
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result__h1893,
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result__h1920,
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result__h1947,
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result__h1974,
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result__h2001,
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result__h2028,
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result__h2073,
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result__h2100,
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result__h2127,
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result__h2154,
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result__h2195,
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result__h2222,
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rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104,
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rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300,
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sbaddress__h1228,
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word64__h4971;
|
|
wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311,
|
|
IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302,
|
|
v__h2728,
|
|
v__h2862;
|
|
wire [7 : 0] strobe64__h5026, strobe64__h5029, strobe64__h5032;
|
|
wire [5 : 0] shift_bits__h4974;
|
|
wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110,
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317,
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95,
|
|
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292,
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257,
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266,
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272,
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274,
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279,
|
|
write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327;
|
|
|
|
// action method reset
|
|
assign RDY_reset = 1'd1 ;
|
|
assign CAN_FIRE_reset = 1'd1 ;
|
|
assign WILL_FIRE_reset = EN_reset ;
|
|
|
|
// actionvalue method av_read
|
|
always@(av_read_dm_addr or
|
|
v__h2728 or rg_sbaddress0 or rg_sbaddress1 or v__h2862)
|
|
begin
|
|
case (av_read_dm_addr)
|
|
7'h38: av_read = v__h2728;
|
|
7'h39: av_read = rg_sbaddress0;
|
|
7'h3A: av_read = rg_sbaddress1;
|
|
7'h3C: av_read = v__h2862;
|
|
default: av_read = 32'd0;
|
|
endcase
|
|
end
|
|
assign RDY_av_read =
|
|
rg_sb_state == 2'd0 &&
|
|
(rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 ||
|
|
!rg_sbcs_sbreadondata ||
|
|
!master_xactor_crg_rd_addr_full$port2__read) ;
|
|
assign CAN_FIRE_av_read = RDY_av_read ;
|
|
assign WILL_FIRE_av_read = EN_av_read ;
|
|
|
|
// action method write
|
|
assign RDY_write = CAN_FIRE_write && !WILL_FIRE_RL_rl_sb_read_finish ;
|
|
assign CAN_FIRE_write =
|
|
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
|
|
rg_sbcs_sberror != 3'd0 ||
|
|
!rg_sbcs_sbreadonaddr ||
|
|
!master_xactor_crg_rd_addr_full$port2__read) &&
|
|
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
|
|
rg_sbcs_sberror != 3'd0 ||
|
|
!master_xactor_crg_wr_addr_full$port2__read &&
|
|
!master_xactor_crg_wr_data_full$port2__read) ;
|
|
assign WILL_FIRE_write = EN_write ;
|
|
|
|
// value method master_m_awvalid
|
|
assign master_awvalid = master_xactor_crg_wr_addr_full ;
|
|
|
|
// value method master_m_awid
|
|
assign master_awid = master_xactor_rg_wr_addr[96:93] ;
|
|
|
|
// value method master_m_awaddr
|
|
assign master_awaddr = master_xactor_rg_wr_addr[92:29] ;
|
|
|
|
// value method master_m_awlen
|
|
assign master_awlen = master_xactor_rg_wr_addr[28:21] ;
|
|
|
|
// value method master_m_awsize
|
|
assign master_awsize = master_xactor_rg_wr_addr[20:18] ;
|
|
|
|
// value method master_m_awburst
|
|
assign master_awburst = master_xactor_rg_wr_addr[17:16] ;
|
|
|
|
// value method master_m_awlock
|
|
assign master_awlock = master_xactor_rg_wr_addr[15] ;
|
|
|
|
// value method master_m_awcache
|
|
assign master_awcache = master_xactor_rg_wr_addr[14:11] ;
|
|
|
|
// value method master_m_awprot
|
|
assign master_awprot = master_xactor_rg_wr_addr[10:8] ;
|
|
|
|
// value method master_m_awqos
|
|
assign master_awqos = master_xactor_rg_wr_addr[7:4] ;
|
|
|
|
// value method master_m_awregion
|
|
assign master_awregion = master_xactor_rg_wr_addr[3:0] ;
|
|
|
|
// action method master_m_awready
|
|
assign CAN_FIRE_master_m_awready = 1'd1 ;
|
|
assign WILL_FIRE_master_m_awready = 1'd1 ;
|
|
|
|
// value method master_m_wvalid
|
|
assign master_wvalid = master_xactor_crg_wr_data_full ;
|
|
|
|
// value method master_m_wid
|
|
assign master_wid = master_xactor_rg_wr_data[76:73] ;
|
|
|
|
// value method master_m_wdata
|
|
assign master_wdata = master_xactor_rg_wr_data[72:9] ;
|
|
|
|
// value method master_m_wstrb
|
|
assign master_wstrb = master_xactor_rg_wr_data[8:1] ;
|
|
|
|
// value method master_m_wlast
|
|
assign master_wlast = master_xactor_rg_wr_data[0] ;
|
|
|
|
// action method master_m_wready
|
|
assign CAN_FIRE_master_m_wready = 1'd1 ;
|
|
assign WILL_FIRE_master_m_wready = 1'd1 ;
|
|
|
|
// action method master_m_bvalid
|
|
assign CAN_FIRE_master_m_bvalid = 1'd1 ;
|
|
assign WILL_FIRE_master_m_bvalid = 1'd1 ;
|
|
|
|
// value method master_m_bready
|
|
assign master_bready = 1'b1 ;
|
|
|
|
// value method master_m_arvalid
|
|
assign master_arvalid = master_xactor_crg_rd_addr_full ;
|
|
|
|
// value method master_m_arid
|
|
assign master_arid = master_xactor_rg_rd_addr[96:93] ;
|
|
|
|
// value method master_m_araddr
|
|
assign master_araddr = master_xactor_rg_rd_addr[92:29] ;
|
|
|
|
// value method master_m_arlen
|
|
assign master_arlen = master_xactor_rg_rd_addr[28:21] ;
|
|
|
|
// value method master_m_arsize
|
|
assign master_arsize = master_xactor_rg_rd_addr[20:18] ;
|
|
|
|
// value method master_m_arburst
|
|
assign master_arburst = master_xactor_rg_rd_addr[17:16] ;
|
|
|
|
// value method master_m_arlock
|
|
assign master_arlock = master_xactor_rg_rd_addr[15] ;
|
|
|
|
// value method master_m_arcache
|
|
assign master_arcache = master_xactor_rg_rd_addr[14:11] ;
|
|
|
|
// value method master_m_arprot
|
|
assign master_arprot = master_xactor_rg_rd_addr[10:8] ;
|
|
|
|
// value method master_m_arqos
|
|
assign master_arqos = master_xactor_rg_rd_addr[7:4] ;
|
|
|
|
// value method master_m_arregion
|
|
assign master_arregion = master_xactor_rg_rd_addr[3:0] ;
|
|
|
|
// action method master_m_arready
|
|
assign CAN_FIRE_master_m_arready = 1'd1 ;
|
|
assign WILL_FIRE_master_m_arready = 1'd1 ;
|
|
|
|
// action method master_m_rvalid
|
|
assign CAN_FIRE_master_m_rvalid = 1'd1 ;
|
|
assign WILL_FIRE_master_m_rvalid = 1'd1 ;
|
|
|
|
// value method master_m_rready
|
|
assign master_rready = !master_xactor_crg_rd_data_full$port2__read ;
|
|
|
|
// rule RL_rl_sb_read_finish
|
|
assign CAN_FIRE_RL_rl_sb_read_finish =
|
|
master_xactor_crg_rd_data_full && rg_sb_state == 2'd1 &&
|
|
rg_sbcs_sberror == 3'd0 ;
|
|
assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ;
|
|
|
|
// rule RL_rl_sb_write_response
|
|
assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ;
|
|
assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_crg_wr_resp_full ;
|
|
|
|
// inputs to muxes for submodule ports
|
|
assign MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ;
|
|
assign MUX_rg_sbaddress0$write_1__SEL_2 =
|
|
EN_write && write_dm_addr != 7'h38 &&
|
|
(rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror == 3'd0 &&
|
|
write_dm_addr == 7'h39 ||
|
|
write_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
|
|
assign MUX_rg_sbaddress0$write_1__SEL_3 =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ;
|
|
assign MUX_rg_sbaddress1$write_1__SEL_2 =
|
|
EN_write && write_dm_addr != 7'h38 &&
|
|
((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
|
|
rg_sb_state == 2'd0 &&
|
|
!rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 ||
|
|
write_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
|
|
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 ;
|
|
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 =
|
|
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ;
|
|
assign MUX_rg_sbcs_sberror$write_1__SEL_1 =
|
|
master_xactor_crg_wr_resp_full &&
|
|
master_xactor_rg_wr_resp[1:0] != 2'b0 ;
|
|
assign MUX_rg_sbcs_sberror$write_1__SEL_3 =
|
|
WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0 ;
|
|
assign MUX_rg_sbcs_sberror$write_1__SEL_4 =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 ;
|
|
assign MUX_rg_sbdata0$write_1__SEL_3 =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 ;
|
|
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_1 =
|
|
{ 4'd0, sbaddress__h1228, 8'd0, x__h3284, 18'd65536 } ;
|
|
assign MUX_master_xactor_rg_rd_addr$write_1__VAL_2 =
|
|
{ 4'd0, addr64__h4331, 8'd0, x__h3284, 18'd65536 } ;
|
|
always@(write_dm_addr or
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
|
|
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311)
|
|
begin
|
|
case (write_dm_addr)
|
|
7'h39, 7'h3A:
|
|
MUX_rg_sbaddress0$write_1__VAL_2 =
|
|
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311;
|
|
default: MUX_rg_sbaddress0$write_1__VAL_2 =
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
|
|
endcase
|
|
end
|
|
always@(write_dm_addr or
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
|
|
IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302)
|
|
begin
|
|
case (write_dm_addr)
|
|
7'h39, 7'h3A:
|
|
MUX_rg_sbaddress1$write_1__VAL_2 =
|
|
IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302;
|
|
default: MUX_rg_sbaddress1$write_1__VAL_2 =
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
|
|
endcase
|
|
end
|
|
always@(write_dm_word)
|
|
begin
|
|
case (write_dm_word[19:17])
|
|
3'd3, 3'd4: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd3;
|
|
default: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd0;
|
|
endcase
|
|
end
|
|
|
|
// inlined wires
|
|
assign master_xactor_crg_wr_addr_full$EN_port1__write =
|
|
master_xactor_crg_wr_addr_full && master_awready ;
|
|
assign master_xactor_crg_wr_addr_full$port2__read =
|
|
!master_xactor_crg_wr_addr_full$EN_port1__write &&
|
|
master_xactor_crg_wr_addr_full ;
|
|
assign master_xactor_crg_wr_addr_full$port3__read =
|
|
MUX_rg_sbdata0$write_1__SEL_3 ||
|
|
master_xactor_crg_wr_addr_full$port2__read ;
|
|
assign master_xactor_crg_wr_data_full$EN_port1__write =
|
|
master_xactor_crg_wr_data_full && master_wready ;
|
|
assign master_xactor_crg_wr_data_full$port2__read =
|
|
!master_xactor_crg_wr_data_full$EN_port1__write &&
|
|
master_xactor_crg_wr_data_full ;
|
|
assign master_xactor_crg_wr_data_full$port3__read =
|
|
MUX_rg_sbdata0$write_1__SEL_3 ||
|
|
master_xactor_crg_wr_data_full$port2__read ;
|
|
assign master_xactor_crg_rd_addr_full$EN_port1__write =
|
|
master_xactor_crg_rd_addr_full && master_arready ;
|
|
assign master_xactor_crg_rd_addr_full$port2__read =
|
|
!master_xactor_crg_rd_addr_full$EN_port1__write &&
|
|
master_xactor_crg_rd_addr_full ;
|
|
assign master_xactor_crg_rd_addr_full$EN_port2__write =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
|
|
EN_write && write_dm_addr == 7'h39 &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ;
|
|
assign master_xactor_crg_rd_addr_full$port3__read =
|
|
master_xactor_crg_rd_addr_full$EN_port2__write ?
|
|
1'd1 :
|
|
master_xactor_crg_rd_addr_full$port2__read ;
|
|
assign master_xactor_crg_rd_data_full$port2__read =
|
|
!CAN_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_crg_rd_data_full ;
|
|
assign master_xactor_crg_rd_data_full$EN_port2__write =
|
|
master_rvalid && !master_xactor_crg_rd_data_full$port2__read ;
|
|
assign master_xactor_crg_rd_data_full$port3__read =
|
|
master_xactor_crg_rd_data_full$EN_port2__write ||
|
|
master_xactor_crg_rd_data_full$port2__read ;
|
|
|
|
// register master_xactor_crg_rd_addr_full
|
|
assign master_xactor_crg_rd_addr_full$D_IN =
|
|
master_xactor_crg_rd_addr_full$port3__read ;
|
|
assign master_xactor_crg_rd_addr_full$EN = 1'b1 ;
|
|
|
|
// register master_xactor_crg_rd_data_full
|
|
assign master_xactor_crg_rd_data_full$D_IN =
|
|
master_xactor_crg_rd_data_full$port3__read ;
|
|
assign master_xactor_crg_rd_data_full$EN = 1'b1 ;
|
|
|
|
// register master_xactor_crg_wr_addr_full
|
|
assign master_xactor_crg_wr_addr_full$D_IN =
|
|
master_xactor_crg_wr_addr_full$port3__read ;
|
|
assign master_xactor_crg_wr_addr_full$EN = 1'b1 ;
|
|
|
|
// register master_xactor_crg_wr_data_full
|
|
assign master_xactor_crg_wr_data_full$D_IN =
|
|
master_xactor_crg_wr_data_full$port3__read ;
|
|
assign master_xactor_crg_wr_data_full$EN = 1'b1 ;
|
|
|
|
// register master_xactor_crg_wr_resp_full
|
|
assign master_xactor_crg_wr_resp_full$D_IN = master_bvalid ;
|
|
assign master_xactor_crg_wr_resp_full$EN = 1'b1 ;
|
|
|
|
// register master_xactor_rg_rd_addr
|
|
assign master_xactor_rg_rd_addr$D_IN =
|
|
MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ?
|
|
MUX_master_xactor_rg_rd_addr$write_1__VAL_1 :
|
|
MUX_master_xactor_rg_rd_addr$write_1__VAL_2 ;
|
|
assign master_xactor_rg_rd_addr$EN =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
|
|
EN_write && write_dm_addr == 7'h39 &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ;
|
|
|
|
// register master_xactor_rg_rd_data
|
|
assign master_xactor_rg_rd_data$D_IN =
|
|
{ master_rid, master_rdata, master_rresp, master_rlast } ;
|
|
assign master_xactor_rg_rd_data$EN = 1'd1 ;
|
|
|
|
// register master_xactor_rg_wr_addr
|
|
assign master_xactor_rg_wr_addr$D_IN =
|
|
{ 4'd0, sbaddress__h1228, 8'd0, x__h4989, 18'd65536 } ;
|
|
assign master_xactor_rg_wr_addr$EN = MUX_rg_sbdata0$write_1__SEL_3 ;
|
|
|
|
// register master_xactor_rg_wr_data
|
|
assign master_xactor_rg_wr_data$D_IN =
|
|
{ 4'd0, wrd_wdata__h5118, wrd_wstrb__h5119, 1'd1 } ;
|
|
assign master_xactor_rg_wr_data$EN = MUX_rg_sbdata0$write_1__SEL_3 ;
|
|
|
|
// register master_xactor_rg_wr_resp
|
|
assign master_xactor_rg_wr_resp$D_IN = { master_bid, master_bresp } ;
|
|
assign master_xactor_rg_wr_resp$EN = master_bvalid ;
|
|
|
|
// register rg_sb_state
|
|
assign rg_sb_state$D_IN =
|
|
(EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ;
|
|
assign rg_sb_state$EN =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
|
|
EN_write && write_dm_addr == 7'h39 &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ||
|
|
WILL_FIRE_RL_rl_sb_read_finish ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbaddress0
|
|
always@(EN_reset or
|
|
MUX_rg_sbaddress0$write_1__SEL_2 or
|
|
MUX_rg_sbaddress0$write_1__VAL_2 or
|
|
MUX_rg_sbaddress0$write_1__SEL_3 or
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
|
|
case (1'b1)
|
|
EN_reset: rg_sbaddress0$D_IN = 32'd0;
|
|
MUX_rg_sbaddress0$write_1__SEL_2:
|
|
rg_sbaddress0$D_IN = MUX_rg_sbaddress0$write_1__VAL_2;
|
|
MUX_rg_sbaddress0$write_1__SEL_3:
|
|
rg_sbaddress0$D_IN =
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
|
|
default: rg_sbaddress0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
assign rg_sbaddress0$EN =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
|
|
MUX_rg_sbaddress0$write_1__SEL_2 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbaddress1
|
|
always@(EN_reset or
|
|
MUX_rg_sbaddress1$write_1__SEL_2 or
|
|
MUX_rg_sbaddress1$write_1__VAL_2 or
|
|
MUX_rg_sbaddress0$write_1__SEL_3 or
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
|
|
case (1'b1)
|
|
EN_reset: rg_sbaddress1$D_IN = 32'd0;
|
|
MUX_rg_sbaddress1$write_1__SEL_2:
|
|
rg_sbaddress1$D_IN = MUX_rg_sbaddress1$write_1__VAL_2;
|
|
MUX_rg_sbaddress0$write_1__SEL_3:
|
|
rg_sbaddress1$D_IN =
|
|
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
|
|
default: rg_sbaddress1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
assign rg_sbaddress1$EN =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
|
|
MUX_rg_sbaddress1$write_1__SEL_2 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbaddress_reading
|
|
assign rg_sbaddress_reading$D_IN =
|
|
MUX_master_xactor_crg_rd_addr_full$port2__write_1__SEL_1 ?
|
|
sbaddress__h1228 :
|
|
addr64__h4331 ;
|
|
assign rg_sbaddress_reading$EN =
|
|
EN_av_read && av_read_dm_addr == 7'h3C &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
|
|
EN_write && write_dm_addr == 7'h39 &&
|
|
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 ;
|
|
|
|
// register rg_sbcs_sbaccess
|
|
assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ;
|
|
assign rg_sbcs_sbaccess$EN =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbcs_sbautoincrement
|
|
assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ;
|
|
assign rg_sbcs_sbautoincrement$EN =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbcs_sbbusyerror
|
|
always@(EN_reset or
|
|
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 or
|
|
write_dm_addr or MUX_rg_sbcs_sbbusyerror$write_1__SEL_3)
|
|
case (1'b1)
|
|
EN_reset: rg_sbcs_sbbusyerror$D_IN = 1'd0;
|
|
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2:
|
|
rg_sbcs_sbbusyerror$D_IN = write_dm_addr != 7'h38;
|
|
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3: rg_sbcs_sbbusyerror$D_IN = 1'd1;
|
|
default: rg_sbcs_sbbusyerror$D_IN = 1'b0 /* unspecified value */ ;
|
|
endcase
|
|
assign rg_sbcs_sbbusyerror$EN =
|
|
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ||
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbcs_sberror
|
|
always@(MUX_rg_sbcs_sberror$write_1__SEL_1 or
|
|
EN_reset or
|
|
MUX_rg_sbcs_sberror$write_1__SEL_3 or
|
|
MUX_rg_sbcs_sberror$write_1__SEL_4 or
|
|
MUX_rg_sbcs_sberror$write_1__VAL_4)
|
|
case (1'b1)
|
|
MUX_rg_sbcs_sberror$write_1__SEL_1: rg_sbcs_sberror$D_IN = 3'd3;
|
|
EN_reset: rg_sbcs_sberror$D_IN = 3'd0;
|
|
MUX_rg_sbcs_sberror$write_1__SEL_3: rg_sbcs_sberror$D_IN = 3'd3;
|
|
MUX_rg_sbcs_sberror$write_1__SEL_4:
|
|
rg_sbcs_sberror$D_IN = MUX_rg_sbcs_sberror$write_1__VAL_4;
|
|
default: rg_sbcs_sberror$D_IN = 3'b010 /* unspecified value */ ;
|
|
endcase
|
|
assign rg_sbcs_sberror$EN =
|
|
WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0 ||
|
|
master_xactor_crg_wr_resp_full &&
|
|
master_xactor_rg_wr_resp[1:0] != 2'b0 ||
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbcs_sbreadonaddr
|
|
assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ;
|
|
assign rg_sbcs_sbreadonaddr$EN =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbcs_sbreadondata
|
|
assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ;
|
|
assign rg_sbcs_sbreadondata$EN =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 ||
|
|
EN_reset ;
|
|
|
|
// register rg_sbdata0
|
|
always@(EN_reset or
|
|
WILL_FIRE_RL_rl_sb_read_finish or
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 or
|
|
MUX_rg_sbdata0$write_1__SEL_3 or write_dm_word)
|
|
case (1'b1)
|
|
EN_reset: rg_sbdata0$D_IN = 32'd0;
|
|
WILL_FIRE_RL_rl_sb_read_finish:
|
|
rg_sbdata0$D_IN =
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79[31:0];
|
|
MUX_rg_sbdata0$write_1__SEL_3: rg_sbdata0$D_IN = write_dm_word;
|
|
default: rg_sbdata0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
|
|
endcase
|
|
assign rg_sbdata0$EN =
|
|
EN_write &&
|
|
write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 ||
|
|
WILL_FIRE_RL_rl_sb_read_finish ||
|
|
EN_reset ;
|
|
|
|
// remaining internal signals
|
|
assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d311 =
|
|
rg_sbcs_sbreadonaddr ?
|
|
(rg_sbcs_sbautoincrement ?
|
|
rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[31:0] :
|
|
write_dm_word) :
|
|
write_dm_word ;
|
|
assign IF_write_dm_addr_EQ_0x39_59_THEN_rg_sbaddress1_ETC___d302 =
|
|
(write_dm_addr == 7'h39) ?
|
|
rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300[63:32] :
|
|
write_dm_word ;
|
|
assign _theResult___fst__h5027 = word64__h4971 << shift_bits__h4974 ;
|
|
assign addr64__h4331 = { rg_sbaddress1, write_dm_word } ;
|
|
assign result__h1836 = { 56'd0, master_xactor_rg_rd_data[10:3] } ;
|
|
assign result__h1866 = { 56'd0, master_xactor_rg_rd_data[18:11] } ;
|
|
assign result__h1893 = { 56'd0, master_xactor_rg_rd_data[26:19] } ;
|
|
assign result__h1920 = { 56'd0, master_xactor_rg_rd_data[34:27] } ;
|
|
assign result__h1947 = { 56'd0, master_xactor_rg_rd_data[42:35] } ;
|
|
assign result__h1974 = { 56'd0, master_xactor_rg_rd_data[50:43] } ;
|
|
assign result__h2001 = { 56'd0, master_xactor_rg_rd_data[58:51] } ;
|
|
assign result__h2028 = { 56'd0, master_xactor_rg_rd_data[66:59] } ;
|
|
assign result__h2073 = { 48'd0, master_xactor_rg_rd_data[18:3] } ;
|
|
assign result__h2100 = { 48'd0, master_xactor_rg_rd_data[34:19] } ;
|
|
assign result__h2127 = { 48'd0, master_xactor_rg_rd_data[50:35] } ;
|
|
assign result__h2154 = { 48'd0, master_xactor_rg_rd_data[66:51] } ;
|
|
assign result__h2195 = { 32'd0, master_xactor_rg_rd_data[34:3] } ;
|
|
assign result__h2222 = { 32'd0, master_xactor_rg_rd_data[66:35] } ;
|
|
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 =
|
|
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror == 3'd0 &&
|
|
rg_sbcs_sbreadondata ;
|
|
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d317 =
|
|
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror == 3'd0 &&
|
|
rg_sbcs_sbreadonaddr ;
|
|
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 =
|
|
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror == 3'd0 &&
|
|
rg_sbcs_sbautoincrement ;
|
|
assign rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 =
|
|
sbaddress__h1228 +
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
|
|
assign rg_sbaddress1_7_CONCAT_write_dm_word_99_PLUS_I_ETC___d300 =
|
|
addr64__h4331 +
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
|
|
assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d292 =
|
|
rg_sbcs_sberror == 3'd0 &&
|
|
(rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement ||
|
|
write_dm_addr != 7'h39) ;
|
|
assign sbaddress__h1228 = { rg_sbaddress1, rg_sbaddress0 } ;
|
|
assign shift_bits__h4974 = { rg_sbaddress0[2:0], 3'b0 } ;
|
|
assign strobe64__h5026 = 8'b00000001 << rg_sbaddress0[2:0] ;
|
|
assign strobe64__h5029 = 8'b00000011 << rg_sbaddress0[2:0] ;
|
|
assign strobe64__h5032 = 8'b00001111 << rg_sbaddress0[2:0] ;
|
|
assign v__h2728 =
|
|
{ 9'd64,
|
|
rg_sbcs_sbbusyerror,
|
|
rg_sb_state != 2'd0,
|
|
rg_sbcs_sbreadonaddr,
|
|
rg_sbcs_sbaccess,
|
|
rg_sbcs_sbautoincrement,
|
|
rg_sbcs_sbreadondata,
|
|
rg_sbcs_sberror,
|
|
12'd2055 } ;
|
|
assign v__h2862 =
|
|
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
|
|
rg_sbcs_sberror != 3'd0) ?
|
|
32'd0 :
|
|
rg_sbdata0 ;
|
|
assign word64__h4971 = { 32'd0, write_dm_word } ;
|
|
assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 =
|
|
write_dm_addr == 7'h38 &&
|
|
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
|
|
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
|
|
write_dm_word[19:17] != 3'd4 &&
|
|
write_dm_word[19:17] != 3'd3 ;
|
|
assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d266 =
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d257 ||
|
|
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A ||
|
|
write_dm_addr == 7'h3C) &&
|
|
rg_sb_state != 2'd0 ;
|
|
assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272 =
|
|
write_dm_addr == 7'h38 &&
|
|
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
|
|
rg_sbcs_sbbusyerror &&
|
|
!write_dm_word[22] ;
|
|
assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d274 =
|
|
write_dm_addr == 7'h38 &&
|
|
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
|
|
(!rg_sbcs_sbbusyerror || write_dm_word[22]) ;
|
|
assign write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279 =
|
|
write_dm_addr == 7'h38 &&
|
|
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
|
|
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
|
|
(write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ;
|
|
assign write_dm_addr_EQ_0x3C_62_AND_rg_sb_state_EQ_0__ETC___d327 =
|
|
write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
|
|
!rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror == 3'd0 ;
|
|
always@(rg_sbcs_sbaccess)
|
|
begin
|
|
case (rg_sbcs_sbaccess)
|
|
3'd0, 3'd1, 3'd2: x__h3284 = rg_sbcs_sbaccess;
|
|
default: x__h3284 = 3'b011;
|
|
endcase
|
|
end
|
|
always@(rg_sbcs_sbaccess)
|
|
begin
|
|
case (rg_sbcs_sbaccess)
|
|
3'd0, 3'd1, 3'd2, 3'd3: x__h4989 = rg_sbcs_sbaccess;
|
|
default: x__h4989 = 3'b111;
|
|
endcase
|
|
end
|
|
always@(rg_sbcs_sbaccess or
|
|
strobe64__h5026 or strobe64__h5029 or strobe64__h5032)
|
|
begin
|
|
case (rg_sbcs_sbaccess)
|
|
3'd0: wrd_wstrb__h5119 = strobe64__h5026;
|
|
3'd1: wrd_wstrb__h5119 = strobe64__h5029;
|
|
3'd2: wrd_wstrb__h5119 = strobe64__h5032;
|
|
3'd3: wrd_wstrb__h5119 = 8'b11111111;
|
|
default: wrd_wstrb__h5119 = 8'd0;
|
|
endcase
|
|
end
|
|
always@(rg_sbcs_sbaccess or word64__h4971 or _theResult___fst__h5027)
|
|
begin
|
|
case (rg_sbcs_sbaccess)
|
|
3'd0, 3'd1, 3'd2: wrd_wdata__h5118 = _theResult___fst__h5027;
|
|
default: wrd_wdata__h5118 = word64__h4971;
|
|
endcase
|
|
end
|
|
always@(rg_sbcs_sbaccess)
|
|
begin
|
|
case (rg_sbcs_sbaccess)
|
|
3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd1;
|
|
3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd2;
|
|
3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd4;
|
|
3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd8;
|
|
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 =
|
|
64'd16;
|
|
endcase
|
|
end
|
|
always@(rg_sbaddress_reading or
|
|
result__h1836 or
|
|
result__h1866 or
|
|
result__h1893 or
|
|
result__h1920 or
|
|
result__h1947 or result__h1974 or result__h2001 or result__h2028)
|
|
begin
|
|
case (rg_sbaddress_reading[2:0])
|
|
3'h0:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h1836;
|
|
3'h1:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h1866;
|
|
3'h2:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h1893;
|
|
3'h3:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h1920;
|
|
3'h4:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h1947;
|
|
3'h5:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h1974;
|
|
3'h6:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h2001;
|
|
3'h7:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
|
|
result__h2028;
|
|
endcase
|
|
end
|
|
always@(rg_sbaddress_reading or
|
|
result__h2073 or result__h2100 or result__h2127 or result__h2154)
|
|
begin
|
|
case (rg_sbaddress_reading[2:0])
|
|
3'h0:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
|
|
result__h2073;
|
|
3'h2:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
|
|
result__h2100;
|
|
3'h4:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
|
|
result__h2127;
|
|
3'h6:
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
|
|
result__h2154;
|
|
default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
|
|
64'd0;
|
|
endcase
|
|
end
|
|
always@(rg_sbaddress_reading or result__h2195 or result__h2222)
|
|
begin
|
|
case (rg_sbaddress_reading[2:0])
|
|
3'h0:
|
|
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
|
|
result__h2195;
|
|
3'h4:
|
|
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
|
|
result__h2222;
|
|
default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0;
|
|
endcase
|
|
end
|
|
always@(rg_sbcs_sbaccess or
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or
|
|
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or
|
|
rg_sbaddress_reading or master_xactor_rg_rd_data)
|
|
begin
|
|
case (rg_sbcs_sbaccess)
|
|
3'd0:
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53;
|
|
3'd1:
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
|
|
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66;
|
|
3'd2:
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
|
|
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1;
|
|
3'd3:
|
|
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
|
|
(rg_sbaddress_reading[2:0] == 3'h0) ?
|
|
master_xactor_rg_rd_data[66:3] :
|
|
64'd0;
|
|
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
|
|
64'd0;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (master_xactor_crg_rd_addr_full$EN)
|
|
master_xactor_crg_rd_addr_full <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_crg_rd_addr_full$D_IN;
|
|
if (master_xactor_crg_rd_data_full$EN)
|
|
master_xactor_crg_rd_data_full <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_crg_rd_data_full$D_IN;
|
|
if (master_xactor_crg_wr_addr_full$EN)
|
|
master_xactor_crg_wr_addr_full <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_crg_wr_addr_full$D_IN;
|
|
if (master_xactor_crg_wr_data_full$EN)
|
|
master_xactor_crg_wr_data_full <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_crg_wr_data_full$D_IN;
|
|
if (master_xactor_crg_wr_resp_full$EN)
|
|
master_xactor_crg_wr_resp_full <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_crg_wr_resp_full$D_IN;
|
|
if (rg_sbaddress0$EN)
|
|
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN;
|
|
if (rg_sbaddress1$EN)
|
|
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN;
|
|
end
|
|
if (master_xactor_rg_rd_addr$EN)
|
|
master_xactor_rg_rd_addr <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_rg_rd_addr$D_IN;
|
|
if (master_xactor_rg_rd_data$EN)
|
|
master_xactor_rg_rd_data <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_rg_rd_data$D_IN;
|
|
if (master_xactor_rg_wr_addr$EN)
|
|
master_xactor_rg_wr_addr <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_rg_wr_addr$D_IN;
|
|
if (master_xactor_rg_wr_data$EN)
|
|
master_xactor_rg_wr_data <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_rg_wr_data$D_IN;
|
|
if (master_xactor_rg_wr_resp$EN)
|
|
master_xactor_rg_wr_resp <= `BSV_ASSIGNMENT_DELAY
|
|
master_xactor_rg_wr_resp$D_IN;
|
|
if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN;
|
|
if (rg_sbaddress_reading$EN)
|
|
rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN;
|
|
if (rg_sbcs_sbaccess$EN)
|
|
rg_sbcs_sbaccess <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbaccess$D_IN;
|
|
if (rg_sbcs_sbautoincrement$EN)
|
|
rg_sbcs_sbautoincrement <= `BSV_ASSIGNMENT_DELAY
|
|
rg_sbcs_sbautoincrement$D_IN;
|
|
if (rg_sbcs_sbbusyerror$EN)
|
|
rg_sbcs_sbbusyerror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbbusyerror$D_IN;
|
|
if (rg_sbcs_sberror$EN)
|
|
rg_sbcs_sberror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sberror$D_IN;
|
|
if (rg_sbcs_sbreadonaddr$EN)
|
|
rg_sbcs_sbreadonaddr <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadonaddr$D_IN;
|
|
if (rg_sbcs_sbreadondata$EN)
|
|
rg_sbcs_sbreadondata <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadondata$D_IN;
|
|
if (rg_sbdata0$EN) rg_sbdata0 <= `BSV_ASSIGNMENT_DELAY rg_sbdata0$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
master_xactor_crg_rd_addr_full = 1'h0;
|
|
master_xactor_crg_rd_data_full = 1'h0;
|
|
master_xactor_crg_wr_addr_full = 1'h0;
|
|
master_xactor_crg_wr_data_full = 1'h0;
|
|
master_xactor_crg_wr_resp_full = 1'h0;
|
|
master_xactor_rg_rd_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
|
|
master_xactor_rg_rd_data = 71'h2AAAAAAAAAAAAAAAAA;
|
|
master_xactor_rg_wr_addr = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
|
|
master_xactor_rg_wr_data = 77'h0AAAAAAAAAAAAAAAAAAA;
|
|
master_xactor_rg_wr_resp = 6'h2A;
|
|
rg_sb_state = 2'h2;
|
|
rg_sbaddress0 = 32'hAAAAAAAA;
|
|
rg_sbaddress1 = 32'hAAAAAAAA;
|
|
rg_sbaddress_reading = 64'hAAAAAAAAAAAAAAAA;
|
|
rg_sbcs_sbaccess = 3'h2;
|
|
rg_sbcs_sbautoincrement = 1'h0;
|
|
rg_sbcs_sbbusyerror = 1'h0;
|
|
rg_sbcs_sberror = 3'h2;
|
|
rg_sbcs_sbreadonaddr = 1'h0;
|
|
rg_sbcs_sbreadondata = 1'h0;
|
|
rg_sbdata0 = 32'hAAAAAAAA;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
|
|
// handling of system tasks
|
|
|
|
// synopsys translate_off
|
|
always@(negedge CLK)
|
|
begin
|
|
#0;
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
|
|
rg_sbcs_sbbusyerror)
|
|
$display("DM_System_Bus.sbdata.read: ignoring due to sbbusyerror");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
|
|
!rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror != 3'd0)
|
|
$display("DM_System_Bus.sbdata.read: ignoring due to sberror = 0x%0h",
|
|
rg_sbcs_sberror);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0)
|
|
$display("DM_System_Bus.sbdata.read: busy, setting sbbusyerror");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr != 7'h38 &&
|
|
av_read_dm_addr != 7'h39 &&
|
|
av_read_dm_addr != 7'h3A &&
|
|
av_read_dm_addr != 7'h3C)
|
|
$write("DM_System_Bus.read: [");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h11) $write("dm_addr_dmstatus");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h12) $write("dm_addr_hartinfo");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h13) $write("dm_addr_haltsum");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h14)
|
|
$write("dm_addr_hawindowsel");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h15) $write("dm_addr_hawindow");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h19)
|
|
$write("dm_addr_devtreeaddr0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h30) $write("dm_addr_authdata");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h40)
|
|
$write("dm_addr_haltregion0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h5F)
|
|
$write("dm_addr_haltregion31");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h60) $write("dm_addr_verbosity");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h16)
|
|
$write("dm_addr_abstractcs");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h17) $write("dm_addr_command");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h04) $write("dm_addr_data0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h05) $write("dm_addr_data1");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h06) $write("dm_addr_data2");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h07) $write("dm_addr_data3");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h08) $write("dm_addr_data4");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h09) $write("dm_addr_data5");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h0A) $write("dm_addr_data6");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h0B) $write("dm_addr_data7");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h0C) $write("dm_addr_data8");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h0D) $write("dm_addr_data9");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h0F) $write("dm_addr_data11");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h18)
|
|
$write("dm_addr_abstractauto");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h20) $write("dm_addr_progbuf0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h3B)
|
|
$write("dm_addr_sbaddress2");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr != 7'h38 &&
|
|
av_read_dm_addr != 7'h39 &&
|
|
av_read_dm_addr != 7'h3A &&
|
|
av_read_dm_addr != 7'h3C &&
|
|
av_read_dm_addr != 7'h10 &&
|
|
av_read_dm_addr != 7'h11 &&
|
|
av_read_dm_addr != 7'h12 &&
|
|
av_read_dm_addr != 7'h13 &&
|
|
av_read_dm_addr != 7'h14 &&
|
|
av_read_dm_addr != 7'h15 &&
|
|
av_read_dm_addr != 7'h19 &&
|
|
av_read_dm_addr != 7'h30 &&
|
|
av_read_dm_addr != 7'h40 &&
|
|
av_read_dm_addr != 7'h5F &&
|
|
av_read_dm_addr != 7'h60 &&
|
|
av_read_dm_addr != 7'h16 &&
|
|
av_read_dm_addr != 7'h17 &&
|
|
av_read_dm_addr != 7'h04 &&
|
|
av_read_dm_addr != 7'h05 &&
|
|
av_read_dm_addr != 7'h06 &&
|
|
av_read_dm_addr != 7'h07 &&
|
|
av_read_dm_addr != 7'h08 &&
|
|
av_read_dm_addr != 7'h09 &&
|
|
av_read_dm_addr != 7'h0A &&
|
|
av_read_dm_addr != 7'h0B &&
|
|
av_read_dm_addr != 7'h0C &&
|
|
av_read_dm_addr != 7'h0D &&
|
|
av_read_dm_addr != 7'h0F &&
|
|
av_read_dm_addr != 7'h18 &&
|
|
av_read_dm_addr != 7'h20 &&
|
|
av_read_dm_addr != 7'h3B &&
|
|
av_read_dm_addr != 7'h3D &&
|
|
av_read_dm_addr != 7'h3E &&
|
|
av_read_dm_addr != 7'h3F)
|
|
$write("<Unknown dm_abstract_command dm_addr 0x%0h>",
|
|
av_read_dm_addr);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_av_read && av_read_dm_addr != 7'h38 &&
|
|
av_read_dm_addr != 7'h39 &&
|
|
av_read_dm_addr != 7'h3A &&
|
|
av_read_dm_addr != 7'h3C)
|
|
$write("] not supported", "\n");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
|
|
write_dm_word[14:12] == 3'd0)
|
|
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
|
|
write_dm_word[14:12] == 3'd0)
|
|
$display(" ERROR: existing sberror (0x%0h) is not being cleared.",
|
|
rg_sbcs_sberror);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
|
|
write_dm_word[14:12] == 3'd0)
|
|
$display(" Must be cleared to re-enable system bus access.");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272)
|
|
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272)
|
|
$display(" ERROR: existing sbbusyerror (%0d) is not being cleared.",
|
|
rg_sbcs_sbbusyerror);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d272)
|
|
$display(" Must be cleared to re-enable system bus access.");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279)
|
|
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279)
|
|
$write(" ERROR: sbaccess ");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h38 &&
|
|
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
|
|
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
|
|
write_dm_word[19:17] == 3'd3)
|
|
$write("DM_SBACCESS_64_BIT");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h38 &&
|
|
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
|
|
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
|
|
write_dm_word[19:17] == 3'd4)
|
|
$write("DM_SBACCESS_128_BIT");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write &&
|
|
write_dm_addr_EQ_0x38_42_AND_rg_sbcs_sberror_E_ETC___d279)
|
|
$write(" not supported", "\n");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr != 7'h38 &&
|
|
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
|
|
rg_sb_state == 2'd0 &&
|
|
rg_sbcs_sbbusyerror)
|
|
$display("DM_System_Bus.sbaddress.write: ignoring due to sbbusyerror");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr != 7'h38 &&
|
|
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
|
|
rg_sb_state == 2'd0 &&
|
|
!rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror != 3'd0)
|
|
$display("DM_System_Bus.sbaddress.write: ignoring due to sberror = 0x%0h",
|
|
rg_sbcs_sberror);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr != 7'h38 &&
|
|
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
|
|
rg_sb_state != 2'd0)
|
|
$display("DM_System_Bus.sbaddress.write: busy, setting sbbusyerror");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
|
|
rg_sbcs_sbbusyerror)
|
|
$display("DM_System_Bus.sbdata.write: ignoring due to sbbusyerror");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
|
|
!rg_sbcs_sbbusyerror &&
|
|
rg_sbcs_sberror != 3'd0)
|
|
$display("DM_System_Bus.sbdata.write: ignoring due to sberror = 0x%0h",
|
|
rg_sbcs_sberror);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state != 2'd0)
|
|
$display("DM_System_Bus.sbdata.write: busy, setting sbbusyerror");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
|
|
write_dm_addr != 7'h3A &&
|
|
write_dm_addr != 7'h3C)
|
|
$write("DM_System_Bus.write: [");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h11) $write("dm_addr_dmstatus");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h12) $write("dm_addr_hartinfo");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h13) $write("dm_addr_haltsum");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h14) $write("dm_addr_hawindowsel");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h15) $write("dm_addr_hawindow");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h19) $write("dm_addr_devtreeaddr0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h30) $write("dm_addr_authdata");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h40) $write("dm_addr_haltregion0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h5F) $write("dm_addr_haltregion31");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h60) $write("dm_addr_verbosity");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h16) $write("dm_addr_abstractcs");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h17) $write("dm_addr_command");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h04) $write("dm_addr_data0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h05) $write("dm_addr_data1");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h06) $write("dm_addr_data2");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h07) $write("dm_addr_data3");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h08) $write("dm_addr_data4");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h09) $write("dm_addr_data5");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h0A) $write("dm_addr_data6");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h0B) $write("dm_addr_data7");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h0C) $write("dm_addr_data8");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h0D) $write("dm_addr_data9");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h0F) $write("dm_addr_data11");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h18) $write("dm_addr_abstractauto");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h20) $write("dm_addr_progbuf0");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h3B) $write("dm_addr_sbaddress2");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
|
|
write_dm_addr != 7'h3A &&
|
|
write_dm_addr != 7'h3C &&
|
|
write_dm_addr != 7'h10 &&
|
|
write_dm_addr != 7'h11 &&
|
|
write_dm_addr != 7'h12 &&
|
|
write_dm_addr != 7'h13 &&
|
|
write_dm_addr != 7'h14 &&
|
|
write_dm_addr != 7'h15 &&
|
|
write_dm_addr != 7'h19 &&
|
|
write_dm_addr != 7'h30 &&
|
|
write_dm_addr != 7'h40 &&
|
|
write_dm_addr != 7'h5F &&
|
|
write_dm_addr != 7'h60 &&
|
|
write_dm_addr != 7'h16 &&
|
|
write_dm_addr != 7'h17 &&
|
|
write_dm_addr != 7'h04 &&
|
|
write_dm_addr != 7'h05 &&
|
|
write_dm_addr != 7'h06 &&
|
|
write_dm_addr != 7'h07 &&
|
|
write_dm_addr != 7'h08 &&
|
|
write_dm_addr != 7'h09 &&
|
|
write_dm_addr != 7'h0A &&
|
|
write_dm_addr != 7'h0B &&
|
|
write_dm_addr != 7'h0C &&
|
|
write_dm_addr != 7'h0D &&
|
|
write_dm_addr != 7'h0F &&
|
|
write_dm_addr != 7'h18 &&
|
|
write_dm_addr != 7'h20 &&
|
|
write_dm_addr != 7'h3B &&
|
|
write_dm_addr != 7'h3D &&
|
|
write_dm_addr != 7'h3E &&
|
|
write_dm_addr != 7'h3F)
|
|
$write("<Unknown dm_abstract_command dm_addr 0x%0h>", write_dm_addr);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
|
|
write_dm_addr != 7'h3A &&
|
|
write_dm_addr != 7'h3C)
|
|
$write("] <= 0x%08h; addr not supported", write_dm_word, "\n");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write(" rdr = ");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write("AXI4_Rd_Data { ", "rid: ");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write("'h%h", master_xactor_rg_rd_data[70:67]);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write(", ", "rdata: ");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write("'h%h", master_xactor_rg_rd_data[66:3]);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write(", ", "rresp: ");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write("'h%h", master_xactor_rg_rd_data[2:1]);
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write(", ", "rlast: ");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0 &&
|
|
master_xactor_rg_rd_data[0])
|
|
$write("True");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0 &&
|
|
!master_xactor_rg_rd_data[0])
|
|
$write("False");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write(", ", "ruser: ");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write("'h%h", 1'd0, " }");
|
|
if (RST_N != `BSV_RESET_VALUE)
|
|
if (WILL_FIRE_RL_rl_sb_read_finish &&
|
|
master_xactor_rg_rd_data[2:1] != 2'b0)
|
|
$write("\n");
|
|
end
|
|
// synopsys translate_on
|
|
endmodule // mkDM_System_Bus
|
|
|