340 lines
12 KiB
Plaintext
340 lines
12 KiB
Plaintext
// Copyright (c) 2013-2019 Bluespec, Inc. All Rights Reserved
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package AXI4_Fabric;
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// ================================================================
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// This package defines a fabric connecting CPUs, Memories and DMAs
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// and other IP blocks.
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// ================================================================
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// Bluespec library imports
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import Vector :: *;
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import FIFOF :: *;
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import SpecialFIFOs :: *;
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import ConfigReg :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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// ================================================================
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// Project imports
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import Semi_FIFOF :: *;
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import AXI4_Types :: *;
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// ================================================================
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// The interface for the fabric module
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interface AXI4_Fabric_IFC #(numeric type num_masters,
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numeric type num_slaves,
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numeric type wd_id,
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numeric type wd_addr,
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numeric type wd_data,
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numeric type wd_user);
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method Action reset;
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method Action set_verbosity (Bit #(4) verbosity);
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// From masters
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interface Vector #(num_masters, AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user)) v_from_masters;
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// To slaves
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interface Vector #(num_slaves, AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user)) v_to_slaves;
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endinterface
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// ================================================================
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// The Fabric module
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// The function parameter is an address-decode function, which returns
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// returns (True, slave-port-num) if address is mapped to slave-port-num
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// (False, ?) if address is unmapped to any port
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module mkAXI4_Fabric #(function Tuple2 #(Bool, Bit #(TLog #(num_slaves)))
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fn_addr_to_slave_num (Bit #(wd_addr) addr))
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(AXI4_Fabric_IFC #(num_masters, num_slaves, wd_id, wd_addr, wd_data, wd_user))
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provisos (Log #(num_masters, log_nm),
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Log #(num_slaves, log_ns),
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Log #(TAdd #(num_masters, 1), log_nm_plus_1),
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Log #(TAdd #(num_slaves, 1), log_ns_plus_1),
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Add #(_dummy, TLog #(num_slaves), log_ns_plus_1));
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Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (0);
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Reg #(Bool) rg_reset <- mkReg (True);
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// Transactors facing masters
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Vector #(num_masters, AXI4_Slave_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user))
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xactors_from_masters <- replicateM (mkAXI4_Slave_Xactor);
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// Transactors facing slaves
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Vector #(num_slaves, AXI4_Master_Xactor_IFC #(wd_id, wd_addr, wd_data, wd_user))
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xactors_to_slaves <- replicateM (mkAXI4_Master_Xactor);
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// FIFOs to keep track of which master originated a transaction, in
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// order to route corresponding responses back to that master.
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// Legal masters are 0..(num_masters-1)
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// The value of 'num_masters' is used for decode errors (no such slave)
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Vector #(num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_wr_sjs <- replicateM (mkSizedFIFOF (8));
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Vector #(num_masters, FIFOF #(Bit #(wd_id))) v_f_wr_err_id <- replicateM (mkSizedFIFOF (8));
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Vector #(num_masters, FIFOF #(Bit #(wd_user))) v_f_wr_err_user <- replicateM (mkSizedFIFOF (8));
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Vector #(num_slaves, FIFOF #(Bit #(log_nm_plus_1))) v_f_wr_mis <- replicateM (mkSizedFIFOF (8));
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Vector #(num_masters, FIFOF #(Bit #(log_ns_plus_1))) v_f_rd_sjs <- replicateM (mkSizedFIFOF (8));
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Vector #(num_masters, FIFOF #(Bit #(wd_id))) v_f_rd_err_id <- replicateM (mkSizedFIFOF (8));
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Vector #(num_masters, FIFOF #(Bit #(wd_user))) v_f_rd_err_user <- replicateM (mkSizedFIFOF (8));
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Vector #(num_slaves, FIFOF #(Bit #(log_nm_plus_1))) v_f_rd_mis <- replicateM (mkSizedFIFOF (8));
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// ----------------------------------------------------------------
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// BEHAVIOR
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rule rl_reset (rg_reset);
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$display ("%0d: AXI4_Fabric.rl_reset", cur_cycle);
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1) begin
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xactors_from_masters [mi].reset;
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v_f_wr_sjs [mi].clear;
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v_f_wr_err_id [mi].clear;
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v_f_wr_err_user [mi].clear;
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v_f_rd_sjs [mi].clear;
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v_f_rd_err_id [mi].clear;
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v_f_rd_err_user [mi].clear;
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end
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for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1) begin
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xactors_to_slaves [sj].reset;
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v_f_wr_mis [sj].clear;
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v_f_rd_mis [sj].clear;
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end
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rg_reset <= False;
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endrule
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// ----------------------------------------------------------------
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// Help functions for moving data from masters to slaves
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Integer num_slaves_i = valueOf (num_slaves);
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function Bool wr_move_from_mi_to_sj (Integer mi, Integer sj);
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let addr = xactors_from_masters [mi].o_wr_addr.first.awaddr;
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match { .legal, .slave_num } = fn_addr_to_slave_num (addr);
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return (legal
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&& ( (num_slaves_i == 1)
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|| (slave_num == fromInteger (sj))));
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endfunction
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function Bool wr_illegal_sj (Integer mi);
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let addr = xactors_from_masters [mi].o_wr_addr.first.awaddr;
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match { .legal, ._ } = fn_addr_to_slave_num (addr);
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return (! legal);
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endfunction
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function Bool rd_move_from_mi_to_sj (Integer mi, Integer sj);
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let addr = xactors_from_masters [mi].o_rd_addr.first.araddr;
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match { .legal, .slave_num } = fn_addr_to_slave_num (addr);
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return (legal
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&& ( (num_slaves_i == 1)
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|| (slave_num == fromInteger (sj))));
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endfunction
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function Bool rd_illegal_sj (Integer mi);
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let addr = xactors_from_masters [mi].o_rd_addr.first.araddr;
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match { .legal, ._ } = fn_addr_to_slave_num (addr);
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return (! legal);
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endfunction
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// ----------------
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// Wr requests from masters to slaves
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// Legal destination slaves
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1)
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rule rl_wr_xaction_master_to_slave (wr_move_from_mi_to_sj (mi, sj));
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AXI4_Wr_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_wr_addr);
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AXI4_Wr_Data #(wd_id, wd_data, wd_user) d <- pop_o (xactors_from_masters [mi].o_wr_data);
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xactors_to_slaves [sj].i_wr_addr.enq (a);
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xactors_to_slaves [sj].i_wr_data.enq (d);
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v_f_wr_mis [sj].enq (fromInteger (mi));
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v_f_wr_sjs [mi].enq (fromInteger (sj));
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: wr master [%0d] -> slave [%0d]", cur_cycle, mi, sj);
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$display (" ", fshow (a));
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$display (" ", fshow (d));
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end
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endrule
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// Non-existent destination slaves
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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rule rl_wr_xaction_no_such_slave (wr_illegal_sj (mi));
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AXI4_Wr_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_wr_addr);
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AXI4_Wr_Data #(wd_id, wd_data, wd_user) d <- pop_o (xactors_from_masters [mi].o_wr_data);
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v_f_wr_sjs [mi].enq (fromInteger (valueOf (num_slaves)));
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v_f_wr_err_id [mi].enq (a.awid);
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v_f_wr_err_user [mi].enq (a.awuser);
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: wr master [%0d] -> illegal addr", cur_cycle, mi);
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$display (" ", fshow (a));
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end
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endrule
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// ----------------
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// Rd requests from masters to slaves
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// Legal destination slaves
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1)
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rule rl_rd_xaction_master_to_slave (rd_move_from_mi_to_sj (mi, sj));
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AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr);
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xactors_to_slaves [sj].i_rd_addr.enq (a);
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v_f_rd_mis [sj].enq (fromInteger (mi));
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v_f_rd_sjs [mi].enq (fromInteger (sj));
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: rd master [%0d] -> slave [%0d]", cur_cycle, mi, sj);
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$display (" ", fshow (a));
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end
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endrule
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// Non-existent destination slaves
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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rule rl_rd_xaction_no_such_slave (rd_illegal_sj (mi));
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AXI4_Rd_Addr #(wd_id, wd_addr, wd_user) a <- pop_o (xactors_from_masters [mi].o_rd_addr);
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v_f_rd_sjs [mi].enq (fromInteger (valueOf (num_slaves)));
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v_f_rd_err_id [mi].enq (a.arid);
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v_f_rd_err_user [mi].enq (a.aruser);
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: rd master [%0d] -> illegal addr", cur_cycle, mi);
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$display (" ", fshow (a));
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end
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endrule
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// ----------------
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// Wr responses from slaves to masters
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1)
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rule rl_wr_resp_slave_to_master ( (v_f_wr_mis [sj].first == fromInteger (mi))
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&& (v_f_wr_sjs [mi].first == fromInteger (sj)));
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v_f_wr_mis [sj].deq;
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v_f_wr_sjs [mi].deq;
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AXI4_Wr_Resp #(wd_id, wd_user) b <- pop_o (xactors_to_slaves [sj].o_wr_resp);
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xactors_from_masters [mi].i_wr_resp.enq (b);
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: wr master [%0d] <- slave [%0d]", cur_cycle, mi, sj);
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$display (" ", fshow (b));
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end
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endrule
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// ----------------
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// Wr error responses to masters
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// v_f_wr_sjs [mi].first has value num_slaves (illegal value)
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// v_f_wr_err_id [mi].first contains the request's 'id' data
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// v_f_wr_err_user [mi].first contains the request's 'user' data
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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rule rl_wr_resp_err_to_master (v_f_wr_sjs [mi].first == fromInteger (valueOf (num_slaves)));
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v_f_wr_sjs [mi].deq;
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v_f_wr_err_id [mi].deq;
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v_f_wr_err_user [mi].deq;
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let b = AXI4_Wr_Resp {bid: v_f_wr_err_id [mi].first,
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bresp: axi4_resp_decerr,
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buser: v_f_wr_err_user [mi].first};
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xactors_from_masters [mi].i_wr_resp.enq (b);
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: wr master [%0d] <- error", cur_cycle, mi);
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$display (" ", fshow (b));
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end
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endrule
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// ----------------
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// Rd responses from slaves to masters
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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for (Integer sj = 0; sj < valueOf (num_slaves); sj = sj + 1)
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rule rl_rd_resp_slave_to_master ( (v_f_rd_mis [sj].first == fromInteger (mi))
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&& (v_f_rd_sjs [mi].first == fromInteger (sj)));
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v_f_rd_mis [sj].deq;
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v_f_rd_sjs [mi].deq;
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AXI4_Rd_Data #(wd_id, wd_data, wd_user) r <- pop_o (xactors_to_slaves [sj].o_rd_data);
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xactors_from_masters [mi].i_rd_data.enq (r);
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: rd master [%0d] <- slave [%0d]", cur_cycle, mi, sj);
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$display (" ", fshow (r));
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end
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endrule
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// ----------------
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// Rd error responses to masters
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// v_f_rd_sjs [mi].first has value num_slaves (illegal value)
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// v_f_rd_err_id [mi].first contains the request's 'id' data
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// v_f_rd_err_user [mi].first contains the request's 'user' data
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for (Integer mi = 0; mi < valueOf (num_masters); mi = mi + 1)
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rule rl_rd_resp_err_to_master (v_f_rd_sjs [mi].first == fromInteger (valueOf (num_slaves)));
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v_f_rd_sjs [mi].deq;
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v_f_rd_err_id [mi].deq;
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v_f_rd_err_user [mi].deq;
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Bit #(wd_data) data = 0;
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let r = AXI4_Rd_Data {rid: v_f_rd_err_id [mi].first,
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rdata: data,
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rresp: axi4_resp_decerr,
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rlast: True,
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ruser: v_f_rd_err_user [mi].first};
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xactors_from_masters [mi].i_rd_data.enq (r);
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if (cfg_verbosity > 1) begin
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$display ("%0d: AXI4_Fabric: rd master [%0d] <- error", cur_cycle, mi);
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$display (" ", fshow (r));
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end
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endrule
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// ----------------------------------------------------------------
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// INTERFACE
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function AXI4_Slave_IFC #(wd_id, wd_addr, wd_data, wd_user) f1 (Integer j)
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= xactors_from_masters [j].axi_side;
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function AXI4_Master_IFC #(wd_id, wd_addr, wd_data, wd_user) f2 (Integer j)
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= xactors_to_slaves [j].axi_side;
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method Action reset () if (! rg_reset);
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rg_reset <= True;
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endmethod
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method Action set_verbosity (Bit #(4) verbosity);
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cfg_verbosity <= verbosity;
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endmethod
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interface v_from_masters = genWith (f1);
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interface v_to_slaves = genWith (f2);
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endmodule
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// ================================================================
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endpackage: AXI4_Fabric
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