117 lines
3.7 KiB
Verilog
117 lines
3.7 KiB
Verilog
// Copyright (c) 2000-2011 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision$
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// $Date$
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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// Dual-Ported BRAM (WRITE FIRST)
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module BRAM2(CLKA,
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ENA,
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WEA,
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ADDRA,
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DIA,
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DOA,
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CLKB,
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ENB,
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WEB,
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ADDRB,
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DIB,
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DOB
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);
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parameter PIPELINED = 0;
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parameter ADDR_WIDTH = 1;
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parameter DATA_WIDTH = 1;
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parameter MEMSIZE = 1;
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input CLKA;
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input ENA;
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input WEA;
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input [ADDR_WIDTH-1:0] ADDRA;
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input [DATA_WIDTH-1:0] DIA;
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output [DATA_WIDTH-1:0] DOA;
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input CLKB;
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input ENB;
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input WEB;
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input [ADDR_WIDTH-1:0] ADDRB;
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input [DATA_WIDTH-1:0] DIB;
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output [DATA_WIDTH-1:0] DOB;
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reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
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reg [DATA_WIDTH-1:0] DOA_R;
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reg [DATA_WIDTH-1:0] DOB_R;
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reg [DATA_WIDTH-1:0] DOA_R2;
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reg [DATA_WIDTH-1:0] DOB_R2;
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`ifdef BSV_NO_INITIAL_BLOCKS
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`else
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// synopsys translate_off
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integer i;
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initial
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begin : init_block
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for (i = 0; i < MEMSIZE; i = i + 1) begin
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RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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end
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DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
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end
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// synopsys translate_on
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`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
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always @(posedge CLKA) begin
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if (ENA) begin
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if (WEA) begin
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RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
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DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
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end
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else begin
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DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
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end
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end
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DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
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end
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always @(posedge CLKB) begin
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if (ENB) begin
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if (WEB) begin
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RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
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DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
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end
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else begin
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DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
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end
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end
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DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
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end
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// Output drivers
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assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
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assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
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endmodule // BRAM2
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