311 lines
11 KiB
Plaintext
311 lines
11 KiB
Plaintext
// Copyright (c) 2019 Bluespec, Inc. All Rights Reserved
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//
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//-
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// RVFI_DII + CHERI modifications:
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// Copyright (c) 2020 Jonathan Woodruff
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// All rights reserved.
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//
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// This software was developed by SRI International and the University of
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// Cambridge Computer Laboratory (Department of Computer Science and
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// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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// DARPA SSITH research programme.
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//
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// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
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//-
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package Test_PLIC;
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// ================================================================
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// Standalone unit-test testbench for PLIC.
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//
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// ================================================================
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// Bluespec lib imports
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import ConfigReg :: *;
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import Vector :: *;
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import FIFOF :: *;
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import GetPut :: *;
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import ClientServer :: *;
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import Connectable :: *;
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import Assert :: *;
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import StmtFSM :: *;
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// ----------------
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// BSV additional libs
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import Cur_Cycle :: *;
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import GetPut_Aux :: *;
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import Semi_FIFOF :: *;
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// ================================================================
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// Project imports
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import AXI4_Types :: *;
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import AXI4_Fabric :: *;
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import Fabric_Defs :: *; // for Wd_Id, Wd_Addr, Wd_Data, Wd_User
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import SoC_Map :: *;
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import PLIC :: *;
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import PLIC_16_CoreNumX2_7 :: *;
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// ================================================================
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Integer n_external_interrupt_sources = valueOf (N_External_Interrupt_Sources);
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typedef TAdd #(1, N_External_Interrupt_Sources) N_Interrupt_Sources;
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typedef Bit #(TLog #(N_Interrupt_Sources)) Source_Id;
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Integer plic_n_targets = valueOf (PLIC_N_Targets);
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Integer target_0 = 0;
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Integer target_1 = 1;
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Integer plic_max_priority = valueOf (PLIC_Max_Priority);
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typedef Bit #(TLog #(TAdd #(1, PLIC_Max_Priority))) Priority;
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// ================================================================
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// The Core module
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(* synthesize *)
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module mkTest_PLIC (Empty);
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// System address map
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SoC_Map_IFC soc_map <- mkSoC_Map;
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// PLIC (Platform-Level Interrupt Controller)
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PLIC_IFC_16_CoreNumX2_7 plic <- mkPLIC_16_CoreNumX2_7;
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// Master transactor through which to read/write PLIC regs
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AXI4_Master_Xactor_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User) master_xactor <- mkAXI4_Master_Xactor;
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Vector #(N_Interrupt_Sources, Reg #(Bool)) vrg_irqs <- replicateM (mkReg (False));
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// ================================================================
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// AXI4 interactions
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FIFOF #(Fabric_Addr) f_read_addr <- mkFIFOF;
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FIFOF #(Fabric_Data) f_read_data <- mkFIFOF;
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function Action fa_read_req (Integer addr);
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action
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let fabric_addr = soc_map.m_plic_addr_base + fromInteger (addr);
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let mem_req_rd_addr = AXI4_Rd_Addr {arid: fabric_default_id,
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araddr: fabric_addr,
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arlen: 0, // burst len = arlen+1
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arsize: zeroExtend (axsize_4),
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arburst: fabric_default_burst,
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arlock: fabric_default_lock,
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arcache: fabric_default_arcache,
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arprot: fabric_default_prot,
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arqos: fabric_default_qos,
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arregion: fabric_default_region,
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aruser: fabric_default_user};
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master_xactor.i_rd_addr.enq (mem_req_rd_addr);
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f_read_addr.enq (fabric_addr);
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endaction
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endfunction
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function Action fa_read_rsp;
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action
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let fabric_addr <- pop (f_read_addr);
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let rd_data <- pop_o (master_xactor.o_rd_data);
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if (rd_data.rresp != axi4_resp_okay) begin
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$display ("ERROR: fa_read_rsp: fabric response error");
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$display (" ", fshow (rd_data));
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end
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let x = (((valueOf (Wd_Data) == 64) && ((fabric_addr & 'h7) == 'h4))
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? (rd_data.rdata >> 32)
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: rd_data.rdata);
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f_read_data.enq (x);
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endaction
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endfunction
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function Action fa_write_req (Integer addr, Fabric_Data data);
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action
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let fabric_addr = soc_map.m_plic_addr_base + fromInteger (addr);
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let mem_req_wr_addr = AXI4_Wr_Addr {awid: fabric_default_id,
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awaddr: fabric_addr,
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awlen: 0, // burst len = awlen+1
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awsize: zeroExtend (axsize_4),
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awburst: fabric_default_burst,
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awlock: fabric_default_lock,
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awcache: fabric_default_awcache,
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awprot: fabric_default_prot,
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awqos: fabric_default_qos,
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awregion: fabric_default_region,
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awuser: fabric_default_user};
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let x = (((valueOf (Wd_Data) == 64) && ((fabric_addr & 'h7) == 'h4))
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? (data << 32)
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: data);
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let mem_req_wr_data = AXI4_Wr_Data {wid: fabric_default_id,
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wdata: x,
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wstrb: '1,
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wlast: True,
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wuser: fabric_default_user};
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master_xactor.i_wr_addr.enq (mem_req_wr_addr);
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master_xactor.i_wr_data.enq (mem_req_wr_data);
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endaction
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endfunction
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function Action fa_write_rsp;
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action
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let wr_resp <- pop_o (master_xactor.o_wr_resp);
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if (wr_resp.bresp != axi4_resp_okay) begin
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$display ("ERROR: rl_discard_write_rsp: fabric response error");
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$display (" ", fshow (wr_resp));
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end
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endaction
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endfunction
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// ================================================================
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// Help functions to interact with PLIC at an "API" level
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function Action fa_print_plic_eips ();
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action
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$write ("PLIC.v_target eip =");
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$write (" ", fshow (plic.v_targets [0].m_eip));
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$write (" ", fshow (plic.v_targets [1].m_eip));
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$display ("");
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endaction
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endfunction
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function Stmt fstmt_set_source_priority (Integer src, Priority prio);
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return seq
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fa_write_req (src * 4, zeroExtend (prio));
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fa_write_rsp;
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endseq;
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endfunction
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function Stmt fstmt_set_target_ies (Integer target, Bit #(32) ies);
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return seq
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fa_write_req ('h2000 + (target * 'h80), zeroExtend (ies));
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fa_write_rsp;
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endseq;
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endfunction
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function Stmt fstmt_set_target_threshold (Integer target, Priority threshold);
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return seq
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fa_write_req ('h20_0000 + (target * 'h1000), zeroExtend (threshold));
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fa_write_rsp;
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endseq;
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endfunction
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function Stmt fstmt_claim (Integer target);
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return seq
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fa_read_req ('h20_0004 + (target * 'h1000));
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fa_read_rsp;
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action
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let x <- pop (f_read_data);
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$display ("fstmt_claim: PLIC returned %0d", x);
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endaction
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endseq;
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endfunction
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function Stmt fstmt_complete (Integer target, Source_Id source_id);
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return seq
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fa_write_req ('h20_0004 + (target * 'h1000), zeroExtend (source_id));
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fa_write_rsp;
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endseq;
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endfunction
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// ================================================================
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// BEHAVIOR
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mkConnection (master_xactor.axi_side, plic.axi4_slave);
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// Drive all interrupt requests from local regs
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for (Integer j = 0; j < n_external_interrupt_sources; j = j + 1)
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rule rl_drive_irq;
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plic.v_sources [j].m_interrupt_req (vrg_irqs [j]);
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endrule
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// ================================================================
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Stmt init = seq
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action
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$display ("Initializing PLIC");
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plic.server_reset.request.put (?);
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endaction
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action
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let rsp <- plic.server_reset.response.get;
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plic.set_addr_map (zeroExtend (soc_map.m_plic_addr_base),
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zeroExtend (soc_map.m_plic_addr_lim));
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endaction
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fstmt_set_source_priority (1, 0);
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fstmt_set_source_priority (2, 0);
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fstmt_set_source_priority (3, 0);
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fstmt_set_source_priority (4, 0);
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fstmt_set_source_priority (5, 0);
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fstmt_set_source_priority (6, 0);
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fstmt_set_source_priority (7, 0);
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fstmt_set_source_priority (8, 0);
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fstmt_set_source_priority (9, 0);
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fstmt_set_source_priority (10, 0);
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fstmt_set_source_priority (11, 0);
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fstmt_set_source_priority (12, 0);
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fstmt_set_source_priority (13, 0);
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fstmt_set_source_priority (14, 0);
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fstmt_set_source_priority (15, 0);
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fstmt_set_source_priority (16, 0);
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fstmt_set_target_ies (target_0, 0);
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fstmt_set_target_ies (target_1, 0);
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fstmt_set_target_threshold (target_0, 7);
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fstmt_set_target_threshold (target_1, 7);
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delay (5);
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$display ("Finished Initializing PLIC");
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endseq;
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Stmt test1 = seq
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$display (">---------------- TEST 1");
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plic.set_verbosity (1);
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fstmt_set_source_priority (5, 4);
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fstmt_set_target_ies (target_0, 'b10_0000); // bit 5
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fstmt_set_target_threshold (target_0, 4);
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fstmt_set_target_ies (target_1, 'b10_0000); // bit 5
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fstmt_set_target_threshold (target_1, 2);
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plic.show_PLIC_state;
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fa_print_plic_eips;
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vrg_irqs [5] <= True;
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delay (2);
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plic.show_PLIC_state;
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fa_print_plic_eips;
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fstmt_set_target_threshold (target_0, 3);
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plic.show_PLIC_state;
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fa_print_plic_eips;
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fstmt_claim (target_1);
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plic.show_PLIC_state;
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fa_print_plic_eips;
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fstmt_complete (target_1, 5);
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plic.show_PLIC_state;
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fa_print_plic_eips;
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endseq;
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// ================================================================
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mkAutoFSM (seq
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init;
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test1;
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$finish (0);
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endseq);
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endmodule
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// ================================================================
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endpackage
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