rsnikhil db114186af More progress towards Tandem Verification trace generation (detail below) ...

Now handling all Alu and Fpu pipeline outputs, traps and xRets.
Still todo:
 (1) Mem pipeline outputs (Ld, Lr/Sc, Amo outputs to dest reg)
 (2) For CSRRx, currently reporting WARL pre-write updates; needs to be WARL'd update.

2020-02-10 15:08:08 -05:00

..

Core.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

CPU_Decode_C.bsv

Changes to support 'C' extension (compressed instructions). Details follow.

2019-04-09 13:50:16 -04:00

CsrFile.bsv

More progress towards Tandem Verification trace generation (detail below)

2020-02-10 15:08:08 -05:00

LLC_AXI4_Adapter.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

MMIO_AXI4_Adapter.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

MMIOPlatform.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc_IFC.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

Proc.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00