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db114186af8e8785c6ee970465222af0b804480b
Toooba/src_Core/RISCY_OOO/procs/lib
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rsnikhil db114186af More progress towards Tandem Verification trace generation (detail below) 
Now handling all Alu and Fpu pipeline outputs, traps and xRets.
Still todo:
 (1) Mem pipeline outputs (Ld, Lr/Sc, Amo outputs to dest reg)
 (2) For CSRRx, currently reporting WARL pre-write updates; needs to be WARL'd update.
2020-02-10 15:08:08 -05:00
..
Amo.bsv
Initial load of files
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Bht.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
BrPred.bsv
Changes to support 'C' extension (compressed instructions). Details follow.
2019-04-09 13:50:16 -04:00
Btb.bsv
Reduce needless fetch stalls in presence of compressed instructions
2020-01-01 22:22:17 +00:00
Bypass.bsv
Initial load of files
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CacheUtils.bsv
Initial load of files
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ConcatReg.bsv
Initial load of files
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Decode.bsv
Initial load of files
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DirPredictor.bsv
Initial load of files
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DTlb.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
Ehr.bsv
Initial load of files
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EpochManager.bsv
Initial load of files
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Exec.bsv
Changes to support 'C' extension (compressed instructions). Details follow.
2019-04-09 13:50:16 -04:00
Fifo.bsv
Initial load of files
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FP_Utils.bsv
FP ISA tests bug fixes:
2019-12-06 14:27:33 +05:30
Fpu.bsv
Fix FMIN/FMAX ISA test failures
2020-01-02 01:12:51 +00:00
FullAssocTlb.bsv
Initial load of files
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GlobalBrHistReg.bsv
Initial load of files
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GlobalSpecUpdate.bsv
Initial load of files
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GSelectPred.bsv
Initial load of files
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GSharePred.bsv
Initial load of files
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HasSpecBits.bsv
Initial load of files
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ITlb.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
L1CoCache.bsv
Initial load of files
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L1LLConnect.bsv
Initial load of files
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L2SetAssocTlb.bsv
Initial load of files
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L2Tlb.bsv
Bugfix. Now passing rv64si-p-dirty ISA test.
2019-04-11 14:30:53 -04:00
LatencyTimer.bsv
Initial load of files
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LLCache.bsv
Initial load of files
2019-03-26 14:49:40 -04:00
LLCDmaConnect.bsv
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
LLCRqMshrSecureModel.bsv
Initial load of files
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MemLoader.bsv
Changes to support 'C' extension (compressed instructions). Details follow.
2019-04-09 13:50:16 -04:00
MemLoaderIF.bsv
Initial load of files
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MemoryTypes.bsv
Initial load of files
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MMIOAddrs.bsv
Small tweak to remove unnecessary explicit boot rom addrs (subsumed by IO)
2019-04-22 15:12:30 -04:00
MMIOCore.bsv
Bug fixes; now passing rv64mi-p-access ISA test
2019-04-10 12:42:23 -04:00
MMIOInst.bsv
Revert unwanted MMIOInst diff in e7fbf32b38
2019-11-03 03:47:25 +00:00
MsgFifo.bsv
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MulDiv.bsv
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Performance.bsv
Initial load of files
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PhysRFile.bsv
Initial load of files
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ProcTypes.bsv
Work in progress on Debug Module integration. Got further on start/step/halt
2020-01-12 22:25:14 -05:00
Ras.bsv
Initial load of files
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RenameDebugIF.bsv
Initial load of files
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RenamingTable.bsv
Initial load of files
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ReorderBuffer.bsv
More progress towards Tandem Verification trace generation (detail below)
2020-02-10 15:08:08 -05:00
ReservationStationEhr.bsv
Added verbosity guards around $displays to dial down log verbosity
2019-04-01 20:35:52 -04:00
SafeCounter.bsv
Initial load of files
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Scoreboard.bsv
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SetAssocTlb.bsv
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SpecFifo.bsv
Initial load of files
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SpecPoisonFifo.bsv
Initial load of files
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SpecTagManager.bsv
Initial load of files
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SplitLSQ.bsv
FP ISA tests bug fixes:
2019-12-06 14:27:33 +05:30
StoreBuffer.bsv
Initial load of files
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TlbConnect.bsv
Initial load of files
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TlbTypes.bsv
Initial load of files
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TourPred.bsv
Initial load of files
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TourPredSecure.bsv
Initial load of files
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TranslationCache.bsv
Initial load of files
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Types.bsv
Changes to support 'C' extension (compressed instructions). Details follow.
2019-04-09 13:50:16 -04:00
VerificationPacket.bsv
Initial load of files
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