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Toooba/src_SSITH_P3/Verilog_RTL_sim/mkProc.v
Peter Rugg 3117fcc9d5 Regenerate verilog
2020-06-07 16:52:34 +01:00

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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Sat Jun 6 22:42:54 BST 2020
//
//
// Ports:
// Name I/O size props
// RDY_start O 1
// master0_awid O 5
// master0_awaddr O 64
// master0_awlen O 8
// master0_awsize O 3
// master0_awburst O 2
// master0_awlock O 1
// master0_awcache O 4
// master0_awprot O 3
// master0_awqos O 4
// master0_awregion O 4
// master0_awvalid O 1
// master0_wdata O 64
// master0_wstrb O 8
// master0_wlast O 1
// master0_wuser O 1
// master0_wvalid O 1
// master0_bready O 1
// master0_arid O 5
// master0_araddr O 64
// master0_arlen O 8
// master0_arsize O 3
// master0_arburst O 2
// master0_arlock O 1
// master0_arcache O 4
// master0_arprot O 3
// master0_arqos O 4
// master0_arregion O 4
// master0_arvalid O 1
// master0_rready O 1
// master1_awid O 4
// master1_awaddr O 64
// master1_awlen O 8
// master1_awsize O 3
// master1_awburst O 2
// master1_awlock O 1
// master1_awcache O 4
// master1_awprot O 3
// master1_awqos O 4
// master1_awregion O 4
// master1_awvalid O 1
// master1_wdata O 64
// master1_wstrb O 8
// master1_wlast O 1
// master1_wuser O 1
// master1_wvalid O 1
// master1_bready O 1
// master1_arid O 4
// master1_araddr O 64
// master1_arlen O 8
// master1_arsize O 3
// master1_arburst O 2
// master1_arlock O 1
// master1_arcache O 4
// master1_arprot O 3
// master1_arqos O 4
// master1_arregion O 4
// master1_arvalid O 1
// master1_rready O 1
// RDY_set_verbosity O 1 const
// debug_module_mem_server_awready O 1
// debug_module_mem_server_wready O 1
// debug_module_mem_server_bid O 5
// debug_module_mem_server_bresp O 2
// debug_module_mem_server_bvalid O 1
// debug_module_mem_server_arready O 1
// debug_module_mem_server_rid O 5
// debug_module_mem_server_rdata O 64
// debug_module_mem_server_rresp O 2
// debug_module_mem_server_rlast O 1
// debug_module_mem_server_ruser O 1
// debug_module_mem_server_rvalid O 1
// RDY_hart0_run_halt_server_request_put O 1 reg
// hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_gpr_mem_server_request_put O 1 reg
// hart0_gpr_mem_server_response_get O 65 reg
// RDY_hart0_gpr_mem_server_response_get O 1 reg
// RDY_hart0_fpr_mem_server_request_put O 1 reg
// hart0_fpr_mem_server_response_get O 65 reg
// RDY_hart0_fpr_mem_server_response_get O 1 reg
// RDY_hart0_csr_mem_server_request_put O 1 reg
// hart0_csr_mem_server_response_get O 65 reg
// RDY_hart0_csr_mem_server_response_get O 1 reg
// RDY_hart0_put_other_req_put O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// start_startpc I 64
// start_tohostAddr I 64 reg
// start_fromhostAddr I 64 reg
// master0_awready I 1
// master0_wready I 1
// master0_bid I 5
// master0_bresp I 2
// master0_arready I 1
// master0_rid I 5
// master0_rdata I 64
// master0_rresp I 2
// master0_rlast I 1
// master0_ruser I 1
// master1_awready I 1
// master1_wready I 1
// master1_bid I 4
// master1_bresp I 2
// master1_arready I 1
// master1_rid I 4
// master1_rdata I 64
// master1_rresp I 2
// master1_rlast I 1
// master1_ruser I 1
// m_external_interrupt_req_set_not_clear I 1 reg
// s_external_interrupt_req_set_not_clear I 1
// non_maskable_interrupt_req_set_not_clear I 1 unused
// set_verbosity_verbosity I 4
// debug_module_mem_server_awid I 5
// debug_module_mem_server_awaddr I 64
// debug_module_mem_server_awlen I 8
// debug_module_mem_server_awsize I 3
// debug_module_mem_server_awburst I 2
// debug_module_mem_server_awlock I 1
// debug_module_mem_server_awcache I 4
// debug_module_mem_server_awprot I 3
// debug_module_mem_server_awqos I 4
// debug_module_mem_server_awregion I 4
// debug_module_mem_server_wdata I 64
// debug_module_mem_server_wstrb I 8
// debug_module_mem_server_wlast I 1
// debug_module_mem_server_wuser I 1
// debug_module_mem_server_bready I 1
// debug_module_mem_server_arid I 5
// debug_module_mem_server_araddr I 64
// debug_module_mem_server_arlen I 8
// debug_module_mem_server_arsize I 3
// debug_module_mem_server_arburst I 2
// debug_module_mem_server_arlock I 1
// debug_module_mem_server_arcache I 4
// debug_module_mem_server_arprot I 3
// debug_module_mem_server_arqos I 4
// debug_module_mem_server_arregion I 4
// debug_module_mem_server_rready I 1
// hart0_run_halt_server_request_put I 1 reg
// hart0_gpr_mem_server_request_put I 70 reg
// hart0_fpr_mem_server_request_put I 70 reg
// hart0_csr_mem_server_request_put I 77 reg
// hart0_put_other_req_put I 4
// EN_start I 1
// master0_bvalid I 1
// master0_rvalid I 1
// master1_bvalid I 1
// master1_rvalid I 1
// EN_set_verbosity I 1
// debug_module_mem_server_awvalid I 1
// debug_module_mem_server_wvalid I 1
// debug_module_mem_server_arvalid I 1
// EN_hart0_run_halt_server_request_put I 1
// EN_hart0_gpr_mem_server_request_put I 1
// EN_hart0_fpr_mem_server_request_put I 1
// EN_hart0_csr_mem_server_request_put I 1
// EN_hart0_put_other_req_put I 1
// EN_hart0_run_halt_server_response_get I 1
// EN_hart0_gpr_mem_server_response_get I 1
// EN_hart0_fpr_mem_server_response_get I 1
// EN_hart0_csr_mem_server_response_get I 1
//
// Combinational paths from inputs to outputs:
// (debug_module_mem_server_awid,
// debug_module_mem_server_awaddr,
// debug_module_mem_server_awlen,
// debug_module_mem_server_awsize,
// debug_module_mem_server_awburst,
// debug_module_mem_server_awlock,
// debug_module_mem_server_awcache,
// debug_module_mem_server_awprot,
// debug_module_mem_server_awqos,
// debug_module_mem_server_awregion,
// debug_module_mem_server_wdata,
// debug_module_mem_server_wstrb,
// debug_module_mem_server_wlast,
// debug_module_mem_server_wuser,
// debug_module_mem_server_awvalid,
// debug_module_mem_server_wvalid) -> debug_module_mem_server_bid
// (debug_module_mem_server_awid,
// debug_module_mem_server_awaddr,
// debug_module_mem_server_awlen,
// debug_module_mem_server_awsize,
// debug_module_mem_server_awburst,
// debug_module_mem_server_awlock,
// debug_module_mem_server_awcache,
// debug_module_mem_server_awprot,
// debug_module_mem_server_awqos,
// debug_module_mem_server_awregion,
// debug_module_mem_server_wdata,
// debug_module_mem_server_wstrb,
// debug_module_mem_server_wlast,
// debug_module_mem_server_wuser,
// debug_module_mem_server_awvalid,
// debug_module_mem_server_wvalid) -> debug_module_mem_server_bresp
// (debug_module_mem_server_awid,
// debug_module_mem_server_awaddr,
// debug_module_mem_server_awlen,
// debug_module_mem_server_awsize,
// debug_module_mem_server_awburst,
// debug_module_mem_server_awlock,
// debug_module_mem_server_awcache,
// debug_module_mem_server_awprot,
// debug_module_mem_server_awqos,
// debug_module_mem_server_awregion,
// debug_module_mem_server_wdata,
// debug_module_mem_server_wstrb,
// debug_module_mem_server_wlast,
// debug_module_mem_server_wuser,
// debug_module_mem_server_awvalid,
// debug_module_mem_server_wvalid) -> debug_module_mem_server_buser
// (debug_module_mem_server_awid,
// debug_module_mem_server_awaddr,
// debug_module_mem_server_awlen,
// debug_module_mem_server_awsize,
// debug_module_mem_server_awburst,
// debug_module_mem_server_awlock,
// debug_module_mem_server_awcache,
// debug_module_mem_server_awprot,
// debug_module_mem_server_awqos,
// debug_module_mem_server_awregion,
// debug_module_mem_server_wdata,
// debug_module_mem_server_wstrb,
// debug_module_mem_server_wlast,
// debug_module_mem_server_wuser,
// debug_module_mem_server_awvalid,
// debug_module_mem_server_wvalid) -> debug_module_mem_server_bvalid
// (debug_module_mem_server_arid,
// debug_module_mem_server_araddr,
// debug_module_mem_server_arlen,
// debug_module_mem_server_arsize,
// debug_module_mem_server_arburst,
// debug_module_mem_server_arlock,
// debug_module_mem_server_arcache,
// debug_module_mem_server_arprot,
// debug_module_mem_server_arqos,
// debug_module_mem_server_arregion,
// debug_module_mem_server_arvalid) -> debug_module_mem_server_rid
// (debug_module_mem_server_arid,
// debug_module_mem_server_araddr,
// debug_module_mem_server_arlen,
// debug_module_mem_server_arsize,
// debug_module_mem_server_arburst,
// debug_module_mem_server_arlock,
// debug_module_mem_server_arcache,
// debug_module_mem_server_arprot,
// debug_module_mem_server_arqos,
// debug_module_mem_server_arregion,
// debug_module_mem_server_arvalid) -> debug_module_mem_server_rdata
// (debug_module_mem_server_arid,
// debug_module_mem_server_araddr,
// debug_module_mem_server_arlen,
// debug_module_mem_server_arsize,
// debug_module_mem_server_arburst,
// debug_module_mem_server_arlock,
// debug_module_mem_server_arcache,
// debug_module_mem_server_arprot,
// debug_module_mem_server_arqos,
// debug_module_mem_server_arregion,
// debug_module_mem_server_arvalid) -> debug_module_mem_server_rresp
// (debug_module_mem_server_arid,
// debug_module_mem_server_araddr,
// debug_module_mem_server_arlen,
// debug_module_mem_server_arsize,
// debug_module_mem_server_arburst,
// debug_module_mem_server_arlock,
// debug_module_mem_server_arcache,
// debug_module_mem_server_arprot,
// debug_module_mem_server_arqos,
// debug_module_mem_server_arregion,
// debug_module_mem_server_arvalid) -> debug_module_mem_server_rlast
// (debug_module_mem_server_arid,
// debug_module_mem_server_araddr,
// debug_module_mem_server_arlen,
// debug_module_mem_server_arsize,
// debug_module_mem_server_arburst,
// debug_module_mem_server_arlock,
// debug_module_mem_server_arcache,
// debug_module_mem_server_arprot,
// debug_module_mem_server_arqos,
// debug_module_mem_server_arregion,
// debug_module_mem_server_arvalid) -> debug_module_mem_server_ruser
// (debug_module_mem_server_arid,
// debug_module_mem_server_araddr,
// debug_module_mem_server_arlen,
// debug_module_mem_server_arsize,
// debug_module_mem_server_arburst,
// debug_module_mem_server_arlock,
// debug_module_mem_server_arcache,
// debug_module_mem_server_arprot,
// debug_module_mem_server_arqos,
// debug_module_mem_server_arregion,
// debug_module_mem_server_arvalid) -> debug_module_mem_server_rvalid
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkProc(CLK,
RST_N,
start_startpc,
start_tohostAddr,
start_fromhostAddr,
EN_start,
RDY_start,
master0_awid,
master0_awaddr,
master0_awlen,
master0_awsize,
master0_awburst,
master0_awlock,
master0_awcache,
master0_awprot,
master0_awqos,
master0_awregion,
master0_awvalid,
master0_awready,
master0_wdata,
master0_wstrb,
master0_wlast,
master0_wuser,
master0_wvalid,
master0_wready,
master0_bid,
master0_bresp,
master0_bvalid,
master0_bready,
master0_arid,
master0_araddr,
master0_arlen,
master0_arsize,
master0_arburst,
master0_arlock,
master0_arcache,
master0_arprot,
master0_arqos,
master0_arregion,
master0_arvalid,
master0_arready,
master0_rid,
master0_rdata,
master0_rresp,
master0_rlast,
master0_ruser,
master0_rvalid,
master0_rready,
master1_awid,
master1_awaddr,
master1_awlen,
master1_awsize,
master1_awburst,
master1_awlock,
master1_awcache,
master1_awprot,
master1_awqos,
master1_awregion,
master1_awvalid,
master1_awready,
master1_wdata,
master1_wstrb,
master1_wlast,
master1_wuser,
master1_wvalid,
master1_wready,
master1_bid,
master1_bresp,
master1_bvalid,
master1_bready,
master1_arid,
master1_araddr,
master1_arlen,
master1_arsize,
master1_arburst,
master1_arlock,
master1_arcache,
master1_arprot,
master1_arqos,
master1_arregion,
master1_arvalid,
master1_arready,
master1_rid,
master1_rdata,
master1_rresp,
master1_rlast,
master1_ruser,
master1_rvalid,
master1_rready,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
non_maskable_interrupt_req_set_not_clear,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
debug_module_mem_server_awid,
debug_module_mem_server_awaddr,
debug_module_mem_server_awlen,
debug_module_mem_server_awsize,
debug_module_mem_server_awburst,
debug_module_mem_server_awlock,
debug_module_mem_server_awcache,
debug_module_mem_server_awprot,
debug_module_mem_server_awqos,
debug_module_mem_server_awregion,
debug_module_mem_server_awvalid,
debug_module_mem_server_awready,
debug_module_mem_server_wdata,
debug_module_mem_server_wstrb,
debug_module_mem_server_wlast,
debug_module_mem_server_wuser,
debug_module_mem_server_wvalid,
debug_module_mem_server_wready,
debug_module_mem_server_bid,
debug_module_mem_server_bresp,
debug_module_mem_server_bvalid,
debug_module_mem_server_bready,
debug_module_mem_server_arid,
debug_module_mem_server_araddr,
debug_module_mem_server_arlen,
debug_module_mem_server_arsize,
debug_module_mem_server_arburst,
debug_module_mem_server_arlock,
debug_module_mem_server_arcache,
debug_module_mem_server_arprot,
debug_module_mem_server_arqos,
debug_module_mem_server_arregion,
debug_module_mem_server_arvalid,
debug_module_mem_server_arready,
debug_module_mem_server_rid,
debug_module_mem_server_rdata,
debug_module_mem_server_rresp,
debug_module_mem_server_rlast,
debug_module_mem_server_ruser,
debug_module_mem_server_rvalid,
debug_module_mem_server_rready,
hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_response_get,
hart0_run_halt_server_response_get,
RDY_hart0_run_halt_server_response_get,
hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_response_get,
hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
RDY_hart0_fpr_mem_server_response_get,
hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_response_get,
hart0_csr_mem_server_response_get,
RDY_hart0_csr_mem_server_response_get,
hart0_put_other_req_put,
EN_hart0_put_other_req_put,
RDY_hart0_put_other_req_put);
input CLK;
input RST_N;
// action method start
input [63 : 0] start_startpc;
input [63 : 0] start_tohostAddr;
input [63 : 0] start_fromhostAddr;
input EN_start;
output RDY_start;
// value method master0_aw_awid
output [4 : 0] master0_awid;
// value method master0_aw_awaddr
output [63 : 0] master0_awaddr;
// value method master0_aw_awlen
output [7 : 0] master0_awlen;
// value method master0_aw_awsize
output [2 : 0] master0_awsize;
// value method master0_aw_awburst
output [1 : 0] master0_awburst;
// value method master0_aw_awlock
output master0_awlock;
// value method master0_aw_awcache
output [3 : 0] master0_awcache;
// value method master0_aw_awprot
output [2 : 0] master0_awprot;
// value method master0_aw_awqos
output [3 : 0] master0_awqos;
// value method master0_aw_awregion
output [3 : 0] master0_awregion;
// value method master0_aw_awuser
// value method master0_aw_awvalid
output master0_awvalid;
// action method master0_aw_awready
input master0_awready;
// value method master0_w_wdata
output [63 : 0] master0_wdata;
// value method master0_w_wstrb
output [7 : 0] master0_wstrb;
// value method master0_w_wlast
output master0_wlast;
// value method master0_w_wuser
output master0_wuser;
// value method master0_w_wvalid
output master0_wvalid;
// action method master0_w_wready
input master0_wready;
// action method master0_b_bflit
input [4 : 0] master0_bid;
input [1 : 0] master0_bresp;
input master0_bvalid;
// value method master0_b_bready
output master0_bready;
// value method master0_ar_arid
output [4 : 0] master0_arid;
// value method master0_ar_araddr
output [63 : 0] master0_araddr;
// value method master0_ar_arlen
output [7 : 0] master0_arlen;
// value method master0_ar_arsize
output [2 : 0] master0_arsize;
// value method master0_ar_arburst
output [1 : 0] master0_arburst;
// value method master0_ar_arlock
output master0_arlock;
// value method master0_ar_arcache
output [3 : 0] master0_arcache;
// value method master0_ar_arprot
output [2 : 0] master0_arprot;
// value method master0_ar_arqos
output [3 : 0] master0_arqos;
// value method master0_ar_arregion
output [3 : 0] master0_arregion;
// value method master0_ar_aruser
// value method master0_ar_arvalid
output master0_arvalid;
// action method master0_ar_arready
input master0_arready;
// action method master0_r_rflit
input [4 : 0] master0_rid;
input [63 : 0] master0_rdata;
input [1 : 0] master0_rresp;
input master0_rlast;
input master0_ruser;
input master0_rvalid;
// value method master0_r_rready
output master0_rready;
// value method master1_aw_awid
output [3 : 0] master1_awid;
// value method master1_aw_awaddr
output [63 : 0] master1_awaddr;
// value method master1_aw_awlen
output [7 : 0] master1_awlen;
// value method master1_aw_awsize
output [2 : 0] master1_awsize;
// value method master1_aw_awburst
output [1 : 0] master1_awburst;
// value method master1_aw_awlock
output master1_awlock;
// value method master1_aw_awcache
output [3 : 0] master1_awcache;
// value method master1_aw_awprot
output [2 : 0] master1_awprot;
// value method master1_aw_awqos
output [3 : 0] master1_awqos;
// value method master1_aw_awregion
output [3 : 0] master1_awregion;
// value method master1_aw_awuser
// value method master1_aw_awvalid
output master1_awvalid;
// action method master1_aw_awready
input master1_awready;
// value method master1_w_wdata
output [63 : 0] master1_wdata;
// value method master1_w_wstrb
output [7 : 0] master1_wstrb;
// value method master1_w_wlast
output master1_wlast;
// value method master1_w_wuser
output master1_wuser;
// value method master1_w_wvalid
output master1_wvalid;
// action method master1_w_wready
input master1_wready;
// action method master1_b_bflit
input [3 : 0] master1_bid;
input [1 : 0] master1_bresp;
input master1_bvalid;
// value method master1_b_bready
output master1_bready;
// value method master1_ar_arid
output [3 : 0] master1_arid;
// value method master1_ar_araddr
output [63 : 0] master1_araddr;
// value method master1_ar_arlen
output [7 : 0] master1_arlen;
// value method master1_ar_arsize
output [2 : 0] master1_arsize;
// value method master1_ar_arburst
output [1 : 0] master1_arburst;
// value method master1_ar_arlock
output master1_arlock;
// value method master1_ar_arcache
output [3 : 0] master1_arcache;
// value method master1_ar_arprot
output [2 : 0] master1_arprot;
// value method master1_ar_arqos
output [3 : 0] master1_arqos;
// value method master1_ar_arregion
output [3 : 0] master1_arregion;
// value method master1_ar_aruser
// value method master1_ar_arvalid
output master1_arvalid;
// action method master1_ar_arready
input master1_arready;
// action method master1_r_rflit
input [3 : 0] master1_rid;
input [63 : 0] master1_rdata;
input [1 : 0] master1_rresp;
input master1_rlast;
input master1_ruser;
input master1_rvalid;
// value method master1_r_rready
output master1_rready;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method non_maskable_interrupt_req
input non_maskable_interrupt_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method debug_module_mem_server_aw_awflit
input [4 : 0] debug_module_mem_server_awid;
input [63 : 0] debug_module_mem_server_awaddr;
input [7 : 0] debug_module_mem_server_awlen;
input [2 : 0] debug_module_mem_server_awsize;
input [1 : 0] debug_module_mem_server_awburst;
input debug_module_mem_server_awlock;
input [3 : 0] debug_module_mem_server_awcache;
input [2 : 0] debug_module_mem_server_awprot;
input [3 : 0] debug_module_mem_server_awqos;
input [3 : 0] debug_module_mem_server_awregion;
input debug_module_mem_server_awvalid;
// value method debug_module_mem_server_aw_awready
output debug_module_mem_server_awready;
// action method debug_module_mem_server_w_wflit
input [63 : 0] debug_module_mem_server_wdata;
input [7 : 0] debug_module_mem_server_wstrb;
input debug_module_mem_server_wlast;
input debug_module_mem_server_wuser;
input debug_module_mem_server_wvalid;
// value method debug_module_mem_server_w_wready
output debug_module_mem_server_wready;
// value method debug_module_mem_server_b_bid
output [4 : 0] debug_module_mem_server_bid;
// value method debug_module_mem_server_b_bresp
output [1 : 0] debug_module_mem_server_bresp;
// value method debug_module_mem_server_b_buser
// value method debug_module_mem_server_b_bvalid
output debug_module_mem_server_bvalid;
// action method debug_module_mem_server_b_bready
input debug_module_mem_server_bready;
// action method debug_module_mem_server_ar_arflit
input [4 : 0] debug_module_mem_server_arid;
input [63 : 0] debug_module_mem_server_araddr;
input [7 : 0] debug_module_mem_server_arlen;
input [2 : 0] debug_module_mem_server_arsize;
input [1 : 0] debug_module_mem_server_arburst;
input debug_module_mem_server_arlock;
input [3 : 0] debug_module_mem_server_arcache;
input [2 : 0] debug_module_mem_server_arprot;
input [3 : 0] debug_module_mem_server_arqos;
input [3 : 0] debug_module_mem_server_arregion;
input debug_module_mem_server_arvalid;
// value method debug_module_mem_server_ar_arready
output debug_module_mem_server_arready;
// value method debug_module_mem_server_r_rid
output [4 : 0] debug_module_mem_server_rid;
// value method debug_module_mem_server_r_rdata
output [63 : 0] debug_module_mem_server_rdata;
// value method debug_module_mem_server_r_rresp
output [1 : 0] debug_module_mem_server_rresp;
// value method debug_module_mem_server_r_rlast
output debug_module_mem_server_rlast;
// value method debug_module_mem_server_r_ruser
output debug_module_mem_server_ruser;
// value method debug_module_mem_server_r_rvalid
output debug_module_mem_server_rvalid;
// action method debug_module_mem_server_r_rready
input debug_module_mem_server_rready;
// action method hart0_run_halt_server_request_put
input hart0_run_halt_server_request_put;
input EN_hart0_run_halt_server_request_put;
output RDY_hart0_run_halt_server_request_put;
// actionvalue method hart0_run_halt_server_response_get
input EN_hart0_run_halt_server_response_get;
output hart0_run_halt_server_response_get;
output RDY_hart0_run_halt_server_response_get;
// action method hart0_gpr_mem_server_request_put
input [69 : 0] hart0_gpr_mem_server_request_put;
input EN_hart0_gpr_mem_server_request_put;
output RDY_hart0_gpr_mem_server_request_put;
// actionvalue method hart0_gpr_mem_server_response_get
input EN_hart0_gpr_mem_server_response_get;
output [64 : 0] hart0_gpr_mem_server_response_get;
output RDY_hart0_gpr_mem_server_response_get;
// action method hart0_fpr_mem_server_request_put
input [69 : 0] hart0_fpr_mem_server_request_put;
input EN_hart0_fpr_mem_server_request_put;
output RDY_hart0_fpr_mem_server_request_put;
// actionvalue method hart0_fpr_mem_server_response_get
input EN_hart0_fpr_mem_server_response_get;
output [64 : 0] hart0_fpr_mem_server_response_get;
output RDY_hart0_fpr_mem_server_response_get;
// action method hart0_csr_mem_server_request_put
input [76 : 0] hart0_csr_mem_server_request_put;
input EN_hart0_csr_mem_server_request_put;
output RDY_hart0_csr_mem_server_request_put;
// actionvalue method hart0_csr_mem_server_response_get
input EN_hart0_csr_mem_server_response_get;
output [64 : 0] hart0_csr_mem_server_response_get;
output RDY_hart0_csr_mem_server_response_get;
// action method hart0_put_other_req_put
input [3 : 0] hart0_put_other_req_put;
input EN_hart0_put_other_req_put;
output RDY_hart0_put_other_req_put;
// signals for module outputs
wire [64 : 0] hart0_csr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
hart0_gpr_mem_server_response_get;
wire [63 : 0] debug_module_mem_server_rdata,
master0_araddr,
master0_awaddr,
master0_wdata,
master1_araddr,
master1_awaddr,
master1_wdata;
wire [7 : 0] master0_arlen,
master0_awlen,
master0_wstrb,
master1_arlen,
master1_awlen,
master1_wstrb;
wire [4 : 0] debug_module_mem_server_bid,
debug_module_mem_server_rid,
master0_arid,
master0_awid;
wire [3 : 0] master0_arcache,
master0_arqos,
master0_arregion,
master0_awcache,
master0_awqos,
master0_awregion,
master1_arcache,
master1_arid,
master1_arqos,
master1_arregion,
master1_awcache,
master1_awid,
master1_awqos,
master1_awregion;
wire [2 : 0] master0_arprot,
master0_arsize,
master0_awprot,
master0_awsize,
master1_arprot,
master1_arsize,
master1_awprot,
master1_awsize;
wire [1 : 0] debug_module_mem_server_bresp,
debug_module_mem_server_rresp,
master0_arburst,
master0_awburst,
master1_arburst,
master1_awburst;
wire RDY_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_response_get,
RDY_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_response_get,
RDY_hart0_put_other_req_put,
RDY_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_response_get,
RDY_set_verbosity,
RDY_start,
debug_module_mem_server_arready,
debug_module_mem_server_awready,
debug_module_mem_server_bvalid,
debug_module_mem_server_rlast,
debug_module_mem_server_ruser,
debug_module_mem_server_rvalid,
debug_module_mem_server_wready,
hart0_run_halt_server_response_get,
master0_arlock,
master0_arvalid,
master0_awlock,
master0_awvalid,
master0_bready,
master0_rready,
master0_wlast,
master0_wuser,
master0_wvalid,
master1_arlock,
master1_arvalid,
master1_awlock,
master1_awvalid,
master1_bready,
master1_rready,
master1_wlast,
master1_wuser,
master1_wvalid;
// inlined wires
wire [584 : 0] enqDst_1_0_lat_0$wget;
wire [583 : 0] propDstData_1_0_lat_0$wget, propDstData_1_1_lat_0$wget;
wire [98 : 0] llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1,
llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read,
llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read,
llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read,
llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1,
llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read,
llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read,
llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read,
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1,
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read,
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read,
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port3__read,
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1,
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read,
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read,
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read;
wire [97 : 0] llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget,
llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget,
mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1,
mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read,
mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read,
mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read,
mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1,
mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read,
mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read,
mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read;
wire [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1,
llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read,
llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read,
llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read,
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1,
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read,
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read,
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read,
mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1,
mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read,
mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read,
mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read;
wire [73 : 0] enqDst_0_lat_0$wget,
llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1,
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read,
llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read,
llc_axi4_adapter_master_xactor_shim_rff_rv$port3__read,
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1,
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read,
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read,
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read,
llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget;
wire [72 : 0] llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget,
mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1,
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read,
mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read,
mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read,
propDstData_0_lat_0$wget,
propDstData_1_lat_0$wget;
wire [71 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget;
wire [65 : 0] llc_mem_server_enqDst_0_lat_0$wget;
wire [64 : 0] mmioPlatform_toHostQ_enqReq_lat_0$wget;
wire [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1,
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read,
llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read,
llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read,
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read,
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read,
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read;
wire [6 : 0] llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget,
mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1,
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read,
mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read,
mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read;
wire [5 : 0] mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget;
wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read;
wire enqDst_0_lat_0$whas,
enqDst_1_0_lat_0$whas,
llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write,
llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write,
llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas,
llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas,
llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas,
llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas,
llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas,
llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas,
llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas,
llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas,
llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas,
llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas,
llc_mem_server_propDstIdx_0_lat_1$whas,
mmioPlatform_fromHostQ_deqReq_lat_0$whas,
mmioPlatform_toHostQ_enqReq_lat_0$whas,
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write,
mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write,
mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write,
mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write,
mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas,
mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas,
mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas,
mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas,
mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas,
propDstIdx_1_1_lat_1$whas,
propDstIdx_1_lat_1$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register enqDst_0_rl
reg [73 : 0] enqDst_0_rl;
wire [73 : 0] enqDst_0_rl$D_IN;
wire enqDst_0_rl$EN;
// register enqDst_1_0_rl
reg [584 : 0] enqDst_1_0_rl;
wire [584 : 0] enqDst_1_0_rl$D_IN;
wire enqDst_1_0_rl$EN;
// register llc_axi4_adapter_cfg_verbosity
reg [3 : 0] llc_axi4_adapter_cfg_verbosity;
wire [3 : 0] llc_axi4_adapter_cfg_verbosity$D_IN;
wire llc_axi4_adapter_cfg_verbosity$EN;
// register llc_axi4_adapter_ctr_wr_rsps_pending_crg
reg [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg;
wire [3 : 0] llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
wire llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN;
// register llc_axi4_adapter_master_xactor_clearing
reg llc_axi4_adapter_master_xactor_clearing;
wire llc_axi4_adapter_master_xactor_clearing$D_IN,
llc_axi4_adapter_master_xactor_clearing$EN;
// register llc_axi4_adapter_master_xactor_shim_arff_rv
reg [98 : 0] llc_axi4_adapter_master_xactor_shim_arff_rv;
wire [98 : 0] llc_axi4_adapter_master_xactor_shim_arff_rv$D_IN;
wire llc_axi4_adapter_master_xactor_shim_arff_rv$EN;
// register llc_axi4_adapter_master_xactor_shim_awff_rv
reg [98 : 0] llc_axi4_adapter_master_xactor_shim_awff_rv;
wire [98 : 0] llc_axi4_adapter_master_xactor_shim_awff_rv$D_IN;
wire llc_axi4_adapter_master_xactor_shim_awff_rv$EN;
// register llc_axi4_adapter_master_xactor_shim_bff_rv
reg [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv;
wire [7 : 0] llc_axi4_adapter_master_xactor_shim_bff_rv$D_IN;
wire llc_axi4_adapter_master_xactor_shim_bff_rv$EN;
// register llc_axi4_adapter_master_xactor_shim_rff_rv
reg [73 : 0] llc_axi4_adapter_master_xactor_shim_rff_rv;
wire [73 : 0] llc_axi4_adapter_master_xactor_shim_rff_rv$D_IN;
wire llc_axi4_adapter_master_xactor_shim_rff_rv$EN;
// register llc_axi4_adapter_master_xactor_shim_wff_rv
reg [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv;
wire [74 : 0] llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN;
wire llc_axi4_adapter_master_xactor_shim_wff_rv$EN;
// register llc_axi4_adapter_rg_cline
reg [515 : 0] llc_axi4_adapter_rg_cline;
wire [515 : 0] llc_axi4_adapter_rg_cline$D_IN;
wire llc_axi4_adapter_rg_cline$EN;
// register llc_axi4_adapter_rg_rd_req_beat
reg [2 : 0] llc_axi4_adapter_rg_rd_req_beat;
wire [2 : 0] llc_axi4_adapter_rg_rd_req_beat$D_IN;
wire llc_axi4_adapter_rg_rd_req_beat$EN;
// register llc_axi4_adapter_rg_rd_rsp_beat
reg [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat;
wire [2 : 0] llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
wire llc_axi4_adapter_rg_rd_rsp_beat$EN;
// register llc_axi4_adapter_rg_wr_req_beat
reg [2 : 0] llc_axi4_adapter_rg_wr_req_beat;
wire [2 : 0] llc_axi4_adapter_rg_wr_req_beat$D_IN;
wire llc_axi4_adapter_rg_wr_req_beat$EN;
// register llc_mem_server_axi4_slave_xactor_clearing
reg llc_mem_server_axi4_slave_xactor_clearing;
wire llc_mem_server_axi4_slave_xactor_clearing$D_IN,
llc_mem_server_axi4_slave_xactor_clearing$EN;
// register llc_mem_server_axi4_slave_xactor_shim_arff_rv
reg [98 : 0] llc_mem_server_axi4_slave_xactor_shim_arff_rv;
wire [98 : 0] llc_mem_server_axi4_slave_xactor_shim_arff_rv$D_IN;
wire llc_mem_server_axi4_slave_xactor_shim_arff_rv$EN;
// register llc_mem_server_axi4_slave_xactor_shim_awff_rv
reg [98 : 0] llc_mem_server_axi4_slave_xactor_shim_awff_rv;
wire [98 : 0] llc_mem_server_axi4_slave_xactor_shim_awff_rv$D_IN;
wire llc_mem_server_axi4_slave_xactor_shim_awff_rv$EN;
// register llc_mem_server_axi4_slave_xactor_shim_bff_rv
reg [7 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rv;
wire [7 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rv$D_IN;
wire llc_mem_server_axi4_slave_xactor_shim_bff_rv$EN;
// register llc_mem_server_axi4_slave_xactor_shim_rff_rv
reg [73 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rv;
wire [73 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rv$D_IN;
wire llc_mem_server_axi4_slave_xactor_shim_rff_rv$EN;
// register llc_mem_server_axi4_slave_xactor_shim_wff_rv
reg [74 : 0] llc_mem_server_axi4_slave_xactor_shim_wff_rv;
wire [74 : 0] llc_mem_server_axi4_slave_xactor_shim_wff_rv$D_IN;
wire llc_mem_server_axi4_slave_xactor_shim_wff_rv$EN;
// register llc_mem_server_enqDst_0_rl
reg [65 : 0] llc_mem_server_enqDst_0_rl;
wire [65 : 0] llc_mem_server_enqDst_0_rl$D_IN;
wire llc_mem_server_enqDst_0_rl$EN;
// register llc_mem_server_propDstData_0_rl
reg [64 : 0] llc_mem_server_propDstData_0_rl;
wire [64 : 0] llc_mem_server_propDstData_0_rl$D_IN;
wire llc_mem_server_propDstData_0_rl$EN;
// register llc_mem_server_propDstIdx_0_rl
reg llc_mem_server_propDstIdx_0_rl;
wire llc_mem_server_propDstIdx_0_rl$D_IN, llc_mem_server_propDstIdx_0_rl$EN;
// register llc_mem_server_rg_cacheline_cache_addr
reg [63 : 0] llc_mem_server_rg_cacheline_cache_addr;
wire [63 : 0] llc_mem_server_rg_cacheline_cache_addr$D_IN;
wire llc_mem_server_rg_cacheline_cache_addr$EN;
// register llc_mem_server_rg_cacheline_cache_data
reg [515 : 0] llc_mem_server_rg_cacheline_cache_data;
wire [515 : 0] llc_mem_server_rg_cacheline_cache_data$D_IN;
wire llc_mem_server_rg_cacheline_cache_data$EN;
// register llc_mem_server_rg_cacheline_cache_dirty_delay
reg [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay;
wire [9 : 0] llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN;
wire llc_mem_server_rg_cacheline_cache_dirty_delay$EN;
// register llc_mem_server_rg_cacheline_cache_state
reg [2 : 0] llc_mem_server_rg_cacheline_cache_state;
reg [2 : 0] llc_mem_server_rg_cacheline_cache_state$D_IN;
wire llc_mem_server_rg_cacheline_cache_state$EN;
// register mmioPlatform_amoResp
reg [128 : 0] mmioPlatform_amoResp;
wire [128 : 0] mmioPlatform_amoResp$D_IN;
wire mmioPlatform_amoResp$EN;
// register mmioPlatform_curReq
reg [66 : 0] mmioPlatform_curReq;
wire [66 : 0] mmioPlatform_curReq$D_IN;
wire mmioPlatform_curReq$EN;
// register mmioPlatform_cycle
reg [6 : 0] mmioPlatform_cycle;
wire [6 : 0] mmioPlatform_cycle$D_IN;
wire mmioPlatform_cycle$EN;
// register mmioPlatform_fetchedInsts_0
reg [31 : 0] mmioPlatform_fetchedInsts_0;
wire [31 : 0] mmioPlatform_fetchedInsts_0$D_IN;
wire mmioPlatform_fetchedInsts_0$EN;
// register mmioPlatform_fetchingWay
reg mmioPlatform_fetchingWay;
wire mmioPlatform_fetchingWay$D_IN, mmioPlatform_fetchingWay$EN;
// register mmioPlatform_fromHostAddr
reg [60 : 0] mmioPlatform_fromHostAddr;
wire [60 : 0] mmioPlatform_fromHostAddr$D_IN;
wire mmioPlatform_fromHostAddr$EN;
// register mmioPlatform_fromHostQ_clearReq_rl
reg mmioPlatform_fromHostQ_clearReq_rl;
wire mmioPlatform_fromHostQ_clearReq_rl$D_IN,
mmioPlatform_fromHostQ_clearReq_rl$EN;
// register mmioPlatform_fromHostQ_data_0
reg [63 : 0] mmioPlatform_fromHostQ_data_0;
wire [63 : 0] mmioPlatform_fromHostQ_data_0$D_IN;
wire mmioPlatform_fromHostQ_data_0$EN;
// register mmioPlatform_fromHostQ_deqReq_rl
reg mmioPlatform_fromHostQ_deqReq_rl;
wire mmioPlatform_fromHostQ_deqReq_rl$D_IN,
mmioPlatform_fromHostQ_deqReq_rl$EN;
// register mmioPlatform_fromHostQ_empty
reg mmioPlatform_fromHostQ_empty;
wire mmioPlatform_fromHostQ_empty$D_IN, mmioPlatform_fromHostQ_empty$EN;
// register mmioPlatform_fromHostQ_enqReq_rl
reg [64 : 0] mmioPlatform_fromHostQ_enqReq_rl;
wire [64 : 0] mmioPlatform_fromHostQ_enqReq_rl$D_IN;
wire mmioPlatform_fromHostQ_enqReq_rl$EN;
// register mmioPlatform_fromHostQ_full
reg mmioPlatform_fromHostQ_full;
wire mmioPlatform_fromHostQ_full$D_IN, mmioPlatform_fromHostQ_full$EN;
// register mmioPlatform_instSel
reg [1 : 0] mmioPlatform_instSel;
wire [1 : 0] mmioPlatform_instSel$D_IN;
wire mmioPlatform_instSel$EN;
// register mmioPlatform_mtime
reg [63 : 0] mmioPlatform_mtime;
wire [63 : 0] mmioPlatform_mtime$D_IN;
wire mmioPlatform_mtime$EN;
// register mmioPlatform_mtimecmp_0
reg [63 : 0] mmioPlatform_mtimecmp_0;
wire [63 : 0] mmioPlatform_mtimecmp_0$D_IN;
wire mmioPlatform_mtimecmp_0$EN;
// register mmioPlatform_mtip_0
reg mmioPlatform_mtip_0;
wire mmioPlatform_mtip_0$D_IN, mmioPlatform_mtip_0$EN;
// register mmioPlatform_reqAmofunc
reg [3 : 0] mmioPlatform_reqAmofunc;
wire [3 : 0] mmioPlatform_reqAmofunc$D_IN;
wire mmioPlatform_reqAmofunc$EN;
// register mmioPlatform_reqBE
reg [15 : 0] mmioPlatform_reqBE;
wire [15 : 0] mmioPlatform_reqBE$D_IN;
wire mmioPlatform_reqBE$EN;
// register mmioPlatform_reqData
reg [128 : 0] mmioPlatform_reqData;
wire [128 : 0] mmioPlatform_reqData$D_IN;
wire mmioPlatform_reqData$EN;
// register mmioPlatform_reqFunc
reg [5 : 0] mmioPlatform_reqFunc;
reg [5 : 0] mmioPlatform_reqFunc$D_IN;
wire mmioPlatform_reqFunc$EN;
// register mmioPlatform_reqSz
reg [1 : 0] mmioPlatform_reqSz;
wire [1 : 0] mmioPlatform_reqSz$D_IN;
wire mmioPlatform_reqSz$EN;
// register mmioPlatform_state
reg [1 : 0] mmioPlatform_state;
reg [1 : 0] mmioPlatform_state$D_IN;
wire mmioPlatform_state$EN;
// register mmioPlatform_toHostAddr
reg [60 : 0] mmioPlatform_toHostAddr;
wire [60 : 0] mmioPlatform_toHostAddr$D_IN;
wire mmioPlatform_toHostAddr$EN;
// register mmioPlatform_toHostQ_clearReq_rl
reg mmioPlatform_toHostQ_clearReq_rl;
wire mmioPlatform_toHostQ_clearReq_rl$D_IN,
mmioPlatform_toHostQ_clearReq_rl$EN;
// register mmioPlatform_toHostQ_data_0
reg [63 : 0] mmioPlatform_toHostQ_data_0;
wire [63 : 0] mmioPlatform_toHostQ_data_0$D_IN;
wire mmioPlatform_toHostQ_data_0$EN;
// register mmioPlatform_toHostQ_deqReq_rl
reg mmioPlatform_toHostQ_deqReq_rl;
wire mmioPlatform_toHostQ_deqReq_rl$D_IN, mmioPlatform_toHostQ_deqReq_rl$EN;
// register mmioPlatform_toHostQ_empty
reg mmioPlatform_toHostQ_empty;
wire mmioPlatform_toHostQ_empty$D_IN, mmioPlatform_toHostQ_empty$EN;
// register mmioPlatform_toHostQ_enqReq_rl
reg [64 : 0] mmioPlatform_toHostQ_enqReq_rl;
wire [64 : 0] mmioPlatform_toHostQ_enqReq_rl$D_IN;
wire mmioPlatform_toHostQ_enqReq_rl$EN;
// register mmioPlatform_toHostQ_full
reg mmioPlatform_toHostQ_full;
wire mmioPlatform_toHostQ_full$D_IN, mmioPlatform_toHostQ_full$EN;
// register mmioPlatform_waitLowerMSIPCRs
reg mmioPlatform_waitLowerMSIPCRs;
wire mmioPlatform_waitLowerMSIPCRs$D_IN, mmioPlatform_waitLowerMSIPCRs$EN;
// register mmioPlatform_waitMTIPCRs
reg mmioPlatform_waitMTIPCRs;
wire mmioPlatform_waitMTIPCRs$D_IN, mmioPlatform_waitMTIPCRs$EN;
// register mmioPlatform_waitUpperMSIPCRs
reg mmioPlatform_waitUpperMSIPCRs;
wire mmioPlatform_waitUpperMSIPCRs$D_IN, mmioPlatform_waitUpperMSIPCRs$EN;
// register mmio_axi4_adapter_cfg_verbosity
reg [3 : 0] mmio_axi4_adapter_cfg_verbosity;
wire [3 : 0] mmio_axi4_adapter_cfg_verbosity$D_IN;
wire mmio_axi4_adapter_cfg_verbosity$EN;
// register mmio_axi4_adapter_ctr_wr_rsps_pending_crg
reg [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg;
wire [3 : 0] mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
wire mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN;
// register mmio_axi4_adapter_master_xactor_clearing
reg mmio_axi4_adapter_master_xactor_clearing;
wire mmio_axi4_adapter_master_xactor_clearing$D_IN,
mmio_axi4_adapter_master_xactor_clearing$EN;
// register mmio_axi4_adapter_master_xactor_shim_arff_rv
reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv;
wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN;
wire mmio_axi4_adapter_master_xactor_shim_arff_rv$EN;
// register mmio_axi4_adapter_master_xactor_shim_awff_rv
reg [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv;
wire [97 : 0] mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN;
wire mmio_axi4_adapter_master_xactor_shim_awff_rv$EN;
// register mmio_axi4_adapter_master_xactor_shim_bff_rv
reg [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv;
wire [6 : 0] mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN;
wire mmio_axi4_adapter_master_xactor_shim_bff_rv$EN;
// register mmio_axi4_adapter_master_xactor_shim_rff_rv
reg [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv;
wire [72 : 0] mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN;
wire mmio_axi4_adapter_master_xactor_shim_rff_rv$EN;
// register mmio_axi4_adapter_master_xactor_shim_wff_rv
reg [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv;
wire [74 : 0] mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN;
wire mmio_axi4_adapter_master_xactor_shim_wff_rv$EN;
// register mmio_axi4_adapter_read_req_addr
reg [63 : 0] mmio_axi4_adapter_read_req_addr;
wire [63 : 0] mmio_axi4_adapter_read_req_addr$D_IN;
wire mmio_axi4_adapter_read_req_addr$EN;
// register propDstData_0_rl
reg [72 : 0] propDstData_0_rl;
wire [72 : 0] propDstData_0_rl$D_IN;
wire propDstData_0_rl$EN;
// register propDstData_1_0_rl
reg [583 : 0] propDstData_1_0_rl;
wire [583 : 0] propDstData_1_0_rl$D_IN;
wire propDstData_1_0_rl$EN;
// register propDstData_1_1_rl
reg [583 : 0] propDstData_1_1_rl;
wire [583 : 0] propDstData_1_1_rl$D_IN;
wire propDstData_1_1_rl$EN;
// register propDstData_1_rl
reg [72 : 0] propDstData_1_rl;
wire [72 : 0] propDstData_1_rl$D_IN;
wire propDstData_1_rl$EN;
// register propDstIdx_0_rl
reg propDstIdx_0_rl;
wire propDstIdx_0_rl$D_IN, propDstIdx_0_rl$EN;
// register propDstIdx_1_0_rl
reg propDstIdx_1_0_rl;
wire propDstIdx_1_0_rl$D_IN, propDstIdx_1_0_rl$EN;
// register propDstIdx_1_1_rl
reg propDstIdx_1_1_rl;
wire propDstIdx_1_1_rl$D_IN, propDstIdx_1_1_rl$EN;
// register propDstIdx_1_rl
reg propDstIdx_1_rl;
wire propDstIdx_1_rl$D_IN, propDstIdx_1_rl$EN;
// register srcRR_0
reg srcRR_0;
wire srcRR_0$D_IN, srcRR_0$EN;
// register srcRR_1_0
reg srcRR_1_0;
wire srcRR_1_0$D_IN, srcRR_1_0$EN;
// ports of submodule core_0
reg [130 : 0] core_0$mmioToPlatform_pRs_enq_x;
reg [38 : 0] core_0$mmioToPlatform_pRq_enq_x;
wire [586 : 0] core_0$dCacheToParent_fromP_enq_x,
core_0$iCacheToParent_fromP_enq_x;
wire [582 : 0] core_0$dCacheToParent_rsToP_first,
core_0$iCacheToParent_rsToP_first;
wire [214 : 0] core_0$mmioToPlatform_cRq_first;
wire [76 : 0] core_0$hart0_csr_mem_server_request_put;
wire [71 : 0] core_0$dCacheToParent_rqToP_first,
core_0$iCacheToParent_rqToP_first;
wire [69 : 0] core_0$hart0_fpr_mem_server_request_put,
core_0$hart0_gpr_mem_server_request_put;
wire [64 : 0] core_0$hart0_csr_mem_server_response_get,
core_0$hart0_fpr_mem_server_response_get,
core_0$hart0_gpr_mem_server_response_get,
core_0$tlbToMem_memReq_first,
core_0$tlbToMem_respLd_enq_x;
wire [63 : 0] core_0$coreReq_start_fromHostAddr,
core_0$coreReq_start_startpc,
core_0$coreReq_start_toHostAddr,
core_0$mmioToPlatform_setTime_t;
wire [4 : 0] core_0$coreReq_perfReq_t;
wire [3 : 0] core_0$coreReq_perfReq_loc;
wire core_0$EN_coreIndInv_perfResp,
core_0$EN_coreIndInv_terminate,
core_0$EN_coreReq_perfReq,
core_0$EN_coreReq_start,
core_0$EN_dCacheToParent_fromP_enq,
core_0$EN_dCacheToParent_rqToP_deq,
core_0$EN_dCacheToParent_rsToP_deq,
core_0$EN_deadlock_checkStarted_get,
core_0$EN_deadlock_commitInstStuck_get,
core_0$EN_deadlock_commitUserInstStuck_get,
core_0$EN_deadlock_dCacheCRqStuck_get,
core_0$EN_deadlock_dCachePRqStuck_get,
core_0$EN_deadlock_iCacheCRqStuck_get,
core_0$EN_deadlock_iCachePRqStuck_get,
core_0$EN_deadlock_renameCorrectPathStuck_get,
core_0$EN_deadlock_renameInstStuck_get,
core_0$EN_hart0_csr_mem_server_request_put,
core_0$EN_hart0_csr_mem_server_response_get,
core_0$EN_hart0_fpr_mem_server_request_put,
core_0$EN_hart0_fpr_mem_server_response_get,
core_0$EN_hart0_gpr_mem_server_request_put,
core_0$EN_hart0_gpr_mem_server_response_get,
core_0$EN_hart0_run_halt_server_request_put,
core_0$EN_hart0_run_halt_server_response_get,
core_0$EN_iCacheToParent_fromP_enq,
core_0$EN_iCacheToParent_rqToP_deq,
core_0$EN_iCacheToParent_rsToP_deq,
core_0$EN_mmioToPlatform_cRq_deq,
core_0$EN_mmioToPlatform_cRs_deq,
core_0$EN_mmioToPlatform_pRq_enq,
core_0$EN_mmioToPlatform_pRs_enq,
core_0$EN_mmioToPlatform_setTime,
core_0$EN_recvDoStats,
core_0$EN_renameDebug_renameErr_get,
core_0$EN_sendDoStats,
core_0$EN_setMEIP,
core_0$EN_setSEIP,
core_0$EN_tlbToMem_memReq_deq,
core_0$EN_tlbToMem_respLd_enq,
core_0$RDY_coreIndInv_terminate,
core_0$RDY_dCacheToParent_fromP_enq,
core_0$RDY_dCacheToParent_rqToP_deq,
core_0$RDY_dCacheToParent_rqToP_first,
core_0$RDY_dCacheToParent_rsToP_deq,
core_0$RDY_dCacheToParent_rsToP_first,
core_0$RDY_deadlock_checkStarted_get,
core_0$RDY_deadlock_commitInstStuck_get,
core_0$RDY_deadlock_commitUserInstStuck_get,
core_0$RDY_deadlock_dCacheCRqStuck_get,
core_0$RDY_deadlock_dCachePRqStuck_get,
core_0$RDY_deadlock_iCacheCRqStuck_get,
core_0$RDY_deadlock_iCachePRqStuck_get,
core_0$RDY_deadlock_renameCorrectPathStuck_get,
core_0$RDY_deadlock_renameInstStuck_get,
core_0$RDY_hart0_csr_mem_server_request_put,
core_0$RDY_hart0_csr_mem_server_response_get,
core_0$RDY_hart0_fpr_mem_server_request_put,
core_0$RDY_hart0_fpr_mem_server_response_get,
core_0$RDY_hart0_gpr_mem_server_request_put,
core_0$RDY_hart0_gpr_mem_server_response_get,
core_0$RDY_hart0_run_halt_server_request_put,
core_0$RDY_hart0_run_halt_server_response_get,
core_0$RDY_iCacheToParent_fromP_enq,
core_0$RDY_iCacheToParent_rqToP_deq,
core_0$RDY_iCacheToParent_rqToP_first,
core_0$RDY_iCacheToParent_rsToP_deq,
core_0$RDY_iCacheToParent_rsToP_first,
core_0$RDY_mmioToPlatform_cRq_deq,
core_0$RDY_mmioToPlatform_cRq_first,
core_0$RDY_mmioToPlatform_cRs_deq,
core_0$RDY_mmioToPlatform_cRs_first,
core_0$RDY_mmioToPlatform_pRq_enq,
core_0$RDY_mmioToPlatform_pRs_enq,
core_0$RDY_renameDebug_renameErr_get,
core_0$RDY_sendDoStats,
core_0$RDY_tlbToMem_memReq_deq,
core_0$RDY_tlbToMem_memReq_first,
core_0$RDY_tlbToMem_respLd_enq,
core_0$hart0_run_halt_server_request_put,
core_0$hart0_run_halt_server_response_get,
core_0$mmioToPlatform_cRq_notEmpty,
core_0$mmioToPlatform_cRs_first,
core_0$recvDoStats_x,
core_0$sendDoStats,
core_0$setMEIP_v,
core_0$setSEIP_v;
// ports of submodule llc
reg [648 : 0] llc$dma_memReq_enq_x;
wire [644 : 0] llc$to_mem_toM_first;
wire [587 : 0] llc$to_child_toC_first;
wire [583 : 0] llc$to_child_rsFromC_enq_x;
wire [520 : 0] llc$dma_respLd_first, llc$to_mem_rsFromM_enq_x;
wire [72 : 0] llc$to_child_rqFromC_enq_x;
wire [4 : 0] llc$dma_respSt_first;
wire [3 : 0] llc$perf_req_r;
wire llc$EN_cRqStuck_get,
llc$EN_dma_memReq_enq,
llc$EN_dma_respLd_deq,
llc$EN_dma_respSt_deq,
llc$EN_perf_req,
llc$EN_perf_resp,
llc$EN_perf_setStatus,
llc$EN_to_child_rqFromC_enq,
llc$EN_to_child_rsFromC_enq,
llc$EN_to_child_toC_deq,
llc$EN_to_mem_rsFromM_enq,
llc$EN_to_mem_toM_deq,
llc$RDY_dma_memReq_enq,
llc$RDY_dma_respLd_deq,
llc$RDY_dma_respLd_first,
llc$RDY_dma_respSt_deq,
llc$RDY_dma_respSt_first,
llc$RDY_to_child_rqFromC_enq,
llc$RDY_to_child_rsFromC_enq,
llc$RDY_to_child_toC_deq,
llc$RDY_to_child_toC_first,
llc$RDY_to_mem_rsFromM_enq,
llc$RDY_to_mem_toM_deq,
llc$RDY_to_mem_toM_first,
llc$perf_setStatus_doStats;
// ports of submodule llc_axi4_adapter_f_pending_reads
wire [68 : 0] llc_axi4_adapter_f_pending_reads$D_IN,
llc_axi4_adapter_f_pending_reads$D_OUT;
wire llc_axi4_adapter_f_pending_reads$CLR,
llc_axi4_adapter_f_pending_reads$DEQ,
llc_axi4_adapter_f_pending_reads$EMPTY_N,
llc_axi4_adapter_f_pending_reads$ENQ,
llc_axi4_adapter_f_pending_reads$FULL_N;
// ports of submodule llc_mem_server_f_dword_in_line
wire [2 : 0] llc_mem_server_f_dword_in_line$D_IN;
wire llc_mem_server_f_dword_in_line$CLR,
llc_mem_server_f_dword_in_line$DEQ,
llc_mem_server_f_dword_in_line$ENQ;
// ports of submodule llc_mem_server_tlbQ
wire [64 : 0] llc_mem_server_tlbQ$D_IN, llc_mem_server_tlbQ$D_OUT;
wire llc_mem_server_tlbQ$CLR,
llc_mem_server_tlbQ$DEQ,
llc_mem_server_tlbQ$EMPTY_N,
llc_mem_server_tlbQ$ENQ,
llc_mem_server_tlbQ$FULL_N;
// ports of submodule mmio_axi4_adapter_f_reqs_from_core
reg [214 : 0] mmio_axi4_adapter_f_reqs_from_core$D_IN;
wire [214 : 0] mmio_axi4_adapter_f_reqs_from_core$D_OUT;
wire mmio_axi4_adapter_f_reqs_from_core$CLR,
mmio_axi4_adapter_f_reqs_from_core$DEQ,
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N,
mmio_axi4_adapter_f_reqs_from_core$ENQ,
mmio_axi4_adapter_f_reqs_from_core$FULL_N;
// ports of submodule mmio_axi4_adapter_f_rsps_to_core
reg [129 : 0] mmio_axi4_adapter_f_rsps_to_core$D_IN;
wire [129 : 0] mmio_axi4_adapter_f_rsps_to_core$D_OUT;
wire mmio_axi4_adapter_f_rsps_to_core$CLR,
mmio_axi4_adapter_f_rsps_to_core$DEQ,
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N,
mmio_axi4_adapter_f_rsps_to_core$ENQ,
mmio_axi4_adapter_f_rsps_to_core$FULL_N;
// ports of submodule mmio_axi4_adapter_soc_map
wire [63 : 0] mmio_axi4_adapter_soc_map$m_is_IO_addr_addr,
mmio_axi4_adapter_soc_map$m_is_mem_addr_addr,
mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr;
wire mmio_axi4_adapter_soc_map$m_is_IO_addr;
// rule scheduling signals
wire CAN_FIRE_RL_broadcastStats,
CAN_FIRE_RL_doEnq,
CAN_FIRE_RL_doEnq_1,
CAN_FIRE_RL_dstSelectSrc,
CAN_FIRE_RL_dstSelectSrc_1,
CAN_FIRE_RL_enqDst_0_canon,
CAN_FIRE_RL_enqDst_1_0_canon,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek,
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop,
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut,
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut,
CAN_FIRE_RL_llc_mem_server_doEnq,
CAN_FIRE_RL_llc_mem_server_dstSelectSrc,
CAN_FIRE_RL_llc_mem_server_enqDst_0_canon,
CAN_FIRE_RL_llc_mem_server_propDstData_0_canon,
CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss,
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss,
CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req,
CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req,
CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb,
CAN_FIRE_RL_llc_mem_server_sendStRespToTlb,
CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC,
CAN_FIRE_RL_llc_mem_server_srcPropose,
CAN_FIRE_RL_mmioPlatform_fromHostQ_canonicalize,
CAN_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon,
CAN_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon,
CAN_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon,
CAN_FIRE_RL_mmioPlatform_incCycle,
CAN_FIRE_RL_mmioPlatform_incTime,
CAN_FIRE_RL_mmioPlatform_processFromHost,
CAN_FIRE_RL_mmioPlatform_processMSIP,
CAN_FIRE_RL_mmioPlatform_processMTime,
CAN_FIRE_RL_mmioPlatform_processMTimeCmp,
CAN_FIRE_RL_mmioPlatform_processToHost,
CAN_FIRE_RL_mmioPlatform_propagateTime,
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp,
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp,
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp,
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req,
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req,
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req,
CAN_FIRE_RL_mmioPlatform_selectReq,
CAN_FIRE_RL_mmioPlatform_toHostQ_canonicalize,
CAN_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon,
CAN_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon,
CAN_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon,
CAN_FIRE_RL_mmioPlatform_waitMSIPDone,
CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone,
CAN_FIRE_RL_mmioPlatform_waitMTimeDone,
CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek,
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop,
CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps,
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req,
CAN_FIRE_RL_propDstData_0_canon,
CAN_FIRE_RL_propDstData_1_0_canon,
CAN_FIRE_RL_propDstData_1_1_canon,
CAN_FIRE_RL_propDstData_1_canon,
CAN_FIRE_RL_propDstIdx_0_canon,
CAN_FIRE_RL_propDstIdx_1_0_canon,
CAN_FIRE_RL_propDstIdx_1_1_canon,
CAN_FIRE_RL_propDstIdx_1_canon,
CAN_FIRE_RL_rl_dummy1,
CAN_FIRE_RL_rl_dummy2,
CAN_FIRE_RL_rl_dummy20,
CAN_FIRE_RL_rl_dummy3,
CAN_FIRE_RL_rl_dummy4,
CAN_FIRE_RL_rl_dummy5,
CAN_FIRE_RL_rl_dummy6,
CAN_FIRE_RL_rl_dummy7,
CAN_FIRE_RL_rl_dummy8,
CAN_FIRE_RL_rl_dummy9,
CAN_FIRE_RL_rl_terminate,
CAN_FIRE_RL_rl_tohost,
CAN_FIRE_RL_sendPRq,
CAN_FIRE_RL_sendPRq_1,
CAN_FIRE_RL_sendPRs,
CAN_FIRE_RL_sendPRs_1,
CAN_FIRE_RL_srcPropose,
CAN_FIRE_RL_srcPropose_1,
CAN_FIRE_RL_srcPropose_2,
CAN_FIRE_RL_srcPropose_3,
CAN_FIRE_debug_module_mem_server_ar_arflit,
CAN_FIRE_debug_module_mem_server_aw_awflit,
CAN_FIRE_debug_module_mem_server_b_bready,
CAN_FIRE_debug_module_mem_server_r_rready,
CAN_FIRE_debug_module_mem_server_w_wflit,
CAN_FIRE_hart0_csr_mem_server_request_put,
CAN_FIRE_hart0_csr_mem_server_response_get,
CAN_FIRE_hart0_fpr_mem_server_request_put,
CAN_FIRE_hart0_fpr_mem_server_response_get,
CAN_FIRE_hart0_gpr_mem_server_request_put,
CAN_FIRE_hart0_gpr_mem_server_response_get,
CAN_FIRE_hart0_put_other_req_put,
CAN_FIRE_hart0_run_halt_server_request_put,
CAN_FIRE_hart0_run_halt_server_response_get,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_master0_ar_arready,
CAN_FIRE_master0_aw_awready,
CAN_FIRE_master0_b_bflit,
CAN_FIRE_master0_r_rflit,
CAN_FIRE_master0_w_wready,
CAN_FIRE_master1_ar_arready,
CAN_FIRE_master1_aw_awready,
CAN_FIRE_master1_b_bflit,
CAN_FIRE_master1_r_rflit,
CAN_FIRE_master1_w_wready,
CAN_FIRE_non_maskable_interrupt_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_start,
WILL_FIRE_RL_broadcastStats,
WILL_FIRE_RL_doEnq,
WILL_FIRE_RL_doEnq_1,
WILL_FIRE_RL_dstSelectSrc,
WILL_FIRE_RL_dstSelectSrc_1,
WILL_FIRE_RL_enqDst_0_canon,
WILL_FIRE_RL_enqDst_1_0_canon,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek,
WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop,
WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps,
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut,
WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut,
WILL_FIRE_RL_llc_mem_server_doEnq,
WILL_FIRE_RL_llc_mem_server_dstSelectSrc,
WILL_FIRE_RL_llc_mem_server_enqDst_0_canon,
WILL_FIRE_RL_llc_mem_server_propDstData_0_canon,
WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss,
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss,
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req,
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req,
WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb,
WILL_FIRE_RL_llc_mem_server_sendStRespToTlb,
WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC,
WILL_FIRE_RL_llc_mem_server_srcPropose,
WILL_FIRE_RL_mmioPlatform_fromHostQ_canonicalize,
WILL_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon,
WILL_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon,
WILL_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon,
WILL_FIRE_RL_mmioPlatform_incCycle,
WILL_FIRE_RL_mmioPlatform_incTime,
WILL_FIRE_RL_mmioPlatform_processFromHost,
WILL_FIRE_RL_mmioPlatform_processMSIP,
WILL_FIRE_RL_mmioPlatform_processMTime,
WILL_FIRE_RL_mmioPlatform_processMTimeCmp,
WILL_FIRE_RL_mmioPlatform_processToHost,
WILL_FIRE_RL_mmioPlatform_propagateTime,
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp,
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp,
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp,
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req,
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req,
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req,
WILL_FIRE_RL_mmioPlatform_selectReq,
WILL_FIRE_RL_mmioPlatform_toHostQ_canonicalize,
WILL_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon,
WILL_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon,
WILL_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon,
WILL_FIRE_RL_mmioPlatform_waitMSIPDone,
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone,
WILL_FIRE_RL_mmioPlatform_waitMTimeDone,
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek,
WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop,
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps,
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req,
WILL_FIRE_RL_propDstData_0_canon,
WILL_FIRE_RL_propDstData_1_0_canon,
WILL_FIRE_RL_propDstData_1_1_canon,
WILL_FIRE_RL_propDstData_1_canon,
WILL_FIRE_RL_propDstIdx_0_canon,
WILL_FIRE_RL_propDstIdx_1_0_canon,
WILL_FIRE_RL_propDstIdx_1_1_canon,
WILL_FIRE_RL_propDstIdx_1_canon,
WILL_FIRE_RL_rl_dummy1,
WILL_FIRE_RL_rl_dummy2,
WILL_FIRE_RL_rl_dummy20,
WILL_FIRE_RL_rl_dummy3,
WILL_FIRE_RL_rl_dummy4,
WILL_FIRE_RL_rl_dummy5,
WILL_FIRE_RL_rl_dummy6,
WILL_FIRE_RL_rl_dummy7,
WILL_FIRE_RL_rl_dummy8,
WILL_FIRE_RL_rl_dummy9,
WILL_FIRE_RL_rl_terminate,
WILL_FIRE_RL_rl_tohost,
WILL_FIRE_RL_sendPRq,
WILL_FIRE_RL_sendPRq_1,
WILL_FIRE_RL_sendPRs,
WILL_FIRE_RL_sendPRs_1,
WILL_FIRE_RL_srcPropose,
WILL_FIRE_RL_srcPropose_1,
WILL_FIRE_RL_srcPropose_2,
WILL_FIRE_RL_srcPropose_3,
WILL_FIRE_debug_module_mem_server_ar_arflit,
WILL_FIRE_debug_module_mem_server_aw_awflit,
WILL_FIRE_debug_module_mem_server_b_bready,
WILL_FIRE_debug_module_mem_server_r_rready,
WILL_FIRE_debug_module_mem_server_w_wflit,
WILL_FIRE_hart0_csr_mem_server_request_put,
WILL_FIRE_hart0_csr_mem_server_response_get,
WILL_FIRE_hart0_fpr_mem_server_request_put,
WILL_FIRE_hart0_fpr_mem_server_response_get,
WILL_FIRE_hart0_gpr_mem_server_request_put,
WILL_FIRE_hart0_gpr_mem_server_response_get,
WILL_FIRE_hart0_put_other_req_put,
WILL_FIRE_hart0_run_halt_server_request_put,
WILL_FIRE_hart0_run_halt_server_response_get,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_master0_ar_arready,
WILL_FIRE_master0_aw_awready,
WILL_FIRE_master0_b_bflit,
WILL_FIRE_master0_r_rflit,
WILL_FIRE_master0_w_wready,
WILL_FIRE_master1_ar_arready,
WILL_FIRE_master1_aw_awready,
WILL_FIRE_master1_b_bflit,
WILL_FIRE_master1_r_rflit,
WILL_FIRE_master1_w_wready,
WILL_FIRE_non_maskable_interrupt_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_start;
// inputs to muxes for submodule ports
reg [1 : 0] MUX_mmioPlatform_state$write_1__VAL_3,
MUX_mmioPlatform_state$write_1__VAL_4;
wire [648 : 0] MUX_llc$dma_memReq_enq_1__VAL_1,
MUX_llc$dma_memReq_enq_1__VAL_2,
MUX_llc$dma_memReq_enq_1__VAL_3,
MUX_llc$dma_memReq_enq_1__VAL_4;
wire [586 : 0] MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1,
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2;
wire [515 : 0] MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1;
wire [214 : 0] MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4;
wire [130 : 0] MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8,
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9;
wire [129 : 0] MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1,
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3;
wire [128 : 0] MUX_mmioPlatform_amoResp$write_1__VAL_1,
MUX_mmioPlatform_amoResp$write_1__VAL_2;
wire [66 : 0] MUX_mmioPlatform_curReq$write_1__VAL_1,
MUX_mmioPlatform_curReq$write_1__VAL_2;
wire [63 : 0] MUX_mmioPlatform_mtime$write_1__VAL_2;
wire [38 : 0] MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2,
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3,
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4;
wire [9 : 0] MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2;
wire [6 : 0] MUX_mmioPlatform_cycle$write_1__VAL_1;
wire [1 : 0] MUX_mmioPlatform_instSel$write_1__VAL_2,
MUX_mmioPlatform_state$write_1__VAL_1,
MUX_mmioPlatform_state$write_1__VAL_2,
MUX_mmioPlatform_state$write_1__VAL_5;
wire MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1,
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2,
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3,
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4,
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5,
MUX_llc$dma_memReq_enq_1__SEL_1,
MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2,
MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3,
MUX_mmioPlatform_amoResp$write_1__SEL_1,
MUX_mmioPlatform_amoResp$write_1__SEL_2,
MUX_mmioPlatform_curReq$write_1__SEL_1,
MUX_mmioPlatform_fetchingWay$write_1__SEL_1,
MUX_mmioPlatform_fetchingWay$write_1__VAL_2,
MUX_mmioPlatform_mtip_0$write_1__VAL_2,
MUX_mmioPlatform_state$write_1__SEL_6,
MUX_mmioPlatform_state$write_1__SEL_7,
MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2,
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1,
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1,
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1,
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h199287;
reg [31 : 0] v__h198828;
reg [31 : 0] v__h11334;
reg [31 : 0] v__h15872;
reg [31 : 0] v__h16015;
reg [31 : 0] v__h4355;
reg [31 : 0] v__h7976;
reg [31 : 0] v__h19401;
reg [31 : 0] v__h18404;
reg [31 : 0] v__h18934;
reg [31 : 0] v__h10395;
reg [31 : 0] v__h10590;
reg [31 : 0] v__h176479;
reg [31 : 0] v__h190188;
reg [31 : 0] v__h168458;
reg [31 : 0] v__h197814;
reg [31 : 0] v__h169047;
reg [31 : 0] v__h169233;
reg [31 : 0] v__h4349;
reg [31 : 0] v__h7970;
reg [31 : 0] v__h10389;
reg [31 : 0] v__h10584;
reg [31 : 0] v__h11328;
reg [31 : 0] v__h15866;
reg [31 : 0] v__h16009;
reg [31 : 0] v__h18398;
reg [31 : 0] v__h18928;
reg [31 : 0] v__h19395;
reg [31 : 0] v__h168452;
reg [31 : 0] v__h169041;
reg [31 : 0] v__h169227;
reg [31 : 0] v__h176473;
reg [31 : 0] v__h190182;
reg [31 : 0] v__h197808;
reg [31 : 0] v__h198822;
reg [31 : 0] v__h199281;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1,
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2,
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3,
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4,
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10,
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13,
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9,
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33,
CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q37,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990,
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037,
IF_mmioPlatform_reqSz_95_EQ_0b0_96_THEN_IF_mmi_ETC___d1078,
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005,
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007,
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694,
dword__h125391,
ld_data__h163305,
v_wdata__h190496,
w1__h63930,
w1__h63935,
w2__h63931,
w2__h63937;
reg [31 : 0] SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107;
reg [7 : 0] v_wstrb__h190497;
reg [5 : 0] IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587;
reg [2 : 0] x__h75682;
reg [1 : 0] CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20,
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21,
CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q35;
reg CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14,
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15,
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36,
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1193,
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1430,
v_wuser__h190499,
x__h102503,
x__h75683;
wire [583 : 0] IF_enqDst_1_0_lat_1_whas__354_THEN_enqDst_1_0__ETC___d1401;
wire [519 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1550;
wire [517 : 0] IF_enqDst_1_0_lat_1_whas__354_THEN_enqDst_1_0__ETC___d1400;
wire [515 : 0] IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1392,
IF_llc_axi4_adapter_rg_rd_rsp_beat_971_BIT_0_0_ETC___d2013,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1545;
wire [383 : 0] IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1742,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1527;
wire [128 : 0] amoExec___d626,
amoExec___d703,
amoExec___d765,
amoExec___d810;
wire [127 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1493,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1510,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1544,
_0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213;
wire [97 : 0] llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42,
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40;
wire [96 : 0] mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18,
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16;
wire [73 : 0] llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41,
mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17;
wire [72 : 0] llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39;
wire [66 : 0] IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511;
wire [64 : 0] IF_llc_mem_server_propDstData_0_lat_0_whas__82_ETC___d1828;
wire [63 : 0] IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1372,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946,
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998,
IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686,
IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751,
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d661,
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d724,
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d831,
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d687,
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d752,
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1286,
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1324,
addr1__h66648,
data__h115667,
failed_testnum__h198871,
line_addr__h115100,
line_addr__h125208,
line_addr__h168594,
mmioPlatform_mtime__h46207,
newData__h37921,
newData__h42646,
op_result__h64708,
op_result__h65435,
op_result__h65440,
op_result__h65445,
op_result__h65450,
op_result__h65456,
op_result__h65463,
op_result__h65469,
result__h63981,
result__h64289,
result__h64316,
result__h64343,
result__h64370,
result__h64397,
result__h64424,
result__h64451,
result__h64478,
result__h64522,
result__h64549,
result__h64576,
result__h64603,
result__h64643,
result__h64670,
result__h64795,
result__h65019,
result__h65046,
result__h65073,
result__h65100,
result__h65127,
result__h65154,
result__h65181,
result__h65225,
result__h65252,
result__h65279,
result__h65306,
result__h65346,
result__h65373,
result__h65490,
result__h65556,
result__h65622,
result__h65688,
result__h65754,
result__h65820,
result__h65886,
result__h65948,
result__h65993,
result__h66059,
result__h66125,
result__h66183,
result__h66228,
v_awaddr__h190085,
w1___1__h64224,
w2___1__h64225,
x__h46418,
x__h51463,
x__h54199;
wire [47 : 0] IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d653,
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d719,
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d826;
wire [31 : 0] IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d644,
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d714,
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d821,
IF_mmio_axi4_adapter_f_rsps_to_core_first__77__ETC___d1114,
mmioPlatform_mtime_BITS_31_TO_0__q8,
mmioPlatform_mtime_BITS_63_TO_32__q7,
mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6,
mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5,
v__h37337,
v__h37374,
w13930_BITS_31_TO_0__q11,
w23931_BITS_31_TO_0__q12,
x_data__h35020;
wire [8 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__143_THEN__ETC___d1249;
wire [7 : 0] mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622;
wire [6 : 0] llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38;
wire [4 : 0] SEL_ARR_IF_propDstData_0_lat_0_whas__143_THEN__ETC___d1248;
wire [3 : 0] b__h168385, b__h4255;
wire [2 : 0] SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1468,
v_awsize_val__h15184;
wire [1 : 0] IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1377,
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1291,
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1329;
wire IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668,
IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d562,
IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663,
IF_enqDst_0_lat_0_whas__158_THEN_enqDst_0_lat__ETC___d1163,
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1362,
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1382,
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1398,
IF_llc_mem_server_enqDst_0_lat_0_whas__833_THE_ETC___d1838,
IF_llc_mem_server_propDstIdx_0_lat_0_whas__818_ETC___d1821,
IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735,
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d563,
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_2_ETC___d835,
IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334,
IF_mmioPlatform_waitLowerMSIPCRs_98_THEN_core__ETC___d606,
IF_mmio_axi4_adapter_f_rsps_to_core_first__77__ETC___d1092,
IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225,
IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53,
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1312,
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1350,
IF_propDstIdx_0_lat_0_whas__129_THEN_NOT_propD_ETC___d1195,
IF_propDstIdx_0_lat_0_whas__129_THEN_propDstId_ETC___d1132,
IF_propDstIdx_1_0_lat_0_whas__266_THEN_NOT_pro_ETC___d1432,
IF_propDstIdx_1_0_lat_0_whas__266_THEN_propDst_ETC___d1269,
IF_propDstIdx_1_1_lat_0_whas__273_THEN_propDst_ETC___d1276,
IF_propDstIdx_1_lat_0_whas__136_THEN_propDstId_ETC___d1139,
NOT_enqDst_0_rl_161_BIT_73_162_167_AND_SEL_ARR_ETC___d1255,
NOT_enqDst_0_rl_161_BIT_73_162_167_AND_SEL_ARR_ETC___d1260,
NOT_enqDst_1_0_rl_360_BIT_584_361_366_AND_SEL__ETC___d1556,
NOT_enqDst_1_0_rl_360_BIT_584_361_366_AND_SEL__ETC___d1561,
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967,
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d2046,
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d2049,
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1082,
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1095,
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d867,
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d875,
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d880,
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d890,
NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480,
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596,
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694,
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758,
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1197,
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1434,
llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d1978,
llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1758,
llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1659,
mmioPlatform_cycle_57_ULT_99___d458,
mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097,
mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726,
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467,
mmioPlatform_reqBE_BIT_0___h34176,
mmioPlatform_reqBE_BIT_4___h34136,
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573,
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680,
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746,
x__h75482,
x__h91204,
x__h97768;
// action method start
assign RDY_start = mmioPlatform_state == 2'd0 ;
assign CAN_FIRE_start = mmioPlatform_state == 2'd0 ;
assign WILL_FIRE_start = EN_start ;
// value method master0_aw_awid
assign master0_awid =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[97:93] ;
// value method master0_aw_awaddr
assign master0_awaddr =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[92:29] ;
// value method master0_aw_awlen
assign master0_awlen =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[28:21] ;
// value method master0_aw_awsize
assign master0_awsize =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[20:18] ;
// value method master0_aw_awburst
assign master0_awburst =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[17:16] ;
// value method master0_aw_awlock
assign master0_awlock =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[15] ;
// value method master0_aw_awcache
assign master0_awcache =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[14:11] ;
// value method master0_aw_awprot
assign master0_awprot =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[10:8] ;
// value method master0_aw_awqos
assign master0_awqos =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[7:4] ;
// value method master0_aw_awregion
assign master0_awregion =
llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40[3:0] ;
// value method master0_aw_awvalid
assign master0_awvalid =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ;
// action method master0_aw_awready
assign CAN_FIRE_master0_aw_awready = 1'd1 ;
assign WILL_FIRE_master0_aw_awready = 1'd1 ;
// value method master0_w_wdata
assign master0_wdata =
llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[73:10] ;
// value method master0_w_wstrb
assign master0_wstrb =
llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[9:2] ;
// value method master0_w_wlast
assign master0_wlast =
llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[1] ;
// value method master0_w_wuser
assign master0_wuser =
llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41[0] ;
// value method master0_w_wvalid
assign master0_wvalid =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ;
// action method master0_w_wready
assign CAN_FIRE_master0_w_wready = 1'd1 ;
assign WILL_FIRE_master0_w_wready = 1'd1 ;
// action method master0_b_bflit
assign CAN_FIRE_master0_b_bflit = 1'd1 ;
assign WILL_FIRE_master0_b_bflit = master0_bvalid ;
// value method master0_b_bready
assign master0_bready = !llc_axi4_adapter_master_xactor_shim_bff_rv[7] ;
// value method master0_ar_arid
assign master0_arid =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[97:93] ;
// value method master0_ar_araddr
assign master0_araddr =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[92:29] ;
// value method master0_ar_arlen
assign master0_arlen =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[28:21] ;
// value method master0_ar_arsize
assign master0_arsize =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[20:18] ;
// value method master0_ar_arburst
assign master0_arburst =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[17:16] ;
// value method master0_ar_arlock
assign master0_arlock =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[15] ;
// value method master0_ar_arcache
assign master0_arcache =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[14:11] ;
// value method master0_ar_arprot
assign master0_arprot =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[10:8] ;
// value method master0_ar_arqos
assign master0_arqos =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[7:4] ;
// value method master0_ar_arregion
assign master0_arregion =
llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42[3:0] ;
// value method master0_ar_arvalid
assign master0_arvalid =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ;
// action method master0_ar_arready
assign CAN_FIRE_master0_ar_arready = 1'd1 ;
assign WILL_FIRE_master0_ar_arready = 1'd1 ;
// action method master0_r_rflit
assign CAN_FIRE_master0_r_rflit = 1'd1 ;
assign WILL_FIRE_master0_r_rflit = master0_rvalid ;
// value method master0_r_rready
assign master0_rready = !llc_axi4_adapter_master_xactor_shim_rff_rv[73] ;
// value method master1_aw_awid
assign master1_awid =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[96:93] ;
// value method master1_aw_awaddr
assign master1_awaddr =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[92:29] ;
// value method master1_aw_awlen
assign master1_awlen =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[28:21] ;
// value method master1_aw_awsize
assign master1_awsize =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[20:18] ;
// value method master1_aw_awburst
assign master1_awburst =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[17:16] ;
// value method master1_aw_awlock
assign master1_awlock =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[15] ;
// value method master1_aw_awcache
assign master1_awcache =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[14:11] ;
// value method master1_aw_awprot
assign master1_awprot =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[10:8] ;
// value method master1_aw_awqos
assign master1_awqos =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[7:4] ;
// value method master1_aw_awregion
assign master1_awregion =
mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16[3:0] ;
// value method master1_aw_awvalid
assign master1_awvalid =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ;
// action method master1_aw_awready
assign CAN_FIRE_master1_aw_awready = 1'd1 ;
assign WILL_FIRE_master1_aw_awready = 1'd1 ;
// value method master1_w_wdata
assign master1_wdata =
mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[73:10] ;
// value method master1_w_wstrb
assign master1_wstrb =
mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[9:2] ;
// value method master1_w_wlast
assign master1_wlast =
mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[1] ;
// value method master1_w_wuser
assign master1_wuser =
mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17[0] ;
// value method master1_w_wvalid
assign master1_wvalid =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ;
// action method master1_w_wready
assign CAN_FIRE_master1_w_wready = 1'd1 ;
assign WILL_FIRE_master1_w_wready = 1'd1 ;
// action method master1_b_bflit
assign CAN_FIRE_master1_b_bflit = 1'd1 ;
assign WILL_FIRE_master1_b_bflit = master1_bvalid ;
// value method master1_b_bready
assign master1_bready = !mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ;
// value method master1_ar_arid
assign master1_arid =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[96:93] ;
// value method master1_ar_araddr
assign master1_araddr =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[92:29] ;
// value method master1_ar_arlen
assign master1_arlen =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[28:21] ;
// value method master1_ar_arsize
assign master1_arsize =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[20:18] ;
// value method master1_ar_arburst
assign master1_arburst =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[17:16] ;
// value method master1_ar_arlock
assign master1_arlock =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[15] ;
// value method master1_ar_arcache
assign master1_arcache =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[14:11] ;
// value method master1_ar_arprot
assign master1_arprot =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[10:8] ;
// value method master1_ar_arqos
assign master1_arqos =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[7:4] ;
// value method master1_ar_arregion
assign master1_arregion =
mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18[3:0] ;
// value method master1_ar_arvalid
assign master1_arvalid =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ;
// action method master1_ar_arready
assign CAN_FIRE_master1_ar_arready = 1'd1 ;
assign WILL_FIRE_master1_ar_arready = 1'd1 ;
// action method master1_r_rflit
assign CAN_FIRE_master1_r_rflit = 1'd1 ;
assign WILL_FIRE_master1_r_rflit = master1_rvalid ;
// value method master1_r_rready
assign master1_rready = !mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method non_maskable_interrupt_req
assign CAN_FIRE_non_maskable_interrupt_req = 1'd1 ;
assign WILL_FIRE_non_maskable_interrupt_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method debug_module_mem_server_aw_awflit
assign CAN_FIRE_debug_module_mem_server_aw_awflit = 1'd1 ;
assign WILL_FIRE_debug_module_mem_server_aw_awflit =
debug_module_mem_server_awvalid ;
// value method debug_module_mem_server_aw_awready
assign debug_module_mem_server_awready =
!llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ;
// action method debug_module_mem_server_w_wflit
assign CAN_FIRE_debug_module_mem_server_w_wflit = 1'd1 ;
assign WILL_FIRE_debug_module_mem_server_w_wflit =
debug_module_mem_server_wvalid ;
// value method debug_module_mem_server_w_wready
assign debug_module_mem_server_wready =
!llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ;
// value method debug_module_mem_server_b_bid
assign debug_module_mem_server_bid =
llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38[6:2] ;
// value method debug_module_mem_server_b_bresp
assign debug_module_mem_server_bresp =
llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38[1:0] ;
// value method debug_module_mem_server_b_bvalid
assign debug_module_mem_server_bvalid =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ;
// action method debug_module_mem_server_b_bready
assign CAN_FIRE_debug_module_mem_server_b_bready = 1'd1 ;
assign WILL_FIRE_debug_module_mem_server_b_bready = 1'd1 ;
// action method debug_module_mem_server_ar_arflit
assign CAN_FIRE_debug_module_mem_server_ar_arflit = 1'd1 ;
assign WILL_FIRE_debug_module_mem_server_ar_arflit =
debug_module_mem_server_arvalid ;
// value method debug_module_mem_server_ar_arready
assign debug_module_mem_server_arready =
!llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ;
// value method debug_module_mem_server_r_rid
assign debug_module_mem_server_rid =
llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[72:68] ;
// value method debug_module_mem_server_r_rdata
assign debug_module_mem_server_rdata =
llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[67:4] ;
// value method debug_module_mem_server_r_rresp
assign debug_module_mem_server_rresp =
llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[3:2] ;
// value method debug_module_mem_server_r_rlast
assign debug_module_mem_server_rlast =
llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[1] ;
// value method debug_module_mem_server_r_ruser
assign debug_module_mem_server_ruser =
llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39[0] ;
// value method debug_module_mem_server_r_rvalid
assign debug_module_mem_server_rvalid =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ;
// action method debug_module_mem_server_r_rready
assign CAN_FIRE_debug_module_mem_server_r_rready = 1'd1 ;
assign WILL_FIRE_debug_module_mem_server_r_rready = 1'd1 ;
// action method hart0_run_halt_server_request_put
assign RDY_hart0_run_halt_server_request_put =
core_0$RDY_hart0_run_halt_server_request_put ;
assign CAN_FIRE_hart0_run_halt_server_request_put =
core_0$RDY_hart0_run_halt_server_request_put ;
assign WILL_FIRE_hart0_run_halt_server_request_put =
EN_hart0_run_halt_server_request_put ;
// actionvalue method hart0_run_halt_server_response_get
assign hart0_run_halt_server_response_get =
core_0$hart0_run_halt_server_response_get ;
assign RDY_hart0_run_halt_server_response_get =
core_0$RDY_hart0_run_halt_server_response_get ;
assign CAN_FIRE_hart0_run_halt_server_response_get =
core_0$RDY_hart0_run_halt_server_response_get ;
assign WILL_FIRE_hart0_run_halt_server_response_get =
EN_hart0_run_halt_server_response_get ;
// action method hart0_gpr_mem_server_request_put
assign RDY_hart0_gpr_mem_server_request_put =
core_0$RDY_hart0_gpr_mem_server_request_put ;
assign CAN_FIRE_hart0_gpr_mem_server_request_put =
core_0$RDY_hart0_gpr_mem_server_request_put ;
assign WILL_FIRE_hart0_gpr_mem_server_request_put =
EN_hart0_gpr_mem_server_request_put ;
// actionvalue method hart0_gpr_mem_server_response_get
assign hart0_gpr_mem_server_response_get =
core_0$hart0_gpr_mem_server_response_get ;
assign RDY_hart0_gpr_mem_server_response_get =
core_0$RDY_hart0_gpr_mem_server_response_get ;
assign CAN_FIRE_hart0_gpr_mem_server_response_get =
core_0$RDY_hart0_gpr_mem_server_response_get ;
assign WILL_FIRE_hart0_gpr_mem_server_response_get =
EN_hart0_gpr_mem_server_response_get ;
// action method hart0_fpr_mem_server_request_put
assign RDY_hart0_fpr_mem_server_request_put =
core_0$RDY_hart0_fpr_mem_server_request_put ;
assign CAN_FIRE_hart0_fpr_mem_server_request_put =
core_0$RDY_hart0_fpr_mem_server_request_put ;
assign WILL_FIRE_hart0_fpr_mem_server_request_put =
EN_hart0_fpr_mem_server_request_put ;
// actionvalue method hart0_fpr_mem_server_response_get
assign hart0_fpr_mem_server_response_get =
core_0$hart0_fpr_mem_server_response_get ;
assign RDY_hart0_fpr_mem_server_response_get =
core_0$RDY_hart0_fpr_mem_server_response_get ;
assign CAN_FIRE_hart0_fpr_mem_server_response_get =
core_0$RDY_hart0_fpr_mem_server_response_get ;
assign WILL_FIRE_hart0_fpr_mem_server_response_get =
EN_hart0_fpr_mem_server_response_get ;
// action method hart0_csr_mem_server_request_put
assign RDY_hart0_csr_mem_server_request_put =
core_0$RDY_hart0_csr_mem_server_request_put ;
assign CAN_FIRE_hart0_csr_mem_server_request_put =
core_0$RDY_hart0_csr_mem_server_request_put ;
assign WILL_FIRE_hart0_csr_mem_server_request_put =
EN_hart0_csr_mem_server_request_put ;
// actionvalue method hart0_csr_mem_server_response_get
assign hart0_csr_mem_server_response_get =
core_0$hart0_csr_mem_server_response_get ;
assign RDY_hart0_csr_mem_server_response_get =
core_0$RDY_hart0_csr_mem_server_response_get ;
assign CAN_FIRE_hart0_csr_mem_server_response_get =
core_0$RDY_hart0_csr_mem_server_response_get ;
assign WILL_FIRE_hart0_csr_mem_server_response_get =
EN_hart0_csr_mem_server_response_get ;
// action method hart0_put_other_req_put
assign RDY_hart0_put_other_req_put = 1'd1 ;
assign CAN_FIRE_hart0_put_other_req_put = 1'd1 ;
assign WILL_FIRE_hart0_put_other_req_put = EN_hart0_put_other_req_put ;
// submodule core_0
mkCore core_0(.CLK(CLK),
.RST_N(RST_N),
.coreReq_perfReq_loc(core_0$coreReq_perfReq_loc),
.coreReq_perfReq_t(core_0$coreReq_perfReq_t),
.coreReq_start_fromHostAddr(core_0$coreReq_start_fromHostAddr),
.coreReq_start_startpc(core_0$coreReq_start_startpc),
.coreReq_start_toHostAddr(core_0$coreReq_start_toHostAddr),
.dCacheToParent_fromP_enq_x(core_0$dCacheToParent_fromP_enq_x),
.hart0_csr_mem_server_request_put(core_0$hart0_csr_mem_server_request_put),
.hart0_fpr_mem_server_request_put(core_0$hart0_fpr_mem_server_request_put),
.hart0_gpr_mem_server_request_put(core_0$hart0_gpr_mem_server_request_put),
.hart0_run_halt_server_request_put(core_0$hart0_run_halt_server_request_put),
.iCacheToParent_fromP_enq_x(core_0$iCacheToParent_fromP_enq_x),
.mmioToPlatform_pRq_enq_x(core_0$mmioToPlatform_pRq_enq_x),
.mmioToPlatform_pRs_enq_x(core_0$mmioToPlatform_pRs_enq_x),
.mmioToPlatform_setTime_t(core_0$mmioToPlatform_setTime_t),
.recvDoStats_x(core_0$recvDoStats_x),
.setMEIP_v(core_0$setMEIP_v),
.setSEIP_v(core_0$setSEIP_v),
.tlbToMem_respLd_enq_x(core_0$tlbToMem_respLd_enq_x),
.EN_coreReq_start(core_0$EN_coreReq_start),
.EN_coreReq_perfReq(core_0$EN_coreReq_perfReq),
.EN_coreIndInv_perfResp(core_0$EN_coreIndInv_perfResp),
.EN_coreIndInv_terminate(core_0$EN_coreIndInv_terminate),
.EN_dCacheToParent_rsToP_deq(core_0$EN_dCacheToParent_rsToP_deq),
.EN_dCacheToParent_rqToP_deq(core_0$EN_dCacheToParent_rqToP_deq),
.EN_dCacheToParent_fromP_enq(core_0$EN_dCacheToParent_fromP_enq),
.EN_iCacheToParent_rsToP_deq(core_0$EN_iCacheToParent_rsToP_deq),
.EN_iCacheToParent_rqToP_deq(core_0$EN_iCacheToParent_rqToP_deq),
.EN_iCacheToParent_fromP_enq(core_0$EN_iCacheToParent_fromP_enq),
.EN_tlbToMem_memReq_deq(core_0$EN_tlbToMem_memReq_deq),
.EN_tlbToMem_respLd_enq(core_0$EN_tlbToMem_respLd_enq),
.EN_mmioToPlatform_cRq_deq(core_0$EN_mmioToPlatform_cRq_deq),
.EN_mmioToPlatform_pRs_enq(core_0$EN_mmioToPlatform_pRs_enq),
.EN_mmioToPlatform_pRq_enq(core_0$EN_mmioToPlatform_pRq_enq),
.EN_mmioToPlatform_cRs_deq(core_0$EN_mmioToPlatform_cRs_deq),
.EN_mmioToPlatform_setTime(core_0$EN_mmioToPlatform_setTime),
.EN_sendDoStats(core_0$EN_sendDoStats),
.EN_recvDoStats(core_0$EN_recvDoStats),
.EN_deadlock_dCacheCRqStuck_get(core_0$EN_deadlock_dCacheCRqStuck_get),
.EN_deadlock_dCachePRqStuck_get(core_0$EN_deadlock_dCachePRqStuck_get),
.EN_deadlock_iCacheCRqStuck_get(core_0$EN_deadlock_iCacheCRqStuck_get),
.EN_deadlock_iCachePRqStuck_get(core_0$EN_deadlock_iCachePRqStuck_get),
.EN_deadlock_renameInstStuck_get(core_0$EN_deadlock_renameInstStuck_get),
.EN_deadlock_renameCorrectPathStuck_get(core_0$EN_deadlock_renameCorrectPathStuck_get),
.EN_deadlock_commitInstStuck_get(core_0$EN_deadlock_commitInstStuck_get),
.EN_deadlock_commitUserInstStuck_get(core_0$EN_deadlock_commitUserInstStuck_get),
.EN_deadlock_checkStarted_get(core_0$EN_deadlock_checkStarted_get),
.EN_renameDebug_renameErr_get(core_0$EN_renameDebug_renameErr_get),
.EN_setMEIP(core_0$EN_setMEIP),
.EN_setSEIP(core_0$EN_setSEIP),
.EN_hart0_run_halt_server_request_put(core_0$EN_hart0_run_halt_server_request_put),
.EN_hart0_run_halt_server_response_get(core_0$EN_hart0_run_halt_server_response_get),
.EN_hart0_gpr_mem_server_request_put(core_0$EN_hart0_gpr_mem_server_request_put),
.EN_hart0_gpr_mem_server_response_get(core_0$EN_hart0_gpr_mem_server_response_get),
.EN_hart0_fpr_mem_server_request_put(core_0$EN_hart0_fpr_mem_server_request_put),
.EN_hart0_fpr_mem_server_response_get(core_0$EN_hart0_fpr_mem_server_response_get),
.EN_hart0_csr_mem_server_request_put(core_0$EN_hart0_csr_mem_server_request_put),
.EN_hart0_csr_mem_server_response_get(core_0$EN_hart0_csr_mem_server_response_get),
.RDY_coreReq_start(),
.RDY_coreReq_perfReq(),
.coreIndInv_perfResp(),
.RDY_coreIndInv_perfResp(),
.RDY_coreIndInv_terminate(core_0$RDY_coreIndInv_terminate),
.dCacheToParent_rsToP_notEmpty(),
.RDY_dCacheToParent_rsToP_notEmpty(),
.RDY_dCacheToParent_rsToP_deq(core_0$RDY_dCacheToParent_rsToP_deq),
.dCacheToParent_rsToP_first(core_0$dCacheToParent_rsToP_first),
.RDY_dCacheToParent_rsToP_first(core_0$RDY_dCacheToParent_rsToP_first),
.dCacheToParent_rqToP_notEmpty(),
.RDY_dCacheToParent_rqToP_notEmpty(),
.RDY_dCacheToParent_rqToP_deq(core_0$RDY_dCacheToParent_rqToP_deq),
.dCacheToParent_rqToP_first(core_0$dCacheToParent_rqToP_first),
.RDY_dCacheToParent_rqToP_first(core_0$RDY_dCacheToParent_rqToP_first),
.dCacheToParent_fromP_notFull(),
.RDY_dCacheToParent_fromP_notFull(),
.RDY_dCacheToParent_fromP_enq(core_0$RDY_dCacheToParent_fromP_enq),
.iCacheToParent_rsToP_notEmpty(),
.RDY_iCacheToParent_rsToP_notEmpty(),
.RDY_iCacheToParent_rsToP_deq(core_0$RDY_iCacheToParent_rsToP_deq),
.iCacheToParent_rsToP_first(core_0$iCacheToParent_rsToP_first),
.RDY_iCacheToParent_rsToP_first(core_0$RDY_iCacheToParent_rsToP_first),
.iCacheToParent_rqToP_notEmpty(),
.RDY_iCacheToParent_rqToP_notEmpty(),
.RDY_iCacheToParent_rqToP_deq(core_0$RDY_iCacheToParent_rqToP_deq),
.iCacheToParent_rqToP_first(core_0$iCacheToParent_rqToP_first),
.RDY_iCacheToParent_rqToP_first(core_0$RDY_iCacheToParent_rqToP_first),
.iCacheToParent_fromP_notFull(),
.RDY_iCacheToParent_fromP_notFull(),
.RDY_iCacheToParent_fromP_enq(core_0$RDY_iCacheToParent_fromP_enq),
.tlbToMem_memReq_notEmpty(),
.RDY_tlbToMem_memReq_notEmpty(),
.RDY_tlbToMem_memReq_deq(core_0$RDY_tlbToMem_memReq_deq),
.tlbToMem_memReq_first(core_0$tlbToMem_memReq_first),
.RDY_tlbToMem_memReq_first(core_0$RDY_tlbToMem_memReq_first),
.tlbToMem_respLd_notFull(),
.RDY_tlbToMem_respLd_notFull(),
.RDY_tlbToMem_respLd_enq(core_0$RDY_tlbToMem_respLd_enq),
.mmioToPlatform_cRq_notEmpty(core_0$mmioToPlatform_cRq_notEmpty),
.RDY_mmioToPlatform_cRq_notEmpty(),
.RDY_mmioToPlatform_cRq_deq(core_0$RDY_mmioToPlatform_cRq_deq),
.mmioToPlatform_cRq_first(core_0$mmioToPlatform_cRq_first),
.RDY_mmioToPlatform_cRq_first(core_0$RDY_mmioToPlatform_cRq_first),
.mmioToPlatform_pRs_notFull(),
.RDY_mmioToPlatform_pRs_notFull(),
.RDY_mmioToPlatform_pRs_enq(core_0$RDY_mmioToPlatform_pRs_enq),
.mmioToPlatform_pRq_notFull(),
.RDY_mmioToPlatform_pRq_notFull(),
.RDY_mmioToPlatform_pRq_enq(core_0$RDY_mmioToPlatform_pRq_enq),
.mmioToPlatform_cRs_notEmpty(),
.RDY_mmioToPlatform_cRs_notEmpty(),
.RDY_mmioToPlatform_cRs_deq(core_0$RDY_mmioToPlatform_cRs_deq),
.mmioToPlatform_cRs_first(core_0$mmioToPlatform_cRs_first),
.RDY_mmioToPlatform_cRs_first(core_0$RDY_mmioToPlatform_cRs_first),
.RDY_mmioToPlatform_setTime(),
.sendDoStats(core_0$sendDoStats),
.RDY_sendDoStats(core_0$RDY_sendDoStats),
.RDY_recvDoStats(),
.deadlock_dCacheCRqStuck_get(),
.RDY_deadlock_dCacheCRqStuck_get(core_0$RDY_deadlock_dCacheCRqStuck_get),
.deadlock_dCachePRqStuck_get(),
.RDY_deadlock_dCachePRqStuck_get(core_0$RDY_deadlock_dCachePRqStuck_get),
.deadlock_iCacheCRqStuck_get(),
.RDY_deadlock_iCacheCRqStuck_get(core_0$RDY_deadlock_iCacheCRqStuck_get),
.deadlock_iCachePRqStuck_get(),
.RDY_deadlock_iCachePRqStuck_get(core_0$RDY_deadlock_iCachePRqStuck_get),
.deadlock_renameInstStuck_get(),
.RDY_deadlock_renameInstStuck_get(core_0$RDY_deadlock_renameInstStuck_get),
.deadlock_renameCorrectPathStuck_get(),
.RDY_deadlock_renameCorrectPathStuck_get(core_0$RDY_deadlock_renameCorrectPathStuck_get),
.deadlock_commitInstStuck_get(),
.RDY_deadlock_commitInstStuck_get(core_0$RDY_deadlock_commitInstStuck_get),
.deadlock_commitUserInstStuck_get(),
.RDY_deadlock_commitUserInstStuck_get(core_0$RDY_deadlock_commitUserInstStuck_get),
.RDY_deadlock_checkStarted_get(core_0$RDY_deadlock_checkStarted_get),
.renameDebug_renameErr_get(),
.RDY_renameDebug_renameErr_get(core_0$RDY_renameDebug_renameErr_get),
.RDY_setMEIP(),
.RDY_setSEIP(),
.RDY_hart0_run_halt_server_request_put(core_0$RDY_hart0_run_halt_server_request_put),
.hart0_run_halt_server_response_get(core_0$hart0_run_halt_server_response_get),
.RDY_hart0_run_halt_server_response_get(core_0$RDY_hart0_run_halt_server_response_get),
.RDY_hart0_gpr_mem_server_request_put(core_0$RDY_hart0_gpr_mem_server_request_put),
.hart0_gpr_mem_server_response_get(core_0$hart0_gpr_mem_server_response_get),
.RDY_hart0_gpr_mem_server_response_get(core_0$RDY_hart0_gpr_mem_server_response_get),
.RDY_hart0_fpr_mem_server_request_put(core_0$RDY_hart0_fpr_mem_server_request_put),
.hart0_fpr_mem_server_response_get(core_0$hart0_fpr_mem_server_response_get),
.RDY_hart0_fpr_mem_server_response_get(core_0$RDY_hart0_fpr_mem_server_response_get),
.RDY_hart0_csr_mem_server_request_put(core_0$RDY_hart0_csr_mem_server_request_put),
.hart0_csr_mem_server_response_get(core_0$hart0_csr_mem_server_response_get),
.RDY_hart0_csr_mem_server_response_get(core_0$RDY_hart0_csr_mem_server_response_get));
// submodule llc
mkLLCache llc(.CLK(CLK),
.RST_N(RST_N),
.dma_memReq_enq_x(llc$dma_memReq_enq_x),
.perf_req_r(llc$perf_req_r),
.perf_setStatus_doStats(llc$perf_setStatus_doStats),
.to_child_rqFromC_enq_x(llc$to_child_rqFromC_enq_x),
.to_child_rsFromC_enq_x(llc$to_child_rsFromC_enq_x),
.to_mem_rsFromM_enq_x(llc$to_mem_rsFromM_enq_x),
.EN_to_child_rsFromC_enq(llc$EN_to_child_rsFromC_enq),
.EN_to_child_rqFromC_enq(llc$EN_to_child_rqFromC_enq),
.EN_to_child_toC_deq(llc$EN_to_child_toC_deq),
.EN_dma_memReq_enq(llc$EN_dma_memReq_enq),
.EN_dma_respLd_deq(llc$EN_dma_respLd_deq),
.EN_dma_respSt_deq(llc$EN_dma_respSt_deq),
.EN_to_mem_toM_deq(llc$EN_to_mem_toM_deq),
.EN_to_mem_rsFromM_enq(llc$EN_to_mem_rsFromM_enq),
.EN_cRqStuck_get(llc$EN_cRqStuck_get),
.EN_perf_setStatus(llc$EN_perf_setStatus),
.EN_perf_req(llc$EN_perf_req),
.EN_perf_resp(llc$EN_perf_resp),
.to_child_rsFromC_notFull(),
.RDY_to_child_rsFromC_notFull(),
.RDY_to_child_rsFromC_enq(llc$RDY_to_child_rsFromC_enq),
.to_child_rqFromC_notFull(),
.RDY_to_child_rqFromC_notFull(),
.RDY_to_child_rqFromC_enq(llc$RDY_to_child_rqFromC_enq),
.to_child_toC_notEmpty(),
.RDY_to_child_toC_notEmpty(),
.RDY_to_child_toC_deq(llc$RDY_to_child_toC_deq),
.to_child_toC_first(llc$to_child_toC_first),
.RDY_to_child_toC_first(llc$RDY_to_child_toC_first),
.dma_memReq_notFull(),
.RDY_dma_memReq_notFull(),
.RDY_dma_memReq_enq(llc$RDY_dma_memReq_enq),
.dma_respLd_notEmpty(),
.RDY_dma_respLd_notEmpty(),
.RDY_dma_respLd_deq(llc$RDY_dma_respLd_deq),
.dma_respLd_first(llc$dma_respLd_first),
.RDY_dma_respLd_first(llc$RDY_dma_respLd_first),
.dma_respSt_notEmpty(),
.RDY_dma_respSt_notEmpty(),
.RDY_dma_respSt_deq(llc$RDY_dma_respSt_deq),
.dma_respSt_first(llc$dma_respSt_first),
.RDY_dma_respSt_first(llc$RDY_dma_respSt_first),
.to_mem_toM_notEmpty(),
.RDY_to_mem_toM_notEmpty(),
.RDY_to_mem_toM_deq(llc$RDY_to_mem_toM_deq),
.to_mem_toM_first(llc$to_mem_toM_first),
.RDY_to_mem_toM_first(llc$RDY_to_mem_toM_first),
.to_mem_rsFromM_notFull(),
.RDY_to_mem_rsFromM_notFull(),
.RDY_to_mem_rsFromM_enq(llc$RDY_to_mem_rsFromM_enq),
.cRqStuck_get(),
.RDY_cRqStuck_get(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule llc_axi4_adapter_f_pending_reads
FIFO2 #(.width(32'd69),
.guarded(32'd1)) llc_axi4_adapter_f_pending_reads(.RST(RST_N),
.CLK(CLK),
.D_IN(llc_axi4_adapter_f_pending_reads$D_IN),
.ENQ(llc_axi4_adapter_f_pending_reads$ENQ),
.DEQ(llc_axi4_adapter_f_pending_reads$DEQ),
.CLR(llc_axi4_adapter_f_pending_reads$CLR),
.D_OUT(llc_axi4_adapter_f_pending_reads$D_OUT),
.FULL_N(llc_axi4_adapter_f_pending_reads$FULL_N),
.EMPTY_N(llc_axi4_adapter_f_pending_reads$EMPTY_N));
// submodule llc_mem_server_f_dword_in_line
FIFO2 #(.width(32'd3),
.guarded(32'd1)) llc_mem_server_f_dword_in_line(.RST(RST_N),
.CLK(CLK),
.D_IN(llc_mem_server_f_dword_in_line$D_IN),
.ENQ(llc_mem_server_f_dword_in_line$ENQ),
.DEQ(llc_mem_server_f_dword_in_line$DEQ),
.CLR(llc_mem_server_f_dword_in_line$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule llc_mem_server_tlbQ
FIFO2 #(.width(32'd65), .guarded(32'd1)) llc_mem_server_tlbQ(.RST(RST_N),
.CLK(CLK),
.D_IN(llc_mem_server_tlbQ$D_IN),
.ENQ(llc_mem_server_tlbQ$ENQ),
.DEQ(llc_mem_server_tlbQ$DEQ),
.CLR(llc_mem_server_tlbQ$CLR),
.D_OUT(llc_mem_server_tlbQ$D_OUT),
.FULL_N(llc_mem_server_tlbQ$FULL_N),
.EMPTY_N(llc_mem_server_tlbQ$EMPTY_N));
// submodule mmio_axi4_adapter_f_reqs_from_core
FIFO2 #(.width(32'd215),
.guarded(32'd1)) mmio_axi4_adapter_f_reqs_from_core(.RST(RST_N),
.CLK(CLK),
.D_IN(mmio_axi4_adapter_f_reqs_from_core$D_IN),
.ENQ(mmio_axi4_adapter_f_reqs_from_core$ENQ),
.DEQ(mmio_axi4_adapter_f_reqs_from_core$DEQ),
.CLR(mmio_axi4_adapter_f_reqs_from_core$CLR),
.D_OUT(mmio_axi4_adapter_f_reqs_from_core$D_OUT),
.FULL_N(mmio_axi4_adapter_f_reqs_from_core$FULL_N),
.EMPTY_N(mmio_axi4_adapter_f_reqs_from_core$EMPTY_N));
// submodule mmio_axi4_adapter_f_rsps_to_core
FIFO2 #(.width(32'd130),
.guarded(32'd1)) mmio_axi4_adapter_f_rsps_to_core(.RST(RST_N),
.CLK(CLK),
.D_IN(mmio_axi4_adapter_f_rsps_to_core$D_IN),
.ENQ(mmio_axi4_adapter_f_rsps_to_core$ENQ),
.DEQ(mmio_axi4_adapter_f_rsps_to_core$DEQ),
.CLR(mmio_axi4_adapter_f_rsps_to_core$CLR),
.D_OUT(mmio_axi4_adapter_f_rsps_to_core$D_OUT),
.FULL_N(mmio_axi4_adapter_f_rsps_to_core$FULL_N),
.EMPTY_N(mmio_axi4_adapter_f_rsps_to_core$EMPTY_N));
// submodule mmio_axi4_adapter_soc_map
mkSoC_Map mmio_axi4_adapter_soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(mmio_axi4_adapter_soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(mmio_axi4_adapter_soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr),
.m_plic_addr_range(),
.m_near_mem_io_addr_range(),
.m_flash_mem_addr_range(),
.m_ethernet_0_addr_range(),
.m_dma_0_addr_range(),
.m_uart16550_0_addr_range(),
.m_gpio_0_addr_range(),
.m_boot_rom_addr_range(),
.m_ddr4_0_uncached_addr_range(),
.m_ddr4_0_cached_addr_range(),
.m_mem0_controller_addr_range(),
.m_is_mem_addr(),
.m_is_IO_addr(mmio_axi4_adapter_soc_map$m_is_IO_addr),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_srcPropose
assign CAN_FIRE_RL_srcPropose =
core_0$RDY_dCacheToParent_rqToP_first &&
core_0$RDY_dCacheToParent_rqToP_deq &&
!propDstIdx_0_rl ;
assign WILL_FIRE_RL_srcPropose = CAN_FIRE_RL_srcPropose ;
// rule RL_srcPropose_1
assign CAN_FIRE_RL_srcPropose_1 =
core_0$RDY_iCacheToParent_rqToP_first &&
core_0$RDY_iCacheToParent_rqToP_deq &&
!propDstIdx_1_rl ;
assign WILL_FIRE_RL_srcPropose_1 = CAN_FIRE_RL_srcPropose_1 ;
// rule RL_dstSelectSrc
assign CAN_FIRE_RL_dstSelectSrc = 1'd1 ;
assign WILL_FIRE_RL_dstSelectSrc = 1'd1 ;
// rule RL_doEnq
assign CAN_FIRE_RL_doEnq =
llc$RDY_to_child_rqFromC_enq &&
IF_enqDst_0_lat_0_whas__158_THEN_enqDst_0_lat__ETC___d1163 ;
assign WILL_FIRE_RL_doEnq = CAN_FIRE_RL_doEnq ;
// rule RL_srcPropose_2
assign CAN_FIRE_RL_srcPropose_2 =
core_0$RDY_dCacheToParent_rsToP_first &&
core_0$RDY_dCacheToParent_rsToP_deq &&
!propDstIdx_1_0_rl ;
assign WILL_FIRE_RL_srcPropose_2 = CAN_FIRE_RL_srcPropose_2 ;
// rule RL_srcPropose_3
assign CAN_FIRE_RL_srcPropose_3 =
core_0$RDY_iCacheToParent_rsToP_first &&
core_0$RDY_iCacheToParent_rsToP_deq &&
!propDstIdx_1_1_rl ;
assign WILL_FIRE_RL_srcPropose_3 = CAN_FIRE_RL_srcPropose_3 ;
// rule RL_dstSelectSrc_1
assign CAN_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
assign WILL_FIRE_RL_dstSelectSrc_1 = 1'd1 ;
// rule RL_doEnq_1
assign CAN_FIRE_RL_doEnq_1 =
llc$RDY_to_child_rsFromC_enq &&
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1362 ;
assign WILL_FIRE_RL_doEnq_1 = CAN_FIRE_RL_doEnq_1 ;
// rule RL_sendPRq
assign CAN_FIRE_RL_sendPRq =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_dCacheToParent_fromP_enq &&
!llc$to_child_toC_first[587] &&
!llc$to_child_toC_first[0] ;
assign WILL_FIRE_RL_sendPRq = CAN_FIRE_RL_sendPRq ;
// rule RL_sendPRs
assign CAN_FIRE_RL_sendPRs =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_dCacheToParent_fromP_enq &&
llc$to_child_toC_first[587] &&
!llc$to_child_toC_first[520] ;
assign WILL_FIRE_RL_sendPRs = CAN_FIRE_RL_sendPRs ;
// rule RL_sendPRq_1
assign CAN_FIRE_RL_sendPRq_1 =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_iCacheToParent_fromP_enq &&
!llc$to_child_toC_first[587] &&
llc$to_child_toC_first[0] ;
assign WILL_FIRE_RL_sendPRq_1 = CAN_FIRE_RL_sendPRq_1 ;
// rule RL_sendPRs_1
assign CAN_FIRE_RL_sendPRs_1 =
llc$RDY_to_child_toC_first && llc$RDY_to_child_toC_deq &&
core_0$RDY_iCacheToParent_fromP_enq &&
llc$to_child_toC_first[587] &&
llc$to_child_toC_first[520] ;
assign WILL_FIRE_RL_sendPRs_1 = CAN_FIRE_RL_sendPRs_1 ;
// rule RL_broadcastStats
assign CAN_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ;
assign WILL_FIRE_RL_broadcastStats = core_0$RDY_sendDoStats ;
// rule RL_rl_dummy1
assign CAN_FIRE_RL_rl_dummy1 = core_0$RDY_deadlock_dCacheCRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy1 = core_0$RDY_deadlock_dCacheCRqStuck_get ;
// rule RL_rl_dummy2
assign CAN_FIRE_RL_rl_dummy2 = core_0$RDY_deadlock_dCachePRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy2 = core_0$RDY_deadlock_dCachePRqStuck_get ;
// rule RL_rl_dummy3
assign CAN_FIRE_RL_rl_dummy3 = core_0$RDY_deadlock_iCacheCRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy3 = core_0$RDY_deadlock_iCacheCRqStuck_get ;
// rule RL_rl_dummy4
assign CAN_FIRE_RL_rl_dummy4 = core_0$RDY_deadlock_iCachePRqStuck_get ;
assign WILL_FIRE_RL_rl_dummy4 = core_0$RDY_deadlock_iCachePRqStuck_get ;
// rule RL_rl_dummy5
assign CAN_FIRE_RL_rl_dummy5 = core_0$RDY_deadlock_renameInstStuck_get ;
assign WILL_FIRE_RL_rl_dummy5 = core_0$RDY_deadlock_renameInstStuck_get ;
// rule RL_rl_dummy6
assign CAN_FIRE_RL_rl_dummy6 =
core_0$RDY_deadlock_renameCorrectPathStuck_get ;
assign WILL_FIRE_RL_rl_dummy6 =
core_0$RDY_deadlock_renameCorrectPathStuck_get ;
// rule RL_rl_dummy7
assign CAN_FIRE_RL_rl_dummy7 = core_0$RDY_deadlock_commitInstStuck_get ;
assign WILL_FIRE_RL_rl_dummy7 = core_0$RDY_deadlock_commitInstStuck_get ;
// rule RL_rl_dummy8
assign CAN_FIRE_RL_rl_dummy8 = core_0$RDY_deadlock_commitUserInstStuck_get ;
assign WILL_FIRE_RL_rl_dummy8 =
core_0$RDY_deadlock_commitUserInstStuck_get ;
// rule RL_rl_dummy9
assign CAN_FIRE_RL_rl_dummy9 = core_0$RDY_deadlock_checkStarted_get ;
assign WILL_FIRE_RL_rl_dummy9 = core_0$RDY_deadlock_checkStarted_get ;
// rule RL_rl_dummy20
assign CAN_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ;
assign WILL_FIRE_RL_rl_dummy20 = core_0$RDY_renameDebug_renameErr_get ;
// rule RL_rl_terminate
assign CAN_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ;
assign WILL_FIRE_RL_rl_terminate = core_0$RDY_coreIndInv_terminate ;
// rule RL_rl_tohost
assign CAN_FIRE_RL_rl_tohost = !mmioPlatform_toHostQ_empty ;
assign WILL_FIRE_RL_rl_tohost = CAN_FIRE_RL_rl_tohost ;
// rule RL_mmio_axi4_adapter_rl_handle_write_req
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req =
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd2 ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ;
// rule RL_mmio_axi4_adapter_rl_handle_read_req
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req =
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd1 &&
b__h4255 == 4'd0 ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
// rule RL_mmio_axi4_adapter_rl_handle_non_Ld_St
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St =
mmio_axi4_adapter_f_reqs_from_core$EMPTY_N &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd1 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd2 ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek =
mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop =
mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas &&
!mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop =
mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] &&
mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek =
mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_setPeek ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop =
mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas &&
!mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop =
mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] &&
mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut =
mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas &&
mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut =
!mmio_axi4_adapter_master_xactor_shim_bff_rv[6] &&
mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ;
// rule RL_mmio_axi4_adapter_rl_discard_write_rsp
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp =
!mmio_axi4_adapter_master_xactor_clearing &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[6] &&
b__h4255 != 4'd0 &&
(mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0 ||
mmio_axi4_adapter_f_rsps_to_core$FULL_N) ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp =
CAN_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
!WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek =
mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop =
mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas &&
!mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop =
mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] &&
mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut =
mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas &&
mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ;
// rule RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut =
!mmio_axi4_adapter_master_xactor_shim_rff_rv[72] &&
mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ;
// rule RL_mmio_axi4_adapter_rl_handle_read_rsps
assign CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps =
!mmio_axi4_adapter_master_xactor_clearing &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72] &&
mmio_axi4_adapter_f_rsps_to_core$FULL_N ;
assign WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps =
CAN_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
!WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
!WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ;
// rule RL_mmio_axi4_adapter_master_xactor_do_clear
assign CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear =
mmio_axi4_adapter_master_xactor_clearing ;
assign WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_do_clear =
mmio_axi4_adapter_master_xactor_clearing ;
// rule RL_mmioPlatform_propagateTime
assign CAN_FIRE_RL_mmioPlatform_propagateTime = mmioPlatform_state != 2'd0 ;
assign WILL_FIRE_RL_mmioPlatform_propagateTime =
CAN_FIRE_RL_mmioPlatform_propagateTime ;
// rule RL_mmioPlatform_incCycle
assign CAN_FIRE_RL_mmioPlatform_incCycle =
mmioPlatform_state != 2'd0 &&
mmioPlatform_cycle_57_ULT_99___d458 ;
assign WILL_FIRE_RL_mmioPlatform_incCycle =
CAN_FIRE_RL_mmioPlatform_incCycle ;
// rule RL_mmioPlatform_incTime
assign CAN_FIRE_RL_mmioPlatform_incTime =
mmioPlatform_state == 2'd1 &&
!mmioPlatform_cycle_57_ULT_99___d458 ;
assign WILL_FIRE_RL_mmioPlatform_incTime =
CAN_FIRE_RL_mmioPlatform_incTime ;
// rule RL_mmioPlatform_selectReq
assign CAN_FIRE_RL_mmioPlatform_selectReq =
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ||
core_0$RDY_mmioToPlatform_pRq_enq) &&
NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 &&
mmioPlatform_state == 2'd1 ;
assign WILL_FIRE_RL_mmioPlatform_selectReq =
CAN_FIRE_RL_mmioPlatform_selectReq &&
!WILL_FIRE_RL_mmioPlatform_incTime ;
// rule RL_mmioPlatform_waitTimerInterruptDone
assign CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone =
(!mmioPlatform_waitMTIPCRs ||
core_0$RDY_mmioToPlatform_cRs_deq) &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_curReq[66:64] == 3'd1 ;
assign WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone =
CAN_FIRE_RL_mmioPlatform_waitTimerInterruptDone ;
// rule RL_mmioPlatform_processMSIP
assign CAN_FIRE_RL_mmioPlatform_processMSIP =
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d563 &&
mmioPlatform_curReq[66:64] == 3'd2 &&
mmioPlatform_state == 2'd2 ;
assign WILL_FIRE_RL_mmioPlatform_processMSIP =
CAN_FIRE_RL_mmioPlatform_processMSIP ;
// rule RL_mmioPlatform_waitMSIPDone
assign CAN_FIRE_RL_mmioPlatform_waitMSIPDone =
core_0$RDY_mmioToPlatform_pRs_enq &&
IF_mmioPlatform_waitLowerMSIPCRs_98_THEN_core__ETC___d606 &&
mmioPlatform_curReq[66:64] == 3'd2 &&
mmioPlatform_state == 2'd3 ;
assign WILL_FIRE_RL_mmioPlatform_waitMSIPDone =
CAN_FIRE_RL_mmioPlatform_waitMSIPDone ;
// rule RL_mmioPlatform_processMTimeCmp
assign CAN_FIRE_RL_mmioPlatform_processMTimeCmp =
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14 &&
mmioPlatform_curReq[66:64] == 3'd3 &&
mmioPlatform_state == 2'd2 ;
assign WILL_FIRE_RL_mmioPlatform_processMTimeCmp =
CAN_FIRE_RL_mmioPlatform_processMTimeCmp ;
// rule RL_mmioPlatform_waitMTimeCmpDone
assign CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone =
core_0$RDY_mmioToPlatform_cRs_deq &&
core_0$RDY_mmioToPlatform_pRs_enq &&
mmioPlatform_curReq[66:64] == 3'd3 &&
mmioPlatform_state == 2'd3 ;
assign WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone =
CAN_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
// rule RL_mmioPlatform_processMTime
assign CAN_FIRE_RL_mmioPlatform_processMTime =
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15 &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_curReq[66:64] == 3'd4 ;
assign WILL_FIRE_RL_mmioPlatform_processMTime =
CAN_FIRE_RL_mmioPlatform_processMTime ;
// rule RL_mmioPlatform_waitMTimeDone
assign CAN_FIRE_RL_mmioPlatform_waitMTimeDone =
core_0$RDY_mmioToPlatform_pRs_enq &&
(!mmioPlatform_waitMTIPCRs ||
core_0$RDY_mmioToPlatform_cRs_deq) &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_curReq[66:64] == 3'd4 ;
assign WILL_FIRE_RL_mmioPlatform_waitMTimeDone =
CAN_FIRE_RL_mmioPlatform_waitMTimeDone ;
// rule RL_mmioPlatform_processToHost
assign CAN_FIRE_RL_mmioPlatform_processToHost =
core_0$RDY_mmioToPlatform_pRs_enq &&
(mmioPlatform_reqFunc[5:4] != 2'd2 ||
!mmioPlatform_toHostQ_empty ||
x__h54199 == 64'd0 ||
!mmioPlatform_toHostQ_full) &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_curReq[66:64] == 3'd5 ;
assign WILL_FIRE_RL_mmioPlatform_processToHost =
CAN_FIRE_RL_mmioPlatform_processToHost ;
// rule RL_mmioPlatform_processFromHost
assign CAN_FIRE_RL_mmioPlatform_processFromHost =
core_0$RDY_mmioToPlatform_pRs_enq &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_curReq[66:64] == 3'd6 ;
assign WILL_FIRE_RL_mmioPlatform_processFromHost =
CAN_FIRE_RL_mmioPlatform_processFromHost ;
// rule RL_mmioPlatform_rl_mmio_to_fabric_req
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req =
mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d867 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req =
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;
// rule RL_mmioPlatform_rl_mmio_from_fabric_rsp
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp =
core_0$RDY_mmioToPlatform_pRs_enq &&
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d875 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp =
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ;
// rule RL_mmioPlatform_rl_mmio_to_fabric_amo_req
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req =
mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d880 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req =
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ;
// rule RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp =
core_0$RDY_mmioToPlatform_pRs_enq &&
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
(!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ||
mmio_axi4_adapter_f_reqs_from_core$FULL_N) &&
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d890 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp =
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ;
// rule RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req =
mmio_axi4_adapter_f_reqs_from_core$FULL_N &&
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1082 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req =
CAN_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ;
// rule RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp
assign CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp =
mmio_axi4_adapter_f_rsps_to_core$EMPTY_N &&
IF_mmio_axi4_adapter_f_rsps_to_core_first__77__ETC___d1092 &&
NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1095 ;
assign WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp =
CAN_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ;
// rule RL_mmioPlatform_toHostQ_canonicalize
assign CAN_FIRE_RL_mmioPlatform_toHostQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_canonicalize = 1'd1 ;
// rule RL_mmioPlatform_toHostQ_enqReq_canon
assign CAN_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_enqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_toHostQ_deqReq_canon
assign CAN_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_deqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_toHostQ_clearReq_canon
assign CAN_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_toHostQ_clearReq_canon = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_canonicalize
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_canonicalize = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_enqReq_canon
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_enqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_deqReq_canon
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_deqReq_canon = 1'd1 ;
// rule RL_mmioPlatform_fromHostQ_clearReq_canon
assign CAN_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmioPlatform_fromHostQ_clearReq_canon = 1'd1 ;
// rule RL_propDstIdx_0_canon
assign CAN_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_canon
assign CAN_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_canon = 1'd1 ;
// rule RL_propDstData_0_canon
assign CAN_FIRE_RL_propDstData_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_0_canon = 1'd1 ;
// rule RL_propDstData_1_canon
assign CAN_FIRE_RL_propDstData_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_canon = 1'd1 ;
// rule RL_enqDst_0_canon
assign CAN_FIRE_RL_enqDst_0_canon = 1'd1 ;
assign WILL_FIRE_RL_enqDst_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_0_canon
assign CAN_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_0_canon = 1'd1 ;
// rule RL_propDstIdx_1_1_canon
assign CAN_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstIdx_1_1_canon = 1'd1 ;
// rule RL_propDstData_1_0_canon
assign CAN_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_0_canon = 1'd1 ;
// rule RL_propDstData_1_1_canon
assign CAN_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
assign WILL_FIRE_RL_propDstData_1_1_canon = 1'd1 ;
// rule RL_enqDst_1_0_canon
assign CAN_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
assign WILL_FIRE_RL_enqDst_1_0_canon = 1'd1 ;
// rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay =
llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
llc_mem_server_rg_cacheline_cache_dirty_delay != 10'd0 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ;
// rule RL_llc_mem_server_rl_cacheline_cache_writeback_finish
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish =
llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq &&
!llc$dma_respSt_first[4] &&
llc_mem_server_rg_cacheline_cache_state == 3'd1 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ;
// rule RL_llc_mem_server_rl_cacheline_cache_reload_finish
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish =
llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq &&
!llc$dma_respLd_first[4] &&
llc_mem_server_rg_cacheline_cache_state == 3'd2 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ;
// rule RL_llc_mem_server_srcPropose
assign CAN_FIRE_RL_llc_mem_server_srcPropose =
core_0$RDY_tlbToMem_memReq_first &&
core_0$RDY_tlbToMem_memReq_deq &&
!llc_mem_server_propDstIdx_0_rl ;
assign WILL_FIRE_RL_llc_mem_server_srcPropose =
CAN_FIRE_RL_llc_mem_server_srcPropose ;
// rule RL_llc_mem_server_dstSelectSrc
assign CAN_FIRE_RL_llc_mem_server_dstSelectSrc = 1'd1 ;
assign WILL_FIRE_RL_llc_mem_server_dstSelectSrc = 1'd1 ;
// rule RL_llc_mem_server_doEnq
assign CAN_FIRE_RL_llc_mem_server_doEnq =
llc_mem_server_tlbQ$FULL_N &&
IF_llc_mem_server_enqDst_0_lat_0_whas__833_THE_ETC___d1838 ;
assign WILL_FIRE_RL_llc_mem_server_doEnq =
CAN_FIRE_RL_llc_mem_server_doEnq ;
// rule RL_llc_mem_server_sendLdRespToTlb
assign CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb =
llc$RDY_dma_respLd_first && llc$RDY_dma_respLd_deq &&
core_0$RDY_tlbToMem_respLd_enq &&
llc$dma_respLd_first[4] ;
assign WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb =
CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ;
// rule RL_llc_mem_server_sendStRespToTlb
assign CAN_FIRE_RL_llc_mem_server_sendStRespToTlb =
llc$RDY_dma_respSt_first && llc$RDY_dma_respSt_deq &&
llc$dma_respSt_first[4] ;
assign WILL_FIRE_RL_llc_mem_server_sendStRespToTlb =
CAN_FIRE_RL_llc_mem_server_sendStRespToTlb ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut =
llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas &&
llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut =
!llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] &&
llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut =
llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas &&
llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut =
!llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] &&
llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut =
llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas &&
llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut =
!llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] &&
llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ;
// rule RL_llc_mem_server_rl_handle_MemLoader_ld_req
assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req =
!llc_mem_server_axi4_slave_xactor_clearing &&
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] &&
!llc_mem_server_axi4_slave_xactor_shim_rff_rv[73] &&
(llc_mem_server_rg_cacheline_cache_state == 3'd3 ||
llc_mem_server_rg_cacheline_cache_state == 3'd4) &&
llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1758 ;
assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req =
CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ;
// rule RL_llc_mem_server_rl_handle_MemLoader_st_req
assign CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req =
!llc_mem_server_axi4_slave_xactor_clearing &&
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] &&
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[74] &&
!llc_mem_server_axi4_slave_xactor_shim_bff_rv[7] &&
(llc_mem_server_rg_cacheline_cache_state == 3'd3 ||
llc_mem_server_rg_cacheline_cache_state == 3'd4) &&
llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1659 ;
assign WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req =
CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;
// rule RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged =
llc$RDY_dma_memReq_enq &&
llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
llc_mem_server_rg_cacheline_cache_dirty_delay == 10'd0 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;
// rule RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss =
llc$RDY_dma_memReq_enq &&
!llc_mem_server_axi4_slave_xactor_clearing &&
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] &&
llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
!llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1659 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;
// rule RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss =
llc$RDY_dma_memReq_enq &&
!llc_mem_server_axi4_slave_xactor_clearing &&
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] &&
llc_mem_server_rg_cacheline_cache_state == 3'd4 &&
!llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1758 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss &&
!WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;
// rule RL_llc_mem_server_rl_cacheline_cache_reload_req_st
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st =
!llc_mem_server_axi4_slave_xactor_clearing &&
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[98] &&
llc$RDY_dma_memReq_enq &&
llc_mem_server_rg_cacheline_cache_state == 3'd3 &&
!llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1659 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ;
// rule RL_llc_mem_server_rl_cacheline_cache_reload_req_ld
assign CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld =
!llc_mem_server_axi4_slave_xactor_clearing &&
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[98] &&
llc$RDY_dma_memReq_enq &&
llc_mem_server_rg_cacheline_cache_state == 3'd3 &&
!llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1758 ;
assign WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld =
CAN_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld &&
!WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ;
// rule RL_llc_mem_server_sendTlbReqToLLC
assign CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC =
llc$RDY_dma_memReq_enq && llc_mem_server_tlbQ$EMPTY_N ;
assign WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC =
CAN_FIRE_RL_llc_mem_server_sendTlbReqToLLC &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss &&
!WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek =
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_setPeek ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop =
llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas &&
!llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop =
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] &&
llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek =
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_setPeek ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop =
llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas &&
!llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop ;
// rule RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop =
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] &&
llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ;
// rule RL_llc_mem_server_axi4_slave_xactor_do_clear
assign CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear =
llc_mem_server_axi4_slave_xactor_clearing ;
assign WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_do_clear =
llc_mem_server_axi4_slave_xactor_clearing ;
// rule RL_llc_mem_server_propDstIdx_0_canon
assign CAN_FIRE_RL_llc_mem_server_propDstIdx_0_canon = 1'd1 ;
assign WILL_FIRE_RL_llc_mem_server_propDstIdx_0_canon = 1'd1 ;
// rule RL_llc_mem_server_propDstData_0_canon
assign CAN_FIRE_RL_llc_mem_server_propDstData_0_canon = 1'd1 ;
assign WILL_FIRE_RL_llc_mem_server_propDstData_0_canon = 1'd1 ;
// rule RL_llc_mem_server_enqDst_0_canon
assign CAN_FIRE_RL_llc_mem_server_enqDst_0_canon = 1'd1 ;
assign WILL_FIRE_RL_llc_mem_server_enqDst_0_canon = 1'd1 ;
// rule RL_llc_axi4_adapter_rl_handle_write_req
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
!llc_axi4_adapter_master_xactor_clearing &&
llc$RDY_to_mem_toM_first &&
!llc_axi4_adapter_master_xactor_shim_wff_rv[74] &&
(llc_axi4_adapter_rg_wr_req_beat != 3'd0 ||
!llc_axi4_adapter_master_xactor_shim_awff_rv[98]) &&
(llc_axi4_adapter_rg_wr_req_beat != 3'd7 ||
llc$RDY_to_mem_toM_deq) &&
llc$to_mem_toM_first[644] ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// rule RL_llc_axi4_adapter_rl_handle_read_req
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
!llc_axi4_adapter_master_xactor_clearing &&
llc$RDY_to_mem_toM_first &&
llc$RDY_to_mem_toM_deq &&
!llc_axi4_adapter_master_xactor_shim_arff_rv[98] &&
llc_axi4_adapter_f_pending_reads$FULL_N &&
!llc$to_mem_toM_first[644] &&
b__h168385 == 4'd0 ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek =
llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_setPeek ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop =
llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas &&
!llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop =
llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] &&
llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek =
llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_setPeek ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop =
llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas &&
!llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop =
llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] &&
llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut =
llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas &&
llc_axi4_adapter_master_xactor_shim_bff_rv[7] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut =
!llc_axi4_adapter_master_xactor_shim_bff_rv[7] &&
llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ;
// rule RL_llc_axi4_adapter_rl_discard_write_rsp
assign CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
!llc_axi4_adapter_master_xactor_clearing &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[7] &&
b__h168385 != 4'd0 ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek =
llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_setPeek ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop =
llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas &&
!llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop =
llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] &&
llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut =
llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas &&
llc_axi4_adapter_master_xactor_shim_rff_rv[73] ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut ;
// rule RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut =
!llc_axi4_adapter_master_xactor_shim_rff_rv[73] &&
llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ;
// rule RL_llc_axi4_adapter_rl_handle_read_rsps
assign CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
!llc_axi4_adapter_master_xactor_clearing &&
llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d1978 ;
assign WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// rule RL_llc_axi4_adapter_master_xactor_do_clear
assign CAN_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear =
llc_axi4_adapter_master_xactor_clearing ;
assign WILL_FIRE_RL_llc_axi4_adapter_master_xactor_do_clear =
llc_axi4_adapter_master_xactor_clearing ;
// inputs to muxes for submodule ports
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
!mmioPlatform_reqBE[4] &&
mmioPlatform_reqBE[0] ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 =
WILL_FIRE_RL_mmioPlatform_processMTime &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 =
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746 ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
(!mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 ||
!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 =
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
assign MUX_llc$dma_memReq_enq_1__SEL_1 =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ;
assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ;
assign MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ;
assign MUX_mmioPlatform_amoResp$write_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ;
assign MUX_mmioPlatform_amoResp$write_1__SEL_2 =
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ;
assign MUX_mmioPlatform_curReq$write_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ||
core_0$mmioToPlatform_cRq_notEmpty) ;
assign MUX_mmioPlatform_fetchingWay$write_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) &&
core_0$mmioToPlatform_cRq_notEmpty ;
assign MUX_mmioPlatform_state$write_1__SEL_6 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
WILL_FIRE_RL_mmioPlatform_processFromHost ||
WILL_FIRE_RL_mmioPlatform_processToHost ||
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone ||
EN_start ;
assign MUX_mmioPlatform_state$write_1__SEL_7 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ;
assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 =
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__PSEL_1 &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr ;
assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 =
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] ==
2'd0 ;
assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 =
{ 1'd0, llc$to_child_toC_first[586:1] } ;
assign MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 =
{ 1'd1,
llc$to_child_toC_first[586:521],
llc$to_child_toC_first[519:0] } ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 =
{ 1'd0,
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587,
(mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
mmioPlatform_reqData[31:0] :
x_data__h35020 } ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 =
{ 7'd106,
(IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
!mmioPlatform_mtip_0) ?
32'd1 :
32'd0 } ;
assign MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4 =
{ 7'd106,
(mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
!mmioPlatform_mtip_0) ?
32'd1 :
32'd0 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1 =
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA :
131'h4AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2 =
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA :
{ 67'h60000000000000000,
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d687 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 =
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
131'h2AAAAAAAAAAAAAAA955555554AAAAAAAA :
{ 67'h60000000000000000,
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d752 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 =
{ 65'h0AAAAAAAAAAAAAAAA,
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] &&
mmioPlatform_fetchingWay,
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107,
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ||
mmioPlatform_fetchingWay,
IF_mmio_axi4_adapter_f_rsps_to_core_first__77__ETC___d1114 } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 =
{ 2'd3, mmioPlatform_amoResp } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 =
{ 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 =
{ 67'h60000000000000000,
mmioPlatform_waitLowerMSIPCRs ?
{ 63'd0, core_0$mmioToPlatform_cRs_first } :
{ v__h37337, 32'd0 } } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 =
{ mmioPlatform_reqFunc[5:4] != 2'd0,
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA :
{ (mmioPlatform_reqFunc[5:4] == 2'd2) ?
mmioPlatform_toHostQ_empty :
mmioPlatform_reqFunc[5:4] == 2'd1,
65'd0,
mmioPlatform_toHostQ_empty ?
64'd0 :
mmioPlatform_toHostQ_data_0 } } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 =
{ mmioPlatform_reqFunc[5:4] != 2'd0,
(mmioPlatform_reqFunc[5:4] == 2'd0) ?
130'h2AAAAAAAAAAAAAAA955555554AAAAAAAA :
{ IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_2_ETC___d835,
65'd0,
mmioPlatform_fromHostQ_empty ?
64'd0 :
mmioPlatform_fromHostQ_data_0 } } ;
assign MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ?
{ 2'd3, mmio_axi4_adapter_f_rsps_to_core$D_OUT[128:0] } :
{ 1'd1, mmio_axi4_adapter_f_rsps_to_core$D_OUT } ;
assign MUX_llc$dma_memReq_enq_1__VAL_1 =
{ llc_mem_server_rg_cacheline_cache_addr,
64'hFFFFFFFFFFFFFFFF,
llc_mem_server_rg_cacheline_cache_data,
5'd10 } ;
assign MUX_llc$dma_memReq_enq_1__VAL_2 =
{ line_addr__h115100,
585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ;
assign MUX_llc$dma_memReq_enq_1__VAL_3 =
{ line_addr__h125208,
585'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554A } ;
assign MUX_llc$dma_memReq_enq_1__VAL_4 =
{ llc_mem_server_tlbQ$D_OUT[64:1],
581'h00000000000000001555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555,
llc_mem_server_tlbQ$D_OUT[0],
llc_mem_server_tlbQ$D_OUT[6:4] } ;
assign MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 =
{ llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] !=
2'd3 &&
llc_mem_server_rg_cacheline_cache_data[515],
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] !=
2'd2 &&
llc_mem_server_rg_cacheline_cache_data[514],
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] !=
2'd1 &&
llc_mem_server_rg_cacheline_cache_data[513],
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:33] !=
2'd0 &&
llc_mem_server_rg_cacheline_cache_data[512],
IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1742,
(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd1) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[127:64],
(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd0) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[63:0] } ;
assign MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 =
llc_mem_server_rg_cacheline_cache_dirty_delay - 10'd1 ;
assign MUX_mmioPlatform_amoResp$write_1__VAL_1 =
{ 65'd0,
(mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtimecmp_0 :
IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686 } ;
assign MUX_mmioPlatform_amoResp$write_1__VAL_2 =
{ 65'd0,
(mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtime :
IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751 } ;
assign MUX_mmioPlatform_curReq$write_1__VAL_1 =
(!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ?
67'h1AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[214:154] >= 61'd33554432 &&
core_0$mmioToPlatform_cRq_first[214:154] < 61'd33554433) ?
67'h2AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[214:154] >=
61'd33556480 &&
core_0$mmioToPlatform_cRq_first[214:154] < 61'd33556481) ?
67'h3AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[214:154] ==
61'd33560575) ?
67'h4AAAAAAAAAAAAAAAA :
IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511))) ;
assign MUX_mmioPlatform_curReq$write_1__VAL_2 =
{ 3'd7,
(mmioPlatform_instSel == 2'd3) ?
mmioPlatform_curReq[63:0] + 64'd8 :
mmioPlatform_curReq[63:0] } ;
assign MUX_mmioPlatform_cycle$write_1__VAL_1 = mmioPlatform_cycle + 7'd1 ;
assign MUX_mmioPlatform_fetchingWay$write_1__VAL_2 =
mmioPlatform_fetchingWay + 1'd1 ;
assign MUX_mmioPlatform_instSel$write_1__VAL_2 =
mmioPlatform_instSel + 2'd1 ;
assign MUX_mmioPlatform_mtime$write_1__VAL_2 = mmioPlatform_mtime + 64'd1 ;
assign MUX_mmioPlatform_mtip_0$write_1__VAL_2 =
IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
!mmioPlatform_mtip_0 ;
assign MUX_mmioPlatform_state$write_1__VAL_1 =
(!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) ?
2'd3 :
2'd2 ;
assign MUX_mmioPlatform_state$write_1__VAL_2 =
(mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ?
2'd1 :
((mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
(mmioPlatform_reqBE[0] ? 2'd3 : 2'd1) :
2'd3) ;
always@(mmioPlatform_reqFunc or
IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 or
mmioPlatform_mtip_0)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0: MUX_mmioPlatform_state$write_1__VAL_3 = 2'd1;
2'd1: MUX_mmioPlatform_state$write_1__VAL_3 = mmioPlatform_reqFunc[5:4];
default: MUX_mmioPlatform_state$write_1__VAL_3 =
(IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
!mmioPlatform_mtip_0 ||
!IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
mmioPlatform_mtip_0) ?
2'd3 :
2'd1;
endcase
end
always@(mmioPlatform_reqFunc or
mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 or
mmioPlatform_mtip_0)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0: MUX_mmioPlatform_state$write_1__VAL_4 = 2'd1;
2'd1: MUX_mmioPlatform_state$write_1__VAL_4 = mmioPlatform_reqFunc[5:4];
default: MUX_mmioPlatform_state$write_1__VAL_4 =
(mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
mmioPlatform_mtip_0) ?
2'd3 :
2'd1;
endcase
end
assign MUX_mmioPlatform_state$write_1__VAL_5 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ?
(mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 ?
2'd2 :
2'd1) :
2'd1 ;
assign MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 =
mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
mmioPlatform_mtip_0 ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 =
{ mmioPlatform_curReq[63:0],
6'd42,
mmioPlatform_reqBE,
65'd0,
IF_mmioPlatform_reqSz_95_EQ_0b0_96_THEN_IF_mmi_ETC___d1078 } ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 =
{ mmioPlatform_curReq[63:0],
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587,
mmioPlatform_reqBE,
mmioPlatform_reqData } ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 =
{ mmioPlatform_curReq[63:0],
151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4 =
{ addr1__h66648, 151'h34AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 =
{ 66'd0, mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] } ;
assign MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3 =
{ mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] ==
2'd0,
1'd0,
_0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 } ;
// inlined wires
assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget =
{ master1_bid, master1_bresp } ;
assign mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas =
master1_bvalid &&
!mmio_axi4_adapter_master_xactor_shim_bff_rv[6] ;
assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget =
{ master1_rid,
master1_rdata,
master1_rresp,
master1_rlast,
master1_ruser } ;
assign mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas =
master1_rvalid &&
!mmio_axi4_adapter_master_xactor_shim_rff_rv[72] ;
assign mmioPlatform_toHostQ_enqReq_lat_0$wget = { 1'd1, x__h54199 } ;
assign mmioPlatform_toHostQ_enqReq_lat_0$whas =
WILL_FIRE_RL_mmioPlatform_processToHost &&
mmioPlatform_reqFunc[5:4] == 2'd2 &&
mmioPlatform_toHostQ_empty &&
x__h54199 != 64'd0 ;
assign mmioPlatform_fromHostQ_deqReq_lat_0$whas =
WILL_FIRE_RL_mmioPlatform_processFromHost &&
mmioPlatform_reqFunc[5:4] == 2'd2 &&
!mmioPlatform_fromHostQ_empty &&
x__h51463 == 64'd0 ;
assign propDstIdx_1_lat_1$whas =
!enqDst_0_rl[73] &&
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1197 &&
x__h75482 ;
assign propDstData_0_lat_0$wget =
{ core_0$dCacheToParent_rqToP_first, 1'd0 } ;
assign propDstData_1_lat_0$wget =
{ core_0$iCacheToParent_rqToP_first, 1'd1 } ;
assign enqDst_0_lat_0$wget =
{ 1'd1,
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22,
SEL_ARR_IF_propDstData_0_lat_0_whas__143_THEN__ETC___d1249 } ;
assign enqDst_0_lat_0$whas =
!enqDst_0_rl[73] &&
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1197 ;
assign propDstIdx_1_1_lat_1$whas =
!enqDst_1_0_rl[584] &&
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1434 &&
x__h97768 ;
assign propDstData_1_0_lat_0$wget =
{ core_0$dCacheToParent_rsToP_first, 1'd0 } ;
assign propDstData_1_1_lat_0$wget =
{ core_0$iCacheToParent_rsToP_first, 1'd1 } ;
assign enqDst_1_0_lat_0$wget =
{ 1'd1,
CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q37,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1550 } ;
assign enqDst_1_0_lat_0$whas =
!enqDst_1_0_rl[584] &&
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1434 ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget =
{ debug_module_mem_server_awid,
debug_module_mem_server_awaddr,
debug_module_mem_server_awlen,
debug_module_mem_server_awsize,
debug_module_mem_server_awburst,
debug_module_mem_server_awlock,
debug_module_mem_server_awcache,
debug_module_mem_server_awprot,
debug_module_mem_server_awqos,
debug_module_mem_server_awregion } ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$whas =
debug_module_mem_server_awvalid &&
!llc_mem_server_axi4_slave_xactor_shim_awff_rv[98] ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget =
{ debug_module_mem_server_wdata,
debug_module_mem_server_wstrb,
debug_module_mem_server_wlast,
debug_module_mem_server_wuser } ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$whas =
debug_module_mem_server_wvalid &&
!llc_mem_server_axi4_slave_xactor_shim_wff_rv[74] ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget =
{ debug_module_mem_server_arid,
debug_module_mem_server_araddr,
debug_module_mem_server_arlen,
debug_module_mem_server_arsize,
debug_module_mem_server_arburst,
debug_module_mem_server_arlock,
debug_module_mem_server_arcache,
debug_module_mem_server_arprot,
debug_module_mem_server_arqos,
debug_module_mem_server_arregion } ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$whas =
debug_module_mem_server_arvalid &&
!llc_mem_server_axi4_slave_xactor_shim_arff_rv[98] ;
assign llc_mem_server_propDstIdx_0_lat_1$whas =
!llc_mem_server_enqDst_0_rl[65] &&
IF_llc_mem_server_propDstIdx_0_lat_0_whas__818_ETC___d1821 ;
assign llc_mem_server_enqDst_0_lat_0$wget =
{ 1'd1,
IF_llc_mem_server_propDstData_0_lat_0_whas__82_ETC___d1828 } ;
assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget =
{ master0_bid, master0_bresp } ;
assign llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$whas =
master0_bvalid &&
!llc_axi4_adapter_master_xactor_shim_bff_rv[7] ;
assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget =
{ master0_rid,
master0_rdata,
master0_rresp,
master0_rlast,
master0_ruser } ;
assign llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$whas =
master0_rvalid &&
!llc_axi4_adapter_master_xactor_shim_rff_rv[73] ;
assign mmio_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas =
mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97] &&
master1_awready ;
assign mmio_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas =
mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] &&
master1_wready ;
assign mmio_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas =
mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97] &&
master1_arready ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_b_dropWire$whas =
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[7] &&
debug_module_mem_server_bready ;
assign llc_mem_server_axi4_slave_xactor_ug_slave_u_r_dropWire$whas =
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[73] &&
debug_module_mem_server_rready ;
assign llc_axi4_adapter_master_xactor_ug_master_u_aw_dropWire$whas =
llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[98] &&
master0_awready ;
assign llc_axi4_adapter_master_xactor_ug_master_u_w_dropWire$whas =
llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[74] &&
master0_wready ;
assign llc_axi4_adapter_master_xactor_ug_master_u_ar_dropWire$whas =
llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[98] &&
master0_arready ;
assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr ;
assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 =
{ 5'd16,
mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151],
8'd0,
v_awsize_val__h15184,
18'd65536 } ;
assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read =
mmio_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ?
mmio_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 :
mmio_axi4_adapter_master_xactor_shim_awff_rv ;
assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ?
98'h0AAAAAAAAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read ;
assign mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read =
mmio_axi4_adapter_master_xactor_clearing ?
98'h0AAAAAAAAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_awff_rv$port2__read ;
assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr ;
assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 =
{ 1'd1,
mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0],
mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:129],
2'd2 } ;
assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read =
mmio_axi4_adapter_master_xactor_shim_wff_rv$EN_port0__write ?
mmio_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 :
mmio_axi4_adapter_master_xactor_shim_wff_rv ;
assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_doDrop ?
75'h2AAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read ;
assign mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read =
mmio_axi4_adapter_master_xactor_clearing ?
75'h2AAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_wff_rv$port2__read ;
assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 =
{ 1'd1,
mmio_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ;
assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_doPut ?
mmio_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 :
mmio_axi4_adapter_master_xactor_shim_bff_rv ;
assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read =
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ?
7'd42 :
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read ;
assign mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read =
mmio_axi4_adapter_master_xactor_clearing ?
7'd42 :
mmio_axi4_adapter_master_xactor_shim_bff_rv$port2__read ;
assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr ;
assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 =
{ 5'd16,
mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151],
29'd851968 } ;
assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read =
mmio_axi4_adapter_master_xactor_shim_arff_rv$EN_port0__write ?
mmio_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 :
mmio_axi4_adapter_master_xactor_shim_arff_rv ;
assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ?
98'h0AAAAAAAAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read ;
assign mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read =
mmio_axi4_adapter_master_xactor_clearing ?
98'h0AAAAAAAAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_arff_rv$port2__read ;
assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 =
{ 1'd1,
mmio_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ;
assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read =
CAN_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_doPut ?
mmio_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 :
mmio_axi4_adapter_master_xactor_shim_rff_rv ;
assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ?
73'h0AAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read ;
assign mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read =
mmio_axi4_adapter_master_xactor_clearing ?
73'h0AAAAAAAAAAAAAAAAAA :
mmio_axi4_adapter_master_xactor_shim_rff_rv$port2__read ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
mmio_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
b__h4255 - 4'd1 ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp ?
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
b__h4255 ;
assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 =
{ 1'd1,
llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_putWire$wget } ;
assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_doPut ?
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port0__write_1 :
llc_mem_server_axi4_slave_xactor_shim_awff_rv ;
assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read =
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read ;
assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read =
llc_mem_server_axi4_slave_xactor_clearing ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port2__read ;
assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 =
{ 1'd1,
llc_mem_server_axi4_slave_xactor_ug_slave_u_w_putWire$wget } ;
assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_doPut ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port0__write_1 :
llc_mem_server_axi4_slave_xactor_shim_wff_rv ;
assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read =
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ?
75'h2AAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read ;
assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read =
llc_mem_server_axi4_slave_xactor_clearing ?
75'h2AAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port2__read ;
assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read =
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ?
8'd128 :
llc_mem_server_axi4_slave_xactor_shim_bff_rv ;
assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_doDrop ?
8'd42 :
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read ;
assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read =
llc_mem_server_axi4_slave_xactor_clearing ?
8'd42 :
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port2__read ;
assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 =
{ 1'd1,
llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_putWire$wget } ;
assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_doPut ?
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port0__write_1 :
llc_mem_server_axi4_slave_xactor_shim_arff_rv ;
assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read =
CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read ;
assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$port3__read =
llc_mem_server_axi4_slave_xactor_clearing ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port2__read ;
assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 =
{ 6'd32, dword__h125391, 4'd2 } ;
assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read =
CAN_FIRE_RL_llc_mem_server_rl_handle_MemLoader_ld_req ?
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port0__write_1 :
llc_mem_server_axi4_slave_xactor_shim_rff_rv ;
assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read =
CAN_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_doDrop ?
74'h0AAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read ;
assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read =
llc_mem_server_axi4_slave_xactor_clearing ?
74'h0AAAAAAAAAAAAAAAAAA :
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port2__read ;
assign llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 ;
assign llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 =
{ 6'd32, v_awaddr__h190085, 29'd15532032 } ;
assign llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read =
llc_axi4_adapter_master_xactor_shim_awff_rv$EN_port0__write ?
llc_axi4_adapter_master_xactor_shim_awff_rv$port0__write_1 :
llc_axi4_adapter_master_xactor_shim_awff_rv ;
assign llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_doDrop ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read ;
assign llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read =
llc_axi4_adapter_master_xactor_clearing ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_awff_rv$port2__read ;
assign llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 =
{ 1'd1,
v_wdata__h190496,
v_wstrb__h190497,
llc_axi4_adapter_rg_wr_req_beat == 3'd7,
v_wuser__h190499 } ;
assign llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ?
llc_axi4_adapter_master_xactor_shim_wff_rv$port0__write_1 :
llc_axi4_adapter_master_xactor_shim_wff_rv ;
assign llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_doDrop ?
75'h2AAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read ;
assign llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read =
llc_axi4_adapter_master_xactor_clearing ?
75'h2AAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_wff_rv$port2__read ;
assign llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 =
{ 1'd1,
llc_axi4_adapter_master_xactor_ug_master_u_b_putWire$wget } ;
assign llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_doPut ?
llc_axi4_adapter_master_xactor_shim_bff_rv$port0__write_1 :
llc_axi4_adapter_master_xactor_shim_bff_rv ;
assign llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ?
8'd42 :
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read ;
assign llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read =
llc_axi4_adapter_master_xactor_clearing ?
8'd42 :
llc_axi4_adapter_master_xactor_shim_bff_rv$port2__read ;
assign llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 =
{ 6'd32, line_addr__h168594, 29'd15532032 } ;
assign llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ?
llc_axi4_adapter_master_xactor_shim_arff_rv$port0__write_1 :
llc_axi4_adapter_master_xactor_shim_arff_rv ;
assign llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_doDrop ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read ;
assign llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read =
llc_axi4_adapter_master_xactor_clearing ?
99'h2AAAAAAAAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_arff_rv$port2__read ;
assign llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 =
{ 1'd1,
llc_axi4_adapter_master_xactor_ug_master_u_r_putWire$wget } ;
assign llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read =
CAN_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_doPut ?
llc_axi4_adapter_master_xactor_shim_rff_rv$port0__write_1 :
llc_axi4_adapter_master_xactor_shim_rff_rv ;
assign llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ?
74'h0AAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read ;
assign llc_axi4_adapter_master_xactor_shim_rff_rv$port3__read =
llc_axi4_adapter_master_xactor_clearing ?
74'h0AAAAAAAAAAAAAAAAAA :
llc_axi4_adapter_master_xactor_shim_rff_rv$port2__read ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 =
llc_axi4_adapter_ctr_wr_rsps_pending_crg + 4'd1 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 =
b__h168385 - 4'd1 ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp ?
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port1__write_1 :
b__h168385 ;
// register cfg_verbosity
assign cfg_verbosity$D_IN =
EN_hart0_put_other_req_put ?
hart0_put_other_req_put :
set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ;
// register enqDst_0_rl
assign enqDst_0_rl$D_IN =
{ !CAN_FIRE_RL_doEnq &&
IF_enqDst_0_lat_0_whas__158_THEN_enqDst_0_lat__ETC___d1163,
CAN_FIRE_RL_doEnq ?
73'h0AAAAAAAAAAAAAAAAAA :
(enqDst_0_lat_0$whas ?
enqDst_0_lat_0$wget[72:0] :
enqDst_0_rl[72:0]) } ;
assign enqDst_0_rl$EN = 1'd1 ;
// register enqDst_1_0_rl
assign enqDst_1_0_rl$D_IN =
{ !CAN_FIRE_RL_doEnq_1 &&
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1362,
IF_enqDst_1_0_lat_1_whas__354_THEN_enqDst_1_0__ETC___d1401 } ;
assign enqDst_1_0_rl$EN = 1'd1 ;
// register llc_axi4_adapter_cfg_verbosity
assign llc_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ;
assign llc_axi4_adapter_cfg_verbosity$EN = 1'b0 ;
// register llc_axi4_adapter_ctr_wr_rsps_pending_crg
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
assign llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_clearing
assign llc_axi4_adapter_master_xactor_clearing$D_IN = 1'd0 ;
assign llc_axi4_adapter_master_xactor_clearing$EN =
llc_axi4_adapter_master_xactor_clearing ;
// register llc_axi4_adapter_master_xactor_shim_arff_rv
assign llc_axi4_adapter_master_xactor_shim_arff_rv$D_IN =
llc_axi4_adapter_master_xactor_shim_arff_rv$port3__read ;
assign llc_axi4_adapter_master_xactor_shim_arff_rv$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_shim_awff_rv
assign llc_axi4_adapter_master_xactor_shim_awff_rv$D_IN =
llc_axi4_adapter_master_xactor_shim_awff_rv$port3__read ;
assign llc_axi4_adapter_master_xactor_shim_awff_rv$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_shim_bff_rv
assign llc_axi4_adapter_master_xactor_shim_bff_rv$D_IN =
llc_axi4_adapter_master_xactor_shim_bff_rv$port3__read ;
assign llc_axi4_adapter_master_xactor_shim_bff_rv$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_shim_rff_rv
assign llc_axi4_adapter_master_xactor_shim_rff_rv$D_IN =
llc_axi4_adapter_master_xactor_shim_rff_rv$port3__read ;
assign llc_axi4_adapter_master_xactor_shim_rff_rv$EN = 1'b1 ;
// register llc_axi4_adapter_master_xactor_shim_wff_rv
assign llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN =
llc_axi4_adapter_master_xactor_shim_wff_rv$port3__read ;
assign llc_axi4_adapter_master_xactor_shim_wff_rv$EN = 1'b1 ;
// register llc_axi4_adapter_rg_cline
assign llc_axi4_adapter_rg_cline$D_IN =
IF_llc_axi4_adapter_rg_rd_rsp_beat_971_BIT_0_0_ETC___d2013 ;
assign llc_axi4_adapter_rg_cline$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// register llc_axi4_adapter_rg_rd_req_beat
assign llc_axi4_adapter_rg_rd_req_beat$D_IN = 3'h0 ;
assign llc_axi4_adapter_rg_rd_req_beat$EN = 1'b0 ;
// register llc_axi4_adapter_rg_rd_rsp_beat
assign llc_axi4_adapter_rg_rd_rsp_beat$D_IN =
llc_axi4_adapter_rg_rd_rsp_beat + 3'd1 ;
assign llc_axi4_adapter_rg_rd_rsp_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps ;
// register llc_axi4_adapter_rg_wr_req_beat
assign llc_axi4_adapter_rg_wr_req_beat$D_IN =
llc_axi4_adapter_rg_wr_req_beat + 3'd1 ;
assign llc_axi4_adapter_rg_wr_req_beat$EN =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_write_req ;
// register llc_mem_server_axi4_slave_xactor_clearing
assign llc_mem_server_axi4_slave_xactor_clearing$D_IN = 1'd0 ;
assign llc_mem_server_axi4_slave_xactor_clearing$EN =
llc_mem_server_axi4_slave_xactor_clearing ;
// register llc_mem_server_axi4_slave_xactor_shim_arff_rv
assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$D_IN =
llc_mem_server_axi4_slave_xactor_shim_arff_rv$port3__read ;
assign llc_mem_server_axi4_slave_xactor_shim_arff_rv$EN = 1'b1 ;
// register llc_mem_server_axi4_slave_xactor_shim_awff_rv
assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$D_IN =
llc_mem_server_axi4_slave_xactor_shim_awff_rv$port3__read ;
assign llc_mem_server_axi4_slave_xactor_shim_awff_rv$EN = 1'b1 ;
// register llc_mem_server_axi4_slave_xactor_shim_bff_rv
assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$D_IN =
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port3__read ;
assign llc_mem_server_axi4_slave_xactor_shim_bff_rv$EN = 1'b1 ;
// register llc_mem_server_axi4_slave_xactor_shim_rff_rv
assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$D_IN =
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port3__read ;
assign llc_mem_server_axi4_slave_xactor_shim_rff_rv$EN = 1'b1 ;
// register llc_mem_server_axi4_slave_xactor_shim_wff_rv
assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$D_IN =
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port3__read ;
assign llc_mem_server_axi4_slave_xactor_shim_wff_rv$EN = 1'b1 ;
// register llc_mem_server_enqDst_0_rl
assign llc_mem_server_enqDst_0_rl$D_IN =
{ !CAN_FIRE_RL_llc_mem_server_doEnq &&
IF_llc_mem_server_enqDst_0_lat_0_whas__833_THE_ETC___d1838,
CAN_FIRE_RL_llc_mem_server_doEnq ?
65'h0AAAAAAAAAAAAAAAA :
(llc_mem_server_propDstIdx_0_lat_1$whas ?
llc_mem_server_enqDst_0_lat_0$wget[64:0] :
llc_mem_server_enqDst_0_rl[64:0]) } ;
assign llc_mem_server_enqDst_0_rl$EN = 1'd1 ;
// register llc_mem_server_propDstData_0_rl
assign llc_mem_server_propDstData_0_rl$D_IN =
IF_llc_mem_server_propDstData_0_lat_0_whas__82_ETC___d1828 ;
assign llc_mem_server_propDstData_0_rl$EN = 1'd1 ;
// register llc_mem_server_propDstIdx_0_rl
assign llc_mem_server_propDstIdx_0_rl$D_IN =
!llc_mem_server_propDstIdx_0_lat_1$whas &&
IF_llc_mem_server_propDstIdx_0_lat_0_whas__818_ETC___d1821 ;
assign llc_mem_server_propDstIdx_0_rl$EN = 1'd1 ;
// register llc_mem_server_rg_cacheline_cache_addr
assign llc_mem_server_rg_cacheline_cache_addr$D_IN =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ?
line_addr__h115100 :
line_addr__h125208 ;
assign llc_mem_server_rg_cacheline_cache_addr$EN =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ;
// register llc_mem_server_rg_cacheline_cache_data
assign llc_mem_server_rg_cacheline_cache_data$D_IN =
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ?
MUX_llc_mem_server_rg_cacheline_cache_data$write_1__VAL_1 :
llc$dma_respLd_first[520:5] ;
assign llc_mem_server_rg_cacheline_cache_data$EN =
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ;
// register llc_mem_server_rg_cacheline_cache_dirty_delay
assign llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN =
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ?
10'd1023 :
MUX_llc_mem_server_rg_cacheline_cache_dirty_delay$write_1__VAL_2 ;
assign llc_mem_server_rg_cacheline_cache_dirty_delay$EN =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_delay ||
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;
// register llc_mem_server_rg_cacheline_cache_state
always@(MUX_llc$dma_memReq_enq_1__SEL_1 or
MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2 or
MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3 or
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req)
begin
case (1'b1) // synopsys parallel_case
MUX_llc$dma_memReq_enq_1__SEL_1:
llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd1;
MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_2:
llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd2;
MUX_llc_mem_server_rg_cacheline_cache_state$write_1__SEL_3:
llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd3;
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req:
llc_mem_server_rg_cacheline_cache_state$D_IN = 3'd4;
default: llc_mem_server_rg_cacheline_cache_state$D_IN =
3'b010 /* unspecified value */ ;
endcase
end
assign llc_mem_server_rg_cacheline_cache_state$EN =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ||
WILL_FIRE_RL_llc_mem_server_rl_handle_MemLoader_st_req ;
// register mmioPlatform_amoResp
assign mmioPlatform_amoResp$D_IN =
MUX_mmioPlatform_amoResp$write_1__SEL_1 ?
MUX_mmioPlatform_amoResp$write_1__VAL_1 :
MUX_mmioPlatform_amoResp$write_1__VAL_2 ;
assign mmioPlatform_amoResp$EN =
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ;
// register mmioPlatform_curReq
assign mmioPlatform_curReq$D_IN =
MUX_mmioPlatform_curReq$write_1__SEL_1 ?
MUX_mmioPlatform_curReq$write_1__VAL_1 :
MUX_mmioPlatform_curReq$write_1__VAL_2 ;
assign mmioPlatform_curReq$EN =
MUX_mmioPlatform_curReq$write_1__SEL_1 ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] &&
mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 ;
// register mmioPlatform_cycle
assign mmioPlatform_cycle$D_IN =
WILL_FIRE_RL_mmioPlatform_incCycle ?
MUX_mmioPlatform_cycle$write_1__VAL_1 :
7'd0 ;
assign mmioPlatform_cycle$EN =
WILL_FIRE_RL_mmioPlatform_incCycle ||
WILL_FIRE_RL_mmioPlatform_incTime ;
// register mmioPlatform_fetchedInsts_0
assign mmioPlatform_fetchedInsts_0$D_IN =
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107 ;
assign mmioPlatform_fetchedInsts_0$EN =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] &&
mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 &&
!mmioPlatform_fetchingWay ;
// register mmioPlatform_fetchingWay
assign mmioPlatform_fetchingWay$D_IN =
!MUX_mmioPlatform_fetchingWay$write_1__SEL_1 &&
MUX_mmioPlatform_fetchingWay$write_1__VAL_2 ;
assign mmioPlatform_fetchingWay$EN =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) &&
core_0$mmioToPlatform_cRq_notEmpty ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] &&
mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 ;
// register mmioPlatform_fromHostAddr
assign mmioPlatform_fromHostAddr$D_IN = start_fromhostAddr[63:3] ;
assign mmioPlatform_fromHostAddr$EN = EN_start ;
// register mmioPlatform_fromHostQ_clearReq_rl
assign mmioPlatform_fromHostQ_clearReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_fromHostQ_clearReq_rl$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_data_0
assign mmioPlatform_fromHostQ_data_0$D_IN =
mmioPlatform_fromHostQ_enqReq_rl[63:0] ;
assign mmioPlatform_fromHostQ_data_0$EN =
!mmioPlatform_fromHostQ_clearReq_rl &&
mmioPlatform_fromHostQ_enqReq_rl[64] ;
// register mmioPlatform_fromHostQ_deqReq_rl
assign mmioPlatform_fromHostQ_deqReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_fromHostQ_deqReq_rl$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_empty
assign mmioPlatform_fromHostQ_empty$D_IN =
mmioPlatform_fromHostQ_clearReq_rl ||
!mmioPlatform_fromHostQ_enqReq_rl[64] &&
(mmioPlatform_fromHostQ_deqReq_lat_0$whas ||
mmioPlatform_fromHostQ_deqReq_rl ||
mmioPlatform_fromHostQ_empty) ;
assign mmioPlatform_fromHostQ_empty$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_enqReq_rl
assign mmioPlatform_fromHostQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign mmioPlatform_fromHostQ_enqReq_rl$EN = 1'd1 ;
// register mmioPlatform_fromHostQ_full
assign mmioPlatform_fromHostQ_full$D_IN =
!mmioPlatform_fromHostQ_clearReq_rl &&
(mmioPlatform_fromHostQ_enqReq_rl[64] ||
!mmioPlatform_fromHostQ_deqReq_lat_0$whas &&
!mmioPlatform_fromHostQ_deqReq_rl &&
mmioPlatform_fromHostQ_full) ;
assign mmioPlatform_fromHostQ_full$EN = 1'd1 ;
// register mmioPlatform_instSel
assign mmioPlatform_instSel$D_IN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ?
core_0$mmioToPlatform_cRq_first[154:153] :
MUX_mmioPlatform_instSel$write_1__VAL_2 ;
assign mmioPlatform_instSel$EN =
WILL_FIRE_RL_mmioPlatform_selectReq &&
(mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467) &&
core_0$mmioToPlatform_cRq_notEmpty ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] &&
mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 ;
// register mmioPlatform_mtime
assign mmioPlatform_mtime$D_IN =
MUX_mmioPlatform_amoResp$write_1__SEL_2 ?
newData__h42646 :
MUX_mmioPlatform_mtime$write_1__VAL_2 ;
assign mmioPlatform_mtime$EN =
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 ||
WILL_FIRE_RL_mmioPlatform_incTime ;
// register mmioPlatform_mtimecmp_0
assign mmioPlatform_mtimecmp_0$D_IN = newData__h37921 ;
assign mmioPlatform_mtimecmp_0$EN =
MUX_mmioPlatform_amoResp$write_1__SEL_1 ;
// register mmioPlatform_mtip_0
assign mmioPlatform_mtip_0$D_IN =
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 ||
MUX_mmioPlatform_mtip_0$write_1__VAL_2 ;
assign mmioPlatform_mtip_0$EN =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 ;
// register mmioPlatform_reqAmofunc
assign mmioPlatform_reqAmofunc$D_IN =
(core_0$mmioToPlatform_cRq_first[150:149] != 2'd0 &&
core_0$mmioToPlatform_cRq_first[150:149] != 2'd1 &&
core_0$mmioToPlatform_cRq_first[150:149] != 2'd2) ?
core_0$mmioToPlatform_cRq_first[148:145] :
4'd9 ;
assign mmioPlatform_reqAmofunc$EN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqBE
assign mmioPlatform_reqBE$D_IN = core_0$mmioToPlatform_cRq_first[144:129] ;
assign mmioPlatform_reqBE$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqData
assign mmioPlatform_reqData$D_IN = core_0$mmioToPlatform_cRq_first[128:0] ;
assign mmioPlatform_reqData$EN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqFunc
always@(core_0$mmioToPlatform_cRq_first)
begin
case (core_0$mmioToPlatform_cRq_first[150:149])
2'd0, 2'd1, 2'd2:
mmioPlatform_reqFunc$D_IN =
core_0$mmioToPlatform_cRq_first[150:145];
2'd3:
mmioPlatform_reqFunc$D_IN =
{ 2'd3, core_0$mmioToPlatform_cRq_first[148:145] };
endcase
end
assign mmioPlatform_reqFunc$EN =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_reqSz
assign mmioPlatform_reqSz$D_IN = 2'b11 ;
assign mmioPlatform_reqSz$EN = MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
// register mmioPlatform_state
always@(MUX_mmioPlatform_curReq$write_1__SEL_1 or
MUX_mmioPlatform_state$write_1__VAL_1 or
WILL_FIRE_RL_mmioPlatform_processMSIP or
MUX_mmioPlatform_state$write_1__VAL_2 or
WILL_FIRE_RL_mmioPlatform_processMTimeCmp or
MUX_mmioPlatform_state$write_1__VAL_3 or
WILL_FIRE_RL_mmioPlatform_processMTime or
MUX_mmioPlatform_state$write_1__VAL_4 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp or
MUX_mmioPlatform_state$write_1__VAL_5 or
MUX_mmioPlatform_state$write_1__SEL_6 or
MUX_mmioPlatform_state$write_1__SEL_7)
begin
case (1'b1) // synopsys parallel_case
MUX_mmioPlatform_curReq$write_1__SEL_1:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_1;
WILL_FIRE_RL_mmioPlatform_processMSIP:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_2;
WILL_FIRE_RL_mmioPlatform_processMTimeCmp:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_3;
WILL_FIRE_RL_mmioPlatform_processMTime:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_4;
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp:
mmioPlatform_state$D_IN = MUX_mmioPlatform_state$write_1__VAL_5;
MUX_mmioPlatform_state$write_1__SEL_6: mmioPlatform_state$D_IN = 2'd1;
MUX_mmioPlatform_state$write_1__SEL_7: mmioPlatform_state$D_IN = 2'd3;
default: mmioPlatform_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign mmioPlatform_state$EN =
MUX_mmioPlatform_curReq$write_1__SEL_1 ||
WILL_FIRE_RL_mmioPlatform_processMSIP ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp ||
WILL_FIRE_RL_mmioPlatform_processMTime ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
WILL_FIRE_RL_mmioPlatform_processFromHost ||
WILL_FIRE_RL_mmioPlatform_processToHost ||
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone ||
EN_start ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ;
// register mmioPlatform_toHostAddr
assign mmioPlatform_toHostAddr$D_IN = start_tohostAddr[63:3] ;
assign mmioPlatform_toHostAddr$EN = EN_start ;
// register mmioPlatform_toHostQ_clearReq_rl
assign mmioPlatform_toHostQ_clearReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_toHostQ_clearReq_rl$EN = 1'd1 ;
// register mmioPlatform_toHostQ_data_0
assign mmioPlatform_toHostQ_data_0$D_IN =
mmioPlatform_toHostQ_enqReq_lat_0$whas ?
mmioPlatform_toHostQ_enqReq_lat_0$wget[63:0] :
mmioPlatform_toHostQ_enqReq_rl[63:0] ;
assign mmioPlatform_toHostQ_data_0$EN =
!mmioPlatform_toHostQ_clearReq_rl &&
IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 ;
// register mmioPlatform_toHostQ_deqReq_rl
assign mmioPlatform_toHostQ_deqReq_rl$D_IN = 1'd0 ;
assign mmioPlatform_toHostQ_deqReq_rl$EN = 1'd1 ;
// register mmioPlatform_toHostQ_empty
assign mmioPlatform_toHostQ_empty$D_IN =
mmioPlatform_toHostQ_clearReq_rl ||
(mmioPlatform_toHostQ_enqReq_lat_0$whas ?
!mmioPlatform_toHostQ_enqReq_lat_0$wget[64] :
!mmioPlatform_toHostQ_enqReq_rl[64]) ;
assign mmioPlatform_toHostQ_empty$EN = 1'd1 ;
// register mmioPlatform_toHostQ_enqReq_rl
assign mmioPlatform_toHostQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign mmioPlatform_toHostQ_enqReq_rl$EN = 1'd1 ;
// register mmioPlatform_toHostQ_full
assign mmioPlatform_toHostQ_full$D_IN =
!mmioPlatform_toHostQ_clearReq_rl &&
(IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 ||
!(!mmioPlatform_toHostQ_empty) &&
!mmioPlatform_toHostQ_deqReq_rl &&
mmioPlatform_toHostQ_full) ;
assign mmioPlatform_toHostQ_full$EN = 1'd1 ;
// register mmioPlatform_waitLowerMSIPCRs
assign mmioPlatform_waitLowerMSIPCRs$D_IN =
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 ||
mmioPlatform_reqBE[0] ;
assign mmioPlatform_waitLowerMSIPCRs$EN =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596 ;
// register mmioPlatform_waitMTIPCRs
assign mmioPlatform_waitMTIPCRs$D_IN =
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 ||
MUX_mmioPlatform_waitMTIPCRs$write_1__VAL_2 ;
assign mmioPlatform_waitMTIPCRs$EN =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 ;
// register mmioPlatform_waitUpperMSIPCRs
assign mmioPlatform_waitUpperMSIPCRs$D_IN = 1'd0 ;
assign mmioPlatform_waitUpperMSIPCRs$EN =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596 ;
// register mmio_axi4_adapter_cfg_verbosity
assign mmio_axi4_adapter_cfg_verbosity$D_IN = 4'h0 ;
assign mmio_axi4_adapter_cfg_verbosity$EN = 1'b0 ;
// register mmio_axi4_adapter_ctr_wr_rsps_pending_crg
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN =
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port2__read ;
assign mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_clearing
assign mmio_axi4_adapter_master_xactor_clearing$D_IN = 1'd0 ;
assign mmio_axi4_adapter_master_xactor_clearing$EN =
mmio_axi4_adapter_master_xactor_clearing ;
// register mmio_axi4_adapter_master_xactor_shim_arff_rv
assign mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN =
mmio_axi4_adapter_master_xactor_shim_arff_rv$port3__read ;
assign mmio_axi4_adapter_master_xactor_shim_arff_rv$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_shim_awff_rv
assign mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN =
mmio_axi4_adapter_master_xactor_shim_awff_rv$port3__read ;
assign mmio_axi4_adapter_master_xactor_shim_awff_rv$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_shim_bff_rv
assign mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN =
mmio_axi4_adapter_master_xactor_shim_bff_rv$port3__read ;
assign mmio_axi4_adapter_master_xactor_shim_bff_rv$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_shim_rff_rv
assign mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN =
mmio_axi4_adapter_master_xactor_shim_rff_rv$port3__read ;
assign mmio_axi4_adapter_master_xactor_shim_rff_rv$EN = 1'b1 ;
// register mmio_axi4_adapter_master_xactor_shim_wff_rv
assign mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN =
mmio_axi4_adapter_master_xactor_shim_wff_rv$port3__read ;
assign mmio_axi4_adapter_master_xactor_shim_wff_rv$EN = 1'b1 ;
// register mmio_axi4_adapter_read_req_addr
assign mmio_axi4_adapter_read_req_addr$D_IN =
mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ;
assign mmio_axi4_adapter_read_req_addr$EN =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr ;
// register propDstData_0_rl
assign propDstData_0_rl$D_IN =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget :
propDstData_0_rl ;
assign propDstData_0_rl$EN = 1'd1 ;
// register propDstData_1_0_rl
assign propDstData_1_0_rl$D_IN =
{ IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1286,
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1291,
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[517] :
propDstData_1_0_rl[517],
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[516:1] :
propDstData_1_0_rl[516:1],
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1312 } ;
assign propDstData_1_0_rl$EN = 1'd1 ;
// register propDstData_1_1_rl
assign propDstData_1_1_rl$D_IN =
{ IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1324,
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1329,
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[517] :
propDstData_1_1_rl[517],
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[516:1] :
propDstData_1_1_rl[516:1],
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1350 } ;
assign propDstData_1_1_rl$EN = 1'd1 ;
// register propDstData_1_rl
assign propDstData_1_rl$D_IN =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget :
propDstData_1_rl ;
assign propDstData_1_rl$EN = 1'd1 ;
// register propDstIdx_0_rl
assign propDstIdx_0_rl$D_IN =
!NOT_enqDst_0_rl_161_BIT_73_162_167_AND_SEL_ARR_ETC___d1255 &&
IF_propDstIdx_0_lat_0_whas__129_THEN_propDstId_ETC___d1132 ;
assign propDstIdx_0_rl$EN = 1'd1 ;
// register propDstIdx_1_0_rl
assign propDstIdx_1_0_rl$D_IN =
!NOT_enqDst_1_0_rl_360_BIT_584_361_366_AND_SEL__ETC___d1556 &&
IF_propDstIdx_1_0_lat_0_whas__266_THEN_propDst_ETC___d1269 ;
assign propDstIdx_1_0_rl$EN = 1'd1 ;
// register propDstIdx_1_1_rl
assign propDstIdx_1_1_rl$D_IN =
!propDstIdx_1_1_lat_1$whas &&
IF_propDstIdx_1_1_lat_0_whas__273_THEN_propDst_ETC___d1276 ;
assign propDstIdx_1_1_rl$EN = 1'd1 ;
// register propDstIdx_1_rl
assign propDstIdx_1_rl$D_IN =
!propDstIdx_1_lat_1$whas &&
IF_propDstIdx_1_lat_0_whas__136_THEN_propDstId_ETC___d1139 ;
assign propDstIdx_1_rl$EN = 1'd1 ;
// register srcRR_0
assign srcRR_0$D_IN = srcRR_0 + 1'd1 ;
assign srcRR_0$EN = enqDst_0_lat_0$whas ;
// register srcRR_1_0
assign srcRR_1_0$D_IN = srcRR_1_0 + 1'd1 ;
assign srcRR_1_0$EN = enqDst_1_0_lat_0$whas ;
// submodule core_0
assign core_0$coreReq_perfReq_loc = 4'h0 ;
assign core_0$coreReq_perfReq_t = 5'h0 ;
assign core_0$coreReq_start_fromHostAddr = start_fromhostAddr ;
assign core_0$coreReq_start_startpc = start_startpc ;
assign core_0$coreReq_start_toHostAddr = start_tohostAddr ;
assign core_0$dCacheToParent_fromP_enq_x =
WILL_FIRE_RL_sendPRq ?
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 :
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ;
assign core_0$hart0_csr_mem_server_request_put =
hart0_csr_mem_server_request_put ;
assign core_0$hart0_fpr_mem_server_request_put =
hart0_fpr_mem_server_request_put ;
assign core_0$hart0_gpr_mem_server_request_put =
hart0_gpr_mem_server_request_put ;
assign core_0$hart0_run_halt_server_request_put =
hart0_run_halt_server_request_put ;
assign core_0$iCacheToParent_fromP_enq_x =
WILL_FIRE_RL_sendPRq_1 ?
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_1 :
MUX_core_0$dCacheToParent_fromP_enq_1__VAL_2 ;
always@(MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1 or
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2 or
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2 or
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3 or
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3 or
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4 or
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_1:
core_0$mmioToPlatform_pRq_enq_x = 39'h6A00000001;
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_2:
core_0$mmioToPlatform_pRq_enq_x =
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_2;
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_3:
core_0$mmioToPlatform_pRq_enq_x =
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_3;
MUX_core_0$mmioToPlatform_pRq_enq_1__SEL_4:
core_0$mmioToPlatform_pRq_enq_x =
MUX_core_0$mmioToPlatform_pRq_enq_1__VAL_4;
default: core_0$mmioToPlatform_pRq_enq_x =
39'h2AAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4 or
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5 or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6 or
WILL_FIRE_RL_mmioPlatform_waitMSIPDone or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7 or
WILL_FIRE_RL_mmioPlatform_processToHost or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8 or
WILL_FIRE_RL_mmioPlatform_processFromHost or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp or
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10)
begin
case (1'b1) // synopsys parallel_case
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_1:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_1;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_2:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_2;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_3:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_3;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_4:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_4;
MUX_core_0$mmioToPlatform_pRs_enq_1__SEL_5:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_5;
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_6;
WILL_FIRE_RL_mmioPlatform_waitMSIPDone:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_7;
WILL_FIRE_RL_mmioPlatform_processToHost:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_8;
WILL_FIRE_RL_mmioPlatform_processFromHost:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_9;
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp:
core_0$mmioToPlatform_pRs_enq_x =
MUX_core_0$mmioToPlatform_pRs_enq_1__VAL_10;
default: core_0$mmioToPlatform_pRs_enq_x =
131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign core_0$mmioToPlatform_setTime_t = mmioPlatform_mtime ;
assign core_0$recvDoStats_x = core_0$sendDoStats ;
assign core_0$setMEIP_v = m_external_interrupt_req_set_not_clear ;
assign core_0$setSEIP_v = s_external_interrupt_req_set_not_clear ;
assign core_0$tlbToMem_respLd_enq_x =
{ ld_data__h163305, llc$dma_respLd_first[3] } ;
assign core_0$EN_coreReq_start = EN_start ;
assign core_0$EN_coreReq_perfReq = 1'b0 ;
assign core_0$EN_coreIndInv_perfResp = 1'b0 ;
assign core_0$EN_coreIndInv_terminate = core_0$RDY_coreIndInv_terminate ;
assign core_0$EN_dCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_2 ;
assign core_0$EN_dCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose ;
assign core_0$EN_dCacheToParent_fromP_enq =
WILL_FIRE_RL_sendPRq || WILL_FIRE_RL_sendPRs ;
assign core_0$EN_iCacheToParent_rsToP_deq = CAN_FIRE_RL_srcPropose_3 ;
assign core_0$EN_iCacheToParent_rqToP_deq = CAN_FIRE_RL_srcPropose_1 ;
assign core_0$EN_iCacheToParent_fromP_enq =
WILL_FIRE_RL_sendPRq_1 || WILL_FIRE_RL_sendPRs_1 ;
assign core_0$EN_tlbToMem_memReq_deq =
CAN_FIRE_RL_llc_mem_server_srcPropose ;
assign core_0$EN_tlbToMem_respLd_enq =
CAN_FIRE_RL_llc_mem_server_sendLdRespToTlb ;
assign core_0$EN_mmioToPlatform_cRq_deq =
MUX_mmioPlatform_fetchingWay$write_1__SEL_1 ;
assign core_0$EN_mmioToPlatform_pRs_enq =
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573 ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746 ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp &&
(!mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 ||
!mmio_axi4_adapter_f_rsps_to_core$D_OUT[129]) ||
WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone ||
WILL_FIRE_RL_mmioPlatform_processToHost ||
WILL_FIRE_RL_mmioPlatform_processFromHost ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ;
assign core_0$EN_mmioToPlatform_pRq_enq =
WILL_FIRE_RL_mmioPlatform_selectReq && !mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ||
WILL_FIRE_RL_mmioPlatform_processMSIP &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
!mmioPlatform_reqBE[4] &&
mmioPlatform_reqBE[0] ||
WILL_FIRE_RL_mmioPlatform_processMTimeCmp &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 ||
WILL_FIRE_RL_mmioPlatform_processMTime &&
NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 ;
assign core_0$EN_mmioToPlatform_cRs_deq =
(WILL_FIRE_RL_mmioPlatform_waitMTimeDone ||
WILL_FIRE_RL_mmioPlatform_waitTimerInterruptDone) &&
mmioPlatform_waitMTIPCRs ||
WILL_FIRE_RL_mmioPlatform_waitMSIPDone &&
(mmioPlatform_waitLowerMSIPCRs ||
mmioPlatform_waitUpperMSIPCRs) ||
WILL_FIRE_RL_mmioPlatform_waitMTimeCmpDone ;
assign core_0$EN_mmioToPlatform_setTime =
CAN_FIRE_RL_mmioPlatform_propagateTime ;
assign core_0$EN_sendDoStats = core_0$RDY_sendDoStats ;
assign core_0$EN_recvDoStats = core_0$RDY_sendDoStats ;
assign core_0$EN_deadlock_dCacheCRqStuck_get =
core_0$RDY_deadlock_dCacheCRqStuck_get ;
assign core_0$EN_deadlock_dCachePRqStuck_get =
core_0$RDY_deadlock_dCachePRqStuck_get ;
assign core_0$EN_deadlock_iCacheCRqStuck_get =
core_0$RDY_deadlock_iCacheCRqStuck_get ;
assign core_0$EN_deadlock_iCachePRqStuck_get =
core_0$RDY_deadlock_iCachePRqStuck_get ;
assign core_0$EN_deadlock_renameInstStuck_get =
core_0$RDY_deadlock_renameInstStuck_get ;
assign core_0$EN_deadlock_renameCorrectPathStuck_get =
core_0$RDY_deadlock_renameCorrectPathStuck_get ;
assign core_0$EN_deadlock_commitInstStuck_get =
core_0$RDY_deadlock_commitInstStuck_get ;
assign core_0$EN_deadlock_commitUserInstStuck_get =
core_0$RDY_deadlock_commitUserInstStuck_get ;
assign core_0$EN_deadlock_checkStarted_get =
core_0$RDY_deadlock_checkStarted_get ;
assign core_0$EN_renameDebug_renameErr_get =
core_0$RDY_renameDebug_renameErr_get ;
assign core_0$EN_setMEIP = 1'd1 ;
assign core_0$EN_setSEIP = 1'd1 ;
assign core_0$EN_hart0_run_halt_server_request_put =
EN_hart0_run_halt_server_request_put ;
assign core_0$EN_hart0_run_halt_server_response_get =
EN_hart0_run_halt_server_response_get ;
assign core_0$EN_hart0_gpr_mem_server_request_put =
EN_hart0_gpr_mem_server_request_put ;
assign core_0$EN_hart0_gpr_mem_server_response_get =
EN_hart0_gpr_mem_server_response_get ;
assign core_0$EN_hart0_fpr_mem_server_request_put =
EN_hart0_fpr_mem_server_request_put ;
assign core_0$EN_hart0_fpr_mem_server_response_get =
EN_hart0_fpr_mem_server_response_get ;
assign core_0$EN_hart0_csr_mem_server_request_put =
EN_hart0_csr_mem_server_request_put ;
assign core_0$EN_hart0_csr_mem_server_response_get =
EN_hart0_csr_mem_server_response_get ;
// submodule llc
always@(MUX_llc$dma_memReq_enq_1__SEL_1 or
MUX_llc$dma_memReq_enq_1__VAL_1 or
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st or
MUX_llc$dma_memReq_enq_1__VAL_2 or
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld or
MUX_llc$dma_memReq_enq_1__VAL_3 or
WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC or
MUX_llc$dma_memReq_enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_llc$dma_memReq_enq_1__SEL_1:
llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_1;
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st:
llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_2;
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld:
llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_3;
WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC:
llc$dma_memReq_enq_x = MUX_llc$dma_memReq_enq_1__VAL_4;
default: llc$dma_memReq_enq_x =
649'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign llc$perf_req_r = 4'h0 ;
assign llc$perf_setStatus_doStats = core_0$sendDoStats ;
assign llc$to_child_rqFromC_enq_x =
enqDst_0_lat_0$whas ?
enqDst_0_lat_0$wget[72:0] :
enqDst_0_rl[72:0] ;
assign llc$to_child_rsFromC_enq_x =
{ IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1372,
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1377,
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1382,
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1392,
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1398 } ;
assign llc$to_mem_rsFromM_enq_x =
{ IF_llc_axi4_adapter_rg_rd_rsp_beat_971_BIT_0_0_ETC___d2013,
llc_axi4_adapter_f_pending_reads$D_OUT[4:0] } ;
assign llc$EN_to_child_rsFromC_enq = CAN_FIRE_RL_doEnq_1 ;
assign llc$EN_to_child_rqFromC_enq = CAN_FIRE_RL_doEnq ;
assign llc$EN_to_child_toC_deq =
WILL_FIRE_RL_sendPRs_1 || WILL_FIRE_RL_sendPRq_1 ||
WILL_FIRE_RL_sendPRs ||
WILL_FIRE_RL_sendPRq ;
assign llc$EN_dma_memReq_enq =
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_ld_miss ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_st_miss ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_dirty_aged ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_st ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_req_ld ||
WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ;
assign llc$EN_dma_respLd_deq =
WILL_FIRE_RL_llc_mem_server_sendLdRespToTlb ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_reload_finish ;
assign llc$EN_dma_respSt_deq =
WILL_FIRE_RL_llc_mem_server_sendStRespToTlb ||
WILL_FIRE_RL_llc_mem_server_rl_cacheline_cache_writeback_finish ;
assign llc$EN_to_mem_toM_deq =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd7 ||
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
assign llc$EN_to_mem_rsFromM_enq =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
assign llc$EN_cRqStuck_get = 1'b0 ;
assign llc$EN_perf_setStatus = core_0$RDY_sendDoStats ;
assign llc$EN_perf_req = 1'b0 ;
assign llc$EN_perf_resp = 1'b0 ;
// submodule llc_axi4_adapter_f_pending_reads
assign llc_axi4_adapter_f_pending_reads$D_IN = llc$to_mem_toM_first[68:0] ;
assign llc_axi4_adapter_f_pending_reads$ENQ =
CAN_FIRE_RL_llc_axi4_adapter_rl_handle_read_req ;
assign llc_axi4_adapter_f_pending_reads$DEQ =
WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 ;
assign llc_axi4_adapter_f_pending_reads$CLR = 1'b0 ;
// submodule llc_mem_server_f_dword_in_line
assign llc_mem_server_f_dword_in_line$D_IN = 3'h0 ;
assign llc_mem_server_f_dword_in_line$ENQ = 1'b0 ;
assign llc_mem_server_f_dword_in_line$DEQ = 1'b0 ;
assign llc_mem_server_f_dword_in_line$CLR = 1'b0 ;
// submodule llc_mem_server_tlbQ
assign llc_mem_server_tlbQ$D_IN =
llc_mem_server_propDstIdx_0_lat_1$whas ?
llc_mem_server_enqDst_0_lat_0$wget[64:0] :
llc_mem_server_enqDst_0_rl[64:0] ;
assign llc_mem_server_tlbQ$ENQ = CAN_FIRE_RL_llc_mem_server_doEnq ;
assign llc_mem_server_tlbQ$DEQ =
WILL_FIRE_RL_llc_mem_server_sendTlbReqToLLC ;
assign llc_mem_server_tlbQ$CLR = 1'b0 ;
// submodule mmio_axi4_adapter_f_reqs_from_core
always@(MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1 or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3 or
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req or
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__SEL_1:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_1;
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_2;
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_3;
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req:
mmio_axi4_adapter_f_reqs_from_core$D_IN =
MUX_mmio_axi4_adapter_f_reqs_from_core$enq_1__VAL_4;
default: mmio_axi4_adapter_f_reqs_from_core$D_IN =
215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign mmio_axi4_adapter_f_reqs_from_core$ENQ =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp &&
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_amo_req ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_to_fabric_ifetch_req ;
assign mmio_axi4_adapter_f_reqs_from_core$DEQ =
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req ;
assign mmio_axi4_adapter_f_reqs_from_core$CLR = 1'b0 ;
// submodule mmio_axi4_adapter_f_rsps_to_core
always@(MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1 or
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1 or
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2 or
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps or
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_1:
mmio_axi4_adapter_f_rsps_to_core$D_IN =
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_1;
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__SEL_2:
mmio_axi4_adapter_f_rsps_to_core$D_IN =
130'h200000000000000000000000000000000;
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps:
mmio_axi4_adapter_f_rsps_to_core$D_IN =
MUX_mmio_axi4_adapter_f_rsps_to_core$enq_1__VAL_3;
default: mmio_axi4_adapter_f_rsps_to_core$D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign mmio_axi4_adapter_f_rsps_to_core$ENQ =
(WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req) &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] ==
2'd0 ||
WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps ;
assign mmio_axi4_adapter_f_rsps_to_core$DEQ =
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_ifetch_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_amo_rsp ||
WILL_FIRE_RL_mmioPlatform_rl_mmio_from_fabric_rsp ;
assign mmio_axi4_adapter_f_rsps_to_core$CLR = 1'b0 ;
// submodule mmio_axi4_adapter_soc_map
assign mmio_axi4_adapter_soc_map$m_is_IO_addr_addr =
mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151] ;
assign mmio_axi4_adapter_soc_map$m_is_mem_addr_addr = 64'h0 ;
assign mmio_axi4_adapter_soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
module_amoExec instance_amoExec_1(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622),
.amoExec_wordIdx({ 1'd0,
mmioPlatform_reqBE_BIT_4___h34136 &&
!mmioPlatform_reqBE_BIT_0___h34176 }),
.amoExec_current({ 65'd0, x__h46418 }),
.amoExec_inpt(mmioPlatform_reqData),
.amoExec(amoExec___d626));
module_amoExec instance_amoExec_0(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622),
.amoExec_wordIdx({ 1'd0,
mmioPlatform_reqBE_BIT_4___h34136 &&
!mmioPlatform_reqBE_BIT_0___h34176 }),
.amoExec_current({ 65'd0,
mmioPlatform_mtime__h46207 }),
.amoExec_inpt(mmioPlatform_reqData),
.amoExec(amoExec___d703));
module_amoExec instance_amoExec_3(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622),
.amoExec_wordIdx({ 1'd0,
mmioPlatform_reqBE_BIT_4___h34136 &&
!mmioPlatform_reqBE_BIT_0___h34176 }),
.amoExec_current(129'd0),
.amoExec_inpt(mmioPlatform_reqData),
.amoExec(amoExec___d765));
module_amoExec instance_amoExec_2(.amoExec_amo_inst(mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622),
.amoExec_wordIdx({ 1'd0,
mmioPlatform_reqBE_BIT_4___h34136 &&
!mmioPlatform_reqBE_BIT_0___h34176 }),
.amoExec_current({ 65'd0,
mmioPlatform_fromHostQ_data_0 }),
.amoExec_inpt(mmioPlatform_reqData),
.amoExec(amoExec___d810));
assign IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668 =
(IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
!mmioPlatform_mtip_0 ||
!IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
mmioPlatform_mtip_0) ?
core_0$RDY_mmioToPlatform_pRq_enq :
core_0$RDY_mmioToPlatform_pRs_enq ;
assign IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d562 =
(mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
(mmioPlatform_reqBE[0] ?
core_0$RDY_mmioToPlatform_pRq_enq :
core_0$RDY_mmioToPlatform_pRs_enq) :
!mmioPlatform_reqBE[0] || core_0$RDY_mmioToPlatform_pRq_enq ;
assign IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 =
newData__h37921 <= mmioPlatform_mtime ;
assign IF_core_0_mmioToPlatform_cRq_first__88_BITS_21_ETC___d511 =
(core_0$mmioToPlatform_cRq_first[214:154] ==
mmioPlatform_toHostAddr) ?
67'h5AAAAAAAAAAAAAAAA :
((core_0$mmioToPlatform_cRq_first[214:154] ==
mmioPlatform_fromHostAddr) ?
67'h6AAAAAAAAAAAAAAAA :
{ 3'd7, core_0$mmioToPlatform_cRq_first[214:151] }) ;
assign IF_enqDst_0_lat_0_whas__158_THEN_enqDst_0_lat__ETC___d1163 =
enqDst_0_lat_0$whas ? enqDst_0_lat_0$wget[73] : enqDst_0_rl[73] ;
assign IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1362 =
enqDst_1_0_lat_0$whas ?
enqDst_1_0_lat_0$wget[584] :
enqDst_1_0_rl[584] ;
assign IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1372 =
enqDst_1_0_lat_0$whas ?
enqDst_1_0_lat_0$wget[583:520] :
enqDst_1_0_rl[583:520] ;
assign IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1377 =
enqDst_1_0_lat_0$whas ?
enqDst_1_0_lat_0$wget[519:518] :
enqDst_1_0_rl[519:518] ;
assign IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1382 =
enqDst_1_0_lat_0$whas ?
enqDst_1_0_lat_0$wget[517] :
enqDst_1_0_rl[517] ;
assign IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1392 =
enqDst_1_0_lat_0$whas ?
enqDst_1_0_lat_0$wget[516:1] :
enqDst_1_0_rl[516:1] ;
assign IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1398 =
enqDst_1_0_lat_0$whas ?
enqDst_1_0_lat_0$wget[0] :
enqDst_1_0_rl[0] ;
assign IF_enqDst_1_0_lat_1_whas__354_THEN_enqDst_1_0__ETC___d1400 =
{ CAN_FIRE_RL_doEnq_1 ||
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1382,
CAN_FIRE_RL_doEnq_1 ?
516'h555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 :
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1392,
x__h91204 } ;
assign IF_enqDst_1_0_lat_1_whas__354_THEN_enqDst_1_0__ETC___d1401 =
{ CAN_FIRE_RL_doEnq_1 ?
64'hAAAAAAAAAAAAAAAA :
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1372,
CAN_FIRE_RL_doEnq_1 ?
2'b10 :
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1377,
IF_enqDst_1_0_lat_1_whas__354_THEN_enqDst_1_0__ETC___d1400 } ;
assign IF_llc_axi4_adapter_rg_rd_rsp_beat_971_BIT_0_0_ETC___d2013 =
{ llc_axi4_adapter_rg_rd_rsp_beat[0] ?
llc_axi4_adapter_rg_cline[515:512] :
{ llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0],
llc_axi4_adapter_rg_cline[515:513] },
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4],
llc_axi4_adapter_rg_cline[511:64] } ;
assign IF_llc_mem_server_axi4_slave_xactor_shim_awff__ETC___d1742 =
{ (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd7) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[511:448],
(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd6) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[447:384],
(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd5) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[383:320],
(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd4) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[319:256],
(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd3) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[255:192],
(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32] ==
3'd2) ?
data__h115667 :
llc_mem_server_rg_cacheline_cache_data[191:128] } ;
assign IF_llc_mem_server_enqDst_0_lat_0_whas__833_THE_ETC___d1838 =
llc_mem_server_propDstIdx_0_lat_1$whas ?
llc_mem_server_enqDst_0_lat_0$wget[65] :
llc_mem_server_enqDst_0_rl[65] ;
assign IF_llc_mem_server_propDstData_0_lat_0_whas__82_ETC___d1828 =
CAN_FIRE_RL_llc_mem_server_srcPropose ?
core_0$tlbToMem_memReq_first :
llc_mem_server_propDstData_0_rl ;
assign IF_llc_mem_server_propDstIdx_0_lat_0_whas__818_ETC___d1821 =
CAN_FIRE_RL_llc_mem_server_srcPropose ||
llc_mem_server_propDstIdx_0_rl ;
assign IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946 =
(mmioPlatform_curReq[2:0] == 3'h0) ?
mmioPlatform_reqData[63:0] :
64'd0 ;
assign IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998 =
(mmioPlatform_curReq[2:0] == 3'h0) ?
mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:0] :
64'd0 ;
assign IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735 =
((mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
!mmioPlatform_mtip_0) ?
core_0$RDY_mmioToPlatform_pRq_enq :
mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 ||
!mmioPlatform_mtip_0 ||
core_0$RDY_mmioToPlatform_pRq_enq) &&
(mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
mmioPlatform_mtip_0 ||
core_0$RDY_mmioToPlatform_pRs_enq) ;
assign IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686 =
mmioPlatform_reqBE[4] ?
{ {32{mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5[31]}},
mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 } :
{ {32{mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6[31]}},
mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 } ;
assign IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751 =
mmioPlatform_reqBE[4] ?
{ {32{mmioPlatform_mtime_BITS_63_TO_32__q7[31]}},
mmioPlatform_mtime_BITS_63_TO_32__q7 } :
{ {32{mmioPlatform_mtime_BITS_31_TO_0__q8[31]}},
mmioPlatform_mtime_BITS_31_TO_0__q8 } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d644 =
{ mmioPlatform_reqBE[7] ?
mmioPlatform_reqData[63:56] :
mmioPlatform_mtimecmp_0[63:56],
mmioPlatform_reqBE[6] ?
mmioPlatform_reqData[55:48] :
mmioPlatform_mtimecmp_0[55:48],
mmioPlatform_reqBE[5] ?
mmioPlatform_reqData[47:40] :
mmioPlatform_mtimecmp_0[47:40],
mmioPlatform_reqBE[4] ?
mmioPlatform_reqData[39:32] :
mmioPlatform_mtimecmp_0[39:32] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d653 =
{ IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d644,
mmioPlatform_reqBE[3] ?
mmioPlatform_reqData[31:24] :
mmioPlatform_mtimecmp_0[31:24],
mmioPlatform_reqBE[2] ?
mmioPlatform_reqData[23:16] :
mmioPlatform_mtimecmp_0[23:16] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d661 =
{ IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d653,
mmioPlatform_reqBE[1] ?
mmioPlatform_reqData[15:8] :
mmioPlatform_mtimecmp_0[15:8],
mmioPlatform_reqBE[0] ?
mmioPlatform_reqData[7:0] :
mmioPlatform_mtimecmp_0[7:0] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d714 =
{ mmioPlatform_reqBE[7] ?
mmioPlatform_reqData[63:56] :
mmioPlatform_mtime[63:56],
mmioPlatform_reqBE[6] ?
mmioPlatform_reqData[55:48] :
mmioPlatform_mtime[55:48],
mmioPlatform_reqBE[5] ?
mmioPlatform_reqData[47:40] :
mmioPlatform_mtime[47:40],
mmioPlatform_reqBE[4] ?
mmioPlatform_reqData[39:32] :
mmioPlatform_mtime[39:32] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d719 =
{ IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d714,
mmioPlatform_reqBE[3] ?
mmioPlatform_reqData[31:24] :
mmioPlatform_mtime[31:24],
mmioPlatform_reqBE[2] ?
mmioPlatform_reqData[23:16] :
mmioPlatform_mtime[23:16] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d724 =
{ IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d719,
mmioPlatform_reqBE[1] ?
mmioPlatform_reqData[15:8] :
mmioPlatform_mtime[15:8],
mmioPlatform_reqBE[0] ?
mmioPlatform_reqData[7:0] :
mmioPlatform_mtime[7:0] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d821 =
{ mmioPlatform_reqBE[7] ?
mmioPlatform_reqData[63:56] :
mmioPlatform_fromHostQ_data_0[63:56],
mmioPlatform_reqBE[6] ?
mmioPlatform_reqData[55:48] :
mmioPlatform_fromHostQ_data_0[55:48],
mmioPlatform_reqBE[5] ?
mmioPlatform_reqData[47:40] :
mmioPlatform_fromHostQ_data_0[47:40],
mmioPlatform_reqBE[4] ?
mmioPlatform_reqData[39:32] :
mmioPlatform_fromHostQ_data_0[39:32] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d826 =
{ IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d821,
mmioPlatform_reqBE[3] ?
mmioPlatform_reqData[31:24] :
mmioPlatform_fromHostQ_data_0[31:24],
mmioPlatform_reqBE[2] ?
mmioPlatform_reqData[23:16] :
mmioPlatform_fromHostQ_data_0[23:16] } ;
assign IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d831 =
{ IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d826,
mmioPlatform_reqBE[1] ?
mmioPlatform_reqData[15:8] :
mmioPlatform_fromHostQ_data_0[15:8],
mmioPlatform_reqBE[0] ?
mmioPlatform_reqData[7:0] :
mmioPlatform_fromHostQ_data_0[7:0] } ;
assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d563 =
(mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4]) ?
core_0$RDY_mmioToPlatform_pRs_enq :
IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d562 ;
assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d687 =
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtimecmp_0 :
IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d686 ;
assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_1_ETC___d752 =
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ?
mmioPlatform_mtime :
IF_mmioPlatform_reqBE_49_BIT_4_50_THEN_SEXT_mm_ETC___d751 ;
assign IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_2_ETC___d835 =
(mmioPlatform_reqFunc[5:4] == 2'd2) ?
(mmioPlatform_fromHostQ_empty ?
x__h54199 == 64'd0 :
x__h51463 == 64'd0) :
mmioPlatform_reqFunc[5:4] == 2'd1 ;
assign IF_mmioPlatform_toHostQ_enqReq_lat_1_whas__25__ETC___d334 =
mmioPlatform_toHostQ_enqReq_lat_0$whas ?
mmioPlatform_toHostQ_enqReq_lat_0$wget[64] :
mmioPlatform_toHostQ_enqReq_rl[64] ;
assign IF_mmioPlatform_waitLowerMSIPCRs_98_THEN_core__ETC___d606 =
mmioPlatform_waitLowerMSIPCRs ?
core_0$RDY_mmioToPlatform_cRs_first &&
core_0$RDY_mmioToPlatform_cRs_deq :
(!mmioPlatform_waitUpperMSIPCRs ||
core_0$RDY_mmioToPlatform_cRs_first) &&
(!mmioPlatform_waitUpperMSIPCRs ||
core_0$RDY_mmioToPlatform_cRs_deq) ;
assign IF_mmio_axi4_adapter_f_rsps_to_core_first__77__ETC___d1092 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ?
mmioPlatform_fetchingWay <
(mmioPlatform_reqFunc[5:4] == 2'd0 &&
mmioPlatform_reqFunc[0]) ||
core_0$RDY_mmioToPlatform_pRs_enq :
core_0$RDY_mmioToPlatform_pRs_enq ;
assign IF_mmio_axi4_adapter_f_rsps_to_core_first__77__ETC___d1114 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[129] ?
(mmioPlatform_fetchingWay ?
mmioPlatform_fetchedInsts_0 :
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107) :
mmioPlatform_fetchedInsts_0 ;
assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d225 =
mmio_axi4_adapter_soc_map$m_is_IO_addr ?
!mmio_axi4_adapter_master_xactor_clearing &&
!mmio_axi4_adapter_master_xactor_shim_awff_rv[97] &&
!mmio_axi4_adapter_master_xactor_shim_wff_rv[74] :
mmio_axi4_adapter_f_rsps_to_core$FULL_N ;
assign IF_mmio_axi4_adapter_soc_map_m_is_IO_addr_mmio_ETC___d53 =
mmio_axi4_adapter_soc_map$m_is_IO_addr ?
!mmio_axi4_adapter_master_xactor_clearing &&
!mmio_axi4_adapter_master_xactor_shim_arff_rv[97] :
mmio_axi4_adapter_f_rsps_to_core$FULL_N ;
assign IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1286 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[583:520] :
propDstData_1_0_rl[583:520] ;
assign IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1291 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[519:518] :
propDstData_1_0_rl[519:518] ;
assign IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1312 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[0] :
propDstData_1_0_rl[0] ;
assign IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1324 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[583:520] :
propDstData_1_1_rl[583:520] ;
assign IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1329 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[519:518] :
propDstData_1_1_rl[519:518] ;
assign IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1350 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[0] :
propDstData_1_1_rl[0] ;
assign IF_propDstIdx_0_lat_0_whas__129_THEN_NOT_propD_ETC___d1195 =
!CAN_FIRE_RL_srcPropose && !propDstIdx_0_rl ;
assign IF_propDstIdx_0_lat_0_whas__129_THEN_propDstId_ETC___d1132 =
CAN_FIRE_RL_srcPropose || propDstIdx_0_rl ;
assign IF_propDstIdx_1_0_lat_0_whas__266_THEN_NOT_pro_ETC___d1432 =
!CAN_FIRE_RL_srcPropose_2 && !propDstIdx_1_0_rl ;
assign IF_propDstIdx_1_0_lat_0_whas__266_THEN_propDst_ETC___d1269 =
CAN_FIRE_RL_srcPropose_2 || propDstIdx_1_0_rl ;
assign IF_propDstIdx_1_1_lat_0_whas__273_THEN_propDst_ETC___d1276 =
CAN_FIRE_RL_srcPropose_3 || propDstIdx_1_1_rl ;
assign IF_propDstIdx_1_lat_0_whas__136_THEN_propDstId_ETC___d1139 =
CAN_FIRE_RL_srcPropose_1 || propDstIdx_1_rl ;
assign NOT_enqDst_0_rl_161_BIT_73_162_167_AND_SEL_ARR_ETC___d1255 =
!enqDst_0_rl[73] &&
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1197 &&
(SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1193 ?
!srcRR_0 :
IF_propDstIdx_0_lat_0_whas__129_THEN_propDstId_ETC___d1132) ;
assign NOT_enqDst_0_rl_161_BIT_73_162_167_AND_SEL_ARR_ETC___d1260 =
!enqDst_0_rl[73] &&
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1197 &&
x__h75482 &&
!CAN_FIRE_RL_srcPropose_1 &&
!propDstIdx_1_rl ;
assign NOT_enqDst_1_0_rl_360_BIT_584_361_366_AND_SEL__ETC___d1556 =
!enqDst_1_0_rl[584] &&
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1434 &&
(SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1430 ?
!srcRR_1_0 :
IF_propDstIdx_1_0_lat_0_whas__266_THEN_propDst_ETC___d1269) ;
assign NOT_enqDst_1_0_rl_360_BIT_584_361_366_AND_SEL__ETC___d1561 =
!enqDst_1_0_rl[584] &&
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1434 &&
x__h97768 &&
!CAN_FIRE_RL_srcPropose_3 &&
!propDstIdx_1_1_rl ;
assign NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 =
llc_axi4_adapter_cfg_verbosity > 4'd1 ;
assign NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d2046 =
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
!llc_axi4_adapter_rg_cline[515] :
!llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ;
assign NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d2049 =
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
llc_axi4_adapter_rg_cline[515] :
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0]) ;
assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1082 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_reqFunc[5:4] == 2'd0 ;
assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d1095 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_reqFunc[5:4] == 2'd0 ;
assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d867 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd2 &&
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqFunc[5:4] == 2'd2) ;
assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d875 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd3 &&
(mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqFunc[5:4] == 2'd2) ;
assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d880 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd2 &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 ;
assign NOT_mmioPlatform_curReq_41_BITS_66_TO_64_42_EQ_ETC___d890 =
mmioPlatform_curReq[66:64] != 3'd0 &&
mmioPlatform_curReq[66:64] != 3'd1 &&
mmioPlatform_curReq[66:64] != 3'd2 &&
mmioPlatform_curReq[66:64] != 3'd3 &&
mmioPlatform_curReq[66:64] != 3'd4 &&
mmioPlatform_curReq[66:64] != 3'd5 &&
mmioPlatform_curReq[66:64] != 3'd6 &&
mmioPlatform_state == 2'd3 &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 ;
assign NOT_mmioPlatform_mtip_0_65_72_AND_mmioPlatform_ETC___d480 =
!mmioPlatform_mtip_0 &&
mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 ||
!core_0$mmioToPlatform_cRq_notEmpty ||
core_0$RDY_mmioToPlatform_cRq_first &&
core_0$RDY_mmioToPlatform_cRq_deq ;
assign NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d596 =
mmioPlatform_reqFunc[5:4] != 2'd0 && !mmioPlatform_reqBE[4] &&
(mmioPlatform_reqBE[0] || mmioPlatform_reqFunc[5:4] == 2'd1 ||
mmioPlatform_reqFunc[5:4] == 2'd2) ;
assign NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d694 =
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
(IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
!mmioPlatform_mtip_0 ||
!IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 &&
mmioPlatform_mtip_0) ;
assign NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ__ETC___d758 =
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
(mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
!mmioPlatform_mtip_0 ||
!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 &&
mmioPlatform_mtip_0) ;
assign SEL_ARR_IF_propDstData_0_lat_0_whas__143_THEN__ETC___d1248 =
{ CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19,
x__h75682,
x__h75683 } ;
assign SEL_ARR_IF_propDstData_0_lat_0_whas__143_THEN__ETC___d1249 =
{ CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20,
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21,
SEL_ARR_IF_propDstData_0_lat_0_whas__143_THEN__ETC___d1248 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1468 =
{ CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1493 =
{ CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1510 =
{ CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1527 =
{ SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1493,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1510,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1544 =
{ CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1545 =
{ SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1468,
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1527,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1544 } ;
assign SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1550 =
{ CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q35,
!CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36,
SEL_ARR_IF_propDstData_1_0_lat_0_whas__281_THE_ETC___d1545,
x__h102503 } ;
assign SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1197 =
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1193 ||
(IF_propDstIdx_0_lat_0_whas__129_THEN_NOT_propD_ETC___d1195 ?
IF_propDstIdx_1_lat_0_whas__136_THEN_propDstId_ETC___d1139 :
IF_propDstIdx_0_lat_0_whas__129_THEN_propDstId_ETC___d1132) ;
assign SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1434 =
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1430 ||
(IF_propDstIdx_1_0_lat_0_whas__266_THEN_NOT_pro_ETC___d1432 ?
IF_propDstIdx_1_1_lat_0_whas__273_THEN_propDst_ETC___d1276 :
IF_propDstIdx_1_0_lat_0_whas__266_THEN_propDst_ETC___d1269) ;
assign _0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213 =
{ 64'd0,
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4] } <<
(mmio_axi4_adapter_read_req_addr[3] ? 32'd64 : 32'd0) ;
assign addr1__h66648 = { mmioPlatform_curReq[63:3], 3'b0 } ;
assign b__h168385 =
llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ?
llc_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
llc_axi4_adapter_ctr_wr_rsps_pending_crg ;
assign b__h4255 =
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN_port0__write ?
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$port0__write_1 :
mmio_axi4_adapter_ctr_wr_rsps_pending_crg ;
assign data__h115667 =
{ llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[9] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[73:66] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[63:56],
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[8] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[65:58] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[55:48],
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[7] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[57:50] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[47:40],
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[6] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[49:42] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[39:32],
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[5] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[41:34] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[31:24],
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[4] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[33:26] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[23:16],
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[3] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[25:18] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[15:8],
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[2] ?
llc_mem_server_axi4_slave_xactor_shim_wff_rv$port1__read[17:10] :
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694[7:0] } ;
assign failed_testnum__h198871 =
{ 1'd0, mmioPlatform_toHostQ_data_0[63:1] } ;
assign line_addr__h115100 =
{ llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[92:35],
6'b0 } ;
assign line_addr__h125208 =
{ llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[92:35],
6'b0 } ;
assign line_addr__h168594 = { llc$to_mem_toM_first[68:11], 6'h0 } ;
assign llc_axi4_adapter_master_xactor_shim_arff_rvpo_ETC__q42 =
llc_axi4_adapter_master_xactor_shim_arff_rv$port1__read[97:0] ;
assign llc_axi4_adapter_master_xactor_shim_awff_rvpo_ETC__q40 =
llc_axi4_adapter_master_xactor_shim_awff_rv$port1__read[97:0] ;
assign llc_axi4_adapter_master_xactor_shim_rff_rv_por_ETC___d1978 =
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[73] &&
(llc_axi4_adapter_rg_rd_rsp_beat != 3'd7 ||
llc$RDY_to_mem_rsFromM_enq &&
llc_axi4_adapter_f_pending_reads$EMPTY_N) ;
assign llc_axi4_adapter_master_xactor_shim_wff_rvpor_ETC__q41 =
llc_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ;
assign llc_mem_server_axi4_slave_xactor_shim_arff_rv__ETC___d1758 =
line_addr__h125208 == llc_mem_server_rg_cacheline_cache_addr ;
assign llc_mem_server_axi4_slave_xactor_shim_awff_rv__ETC___d1659 =
line_addr__h115100 == llc_mem_server_rg_cacheline_cache_addr ;
assign llc_mem_server_axi4_slave_xactor_shim_bff_rvp_ETC__q38 =
llc_mem_server_axi4_slave_xactor_shim_bff_rv$port1__read[6:0] ;
assign llc_mem_server_axi4_slave_xactor_shim_rff_rvp_ETC__q39 =
llc_mem_server_axi4_slave_xactor_shim_rff_rv$port1__read[72:0] ;
assign mmioPlatform_cycle_57_ULT_99___d458 = mmioPlatform_cycle < 7'd99 ;
assign mmioPlatform_fetchingWay_087_ULT_mmioPlatform__ETC___d1097 =
mmioPlatform_fetchingWay < mmioPlatform_reqFunc[0] ;
assign mmioPlatform_mtime_BITS_31_TO_0__q8 = mmioPlatform_mtime[31:0] ;
assign mmioPlatform_mtime_BITS_63_TO_32__q7 = mmioPlatform_mtime[63:32] ;
assign mmioPlatform_mtime__h46207 = mmioPlatform_mtime ;
assign mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 =
mmioPlatform_mtimecmp_0 <= newData__h42646 ;
assign mmioPlatform_mtimecmp_0_66_ULE_mmioPlatform_mt_ETC___d467 =
mmioPlatform_mtimecmp_0 <= mmioPlatform_mtime ;
assign mmioPlatform_mtimecmp_0_BITS_31_TO_0__q6 =
mmioPlatform_mtimecmp_0[31:0] ;
assign mmioPlatform_mtimecmp_0_BITS_63_TO_32__q5 =
mmioPlatform_mtimecmp_0[63:32] ;
assign mmioPlatform_reqBE_BIT_0___h34176 = mmioPlatform_reqBE[0] ;
assign mmioPlatform_reqBE_BIT_4___h34136 = mmioPlatform_reqBE[4] ;
assign mmioPlatform_reqFunc_46_BITS_3_TO_0_85_CONCAT__ETC___d622 =
{ mmioPlatform_reqFunc[3:0],
(mmioPlatform_reqBE[4] && mmioPlatform_reqBE[0]) ? 2'd1 : 2'd2,
2'd0 } ;
assign mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d573 =
mmioPlatform_reqFunc[5:4] == 2'd0 || mmioPlatform_reqBE[4] ||
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2 &&
!mmioPlatform_reqBE[0] ;
assign mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d680 =
mmioPlatform_reqFunc[5:4] == 2'd0 ||
mmioPlatform_reqFunc[5:4] == 2'd1 ||
(!IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 ||
mmioPlatform_mtip_0) &&
(IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4_47__ETC___d663 ||
!mmioPlatform_mtip_0) ;
assign mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_48_ETC___d746 =
mmioPlatform_reqFunc[5:4] == 2'd0 ||
mmioPlatform_reqFunc[5:4] == 2'd1 ||
(!mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 ||
mmioPlatform_mtip_0) &&
(mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioPlat_ETC___d726 ||
!mmioPlatform_mtip_0) ;
assign mmio_axi4_adapter_master_xactor_shim_arff_rvp_ETC__q18 =
mmio_axi4_adapter_master_xactor_shim_arff_rv$port1__read[96:0] ;
assign mmio_axi4_adapter_master_xactor_shim_awff_rvp_ETC__q16 =
mmio_axi4_adapter_master_xactor_shim_awff_rv$port1__read[96:0] ;
assign mmio_axi4_adapter_master_xactor_shim_wff_rvpo_ETC__q17 =
mmio_axi4_adapter_master_xactor_shim_wff_rv$port1__read[73:0] ;
assign newData__h37921 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
amoExec___d626[63:0] :
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d661 ;
assign newData__h42646 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
amoExec___d703[63:0] :
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d724 ;
assign op_result__h64708 =
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005 +
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007 ;
assign op_result__h65435 = w1__h63935 ^ w2__h63937 ;
assign op_result__h65440 = w1__h63935 & w2__h63937 ;
assign op_result__h65445 = w1__h63935 | w2__h63937 ;
assign op_result__h65450 =
(w1__h63935 < w2__h63937) ? w1__h63935 : w2__h63937 ;
assign op_result__h65456 =
(w1__h63935 <= w2__h63937) ? w2__h63937 : w1__h63935 ;
assign op_result__h65463 =
((IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005 ^
64'h8000000000000000) <
(IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007 ^
64'h8000000000000000)) ?
w1__h63935 :
w2__h63937 ;
assign op_result__h65469 =
((IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005 ^
64'h8000000000000000) <=
(IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007 ^
64'h8000000000000000)) ?
w2__h63937 :
w1__h63935 ;
assign result__h63981 =
{ mmioPlatform_reqData[63:8],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0] } ;
assign result__h64289 = { 56'd0, mmioPlatform_reqData[7:0] } ;
assign result__h64316 = { 56'd0, mmioPlatform_reqData[15:8] } ;
assign result__h64343 = { 56'd0, mmioPlatform_reqData[23:16] } ;
assign result__h64370 = { 56'd0, mmioPlatform_reqData[31:24] } ;
assign result__h64397 = { 56'd0, mmioPlatform_reqData[39:32] } ;
assign result__h64424 = { 56'd0, mmioPlatform_reqData[47:40] } ;
assign result__h64451 = { 56'd0, mmioPlatform_reqData[55:48] } ;
assign result__h64478 = { 56'd0, mmioPlatform_reqData[63:56] } ;
assign result__h64522 = { 48'd0, mmioPlatform_reqData[15:0] } ;
assign result__h64549 = { 48'd0, mmioPlatform_reqData[31:16] } ;
assign result__h64576 = { 48'd0, mmioPlatform_reqData[47:32] } ;
assign result__h64603 = { 48'd0, mmioPlatform_reqData[63:48] } ;
assign result__h64643 = { 32'd0, mmioPlatform_reqData[31:0] } ;
assign result__h64670 = { 32'd0, mmioPlatform_reqData[63:32] } ;
assign result__h64795 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[7:0] } ;
assign result__h65019 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:8] } ;
assign result__h65046 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[23:16] } ;
assign result__h65073 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:24] } ;
assign result__h65100 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[39:32] } ;
assign result__h65127 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:40] } ;
assign result__h65154 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[55:48] } ;
assign result__h65181 =
{ 56'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:56] } ;
assign result__h65225 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[15:0] } ;
assign result__h65252 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:16] } ;
assign result__h65279 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[47:32] } ;
assign result__h65306 =
{ 48'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:48] } ;
assign result__h65346 =
{ 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0] } ;
assign result__h65373 =
{ 32'd0, mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32] } ;
assign result__h65490 =
{ mmioPlatform_reqData[63:16],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0],
mmioPlatform_reqData[7:0] } ;
assign result__h65556 =
{ mmioPlatform_reqData[63:24],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0],
mmioPlatform_reqData[15:0] } ;
assign result__h65622 =
{ mmioPlatform_reqData[63:32],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0],
mmioPlatform_reqData[23:0] } ;
assign result__h65688 =
{ mmioPlatform_reqData[63:40],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0],
mmioPlatform_reqData[31:0] } ;
assign result__h65754 =
{ mmioPlatform_reqData[63:48],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0],
mmioPlatform_reqData[39:0] } ;
assign result__h65820 =
{ mmioPlatform_reqData[63:56],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0],
mmioPlatform_reqData[47:0] } ;
assign result__h65886 =
{ IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[7:0],
mmioPlatform_reqData[55:0] } ;
assign result__h65948 =
{ mmioPlatform_reqData[63:16],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[15:0] } ;
assign result__h65993 =
{ mmioPlatform_reqData[63:32],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[15:0],
mmioPlatform_reqData[15:0] } ;
assign result__h66059 =
{ mmioPlatform_reqData[63:48],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[15:0],
mmioPlatform_reqData[31:0] } ;
assign result__h66125 =
{ IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[15:0],
mmioPlatform_reqData[47:0] } ;
assign result__h66183 =
{ mmioPlatform_reqData[63:32],
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[31:0] } ;
assign result__h66228 =
{ IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037[31:0],
mmioPlatform_reqData[31:0] } ;
assign v__h37337 = mmioPlatform_waitUpperMSIPCRs ? v__h37374 : 32'd0 ;
assign v__h37374 = { 31'd0, core_0$mmioToPlatform_cRs_first } ;
assign v_awaddr__h190085 = { llc$to_mem_toM_first[643:586], 6'h0 } ;
assign v_awsize_val__h15184 =
(mmio_axi4_adapter_f_reqs_from_core$D_OUT[136:133] == 4'd0 ||
mmio_axi4_adapter_f_reqs_from_core$D_OUT[132:129] == 4'd0) ?
3'b010 :
3'b011 ;
assign w13930_BITS_31_TO_0__q11 = w1__h63930[31:0] ;
assign w1___1__h64224 = { 32'd0, w1__h63930[31:0] } ;
assign w23931_BITS_31_TO_0__q12 = w2__h63931[31:0] ;
assign w2___1__h64225 = { 32'd0, w2__h63931[31:0] } ;
assign x__h46418 = mmioPlatform_mtimecmp_0 ;
assign x__h51463 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
amoExec___d810[63:0] :
IF_mmioPlatform_reqBE_49_BIT_7_28_THEN_mmioPla_ETC___d831 ;
assign x__h54199 =
(mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd1 &&
mmioPlatform_reqFunc[5:4] != 2'd2) ?
amoExec___d765[63:0] :
{ mmioPlatform_reqBE[7] ? mmioPlatform_reqData[63:56] : 8'd0,
mmioPlatform_reqBE[6] ? mmioPlatform_reqData[55:48] : 8'd0,
mmioPlatform_reqBE[5] ? mmioPlatform_reqData[47:40] : 8'd0,
mmioPlatform_reqBE[4] ? mmioPlatform_reqData[39:32] : 8'd0,
mmioPlatform_reqBE[3] ? mmioPlatform_reqData[31:24] : 8'd0,
mmioPlatform_reqBE[2] ? mmioPlatform_reqData[23:16] : 8'd0,
mmioPlatform_reqBE[1] ? mmioPlatform_reqData[15:8] : 8'd0,
mmioPlatform_reqBE[0] ? mmioPlatform_reqData[7:0] : 8'd0 } ;
assign x__h75482 =
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1193 ?
srcRR_0 :
IF_propDstIdx_0_lat_0_whas__129_THEN_NOT_propD_ETC___d1195 ;
assign x__h91204 =
!CAN_FIRE_RL_doEnq_1 &&
IF_enqDst_1_0_lat_0_whas__357_THEN_enqDst_1_0__ETC___d1398 ;
assign x__h97768 =
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1430 ?
srcRR_1_0 :
IF_propDstIdx_1_0_lat_0_whas__266_THEN_NOT_pro_ETC___d1432 ;
assign x_data__h35020 = { 31'd0, mmioPlatform_reqData[0] } ;
always@(llc$dma_respLd_first)
begin
case (llc$dma_respLd_first[2:0])
3'd0: ld_data__h163305 = llc$dma_respLd_first[68:5];
3'd1: ld_data__h163305 = llc$dma_respLd_first[132:69];
3'd2: ld_data__h163305 = llc$dma_respLd_first[196:133];
3'd3: ld_data__h163305 = llc$dma_respLd_first[260:197];
3'd4: ld_data__h163305 = llc$dma_respLd_first[324:261];
3'd5: ld_data__h163305 = llc$dma_respLd_first[388:325];
3'd6: ld_data__h163305 = llc$dma_respLd_first[452:389];
3'd7: ld_data__h163305 = llc$dma_respLd_first[516:453];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat[0])
1'd0:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1 =
llc$to_mem_toM_first[63:0];
1'd1:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1 =
llc$to_mem_toM_first[127:64];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat[0])
1'd0:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2 =
llc$to_mem_toM_first[191:128];
1'd1:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2 =
llc$to_mem_toM_first[255:192];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat[0])
1'd0:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3 =
llc$to_mem_toM_first[319:256];
1'd1:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3 =
llc$to_mem_toM_first[383:320];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat[0])
1'd0:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4 =
llc$to_mem_toM_first[447:384];
1'd1:
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4 =
llc$to_mem_toM_first[511:448];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1 or
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2 or
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3 or
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4)
begin
case (llc_axi4_adapter_rg_wr_req_beat[2:1])
2'd0:
v_wdata__h190496 =
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q1;
2'd1:
v_wdata__h190496 =
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q2;
2'd2:
v_wdata__h190496 =
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q3;
2'd3:
v_wdata__h190496 =
CASE_llc_axi4_adapter_rg_wr_req_beat_BIT_0_0_l_ETC__q4;
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat)
3'd0: v_wstrb__h190497 = llc$to_mem_toM_first[523:516];
3'd1: v_wstrb__h190497 = llc$to_mem_toM_first[531:524];
3'd2: v_wstrb__h190497 = llc$to_mem_toM_first[539:532];
3'd3: v_wstrb__h190497 = llc$to_mem_toM_first[547:540];
3'd4: v_wstrb__h190497 = llc$to_mem_toM_first[555:548];
3'd5: v_wstrb__h190497 = llc$to_mem_toM_first[563:556];
3'd6: v_wstrb__h190497 = llc$to_mem_toM_first[571:564];
3'd7: v_wstrb__h190497 = llc$to_mem_toM_first[579:572];
endcase
end
always@(llc_axi4_adapter_rg_wr_req_beat or llc$to_mem_toM_first)
begin
case (llc_axi4_adapter_rg_wr_req_beat[2:1])
2'd0: v_wuser__h190499 = llc$to_mem_toM_first[512];
2'd1: v_wuser__h190499 = llc$to_mem_toM_first[513];
2'd2: v_wuser__h190499 = llc$to_mem_toM_first[514];
2'd3: v_wuser__h190499 = llc$to_mem_toM_first[515];
endcase
end
always@(mmioPlatform_curReq or
result__h64289 or
result__h64316 or
result__h64343 or
result__h64370 or
result__h64397 or
result__h64424 or result__h64451 or result__h64478)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64289;
3'h1:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64316;
3'h2:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64343;
3'h3:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64370;
3'h4:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64397;
3'h5:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64424;
3'h6:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64451;
3'h7:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 =
result__h64478;
endcase
end
always@(mmioPlatform_curReq or
result__h64522 or
result__h64549 or result__h64576 or result__h64603)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 =
result__h64522;
3'h2:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 =
result__h64549;
3'h4:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 =
result__h64576;
3'h6:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 =
result__h64603;
default: IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or result__h64643 or result__h64670)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 =
result__h64643;
3'h4:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 =
result__h64670;
default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 = 64'd0;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 or
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946)
begin
case (mmioPlatform_reqSz)
2'b0:
w2__h63931 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925;
2'b01:
w2__h63931 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938;
2'b10:
w2__h63931 = CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q9;
2'b11:
w2__h63931 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 or
w2___1__h64225 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946)
begin
case (mmioPlatform_reqSz)
2'b0:
w2__h63937 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925;
2'b01:
w2__h63937 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938;
2'b10: w2__h63937 = w2___1__h64225;
2'b11:
w2__h63937 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946;
endcase
end
always@(mmioPlatform_curReq or
result__h64795 or
result__h65019 or
result__h65046 or
result__h65073 or
result__h65100 or
result__h65127 or result__h65154 or result__h65181)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h64795;
3'h1:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h65019;
3'h2:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h65046;
3'h3:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h65073;
3'h4:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h65100;
3'h5:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h65127;
3'h6:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h65154;
3'h7:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 =
result__h65181;
endcase
end
always@(mmioPlatform_curReq or
result__h65225 or
result__h65252 or result__h65279 or result__h65306)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 =
result__h65225;
3'h2:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 =
result__h65252;
3'h4:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 =
result__h65279;
3'h6:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 =
result__h65306;
default: IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or result__h65346 or result__h65373)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 =
result__h65346;
3'h4:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 =
result__h65373;
default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 =
64'd0;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 or
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998)
begin
case (mmioPlatform_reqSz)
2'b0:
w1__h63930 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978;
2'b01:
w1__h63930 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990;
2'b10:
w1__h63930 =
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q10;
2'b11:
w1__h63930 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 or
w1___1__h64224 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998)
begin
case (mmioPlatform_reqSz)
2'b0:
w1__h63935 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978;
2'b01:
w1__h63935 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990;
2'b10: w1__h63935 = w1___1__h64224;
2'b11:
w1__h63935 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990 or
w13930_BITS_31_TO_0__q11 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998)
begin
case (mmioPlatform_reqSz)
2'b0:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d978;
2'b01:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d990;
2'b10:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005 =
{ {32{w13930_BITS_31_TO_0__q11[31]}},
w13930_BITS_31_TO_0__q11 };
2'b11:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1005 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d998;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938 or
w23931_BITS_31_TO_0__q12 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946)
begin
case (mmioPlatform_reqSz)
2'b0:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d925;
2'b01:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d938;
2'b10:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007 =
{ {32{w23931_BITS_31_TO_0__q12[31]}},
w23931_BITS_31_TO_0__q12 };
2'b11:
IF_mmioPlatform_reqSz_95_EQ_0b10_02_THEN_SEXT__ETC___d1007 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946;
endcase
end
always@(mmioPlatform_reqAmofunc or
op_result__h65469 or
w2__h63937 or
op_result__h64708 or
op_result__h65435 or
op_result__h65440 or
op_result__h65445 or
op_result__h65463 or op_result__h65450 or op_result__h65456)
begin
case (mmioPlatform_reqAmofunc)
4'd0:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
w2__h63937;
4'd1:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h64708;
4'd2:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h65435;
4'd3:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h65440;
4'd4:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h65445;
4'd5:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h65463;
4'd7:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h65450;
4'd8:
IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h65456;
default: IF_mmioPlatform_reqAmofunc_00_EQ_0_01_THEN_IF__ETC___d1037 =
op_result__h65469;
endcase
end
always@(mmioPlatform_curReq or
result__h65948 or
result__h65993 or result__h66059 or result__h66125)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070 =
result__h65948;
3'h2:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070 =
result__h65993;
3'h4:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070 =
result__h66059;
3'h6:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070 =
result__h66125;
default: IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070 =
64'd0;
endcase
end
always@(mmioPlatform_curReq or
result__h63981 or
result__h65490 or
result__h65556 or
result__h65622 or
result__h65688 or
result__h65754 or result__h65820 or result__h65886)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h63981;
3'h1:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h65490;
3'h2:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h65556;
3'h3:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h65622;
3'h4:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h65688;
3'h5:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h65754;
3'h6:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h65820;
3'h7:
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 =
result__h65886;
endcase
end
always@(mmioPlatform_reqFunc)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0, 2'd1, 2'd2:
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587 =
mmioPlatform_reqFunc;
2'd3:
IF_mmioPlatform_reqFunc_46_BITS_5_TO_4_47_EQ_0_ETC___d587 =
{ 2'd3, mmioPlatform_reqFunc[3:0] };
endcase
end
always@(mmioPlatform_instSel or mmio_axi4_adapter_f_rsps_to_core$D_OUT)
begin
case (mmioPlatform_instSel)
2'd0:
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[31:0];
2'd1:
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[63:32];
2'd2:
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[95:64];
2'd3:
SEL_ARR_mmio_axi4_adapter_f_rsps_to_core_first_ETC___d1107 =
mmio_axi4_adapter_f_rsps_to_core$D_OUT[127:96];
endcase
end
always@(mmioPlatform_curReq or result__h66183 or result__h66228)
begin
case (mmioPlatform_curReq[2:0])
3'h0:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 =
result__h66183;
3'h4:
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 =
result__h66228;
default: CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 =
64'd0;
endcase
end
always@(mmioPlatform_reqSz or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070 or
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13 or
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946)
begin
case (mmioPlatform_reqSz)
2'b0:
IF_mmioPlatform_reqSz_95_EQ_0b0_96_THEN_IF_mmi_ETC___d1078 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1061;
2'b01:
IF_mmioPlatform_reqSz_95_EQ_0b0_96_THEN_IF_mmi_ETC___d1078 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d1070;
2'b10:
IF_mmioPlatform_reqSz_95_EQ_0b0_96_THEN_IF_mmi_ETC___d1078 =
CASE_mmioPlatform_curReq_BITS_2_TO_0_0x0_resul_ETC__q13;
2'b11:
IF_mmioPlatform_reqSz_95_EQ_0b0_96_THEN_IF_mmi_ETC___d1078 =
IF_mmioPlatform_curReq_41_BITS_2_TO_0_97_EQ_0x_ETC___d946;
endcase
end
always@(mmioPlatform_reqFunc or
IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668 or
core_0$RDY_mmioToPlatform_pRs_enq)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0, 2'd1:
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14 =
core_0$RDY_mmioToPlatform_pRs_enq;
default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q14 =
IF_IF_NOT_mmioPlatform_reqFunc_46_BITS_5_TO_4__ETC___d668;
endcase
end
always@(mmioPlatform_reqFunc or
IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735 or
core_0$RDY_mmioToPlatform_pRs_enq)
begin
case (mmioPlatform_reqFunc[5:4])
2'd0, 2'd1:
CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15 =
core_0$RDY_mmioToPlatform_pRs_enq;
default: CASE_mmioPlatform_reqFunc_BITS_5_TO_4_0_core_0_ETC__q15 =
IF_mmioPlatform_mtimecmp_0_66_ULE_IF_NOT_mmioP_ETC___d735;
endcase
end
always@(srcRR_0 or
IF_propDstIdx_0_lat_0_whas__129_THEN_propDstId_ETC___d1132 or
IF_propDstIdx_1_lat_0_whas__136_THEN_propDstId_ETC___d1139)
begin
case (srcRR_0)
1'd0:
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1193 =
IF_propDstIdx_0_lat_0_whas__129_THEN_propDstId_ETC___d1132;
1'd1:
SEL_ARR_IF_propDstIdx_0_lat_0_whas__129_THEN_p_ETC___d1193 =
IF_propDstIdx_1_lat_0_whas__136_THEN_propDstId_ETC___d1139;
endcase
end
always@(srcRR_1_0 or
IF_propDstIdx_1_0_lat_0_whas__266_THEN_propDst_ETC___d1269 or
IF_propDstIdx_1_1_lat_0_whas__273_THEN_propDst_ETC___d1276)
begin
case (srcRR_1_0)
1'd0:
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1430 =
IF_propDstIdx_1_0_lat_0_whas__266_THEN_propDst_ETC___d1269;
1'd1:
SEL_ARR_IF_propDstIdx_1_0_lat_0_whas__266_THEN_ETC___d1430 =
IF_propDstIdx_1_1_lat_0_whas__273_THEN_propDst_ETC___d1276;
endcase
end
always@(x__h75482 or
CAN_FIRE_RL_srcPropose or
propDstData_0_lat_0$wget or
propDstData_0_rl or
CAN_FIRE_RL_srcPropose_1 or
propDstData_1_lat_0$wget or propDstData_1_rl)
begin
case (x__h75482)
1'd0:
x__h75682 =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[3:1] :
propDstData_0_rl[3:1];
1'd1:
x__h75682 =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[3:1] :
propDstData_1_rl[3:1];
endcase
end
always@(x__h75482 or
CAN_FIRE_RL_srcPropose or
propDstData_0_lat_0$wget or
propDstData_0_rl or
CAN_FIRE_RL_srcPropose_1 or
propDstData_1_lat_0$wget or propDstData_1_rl)
begin
case (x__h75482)
1'd0:
x__h75683 =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[0] :
propDstData_0_rl[0];
1'd1:
x__h75683 =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[0] :
propDstData_1_rl[0];
endcase
end
always@(x__h75482 or
CAN_FIRE_RL_srcPropose or
propDstData_0_lat_0$wget or
propDstData_0_rl or
CAN_FIRE_RL_srcPropose_1 or
propDstData_1_lat_0$wget or propDstData_1_rl)
begin
case (x__h75482)
1'd0:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19 =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[4] :
propDstData_0_rl[4];
1'd1:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q19 =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[4] :
propDstData_1_rl[4];
endcase
end
always@(x__h75482 or
CAN_FIRE_RL_srcPropose or
propDstData_0_lat_0$wget or
propDstData_0_rl or
CAN_FIRE_RL_srcPropose_1 or
propDstData_1_lat_0$wget or propDstData_1_rl)
begin
case (x__h75482)
1'd0:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20 =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[8:7] :
propDstData_0_rl[8:7];
1'd1:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q20 =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[8:7] :
propDstData_1_rl[8:7];
endcase
end
always@(x__h75482 or
CAN_FIRE_RL_srcPropose or
propDstData_0_lat_0$wget or
propDstData_0_rl or
CAN_FIRE_RL_srcPropose_1 or
propDstData_1_lat_0$wget or propDstData_1_rl)
begin
case (x__h75482)
1'd0:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21 =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[6:5] :
propDstData_0_rl[6:5];
1'd1:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q21 =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[6:5] :
propDstData_1_rl[6:5];
endcase
end
always@(x__h75482 or
CAN_FIRE_RL_srcPropose or
propDstData_0_lat_0$wget or
propDstData_0_rl or
CAN_FIRE_RL_srcPropose_1 or
propDstData_1_lat_0$wget or propDstData_1_rl)
begin
case (x__h75482)
1'd0:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22 =
CAN_FIRE_RL_srcPropose ?
propDstData_0_lat_0$wget[72:9] :
propDstData_0_rl[72:9];
1'd1:
CASE_x5482_0_IF_CAN_FIRE_RL_srcPropose_THEN_pr_ETC__q22 =
CAN_FIRE_RL_srcPropose_1 ?
propDstData_1_lat_0$wget[72:9] :
propDstData_1_rl[72:9];
endcase
end
always@(x__h97768 or
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1312 or
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1350)
begin
case (x__h97768)
1'd0:
x__h102503 =
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1312;
1'd1:
x__h102503 =
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1350;
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[512:449] :
propDstData_1_0_rl[512:449];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q23 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[512:449] :
propDstData_1_1_rl[512:449];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[448:385] :
propDstData_1_0_rl[448:385];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q24 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[448:385] :
propDstData_1_1_rl[448:385];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[516] :
propDstData_1_0_rl[516];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q25 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[516] :
propDstData_1_1_rl[516];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[515] :
propDstData_1_0_rl[515];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q26 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[515] :
propDstData_1_1_rl[515];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[514] :
propDstData_1_0_rl[514];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q27 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[514] :
propDstData_1_1_rl[514];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[384:321] :
propDstData_1_0_rl[384:321];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q28 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[384:321] :
propDstData_1_1_rl[384:321];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[320:257] :
propDstData_1_0_rl[320:257];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q29 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[320:257] :
propDstData_1_1_rl[320:257];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[256:193] :
propDstData_1_0_rl[256:193];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q30 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[256:193] :
propDstData_1_1_rl[256:193];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[192:129] :
propDstData_1_0_rl[192:129];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q31 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[192:129] :
propDstData_1_1_rl[192:129];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[128:65] :
propDstData_1_0_rl[128:65];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q32 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[128:65] :
propDstData_1_1_rl[128:65];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[64:1] :
propDstData_1_0_rl[64:1];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q33 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[64:1] :
propDstData_1_1_rl[64:1];
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34 =
CAN_FIRE_RL_srcPropose_2 ?
propDstData_1_0_lat_0$wget[513] :
propDstData_1_0_rl[513];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q34 =
CAN_FIRE_RL_srcPropose_3 ?
propDstData_1_1_lat_0$wget[513] :
propDstData_1_1_rl[513];
endcase
end
always@(x__h97768 or
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1291 or
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1329)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q35 =
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1291;
1'd1:
CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q35 =
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1329;
endcase
end
always@(x__h97768 or
CAN_FIRE_RL_srcPropose_2 or
propDstData_1_0_lat_0$wget or
propDstData_1_0_rl or
CAN_FIRE_RL_srcPropose_3 or
propDstData_1_1_lat_0$wget or propDstData_1_1_rl)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36 =
CAN_FIRE_RL_srcPropose_2 ?
!propDstData_1_0_lat_0$wget[517] :
!propDstData_1_0_rl[517];
1'd1:
CASE_x7768_0_IF_CAN_FIRE_RL_srcPropose_2_THEN__ETC__q36 =
CAN_FIRE_RL_srcPropose_3 ?
!propDstData_1_1_lat_0$wget[517] :
!propDstData_1_1_rl[517];
endcase
end
always@(x__h97768 or
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1286 or
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1324)
begin
case (x__h97768)
1'd0:
CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q37 =
IF_propDstData_1_0_lat_0_whas__281_THEN_propDs_ETC___d1286;
1'd1:
CASE_x7768_0_IF_propDstData_1_0_lat_0_whas__28_ETC__q37 =
IF_propDstData_1_1_lat_0_whas__319_THEN_propDs_ETC___d1324;
endcase
end
always@(llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read or
llc_mem_server_rg_cacheline_cache_data)
begin
case (llc_mem_server_axi4_slave_xactor_shim_awff_rv$port1__read[34:32])
3'd0:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[63:0];
3'd1:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[127:64];
3'd2:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[191:128];
3'd3:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[255:192];
3'd4:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[319:256];
3'd5:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[383:320];
3'd6:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[447:384];
3'd7:
SEL_ARR_llc_mem_server_rg_cacheline_cache_data_ETC___d1694 =
llc_mem_server_rg_cacheline_cache_data[511:448];
endcase
end
always@(llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read or
llc_mem_server_rg_cacheline_cache_data)
begin
case (llc_mem_server_axi4_slave_xactor_shim_arff_rv$port1__read[34:32])
3'd0: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[63:0];
3'd1: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[127:64];
3'd2: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[191:128];
3'd3: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[255:192];
3'd4: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[319:256];
3'd5: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[383:320];
3'd6: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[447:384];
3'd7: dword__h125391 = llc_mem_server_rg_cacheline_cache_data[511:448];
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY 74'h0AAAAAAAAAAAAAAAAAA;
enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY
585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
4'd0;
llc_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY 1'd0;
llc_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
8'd42;
llc_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
74'h0AAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
75'h2AAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY 3'd0;
llc_mem_server_axi4_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY
1'd0;
llc_mem_server_axi4_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_mem_server_axi4_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_mem_server_axi4_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
8'd42;
llc_mem_server_axi4_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
74'h0AAAAAAAAAAAAAAAAAA;
llc_mem_server_axi4_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
75'h2AAAAAAAAAAAAAAAAAA;
llc_mem_server_enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY
66'h0AAAAAAAAAAAAAAAA;
llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'd1;
llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY
10'd0;
llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY 3'd3;
mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY 7'd0;
mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_fromHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_fromHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_fromHostQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmioPlatform_fromHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_toHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
mmioPlatform_toHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmioPlatform_toHostQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
4'd0;
mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY
1'd0;
mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
98'h0AAAAAAAAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
98'h0AAAAAAAAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
7'd42;
mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
73'h0AAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
75'h2AAAAAAAAAAAAAAAAAA;
propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY 73'h0AAAAAAAAAAAAAAAAAA;
propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
srcRR_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (enqDst_0_rl$EN)
enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_0_rl$D_IN;
if (enqDst_1_0_rl$EN)
enqDst_1_0_rl <= `BSV_ASSIGNMENT_DELAY enqDst_1_0_rl$D_IN;
if (llc_axi4_adapter_cfg_verbosity$EN)
llc_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_cfg_verbosity$D_IN;
if (llc_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
llc_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
if (llc_axi4_adapter_master_xactor_clearing$EN)
llc_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_clearing$D_IN;
if (llc_axi4_adapter_master_xactor_shim_arff_rv$EN)
llc_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_shim_arff_rv$D_IN;
if (llc_axi4_adapter_master_xactor_shim_awff_rv$EN)
llc_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_shim_awff_rv$D_IN;
if (llc_axi4_adapter_master_xactor_shim_bff_rv$EN)
llc_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_shim_bff_rv$D_IN;
if (llc_axi4_adapter_master_xactor_shim_rff_rv$EN)
llc_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_shim_rff_rv$D_IN;
if (llc_axi4_adapter_master_xactor_shim_wff_rv$EN)
llc_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_master_xactor_shim_wff_rv$D_IN;
if (llc_axi4_adapter_rg_rd_req_beat$EN)
llc_axi4_adapter_rg_rd_req_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_rd_req_beat$D_IN;
if (llc_axi4_adapter_rg_rd_rsp_beat$EN)
llc_axi4_adapter_rg_rd_rsp_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_rd_rsp_beat$D_IN;
if (llc_axi4_adapter_rg_wr_req_beat$EN)
llc_axi4_adapter_rg_wr_req_beat <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_wr_req_beat$D_IN;
if (llc_mem_server_axi4_slave_xactor_clearing$EN)
llc_mem_server_axi4_slave_xactor_clearing <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_axi4_slave_xactor_clearing$D_IN;
if (llc_mem_server_axi4_slave_xactor_shim_arff_rv$EN)
llc_mem_server_axi4_slave_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_axi4_slave_xactor_shim_arff_rv$D_IN;
if (llc_mem_server_axi4_slave_xactor_shim_awff_rv$EN)
llc_mem_server_axi4_slave_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_axi4_slave_xactor_shim_awff_rv$D_IN;
if (llc_mem_server_axi4_slave_xactor_shim_bff_rv$EN)
llc_mem_server_axi4_slave_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_axi4_slave_xactor_shim_bff_rv$D_IN;
if (llc_mem_server_axi4_slave_xactor_shim_rff_rv$EN)
llc_mem_server_axi4_slave_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_axi4_slave_xactor_shim_rff_rv$D_IN;
if (llc_mem_server_axi4_slave_xactor_shim_wff_rv$EN)
llc_mem_server_axi4_slave_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_axi4_slave_xactor_shim_wff_rv$D_IN;
if (llc_mem_server_enqDst_0_rl$EN)
llc_mem_server_enqDst_0_rl <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_enqDst_0_rl$D_IN;
if (llc_mem_server_propDstData_0_rl$EN)
llc_mem_server_propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_propDstData_0_rl$D_IN;
if (llc_mem_server_propDstIdx_0_rl$EN)
llc_mem_server_propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_propDstIdx_0_rl$D_IN;
if (llc_mem_server_rg_cacheline_cache_addr$EN)
llc_mem_server_rg_cacheline_cache_addr <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_rg_cacheline_cache_addr$D_IN;
if (llc_mem_server_rg_cacheline_cache_dirty_delay$EN)
llc_mem_server_rg_cacheline_cache_dirty_delay <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_rg_cacheline_cache_dirty_delay$D_IN;
if (llc_mem_server_rg_cacheline_cache_state$EN)
llc_mem_server_rg_cacheline_cache_state <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_rg_cacheline_cache_state$D_IN;
if (mmioPlatform_cycle$EN)
mmioPlatform_cycle <= `BSV_ASSIGNMENT_DELAY mmioPlatform_cycle$D_IN;
if (mmioPlatform_fromHostAddr$EN)
mmioPlatform_fromHostAddr <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostAddr$D_IN;
if (mmioPlatform_fromHostQ_clearReq_rl$EN)
mmioPlatform_fromHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_clearReq_rl$D_IN;
if (mmioPlatform_fromHostQ_data_0$EN)
mmioPlatform_fromHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_data_0$D_IN;
if (mmioPlatform_fromHostQ_deqReq_rl$EN)
mmioPlatform_fromHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_deqReq_rl$D_IN;
if (mmioPlatform_fromHostQ_empty$EN)
mmioPlatform_fromHostQ_empty <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_empty$D_IN;
if (mmioPlatform_fromHostQ_enqReq_rl$EN)
mmioPlatform_fromHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_enqReq_rl$D_IN;
if (mmioPlatform_fromHostQ_full$EN)
mmioPlatform_fromHostQ_full <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fromHostQ_full$D_IN;
if (mmioPlatform_mtime$EN)
mmioPlatform_mtime <= `BSV_ASSIGNMENT_DELAY mmioPlatform_mtime$D_IN;
if (mmioPlatform_mtimecmp_0$EN)
mmioPlatform_mtimecmp_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_mtimecmp_0$D_IN;
if (mmioPlatform_mtip_0$EN)
mmioPlatform_mtip_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_mtip_0$D_IN;
if (mmioPlatform_state$EN)
mmioPlatform_state <= `BSV_ASSIGNMENT_DELAY mmioPlatform_state$D_IN;
if (mmioPlatform_toHostAddr$EN)
mmioPlatform_toHostAddr <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostAddr$D_IN;
if (mmioPlatform_toHostQ_clearReq_rl$EN)
mmioPlatform_toHostQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_clearReq_rl$D_IN;
if (mmioPlatform_toHostQ_data_0$EN)
mmioPlatform_toHostQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_data_0$D_IN;
if (mmioPlatform_toHostQ_deqReq_rl$EN)
mmioPlatform_toHostQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_deqReq_rl$D_IN;
if (mmioPlatform_toHostQ_empty$EN)
mmioPlatform_toHostQ_empty <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_empty$D_IN;
if (mmioPlatform_toHostQ_enqReq_rl$EN)
mmioPlatform_toHostQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_enqReq_rl$D_IN;
if (mmioPlatform_toHostQ_full$EN)
mmioPlatform_toHostQ_full <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_toHostQ_full$D_IN;
if (mmio_axi4_adapter_cfg_verbosity$EN)
mmio_axi4_adapter_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_cfg_verbosity$D_IN;
if (mmio_axi4_adapter_ctr_wr_rsps_pending_crg$EN)
mmio_axi4_adapter_ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_ctr_wr_rsps_pending_crg$D_IN;
if (mmio_axi4_adapter_master_xactor_clearing$EN)
mmio_axi4_adapter_master_xactor_clearing <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_clearing$D_IN;
if (mmio_axi4_adapter_master_xactor_shim_arff_rv$EN)
mmio_axi4_adapter_master_xactor_shim_arff_rv <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_shim_arff_rv$D_IN;
if (mmio_axi4_adapter_master_xactor_shim_awff_rv$EN)
mmio_axi4_adapter_master_xactor_shim_awff_rv <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_shim_awff_rv$D_IN;
if (mmio_axi4_adapter_master_xactor_shim_bff_rv$EN)
mmio_axi4_adapter_master_xactor_shim_bff_rv <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_shim_bff_rv$D_IN;
if (mmio_axi4_adapter_master_xactor_shim_rff_rv$EN)
mmio_axi4_adapter_master_xactor_shim_rff_rv <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_shim_rff_rv$D_IN;
if (mmio_axi4_adapter_master_xactor_shim_wff_rv$EN)
mmio_axi4_adapter_master_xactor_shim_wff_rv <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_master_xactor_shim_wff_rv$D_IN;
if (propDstData_0_rl$EN)
propDstData_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_0_rl$D_IN;
if (propDstData_1_0_rl$EN)
propDstData_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_0_rl$D_IN;
if (propDstData_1_1_rl$EN)
propDstData_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_1_rl$D_IN;
if (propDstData_1_rl$EN)
propDstData_1_rl <= `BSV_ASSIGNMENT_DELAY propDstData_1_rl$D_IN;
if (propDstIdx_0_rl$EN)
propDstIdx_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_0_rl$D_IN;
if (propDstIdx_1_0_rl$EN)
propDstIdx_1_0_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_0_rl$D_IN;
if (propDstIdx_1_1_rl$EN)
propDstIdx_1_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_1_rl$D_IN;
if (propDstIdx_1_rl$EN)
propDstIdx_1_rl <= `BSV_ASSIGNMENT_DELAY propDstIdx_1_rl$D_IN;
if (srcRR_0$EN) srcRR_0 <= `BSV_ASSIGNMENT_DELAY srcRR_0$D_IN;
if (srcRR_1_0$EN) srcRR_1_0 <= `BSV_ASSIGNMENT_DELAY srcRR_1_0$D_IN;
end
if (llc_axi4_adapter_rg_cline$EN)
llc_axi4_adapter_rg_cline <= `BSV_ASSIGNMENT_DELAY
llc_axi4_adapter_rg_cline$D_IN;
if (llc_mem_server_rg_cacheline_cache_data$EN)
llc_mem_server_rg_cacheline_cache_data <= `BSV_ASSIGNMENT_DELAY
llc_mem_server_rg_cacheline_cache_data$D_IN;
if (mmioPlatform_amoResp$EN)
mmioPlatform_amoResp <= `BSV_ASSIGNMENT_DELAY mmioPlatform_amoResp$D_IN;
if (mmioPlatform_curReq$EN)
mmioPlatform_curReq <= `BSV_ASSIGNMENT_DELAY mmioPlatform_curReq$D_IN;
if (mmioPlatform_fetchedInsts_0$EN)
mmioPlatform_fetchedInsts_0 <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fetchedInsts_0$D_IN;
if (mmioPlatform_fetchingWay$EN)
mmioPlatform_fetchingWay <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_fetchingWay$D_IN;
if (mmioPlatform_instSel$EN)
mmioPlatform_instSel <= `BSV_ASSIGNMENT_DELAY mmioPlatform_instSel$D_IN;
if (mmioPlatform_reqAmofunc$EN)
mmioPlatform_reqAmofunc <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_reqAmofunc$D_IN;
if (mmioPlatform_reqBE$EN)
mmioPlatform_reqBE <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqBE$D_IN;
if (mmioPlatform_reqData$EN)
mmioPlatform_reqData <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqData$D_IN;
if (mmioPlatform_reqFunc$EN)
mmioPlatform_reqFunc <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqFunc$D_IN;
if (mmioPlatform_reqSz$EN)
mmioPlatform_reqSz <= `BSV_ASSIGNMENT_DELAY mmioPlatform_reqSz$D_IN;
if (mmioPlatform_waitLowerMSIPCRs$EN)
mmioPlatform_waitLowerMSIPCRs <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_waitLowerMSIPCRs$D_IN;
if (mmioPlatform_waitMTIPCRs$EN)
mmioPlatform_waitMTIPCRs <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_waitMTIPCRs$D_IN;
if (mmioPlatform_waitUpperMSIPCRs$EN)
mmioPlatform_waitUpperMSIPCRs <= `BSV_ASSIGNMENT_DELAY
mmioPlatform_waitUpperMSIPCRs$D_IN;
if (mmio_axi4_adapter_read_req_addr$EN)
mmio_axi4_adapter_read_req_addr <= `BSV_ASSIGNMENT_DELAY
mmio_axi4_adapter_read_req_addr$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
enqDst_0_rl = 74'h2AAAAAAAAAAAAAAAAAA;
enqDst_1_0_rl =
585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_cfg_verbosity = 4'hA;
llc_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
llc_axi4_adapter_master_xactor_clearing = 1'h0;
llc_axi4_adapter_master_xactor_shim_arff_rv =
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_shim_awff_rv =
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_shim_bff_rv = 8'hAA;
llc_axi4_adapter_master_xactor_shim_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_rg_cline =
516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_axi4_adapter_rg_rd_req_beat = 3'h2;
llc_axi4_adapter_rg_rd_rsp_beat = 3'h2;
llc_axi4_adapter_rg_wr_req_beat = 3'h2;
llc_mem_server_axi4_slave_xactor_clearing = 1'h0;
llc_mem_server_axi4_slave_xactor_shim_arff_rv =
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_mem_server_axi4_slave_xactor_shim_awff_rv =
99'h2AAAAAAAAAAAAAAAAAAAAAAAA;
llc_mem_server_axi4_slave_xactor_shim_bff_rv = 8'hAA;
llc_mem_server_axi4_slave_xactor_shim_rff_rv = 74'h2AAAAAAAAAAAAAAAAAA;
llc_mem_server_axi4_slave_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA;
llc_mem_server_enqDst_0_rl = 66'h2AAAAAAAAAAAAAAAA;
llc_mem_server_propDstData_0_rl = 65'h0AAAAAAAAAAAAAAAA;
llc_mem_server_propDstIdx_0_rl = 1'h0;
llc_mem_server_rg_cacheline_cache_addr = 64'hAAAAAAAAAAAAAAAA;
llc_mem_server_rg_cacheline_cache_data =
516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
llc_mem_server_rg_cacheline_cache_dirty_delay = 10'h2AA;
llc_mem_server_rg_cacheline_cache_state = 3'h2;
mmioPlatform_amoResp = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmioPlatform_curReq = 67'h2AAAAAAAAAAAAAAAA;
mmioPlatform_cycle = 7'h2A;
mmioPlatform_fetchedInsts_0 = 32'hAAAAAAAA;
mmioPlatform_fetchingWay = 1'h0;
mmioPlatform_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_clearReq_rl = 1'h0;
mmioPlatform_fromHostQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_deqReq_rl = 1'h0;
mmioPlatform_fromHostQ_empty = 1'h0;
mmioPlatform_fromHostQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_fromHostQ_full = 1'h0;
mmioPlatform_instSel = 2'h2;
mmioPlatform_mtime = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_mtimecmp_0 = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_mtip_0 = 1'h0;
mmioPlatform_reqAmofunc = 4'hA;
mmioPlatform_reqBE = 16'hAAAA;
mmioPlatform_reqData = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmioPlatform_reqFunc = 6'h2A;
mmioPlatform_reqSz = 2'h2;
mmioPlatform_state = 2'h2;
mmioPlatform_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_clearReq_rl = 1'h0;
mmioPlatform_toHostQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_deqReq_rl = 1'h0;
mmioPlatform_toHostQ_empty = 1'h0;
mmioPlatform_toHostQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
mmioPlatform_toHostQ_full = 1'h0;
mmioPlatform_waitLowerMSIPCRs = 1'h0;
mmioPlatform_waitMTIPCRs = 1'h0;
mmioPlatform_waitUpperMSIPCRs = 1'h0;
mmio_axi4_adapter_cfg_verbosity = 4'hA;
mmio_axi4_adapter_ctr_wr_rsps_pending_crg = 4'hA;
mmio_axi4_adapter_master_xactor_clearing = 1'h0;
mmio_axi4_adapter_master_xactor_shim_arff_rv =
98'h2AAAAAAAAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_shim_awff_rv =
98'h2AAAAAAAAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_shim_bff_rv = 7'h2A;
mmio_axi4_adapter_master_xactor_shim_rff_rv = 73'h0AAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_master_xactor_shim_wff_rv = 75'h2AAAAAAAAAAAAAAAAAA;
mmio_axi4_adapter_read_req_addr = 64'hAAAAAAAAAAAAAAAA;
propDstData_0_rl = 73'h0AAAAAAAAAAAAAAAAAA;
propDstData_1_0_rl =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_1_rl =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
propDstData_1_rl = 73'h0AAAAAAAAAAAAAAAAAA;
propDstIdx_0_rl = 1'h0;
propDstIdx_1_0_rl = 1'h0;
propDstIdx_1_1_rl = 1'h0;
propDstIdx_1_rl = 1'h0;
srcRR_0 = 1'h0;
srcRR_1_0 = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_start)
begin
v__h199287 = $stime;
#0;
end
v__h199281 = v__h199287 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_start)
$display("%0d: %m.method start: startpc %0h, tohostAddr %0h, fromhostAddr %0h",
v__h199281,
start_startpc,
start_tohostAddr,
start_fromhostAddr);
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_rl_161_BIT_73_162_167_AND_SEL_ARR_ETC___d1255 &&
IF_propDstIdx_0_lat_0_whas__129_THEN_NOT_propD_ETC___d1195)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_0_rl_161_BIT_73_162_167_AND_SEL_ARR_ETC___d1260)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_rl_360_BIT_584_361_366_AND_SEL__ETC___d1556 &&
IF_propDstIdx_1_0_lat_0_whas__266_THEN_NOT_pro_ETC___d1432)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (NOT_enqDst_1_0_rl_360_BIT_584_361_366_AND_SEL__ETC___d1561)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (core_0$RDY_coreIndInv_terminate)
$display("Core %d terminated", $signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost)
begin
v__h198828 = $stime;
#0;
end
v__h198822 = v__h198828 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost)
$display("%0d: mmioPlatform.rl_tohost: 0x%0x (= %0d)",
v__h198822,
mmioPlatform_toHostQ_data_0,
mmioPlatform_toHostQ_data_0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 &&
mmioPlatform_toHostQ_data_0[63:1] == 63'd0)
$display("PASS");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0 &&
mmioPlatform_toHostQ_data_0[63:1] != 63'd0)
$display("FAIL %0d", failed_testnum__h198871);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_tohost && mmioPlatform_toHostQ_data_0 != 64'd0)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h11334 = $stime;
#0;
end
v__h11328 = v__h11334 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%d: %m.rl_handle_write_req: St request:", v__h11328);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("tagged St ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("TaggedData { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h15872 = $stime;
#0;
end
v__h15866 = v__h15872 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h15866);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h16015 = $stime;
#0;
end
v__h16009 = v__h16015 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_handle_write_req: unmapped IO address; returning error response",
v__h16009);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("tagged St ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("TaggedData { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_write_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h4355 = $stime;
#0;
end
v__h4349 = v__h4355 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_handle_read_req: Ld request", v__h4349);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("tagged Ld ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("TaggedData { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_ARFlit { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_Size { ", "val: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 3'b011, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("INCR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("NORMAL");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h7976 = $stime;
#0;
end
v__h7970 = v__h7976 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_handle_read_req: unmapped IO address; returning error response",
v__h7970);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("tagged Ld ", "");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("TaggedData { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_req &&
!mmio_axi4_adapter_soc_map$m_is_IO_addr &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
begin
v__h19401 = $stime;
#0;
end
v__h19395 = v__h19401 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$display("%0d:%m.rl_handle_non_Ld_St: ERROR: neither Ld nor St? exit.",
v__h19395);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("MMIOCRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[214:151]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write(", ", "func: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd0)
$write("tagged Inst ",
"'h%h",
mmio_axi4_adapter_f_reqs_from_core$D_OUT[145]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0)
$write("tagged Amo ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd0)
$write("Swap");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd1)
$write("Add");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd2)
$write("Xor");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd3)
$write("And");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd4)
$write("Or");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd5)
$write("Min");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd6)
$write("Max");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd7)
$write("Minu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] == 4'd8)
$write("Maxu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[150:149] != 2'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd0 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd1 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd2 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd3 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd4 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd5 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd6 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd7 &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[148:145] != 4'd8)
$write("None");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[129])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[130])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[131])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[132])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[133])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[134])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[135])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[136])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[137])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[138])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[139])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[140])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[141])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[142])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[143])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[144])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("TaggedData { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St &&
!mmio_axi4_adapter_f_reqs_from_core$D_OUT[128])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[63:0], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St)
$write("'h%h", mmio_axi4_adapter_f_reqs_from_core$D_OUT[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_non_Ld_St) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut)
$display("WARNING: putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h18404 = $stime;
#0;
end
v__h18398 = v__h18404 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_discard_write_rsp", v__h18398);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_BFlit { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] ==
2'd0)
$write("OKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] ==
2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] ==
2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd1 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
begin
v__h18934 = $stime;
#0;
end
v__h18928 = v__h18934 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$display("%0d:%m.rl_discard_write_rsp: ERROR: fabric response error: exit.",
v__h18928);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$write("AXI4_BFlit { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] ==
2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] ==
2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd1 &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_discard_write_rsp &&
mmio_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut)
$display("WARNING: putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
begin
v__h10395 = $stime;
#0;
end
v__h10389 = v__h10395 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_handle_read_rsps ", v__h10389);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("AXI4_RFlit { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] ==
2'd0)
$write("OKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] ==
2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] ==
2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd1 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
!mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0],
" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
begin
v__h10590 = $stime;
#0;
end
v__h10584 = v__h10590 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$display("%0d: %m.rl_handle_read_rsp: fabric response error",
v__h10584);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write("AXI4_RFlit { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[71:68]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] ==
2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] ==
2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd1 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
!mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write("'h%h",
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0],
" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" Response MMIO to core: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("MMIODataPRs { ", "valid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] ==
2'd0)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0 &&
mmio_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("TaggedData { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h",
_0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213[63:0],
" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("'h%h",
_0_CONCAT_mmio_axi4_adapter_master_xactor_shim__ETC___d213[127:64],
" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmio_axi4_adapter_rl_handle_read_rsps &&
mmio_axi4_adapter_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmioPlatform_processToHost &&
mmioPlatform_reqFunc[5:4] == 2'd2 &&
!mmioPlatform_toHostQ_empty)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmioPlatform_processToHost &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd2 &&
mmioPlatform_reqFunc[5:4] != 2'd1)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
mmioPlatform_reqFunc[5:4] == 2'd2 &&
mmioPlatform_fromHostQ_empty &&
x__h54199 != 64'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
mmioPlatform_reqFunc[5:4] == 2'd2 &&
!mmioPlatform_fromHostQ_empty &&
x__h51463 != 64'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_mmioPlatform_processFromHost &&
mmioPlatform_reqFunc[5:4] != 2'd0 &&
mmioPlatform_reqFunc[5:4] != 2'd2 &&
mmioPlatform_reqFunc[5:4] != 2'd1)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (!llc_mem_server_enqDst_0_rl[65] &&
IF_llc_mem_server_propDstIdx_0_lat_0_whas__818_ETC___d1821 &&
!CAN_FIRE_RL_llc_mem_server_srcPropose &&
!llc_mem_server_propDstIdx_0_rl)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_mem_server_sendStRespToTlb)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_aw_warnDoPut)
$display("WARNING: putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_w_warnDoPut)
$display("WARNING: putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_ar_warnDoPut)
$display("WARNING: putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_b_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_mem_server_axi4_slave_xactor_ug_slave_u_r_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
begin
v__h176479 = $stime;
#0;
end
v__h176473 = v__h176479 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$display("%d: LLC_AXI4_Adapter.rl_handle_write_req: Wb request from LLC to memory:",
v__h176473);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("WbMemRs { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[643:580]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(", ", "byteEn: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[516])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[516])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[517])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[517])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[518])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[518])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[519])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[519])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[520])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[520])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[521])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[521])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[522])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[522])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[523])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[523])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[524])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[524])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[525])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[525])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[526])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[526])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[527])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[527])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[528])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[528])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[529])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[529])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[530])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[530])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[531])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[531])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[532])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[532])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[533])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[533])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[534])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[534])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[535])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[535])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[536])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[536])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[537])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[537])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[538])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[538])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[539])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[539])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[540])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[540])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[541])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[541])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[542])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[542])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[543])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[543])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[544])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[544])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[545])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[545])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[546])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[546])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[547])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[547])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[548])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[548])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[549])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[549])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[550])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[550])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[551])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[551])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[552])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[552])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[553])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[553])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[554])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[554])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[555])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[555])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[556])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[556])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[557])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[557])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[558])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[558])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[559])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[559])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[560])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[560])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[561])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[561])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[562])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[562])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[563])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[563])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[564])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[564])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[565])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[565])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[566])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[566])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[567])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[567])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[568])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[568])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[569])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[569])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[570])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[570])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[571])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[571])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[572])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[572])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[573])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[573])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[574])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[574])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[575])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[575])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[576])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[576])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[577])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[577])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[578])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[578])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[579])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[579])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("CLine { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[512])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[512])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[513])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[513])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[514])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[514])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc$to_mem_toM_first[515])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
!llc$to_mem_toM_first[515])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[63:0], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[191:128], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[255:192], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[319:256], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[383:320], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[447:384], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[511:448], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h190188 = $stime;
#0;
end
v__h190182 = v__h190188 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h190182);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_write_req &&
llc_axi4_adapter_rg_wr_req_beat == 3'd0 &&
llc_axi4_adapter_ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
begin
v__h168458 = $stime;
#0;
end
v__h168452 = v__h168458 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$display("%0d: LLC_AXI4_Adapter.rl_handle_read_req: Ld request from LLC to memory: beat %0d",
v__h168452,
llc_axi4_adapter_rg_rd_req_beat);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("LdMemRq { ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[68:5]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(", ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("LdMemRqId { ", "refill: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0 &&
llc$to_mem_toM_first[4])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0 &&
!llc$to_mem_toM_first[4])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(", ", "mshrIdx: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("'h%h", llc$to_mem_toM_first[3:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
llc_axi4_adapter_cfg_verbosity != 4'd0 &&
llc_axi4_adapter_rg_rd_req_beat == 3'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("AXI4_ARFlit { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 5'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", line_addr__h168594);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 8'd7);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("AXI4_Size { ", "val: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 3'b011, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("INCR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("NORMAL");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_req &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_aw_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_w_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_b_warnDoPut)
$display("WARNING: putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
begin
v__h197814 = $stime;
#0;
end
v__h197808 = v__h197814 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$display("%0d: LLC_AXI4_Adapter.rl_discard_write_rsp: fabric response error: exit",
v__h197808);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$write("AXI4_BFlit { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[6:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] == 2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd0 &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] !=
2'd1 &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_discard_write_rsp &&
llc_axi4_adapter_master_xactor_shim_bff_rv$port1__read[1:0] != 2'd0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_ar_warnDoDrop)
$display("WARNING: dropping from Source that can't be dropped from");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_master_xactor_ug_master_u_r_warnDoPut)
$display("WARNING: putting into a Sink that can't be put into");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
begin
v__h169047 = $stime;
#0;
end
v__h169041 = v__h169047 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsps: beat %0d ",
v__h169041,
llc_axi4_adapter_rg_rd_rsp_beat);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("AXI4_RFlit { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd0)
$write("OKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd1 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
!llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0],
" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
begin
v__h169233 = $stime;
#0;
end
v__h169227 = v__h169233 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$display("%0d: LLC_AXI4_Adapter.rl_handle_read_rsp: fabric response error; exit",
v__h169227);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("AXI4_RFlit { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[72:68]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd1)
$write("EXOKAY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] == 2'd2)
$write("SLVERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd1 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd2)
$write("DECERR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] !=
2'd0 &&
!llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[1])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[0],
" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[3:2] != 2'd0)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" Response to LLC: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("MemRsMsg { ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("CLine { ", "tag: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
!llc_axi4_adapter_rg_cline[512] :
!llc_axi4_adapter_rg_cline[513]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
llc_axi4_adapter_rg_cline[512] :
llc_axi4_adapter_rg_cline[513]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
!llc_axi4_adapter_rg_cline[513] :
!llc_axi4_adapter_rg_cline[514]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
llc_axi4_adapter_rg_cline[513] :
llc_axi4_adapter_rg_cline[514]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
!llc_axi4_adapter_rg_cline[514] :
!llc_axi4_adapter_rg_cline[515]))
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
(llc_axi4_adapter_rg_rd_rsp_beat[0] ?
llc_axi4_adapter_rg_cline[514] :
llc_axi4_adapter_rg_cline[515]))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d2046)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d2049)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_rg_cline[127:64], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_rg_cline[191:128], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_rg_cline[255:192], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_rg_cline[319:256], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_rg_cline[383:320], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_rg_cline[447:384], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("<V ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_rg_cline[511:448], " ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h",
llc_axi4_adapter_master_xactor_shim_rff_rv$port1__read[67:4],
" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" >");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "child: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("LdMemRqId { ", "refill: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
llc_axi4_adapter_f_pending_reads$D_OUT[4])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967 &&
!llc_axi4_adapter_f_pending_reads$D_OUT[4])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(", ", "mshrIdx: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("'h%h", llc_axi4_adapter_f_pending_reads$D_OUT[3:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write(" }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_llc_axi4_adapter_rl_handle_read_rsps &&
llc_axi4_adapter_rg_rd_rsp_beat == 3'd7 &&
NOT_llc_axi4_adapter_cfg_verbosity_read__949_U_ETC___d1967)
$write("\n");
end
// synopsys translate_on
endmodule // mkProc
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