83 lines
2.6 KiB
Plaintext
83 lines
2.6 KiB
Plaintext
Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
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>================================================================
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The './isa' sub-directory contains pre-built ELF and objdump files
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(.dump) for all the standard RISC-V ISA tests. For example, the
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files:
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./isa/rv32ui-p-add
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./isa/rv32ui-p-add.dump
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are an ELF file and its objdump (disassembly) that tests the RISC-V
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user-level integer ADD instruction for RV32. The tests are built when
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one clones the following GitHub repository:
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https://github.com/riscv/riscv-tools.git
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and follows the build directions therein, resulting in all the ISA
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tests being built, such as this:
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<riscv-tools build dir>/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-add
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>================================================================
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The Makefile has a command to run regressions on ISA tests.
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$ make test
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In the Makefile, you will see definitions for ARCH (such as `RV32IMU`)
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and SIM (such as `verilator`), which together specify which simulator
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will be run (`builds/<ARCH>_SIM/exe_HW_sim`). You can change the ARCH
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and SIM definitions in the Makefile for a different simulator, or
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redefine them on the `make` command line.
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It will run the the Python program 'Run_regression.py', described
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below, to run the simulator on all the ISA tests relevant to the
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architecture ARCH. A per-ISA-test log is captured in the 'Logs/'
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directory.
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>================================================================
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With the Python program './Run_regression.py' you can run a regression
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on all the standard RISC-V ISA tests that are relevant to your RISC-V
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simulation executable (i.e., for the RISC-V features and extensions
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supported by your simulation executable).
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Please do:
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$ ./Run_regression.py --help
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for usage information.
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Example:
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$ ./Run_regression.py ../RV32IMU_verilator/exe_HW_sim ./isa ./Logs v1
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will run the verilator simulation executable on the all RISC-V ISA
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tests that match the following:
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./isa/rv32ui-p*
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./isa/rv32mi-p*
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./isa/rv32um-p*
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and leave a transcript of each test's simulation output in files like
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./Logs/rv32ui-p-add.log
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Each log will contain an instruction trace.
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Example:
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$ ./Run_regression.py ../RV64AIMSU_verilator/exe_HW_sim ./isa ./Logs v1
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will run the verilator simulation executable on the all RISC-V ISA
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tests that match the following:
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./isa/rv64ui-p*
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./isa/rv64um-p*
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./isa/rv64ua-p*
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./isa/rv64mi-p*
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./isa/rv64si-p*
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./isa/rv64ui-v*
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./isa/rv64um-v*
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./isa/rv64ua-v*
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>================================================================
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