Files
Toooba/src_Core/RISCY_OOO/procs/lib
rsnikhil 83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
2020-02-04 16:02:53 -05:00
..
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-12-06 14:27:33 +05:30
2020-01-02 01:12:51 +00:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-12-06 14:27:33 +05:30
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00
2019-03-26 14:49:40 -04:00