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e02b352bbb8a4af89ff729dca34aa43aa047a5dd
Toooba/src_SSITH_P3/Verilog_RTL/mkCore.v
rsnikhil 83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module 
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
2020-02-04 16:02:53 -05:00

40490 lines
1.8 MiB
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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_coreReq_start O 1 const
// RDY_coreReq_perfReq O 1 reg
// coreIndInv_perfResp O 73
// RDY_coreIndInv_perfResp O 1 reg
// RDY_coreIndInv_terminate O 1 reg
// dCacheToParent_rsToP_notEmpty O 1
// RDY_dCacheToParent_rsToP_notEmpty O 1 const
// RDY_dCacheToParent_rsToP_deq O 1
// dCacheToParent_rsToP_first O 579
// RDY_dCacheToParent_rsToP_first O 1
// dCacheToParent_rqToP_notEmpty O 1
// RDY_dCacheToParent_rqToP_notEmpty O 1 const
// RDY_dCacheToParent_rqToP_deq O 1
// dCacheToParent_rqToP_first O 72
// RDY_dCacheToParent_rqToP_first O 1
// dCacheToParent_fromP_notFull O 1
// RDY_dCacheToParent_fromP_notFull O 1 const
// RDY_dCacheToParent_fromP_enq O 1
// iCacheToParent_rsToP_notEmpty O 1
// RDY_iCacheToParent_rsToP_notEmpty O 1 const
// RDY_iCacheToParent_rsToP_deq O 1
// iCacheToParent_rsToP_first O 579
// RDY_iCacheToParent_rsToP_first O 1
// iCacheToParent_rqToP_notEmpty O 1
// RDY_iCacheToParent_rqToP_notEmpty O 1 const
// RDY_iCacheToParent_rqToP_deq O 1
// iCacheToParent_rqToP_first O 72
// RDY_iCacheToParent_rqToP_first O 1
// iCacheToParent_fromP_notFull O 1
// RDY_iCacheToParent_fromP_notFull O 1 const
// RDY_iCacheToParent_fromP_enq O 1
// tlbToMem_memReq_notEmpty O 1
// RDY_tlbToMem_memReq_notEmpty O 1 const
// RDY_tlbToMem_memReq_deq O 1
// tlbToMem_memReq_first O 65
// RDY_tlbToMem_memReq_first O 1
// tlbToMem_respLd_notFull O 1
// RDY_tlbToMem_respLd_notFull O 1 const
// RDY_tlbToMem_respLd_enq O 1
// mmioToPlatform_cRq_notEmpty O 1
// RDY_mmioToPlatform_cRq_notEmpty O 1 const
// RDY_mmioToPlatform_cRq_deq O 1
// mmioToPlatform_cRq_first O 142
// RDY_mmioToPlatform_cRq_first O 1
// mmioToPlatform_pRs_notFull O 1
// RDY_mmioToPlatform_pRs_notFull O 1 const
// RDY_mmioToPlatform_pRs_enq O 1
// mmioToPlatform_pRq_notFull O 1
// RDY_mmioToPlatform_pRq_notFull O 1 const
// RDY_mmioToPlatform_pRq_enq O 1
// mmioToPlatform_cRs_notEmpty O 1
// RDY_mmioToPlatform_cRs_notEmpty O 1 const
// RDY_mmioToPlatform_cRs_deq O 1
// mmioToPlatform_cRs_first O 1 reg
// RDY_mmioToPlatform_cRs_first O 1
// RDY_mmioToPlatform_setTime O 1 const
// sendDoStats O 1 reg
// RDY_sendDoStats O 1 reg
// RDY_recvDoStats O 1 const
// deadlock_dCacheCRqStuck_get O 73 const
// RDY_deadlock_dCacheCRqStuck_get O 1 const
// deadlock_dCachePRqStuck_get O 68 const
// RDY_deadlock_dCachePRqStuck_get O 1 const
// deadlock_iCacheCRqStuck_get O 68 const
// RDY_deadlock_iCacheCRqStuck_get O 1 const
// deadlock_iCachePRqStuck_get O 68 const
// RDY_deadlock_iCachePRqStuck_get O 1 const
// deadlock_renameInstStuck_get O 78 const
// RDY_deadlock_renameInstStuck_get O 1 const
// deadlock_renameCorrectPathStuck_get O 78 const
// RDY_deadlock_renameCorrectPathStuck_get O 1 const
// deadlock_commitInstStuck_get O 163 const
// RDY_deadlock_commitInstStuck_get O 1 const
// deadlock_commitUserInstStuck_get O 163 const
// RDY_deadlock_commitUserInstStuck_get O 1 const
// RDY_deadlock_checkStarted_get O 1 const
// renameDebug_renameErr_get O 89 const
// RDY_renameDebug_renameErr_get O 1 const
// RDY_setMEIP O 1 const
// RDY_setSEIP O 1 const
// RDY_hart0_run_halt_server_request_put O 1 reg
// hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_run_halt_server_response_get O 1 reg
// RDY_hart0_gpr_mem_server_request_put O 1 reg
// hart0_gpr_mem_server_response_get O 65 reg
// RDY_hart0_gpr_mem_server_response_get O 1 reg
// RDY_hart0_fpr_mem_server_request_put O 1 reg
// hart0_fpr_mem_server_response_get O 65 reg
// RDY_hart0_fpr_mem_server_response_get O 1 reg
// RDY_hart0_csr_mem_server_request_put O 1 reg
// hart0_csr_mem_server_response_get O 65 reg
// RDY_hart0_csr_mem_server_response_get O 1 reg
// v_to_TV_0_get O 320
// RDY_v_to_TV_0_get O 1 reg
// v_to_TV_1_get O 320
// RDY_v_to_TV_1_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// coreReq_start_startpc I 64
// coreReq_start_toHostAddr I 64 reg
// coreReq_start_fromHostAddr I 64 reg
// coreReq_perfReq_loc I 4 reg
// coreReq_perfReq_t I 5 reg
// dCacheToParent_fromP_enq_x I 583
// iCacheToParent_fromP_enq_x I 583
// tlbToMem_respLd_enq_x I 65
// mmioToPlatform_pRs_enq_x I 67
// mmioToPlatform_pRq_enq_x I 39
// mmioToPlatform_setTime_t I 64 reg
// recvDoStats_x I 1 reg
// setMEIP_v I 1
// setSEIP_v I 1
// hart0_run_halt_server_request_put I 1 reg
// hart0_gpr_mem_server_request_put I 70 reg
// hart0_fpr_mem_server_request_put I 70 reg
// hart0_csr_mem_server_request_put I 77 reg
// EN_coreReq_start I 1
// EN_coreReq_perfReq I 1
// EN_coreIndInv_terminate I 1
// EN_dCacheToParent_rsToP_deq I 1
// EN_dCacheToParent_rqToP_deq I 1
// EN_dCacheToParent_fromP_enq I 1
// EN_iCacheToParent_rsToP_deq I 1
// EN_iCacheToParent_rqToP_deq I 1
// EN_iCacheToParent_fromP_enq I 1
// EN_tlbToMem_memReq_deq I 1
// EN_tlbToMem_respLd_enq I 1
// EN_mmioToPlatform_cRq_deq I 1
// EN_mmioToPlatform_pRs_enq I 1
// EN_mmioToPlatform_pRq_enq I 1
// EN_mmioToPlatform_cRs_deq I 1
// EN_mmioToPlatform_setTime I 1
// EN_recvDoStats I 1
// EN_deadlock_checkStarted_get I 1 unused
// EN_setMEIP I 1
// EN_setSEIP I 1
// EN_hart0_run_halt_server_request_put I 1
// EN_hart0_gpr_mem_server_request_put I 1
// EN_hart0_fpr_mem_server_request_put I 1
// EN_hart0_csr_mem_server_request_put I 1
// EN_coreIndInv_perfResp I 1
// EN_sendDoStats I 1
// EN_deadlock_dCacheCRqStuck_get I 1 unused
// EN_deadlock_dCachePRqStuck_get I 1 unused
// EN_deadlock_iCacheCRqStuck_get I 1 unused
// EN_deadlock_iCachePRqStuck_get I 1 unused
// EN_deadlock_renameInstStuck_get I 1 unused
// EN_deadlock_renameCorrectPathStuck_get I 1 unused
// EN_deadlock_commitInstStuck_get I 1 unused
// EN_deadlock_commitUserInstStuck_get I 1 unused
// EN_renameDebug_renameErr_get I 1 unused
// EN_hart0_run_halt_server_response_get I 1
// EN_hart0_gpr_mem_server_response_get I 1
// EN_hart0_fpr_mem_server_response_get I 1
// EN_hart0_csr_mem_server_response_get I 1
// EN_v_to_TV_0_get I 1
// EN_v_to_TV_1_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCore(CLK,
RST_N,
coreReq_start_startpc,
coreReq_start_toHostAddr,
coreReq_start_fromHostAddr,
EN_coreReq_start,
RDY_coreReq_start,
coreReq_perfReq_loc,
coreReq_perfReq_t,
EN_coreReq_perfReq,
RDY_coreReq_perfReq,
EN_coreIndInv_perfResp,
coreIndInv_perfResp,
RDY_coreIndInv_perfResp,
EN_coreIndInv_terminate,
RDY_coreIndInv_terminate,
dCacheToParent_rsToP_notEmpty,
RDY_dCacheToParent_rsToP_notEmpty,
EN_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_deq,
dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_first,
dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rqToP_notEmpty,
EN_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_deq,
dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_first,
dCacheToParent_fromP_notFull,
RDY_dCacheToParent_fromP_notFull,
dCacheToParent_fromP_enq_x,
EN_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_enq,
iCacheToParent_rsToP_notEmpty,
RDY_iCacheToParent_rsToP_notEmpty,
EN_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_deq,
iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_first,
iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rqToP_notEmpty,
EN_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_deq,
iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_first,
iCacheToParent_fromP_notFull,
RDY_iCacheToParent_fromP_notFull,
iCacheToParent_fromP_enq_x,
EN_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_enq,
tlbToMem_memReq_notEmpty,
RDY_tlbToMem_memReq_notEmpty,
EN_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_deq,
tlbToMem_memReq_first,
RDY_tlbToMem_memReq_first,
tlbToMem_respLd_notFull,
RDY_tlbToMem_respLd_notFull,
tlbToMem_respLd_enq_x,
EN_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_enq,
mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRq_notEmpty,
EN_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_deq,
mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_first,
mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_pRs_notFull,
mmioToPlatform_pRs_enq_x,
EN_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_enq,
mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRq_notFull,
mmioToPlatform_pRq_enq_x,
EN_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_enq,
mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_cRs_notEmpty,
EN_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_deq,
mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_first,
mmioToPlatform_setTime_t,
EN_mmioToPlatform_setTime,
RDY_mmioToPlatform_setTime,
EN_sendDoStats,
sendDoStats,
RDY_sendDoStats,
recvDoStats_x,
EN_recvDoStats,
RDY_recvDoStats,
EN_deadlock_dCacheCRqStuck_get,
deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
EN_deadlock_dCachePRqStuck_get,
deadlock_dCachePRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
EN_deadlock_iCacheCRqStuck_get,
deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
EN_deadlock_iCachePRqStuck_get,
deadlock_iCachePRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
EN_deadlock_renameInstStuck_get,
deadlock_renameInstStuck_get,
RDY_deadlock_renameInstStuck_get,
EN_deadlock_renameCorrectPathStuck_get,
deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
EN_deadlock_commitInstStuck_get,
deadlock_commitInstStuck_get,
RDY_deadlock_commitInstStuck_get,
EN_deadlock_commitUserInstStuck_get,
deadlock_commitUserInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
EN_deadlock_checkStarted_get,
RDY_deadlock_checkStarted_get,
EN_renameDebug_renameErr_get,
renameDebug_renameErr_get,
RDY_renameDebug_renameErr_get,
setMEIP_v,
EN_setMEIP,
RDY_setMEIP,
setSEIP_v,
EN_setSEIP,
RDY_setSEIP,
hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_request_put,
EN_hart0_run_halt_server_response_get,
hart0_run_halt_server_response_get,
RDY_hart0_run_halt_server_response_get,
hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_request_put,
EN_hart0_gpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_response_get,
hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_request_put,
EN_hart0_fpr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
RDY_hart0_fpr_mem_server_response_get,
hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_request_put,
EN_hart0_csr_mem_server_response_get,
hart0_csr_mem_server_response_get,
RDY_hart0_csr_mem_server_response_get,
EN_v_to_TV_0_get,
v_to_TV_0_get,
RDY_v_to_TV_0_get,
EN_v_to_TV_1_get,
v_to_TV_1_get,
RDY_v_to_TV_1_get);
input CLK;
input RST_N;
// action method coreReq_start
input [63 : 0] coreReq_start_startpc;
input [63 : 0] coreReq_start_toHostAddr;
input [63 : 0] coreReq_start_fromHostAddr;
input EN_coreReq_start;
output RDY_coreReq_start;
// action method coreReq_perfReq
input [3 : 0] coreReq_perfReq_loc;
input [4 : 0] coreReq_perfReq_t;
input EN_coreReq_perfReq;
output RDY_coreReq_perfReq;
// actionvalue method coreIndInv_perfResp
input EN_coreIndInv_perfResp;
output [72 : 0] coreIndInv_perfResp;
output RDY_coreIndInv_perfResp;
// action method coreIndInv_terminate
input EN_coreIndInv_terminate;
output RDY_coreIndInv_terminate;
// value method dCacheToParent_rsToP_notEmpty
output dCacheToParent_rsToP_notEmpty;
output RDY_dCacheToParent_rsToP_notEmpty;
// action method dCacheToParent_rsToP_deq
input EN_dCacheToParent_rsToP_deq;
output RDY_dCacheToParent_rsToP_deq;
// value method dCacheToParent_rsToP_first
output [578 : 0] dCacheToParent_rsToP_first;
output RDY_dCacheToParent_rsToP_first;
// value method dCacheToParent_rqToP_notEmpty
output dCacheToParent_rqToP_notEmpty;
output RDY_dCacheToParent_rqToP_notEmpty;
// action method dCacheToParent_rqToP_deq
input EN_dCacheToParent_rqToP_deq;
output RDY_dCacheToParent_rqToP_deq;
// value method dCacheToParent_rqToP_first
output [71 : 0] dCacheToParent_rqToP_first;
output RDY_dCacheToParent_rqToP_first;
// value method dCacheToParent_fromP_notFull
output dCacheToParent_fromP_notFull;
output RDY_dCacheToParent_fromP_notFull;
// action method dCacheToParent_fromP_enq
input [582 : 0] dCacheToParent_fromP_enq_x;
input EN_dCacheToParent_fromP_enq;
output RDY_dCacheToParent_fromP_enq;
// value method iCacheToParent_rsToP_notEmpty
output iCacheToParent_rsToP_notEmpty;
output RDY_iCacheToParent_rsToP_notEmpty;
// action method iCacheToParent_rsToP_deq
input EN_iCacheToParent_rsToP_deq;
output RDY_iCacheToParent_rsToP_deq;
// value method iCacheToParent_rsToP_first
output [578 : 0] iCacheToParent_rsToP_first;
output RDY_iCacheToParent_rsToP_first;
// value method iCacheToParent_rqToP_notEmpty
output iCacheToParent_rqToP_notEmpty;
output RDY_iCacheToParent_rqToP_notEmpty;
// action method iCacheToParent_rqToP_deq
input EN_iCacheToParent_rqToP_deq;
output RDY_iCacheToParent_rqToP_deq;
// value method iCacheToParent_rqToP_first
output [71 : 0] iCacheToParent_rqToP_first;
output RDY_iCacheToParent_rqToP_first;
// value method iCacheToParent_fromP_notFull
output iCacheToParent_fromP_notFull;
output RDY_iCacheToParent_fromP_notFull;
// action method iCacheToParent_fromP_enq
input [582 : 0] iCacheToParent_fromP_enq_x;
input EN_iCacheToParent_fromP_enq;
output RDY_iCacheToParent_fromP_enq;
// value method tlbToMem_memReq_notEmpty
output tlbToMem_memReq_notEmpty;
output RDY_tlbToMem_memReq_notEmpty;
// action method tlbToMem_memReq_deq
input EN_tlbToMem_memReq_deq;
output RDY_tlbToMem_memReq_deq;
// value method tlbToMem_memReq_first
output [64 : 0] tlbToMem_memReq_first;
output RDY_tlbToMem_memReq_first;
// value method tlbToMem_respLd_notFull
output tlbToMem_respLd_notFull;
output RDY_tlbToMem_respLd_notFull;
// action method tlbToMem_respLd_enq
input [64 : 0] tlbToMem_respLd_enq_x;
input EN_tlbToMem_respLd_enq;
output RDY_tlbToMem_respLd_enq;
// value method mmioToPlatform_cRq_notEmpty
output mmioToPlatform_cRq_notEmpty;
output RDY_mmioToPlatform_cRq_notEmpty;
// action method mmioToPlatform_cRq_deq
input EN_mmioToPlatform_cRq_deq;
output RDY_mmioToPlatform_cRq_deq;
// value method mmioToPlatform_cRq_first
output [141 : 0] mmioToPlatform_cRq_first;
output RDY_mmioToPlatform_cRq_first;
// value method mmioToPlatform_pRs_notFull
output mmioToPlatform_pRs_notFull;
output RDY_mmioToPlatform_pRs_notFull;
// action method mmioToPlatform_pRs_enq
input [66 : 0] mmioToPlatform_pRs_enq_x;
input EN_mmioToPlatform_pRs_enq;
output RDY_mmioToPlatform_pRs_enq;
// value method mmioToPlatform_pRq_notFull
output mmioToPlatform_pRq_notFull;
output RDY_mmioToPlatform_pRq_notFull;
// action method mmioToPlatform_pRq_enq
input [38 : 0] mmioToPlatform_pRq_enq_x;
input EN_mmioToPlatform_pRq_enq;
output RDY_mmioToPlatform_pRq_enq;
// value method mmioToPlatform_cRs_notEmpty
output mmioToPlatform_cRs_notEmpty;
output RDY_mmioToPlatform_cRs_notEmpty;
// action method mmioToPlatform_cRs_deq
input EN_mmioToPlatform_cRs_deq;
output RDY_mmioToPlatform_cRs_deq;
// value method mmioToPlatform_cRs_first
output mmioToPlatform_cRs_first;
output RDY_mmioToPlatform_cRs_first;
// action method mmioToPlatform_setTime
input [63 : 0] mmioToPlatform_setTime_t;
input EN_mmioToPlatform_setTime;
output RDY_mmioToPlatform_setTime;
// actionvalue method sendDoStats
input EN_sendDoStats;
output sendDoStats;
output RDY_sendDoStats;
// action method recvDoStats
input recvDoStats_x;
input EN_recvDoStats;
output RDY_recvDoStats;
// actionvalue method deadlock_dCacheCRqStuck_get
input EN_deadlock_dCacheCRqStuck_get;
output [72 : 0] deadlock_dCacheCRqStuck_get;
output RDY_deadlock_dCacheCRqStuck_get;
// actionvalue method deadlock_dCachePRqStuck_get
input EN_deadlock_dCachePRqStuck_get;
output [67 : 0] deadlock_dCachePRqStuck_get;
output RDY_deadlock_dCachePRqStuck_get;
// actionvalue method deadlock_iCacheCRqStuck_get
input EN_deadlock_iCacheCRqStuck_get;
output [67 : 0] deadlock_iCacheCRqStuck_get;
output RDY_deadlock_iCacheCRqStuck_get;
// actionvalue method deadlock_iCachePRqStuck_get
input EN_deadlock_iCachePRqStuck_get;
output [67 : 0] deadlock_iCachePRqStuck_get;
output RDY_deadlock_iCachePRqStuck_get;
// actionvalue method deadlock_renameInstStuck_get
input EN_deadlock_renameInstStuck_get;
output [77 : 0] deadlock_renameInstStuck_get;
output RDY_deadlock_renameInstStuck_get;
// actionvalue method deadlock_renameCorrectPathStuck_get
input EN_deadlock_renameCorrectPathStuck_get;
output [77 : 0] deadlock_renameCorrectPathStuck_get;
output RDY_deadlock_renameCorrectPathStuck_get;
// actionvalue method deadlock_commitInstStuck_get
input EN_deadlock_commitInstStuck_get;
output [162 : 0] deadlock_commitInstStuck_get;
output RDY_deadlock_commitInstStuck_get;
// actionvalue method deadlock_commitUserInstStuck_get
input EN_deadlock_commitUserInstStuck_get;
output [162 : 0] deadlock_commitUserInstStuck_get;
output RDY_deadlock_commitUserInstStuck_get;
// action method deadlock_checkStarted_get
input EN_deadlock_checkStarted_get;
output RDY_deadlock_checkStarted_get;
// actionvalue method renameDebug_renameErr_get
input EN_renameDebug_renameErr_get;
output [88 : 0] renameDebug_renameErr_get;
output RDY_renameDebug_renameErr_get;
// action method setMEIP
input setMEIP_v;
input EN_setMEIP;
output RDY_setMEIP;
// action method setSEIP
input setSEIP_v;
input EN_setSEIP;
output RDY_setSEIP;
// action method hart0_run_halt_server_request_put
input hart0_run_halt_server_request_put;
input EN_hart0_run_halt_server_request_put;
output RDY_hart0_run_halt_server_request_put;
// actionvalue method hart0_run_halt_server_response_get
input EN_hart0_run_halt_server_response_get;
output hart0_run_halt_server_response_get;
output RDY_hart0_run_halt_server_response_get;
// action method hart0_gpr_mem_server_request_put
input [69 : 0] hart0_gpr_mem_server_request_put;
input EN_hart0_gpr_mem_server_request_put;
output RDY_hart0_gpr_mem_server_request_put;
// actionvalue method hart0_gpr_mem_server_response_get
input EN_hart0_gpr_mem_server_response_get;
output [64 : 0] hart0_gpr_mem_server_response_get;
output RDY_hart0_gpr_mem_server_response_get;
// action method hart0_fpr_mem_server_request_put
input [69 : 0] hart0_fpr_mem_server_request_put;
input EN_hart0_fpr_mem_server_request_put;
output RDY_hart0_fpr_mem_server_request_put;
// actionvalue method hart0_fpr_mem_server_response_get
input EN_hart0_fpr_mem_server_response_get;
output [64 : 0] hart0_fpr_mem_server_response_get;
output RDY_hart0_fpr_mem_server_response_get;
// action method hart0_csr_mem_server_request_put
input [76 : 0] hart0_csr_mem_server_request_put;
input EN_hart0_csr_mem_server_request_put;
output RDY_hart0_csr_mem_server_request_put;
// actionvalue method hart0_csr_mem_server_response_get
input EN_hart0_csr_mem_server_response_get;
output [64 : 0] hart0_csr_mem_server_response_get;
output RDY_hart0_csr_mem_server_response_get;
// actionvalue method v_to_TV_0_get
input EN_v_to_TV_0_get;
output [319 : 0] v_to_TV_0_get;
output RDY_v_to_TV_0_get;
// actionvalue method v_to_TV_1_get
input EN_v_to_TV_1_get;
output [319 : 0] v_to_TV_1_get;
output RDY_v_to_TV_1_get;
// signals for module outputs
wire [578 : 0] dCacheToParent_rsToP_first, iCacheToParent_rsToP_first;
wire [319 : 0] v_to_TV_0_get, v_to_TV_1_get;
wire [162 : 0] deadlock_commitInstStuck_get,
deadlock_commitUserInstStuck_get;
wire [141 : 0] mmioToPlatform_cRq_first;
wire [88 : 0] renameDebug_renameErr_get;
wire [77 : 0] deadlock_renameCorrectPathStuck_get,
deadlock_renameInstStuck_get;
wire [72 : 0] coreIndInv_perfResp, deadlock_dCacheCRqStuck_get;
wire [71 : 0] dCacheToParent_rqToP_first, iCacheToParent_rqToP_first;
wire [67 : 0] deadlock_dCachePRqStuck_get,
deadlock_iCacheCRqStuck_get,
deadlock_iCachePRqStuck_get;
wire [64 : 0] hart0_csr_mem_server_response_get,
hart0_fpr_mem_server_response_get,
hart0_gpr_mem_server_response_get,
tlbToMem_memReq_first;
wire RDY_coreIndInv_perfResp,
RDY_coreIndInv_terminate,
RDY_coreReq_perfReq,
RDY_coreReq_start,
RDY_dCacheToParent_fromP_enq,
RDY_dCacheToParent_fromP_notFull,
RDY_dCacheToParent_rqToP_deq,
RDY_dCacheToParent_rqToP_first,
RDY_dCacheToParent_rqToP_notEmpty,
RDY_dCacheToParent_rsToP_deq,
RDY_dCacheToParent_rsToP_first,
RDY_dCacheToParent_rsToP_notEmpty,
RDY_deadlock_checkStarted_get,
RDY_deadlock_commitInstStuck_get,
RDY_deadlock_commitUserInstStuck_get,
RDY_deadlock_dCacheCRqStuck_get,
RDY_deadlock_dCachePRqStuck_get,
RDY_deadlock_iCacheCRqStuck_get,
RDY_deadlock_iCachePRqStuck_get,
RDY_deadlock_renameCorrectPathStuck_get,
RDY_deadlock_renameInstStuck_get,
RDY_hart0_csr_mem_server_request_put,
RDY_hart0_csr_mem_server_response_get,
RDY_hart0_fpr_mem_server_request_put,
RDY_hart0_fpr_mem_server_response_get,
RDY_hart0_gpr_mem_server_request_put,
RDY_hart0_gpr_mem_server_response_get,
RDY_hart0_run_halt_server_request_put,
RDY_hart0_run_halt_server_response_get,
RDY_iCacheToParent_fromP_enq,
RDY_iCacheToParent_fromP_notFull,
RDY_iCacheToParent_rqToP_deq,
RDY_iCacheToParent_rqToP_first,
RDY_iCacheToParent_rqToP_notEmpty,
RDY_iCacheToParent_rsToP_deq,
RDY_iCacheToParent_rsToP_first,
RDY_iCacheToParent_rsToP_notEmpty,
RDY_mmioToPlatform_cRq_deq,
RDY_mmioToPlatform_cRq_first,
RDY_mmioToPlatform_cRq_notEmpty,
RDY_mmioToPlatform_cRs_deq,
RDY_mmioToPlatform_cRs_first,
RDY_mmioToPlatform_cRs_notEmpty,
RDY_mmioToPlatform_pRq_enq,
RDY_mmioToPlatform_pRq_notFull,
RDY_mmioToPlatform_pRs_enq,
RDY_mmioToPlatform_pRs_notFull,
RDY_mmioToPlatform_setTime,
RDY_recvDoStats,
RDY_renameDebug_renameErr_get,
RDY_sendDoStats,
RDY_setMEIP,
RDY_setSEIP,
RDY_tlbToMem_memReq_deq,
RDY_tlbToMem_memReq_first,
RDY_tlbToMem_memReq_notEmpty,
RDY_tlbToMem_respLd_enq,
RDY_tlbToMem_respLd_notFull,
RDY_v_to_TV_0_get,
RDY_v_to_TV_1_get,
dCacheToParent_fromP_notFull,
dCacheToParent_rqToP_notEmpty,
dCacheToParent_rsToP_notEmpty,
hart0_run_halt_server_response_get,
iCacheToParent_fromP_notFull,
iCacheToParent_rqToP_notEmpty,
iCacheToParent_rsToP_notEmpty,
mmioToPlatform_cRq_notEmpty,
mmioToPlatform_cRs_first,
mmioToPlatform_cRs_notEmpty,
mmioToPlatform_pRq_notFull,
mmioToPlatform_pRs_notFull,
sendDoStats,
tlbToMem_memReq_notEmpty,
tlbToMem_respLd_notFull;
// inlined wires
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget;
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget;
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget;
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget;
wire [142 : 0] mmio_cRqQ_enqReq_lat_0$wget, mmio_dataReqQ_enqReq_lat_0$wget;
wire [76 : 0] coreFix_memExe_issueLd$wget;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget;
wire [70 : 0] coreFix_aluExe_0_bypassWire_0$wget,
coreFix_aluExe_0_bypassWire_1$wget,
coreFix_aluExe_0_bypassWire_2$wget,
coreFix_aluExe_0_bypassWire_3$wget;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_lat_0$wget,
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_lat_0$wget;
wire [67 : 0] mmio_pRsQ_enqReq_lat_0$wget;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_lat_0$wget,
mmio_dataRespQ_enqReq_lat_0$wget;
wire [39 : 0] mmio_pRqQ_enqReq_lat_0$wget;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget;
wire [1 : 0] mmio_cRsQ_enqReq_lat_0$wget;
wire coreFix_aluExe_0_bypassWire_0$whas,
coreFix_aluExe_0_bypassWire_1$whas,
coreFix_aluExe_0_bypassWire_2$whas,
coreFix_aluExe_0_bypassWire_3$whas,
coreFix_aluExe_1_bypassWire_2$whas,
coreFix_aluExe_1_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_bypassWire_2$whas,
coreFix_fpuMulDivExe_0_bypassWire_3$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_globalSpecUpdate_correctSpecTag_0$whas,
coreFix_globalSpecUpdate_correctSpecTag_1$whas,
coreFix_memExe_bypassWire_2$whas,
coreFix_memExe_bypassWire_3$whas,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas,
coreFix_memExe_forwardQ_enqReq_lat_0$whas,
coreFix_memExe_issueLd$whas,
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas,
coreFix_memExe_reqLdQ_data_0_lat_0$whas,
coreFix_memExe_reqLdQ_empty_lat_0$whas,
coreFix_memExe_reqLdQ_full_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas,
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas,
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas,
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas,
csrInstOrInterruptInflight_lat_1$whas,
csrf_mcycle_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_dummy_1_0$whas,
csrf_minstret_ehr_data_lat_0$whas,
csrf_minstret_ehr_data_lat_1$whas,
mmio_cRqQ_enqReq_lat_0$whas,
mmio_dataPendQ_enqReq_lat_0$whas,
mmio_dataReqQ_enqReq_lat_0$whas,
mmio_dataRespQ_deqReq_lat_0$whas,
mmio_pRsQ_deqReq_lat_0$whas;
// register commitStage_commitTrap
reg [133 : 0] commitStage_commitTrap;
wire [133 : 0] commitStage_commitTrap$D_IN;
wire commitStage_commitTrap$EN;
// register commitStage_rg_run_state
reg commitStage_rg_run_state;
wire commitStage_rg_run_state$D_IN, commitStage_rg_run_state$EN;
// register commitStage_rg_serialnum
reg [63 : 0] commitStage_rg_serialnum;
wire [63 : 0] commitStage_rg_serialnum$D_IN;
wire commitStage_rg_serialnum$EN;
// register coreFix_doStatsReg
reg coreFix_doStatsReg;
wire coreFix_doStatsReg$D_IN, coreFix_doStatsReg$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt;
wire [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
reg coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
reg [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit;
wire [1 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
reg [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1;
wire [2 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
reg [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1;
wire [582 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl;
wire [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
reg [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl;
wire [58 : 0] coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo;
reg [160 : 0] coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
reg [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
reg [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1;
wire [71 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
reg [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl;
wire [72 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
reg [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
reg [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl;
wire [579 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
reg coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
reg coreFix_memExe_dMem_perfReqQ_clearReq_rl;
wire coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_data_0
reg [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0;
wire [3 : 0] coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
wire coreFix_memExe_dMem_perfReqQ_data_0$EN;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
reg coreFix_memExe_dMem_perfReqQ_deqReq_rl;
wire coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_empty
reg coreFix_memExe_dMem_perfReqQ_empty;
wire coreFix_memExe_dMem_perfReqQ_empty$D_IN,
coreFix_memExe_dMem_perfReqQ_empty$EN;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
reg [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl;
wire [4 : 0] coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
wire coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN;
// register coreFix_memExe_dMem_perfReqQ_full
reg coreFix_memExe_dMem_perfReqQ_full;
wire coreFix_memExe_dMem_perfReqQ_full$D_IN,
coreFix_memExe_dMem_perfReqQ_full$EN;
// register coreFix_memExe_forwardQ_clearReq_rl
reg coreFix_memExe_forwardQ_clearReq_rl;
wire coreFix_memExe_forwardQ_clearReq_rl$D_IN,
coreFix_memExe_forwardQ_clearReq_rl$EN;
// register coreFix_memExe_forwardQ_data_0
reg [68 : 0] coreFix_memExe_forwardQ_data_0;
wire [68 : 0] coreFix_memExe_forwardQ_data_0$D_IN;
wire coreFix_memExe_forwardQ_data_0$EN;
// register coreFix_memExe_forwardQ_data_1
reg [68 : 0] coreFix_memExe_forwardQ_data_1;
wire [68 : 0] coreFix_memExe_forwardQ_data_1$D_IN;
wire coreFix_memExe_forwardQ_data_1$EN;
// register coreFix_memExe_forwardQ_deqP
reg coreFix_memExe_forwardQ_deqP;
wire coreFix_memExe_forwardQ_deqP$D_IN, coreFix_memExe_forwardQ_deqP$EN;
// register coreFix_memExe_forwardQ_deqReq_rl
reg coreFix_memExe_forwardQ_deqReq_rl;
wire coreFix_memExe_forwardQ_deqReq_rl$D_IN,
coreFix_memExe_forwardQ_deqReq_rl$EN;
// register coreFix_memExe_forwardQ_empty
reg coreFix_memExe_forwardQ_empty;
wire coreFix_memExe_forwardQ_empty$D_IN, coreFix_memExe_forwardQ_empty$EN;
// register coreFix_memExe_forwardQ_enqP
reg coreFix_memExe_forwardQ_enqP;
wire coreFix_memExe_forwardQ_enqP$D_IN, coreFix_memExe_forwardQ_enqP$EN;
// register coreFix_memExe_forwardQ_enqReq_rl
reg [69 : 0] coreFix_memExe_forwardQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_forwardQ_enqReq_rl$D_IN;
wire coreFix_memExe_forwardQ_enqReq_rl$EN;
// register coreFix_memExe_forwardQ_full
reg coreFix_memExe_forwardQ_full;
wire coreFix_memExe_forwardQ_full$D_IN, coreFix_memExe_forwardQ_full$EN;
// register coreFix_memExe_memRespLdQ_clearReq_rl
reg coreFix_memExe_memRespLdQ_clearReq_rl;
wire coreFix_memExe_memRespLdQ_clearReq_rl$D_IN,
coreFix_memExe_memRespLdQ_clearReq_rl$EN;
// register coreFix_memExe_memRespLdQ_data_0
reg [68 : 0] coreFix_memExe_memRespLdQ_data_0;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_0$D_IN;
wire coreFix_memExe_memRespLdQ_data_0$EN;
// register coreFix_memExe_memRespLdQ_data_1
reg [68 : 0] coreFix_memExe_memRespLdQ_data_1;
wire [68 : 0] coreFix_memExe_memRespLdQ_data_1$D_IN;
wire coreFix_memExe_memRespLdQ_data_1$EN;
// register coreFix_memExe_memRespLdQ_deqP
reg coreFix_memExe_memRespLdQ_deqP;
wire coreFix_memExe_memRespLdQ_deqP$D_IN, coreFix_memExe_memRespLdQ_deqP$EN;
// register coreFix_memExe_memRespLdQ_deqReq_rl
reg coreFix_memExe_memRespLdQ_deqReq_rl;
wire coreFix_memExe_memRespLdQ_deqReq_rl$D_IN,
coreFix_memExe_memRespLdQ_deqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_empty
reg coreFix_memExe_memRespLdQ_empty;
wire coreFix_memExe_memRespLdQ_empty$D_IN,
coreFix_memExe_memRespLdQ_empty$EN;
// register coreFix_memExe_memRespLdQ_enqP
reg coreFix_memExe_memRespLdQ_enqP;
wire coreFix_memExe_memRespLdQ_enqP$D_IN, coreFix_memExe_memRespLdQ_enqP$EN;
// register coreFix_memExe_memRespLdQ_enqReq_rl
reg [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl;
wire [69 : 0] coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
wire coreFix_memExe_memRespLdQ_enqReq_rl$EN;
// register coreFix_memExe_memRespLdQ_full
reg coreFix_memExe_memRespLdQ_full;
wire coreFix_memExe_memRespLdQ_full$D_IN, coreFix_memExe_memRespLdQ_full$EN;
// register coreFix_memExe_reqLdQ_data_0_rl
reg [68 : 0] coreFix_memExe_reqLdQ_data_0_rl;
wire [68 : 0] coreFix_memExe_reqLdQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLdQ_data_0_rl$EN;
// register coreFix_memExe_reqLdQ_empty_rl
reg coreFix_memExe_reqLdQ_empty_rl;
wire coreFix_memExe_reqLdQ_empty_rl$D_IN, coreFix_memExe_reqLdQ_empty_rl$EN;
// register coreFix_memExe_reqLdQ_full_rl
reg coreFix_memExe_reqLdQ_full_rl;
wire coreFix_memExe_reqLdQ_full_rl$D_IN, coreFix_memExe_reqLdQ_full_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
reg [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl;
wire [152 : 0] coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
wire coreFix_memExe_reqLrScAmoQ_data_0_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
reg coreFix_memExe_reqLrScAmoQ_empty_rl;
wire coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_rl$EN;
// register coreFix_memExe_reqLrScAmoQ_full_rl
reg coreFix_memExe_reqLrScAmoQ_full_rl;
wire coreFix_memExe_reqLrScAmoQ_full_rl$D_IN,
coreFix_memExe_reqLrScAmoQ_full_rl$EN;
// register coreFix_memExe_reqStQ_data_0_rl
reg [65 : 0] coreFix_memExe_reqStQ_data_0_rl;
wire [65 : 0] coreFix_memExe_reqStQ_data_0_rl$D_IN;
wire coreFix_memExe_reqStQ_data_0_rl$EN;
// register coreFix_memExe_reqStQ_empty_rl
reg coreFix_memExe_reqStQ_empty_rl;
wire coreFix_memExe_reqStQ_empty_rl$D_IN, coreFix_memExe_reqStQ_empty_rl$EN;
// register coreFix_memExe_reqStQ_full_rl
reg coreFix_memExe_reqStQ_full_rl;
wire coreFix_memExe_reqStQ_full_rl$D_IN, coreFix_memExe_reqStQ_full_rl$EN;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
reg coreFix_memExe_respLrScAmoQ_clearReq_rl;
wire coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_data_0
reg [63 : 0] coreFix_memExe_respLrScAmoQ_data_0;
wire [63 : 0] coreFix_memExe_respLrScAmoQ_data_0$D_IN;
wire coreFix_memExe_respLrScAmoQ_data_0$EN;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
reg coreFix_memExe_respLrScAmoQ_deqReq_rl;
wire coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_empty
reg coreFix_memExe_respLrScAmoQ_empty;
wire coreFix_memExe_respLrScAmoQ_empty$D_IN,
coreFix_memExe_respLrScAmoQ_empty$EN;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
reg [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl;
wire [64 : 0] coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
wire coreFix_memExe_respLrScAmoQ_enqReq_rl$EN;
// register coreFix_memExe_respLrScAmoQ_full
reg coreFix_memExe_respLrScAmoQ_full;
wire coreFix_memExe_respLrScAmoQ_full$D_IN,
coreFix_memExe_respLrScAmoQ_full$EN;
// register coreFix_memExe_waitLrScAmoMMIOResp
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp;
reg [2 : 0] coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
wire coreFix_memExe_waitLrScAmoMMIOResp$EN;
// register csrInstOrInterruptInflight_rl
reg csrInstOrInterruptInflight_rl;
wire csrInstOrInterruptInflight_rl$D_IN, csrInstOrInterruptInflight_rl$EN;
// register csrf_external_int_en_vec_0
reg csrf_external_int_en_vec_0;
wire csrf_external_int_en_vec_0$D_IN, csrf_external_int_en_vec_0$EN;
// register csrf_external_int_en_vec_1
reg csrf_external_int_en_vec_1;
wire csrf_external_int_en_vec_1$D_IN, csrf_external_int_en_vec_1$EN;
// register csrf_external_int_en_vec_3
reg csrf_external_int_en_vec_3;
wire csrf_external_int_en_vec_3$D_IN, csrf_external_int_en_vec_3$EN;
// register csrf_external_int_pend_vec_0
reg csrf_external_int_pend_vec_0;
wire csrf_external_int_pend_vec_0$D_IN, csrf_external_int_pend_vec_0$EN;
// register csrf_external_int_pend_vec_1
reg csrf_external_int_pend_vec_1;
reg csrf_external_int_pend_vec_1$D_IN;
wire csrf_external_int_pend_vec_1$EN;
// register csrf_external_int_pend_vec_3
reg csrf_external_int_pend_vec_3;
reg csrf_external_int_pend_vec_3$D_IN;
wire csrf_external_int_pend_vec_3$EN;
// register csrf_fflags_reg
reg [4 : 0] csrf_fflags_reg;
reg [4 : 0] csrf_fflags_reg$D_IN;
wire csrf_fflags_reg$EN;
// register csrf_frm_reg
reg [2 : 0] csrf_frm_reg;
wire [2 : 0] csrf_frm_reg$D_IN;
wire csrf_frm_reg$EN;
// register csrf_fs_reg
reg [1 : 0] csrf_fs_reg;
reg [1 : 0] csrf_fs_reg$D_IN;
wire csrf_fs_reg$EN;
// register csrf_ie_vec_0
reg csrf_ie_vec_0;
wire csrf_ie_vec_0$D_IN, csrf_ie_vec_0$EN;
// register csrf_ie_vec_1
reg csrf_ie_vec_1;
reg csrf_ie_vec_1$D_IN;
wire csrf_ie_vec_1$EN;
// register csrf_ie_vec_3
reg csrf_ie_vec_3;
reg csrf_ie_vec_3$D_IN;
wire csrf_ie_vec_3$EN;
// register csrf_mcause_code_reg
reg [3 : 0] csrf_mcause_code_reg;
reg [3 : 0] csrf_mcause_code_reg$D_IN;
wire csrf_mcause_code_reg$EN;
// register csrf_mcause_interrupt_reg
reg csrf_mcause_interrupt_reg;
reg csrf_mcause_interrupt_reg$D_IN;
wire csrf_mcause_interrupt_reg$EN;
// register csrf_mcounteren_cy_reg
reg csrf_mcounteren_cy_reg;
wire csrf_mcounteren_cy_reg$D_IN, csrf_mcounteren_cy_reg$EN;
// register csrf_mcounteren_ir_reg
reg csrf_mcounteren_ir_reg;
wire csrf_mcounteren_ir_reg$D_IN, csrf_mcounteren_ir_reg$EN;
// register csrf_mcounteren_tm_reg
reg csrf_mcounteren_tm_reg;
wire csrf_mcounteren_tm_reg$D_IN, csrf_mcounteren_tm_reg$EN;
// register csrf_mcycle_ehr_data_rl
reg [63 : 0] csrf_mcycle_ehr_data_rl;
wire [63 : 0] csrf_mcycle_ehr_data_rl$D_IN;
wire csrf_mcycle_ehr_data_rl$EN;
// register csrf_medeleg_13_11_reg
reg [2 : 0] csrf_medeleg_13_11_reg;
wire [2 : 0] csrf_medeleg_13_11_reg$D_IN;
wire csrf_medeleg_13_11_reg$EN;
// register csrf_medeleg_15_reg
reg csrf_medeleg_15_reg;
wire csrf_medeleg_15_reg$D_IN, csrf_medeleg_15_reg$EN;
// register csrf_medeleg_9_0_reg
reg [9 : 0] csrf_medeleg_9_0_reg;
wire [9 : 0] csrf_medeleg_9_0_reg$D_IN;
wire csrf_medeleg_9_0_reg$EN;
// register csrf_mepc_csr
reg [63 : 0] csrf_mepc_csr;
reg [63 : 0] csrf_mepc_csr$D_IN;
wire csrf_mepc_csr$EN;
// register csrf_mideleg_11_reg
reg csrf_mideleg_11_reg;
wire csrf_mideleg_11_reg$D_IN, csrf_mideleg_11_reg$EN;
// register csrf_mideleg_1_0_reg
reg [1 : 0] csrf_mideleg_1_0_reg;
wire [1 : 0] csrf_mideleg_1_0_reg$D_IN;
wire csrf_mideleg_1_0_reg$EN;
// register csrf_mideleg_5_3_reg
reg [2 : 0] csrf_mideleg_5_3_reg;
wire [2 : 0] csrf_mideleg_5_3_reg$D_IN;
wire csrf_mideleg_5_3_reg$EN;
// register csrf_mideleg_9_7_reg
reg [2 : 0] csrf_mideleg_9_7_reg;
wire [2 : 0] csrf_mideleg_9_7_reg$D_IN;
wire csrf_mideleg_9_7_reg$EN;
// register csrf_minstret_ehr_data_rl
reg [63 : 0] csrf_minstret_ehr_data_rl;
wire [63 : 0] csrf_minstret_ehr_data_rl$D_IN;
wire csrf_minstret_ehr_data_rl$EN;
// register csrf_mpp_reg
reg [1 : 0] csrf_mpp_reg;
reg [1 : 0] csrf_mpp_reg$D_IN;
wire csrf_mpp_reg$EN;
// register csrf_mprv_reg
reg csrf_mprv_reg;
wire csrf_mprv_reg$D_IN, csrf_mprv_reg$EN;
// register csrf_mscratch_csr
reg [63 : 0] csrf_mscratch_csr;
wire [63 : 0] csrf_mscratch_csr$D_IN;
wire csrf_mscratch_csr$EN;
// register csrf_mtval_csr
reg [63 : 0] csrf_mtval_csr;
reg [63 : 0] csrf_mtval_csr$D_IN;
wire csrf_mtval_csr$EN;
// register csrf_mtvec_base_hi_reg
reg [61 : 0] csrf_mtvec_base_hi_reg;
wire [61 : 0] csrf_mtvec_base_hi_reg$D_IN;
wire csrf_mtvec_base_hi_reg$EN;
// register csrf_mtvec_mode_low_reg
reg csrf_mtvec_mode_low_reg;
wire csrf_mtvec_mode_low_reg$D_IN, csrf_mtvec_mode_low_reg$EN;
// register csrf_mxr_reg
reg csrf_mxr_reg;
wire csrf_mxr_reg$D_IN, csrf_mxr_reg$EN;
// register csrf_ppn_reg
reg [43 : 0] csrf_ppn_reg;
wire [43 : 0] csrf_ppn_reg$D_IN;
wire csrf_ppn_reg$EN;
// register csrf_prev_ie_vec_0
reg csrf_prev_ie_vec_0;
wire csrf_prev_ie_vec_0$D_IN, csrf_prev_ie_vec_0$EN;
// register csrf_prev_ie_vec_1
reg csrf_prev_ie_vec_1;
reg csrf_prev_ie_vec_1$D_IN;
wire csrf_prev_ie_vec_1$EN;
// register csrf_prev_ie_vec_3
reg csrf_prev_ie_vec_3;
reg csrf_prev_ie_vec_3$D_IN;
wire csrf_prev_ie_vec_3$EN;
// register csrf_prv_reg
reg [1 : 0] csrf_prv_reg;
reg [1 : 0] csrf_prv_reg$D_IN;
wire csrf_prv_reg$EN;
// register csrf_rg_dcsr
reg [63 : 0] csrf_rg_dcsr;
reg [63 : 0] csrf_rg_dcsr$D_IN;
wire csrf_rg_dcsr$EN;
// register csrf_rg_dpc
reg [63 : 0] csrf_rg_dpc;
reg [63 : 0] csrf_rg_dpc$D_IN;
wire csrf_rg_dpc$EN;
// register csrf_rg_dscratch0
reg [63 : 0] csrf_rg_dscratch0;
wire [63 : 0] csrf_rg_dscratch0$D_IN;
wire csrf_rg_dscratch0$EN;
// register csrf_rg_dscratch1
reg [63 : 0] csrf_rg_dscratch1;
wire [63 : 0] csrf_rg_dscratch1$D_IN;
wire csrf_rg_dscratch1$EN;
// register csrf_scause_code_reg
reg [3 : 0] csrf_scause_code_reg;
reg [3 : 0] csrf_scause_code_reg$D_IN;
wire csrf_scause_code_reg$EN;
// register csrf_scause_interrupt_reg
reg csrf_scause_interrupt_reg;
reg csrf_scause_interrupt_reg$D_IN;
wire csrf_scause_interrupt_reg$EN;
// register csrf_scounteren_cy_reg
reg csrf_scounteren_cy_reg;
wire csrf_scounteren_cy_reg$D_IN, csrf_scounteren_cy_reg$EN;
// register csrf_scounteren_ir_reg
reg csrf_scounteren_ir_reg;
wire csrf_scounteren_ir_reg$D_IN, csrf_scounteren_ir_reg$EN;
// register csrf_scounteren_tm_reg
reg csrf_scounteren_tm_reg;
wire csrf_scounteren_tm_reg$D_IN, csrf_scounteren_tm_reg$EN;
// register csrf_sepc_csr
reg [63 : 0] csrf_sepc_csr;
reg [63 : 0] csrf_sepc_csr$D_IN;
wire csrf_sepc_csr$EN;
// register csrf_software_int_en_vec_0
reg csrf_software_int_en_vec_0;
wire csrf_software_int_en_vec_0$D_IN, csrf_software_int_en_vec_0$EN;
// register csrf_software_int_en_vec_1
reg csrf_software_int_en_vec_1;
wire csrf_software_int_en_vec_1$D_IN, csrf_software_int_en_vec_1$EN;
// register csrf_software_int_en_vec_3
reg csrf_software_int_en_vec_3;
wire csrf_software_int_en_vec_3$D_IN, csrf_software_int_en_vec_3$EN;
// register csrf_software_int_pend_vec_0
reg csrf_software_int_pend_vec_0;
wire csrf_software_int_pend_vec_0$D_IN, csrf_software_int_pend_vec_0$EN;
// register csrf_software_int_pend_vec_1
reg csrf_software_int_pend_vec_1;
wire csrf_software_int_pend_vec_1$D_IN, csrf_software_int_pend_vec_1$EN;
// register csrf_software_int_pend_vec_3
reg csrf_software_int_pend_vec_3;
reg csrf_software_int_pend_vec_3$D_IN;
wire csrf_software_int_pend_vec_3$EN;
// register csrf_spp_reg
reg csrf_spp_reg;
reg csrf_spp_reg$D_IN;
wire csrf_spp_reg$EN;
// register csrf_sscratch_csr
reg [63 : 0] csrf_sscratch_csr;
wire [63 : 0] csrf_sscratch_csr$D_IN;
wire csrf_sscratch_csr$EN;
// register csrf_stats_module_doStats
reg csrf_stats_module_doStats;
wire csrf_stats_module_doStats$D_IN, csrf_stats_module_doStats$EN;
// register csrf_stval_csr
reg [63 : 0] csrf_stval_csr;
reg [63 : 0] csrf_stval_csr$D_IN;
wire csrf_stval_csr$EN;
// register csrf_stvec_base_hi_reg
reg [61 : 0] csrf_stvec_base_hi_reg;
wire [61 : 0] csrf_stvec_base_hi_reg$D_IN;
wire csrf_stvec_base_hi_reg$EN;
// register csrf_stvec_mode_low_reg
reg csrf_stvec_mode_low_reg;
wire csrf_stvec_mode_low_reg$D_IN, csrf_stvec_mode_low_reg$EN;
// register csrf_sum_reg
reg csrf_sum_reg;
wire csrf_sum_reg$D_IN, csrf_sum_reg$EN;
// register csrf_time_reg
reg [63 : 0] csrf_time_reg;
wire [63 : 0] csrf_time_reg$D_IN;
wire csrf_time_reg$EN;
// register csrf_timer_int_en_vec_0
reg csrf_timer_int_en_vec_0;
wire csrf_timer_int_en_vec_0$D_IN, csrf_timer_int_en_vec_0$EN;
// register csrf_timer_int_en_vec_1
reg csrf_timer_int_en_vec_1;
wire csrf_timer_int_en_vec_1$D_IN, csrf_timer_int_en_vec_1$EN;
// register csrf_timer_int_en_vec_3
reg csrf_timer_int_en_vec_3;
wire csrf_timer_int_en_vec_3$D_IN, csrf_timer_int_en_vec_3$EN;
// register csrf_timer_int_pend_vec_0
reg csrf_timer_int_pend_vec_0;
wire csrf_timer_int_pend_vec_0$D_IN, csrf_timer_int_pend_vec_0$EN;
// register csrf_timer_int_pend_vec_1
reg csrf_timer_int_pend_vec_1;
wire csrf_timer_int_pend_vec_1$D_IN, csrf_timer_int_pend_vec_1$EN;
// register csrf_timer_int_pend_vec_3
reg csrf_timer_int_pend_vec_3;
wire csrf_timer_int_pend_vec_3$D_IN, csrf_timer_int_pend_vec_3$EN;
// register csrf_tsr_reg
reg csrf_tsr_reg;
wire csrf_tsr_reg$D_IN, csrf_tsr_reg$EN;
// register csrf_tvm_reg
reg csrf_tvm_reg;
wire csrf_tvm_reg$D_IN, csrf_tvm_reg$EN;
// register csrf_tw_reg
reg csrf_tw_reg;
wire csrf_tw_reg$D_IN, csrf_tw_reg$EN;
// register csrf_vm_mode_sv39_reg
reg csrf_vm_mode_sv39_reg;
wire csrf_vm_mode_sv39_reg$D_IN, csrf_vm_mode_sv39_reg$EN;
// register flush_brpred
reg flush_brpred;
wire flush_brpred$D_IN, flush_brpred$EN;
// register flush_caches
reg flush_caches;
wire flush_caches$D_IN, flush_caches$EN;
// register flush_reservation
reg flush_reservation;
wire flush_reservation$D_IN, flush_reservation$EN;
// register flush_tlbs
reg flush_tlbs;
wire flush_tlbs$D_IN, flush_tlbs$EN;
// register mmio_cRqQ_clearReq_rl
reg mmio_cRqQ_clearReq_rl;
wire mmio_cRqQ_clearReq_rl$D_IN, mmio_cRqQ_clearReq_rl$EN;
// register mmio_cRqQ_data_0
reg [141 : 0] mmio_cRqQ_data_0;
wire [141 : 0] mmio_cRqQ_data_0$D_IN;
wire mmio_cRqQ_data_0$EN;
// register mmio_cRqQ_deqReq_rl
reg mmio_cRqQ_deqReq_rl;
wire mmio_cRqQ_deqReq_rl$D_IN, mmio_cRqQ_deqReq_rl$EN;
// register mmio_cRqQ_empty
reg mmio_cRqQ_empty;
wire mmio_cRqQ_empty$D_IN, mmio_cRqQ_empty$EN;
// register mmio_cRqQ_enqReq_rl
reg [142 : 0] mmio_cRqQ_enqReq_rl;
wire [142 : 0] mmio_cRqQ_enqReq_rl$D_IN;
wire mmio_cRqQ_enqReq_rl$EN;
// register mmio_cRqQ_full
reg mmio_cRqQ_full;
wire mmio_cRqQ_full$D_IN, mmio_cRqQ_full$EN;
// register mmio_cRsQ_clearReq_rl
reg mmio_cRsQ_clearReq_rl;
wire mmio_cRsQ_clearReq_rl$D_IN, mmio_cRsQ_clearReq_rl$EN;
// register mmio_cRsQ_data_0
reg mmio_cRsQ_data_0;
wire mmio_cRsQ_data_0$D_IN, mmio_cRsQ_data_0$EN;
// register mmio_cRsQ_deqReq_rl
reg mmio_cRsQ_deqReq_rl;
wire mmio_cRsQ_deqReq_rl$D_IN, mmio_cRsQ_deqReq_rl$EN;
// register mmio_cRsQ_empty
reg mmio_cRsQ_empty;
wire mmio_cRsQ_empty$D_IN, mmio_cRsQ_empty$EN;
// register mmio_cRsQ_enqReq_rl
reg [1 : 0] mmio_cRsQ_enqReq_rl;
wire [1 : 0] mmio_cRsQ_enqReq_rl$D_IN;
wire mmio_cRsQ_enqReq_rl$EN;
// register mmio_cRsQ_full
reg mmio_cRsQ_full;
wire mmio_cRsQ_full$D_IN, mmio_cRsQ_full$EN;
// register mmio_dataPendQ_clearReq_rl
reg mmio_dataPendQ_clearReq_rl;
wire mmio_dataPendQ_clearReq_rl$D_IN, mmio_dataPendQ_clearReq_rl$EN;
// register mmio_dataPendQ_deqReq_rl
reg mmio_dataPendQ_deqReq_rl;
wire mmio_dataPendQ_deqReq_rl$D_IN, mmio_dataPendQ_deqReq_rl$EN;
// register mmio_dataPendQ_empty
reg mmio_dataPendQ_empty;
wire mmio_dataPendQ_empty$D_IN, mmio_dataPendQ_empty$EN;
// register mmio_dataPendQ_enqReq_rl
reg mmio_dataPendQ_enqReq_rl;
wire mmio_dataPendQ_enqReq_rl$D_IN, mmio_dataPendQ_enqReq_rl$EN;
// register mmio_dataPendQ_full
reg mmio_dataPendQ_full;
wire mmio_dataPendQ_full$D_IN, mmio_dataPendQ_full$EN;
// register mmio_dataReqQ_clearReq_rl
reg mmio_dataReqQ_clearReq_rl;
wire mmio_dataReqQ_clearReq_rl$D_IN, mmio_dataReqQ_clearReq_rl$EN;
// register mmio_dataReqQ_data_0
reg [141 : 0] mmio_dataReqQ_data_0;
wire [141 : 0] mmio_dataReqQ_data_0$D_IN;
wire mmio_dataReqQ_data_0$EN;
// register mmio_dataReqQ_deqReq_rl
reg mmio_dataReqQ_deqReq_rl;
wire mmio_dataReqQ_deqReq_rl$D_IN, mmio_dataReqQ_deqReq_rl$EN;
// register mmio_dataReqQ_empty
reg mmio_dataReqQ_empty;
wire mmio_dataReqQ_empty$D_IN, mmio_dataReqQ_empty$EN;
// register mmio_dataReqQ_enqReq_rl
reg [142 : 0] mmio_dataReqQ_enqReq_rl;
wire [142 : 0] mmio_dataReqQ_enqReq_rl$D_IN;
wire mmio_dataReqQ_enqReq_rl$EN;
// register mmio_dataReqQ_full
reg mmio_dataReqQ_full;
wire mmio_dataReqQ_full$D_IN, mmio_dataReqQ_full$EN;
// register mmio_dataRespQ_clearReq_rl
reg mmio_dataRespQ_clearReq_rl;
wire mmio_dataRespQ_clearReq_rl$D_IN, mmio_dataRespQ_clearReq_rl$EN;
// register mmio_dataRespQ_data_0
reg [64 : 0] mmio_dataRespQ_data_0;
wire [64 : 0] mmio_dataRespQ_data_0$D_IN;
wire mmio_dataRespQ_data_0$EN;
// register mmio_dataRespQ_deqReq_rl
reg mmio_dataRespQ_deqReq_rl;
wire mmio_dataRespQ_deqReq_rl$D_IN, mmio_dataRespQ_deqReq_rl$EN;
// register mmio_dataRespQ_empty
reg mmio_dataRespQ_empty;
wire mmio_dataRespQ_empty$D_IN, mmio_dataRespQ_empty$EN;
// register mmio_dataRespQ_enqReq_rl
reg [65 : 0] mmio_dataRespQ_enqReq_rl;
wire [65 : 0] mmio_dataRespQ_enqReq_rl$D_IN;
wire mmio_dataRespQ_enqReq_rl$EN;
// register mmio_dataRespQ_full
reg mmio_dataRespQ_full;
wire mmio_dataRespQ_full$D_IN, mmio_dataRespQ_full$EN;
// register mmio_fromHostAddr
reg [60 : 0] mmio_fromHostAddr;
wire [60 : 0] mmio_fromHostAddr$D_IN;
wire mmio_fromHostAddr$EN;
// register mmio_pRqQ_clearReq_rl
reg mmio_pRqQ_clearReq_rl;
wire mmio_pRqQ_clearReq_rl$D_IN, mmio_pRqQ_clearReq_rl$EN;
// register mmio_pRqQ_data_0
reg [38 : 0] mmio_pRqQ_data_0;
wire [38 : 0] mmio_pRqQ_data_0$D_IN;
wire mmio_pRqQ_data_0$EN;
// register mmio_pRqQ_deqReq_rl
reg mmio_pRqQ_deqReq_rl;
wire mmio_pRqQ_deqReq_rl$D_IN, mmio_pRqQ_deqReq_rl$EN;
// register mmio_pRqQ_empty
reg mmio_pRqQ_empty;
wire mmio_pRqQ_empty$D_IN, mmio_pRqQ_empty$EN;
// register mmio_pRqQ_enqReq_rl
reg [39 : 0] mmio_pRqQ_enqReq_rl;
wire [39 : 0] mmio_pRqQ_enqReq_rl$D_IN;
wire mmio_pRqQ_enqReq_rl$EN;
// register mmio_pRqQ_full
reg mmio_pRqQ_full;
wire mmio_pRqQ_full$D_IN, mmio_pRqQ_full$EN;
// register mmio_pRsQ_clearReq_rl
reg mmio_pRsQ_clearReq_rl;
wire mmio_pRsQ_clearReq_rl$D_IN, mmio_pRsQ_clearReq_rl$EN;
// register mmio_pRsQ_data_0
reg [66 : 0] mmio_pRsQ_data_0;
wire [66 : 0] mmio_pRsQ_data_0$D_IN;
wire mmio_pRsQ_data_0$EN;
// register mmio_pRsQ_deqReq_rl
reg mmio_pRsQ_deqReq_rl;
wire mmio_pRsQ_deqReq_rl$D_IN, mmio_pRsQ_deqReq_rl$EN;
// register mmio_pRsQ_empty
reg mmio_pRsQ_empty;
wire mmio_pRsQ_empty$D_IN, mmio_pRsQ_empty$EN;
// register mmio_pRsQ_enqReq_rl
reg [67 : 0] mmio_pRsQ_enqReq_rl;
wire [67 : 0] mmio_pRsQ_enqReq_rl$D_IN;
wire mmio_pRsQ_enqReq_rl$EN;
// register mmio_pRsQ_full
reg mmio_pRsQ_full;
wire mmio_pRsQ_full$D_IN, mmio_pRsQ_full$EN;
// register mmio_toHostAddr
reg [60 : 0] mmio_toHostAddr;
wire [60 : 0] mmio_toHostAddr$D_IN;
wire mmio_toHostAddr$EN;
// register outOfReset
reg outOfReset;
wire outOfReset$D_IN, outOfReset$EN;
// register renameStage_rg_m_halt_req
reg [4 : 0] renameStage_rg_m_halt_req;
reg [4 : 0] renameStage_rg_m_halt_req$D_IN;
wire renameStage_rg_m_halt_req$EN;
// register rg_core_run_state
reg [1 : 0] rg_core_run_state;
reg [1 : 0] rg_core_run_state$D_IN;
wire rg_core_run_state$EN;
// register started
reg started;
wire started$D_IN, started$EN;
// register update_vm_info
reg update_vm_info;
wire update_vm_info$D_IN, update_vm_info$EN;
// ports of submodule coreFix_aluExe_0_dispToRegQ
reg [3 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_0_dispToRegQ$enq_x,
coreFix_aluExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_dispToRegQ$EN_deq,
coreFix_aluExe_0_dispToRegQ$EN_enq,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_dispToRegQ$RDY_deq,
coreFix_aluExe_0_dispToRegQ$RDY_enq,
coreFix_aluExe_0_dispToRegQ$RDY_first,
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_exeToFinQ
reg [3 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [326 : 0] coreFix_aluExe_0_exeToFinQ$enq_x,
coreFix_aluExe_0_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_exeToFinQ$EN_deq,
coreFix_aluExe_0_exeToFinQ$EN_enq,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_exeToFinQ$RDY_deq,
coreFix_aluExe_0_exeToFinQ$RDY_enq,
coreFix_aluExe_0_exeToFinQ$RDY_first,
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_regToExeQ
reg [3 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_0_regToExeQ$enq_x,
coreFix_aluExe_0_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_0_regToExeQ$EN_deq,
coreFix_aluExe_0_regToExeQ$EN_enq,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_regToExeQ$RDY_deq,
coreFix_aluExe_0_regToExeQ$RDY_enq,
coreFix_aluExe_0_regToExeQ$RDY_first,
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_0_rsAlu
reg [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_2_put,
coreFix_aluExe_0_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_0_rsAlu$dispatchData,
coreFix_aluExe_0_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_0_rsAlu$setRegReady_0_put,
coreFix_aluExe_0_rsAlu$setRegReady_1_put,
coreFix_aluExe_0_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_0_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_0_rsAlu$approximateCount;
wire coreFix_aluExe_0_rsAlu$EN_doDispatch,
coreFix_aluExe_0_rsAlu$EN_enq,
coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_0_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_0_rsAlu$RDY_dispatchData,
coreFix_aluExe_0_rsAlu$RDY_doDispatch,
coreFix_aluExe_0_rsAlu$RDY_enq,
coreFix_aluExe_0_rsAlu$canEnq,
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_dispToRegQ
reg [3 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [157 : 0] coreFix_aluExe_1_dispToRegQ$enq_x,
coreFix_aluExe_1_dispToRegQ$first;
wire [11 : 0] coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_dispToRegQ$EN_deq,
coreFix_aluExe_1_dispToRegQ$EN_enq,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_dispToRegQ$RDY_deq,
coreFix_aluExe_1_dispToRegQ$RDY_enq,
coreFix_aluExe_1_dispToRegQ$RDY_first,
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_exeToFinQ
reg [3 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag;
wire [326 : 0] coreFix_aluExe_1_exeToFinQ$enq_x,
coreFix_aluExe_1_exeToFinQ$first;
wire [11 : 0] coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_exeToFinQ$EN_deq,
coreFix_aluExe_1_exeToFinQ$EN_enq,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_exeToFinQ$RDY_deq,
coreFix_aluExe_1_exeToFinQ$RDY_enq,
coreFix_aluExe_1_exeToFinQ$RDY_first,
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_regToExeQ
reg [3 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [421 : 0] coreFix_aluExe_1_regToExeQ$enq_x,
coreFix_aluExe_1_regToExeQ$first;
wire [11 : 0] coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_aluExe_1_regToExeQ$EN_deq,
coreFix_aluExe_1_regToExeQ$EN_enq,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_regToExeQ$RDY_deq,
coreFix_aluExe_1_regToExeQ$RDY_enq,
coreFix_aluExe_1_regToExeQ$RDY_first,
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_aluExe_1_rsAlu
reg [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_2_put,
coreFix_aluExe_1_rsAlu$setRegReady_4_put;
reg [3 : 0] coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag;
wire [161 : 0] coreFix_aluExe_1_rsAlu$dispatchData,
coreFix_aluExe_1_rsAlu$enq_x;
wire [11 : 0] coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_aluExe_1_rsAlu$setRegReady_0_put,
coreFix_aluExe_1_rsAlu$setRegReady_1_put,
coreFix_aluExe_1_rsAlu$setRegReady_3_put;
wire [5 : 0] coreFix_aluExe_1_rsAlu$setRobEnqTime_t;
wire [4 : 0] coreFix_aluExe_1_rsAlu$approximateCount;
wire coreFix_aluExe_1_rsAlu$EN_doDispatch,
coreFix_aluExe_1_rsAlu$EN_enq,
coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put,
coreFix_aluExe_1_rsAlu$EN_setRobEnqTime,
coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation,
coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation,
coreFix_aluExe_1_rsAlu$RDY_dispatchData,
coreFix_aluExe_1_rsAlu$RDY_doDispatch,
coreFix_aluExe_1_rsAlu$RDY_enq,
coreFix_aluExe_1_rsAlu$canEnq,
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_dispToRegQ
reg [3 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [77 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$enq_x,
coreFix_fpuMulDivExe_0_dispToRegQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq,
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first,
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
wire [130 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
wire [195 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put;
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get;
wire coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
wire [68 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get;
wire [66 : 0] coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put;
wire coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag;
wire [101 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first,
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
reg [3 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag;
wire [42 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata;
wire [75 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata;
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
wire coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
reg [3 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag;
wire [35 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data;
wire [11 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
wire [63 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B;
// ports of submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
reg [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN;
wire [127 : 0] coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT;
wire coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ;
// ports of submodule coreFix_fpuMulDivExe_0_regToExeQ
reg [3 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [245 : 0] coreFix_fpuMulDivExe_0_regToExeQ$enq_x,
coreFix_fpuMulDivExe_0_regToExeQ$first;
wire [11 : 0] coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_fpuMulDivExe_0_regToExeQ$EN_deq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_enq,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq,
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first,
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
reg [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put;
reg [3 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag;
wire [86 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x;
wire [11 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put;
wire [5 : 0] coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t;
wire coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
reg [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n;
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData;
wire [152 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq;
wire [63 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr;
wire [57 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot;
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ;
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n;
wire coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
wire [512 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData;
wire [65 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq;
wire [1 : 0] coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n;
wire coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
reg [583 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r;
reg [569 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam;
reg [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq;
reg coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep;
wire [578 : 0] coreFix_memExe_dMem_cache_m_banks_0_pipeline$first;
wire coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
wire [2 : 0] coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
wire [3 : 0] coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT;
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ,
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN,
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
wire coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_dTlb
reg [3 : 0] coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag;
wire [174 : 0] coreFix_memExe_dTlb$procResp;
wire [105 : 0] coreFix_memExe_dTlb$procReq_req;
wire [82 : 0] coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x;
wire [48 : 0] coreFix_memExe_dTlb$updateVMInfo_vm;
wire [28 : 0] coreFix_memExe_dTlb$toParent_rqToP_first;
wire [11 : 0] coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask;
wire [2 : 0] coreFix_memExe_dTlb$perf_req_r;
wire coreFix_memExe_dTlb$EN_deqProcResp,
coreFix_memExe_dTlb$EN_flush,
coreFix_memExe_dTlb$EN_perf_req,
coreFix_memExe_dTlb$EN_perf_resp,
coreFix_memExe_dTlb$EN_perf_setStatus,
coreFix_memExe_dTlb$EN_procReq,
coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation,
coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dTlb$EN_toParent_flush_request_get,
coreFix_memExe_dTlb$EN_toParent_flush_response_put,
coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$EN_toParent_rqToP_deq,
coreFix_memExe_dTlb$EN_updateVMInfo,
coreFix_memExe_dTlb$RDY_deqProcResp,
coreFix_memExe_dTlb$RDY_flush,
coreFix_memExe_dTlb$RDY_procReq,
coreFix_memExe_dTlb$RDY_procResp,
coreFix_memExe_dTlb$RDY_toParent_flush_request_get,
coreFix_memExe_dTlb$RDY_toParent_flush_response_put,
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq,
coreFix_memExe_dTlb$RDY_toParent_rqToP_first,
coreFix_memExe_dTlb$flush_done,
coreFix_memExe_dTlb$noPendingReq,
coreFix_memExe_dTlb$perf_setStatus_doStats,
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_dispToRegQ
reg [3 : 0] coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag;
wire [97 : 0] coreFix_memExe_dispToRegQ$enq_x,
coreFix_memExe_dispToRegQ$first;
wire [11 : 0] coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_dispToRegQ$EN_deq,
coreFix_memExe_dispToRegQ$EN_enq,
coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_dispToRegQ$RDY_deq,
coreFix_memExe_dispToRegQ$RDY_enq,
coreFix_memExe_dispToRegQ$RDY_first,
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
wire coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
wire coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$EN,
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
wire coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
wire coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
wire coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
wire coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
wire coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
wire coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$EN,
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_lsq
reg [3 : 0] coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag;
wire [170 : 0] coreFix_memExe_lsq$firstSt;
wire [113 : 0] coreFix_memExe_lsq$firstLd;
wire [76 : 0] coreFix_memExe_lsq$getIssueLd;
wire [74 : 0] coreFix_memExe_lsq$issueLd;
wire [73 : 0] coreFix_memExe_lsq$respLd;
wire [67 : 0] coreFix_memExe_lsq$issueLd_sbRes;
wire [63 : 0] coreFix_memExe_lsq$issueLd_paddr,
coreFix_memExe_lsq$respLd_alignedData,
coreFix_memExe_lsq$updateAddr_paddr,
coreFix_memExe_lsq$updateData_d;
wire [17 : 0] coreFix_memExe_lsq$enqLd_mem_inst,
coreFix_memExe_lsq$enqSt_mem_inst;
wire [11 : 0] coreFix_memExe_lsq$enqLd_inst_tag,
coreFix_memExe_lsq$enqLd_spec_bits,
coreFix_memExe_lsq$enqSt_inst_tag,
coreFix_memExe_lsq$enqSt_spec_bits,
coreFix_memExe_lsq$specUpdate_correctSpeculation_mask;
wire [9 : 0] coreFix_memExe_lsq$getHit;
wire [8 : 0] coreFix_memExe_lsq$enqLd_dst, coreFix_memExe_lsq$enqSt_dst;
wire [7 : 0] coreFix_memExe_lsq$getOrigBE,
coreFix_memExe_lsq$issueLd_shiftedBE,
coreFix_memExe_lsq$updateAddr_shiftedBE;
wire [6 : 0] coreFix_memExe_lsq$enqLdTag, coreFix_memExe_lsq$enqStTag;
wire [5 : 0] coreFix_memExe_lsq$getHit_t,
coreFix_memExe_lsq$getOrigBE_t,
coreFix_memExe_lsq$setAtCommit_0_put,
coreFix_memExe_lsq$setAtCommit_1_put,
coreFix_memExe_lsq$updateAddr_lsqTag;
wire [4 : 0] coreFix_memExe_lsq$issueLd_lsqTag,
coreFix_memExe_lsq$respLd_t,
coreFix_memExe_lsq$updateAddr_fault;
wire [3 : 0] coreFix_memExe_lsq$updateData_t;
wire [1 : 0] coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx;
wire coreFix_memExe_lsq$EN_deqLd,
coreFix_memExe_lsq$EN_deqSt,
coreFix_memExe_lsq$EN_enqLd,
coreFix_memExe_lsq$EN_enqSt,
coreFix_memExe_lsq$EN_getHit,
coreFix_memExe_lsq$EN_getIssueLd,
coreFix_memExe_lsq$EN_issueLd,
coreFix_memExe_lsq$EN_respLd,
coreFix_memExe_lsq$EN_setAtCommit_0_put,
coreFix_memExe_lsq$EN_setAtCommit_1_put,
coreFix_memExe_lsq$EN_specUpdate_correctSpeculation,
coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_lsq$EN_updateAddr,
coreFix_memExe_lsq$EN_updateData,
coreFix_memExe_lsq$EN_wakeupLdStalledBySB,
coreFix_memExe_lsq$RDY_deqLd,
coreFix_memExe_lsq$RDY_deqSt,
coreFix_memExe_lsq$RDY_enqLd,
coreFix_memExe_lsq$RDY_enqSt,
coreFix_memExe_lsq$RDY_firstLd,
coreFix_memExe_lsq$RDY_firstSt,
coreFix_memExe_lsq$RDY_getIssueLd,
coreFix_memExe_lsq$noWrongPathLoads,
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all,
coreFix_memExe_lsq$stqEmpty,
coreFix_memExe_lsq$updateAddr,
coreFix_memExe_lsq$updateAddr_isMMIO;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
wire coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN,
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
wire coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_regToExeQ
reg [3 : 0] coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag;
wire [192 : 0] coreFix_memExe_regToExeQ$enq_x,
coreFix_memExe_regToExeQ$first;
wire [11 : 0] coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask;
wire coreFix_memExe_regToExeQ$EN_deq,
coreFix_memExe_regToExeQ$EN_enq,
coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation,
coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_regToExeQ$RDY_deq,
coreFix_memExe_regToExeQ$RDY_enq,
coreFix_memExe_regToExeQ$RDY_first,
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
wire coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
wire coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
wire coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
wire coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_0
wire coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_1
wire coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_1$EN,
coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_empty_dummy2_2
wire coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_empty_dummy2_2$EN,
coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
wire coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
wire coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_0
wire coreFix_memExe_reqLdQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_0$EN,
coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_1
wire coreFix_memExe_reqLdQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_1$EN,
coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLdQ_full_dummy2_2
wire coreFix_memExe_reqLdQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLdQ_full_dummy2_2$EN,
coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
wire coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN,
coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_0
wire coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_data_0_dummy2_1
wire coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN,
coreFix_memExe_reqStQ_data_0_dummy2_1$EN,
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_0
wire coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_deqP_dummy2_1
wire coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_deqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_0
wire coreFix_memExe_reqStQ_empty_dummy2_0$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_1
wire coreFix_memExe_reqStQ_empty_dummy2_1$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_1$EN,
coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_empty_dummy2_2
wire coreFix_memExe_reqStQ_empty_dummy2_2$D_IN,
coreFix_memExe_reqStQ_empty_dummy2_2$EN,
coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_0
wire coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_0$EN;
// ports of submodule coreFix_memExe_reqStQ_enqP_dummy2_1
wire coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN,
coreFix_memExe_reqStQ_enqP_dummy2_1$EN;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_0
wire coreFix_memExe_reqStQ_full_dummy2_0$D_IN,
coreFix_memExe_reqStQ_full_dummy2_0$EN,
coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_1
wire coreFix_memExe_reqStQ_full_dummy2_1$D_IN,
coreFix_memExe_reqStQ_full_dummy2_1$EN,
coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_reqStQ_full_dummy2_2
wire coreFix_memExe_reqStQ_full_dummy2_2$D_IN,
coreFix_memExe_reqStQ_full_dummy2_2$EN,
coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN,
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN;
// ports of submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
wire coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule coreFix_memExe_rsMem
reg [7 : 0] coreFix_memExe_rsMem$setRegReady_2_put,
coreFix_memExe_rsMem$setRegReady_4_put;
reg [3 : 0] coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag;
wire [106 : 0] coreFix_memExe_rsMem$dispatchData,
coreFix_memExe_rsMem$enq_x;
wire [11 : 0] coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask;
wire [7 : 0] coreFix_memExe_rsMem$setRegReady_0_put,
coreFix_memExe_rsMem$setRegReady_1_put,
coreFix_memExe_rsMem$setRegReady_3_put;
wire [5 : 0] coreFix_memExe_rsMem$setRobEnqTime_t;
wire coreFix_memExe_rsMem$EN_doDispatch,
coreFix_memExe_rsMem$EN_enq,
coreFix_memExe_rsMem$EN_setRegReady_0_put,
coreFix_memExe_rsMem$EN_setRegReady_1_put,
coreFix_memExe_rsMem$EN_setRegReady_2_put,
coreFix_memExe_rsMem$EN_setRegReady_3_put,
coreFix_memExe_rsMem$EN_setRegReady_4_put,
coreFix_memExe_rsMem$EN_setRobEnqTime,
coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation,
coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation,
coreFix_memExe_rsMem$RDY_dispatchData,
coreFix_memExe_rsMem$RDY_doDispatch,
coreFix_memExe_rsMem$RDY_enq,
coreFix_memExe_rsMem$canEnq,
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule coreFix_memExe_stb
wire [635 : 0] coreFix_memExe_stb$issue;
wire [633 : 0] coreFix_memExe_stb$deq;
wire [67 : 0] coreFix_memExe_stb$search;
wire [63 : 0] coreFix_memExe_stb$enq_data,
coreFix_memExe_stb$enq_paddr,
coreFix_memExe_stb$getEnqIndex_paddr,
coreFix_memExe_stb$noMatchLdQ_paddr,
coreFix_memExe_stb$noMatchStQ_paddr,
coreFix_memExe_stb$search_paddr;
wire [7 : 0] coreFix_memExe_stb$enq_be,
coreFix_memExe_stb$noMatchLdQ_be,
coreFix_memExe_stb$noMatchStQ_be,
coreFix_memExe_stb$search_be;
wire [2 : 0] coreFix_memExe_stb$getEnqIndex;
wire [1 : 0] coreFix_memExe_stb$deq_idx, coreFix_memExe_stb$enq_idx;
wire coreFix_memExe_stb$EN_deq,
coreFix_memExe_stb$EN_enq,
coreFix_memExe_stb$EN_issue,
coreFix_memExe_stb$RDY_deq,
coreFix_memExe_stb$RDY_enq,
coreFix_memExe_stb$RDY_issue,
coreFix_memExe_stb$isEmpty,
coreFix_memExe_stb$noMatchLdQ,
coreFix_memExe_stb$noMatchStQ;
// ports of submodule coreFix_trainBPQ_0
wire [159 : 0] coreFix_trainBPQ_0$D_IN, coreFix_trainBPQ_0$D_OUT;
wire coreFix_trainBPQ_0$CLR,
coreFix_trainBPQ_0$DEQ,
coreFix_trainBPQ_0$EMPTY_N,
coreFix_trainBPQ_0$ENQ,
coreFix_trainBPQ_0$FULL_N;
// ports of submodule coreFix_trainBPQ_1
wire [159 : 0] coreFix_trainBPQ_1$D_IN, coreFix_trainBPQ_1$D_OUT;
wire coreFix_trainBPQ_1$CLR,
coreFix_trainBPQ_1$DEQ,
coreFix_trainBPQ_1$EMPTY_N,
coreFix_trainBPQ_1$ENQ,
coreFix_trainBPQ_1$FULL_N;
// ports of submodule csrInstOrInterruptInflight_dummy2_0
wire csrInstOrInterruptInflight_dummy2_0$D_IN,
csrInstOrInterruptInflight_dummy2_0$EN,
csrInstOrInterruptInflight_dummy2_0$Q_OUT;
// ports of submodule csrInstOrInterruptInflight_dummy2_1
wire csrInstOrInterruptInflight_dummy2_1$D_IN,
csrInstOrInterruptInflight_dummy2_1$EN,
csrInstOrInterruptInflight_dummy2_1$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_0
wire csrf_mcycle_ehr_data_dummy2_0$D_IN,
csrf_mcycle_ehr_data_dummy2_0$EN,
csrf_mcycle_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_mcycle_ehr_data_dummy2_1
wire csrf_mcycle_ehr_data_dummy2_1$D_IN,
csrf_mcycle_ehr_data_dummy2_1$EN,
csrf_mcycle_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_0
wire csrf_minstret_ehr_data_dummy2_0$D_IN,
csrf_minstret_ehr_data_dummy2_0$EN,
csrf_minstret_ehr_data_dummy2_0$Q_OUT;
// ports of submodule csrf_minstret_ehr_data_dummy2_1
wire csrf_minstret_ehr_data_dummy2_1$D_IN,
csrf_minstret_ehr_data_dummy2_1$EN,
csrf_minstret_ehr_data_dummy2_1$Q_OUT;
// ports of submodule csrf_stats_module_writeQ
wire csrf_stats_module_writeQ$CLR,
csrf_stats_module_writeQ$DEQ,
csrf_stats_module_writeQ$D_IN,
csrf_stats_module_writeQ$D_OUT,
csrf_stats_module_writeQ$EMPTY_N,
csrf_stats_module_writeQ$ENQ,
csrf_stats_module_writeQ$FULL_N;
// ports of submodule csrf_terminate_module_terminateQ
wire csrf_terminate_module_terminateQ$CLR,
csrf_terminate_module_terminateQ$DEQ,
csrf_terminate_module_terminateQ$EMPTY_N,
csrf_terminate_module_terminateQ$ENQ,
csrf_terminate_module_terminateQ$FULL_N;
// ports of submodule epochManager
wire [3 : 0] epochManager$checkEpoch_0_check_e,
epochManager$checkEpoch_1_check_e,
epochManager$updatePrevEpoch_0_update_e,
epochManager$updatePrevEpoch_1_update_e;
wire epochManager$EN_incrementEpoch,
epochManager$EN_updatePrevEpoch_0_update,
epochManager$EN_updatePrevEpoch_1_update,
epochManager$RDY_incrementEpoch,
epochManager$checkEpoch_0_check,
epochManager$checkEpoch_1_check;
// ports of submodule f_csr_reqs
wire [76 : 0] f_csr_reqs$D_IN, f_csr_reqs$D_OUT;
wire f_csr_reqs$CLR,
f_csr_reqs$DEQ,
f_csr_reqs$EMPTY_N,
f_csr_reqs$ENQ,
f_csr_reqs$FULL_N;
// ports of submodule f_csr_rsps
reg [64 : 0] f_csr_rsps$D_IN;
wire [64 : 0] f_csr_rsps$D_OUT;
wire f_csr_rsps$CLR,
f_csr_rsps$DEQ,
f_csr_rsps$EMPTY_N,
f_csr_rsps$ENQ,
f_csr_rsps$FULL_N;
// ports of submodule f_fpr_reqs
wire [69 : 0] f_fpr_reqs$D_IN, f_fpr_reqs$D_OUT;
wire f_fpr_reqs$CLR,
f_fpr_reqs$DEQ,
f_fpr_reqs$EMPTY_N,
f_fpr_reqs$ENQ,
f_fpr_reqs$FULL_N;
// ports of submodule f_fpr_rsps
reg [64 : 0] f_fpr_rsps$D_IN;
wire [64 : 0] f_fpr_rsps$D_OUT;
wire f_fpr_rsps$CLR,
f_fpr_rsps$DEQ,
f_fpr_rsps$EMPTY_N,
f_fpr_rsps$ENQ,
f_fpr_rsps$FULL_N;
// ports of submodule f_gpr_reqs
wire [69 : 0] f_gpr_reqs$D_IN, f_gpr_reqs$D_OUT;
wire f_gpr_reqs$CLR,
f_gpr_reqs$DEQ,
f_gpr_reqs$EMPTY_N,
f_gpr_reqs$ENQ,
f_gpr_reqs$FULL_N;
// ports of submodule f_gpr_rsps
reg [64 : 0] f_gpr_rsps$D_IN;
wire [64 : 0] f_gpr_rsps$D_OUT;
wire f_gpr_rsps$CLR,
f_gpr_rsps$DEQ,
f_gpr_rsps$EMPTY_N,
f_gpr_rsps$ENQ,
f_gpr_rsps$FULL_N;
// ports of submodule f_run_halt_reqs
wire f_run_halt_reqs$CLR,
f_run_halt_reqs$DEQ,
f_run_halt_reqs$D_IN,
f_run_halt_reqs$D_OUT,
f_run_halt_reqs$EMPTY_N,
f_run_halt_reqs$ENQ,
f_run_halt_reqs$FULL_N;
// ports of submodule f_run_halt_rsps
wire f_run_halt_rsps$CLR,
f_run_halt_rsps$DEQ,
f_run_halt_rsps$D_IN,
f_run_halt_rsps$D_OUT,
f_run_halt_rsps$EMPTY_N,
f_run_halt_rsps$ENQ,
f_run_halt_rsps$FULL_N;
// ports of submodule fetchStage
reg [63 : 0] fetchStage$redirect_pc;
wire [582 : 0] fetchStage$iMemIfc_to_parent_fromP_enq_x;
wire [578 : 0] fetchStage$iMemIfc_to_parent_rsToP_first;
wire [387 : 0] fetchStage$pipelines_0_first, fetchStage$pipelines_1_first;
wire [80 : 0] fetchStage$iTlbIfc_toParent_rsFromP_enq_x;
wire [71 : 0] fetchStage$iMemIfc_to_parent_rqToP_first;
wire [67 : 0] fetchStage$iMemIfc_cRqStuck_get,
fetchStage$iMemIfc_pRqStuck_get;
wire [65 : 0] fetchStage$mmioIfc_instResp_enq_x;
wire [63 : 0] fetchStage$iMemIfc_to_proc_request_put,
fetchStage$iTlbIfc_to_proc_request_put,
fetchStage$mmioIfc_instReq_first_fst,
fetchStage$mmioIfc_setHtifAddrs_fromHost,
fetchStage$mmioIfc_setHtifAddrs_toHost,
fetchStage$start_pc,
fetchStage$train_predictors_next_pc,
fetchStage$train_predictors_pc;
wire [48 : 0] fetchStage$iTlbIfc_updateVMInfo_vm;
wire [26 : 0] fetchStage$iTlbIfc_toParent_rqToP_first;
wire [23 : 0] fetchStage$train_predictors_dpTrain;
wire [4 : 0] fetchStage$train_predictors_iType;
wire [2 : 0] fetchStage$iTlbIfc_perf_req_r;
wire [1 : 0] fetchStage$iMemIfc_perf_req_r, fetchStage$perf_req_r;
wire fetchStage$EN_done_flushing,
fetchStage$EN_flush_predictors,
fetchStage$EN_iMemIfc_cRqStuck_get,
fetchStage$EN_iMemIfc_flush,
fetchStage$EN_iMemIfc_pRqStuck_get,
fetchStage$EN_iMemIfc_perf_req,
fetchStage$EN_iMemIfc_perf_resp,
fetchStage$EN_iMemIfc_perf_setStatus,
fetchStage$EN_iMemIfc_to_parent_fromP_enq,
fetchStage$EN_iMemIfc_to_parent_rqToP_deq,
fetchStage$EN_iMemIfc_to_parent_rsToP_deq,
fetchStage$EN_iMemIfc_to_proc_request_put,
fetchStage$EN_iMemIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_flush,
fetchStage$EN_iTlbIfc_perf_req,
fetchStage$EN_iTlbIfc_perf_resp,
fetchStage$EN_iTlbIfc_perf_setStatus,
fetchStage$EN_iTlbIfc_toParent_flush_request_get,
fetchStage$EN_iTlbIfc_toParent_flush_response_put,
fetchStage$EN_iTlbIfc_toParent_rqToP_deq,
fetchStage$EN_iTlbIfc_toParent_rsFromP_enq,
fetchStage$EN_iTlbIfc_to_proc_request_put,
fetchStage$EN_iTlbIfc_to_proc_response_get,
fetchStage$EN_iTlbIfc_updateVMInfo,
fetchStage$EN_mmioIfc_instReq_deq,
fetchStage$EN_mmioIfc_instResp_enq,
fetchStage$EN_mmioIfc_setHtifAddrs,
fetchStage$EN_perf_req,
fetchStage$EN_perf_resp,
fetchStage$EN_perf_setStatus,
fetchStage$EN_pipelines_0_deq,
fetchStage$EN_pipelines_1_deq,
fetchStage$EN_redirect,
fetchStage$EN_setWaitFlush,
fetchStage$EN_setWaitRedirect,
fetchStage$EN_start,
fetchStage$EN_stop,
fetchStage$EN_train_predictors,
fetchStage$RDY_done_flushing,
fetchStage$RDY_iMemIfc_cRqStuck_get,
fetchStage$RDY_iMemIfc_pRqStuck_get,
fetchStage$RDY_iMemIfc_to_parent_fromP_enq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rqToP_first,
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq,
fetchStage$RDY_iMemIfc_to_parent_rsToP_first,
fetchStage$RDY_iTlbIfc_flush,
fetchStage$RDY_iTlbIfc_toParent_flush_request_get,
fetchStage$RDY_iTlbIfc_toParent_flush_response_put,
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq,
fetchStage$RDY_iTlbIfc_toParent_rqToP_first,
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq,
fetchStage$RDY_mmioIfc_instReq_deq,
fetchStage$RDY_mmioIfc_instReq_first_fst,
fetchStage$RDY_mmioIfc_instReq_first_snd,
fetchStage$RDY_mmioIfc_instResp_enq,
fetchStage$RDY_pipelines_0_deq,
fetchStage$RDY_pipelines_0_first,
fetchStage$RDY_pipelines_1_deq,
fetchStage$RDY_pipelines_1_first,
fetchStage$emptyForFlush,
fetchStage$flush_predictors_done,
fetchStage$iMemIfc_flush_done,
fetchStage$iMemIfc_perf_setStatus_doStats,
fetchStage$iMemIfc_to_parent_fromP_notFull,
fetchStage$iMemIfc_to_parent_rqToP_notEmpty,
fetchStage$iMemIfc_to_parent_rsToP_notEmpty,
fetchStage$iTlbIfc_flush_done,
fetchStage$iTlbIfc_noPendingReq,
fetchStage$iTlbIfc_perf_setStatus_doStats,
fetchStage$mmioIfc_instReq_first_snd,
fetchStage$perf_setStatus_doStats,
fetchStage$pipelines_0_canDeq,
fetchStage$pipelines_1_canDeq,
fetchStage$train_predictors_isCompressed,
fetchStage$train_predictors_mispred,
fetchStage$train_predictors_taken;
// ports of submodule l2Tlb
wire [83 : 0] l2Tlb$toChildren_rsToC_first;
wire [64 : 0] l2Tlb$toMem_memReq_first, l2Tlb$toMem_respLd_enq_x;
wire [48 : 0] l2Tlb$updateVMInfo_vmD, l2Tlb$updateVMInfo_vmI;
wire [29 : 0] l2Tlb$toChildren_rqFromC_put;
wire [3 : 0] l2Tlb$perf_req_r;
wire l2Tlb$EN_perf_req,
l2Tlb$EN_perf_resp,
l2Tlb$EN_perf_setStatus,
l2Tlb$EN_toChildren_dTlbReqFlush_put,
l2Tlb$EN_toChildren_flushDone_get,
l2Tlb$EN_toChildren_iTlbReqFlush_put,
l2Tlb$EN_toChildren_rqFromC_put,
l2Tlb$EN_toChildren_rsToC_deq,
l2Tlb$EN_toMem_memReq_deq,
l2Tlb$EN_toMem_respLd_enq,
l2Tlb$EN_updateVMInfo,
l2Tlb$RDY_toChildren_dTlbReqFlush_put,
l2Tlb$RDY_toChildren_flushDone_get,
l2Tlb$RDY_toChildren_iTlbReqFlush_put,
l2Tlb$RDY_toChildren_rqFromC_put,
l2Tlb$RDY_toChildren_rsToC_deq,
l2Tlb$RDY_toChildren_rsToC_first,
l2Tlb$RDY_toMem_memReq_deq,
l2Tlb$RDY_toMem_memReq_first,
l2Tlb$RDY_toMem_respLd_enq,
l2Tlb$perf_setStatus_doStats,
l2Tlb$toMem_memReq_notEmpty,
l2Tlb$toMem_respLd_notFull;
// ports of submodule mmio_cRqQ_clearReq_dummy2_0
wire mmio_cRqQ_clearReq_dummy2_0$D_IN, mmio_cRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_clearReq_dummy2_1
wire mmio_cRqQ_clearReq_dummy2_1$D_IN,
mmio_cRqQ_clearReq_dummy2_1$EN,
mmio_cRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRqQ_deqReq_dummy2_0
wire mmio_cRqQ_deqReq_dummy2_0$D_IN, mmio_cRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_1
wire mmio_cRqQ_deqReq_dummy2_1$D_IN, mmio_cRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_deqReq_dummy2_2
wire mmio_cRqQ_deqReq_dummy2_2$D_IN,
mmio_cRqQ_deqReq_dummy2_2$EN,
mmio_cRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRqQ_enqReq_dummy2_0
wire mmio_cRqQ_enqReq_dummy2_0$D_IN, mmio_cRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_1
wire mmio_cRqQ_enqReq_dummy2_1$D_IN, mmio_cRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRqQ_enqReq_dummy2_2
wire mmio_cRqQ_enqReq_dummy2_2$D_IN,
mmio_cRqQ_enqReq_dummy2_2$EN,
mmio_cRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_clearReq_dummy2_0
wire mmio_cRsQ_clearReq_dummy2_0$D_IN, mmio_cRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_clearReq_dummy2_1
wire mmio_cRsQ_clearReq_dummy2_1$D_IN,
mmio_cRsQ_clearReq_dummy2_1$EN,
mmio_cRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_cRsQ_deqReq_dummy2_0
wire mmio_cRsQ_deqReq_dummy2_0$D_IN, mmio_cRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_1
wire mmio_cRsQ_deqReq_dummy2_1$D_IN, mmio_cRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_deqReq_dummy2_2
wire mmio_cRsQ_deqReq_dummy2_2$D_IN,
mmio_cRsQ_deqReq_dummy2_2$EN,
mmio_cRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_cRsQ_enqReq_dummy2_0
wire mmio_cRsQ_enqReq_dummy2_0$D_IN, mmio_cRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_1
wire mmio_cRsQ_enqReq_dummy2_1$D_IN, mmio_cRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_cRsQ_enqReq_dummy2_2
wire mmio_cRsQ_enqReq_dummy2_2$D_IN,
mmio_cRsQ_enqReq_dummy2_2$EN,
mmio_cRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_0
wire mmio_dataPendQ_clearReq_dummy2_0$D_IN,
mmio_dataPendQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_clearReq_dummy2_1
wire mmio_dataPendQ_clearReq_dummy2_1$D_IN,
mmio_dataPendQ_clearReq_dummy2_1$EN,
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_0
wire mmio_dataPendQ_deqReq_dummy2_0$D_IN, mmio_dataPendQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_1
wire mmio_dataPendQ_deqReq_dummy2_1$D_IN, mmio_dataPendQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_deqReq_dummy2_2
wire mmio_dataPendQ_deqReq_dummy2_2$D_IN,
mmio_dataPendQ_deqReq_dummy2_2$EN,
mmio_dataPendQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_0
wire mmio_dataPendQ_enqReq_dummy2_0$D_IN, mmio_dataPendQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_1
wire mmio_dataPendQ_enqReq_dummy2_1$D_IN, mmio_dataPendQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataPendQ_enqReq_dummy2_2
wire mmio_dataPendQ_enqReq_dummy2_2$D_IN,
mmio_dataPendQ_enqReq_dummy2_2$EN,
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_0
wire mmio_dataReqQ_clearReq_dummy2_0$D_IN,
mmio_dataReqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_clearReq_dummy2_1
wire mmio_dataReqQ_clearReq_dummy2_1$D_IN,
mmio_dataReqQ_clearReq_dummy2_1$EN,
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_0
wire mmio_dataReqQ_deqReq_dummy2_0$D_IN, mmio_dataReqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_1
wire mmio_dataReqQ_deqReq_dummy2_1$D_IN, mmio_dataReqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_deqReq_dummy2_2
wire mmio_dataReqQ_deqReq_dummy2_2$D_IN,
mmio_dataReqQ_deqReq_dummy2_2$EN,
mmio_dataReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_0
wire mmio_dataReqQ_enqReq_dummy2_0$D_IN, mmio_dataReqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_1
wire mmio_dataReqQ_enqReq_dummy2_1$D_IN, mmio_dataReqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataReqQ_enqReq_dummy2_2
wire mmio_dataReqQ_enqReq_dummy2_2$D_IN,
mmio_dataReqQ_enqReq_dummy2_2$EN,
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_0
wire mmio_dataRespQ_clearReq_dummy2_0$D_IN,
mmio_dataRespQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_clearReq_dummy2_1
wire mmio_dataRespQ_clearReq_dummy2_1$D_IN,
mmio_dataRespQ_clearReq_dummy2_1$EN,
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_0
wire mmio_dataRespQ_deqReq_dummy2_0$D_IN, mmio_dataRespQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_1
wire mmio_dataRespQ_deqReq_dummy2_1$D_IN, mmio_dataRespQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_deqReq_dummy2_2
wire mmio_dataRespQ_deqReq_dummy2_2$D_IN,
mmio_dataRespQ_deqReq_dummy2_2$EN,
mmio_dataRespQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_0
wire mmio_dataRespQ_enqReq_dummy2_0$D_IN, mmio_dataRespQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_1
wire mmio_dataRespQ_enqReq_dummy2_1$D_IN, mmio_dataRespQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_dataRespQ_enqReq_dummy2_2
wire mmio_dataRespQ_enqReq_dummy2_2$D_IN,
mmio_dataRespQ_enqReq_dummy2_2$EN,
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_clearReq_dummy2_0
wire mmio_pRqQ_clearReq_dummy2_0$D_IN, mmio_pRqQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_clearReq_dummy2_1
wire mmio_pRqQ_clearReq_dummy2_1$D_IN,
mmio_pRqQ_clearReq_dummy2_1$EN,
mmio_pRqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRqQ_deqReq_dummy2_0
wire mmio_pRqQ_deqReq_dummy2_0$D_IN, mmio_pRqQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_1
wire mmio_pRqQ_deqReq_dummy2_1$D_IN, mmio_pRqQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_deqReq_dummy2_2
wire mmio_pRqQ_deqReq_dummy2_2$D_IN,
mmio_pRqQ_deqReq_dummy2_2$EN,
mmio_pRqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRqQ_enqReq_dummy2_0
wire mmio_pRqQ_enqReq_dummy2_0$D_IN, mmio_pRqQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_1
wire mmio_pRqQ_enqReq_dummy2_1$D_IN, mmio_pRqQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRqQ_enqReq_dummy2_2
wire mmio_pRqQ_enqReq_dummy2_2$D_IN,
mmio_pRqQ_enqReq_dummy2_2$EN,
mmio_pRqQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_clearReq_dummy2_0
wire mmio_pRsQ_clearReq_dummy2_0$D_IN, mmio_pRsQ_clearReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_clearReq_dummy2_1
wire mmio_pRsQ_clearReq_dummy2_1$D_IN,
mmio_pRsQ_clearReq_dummy2_1$EN,
mmio_pRsQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule mmio_pRsQ_deqReq_dummy2_0
wire mmio_pRsQ_deqReq_dummy2_0$D_IN, mmio_pRsQ_deqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_1
wire mmio_pRsQ_deqReq_dummy2_1$D_IN, mmio_pRsQ_deqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_deqReq_dummy2_2
wire mmio_pRsQ_deqReq_dummy2_2$D_IN,
mmio_pRsQ_deqReq_dummy2_2$EN,
mmio_pRsQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule mmio_pRsQ_enqReq_dummy2_0
wire mmio_pRsQ_enqReq_dummy2_0$D_IN, mmio_pRsQ_enqReq_dummy2_0$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_1
wire mmio_pRsQ_enqReq_dummy2_1$D_IN, mmio_pRsQ_enqReq_dummy2_1$EN;
// ports of submodule mmio_pRsQ_enqReq_dummy2_2
wire mmio_pRsQ_enqReq_dummy2_2$D_IN,
mmio_pRsQ_enqReq_dummy2_2$EN,
mmio_pRsQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule perfReqQ
wire [8 : 0] perfReqQ$D_IN, perfReqQ$D_OUT;
wire perfReqQ$CLR,
perfReqQ$DEQ,
perfReqQ$EMPTY_N,
perfReqQ$ENQ,
perfReqQ$FULL_N;
// ports of submodule regRenamingTable
reg [26 : 0] regRenamingTable$rename_0_getRename_r;
reg [3 : 0] regRenamingTable$specUpdate_incorrectSpeculation_kill_tag;
wire [32 : 0] regRenamingTable$rename_0_getRename,
regRenamingTable$rename_1_getRename;
wire [26 : 0] regRenamingTable$rename_0_claimRename_r,
regRenamingTable$rename_1_claimRename_r,
regRenamingTable$rename_1_getRename_r;
wire [11 : 0] regRenamingTable$rename_0_claimRename_sb,
regRenamingTable$rename_1_claimRename_sb,
regRenamingTable$specUpdate_correctSpeculation_mask;
wire regRenamingTable$EN_commit_0_commit,
regRenamingTable$EN_commit_1_commit,
regRenamingTable$EN_rename_0_claimRename,
regRenamingTable$EN_rename_1_claimRename,
regRenamingTable$EN_specUpdate_correctSpeculation,
regRenamingTable$EN_specUpdate_incorrectSpeculation,
regRenamingTable$RDY_commit_0_commit,
regRenamingTable$RDY_commit_1_commit,
regRenamingTable$RDY_rename_0_claimRename,
regRenamingTable$RDY_rename_0_getRename,
regRenamingTable$RDY_rename_1_claimRename,
regRenamingTable$RDY_rename_1_getRename,
regRenamingTable$rename_0_canRename,
regRenamingTable$rename_1_canRename,
regRenamingTable$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule rf
reg [63 : 0] rf$write_2_wr_data, rf$write_3_wr_data;
reg [6 : 0] rf$write_2_wr_rindx, rf$write_3_wr_rindx;
wire [63 : 0] rf$read_0_rd1,
rf$read_0_rd2,
rf$read_1_rd1,
rf$read_1_rd2,
rf$read_2_rd1,
rf$read_2_rd2,
rf$read_2_rd3,
rf$read_3_rd1,
rf$read_3_rd2,
rf$read_4_rd1,
rf$write_0_wr_data,
rf$write_1_wr_data,
rf$write_4_wr_data;
wire [6 : 0] rf$read_0_rd1_rindx,
rf$read_0_rd2_rindx,
rf$read_0_rd3_rindx,
rf$read_1_rd1_rindx,
rf$read_1_rd2_rindx,
rf$read_1_rd3_rindx,
rf$read_2_rd1_rindx,
rf$read_2_rd2_rindx,
rf$read_2_rd3_rindx,
rf$read_3_rd1_rindx,
rf$read_3_rd2_rindx,
rf$read_3_rd3_rindx,
rf$read_4_rd1_rindx,
rf$read_4_rd2_rindx,
rf$read_4_rd3_rindx,
rf$write_0_wr_rindx,
rf$write_1_wr_rindx,
rf$write_4_wr_rindx;
wire rf$EN_write_0_wr,
rf$EN_write_1_wr,
rf$EN_write_2_wr,
rf$EN_write_3_wr,
rf$EN_write_4_wr;
// ports of submodule rob
reg [282 : 0] rob$enqPort_0_enq_x;
reg [11 : 0] rob$setExecuted_doFinishFpuMulDiv_0_set_x,
rob$specUpdate_incorrectSpeculation_inst_tag;
reg [4 : 0] rob$setExecuted_deqLSQ_cause,
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags;
reg [3 : 0] rob$specUpdate_incorrectSpeculation_spec_tag;
wire [282 : 0] rob$deqPort_0_deq_data,
rob$deqPort_1_deq_data,
rob$enqPort_1_enq_x;
wire [129 : 0] rob$setExecuted_doFinishAlu_0_set_cf,
rob$setExecuted_doFinishAlu_1_set_cf;
wire [64 : 0] rob$setExecuted_doFinishAlu_0_set_csrData,
rob$setExecuted_doFinishAlu_1_set_csrData;
wire [63 : 0] rob$getOrigPC_0_get,
rob$getOrigPC_1_get,
rob$getOrigPredPC_0_get,
rob$getOrigPredPC_1_get,
rob$setExecuted_doFinishMem_vaddr;
wire [31 : 0] rob$getOrig_Inst_0_get, rob$getOrig_Inst_1_get;
wire [11 : 0] rob$deqPort_0_getDeqInstTag,
rob$enqPort_0_getEnqInstTag,
rob$enqPort_1_getEnqInstTag,
rob$getOrigPC_0_get_x,
rob$getOrigPC_1_get_x,
rob$getOrigPC_2_get_x,
rob$getOrigPredPC_0_get_x,
rob$getOrigPredPC_1_get_x,
rob$getOrig_Inst_0_get_x,
rob$getOrig_Inst_1_get_x,
rob$setExecuted_deqLSQ_x,
rob$setExecuted_doFinishAlu_0_set_x,
rob$setExecuted_doFinishAlu_1_set_x,
rob$setExecuted_doFinishMem_x,
rob$setLSQAtCommitNotified_x,
rob$specUpdate_correctSpeculation_mask;
wire [5 : 0] rob$getEnqTime;
wire [2 : 0] rob$setExecuted_deqLSQ_ld_killed;
wire rob$EN_deqPort_0_deq,
rob$EN_deqPort_1_deq,
rob$EN_enqPort_0_enq,
rob$EN_enqPort_1_enq,
rob$EN_setExecuted_deqLSQ,
rob$EN_setExecuted_doFinishAlu_0_set,
rob$EN_setExecuted_doFinishAlu_1_set,
rob$EN_setExecuted_doFinishFpuMulDiv_0_set,
rob$EN_setExecuted_doFinishMem,
rob$EN_setLSQAtCommitNotified,
rob$EN_specUpdate_correctSpeculation,
rob$EN_specUpdate_incorrectSpeculation,
rob$RDY_deqPort_0_deq,
rob$RDY_deqPort_0_deq_data,
rob$RDY_deqPort_1_deq,
rob$RDY_deqPort_1_deq_data,
rob$RDY_enqPort_0_enq,
rob$RDY_enqPort_1_enq,
rob$RDY_setExecuted_deqLSQ,
rob$RDY_setExecuted_doFinishAlu_0_set,
rob$RDY_setExecuted_doFinishAlu_1_set,
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set,
rob$RDY_setExecuted_doFinishMem,
rob$RDY_setLSQAtCommitNotified,
rob$deqPort_0_canDeq,
rob$deqPort_1_canDeq,
rob$enqPort_0_canEnq,
rob$enqPort_1_canEnq,
rob$isEmpty,
rob$setExecuted_doFinishMem_access_at_commit,
rob$setExecuted_doFinishMem_non_mmio_st_done,
rob$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule sbAggr
reg [6 : 0] sbAggr$setReady_2_put, sbAggr$setReady_4_put;
wire [32 : 0] sbAggr$eagerLookup_0_get_r, sbAggr$eagerLookup_1_get_r;
wire [8 : 0] sbAggr$setBusy_0_set_dst, sbAggr$setBusy_1_set_dst;
wire [6 : 0] sbAggr$setReady_0_put,
sbAggr$setReady_1_put,
sbAggr$setReady_3_put;
wire [3 : 0] sbAggr$eagerLookup_0_get, sbAggr$eagerLookup_1_get;
wire sbAggr$EN_setBusy_0_set,
sbAggr$EN_setBusy_1_set,
sbAggr$EN_setReady_0_put,
sbAggr$EN_setReady_1_put,
sbAggr$EN_setReady_2_put,
sbAggr$EN_setReady_3_put,
sbAggr$EN_setReady_4_put;
// ports of submodule sbCons
reg [6 : 0] sbCons$setReady_2_put, sbCons$setReady_3_put;
wire [32 : 0] sbCons$eagerLookup_0_get_r,
sbCons$eagerLookup_1_get_r,
sbCons$lazyLookup_0_get_r,
sbCons$lazyLookup_1_get_r,
sbCons$lazyLookup_2_get_r,
sbCons$lazyLookup_3_get_r,
sbCons$lazyLookup_4_get_r;
wire [8 : 0] sbCons$setBusy_0_set_dst, sbCons$setBusy_1_set_dst;
wire [6 : 0] sbCons$setReady_0_put,
sbCons$setReady_1_put,
sbCons$setReady_4_put;
wire [3 : 0] sbCons$lazyLookup_0_get,
sbCons$lazyLookup_1_get,
sbCons$lazyLookup_2_get,
sbCons$lazyLookup_3_get;
wire sbCons$EN_setBusy_0_set,
sbCons$EN_setBusy_1_set,
sbCons$EN_setReady_0_put,
sbCons$EN_setReady_1_put,
sbCons$EN_setReady_2_put,
sbCons$EN_setReady_3_put,
sbCons$EN_setReady_4_put;
// ports of submodule specTagManager
reg [3 : 0] specTagManager$specUpdate_incorrectSpeculation_kill_tag;
wire [11 : 0] specTagManager$currentSpecBits,
specTagManager$specUpdate_correctSpeculation_mask;
wire [3 : 0] specTagManager$nextSpecTag;
wire specTagManager$EN_claimSpecTag,
specTagManager$EN_specUpdate_correctSpeculation,
specTagManager$EN_specUpdate_incorrectSpeculation,
specTagManager$RDY_claimSpecTag,
specTagManager$RDY_nextSpecTag,
specTagManager$canClaim,
specTagManager$specUpdate_incorrectSpeculation_kill_all;
// ports of submodule v_f_to_TV_0
wire [319 : 0] v_f_to_TV_0$D_IN, v_f_to_TV_0$D_OUT;
wire v_f_to_TV_0$CLR,
v_f_to_TV_0$DEQ,
v_f_to_TV_0$EMPTY_N,
v_f_to_TV_0$ENQ,
v_f_to_TV_0$FULL_N;
// ports of submodule v_f_to_TV_1
wire [319 : 0] v_f_to_TV_1$D_IN, v_f_to_TV_1$D_OUT;
wire v_f_to_TV_1$CLR,
v_f_to_TV_1$DEQ,
v_f_to_TV_1$EMPTY_N,
v_f_to_TV_1$ENQ,
v_f_to_TV_1$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_commitStage_doCommitKilledLd,
CAN_FIRE_RL_commitStage_doCommitNormalInst,
CAN_FIRE_RL_commitStage_doCommitSystemInst,
CAN_FIRE_RL_commitStage_doCommitTrap_flush,
CAN_FIRE_RL_commitStage_doCommitTrap_handle,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit,
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1,
CAN_FIRE_RL_commitStage_notifyLSQCommit,
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
CAN_FIRE_RL_coreFix_doFetchTrainBP,
CAN_FIRE_RL_coreFix_doFetchTrainBP_1,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
CAN_FIRE_RL_coreFix_memExe_doDispatchMem,
CAN_FIRE_RL_coreFix_memExe_doExeMem,
CAN_FIRE_RL_coreFix_memExe_doFinishMem,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
CAN_FIRE_RL_coreFix_memExe_doIssueSB,
CAN_FIRE_RL_coreFix_memExe_doRegReadMem,
CAN_FIRE_RL_coreFix_memExe_doRespLdForward,
CAN_FIRE_RL_coreFix_memExe_doRespLdMem,
CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
CAN_FIRE_RL_coreFix_memExe_sendLdToMem,
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
CAN_FIRE_RL_coreFix_memExe_sendStToMem,
CAN_FIRE_RL_csrInstOrInterruptInflight_canon,
CAN_FIRE_RL_csrf_incCycle,
CAN_FIRE_RL_csrf_mcycle_ehr_data_canon,
CAN_FIRE_RL_csrf_mcycle_ehr_setRead,
CAN_FIRE_RL_csrf_minstret_ehr_data_canon,
CAN_FIRE_RL_csrf_minstret_ehr_setRead,
CAN_FIRE_RL_flushBrPred,
CAN_FIRE_RL_flushCaches,
CAN_FIRE_RL_mkConnectionGetPut,
CAN_FIRE_RL_mkConnectionGetPut_1,
CAN_FIRE_RL_mmio_cRqQ_canonicalize,
CAN_FIRE_RL_mmio_cRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_canonicalize,
CAN_FIRE_RL_mmio_cRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_cRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_cRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_canonicalize,
CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_canonicalize,
CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_canonicalize,
CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon,
CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon,
CAN_FIRE_RL_mmio_handlePRq,
CAN_FIRE_RL_mmio_pRqQ_canonicalize,
CAN_FIRE_RL_mmio_pRqQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRqQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRqQ_enqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_canonicalize,
CAN_FIRE_RL_mmio_pRsQ_clearReq_canon,
CAN_FIRE_RL_mmio_pRsQ_deqReq_canon,
CAN_FIRE_RL_mmio_pRsQ_enqReq_canon,
CAN_FIRE_RL_mmio_sendDataReq,
CAN_FIRE_RL_mmio_sendDataResp,
CAN_FIRE_RL_mmio_sendInstReq,
CAN_FIRE_RL_mmio_sendInstResp,
CAN_FIRE_RL_prepareCachesAndTlbs,
CAN_FIRE_RL_readyToFetch,
CAN_FIRE_RL_renameStage_doRenaming,
CAN_FIRE_RL_renameStage_doRenaming_SystemInst,
CAN_FIRE_RL_renameStage_doRenaming_Trap,
CAN_FIRE_RL_renameStage_doRenaming_wrongPath,
CAN_FIRE_RL_rl_debug_csr_access_busy,
CAN_FIRE_RL_rl_debug_csr_read,
CAN_FIRE_RL_rl_debug_csr_write,
CAN_FIRE_RL_rl_debug_fpr_access_busy,
CAN_FIRE_RL_rl_debug_fpr_read,
CAN_FIRE_RL_rl_debug_fpr_write,
CAN_FIRE_RL_rl_debug_gpr_access_busy,
CAN_FIRE_RL_rl_debug_gpr_read,
CAN_FIRE_RL_rl_debug_gpr_write,
CAN_FIRE_RL_rl_debug_halt_req,
CAN_FIRE_RL_rl_debug_halt_req_already_halted,
CAN_FIRE_RL_rl_debug_halted,
CAN_FIRE_RL_rl_debug_resume,
CAN_FIRE_RL_rl_debug_run_redundant,
CAN_FIRE_RL_rl_outOfReset,
CAN_FIRE_RL_sendDTlbReq,
CAN_FIRE_RL_sendFlushDone,
CAN_FIRE_RL_sendITlbReq,
CAN_FIRE_RL_sendRobEnqTime,
CAN_FIRE_RL_sendRsToDTlb,
CAN_FIRE_RL_sendRsToITlb,
CAN_FIRE_RL_setDoFlushBrPred,
CAN_FIRE_RL_setDoFlushCaches,
CAN_FIRE_coreIndInv_perfResp,
CAN_FIRE_coreIndInv_terminate,
CAN_FIRE_coreReq_perfReq,
CAN_FIRE_coreReq_start,
CAN_FIRE_dCacheToParent_fromP_enq,
CAN_FIRE_dCacheToParent_rqToP_deq,
CAN_FIRE_dCacheToParent_rsToP_deq,
CAN_FIRE_deadlock_checkStarted_get,
CAN_FIRE_deadlock_commitInstStuck_get,
CAN_FIRE_deadlock_commitUserInstStuck_get,
CAN_FIRE_deadlock_dCacheCRqStuck_get,
CAN_FIRE_deadlock_dCachePRqStuck_get,
CAN_FIRE_deadlock_iCacheCRqStuck_get,
CAN_FIRE_deadlock_iCachePRqStuck_get,
CAN_FIRE_deadlock_renameCorrectPathStuck_get,
CAN_FIRE_deadlock_renameInstStuck_get,
CAN_FIRE_hart0_csr_mem_server_request_put,
CAN_FIRE_hart0_csr_mem_server_response_get,
CAN_FIRE_hart0_fpr_mem_server_request_put,
CAN_FIRE_hart0_fpr_mem_server_response_get,
CAN_FIRE_hart0_gpr_mem_server_request_put,
CAN_FIRE_hart0_gpr_mem_server_response_get,
CAN_FIRE_hart0_run_halt_server_request_put,
CAN_FIRE_hart0_run_halt_server_response_get,
CAN_FIRE_iCacheToParent_fromP_enq,
CAN_FIRE_iCacheToParent_rqToP_deq,
CAN_FIRE_iCacheToParent_rsToP_deq,
CAN_FIRE_mmioToPlatform_cRq_deq,
CAN_FIRE_mmioToPlatform_cRs_deq,
CAN_FIRE_mmioToPlatform_pRq_enq,
CAN_FIRE_mmioToPlatform_pRs_enq,
CAN_FIRE_mmioToPlatform_setTime,
CAN_FIRE_recvDoStats,
CAN_FIRE_renameDebug_renameErr_get,
CAN_FIRE_sendDoStats,
CAN_FIRE_setMEIP,
CAN_FIRE_setSEIP,
CAN_FIRE_tlbToMem_memReq_deq,
CAN_FIRE_tlbToMem_respLd_enq,
CAN_FIRE_v_to_TV_0_get,
CAN_FIRE_v_to_TV_1_get,
WILL_FIRE_RL_commitStage_doCommitKilledLd,
WILL_FIRE_RL_commitStage_doCommitNormalInst,
WILL_FIRE_RL_commitStage_doCommitSystemInst,
WILL_FIRE_RL_commitStage_doCommitTrap_flush,
WILL_FIRE_RL_commitStage_doCommitTrap_handle,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit,
WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1,
WILL_FIRE_RL_commitStage_notifyLSQCommit,
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F,
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T,
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu,
WILL_FIRE_RL_coreFix_doFetchTrainBP,
WILL_FIRE_RL_coreFix_doFetchTrainBP_1,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit,
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon,
WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq,
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem,
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault,
WILL_FIRE_RL_coreFix_memExe_doDispatchMem,
WILL_FIRE_RL_coreFix_memExe_doExeMem,
WILL_FIRE_RL_coreFix_memExe_doFinishMem,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ,
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate,
WILL_FIRE_RL_coreFix_memExe_doIssueSB,
WILL_FIRE_RL_coreFix_memExe_doRegReadMem,
WILL_FIRE_RL_coreFix_memExe_doRespLdForward,
WILL_FIRE_RL_coreFix_memExe_doRespLdMem,
WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon,
WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon,
WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon,
WILL_FIRE_RL_coreFix_memExe_sendLdToMem,
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem,
WILL_FIRE_RL_coreFix_memExe_sendStToMem,
WILL_FIRE_RL_csrInstOrInterruptInflight_canon,
WILL_FIRE_RL_csrf_incCycle,
WILL_FIRE_RL_csrf_mcycle_ehr_data_canon,
WILL_FIRE_RL_csrf_mcycle_ehr_setRead,
WILL_FIRE_RL_csrf_minstret_ehr_data_canon,
WILL_FIRE_RL_csrf_minstret_ehr_setRead,
WILL_FIRE_RL_flushBrPred,
WILL_FIRE_RL_flushCaches,
WILL_FIRE_RL_mkConnectionGetPut,
WILL_FIRE_RL_mkConnectionGetPut_1,
WILL_FIRE_RL_mmio_cRqQ_canonicalize,
WILL_FIRE_RL_mmio_cRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_canonicalize,
WILL_FIRE_RL_mmio_cRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_cRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_cRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_canonicalize,
WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_canonicalize,
WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_canonicalize,
WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon,
WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon,
WILL_FIRE_RL_mmio_handlePRq,
WILL_FIRE_RL_mmio_pRqQ_canonicalize,
WILL_FIRE_RL_mmio_pRqQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRqQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRqQ_enqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_canonicalize,
WILL_FIRE_RL_mmio_pRsQ_clearReq_canon,
WILL_FIRE_RL_mmio_pRsQ_deqReq_canon,
WILL_FIRE_RL_mmio_pRsQ_enqReq_canon,
WILL_FIRE_RL_mmio_sendDataReq,
WILL_FIRE_RL_mmio_sendDataResp,
WILL_FIRE_RL_mmio_sendInstReq,
WILL_FIRE_RL_mmio_sendInstResp,
WILL_FIRE_RL_prepareCachesAndTlbs,
WILL_FIRE_RL_readyToFetch,
WILL_FIRE_RL_renameStage_doRenaming,
WILL_FIRE_RL_renameStage_doRenaming_SystemInst,
WILL_FIRE_RL_renameStage_doRenaming_Trap,
WILL_FIRE_RL_renameStage_doRenaming_wrongPath,
WILL_FIRE_RL_rl_debug_csr_access_busy,
WILL_FIRE_RL_rl_debug_csr_read,
WILL_FIRE_RL_rl_debug_csr_write,
WILL_FIRE_RL_rl_debug_fpr_access_busy,
WILL_FIRE_RL_rl_debug_fpr_read,
WILL_FIRE_RL_rl_debug_fpr_write,
WILL_FIRE_RL_rl_debug_gpr_access_busy,
WILL_FIRE_RL_rl_debug_gpr_read,
WILL_FIRE_RL_rl_debug_gpr_write,
WILL_FIRE_RL_rl_debug_halt_req,
WILL_FIRE_RL_rl_debug_halt_req_already_halted,
WILL_FIRE_RL_rl_debug_halted,
WILL_FIRE_RL_rl_debug_resume,
WILL_FIRE_RL_rl_debug_run_redundant,
WILL_FIRE_RL_rl_outOfReset,
WILL_FIRE_RL_sendDTlbReq,
WILL_FIRE_RL_sendFlushDone,
WILL_FIRE_RL_sendITlbReq,
WILL_FIRE_RL_sendRobEnqTime,
WILL_FIRE_RL_sendRsToDTlb,
WILL_FIRE_RL_sendRsToITlb,
WILL_FIRE_RL_setDoFlushBrPred,
WILL_FIRE_RL_setDoFlushCaches,
WILL_FIRE_coreIndInv_perfResp,
WILL_FIRE_coreIndInv_terminate,
WILL_FIRE_coreReq_perfReq,
WILL_FIRE_coreReq_start,
WILL_FIRE_dCacheToParent_fromP_enq,
WILL_FIRE_dCacheToParent_rqToP_deq,
WILL_FIRE_dCacheToParent_rsToP_deq,
WILL_FIRE_deadlock_checkStarted_get,
WILL_FIRE_deadlock_commitInstStuck_get,
WILL_FIRE_deadlock_commitUserInstStuck_get,
WILL_FIRE_deadlock_dCacheCRqStuck_get,
WILL_FIRE_deadlock_dCachePRqStuck_get,
WILL_FIRE_deadlock_iCacheCRqStuck_get,
WILL_FIRE_deadlock_iCachePRqStuck_get,
WILL_FIRE_deadlock_renameCorrectPathStuck_get,
WILL_FIRE_deadlock_renameInstStuck_get,
WILL_FIRE_hart0_csr_mem_server_request_put,
WILL_FIRE_hart0_csr_mem_server_response_get,
WILL_FIRE_hart0_fpr_mem_server_request_put,
WILL_FIRE_hart0_fpr_mem_server_response_get,
WILL_FIRE_hart0_gpr_mem_server_request_put,
WILL_FIRE_hart0_gpr_mem_server_response_get,
WILL_FIRE_hart0_run_halt_server_request_put,
WILL_FIRE_hart0_run_halt_server_response_get,
WILL_FIRE_iCacheToParent_fromP_enq,
WILL_FIRE_iCacheToParent_rqToP_deq,
WILL_FIRE_iCacheToParent_rsToP_deq,
WILL_FIRE_mmioToPlatform_cRq_deq,
WILL_FIRE_mmioToPlatform_cRs_deq,
WILL_FIRE_mmioToPlatform_pRq_enq,
WILL_FIRE_mmioToPlatform_pRs_enq,
WILL_FIRE_mmioToPlatform_setTime,
WILL_FIRE_recvDoStats,
WILL_FIRE_renameDebug_renameErr_get,
WILL_FIRE_sendDoStats,
WILL_FIRE_setMEIP,
WILL_FIRE_setSEIP,
WILL_FIRE_tlbToMem_memReq_deq,
WILL_FIRE_tlbToMem_respLd_enq,
WILL_FIRE_v_to_TV_0_get,
WILL_FIRE_v_to_TV_1_get;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_coreFix_memExe_lsq$respLd_2__VAL_1,
MUX_coreFix_memExe_lsq$respLd_2__VAL_2,
MUX_fetchStage$redirect_1__VAL_6;
reg [4 : 0] MUX_coreFix_memExe_lsq$respLd_1__VAL_1,
MUX_coreFix_memExe_lsq$respLd_1__VAL_2;
reg [1 : 0] MUX_csrf_fs_reg$write_1__VAL_2, MUX_csrf_fs_reg$write_1__VAL_3;
wire [583 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
wire [579 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2;
wire [569 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
wire [319 : 0] MUX_v_f_to_TV_0$enq_1__VAL_1;
wire [282 : 0] MUX_rob$enqPort_0_enq_1__VAL_1,
MUX_rob$enqPort_0_enq_1__VAL_2,
MUX_rob$enqPort_0_enq_1__VAL_3;
wire [161 : 0] MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2;
wire [160 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
wire [159 : 0] MUX_coreFix_trainBPQ_0$enq_1__VAL_1,
MUX_coreFix_trainBPQ_0$enq_1__VAL_2,
MUX_coreFix_trainBPQ_1$enq_1__VAL_1,
MUX_coreFix_trainBPQ_1$enq_1__VAL_2;
wire [152 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2;
wire [142 : 0] MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1,
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2;
wire [133 : 0] MUX_commitStage_commitTrap$write_1__VAL_2;
wire [69 : 0] MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1;
wire [67 : 0] MUX_coreFix_memExe_lsq$issueLd_4__VAL_1;
wire [64 : 0] MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3,
MUX_f_csr_rsps$enq_1__VAL_3,
MUX_f_fpr_rsps$enq_1__VAL_3;
wire [63 : 0] MUX_commitStage_rg_serialnum$write_1__VAL_1,
MUX_commitStage_rg_serialnum$write_1__VAL_2,
MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1,
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2,
MUX_csrf_mtval_csr$write_1__VAL_1,
MUX_csrf_mtval_csr$write_1__VAL_2,
MUX_csrf_rg_dcsr$write_1__VAL_2,
MUX_csrf_sepc_csr$write_1__VAL_1,
MUX_csrf_stval_csr$write_1__VAL_1,
MUX_fetchStage$redirect_1__VAL_1,
MUX_rf$write_2_wr_2__VAL_1,
MUX_rf$write_2_wr_2__VAL_3,
MUX_rf$write_2_wr_2__VAL_4,
MUX_rf$write_2_wr_2__VAL_5,
MUX_rf$write_2_wr_2__VAL_6,
MUX_rf$write_3_wr_2__VAL_3,
MUX_rf$write_3_wr_2__VAL_4;
wire [58 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
wire [57 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
wire [48 : 0] MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1,
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1;
wire [29 : 0] MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1,
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2;
wire [26 : 0] MUX_regRenamingTable$rename_0_getRename_1__VAL_2,
MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
wire [7 : 0] MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
wire [5 : 0] MUX_coreFix_memExe_lsq$getHit_1__VAL_1;
wire [4 : 0] MUX_csrf_fflags_reg$write_1__VAL_1,
MUX_rob$setExecuted_deqLSQ_2__VAL_2,
MUX_rob$setExecuted_deqLSQ_2__VAL_6,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3,
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4;
wire [3 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2;
wire [2 : 0] MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1,
MUX_csrf_frm_reg$write_1__VAL_1,
MUX_csrf_frm_reg$write_1__VAL_2;
wire [1 : 0] MUX_csrf_mpp_reg$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__VAL_2;
wire MUX_commitStage_rg_run_state$write_1__SEL_1,
MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1,
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3,
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1,
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1,
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1,
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2,
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2,
MUX_coreFix_memExe_lsq$getHit_1__SEL_1,
MUX_coreFix_memExe_lsq$getHit_1__SEL_2,
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1,
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1,
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1,
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2,
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1,
MUX_coreFix_trainBPQ_0$enq_1__SEL_1,
MUX_coreFix_trainBPQ_1$enq_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1,
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2,
MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1,
MUX_csrf_external_int_en_vec_0$write_1__SEL_1,
MUX_csrf_external_int_en_vec_3$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_0$write_1__SEL_2,
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1,
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2,
MUX_csrf_fflags_reg$write_1__SEL_1,
MUX_csrf_fflags_reg$write_1__SEL_2,
MUX_csrf_fflags_reg$write_1__SEL_3,
MUX_csrf_frm_reg$write_1__SEL_1,
MUX_csrf_fs_reg$write_1__SEL_2,
MUX_csrf_fs_reg$write_1__SEL_3,
MUX_csrf_ie_vec_0$write_1__SEL_1,
MUX_csrf_ie_vec_0$write_1__SEL_2,
MUX_csrf_ie_vec_1$write_1__SEL_1,
MUX_csrf_ie_vec_1$write_1__SEL_2,
MUX_csrf_ie_vec_1$write_1__VAL_1,
MUX_csrf_ie_vec_3$write_1__SEL_1,
MUX_csrf_ie_vec_3$write_1__SEL_2,
MUX_csrf_ie_vec_3$write_1__SEL_3,
MUX_csrf_ie_vec_3$write_1__VAL_1,
MUX_csrf_mcause_code_reg$write_1__SEL_1,
MUX_csrf_mcause_code_reg$write_1__SEL_3,
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1,
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1,
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2,
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1,
MUX_csrf_mepc_csr$write_1__SEL_1,
MUX_csrf_mepc_csr$write_1__SEL_3,
MUX_csrf_mideleg_11_reg$write_1__SEL_1,
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1,
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2,
MUX_csrf_mpp_reg$write_1__SEL_1,
MUX_csrf_mscratch_csr$write_1__SEL_1,
MUX_csrf_mtval_csr$write_1__SEL_1,
MUX_csrf_mtval_csr$write_1__SEL_3,
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1,
MUX_csrf_ppn_reg$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__SEL_1,
MUX_csrf_prev_ie_vec_1$write_1__VAL_1,
MUX_csrf_prev_ie_vec_3$write_1__SEL_1,
MUX_csrf_prev_ie_vec_3$write_1__VAL_1,
MUX_csrf_prv_reg$write_1__SEL_1,
MUX_csrf_prv_reg$write_1__SEL_2,
MUX_csrf_prv_reg$write_1__SEL_3,
MUX_csrf_rg_dcsr$write_1__SEL_1,
MUX_csrf_rg_dpc$write_1__SEL_1,
MUX_csrf_rg_dpc$write_1__SEL_3,
MUX_csrf_rg_dscratch0$write_1__SEL_1,
MUX_csrf_rg_dscratch1$write_1__SEL_1,
MUX_csrf_scause_code_reg$write_1__SEL_1,
MUX_csrf_scause_code_reg$write_1__SEL_3,
MUX_csrf_scounteren_cy_reg$write_1__SEL_1,
MUX_csrf_sepc_csr$write_1__SEL_1,
MUX_csrf_sepc_csr$write_1__SEL_3,
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2,
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2,
MUX_csrf_spp_reg$write_1__SEL_1,
MUX_csrf_spp_reg$write_1__VAL_1,
MUX_csrf_sscratch_csr$write_1__SEL_1,
MUX_csrf_stats_module_writeQ$enq_1__SEL_1,
MUX_csrf_stval_csr$write_1__SEL_1,
MUX_csrf_stval_csr$write_1__SEL_3,
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1,
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2,
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2,
MUX_flush_reservation$write_1__SEL_2,
MUX_flush_tlbs$write_1__SEL_1,
MUX_regRenamingTable$rename_0_getRename_1__SEL_1,
MUX_regRenamingTable$rename_0_getRename_1__SEL_2,
MUX_regRenamingTable$rename_0_getRename_1__SEL_3,
MUX_renameStage_rg_m_halt_req$write_1__PSEL_1,
MUX_renameStage_rg_m_halt_req$write_1__SEL_1,
MUX_renameStage_rg_m_halt_req$write_1__SEL_2,
MUX_rf$write_3_wr_1__PSEL_5,
MUX_rf$write_3_wr_1__SEL_1,
MUX_rf$write_3_wr_1__SEL_2,
MUX_rf$write_3_wr_1__SEL_3,
MUX_rf$write_3_wr_1__SEL_4,
MUX_rf$write_3_wr_1__SEL_5,
MUX_rf$write_3_wr_2__SEL_5,
MUX_rg_core_run_state$write_1__SEL_4,
MUX_rob$setExecuted_deqLSQ_1__SEL_1,
MUX_sbAggr$setReady_4_put_1__SEL_1,
MUX_sbAggr$setReady_4_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_1,
MUX_sbCons$setReady_3_put_1__SEL_2,
MUX_sbCons$setReady_3_put_1__SEL_3,
MUX_started$write_1__SEL_1,
MUX_v_f_to_TV_0$enq_1__SEL_1;
// remaining internal signals
reg [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496;
reg [63 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q291,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871,
addr__h287914,
curData__h190763,
data_out__h718171,
rVal1__h606861,
rVal1__h631001,
trap_val__h699101,
x__h194973;
reg [51 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19,
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217,
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218,
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219,
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220,
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205,
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206,
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207,
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208,
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209,
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210,
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221,
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222,
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223,
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224,
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225,
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226,
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215,
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871;
reg [31 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398;
reg [22 : 0] CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86,
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87,
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88,
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89,
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119,
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120,
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49,
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50,
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117,
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118,
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47,
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48,
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121,
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122,
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51,
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52,
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123,
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124,
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54,
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55,
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84,
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85,
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82,
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83,
_theResult___fst_sfd__h343912,
_theResult___fst_sfd__h352635,
_theResult___fst_sfd__h361217,
_theResult___fst_sfd__h370401,
_theResult___fst_sfd__h379037,
_theResult___fst_sfd__h389611,
_theResult___fst_sfd__h398332,
_theResult___fst_sfd__h406914,
_theResult___fst_sfd__h416098,
_theResult___fst_sfd__h424734,
_theResult___fst_sfd__h435306,
_theResult___fst_sfd__h444027,
_theResult___fst_sfd__h452609,
_theResult___fst_sfd__h461793,
_theResult___fst_sfd__h470429;
reg [20 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q281,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q287,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826,
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510;
reg [15 : 0] SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407;
reg [11 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q288,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285,
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235,
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q274,
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296,
CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5,
CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1,
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908;
reg [10 : 0] CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18,
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211,
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212,
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213,
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214,
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183,
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184,
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185,
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186,
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187,
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188,
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160,
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161,
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191,
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192,
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189,
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190,
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143,
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800;
reg [7 : 0] CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75,
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76,
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80,
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81,
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104,
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105,
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34,
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35,
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102,
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103,
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32,
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33,
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110,
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111,
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40,
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41,
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115,
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116,
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45,
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46,
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69,
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70,
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67,
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420,
_theResult___fst_exp__h343911,
_theResult___fst_exp__h352634,
_theResult___fst_exp__h361216,
_theResult___fst_exp__h370400,
_theResult___fst_exp__h379036,
_theResult___fst_exp__h389610,
_theResult___fst_exp__h398331,
_theResult___fst_exp__h406913,
_theResult___fst_exp__h416097,
_theResult___fst_exp__h424733,
_theResult___fst_exp__h435305,
_theResult___fst_exp__h444026,
_theResult___fst_exp__h452608,
_theResult___fst_exp__h461792,
_theResult___fst_exp__h470428;
reg [5 : 0] CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q276,
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q271,
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674;
reg [4 : 0] IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045,
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176;
reg [3 : 0] CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234,
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20,
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q273,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q272,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251,
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252,
CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6,
CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7,
CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2,
CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048,
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062,
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177,
i__h698077,
i__h698237;
reg [2 : 0] CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q280,
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230,
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q277,
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q286,
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227,
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q283,
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q293,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253,
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q289,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265,
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714,
x__h283692,
x__h289463;
reg [1 : 0] CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259,
CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q275,
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q297,
CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8,
CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4;
reg CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260,
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243,
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244,
CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241,
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238,
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242,
CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147,
CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95,
CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94,
CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149,
CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97,
CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96,
CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203,
CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193,
CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125,
CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126,
CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199,
CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195,
CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56,
CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53,
CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128,
CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127,
CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201,
CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197,
CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58,
CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57,
CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131,
CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129,
CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60,
CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59,
CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132,
CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130,
CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172,
CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164,
CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62,
CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61,
CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168,
CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162,
CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170,
CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166,
CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91,
CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90,
CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145,
CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93,
CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92,
CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10851,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10887,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10935,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10977,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11019,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973,
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174,
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175,
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819,
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958,
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985,
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408,
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919,
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374,
SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689;
wire [581 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243;
wire [569 : 0] IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518;
wire [517 : 0] SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941;
wire [511 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578;
wire [447 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004;
wire [383 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569;
wire [321 : 0] basicExec___d11911, basicExec___d12557;
wire [319 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999;
wire [255 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560;
wire [191 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994;
wire [68 : 0] execFpuSimple___d11053;
wire [65 : 0] IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627;
wire [64 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566;
wire [63 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9170,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8355,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659,
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10651,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9881,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9937,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563,
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377,
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424,
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378,
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425,
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8,
_theResult___fst__h601214,
_theResult___snd__h601215,
a___1__h600933,
a___1__h601219,
a__h600792,
amoExec___d880,
b___1__h600934,
b___1__h601264,
b__h600793,
base__h700680,
base__h700883,
data___1__h472852,
data___1__h473660,
data__h473126,
fcsr_csr__read__h607163,
fflags_csr__read__h607138,
frm_csr__read__h607149,
mcause_csr__read__h608803,
mcounteren_csr__read__h608548,
medeleg_csr__read__h608155,
mideleg_csr__read__h608250,
mie_csr__read__h608374,
mip_csr__read__h609036,
mstatus_csr__read__h608007,
mtvec_csr__read__h608456,
n___1__h196376,
n__h192301,
n__read__h609140,
n__read__h609331,
n__read__h6604,
n__read__h709918,
next_pc__h709264,
q___1__h473725,
rVal1__h479605,
rVal2__h479606,
r___1__h473751,
res_data__h335713,
res_data__h335718,
res_data__h381415,
res_data__h381420,
res_data__h427110,
res_data__h427115,
resp_addr__h289818,
robdeqPort_0_deq_data_BITS_95_TO_32__q270,
satp_csr__read__h607864,
scause_csr__read__h607662,
scounteren_csr__read__h607524,
shiftData__h181140,
sie_csr__read__h607428,
sip_csr__read__h607801,
sstatus_csr__read__h607359,
stvec_csr__read__h607471,
upd__h3992,
upd__h5309,
upd__h6718,
upd__h710029,
v__h605746,
v__h630040,
vaddr__h181135,
x__h153450,
x__h156997,
x__h159811,
x__h161659,
x__h181049,
x__h181050,
x__h18170,
x__h20708,
x__h285138,
x__h286992,
x__h46077,
x__h479514,
x__h479515,
x__h479516,
x__h48613,
x__h614524,
x__h614525,
x__h636385,
x__h636386,
x__h692236,
x__h712697,
x_addr__h311921,
x_quotient__h473040,
x_reg_ifc__read__h607268,
x_remainder__h473041,
y__h712723,
y__h714114,
y_avValue__h180137,
y_avValue__h180743,
y_avValue__h476650,
y_avValue__h477258,
y_avValue__h477860,
y_avValue__h606651,
y_avValue__h612381,
y_avValue__h630793,
y_avValue__h634252,
y_avValue__h698948,
y_avValue__h700717,
y_avValue_snd_snd_snd_snd_snd__h712738,
y_avValue_snd_snd_snd_snd_snd__h714163,
y_avValue_snd_snd_snd_snd_snd__h714192;
wire [62 : 0] IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879,
r1__read__h610308,
r1__read__h610712,
r1__read__h611242,
r1__read__h611247,
r1__read__h611266,
r1__read__h611519,
r1__read__h611685,
r1__read__h611796,
r1__read__h611801,
r1__read__h611820;
wire [61 : 0] r1__read__h610310,
r1__read__h610714,
r1__read__h611249,
r1__read__h611268,
r1__read__h611521,
r1__read__h611661,
r1__read__h611687,
r1__read__h611803,
r1__read__h611822;
wire [60 : 0] r1__read__h611523,
r1__read__h611663,
r1__read__h611689,
r1__read__h611824;
wire [59 : 0] r1__read__h610312,
r1__read__h610716,
r1__read__h611260,
r1__read__h611270,
r1__read__h611525,
r1__read__h611691,
r1__read__h611814,
r1__read__h611826;
wire [58 : 0] r1__read__h610314,
r1__read__h610718,
r1__read__h611272,
r1__read__h611527,
r1__read__h611693,
r1__read__h611828;
wire [57 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709,
r1__read__h610316,
r1__read__h610720,
r1__read__h611274,
r1__read__h611529,
r1__read__h611665,
r1__read__h611695,
r1__read__h611830,
y__h252650;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63,
IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174,
IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65,
IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650,
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946,
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338,
_theResult____h343929,
_theResult____h361568,
_theResult____h389628,
_theResult____h407265,
_theResult____h435323,
_theResult____h452960,
_theResult____h500713,
_theResult____h539566,
_theResult____h578870,
_theResult___snd__h352051,
_theResult___snd__h352062,
_theResult___snd__h352064,
_theResult___snd__h352074,
_theResult___snd__h352080,
_theResult___snd__h352103,
_theResult___snd__h360647,
_theResult___snd__h360649,
_theResult___snd__h360656,
_theResult___snd__h360662,
_theResult___snd__h360685,
_theResult___snd__h369817,
_theResult___snd__h369828,
_theResult___snd__h369830,
_theResult___snd__h369840,
_theResult___snd__h369846,
_theResult___snd__h369869,
_theResult___snd__h378437,
_theResult___snd__h378451,
_theResult___snd__h378457,
_theResult___snd__h378475,
_theResult___snd__h397748,
_theResult___snd__h397759,
_theResult___snd__h397761,
_theResult___snd__h397771,
_theResult___snd__h397777,
_theResult___snd__h397800,
_theResult___snd__h406344,
_theResult___snd__h406346,
_theResult___snd__h406353,
_theResult___snd__h406359,
_theResult___snd__h406382,
_theResult___snd__h415514,
_theResult___snd__h415525,
_theResult___snd__h415527,
_theResult___snd__h415537,
_theResult___snd__h415543,
_theResult___snd__h415566,
_theResult___snd__h424134,
_theResult___snd__h424148,
_theResult___snd__h424154,
_theResult___snd__h424172,
_theResult___snd__h443443,
_theResult___snd__h443454,
_theResult___snd__h443456,
_theResult___snd__h443466,
_theResult___snd__h443472,
_theResult___snd__h443495,
_theResult___snd__h452039,
_theResult___snd__h452041,
_theResult___snd__h452048,
_theResult___snd__h452054,
_theResult___snd__h452077,
_theResult___snd__h461209,
_theResult___snd__h461220,
_theResult___snd__h461222,
_theResult___snd__h461232,
_theResult___snd__h461238,
_theResult___snd__h461261,
_theResult___snd__h469829,
_theResult___snd__h469843,
_theResult___snd__h469849,
_theResult___snd__h469867,
_theResult___snd__h499323,
_theResult___snd__h499325,
_theResult___snd__h499332,
_theResult___snd__h499338,
_theResult___snd__h499361,
_theResult___snd__h508960,
_theResult___snd__h508971,
_theResult___snd__h508973,
_theResult___snd__h508983,
_theResult___snd__h508989,
_theResult___snd__h509012,
_theResult___snd__h517728,
_theResult___snd__h517742,
_theResult___snd__h517748,
_theResult___snd__h517766,
_theResult___snd__h538176,
_theResult___snd__h538178,
_theResult___snd__h538185,
_theResult___snd__h538191,
_theResult___snd__h538214,
_theResult___snd__h547813,
_theResult___snd__h547824,
_theResult___snd__h547826,
_theResult___snd__h547836,
_theResult___snd__h547842,
_theResult___snd__h547865,
_theResult___snd__h556581,
_theResult___snd__h556595,
_theResult___snd__h556601,
_theResult___snd__h556619,
_theResult___snd__h577480,
_theResult___snd__h577482,
_theResult___snd__h577489,
_theResult___snd__h577495,
_theResult___snd__h577518,
_theResult___snd__h587117,
_theResult___snd__h587128,
_theResult___snd__h587130,
_theResult___snd__h587140,
_theResult___snd__h587146,
_theResult___snd__h587169,
_theResult___snd__h595885,
_theResult___snd__h595899,
_theResult___snd__h595905,
_theResult___snd__h595923,
r1__read__h611531,
r1__read__h611667,
r1__read__h611697,
r1__read__h611832,
result__h362181,
result__h407878,
result__h453573,
result__h501326,
result__h540179,
result__h579483,
sfd__h336324,
sfd__h382026,
sfd__h427721,
sfd__h480346,
sfd__h519340,
sfd__h558644,
sfdin__h352034,
sfdin__h369800,
sfdin__h397731,
sfdin__h415497,
sfdin__h443426,
sfdin__h461192,
sfdin__h508943,
sfdin__h547796,
sfdin__h587100,
x__h362278,
x__h407975,
x__h453670,
x__h501421,
x__h540274,
x__h579578;
wire [55 : 0] r1__read__h610318,
r1__read__h610722,
r1__read__h611276,
r1__read__h611533,
r1__read__h611699,
r1__read__h611834;
wire [54 : 0] r1__read__h610320,
r1__read__h610724,
r1__read__h611278,
r1__read__h611535,
r1__read__h611701,
r1__read__h611836;
wire [53 : 0] r1__read__h611644,
r1__read__h611669,
r1__read__h611703,
r1__read__h611838,
sfd__h499390,
sfd__h509041,
sfd__h517801,
sfd__h538243,
sfd__h547894,
sfd__h556654,
sfd__h577547,
sfd__h587198,
sfd__h595958,
value__h344551,
value__h390248,
value__h435943;
wire [52 : 0] r1__read__h611537,
r1__read__h611646,
r1__read__h611671,
r1__read__h611705,
r1__read__h611840;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878,
_theResult___fst_sfd__h484300,
_theResult___fst_sfd__h500128,
_theResult___fst_sfd__h500131,
_theResult___fst_sfd__h509779,
_theResult___fst_sfd__h509782,
_theResult___fst_sfd__h518563,
_theResult___fst_sfd__h518566,
_theResult___fst_sfd__h518575,
_theResult___fst_sfd__h518581,
_theResult___fst_sfd__h523153,
_theResult___fst_sfd__h538981,
_theResult___fst_sfd__h538984,
_theResult___fst_sfd__h548632,
_theResult___fst_sfd__h548635,
_theResult___fst_sfd__h557416,
_theResult___fst_sfd__h557419,
_theResult___fst_sfd__h557428,
_theResult___fst_sfd__h557434,
_theResult___fst_sfd__h562457,
_theResult___fst_sfd__h578285,
_theResult___fst_sfd__h578288,
_theResult___fst_sfd__h587936,
_theResult___fst_sfd__h587939,
_theResult___fst_sfd__h596720,
_theResult___fst_sfd__h596723,
_theResult___fst_sfd__h596732,
_theResult___fst_sfd__h596738,
_theResult___sfd__h500028,
_theResult___sfd__h509679,
_theResult___sfd__h518463,
_theResult___sfd__h538881,
_theResult___sfd__h548532,
_theResult___sfd__h557316,
_theResult___sfd__h578185,
_theResult___sfd__h587836,
_theResult___sfd__h596620,
_theResult___snd_fst_sfd__h480300,
_theResult___snd_fst_sfd__h500134,
_theResult___snd_fst_sfd__h518569,
_theResult___snd_fst_sfd__h519294,
_theResult___snd_fst_sfd__h538987,
_theResult___snd_fst_sfd__h557422,
_theResult___snd_fst_sfd__h558598,
_theResult___snd_fst_sfd__h578291,
_theResult___snd_fst_sfd__h596726,
out___1_sfd__h480048,
out___1_sfd__h519042,
out___1_sfd__h558346,
out_sfd__h500031,
out_sfd__h509682,
out_sfd__h518466,
out_sfd__h538884,
out_sfd__h548535,
out_sfd__h557319,
out_sfd__h578188,
out_sfd__h587839,
out_sfd__h596623;
wire [50 : 0] r1__read__h610322, r1__read__h611539;
wire [49 : 0] r1__read__h611648;
wire [48 : 0] r1__read__h610324, r1__read__h611541, r1__read__h611650;
wire [46 : 0] r1__read__h610326, r1__read__h611543;
wire [45 : 0] r1__read__h610328, r1__read__h611545;
wire [44 : 0] r1__read__h610330, r1__read__h611547;
wire [43 : 0] r1__read__h610332, r1__read__h611549;
wire [42 : 0] r1__read__h611551;
wire [41 : 0] r1__read__h611553;
wire [40 : 0] r1__read__h611555;
wire [37 : 0] IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051,
IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180;
wire [31 : 0] IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11,
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10,
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12,
data73126_BITS_31_TO_0__q13,
imm__h651906,
r1__read__h610334,
r1__read__h611557,
x__h191526,
x__h335728,
x__h381430,
x__h427125,
x__h76022,
x_data__h65871,
x_data_imm__h671051,
x_data_imm__h685982;
wire [29 : 0] r1__read__h610336, r1__read__h611559;
wire [27 : 0] r1__read__h611561;
wire [24 : 0] NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083,
sfd__h352132,
sfd__h360714,
sfd__h369898,
sfd__h378510,
sfd__h397829,
sfd__h406411,
sfd__h415595,
sfd__h424207,
sfd__h443524,
sfd__h452106,
sfd__h461290,
sfd__h469902,
value__h484929,
value__h523782,
value__h563086;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804,
_theResult___fst_sfd__h352638,
_theResult___fst_sfd__h361220,
_theResult___fst_sfd__h370404,
_theResult___fst_sfd__h379040,
_theResult___fst_sfd__h379049,
_theResult___fst_sfd__h379055,
_theResult___fst_sfd__h398335,
_theResult___fst_sfd__h406917,
_theResult___fst_sfd__h416101,
_theResult___fst_sfd__h424737,
_theResult___fst_sfd__h424746,
_theResult___fst_sfd__h424752,
_theResult___fst_sfd__h444030,
_theResult___fst_sfd__h452612,
_theResult___fst_sfd__h461796,
_theResult___fst_sfd__h470432,
_theResult___fst_sfd__h470441,
_theResult___fst_sfd__h470447,
_theResult___sfd__h352557,
_theResult___sfd__h361139,
_theResult___sfd__h370323,
_theResult___sfd__h378959,
_theResult___sfd__h379061,
_theResult___sfd__h398254,
_theResult___sfd__h406836,
_theResult___sfd__h416020,
_theResult___sfd__h424656,
_theResult___sfd__h424758,
_theResult___sfd__h443949,
_theResult___sfd__h452531,
_theResult___sfd__h461715,
_theResult___sfd__h470351,
_theResult___sfd__h470453,
_theResult___snd_fst_sfd__h336274,
_theResult___snd_fst_sfd__h361223,
_theResult___snd_fst_sfd__h379043,
_theResult___snd_fst_sfd__h381976,
_theResult___snd_fst_sfd__h406920,
_theResult___snd_fst_sfd__h424740,
_theResult___snd_fst_sfd__h427671,
_theResult___snd_fst_sfd__h452615,
_theResult___snd_fst_sfd__h470435,
f1_sfd__h479985,
f2_sfd__h518979,
f3_sfd__h558283,
out_f_sfd__h379338,
out_f_sfd__h425035,
out_f_sfd__h470730,
out_sfd__h352560,
out_sfd__h361142,
out_sfd__h370326,
out_sfd__h378962,
out_sfd__h398257,
out_sfd__h406839,
out_sfd__h416023,
out_sfd__h424659,
out_sfd__h443952,
out_sfd__h452534,
out_sfd__h461718,
out_sfd__h470354;
wire [19 : 0] r1__read__h611496;
wire [15 : 0] IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767,
_theResult____h647726,
enabled_ints___1__h648251,
enabled_ints__h648298,
pend_ints__h647724,
y__h648263;
wire [13 : 0] r1__read_BITS_13_TO_0___h648274;
wire [12 : 0] fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594;
wire [11 : 0] IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658,
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638,
IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107,
_0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646,
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10006,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8506,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9236,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942,
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334,
renaming_spec_bits__h678574,
result__h643303,
result__h643354,
spec_bits__h681701,
w__h643298,
x__h362311,
x__h408008,
x__h453703,
x__h501454,
x__h540307,
x__h579611,
x__h643302,
x__h643353,
y__h643332,
y__h681714,
y_avValue_fst__h674974,
y_avValue_fst__h675003,
y_avValue_fst__h675037;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794,
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180,
_theResult___exp__h500027,
_theResult___exp__h509678,
_theResult___exp__h518462,
_theResult___exp__h538880,
_theResult___exp__h548531,
_theResult___exp__h557315,
_theResult___exp__h578184,
_theResult___exp__h587835,
_theResult___exp__h596619,
_theResult___fst_exp__h484299,
_theResult___fst_exp__h499363,
_theResult___fst_exp__h499369,
_theResult___fst_exp__h499372,
_theResult___fst_exp__h500127,
_theResult___fst_exp__h500130,
_theResult___fst_exp__h508949,
_theResult___fst_exp__h509014,
_theResult___fst_exp__h509020,
_theResult___fst_exp__h509023,
_theResult___fst_exp__h509778,
_theResult___fst_exp__h509781,
_theResult___fst_exp__h517734,
_theResult___fst_exp__h517773,
_theResult___fst_exp__h517779,
_theResult___fst_exp__h517782,
_theResult___fst_exp__h518562,
_theResult___fst_exp__h518565,
_theResult___fst_exp__h518574,
_theResult___fst_exp__h518577,
_theResult___fst_exp__h523152,
_theResult___fst_exp__h538216,
_theResult___fst_exp__h538222,
_theResult___fst_exp__h538225,
_theResult___fst_exp__h538980,
_theResult___fst_exp__h538983,
_theResult___fst_exp__h547802,
_theResult___fst_exp__h547867,
_theResult___fst_exp__h547873,
_theResult___fst_exp__h547876,
_theResult___fst_exp__h548631,
_theResult___fst_exp__h548634,
_theResult___fst_exp__h556587,
_theResult___fst_exp__h556626,
_theResult___fst_exp__h556632,
_theResult___fst_exp__h556635,
_theResult___fst_exp__h557415,
_theResult___fst_exp__h557418,
_theResult___fst_exp__h557427,
_theResult___fst_exp__h557430,
_theResult___fst_exp__h562456,
_theResult___fst_exp__h577520,
_theResult___fst_exp__h577526,
_theResult___fst_exp__h577529,
_theResult___fst_exp__h578284,
_theResult___fst_exp__h578287,
_theResult___fst_exp__h587106,
_theResult___fst_exp__h587171,
_theResult___fst_exp__h587177,
_theResult___fst_exp__h587180,
_theResult___fst_exp__h587935,
_theResult___fst_exp__h587938,
_theResult___fst_exp__h595891,
_theResult___fst_exp__h595930,
_theResult___fst_exp__h595936,
_theResult___fst_exp__h595939,
_theResult___fst_exp__h596719,
_theResult___fst_exp__h596722,
_theResult___fst_exp__h596731,
_theResult___fst_exp__h596734,
_theResult___snd_fst_exp__h500133,
_theResult___snd_fst_exp__h518568,
_theResult___snd_fst_exp__h538986,
_theResult___snd_fst_exp__h557421,
_theResult___snd_fst_exp__h578290,
_theResult___snd_fst_exp__h596725,
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71,
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106,
din_inc___2_exp__h518622,
din_inc___2_exp__h518657,
din_inc___2_exp__h518683,
din_inc___2_exp__h557475,
din_inc___2_exp__h557510,
din_inc___2_exp__h557536,
din_inc___2_exp__h596779,
din_inc___2_exp__h596814,
din_inc___2_exp__h596840,
out_exp__h500030,
out_exp__h509681,
out_exp__h518465,
out_exp__h538883,
out_exp__h548534,
out_exp__h557318,
out_exp__h578187,
out_exp__h587838,
out_exp__h596622;
wire [8 : 0] IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090,
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637,
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706,
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112,
_0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735,
_theResult___exp__h352556,
_theResult___exp__h361138,
_theResult___exp__h370322,
_theResult___exp__h378958,
_theResult___exp__h379060,
_theResult___exp__h398253,
_theResult___exp__h406835,
_theResult___exp__h416019,
_theResult___exp__h424655,
_theResult___exp__h424757,
_theResult___exp__h443948,
_theResult___exp__h452530,
_theResult___exp__h461714,
_theResult___exp__h470350,
_theResult___exp__h470452,
_theResult___fst_exp__h352040,
_theResult___fst_exp__h352105,
_theResult___fst_exp__h352111,
_theResult___fst_exp__h352114,
_theResult___fst_exp__h352637,
_theResult___fst_exp__h360687,
_theResult___fst_exp__h360693,
_theResult___fst_exp__h360696,
_theResult___fst_exp__h361219,
_theResult___fst_exp__h369806,
_theResult___fst_exp__h369871,
_theResult___fst_exp__h369877,
_theResult___fst_exp__h369880,
_theResult___fst_exp__h370403,
_theResult___fst_exp__h378443,
_theResult___fst_exp__h378482,
_theResult___fst_exp__h378488,
_theResult___fst_exp__h378491,
_theResult___fst_exp__h379039,
_theResult___fst_exp__h379048,
_theResult___fst_exp__h379051,
_theResult___fst_exp__h397737,
_theResult___fst_exp__h397802,
_theResult___fst_exp__h397808,
_theResult___fst_exp__h397811,
_theResult___fst_exp__h398334,
_theResult___fst_exp__h406384,
_theResult___fst_exp__h406390,
_theResult___fst_exp__h406393,
_theResult___fst_exp__h406916,
_theResult___fst_exp__h415503,
_theResult___fst_exp__h415568,
_theResult___fst_exp__h415574,
_theResult___fst_exp__h415577,
_theResult___fst_exp__h416100,
_theResult___fst_exp__h424140,
_theResult___fst_exp__h424179,
_theResult___fst_exp__h424185,
_theResult___fst_exp__h424188,
_theResult___fst_exp__h424736,
_theResult___fst_exp__h424745,
_theResult___fst_exp__h424748,
_theResult___fst_exp__h443432,
_theResult___fst_exp__h443497,
_theResult___fst_exp__h443503,
_theResult___fst_exp__h443506,
_theResult___fst_exp__h444029,
_theResult___fst_exp__h452079,
_theResult___fst_exp__h452085,
_theResult___fst_exp__h452088,
_theResult___fst_exp__h452611,
_theResult___fst_exp__h461198,
_theResult___fst_exp__h461263,
_theResult___fst_exp__h461269,
_theResult___fst_exp__h461272,
_theResult___fst_exp__h461795,
_theResult___fst_exp__h469835,
_theResult___fst_exp__h469874,
_theResult___fst_exp__h469880,
_theResult___fst_exp__h469883,
_theResult___fst_exp__h470431,
_theResult___fst_exp__h470440,
_theResult___fst_exp__h470443,
_theResult___snd_fst_exp__h361222,
_theResult___snd_fst_exp__h379042,
_theResult___snd_fst_exp__h406919,
_theResult___snd_fst_exp__h424739,
_theResult___snd_fst_exp__h452614,
_theResult___snd_fst_exp__h470434,
din_inc___2_exp__h379073,
din_inc___2_exp__h379097,
din_inc___2_exp__h379127,
din_inc___2_exp__h379151,
din_inc___2_exp__h424770,
din_inc___2_exp__h424794,
din_inc___2_exp__h424824,
din_inc___2_exp__h424848,
din_inc___2_exp__h470465,
din_inc___2_exp__h470489,
din_inc___2_exp__h470519,
din_inc___2_exp__h470543,
f1_exp79984_MINUS_127__q136,
f1_exp__h479984,
f2_exp18978_MINUS_127__q176,
f2_exp__h518978,
f3_exp58282_MINUS_127__q153,
f3_exp__h558282,
out_exp__h352559,
out_exp__h361141,
out_exp__h370325,
out_exp__h378961,
out_exp__h398256,
out_exp__h406838,
out_exp__h416022,
out_exp__h424658,
out_exp__h443951,
out_exp__h452533,
out_exp__h461717,
out_exp__h470353,
out_f_exp__h379337,
out_f_exp__h425034,
out_f_exp__h470729,
x__h610293;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310,
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604,
x__h181272,
x__h700695;
wire [4 : 0] IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221,
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961,
checkForException___d12942,
checkForException___d13615,
fflags__h714091,
res_fflags__h335714,
res_fflags__h381416,
res_fflags__h427111,
rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302,
rs1__h651905,
x__h153444,
x__h156991,
x__h159807,
x__h285126,
y_avValue_fst__h712284,
y_avValue_fst__h714006,
y_avValue_fst__h714034;
wire [3 : 0] IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855,
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141,
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142,
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175,
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791,
IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215,
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832,
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
cause_code__h698062,
vm_mode_reg__read__h611502;
wire [2 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
_theResult_____2__h294368,
dcsr_cause__h697582,
next_deqP___1__h294647,
v__h293788,
v__h294019,
x__h299998,
x_decodeInfo_frm__h651589;
wire [1 : 0] IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201,
IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139,
IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74,
IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99,
IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179,
IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29,
IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109,
IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39,
IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156,
IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64,
IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66,
IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142,
IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79,
IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175,
IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101,
IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182,
IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31,
IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114,
IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152,
IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44,
IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159,
IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135,
guard__h343939,
guard__h352648,
guard__h361578,
guard__h370414,
guard__h389638,
guard__h398345,
guard__h407275,
guard__h416111,
guard__h435333,
guard__h444040,
guard__h452970,
guard__h461806,
guard__h491411,
guard__h500723,
guard__h509792,
guard__h530264,
guard__h539576,
guard__h548645,
guard__h569568,
guard__h578880,
guard__h587949,
prv__h715726,
prv__h715770,
r1__read_BITS_13_TO_12___h651774,
sbIdx__h156870,
v__h601727,
v__h601737,
v__h602372,
x__h709324,
x__h714333,
y_avValue_snd_snd_snd_fst__h712732,
y_avValue_snd_snd_snd_fst__h714157,
y_avValue_snd_snd_snd_fst__h714186;
wire IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849,
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10421,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10688,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8936,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9651,
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9919,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10673,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10700,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8982,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9697,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9904,
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9931,
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984,
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673,
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10471,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10759,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10800,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10844,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10859,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10869,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10880,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10899,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10913,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10928,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10945,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10957,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10970,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10999,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11012,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8986,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9701,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9934,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9935,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223,
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11366,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11367,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11368,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11391,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11392,
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11393,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8239,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8240,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8262,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8263,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8264,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8286,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8287,
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8288,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627,
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082,
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099,
IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825,
IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833,
IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748,
IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832,
IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10469,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10702,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10911,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10926,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10943,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10955,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10968,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10985,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10997,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11010,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8984,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9699,
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9933,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020,
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173,
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11342,
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11376,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247,
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8271,
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035,
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136,
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10675,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9906,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156,
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104,
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424,
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840,
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844,
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578,
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611,
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746,
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739,
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724,
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652,
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645,
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630,
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554,
IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361,
IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750,
IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822,
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871,
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001,
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339,
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783,
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46,
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201,
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642,
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491,
IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001,
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029,
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272,
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348,
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642,
NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553,
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283,
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410,
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499,
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506,
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566,
NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696,
NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189,
NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217,
NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358,
NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257,
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419,
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203,
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594,
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053,
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074,
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123,
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179,
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651,
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390,
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447,
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879,
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923,
NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751,
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713,
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768,
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619,
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674,
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473,
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024,
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543,
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585,
NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078,
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265,
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346,
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640,
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168,
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198,
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261,
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392,
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663,
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669,
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830,
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014,
NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403,
NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712,
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426,
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656,
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773,
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120,
NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117,
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431,
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452,
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823,
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844,
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091,
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390,
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325,
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140,
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161,
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241,
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262,
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734,
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755,
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593,
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614,
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678,
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754,
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099,
NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718,
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034,
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353,
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653,
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795,
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813,
NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930,
NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172,
NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684,
NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927,
NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924,
NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359,
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332,
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312,
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260,
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653,
_0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845,
_0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746,
_0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937,
_0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587,
_0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5205,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5232,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6572,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989,
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237,
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239,
_dfoo12,
_dfoo16,
_dfoo18,
_dfoo2,
_dfoo20,
_dfoo24,
_dfoo26,
_dfoo32,
_dfoo7,
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset,
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset,
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put,
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset,
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset,
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put,
_dor1coreFix_memExe_bypassWire_2$EN_wset,
_dor1coreFix_memExe_bypassWire_3$EN_wset,
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset,
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write,
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset,
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put,
_dor1rf$EN_write_0_wr,
_dor1rf$EN_write_1_wr,
_dor1sbAggr$EN_setReady_3_put,
_dor1sbCons$EN_setReady_0_put,
_dor1sbCons$EN_setReady_1_put,
_theResult_____2__h302364,
_theResult_____2__h308358,
_theResult_____2__h316212,
_theResult_____2__h326556,
_theResult_____2__h329781,
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529,
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530,
coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165,
coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204,
coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178,
coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210,
coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186,
coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214,
coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227,
coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620,
coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370,
coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334,
coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373,
coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347,
coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379,
coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11355,
coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11383,
coreFix_aluExe_1_dispToRegQ_first__1311_BIT_13_ETC___d11396,
coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244,
coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250,
coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254,
coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278,
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268,
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660,
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8098,
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8101,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052,
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10849,
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10885,
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933,
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975,
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017,
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944,
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570,
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608,
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583,
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614,
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591,
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573,
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063,
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146,
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693,
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844,
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433,
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730,
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731,
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755,
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267,
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570,
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977,
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428,
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708,
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589,
csrf_prv_reg_read__2727_ULE_1___d14567,
csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974,
csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793,
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811,
f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403,
fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995,
fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935,
fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017,
fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091,
fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005,
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941,
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948,
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970,
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982,
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211,
fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915,
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931,
fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435,
fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752,
fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890,
fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902,
guard__h362176,
guard__h407873,
guard__h453568,
guard__h501321,
guard__h540174,
guard__h579478,
idx__h678705,
k__h664083,
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444,
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836,
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312,
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153,
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009,
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011,
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747,
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606,
msip__h75907,
next_deqP___1__h302643,
next_deqP___1__h308924,
next_deqP___1__h316778,
next_deqP___1__h326835,
next_deqP___1__h330060,
r1__read_BIT_20___h652434,
r__h610340,
regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858,
regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063,
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209,
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655,
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797,
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815,
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119,
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163,
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000,
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229,
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676,
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716,
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757,
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837,
rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247,
rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689,
rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239,
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291,
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292,
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631,
v__h297133,
v__h297651,
v__h307647,
v__h307878,
v__h311523,
v__h311754,
v__h326124,
v__h326355,
v__h329349,
v__h329580,
value_BIT_52___h399003,
x__h601228;
// action method coreReq_start
assign RDY_coreReq_start = 1'd1 ;
assign CAN_FIRE_coreReq_start = 1'd1 ;
assign WILL_FIRE_coreReq_start = EN_coreReq_start ;
// action method coreReq_perfReq
assign RDY_coreReq_perfReq = perfReqQ$FULL_N ;
assign CAN_FIRE_coreReq_perfReq = perfReqQ$FULL_N ;
assign WILL_FIRE_coreReq_perfReq = EN_coreReq_perfReq ;
// actionvalue method coreIndInv_perfResp
assign coreIndInv_perfResp = { perfReqQ$D_OUT, 64'd0 } ;
assign RDY_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_perfResp = perfReqQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_perfResp = EN_coreIndInv_perfResp ;
// action method coreIndInv_terminate
assign RDY_coreIndInv_terminate = csrf_terminate_module_terminateQ$EMPTY_N ;
assign CAN_FIRE_coreIndInv_terminate =
csrf_terminate_module_terminateQ$EMPTY_N ;
assign WILL_FIRE_coreIndInv_terminate = EN_coreIndInv_terminate ;
// value method dCacheToParent_rsToP_notEmpty
assign dCacheToParent_rsToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign RDY_dCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rsToP_deq
assign RDY_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rsToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rsToP_deq = EN_dCacheToParent_rsToP_deq ;
// value method dCacheToParent_rsToP_first
assign dCacheToParent_rsToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578 } ;
assign RDY_dCacheToParent_rsToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty ;
// value method dCacheToParent_rqToP_notEmpty
assign dCacheToParent_rqToP_notEmpty =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign RDY_dCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method dCacheToParent_rqToP_deq
assign RDY_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign CAN_FIRE_dCacheToParent_rqToP_deq =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
assign WILL_FIRE_dCacheToParent_rqToP_deq = EN_dCacheToParent_rqToP_deq ;
// value method dCacheToParent_rqToP_first
assign dCacheToParent_rqToP_first =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604 } ;
assign RDY_dCacheToParent_rqToP_first =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty ;
// value method dCacheToParent_fromP_notFull
assign dCacheToParent_fromP_notFull =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign RDY_dCacheToParent_fromP_notFull = 1'd1 ;
// action method dCacheToParent_fromP_enq
assign RDY_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign CAN_FIRE_dCacheToParent_fromP_enq =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign WILL_FIRE_dCacheToParent_fromP_enq = EN_dCacheToParent_fromP_enq ;
// value method iCacheToParent_rsToP_notEmpty
assign iCacheToParent_rsToP_notEmpty =
fetchStage$iMemIfc_to_parent_rsToP_notEmpty ;
assign RDY_iCacheToParent_rsToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rsToP_deq
assign RDY_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign CAN_FIRE_iCacheToParent_rsToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rsToP_deq ;
assign WILL_FIRE_iCacheToParent_rsToP_deq = EN_iCacheToParent_rsToP_deq ;
// value method iCacheToParent_rsToP_first
assign iCacheToParent_rsToP_first =
fetchStage$iMemIfc_to_parent_rsToP_first ;
assign RDY_iCacheToParent_rsToP_first =
fetchStage$RDY_iMemIfc_to_parent_rsToP_first ;
// value method iCacheToParent_rqToP_notEmpty
assign iCacheToParent_rqToP_notEmpty =
fetchStage$iMemIfc_to_parent_rqToP_notEmpty ;
assign RDY_iCacheToParent_rqToP_notEmpty = 1'd1 ;
// action method iCacheToParent_rqToP_deq
assign RDY_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign CAN_FIRE_iCacheToParent_rqToP_deq =
fetchStage$RDY_iMemIfc_to_parent_rqToP_deq ;
assign WILL_FIRE_iCacheToParent_rqToP_deq = EN_iCacheToParent_rqToP_deq ;
// value method iCacheToParent_rqToP_first
assign iCacheToParent_rqToP_first =
fetchStage$iMemIfc_to_parent_rqToP_first ;
assign RDY_iCacheToParent_rqToP_first =
fetchStage$RDY_iMemIfc_to_parent_rqToP_first ;
// value method iCacheToParent_fromP_notFull
assign iCacheToParent_fromP_notFull =
fetchStage$iMemIfc_to_parent_fromP_notFull ;
assign RDY_iCacheToParent_fromP_notFull = 1'd1 ;
// action method iCacheToParent_fromP_enq
assign RDY_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign CAN_FIRE_iCacheToParent_fromP_enq =
fetchStage$RDY_iMemIfc_to_parent_fromP_enq ;
assign WILL_FIRE_iCacheToParent_fromP_enq = EN_iCacheToParent_fromP_enq ;
// value method tlbToMem_memReq_notEmpty
assign tlbToMem_memReq_notEmpty = l2Tlb$toMem_memReq_notEmpty ;
assign RDY_tlbToMem_memReq_notEmpty = 1'd1 ;
// action method tlbToMem_memReq_deq
assign RDY_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign CAN_FIRE_tlbToMem_memReq_deq = l2Tlb$RDY_toMem_memReq_deq ;
assign WILL_FIRE_tlbToMem_memReq_deq = EN_tlbToMem_memReq_deq ;
// value method tlbToMem_memReq_first
assign tlbToMem_memReq_first = l2Tlb$toMem_memReq_first ;
assign RDY_tlbToMem_memReq_first = l2Tlb$RDY_toMem_memReq_first ;
// value method tlbToMem_respLd_notFull
assign tlbToMem_respLd_notFull = l2Tlb$toMem_respLd_notFull ;
assign RDY_tlbToMem_respLd_notFull = 1'd1 ;
// action method tlbToMem_respLd_enq
assign RDY_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign CAN_FIRE_tlbToMem_respLd_enq = l2Tlb$RDY_toMem_respLd_enq ;
assign WILL_FIRE_tlbToMem_respLd_enq = EN_tlbToMem_respLd_enq ;
// value method mmioToPlatform_cRq_notEmpty
assign mmioToPlatform_cRq_notEmpty = !mmio_cRqQ_empty ;
assign RDY_mmioToPlatform_cRq_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRq_deq
assign RDY_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRq_deq = !mmio_cRqQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRq_deq = EN_mmioToPlatform_cRq_deq ;
// value method mmioToPlatform_cRq_first
assign mmioToPlatform_cRq_first =
{ mmio_cRqQ_data_0[141:78],
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9,
mmio_cRqQ_data_0[71:0] } ;
assign RDY_mmioToPlatform_cRq_first = !mmio_cRqQ_empty ;
// value method mmioToPlatform_pRs_notFull
assign mmioToPlatform_pRs_notFull = !mmio_pRsQ_full ;
assign RDY_mmioToPlatform_pRs_notFull = 1'd1 ;
// action method mmioToPlatform_pRs_enq
assign RDY_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign CAN_FIRE_mmioToPlatform_pRs_enq = !mmio_pRsQ_full ;
assign WILL_FIRE_mmioToPlatform_pRs_enq = EN_mmioToPlatform_pRs_enq ;
// value method mmioToPlatform_pRq_notFull
assign mmioToPlatform_pRq_notFull = !mmio_pRqQ_full ;
assign RDY_mmioToPlatform_pRq_notFull = 1'd1 ;
// action method mmioToPlatform_pRq_enq
assign RDY_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign CAN_FIRE_mmioToPlatform_pRq_enq = !mmio_pRqQ_full ;
assign WILL_FIRE_mmioToPlatform_pRq_enq = EN_mmioToPlatform_pRq_enq ;
// value method mmioToPlatform_cRs_notEmpty
assign mmioToPlatform_cRs_notEmpty = !mmio_cRsQ_empty ;
assign RDY_mmioToPlatform_cRs_notEmpty = 1'd1 ;
// action method mmioToPlatform_cRs_deq
assign RDY_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign CAN_FIRE_mmioToPlatform_cRs_deq = !mmio_cRsQ_empty ;
assign WILL_FIRE_mmioToPlatform_cRs_deq = EN_mmioToPlatform_cRs_deq ;
// value method mmioToPlatform_cRs_first
assign mmioToPlatform_cRs_first = mmio_cRsQ_data_0 ;
assign RDY_mmioToPlatform_cRs_first = !mmio_cRsQ_empty ;
// action method mmioToPlatform_setTime
assign RDY_mmioToPlatform_setTime = 1'd1 ;
assign CAN_FIRE_mmioToPlatform_setTime = 1'd1 ;
assign WILL_FIRE_mmioToPlatform_setTime = EN_mmioToPlatform_setTime ;
// actionvalue method sendDoStats
assign sendDoStats = csrf_stats_module_writeQ$D_OUT ;
assign RDY_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign CAN_FIRE_sendDoStats = csrf_stats_module_writeQ$EMPTY_N ;
assign WILL_FIRE_sendDoStats = EN_sendDoStats ;
// action method recvDoStats
assign RDY_recvDoStats = 1'd1 ;
assign CAN_FIRE_recvDoStats = 1'd1 ;
assign WILL_FIRE_recvDoStats = EN_recvDoStats ;
// actionvalue method deadlock_dCacheCRqStuck_get
assign deadlock_dCacheCRqStuck_get = 73'h0AAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCacheCRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCacheCRqStuck_get =
EN_deadlock_dCacheCRqStuck_get ;
// actionvalue method deadlock_dCachePRqStuck_get
assign deadlock_dCachePRqStuck_get = 68'hAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_dCachePRqStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_dCachePRqStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_dCachePRqStuck_get =
EN_deadlock_dCachePRqStuck_get ;
// actionvalue method deadlock_iCacheCRqStuck_get
assign deadlock_iCacheCRqStuck_get = fetchStage$iMemIfc_cRqStuck_get ;
assign RDY_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign CAN_FIRE_deadlock_iCacheCRqStuck_get =
fetchStage$RDY_iMemIfc_cRqStuck_get ;
assign WILL_FIRE_deadlock_iCacheCRqStuck_get =
EN_deadlock_iCacheCRqStuck_get ;
// actionvalue method deadlock_iCachePRqStuck_get
assign deadlock_iCachePRqStuck_get = fetchStage$iMemIfc_pRqStuck_get ;
assign RDY_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign CAN_FIRE_deadlock_iCachePRqStuck_get =
fetchStage$RDY_iMemIfc_pRqStuck_get ;
assign WILL_FIRE_deadlock_iCachePRqStuck_get =
EN_deadlock_iCachePRqStuck_get ;
// actionvalue method deadlock_renameInstStuck_get
assign deadlock_renameInstStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameInstStuck_get =
EN_deadlock_renameInstStuck_get ;
// actionvalue method deadlock_renameCorrectPathStuck_get
assign deadlock_renameCorrectPathStuck_get = 78'h2AAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_renameCorrectPathStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_renameCorrectPathStuck_get =
EN_deadlock_renameCorrectPathStuck_get ;
// actionvalue method deadlock_commitInstStuck_get
assign deadlock_commitInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitInstStuck_get =
EN_deadlock_commitInstStuck_get ;
// actionvalue method deadlock_commitUserInstStuck_get
assign deadlock_commitUserInstStuck_get =
163'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_deadlock_commitUserInstStuck_get = 1'd0 ;
assign CAN_FIRE_deadlock_commitUserInstStuck_get = 1'd0 ;
assign WILL_FIRE_deadlock_commitUserInstStuck_get =
EN_deadlock_commitUserInstStuck_get ;
// action method deadlock_checkStarted_get
assign RDY_deadlock_checkStarted_get = 1'd0 ;
assign CAN_FIRE_deadlock_checkStarted_get = 1'd0 ;
assign WILL_FIRE_deadlock_checkStarted_get = EN_deadlock_checkStarted_get ;
// actionvalue method renameDebug_renameErr_get
assign renameDebug_renameErr_get = 89'h0AAAAAAAAAAAAAAAAAAAAAA ;
assign RDY_renameDebug_renameErr_get = 1'd0 ;
assign CAN_FIRE_renameDebug_renameErr_get = 1'd0 ;
assign WILL_FIRE_renameDebug_renameErr_get = EN_renameDebug_renameErr_get ;
// action method setMEIP
assign RDY_setMEIP = 1'd1 ;
assign CAN_FIRE_setMEIP = 1'd1 ;
assign WILL_FIRE_setMEIP = EN_setMEIP ;
// action method setSEIP
assign RDY_setSEIP = 1'd1 ;
assign CAN_FIRE_setSEIP = 1'd1 ;
assign WILL_FIRE_setSEIP = EN_setSEIP ;
// action method hart0_run_halt_server_request_put
assign RDY_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
assign CAN_FIRE_hart0_run_halt_server_request_put = f_run_halt_reqs$FULL_N ;
assign WILL_FIRE_hart0_run_halt_server_request_put =
EN_hart0_run_halt_server_request_put ;
// actionvalue method hart0_run_halt_server_response_get
assign hart0_run_halt_server_response_get = f_run_halt_rsps$D_OUT ;
assign RDY_hart0_run_halt_server_response_get = f_run_halt_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_run_halt_server_response_get =
f_run_halt_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_run_halt_server_response_get =
EN_hart0_run_halt_server_response_get ;
// action method hart0_gpr_mem_server_request_put
assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_gpr_mem_server_request_put =
EN_hart0_gpr_mem_server_request_put ;
// actionvalue method hart0_gpr_mem_server_response_get
assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ;
assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_gpr_mem_server_response_get =
EN_hart0_gpr_mem_server_response_get ;
// action method hart0_fpr_mem_server_request_put
assign RDY_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign CAN_FIRE_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
assign WILL_FIRE_hart0_fpr_mem_server_request_put =
EN_hart0_fpr_mem_server_request_put ;
// actionvalue method hart0_fpr_mem_server_response_get
assign hart0_fpr_mem_server_response_get = f_fpr_rsps$D_OUT ;
assign RDY_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_fpr_mem_server_response_get =
EN_hart0_fpr_mem_server_response_get ;
// action method hart0_csr_mem_server_request_put
assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
assign WILL_FIRE_hart0_csr_mem_server_request_put =
EN_hart0_csr_mem_server_request_put ;
// actionvalue method hart0_csr_mem_server_response_get
assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ;
assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_csr_mem_server_response_get =
EN_hart0_csr_mem_server_response_get ;
// actionvalue method v_to_TV_0_get
assign v_to_TV_0_get =
{ v_f_to_TV_0$D_OUT[319:154],
CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5,
v_f_to_TV_0$D_OUT[141:140],
v_f_to_TV_0$D_OUT[140] ?
CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6 :
CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7,
v_f_to_TV_0$D_OUT[135:72],
CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8,
v_f_to_TV_0$D_OUT[69:0] } ;
assign RDY_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
assign CAN_FIRE_v_to_TV_0_get = v_f_to_TV_0$EMPTY_N ;
assign WILL_FIRE_v_to_TV_0_get = EN_v_to_TV_0_get ;
// actionvalue method v_to_TV_1_get
assign v_to_TV_1_get =
{ v_f_to_TV_1$D_OUT[319:154],
CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1,
v_f_to_TV_1$D_OUT[141:140],
v_f_to_TV_1$D_OUT[140] ?
CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2 :
CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3,
v_f_to_TV_1$D_OUT[135:72],
CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4,
v_f_to_TV_1$D_OUT[69:0] } ;
assign RDY_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
assign CAN_FIRE_v_to_TV_1_get = v_f_to_TV_1$EMPTY_N ;
assign WILL_FIRE_v_to_TV_1_get = EN_v_to_TV_1_get ;
// submodule coreFix_aluExe_0_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_0_dispToRegQ$first),
.RDY_first(coreFix_aluExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_0_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_0_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_0_exeToFinQ$first),
.RDY_first(coreFix_aluExe_0_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_0_regToExeQ$RDY_deq),
.first(coreFix_aluExe_0_regToExeQ$first),
.RDY_first(coreFix_aluExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_0_rsAlu
mkReservationStationAlu coreFix_aluExe_0_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_0_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_0_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_0_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_0_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_0_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_0_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_0_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_0_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_0_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_0_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_0_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_0_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_0_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_0_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_0_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_0_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_dispToRegQ
mkAluDispToRegFifo coreFix_aluExe_1_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_dispToRegQ$EN_enq),
.EN_deq(coreFix_aluExe_1_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_dispToRegQ$RDY_deq),
.first(coreFix_aluExe_1_dispToRegQ$first),
.RDY_first(coreFix_aluExe_1_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_exeToFinQ
mkAluExeToFinFifo coreFix_aluExe_1_exeToFinQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_exeToFinQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_exeToFinQ$EN_enq),
.EN_deq(coreFix_aluExe_1_exeToFinQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_exeToFinQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_exeToFinQ$RDY_deq),
.first(coreFix_aluExe_1_exeToFinQ$first),
.RDY_first(coreFix_aluExe_1_exeToFinQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_regToExeQ
mkAluRegToExeFifo coreFix_aluExe_1_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_regToExeQ$EN_enq),
.EN_deq(coreFix_aluExe_1_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_regToExeQ$RDY_enq),
.RDY_deq(coreFix_aluExe_1_regToExeQ$RDY_deq),
.first(coreFix_aluExe_1_regToExeQ$first),
.RDY_first(coreFix_aluExe_1_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_aluExe_1_rsAlu
mkReservationStationAlu coreFix_aluExe_1_rsAlu(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_aluExe_1_rsAlu$enq_x),
.setRegReady_0_put(coreFix_aluExe_1_rsAlu$setRegReady_0_put),
.setRegReady_1_put(coreFix_aluExe_1_rsAlu$setRegReady_1_put),
.setRegReady_2_put(coreFix_aluExe_1_rsAlu$setRegReady_2_put),
.setRegReady_3_put(coreFix_aluExe_1_rsAlu$setRegReady_3_put),
.setRegReady_4_put(coreFix_aluExe_1_rsAlu$setRegReady_4_put),
.setRobEnqTime_t(coreFix_aluExe_1_rsAlu$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_aluExe_1_rsAlu$EN_enq),
.EN_setRobEnqTime(coreFix_aluExe_1_rsAlu$EN_setRobEnqTime),
.EN_doDispatch(coreFix_aluExe_1_rsAlu$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_aluExe_1_rsAlu$RDY_enq),
.canEnq(coreFix_aluExe_1_rsAlu$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_aluExe_1_rsAlu$dispatchData),
.RDY_dispatchData(coreFix_aluExe_1_rsAlu$RDY_dispatchData),
.RDY_doDispatch(coreFix_aluExe_1_rsAlu$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(coreFix_aluExe_1_rsAlu$approximateCount),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
mkFpuMulDivDispToRegFifo coreFix_fpuMulDivExe_0_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_dispToRegQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
mkDoubleDiv coreFix_fpuMulDivExe_0_fpuExec_double_div(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
mkDoubleFMA coreFix_fpuMulDivExe_0_fpuExec_double_fma(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
mkDoubleSqrt coreFix_fpuMulDivExe_0_fpuExec_double_sqrt(.CLK(CLK),
.RST_N(RST_N),
.request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put),
.EN_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put),
.EN_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get),
.RDY_request_put(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put),
.response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get),
.RDY_response_get(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get));
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
mkFmaExecQ coreFix_fpuMulDivExe_0_fpuExec_fmaQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
mkSimpleRespQ coreFix_fpuMulDivExe_0_fpuExec_simpleQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
mkMinimumExecQ coreFix_fpuMulDivExe_0_fpuExec_sqrtQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
mkDivExecQ coreFix_fpuMulDivExe_0_mulDivExec_divQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
int_div_unsigned coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc(.aclk(CLK),
.s_axis_dividend_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata),
.s_axis_dividend_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser),
.s_axis_divisor_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata),
.s_axis_dividend_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid),
.s_axis_divisor_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid),
.m_axis_dout_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready),
.s_axis_dividend_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready),
.s_axis_divisor_tready(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready),
.m_axis_dout_tvalid(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid),
.m_axis_dout_tdata(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata),
.m_axis_dout_tuser(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg
reset_guard coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg(.CLK(CLK),
.RST(RST_N),
.IS_READY(coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
mkMulExecQ coreFix_fpuMulDivExe_0_mulDivExec_mulQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq),
.first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data),
.RDY_first_data(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data),
.first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned),
.RDY_first_poisoned(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
int_mul_signed coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned(.CLK(CLK),
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A),
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B),
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
int_mul_signed_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned(.CLK(CLK),
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A),
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B),
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
int_mul_unsigned coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned(.CLK(CLK),
.A(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A),
.B(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B),
.P(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P));
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
SizedFIFO #(.p1width(32'd128),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd0)) coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN),
.ENQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ),
.DEQ(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ),
.CLR(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR),
.D_OUT(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT),
.FULL_N(),
.EMPTY_N(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N));
// submodule coreFix_fpuMulDivExe_0_regToExeQ
mkFpuMulDivRegToExeFifo coreFix_fpuMulDivExe_0_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_regToExeQ$EN_enq),
.EN_deq(coreFix_fpuMulDivExe_0_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq),
.RDY_deq(coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq),
.first(coreFix_fpuMulDivExe_0_regToExeQ$first),
.RDY_first(coreFix_fpuMulDivExe_0_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
mkReservationStationFpuMulDiv coreFix_fpuMulDivExe_0_rsFpuMulDiv(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x),
.setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put),
.setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put),
.setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put),
.setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put),
.setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put),
.setRobEnqTime_t(coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq),
.EN_setRobEnqTime(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime),
.EN_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq),
.canEnq(coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData),
.RDY_dispatchData(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData),
.RDY_doDispatch(coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
mkDCRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_cRqMshr(.CLK(CLK),
.RST_N(RST_N),
.cRqTransfer_getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r),
.cRqTransfer_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n),
.pipelineResp_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n),
.pipelineResp_getSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_searchEndOfChain_addr(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr),
.pipelineResp_setData_d(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d),
.pipelineResp_setData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n),
.pipelineResp_setStateSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n),
.pipelineResp_setStateSlot_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot),
.pipelineResp_setStateSlot_state(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state),
.pipelineResp_setSucc_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n),
.pipelineResp_setSucc_succ(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ),
.sendRqToP_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n),
.sendRqToP_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n),
.sendRsToP_cRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n),
.sendRsToP_cRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n),
.sendRsToP_cRq_getSlot_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n),
.sendRsToP_cRq_getState_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_n(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n),
.sendRsToP_cRq_setWaitSt_setSlot_clearData_slot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot),
.EN_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit),
.EN_sendRsToP_cRq_setWaitSt_setSlot_clearData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData),
.EN_pipelineResp_setStateSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot),
.EN_pipelineResp_setSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get),
.cRqTransfer_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq),
.RDY_cRqTransfer_getRq(),
.cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit),
.RDY_cRqTransfer_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit),
.sendRsToP_cRq_getState(),
.RDY_sendRsToP_cRq_getState(),
.sendRsToP_cRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq),
.RDY_sendRsToP_cRq_getRq(),
.sendRsToP_cRq_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot),
.RDY_sendRsToP_cRq_getSlot(),
.sendRsToP_cRq_getData(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData),
.RDY_sendRsToP_cRq_getData(),
.RDY_sendRsToP_cRq_setWaitSt_setSlot_clearData(),
.sendRqToP_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq),
.RDY_sendRqToP_getRq(),
.sendRqToP_getSlot(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot),
.RDY_sendRqToP_getSlot(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry),
.pipelineResp_getState(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState),
.RDY_pipelineResp_getState(),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getSlot(),
.RDY_pipelineResp_getSlot(),
.RDY_pipelineResp_setData(),
.RDY_pipelineResp_setStateSlot(),
.pipelineResp_getSucc(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc),
.RDY_pipelineResp_getSucc(),
.RDY_pipelineResp_setSucc(),
.pipelineResp_searchEndOfChain(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain),
.RDY_pipelineResp_searchEndOfChain(),
.emptyForFlush(),
.RDY_emptyForFlush(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
mkDPRqMshrWrapper coreFix_memExe_dMem_cache_m_banks_0_pRqMshr(.CLK(CLK),
.RST_N(RST_N),
.getEmptyEntryInit_r(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r),
.pipelineResp_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n),
.pipelineResp_getState_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n),
.pipelineResp_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n),
.pipelineResp_setDone_setData_d(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d),
.pipelineResp_setDone_setData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n),
.sendRsToP_pRq_getData_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n),
.sendRsToP_pRq_getRq_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n),
.sendRsToP_pRq_releaseEntry_n(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n),
.EN_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit),
.EN_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry),
.EN_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry),
.EN_pipelineResp_setDone_setData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData),
.EN_stuck_get(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get),
.getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit),
.RDY_getEmptyEntryInit(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit),
.sendRsToP_pRq_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq),
.RDY_sendRsToP_pRq_getRq(),
.sendRsToP_pRq_getData(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData),
.RDY_sendRsToP_pRq_getData(),
.RDY_sendRsToP_pRq_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry),
.pipelineResp_getRq(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getState(),
.RDY_pipelineResp_getState(),
.RDY_pipelineResp_releaseEntry(coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry),
.RDY_pipelineResp_setDone_setData(),
.stuck_get(),
.RDY_stuck_get());
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
mkDPipeline coreFix_memExe_dMem_cache_m_banks_0_pipeline(.CLK(CLK),
.RST_N(RST_N),
.deqWrite_swapRq(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq),
.deqWrite_updateRep(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep),
.deqWrite_wrRam(coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam),
.send_r(coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r),
.EN_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send),
.EN_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite),
.RDY_send(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send),
.first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first),
.RDY_first(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first),
.RDY_deqWrite(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
SizedFIFO #(.p1width(32'd3),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
FIFO2 #(.width(32'd3),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd12),
.p3cntr_width(32'd4),
.guarded(32'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN),
.ENQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ),
.DEQ(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ),
.CLR(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR),
.D_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT),
.FULL_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N),
.EMPTY_N(coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_dTlb
mkDTlbSynth coreFix_memExe_dTlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(coreFix_memExe_dTlb$perf_req_r),
.perf_setStatus_doStats(coreFix_memExe_dTlb$perf_setStatus_doStats),
.procReq_req(coreFix_memExe_dTlb$procReq_req),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag),
.toParent_ldTransRsFromP_enq_x(coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x),
.updateVMInfo_vm(coreFix_memExe_dTlb$updateVMInfo_vm),
.EN_flush(coreFix_memExe_dTlb$EN_flush),
.EN_updateVMInfo(coreFix_memExe_dTlb$EN_updateVMInfo),
.EN_procReq(coreFix_memExe_dTlb$EN_procReq),
.EN_deqProcResp(coreFix_memExe_dTlb$EN_deqProcResp),
.EN_toParent_rqToP_deq(coreFix_memExe_dTlb$EN_toParent_rqToP_deq),
.EN_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq),
.EN_toParent_flush_request_get(coreFix_memExe_dTlb$EN_toParent_flush_request_get),
.EN_toParent_flush_response_put(coreFix_memExe_dTlb$EN_toParent_flush_response_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation),
.EN_perf_setStatus(coreFix_memExe_dTlb$EN_perf_setStatus),
.EN_perf_req(coreFix_memExe_dTlb$EN_perf_req),
.EN_perf_resp(coreFix_memExe_dTlb$EN_perf_resp),
.flush_done(coreFix_memExe_dTlb$flush_done),
.RDY_flush_done(),
.RDY_flush(coreFix_memExe_dTlb$RDY_flush),
.RDY_updateVMInfo(),
.noPendingReq(coreFix_memExe_dTlb$noPendingReq),
.RDY_noPendingReq(),
.RDY_procReq(coreFix_memExe_dTlb$RDY_procReq),
.procResp(coreFix_memExe_dTlb$procResp),
.RDY_procResp(coreFix_memExe_dTlb$RDY_procResp),
.RDY_deqProcResp(coreFix_memExe_dTlb$RDY_deqProcResp),
.toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_notEmpty(),
.RDY_toParent_rqToP_deq(coreFix_memExe_dTlb$RDY_toParent_rqToP_deq),
.toParent_rqToP_first(coreFix_memExe_dTlb$toParent_rqToP_first),
.RDY_toParent_rqToP_first(coreFix_memExe_dTlb$RDY_toParent_rqToP_first),
.toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_notFull(),
.RDY_toParent_ldTransRsFromP_enq(coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq),
.RDY_toParent_flush_request_get(coreFix_memExe_dTlb$RDY_toParent_flush_request_get),
.RDY_toParent_flush_response_put(coreFix_memExe_dTlb$RDY_toParent_flush_response_put),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule coreFix_memExe_dispToRegQ
mkMemDispToRegFifo coreFix_memExe_dispToRegQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_dispToRegQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_dispToRegQ$EN_enq),
.EN_deq(coreFix_memExe_dispToRegQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_dispToRegQ$RDY_enq),
.RDY_deq(coreFix_memExe_dispToRegQ$RDY_deq),
.first(coreFix_memExe_dispToRegQ$first),
.RDY_first(coreFix_memExe_dispToRegQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_forwardQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_forwardQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_lsq
mkSplitLSQ coreFix_memExe_lsq(.CLK(CLK),
.RST_N(RST_N),
.enqLd_dst(coreFix_memExe_lsq$enqLd_dst),
.enqLd_inst_tag(coreFix_memExe_lsq$enqLd_inst_tag),
.enqLd_mem_inst(coreFix_memExe_lsq$enqLd_mem_inst),
.enqLd_spec_bits(coreFix_memExe_lsq$enqLd_spec_bits),
.enqSt_dst(coreFix_memExe_lsq$enqSt_dst),
.enqSt_inst_tag(coreFix_memExe_lsq$enqSt_inst_tag),
.enqSt_mem_inst(coreFix_memExe_lsq$enqSt_mem_inst),
.enqSt_spec_bits(coreFix_memExe_lsq$enqSt_spec_bits),
.getHit_t(coreFix_memExe_lsq$getHit_t),
.getOrigBE_t(coreFix_memExe_lsq$getOrigBE_t),
.issueLd_lsqTag(coreFix_memExe_lsq$issueLd_lsqTag),
.issueLd_paddr(coreFix_memExe_lsq$issueLd_paddr),
.issueLd_sbRes(coreFix_memExe_lsq$issueLd_sbRes),
.issueLd_shiftedBE(coreFix_memExe_lsq$issueLd_shiftedBE),
.respLd_alignedData(coreFix_memExe_lsq$respLd_alignedData),
.respLd_t(coreFix_memExe_lsq$respLd_t),
.setAtCommit_0_put(coreFix_memExe_lsq$setAtCommit_0_put),
.setAtCommit_1_put(coreFix_memExe_lsq$setAtCommit_1_put),
.specUpdate_correctSpeculation_mask(coreFix_memExe_lsq$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag),
.updateAddr_fault(coreFix_memExe_lsq$updateAddr_fault),
.updateAddr_isMMIO(coreFix_memExe_lsq$updateAddr_isMMIO),
.updateAddr_lsqTag(coreFix_memExe_lsq$updateAddr_lsqTag),
.updateAddr_paddr(coreFix_memExe_lsq$updateAddr_paddr),
.updateAddr_shiftedBE(coreFix_memExe_lsq$updateAddr_shiftedBE),
.updateData_d(coreFix_memExe_lsq$updateData_d),
.updateData_t(coreFix_memExe_lsq$updateData_t),
.wakeupLdStalledBySB_sbIdx(coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx),
.EN_enqLd(coreFix_memExe_lsq$EN_enqLd),
.EN_enqSt(coreFix_memExe_lsq$EN_enqSt),
.EN_getHit(coreFix_memExe_lsq$EN_getHit),
.EN_updateData(coreFix_memExe_lsq$EN_updateData),
.EN_updateAddr(coreFix_memExe_lsq$EN_updateAddr),
.EN_issueLd(coreFix_memExe_lsq$EN_issueLd),
.EN_getIssueLd(coreFix_memExe_lsq$EN_getIssueLd),
.EN_respLd(coreFix_memExe_lsq$EN_respLd),
.EN_deqLd(coreFix_memExe_lsq$EN_deqLd),
.EN_deqSt(coreFix_memExe_lsq$EN_deqSt),
.EN_wakeupLdStalledBySB(coreFix_memExe_lsq$EN_wakeupLdStalledBySB),
.EN_setAtCommit_0_put(coreFix_memExe_lsq$EN_setAtCommit_0_put),
.EN_setAtCommit_1_put(coreFix_memExe_lsq$EN_setAtCommit_1_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_lsq$EN_specUpdate_correctSpeculation),
.enqLdTag(coreFix_memExe_lsq$enqLdTag),
.RDY_enqLdTag(),
.enqStTag(coreFix_memExe_lsq$enqStTag),
.RDY_enqStTag(),
.RDY_enqLd(coreFix_memExe_lsq$RDY_enqLd),
.RDY_enqSt(coreFix_memExe_lsq$RDY_enqSt),
.getOrigBE(coreFix_memExe_lsq$getOrigBE),
.RDY_getOrigBE(),
.getHit(coreFix_memExe_lsq$getHit),
.RDY_getHit(),
.RDY_updateData(),
.updateAddr(coreFix_memExe_lsq$updateAddr),
.RDY_updateAddr(),
.issueLd(coreFix_memExe_lsq$issueLd),
.RDY_issueLd(),
.getIssueLd(coreFix_memExe_lsq$getIssueLd),
.RDY_getIssueLd(coreFix_memExe_lsq$RDY_getIssueLd),
.respLd(coreFix_memExe_lsq$respLd),
.RDY_respLd(),
.firstLd(coreFix_memExe_lsq$firstLd),
.RDY_firstLd(coreFix_memExe_lsq$RDY_firstLd),
.RDY_deqLd(coreFix_memExe_lsq$RDY_deqLd),
.firstSt(coreFix_memExe_lsq$firstSt),
.RDY_firstSt(coreFix_memExe_lsq$RDY_firstSt),
.RDY_deqSt(coreFix_memExe_lsq$RDY_deqSt),
.RDY_wakeupLdStalledBySB(),
.stqEmpty(coreFix_memExe_lsq$stqEmpty),
.RDY_stqEmpty(),
.RDY_setAtCommit_0_put(),
.RDY_setAtCommit_1_put(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.stqFull_ehrPort0(),
.RDY_stqFull_ehrPort0(),
.ldqFull_ehrPort0(),
.RDY_ldqFull_ehrPort0(),
.noWrongPathLoads(coreFix_memExe_lsq$noWrongPathLoads),
.RDY_noWrongPathLoads());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_memRespLdQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_regToExeQ
mkMemRegToExeFifo coreFix_memExe_regToExeQ(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_regToExeQ$enq_x),
.specUpdate_correctSpeculation_mask(coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_regToExeQ$EN_enq),
.EN_deq(coreFix_memExe_regToExeQ$EN_deq),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_regToExeQ$RDY_enq),
.RDY_deq(coreFix_memExe_regToExeQ$RDY_deq),
.first(coreFix_memExe_regToExeQ$first),
.RDY_first(coreFix_memExe_regToExeQ$RDY_first),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLdQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLdQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLdQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqLrScAmoQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_data_0_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_data_0_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_deqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_deqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_empty_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_empty_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_empty_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT));
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_enqP_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_enqP_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_reqStQ_full_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_0$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_0$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_1$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_1$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT));
// submodule coreFix_memExe_reqStQ_full_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_reqStQ_full_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_reqStQ_full_dummy2_2$D_IN),
.EN(coreFix_memExe_reqStQ_full_dummy2_2$EN),
.Q_OUT(coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN),
.EN(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN),
.Q_OUT(coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT));
// submodule coreFix_memExe_rsMem
mkReservationStationMem coreFix_memExe_rsMem(.CLK(CLK),
.RST_N(RST_N),
.enq_x(coreFix_memExe_rsMem$enq_x),
.setRegReady_0_put(coreFix_memExe_rsMem$setRegReady_0_put),
.setRegReady_1_put(coreFix_memExe_rsMem$setRegReady_1_put),
.setRegReady_2_put(coreFix_memExe_rsMem$setRegReady_2_put),
.setRegReady_3_put(coreFix_memExe_rsMem$setRegReady_3_put),
.setRegReady_4_put(coreFix_memExe_rsMem$setRegReady_4_put),
.setRobEnqTime_t(coreFix_memExe_rsMem$setRobEnqTime_t),
.specUpdate_correctSpeculation_mask(coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag),
.EN_enq(coreFix_memExe_rsMem$EN_enq),
.EN_setRobEnqTime(coreFix_memExe_rsMem$EN_setRobEnqTime),
.EN_doDispatch(coreFix_memExe_rsMem$EN_doDispatch),
.EN_setRegReady_0_put(coreFix_memExe_rsMem$EN_setRegReady_0_put),
.EN_setRegReady_1_put(coreFix_memExe_rsMem$EN_setRegReady_1_put),
.EN_setRegReady_2_put(coreFix_memExe_rsMem$EN_setRegReady_2_put),
.EN_setRegReady_3_put(coreFix_memExe_rsMem$EN_setRegReady_3_put),
.EN_setRegReady_4_put(coreFix_memExe_rsMem$EN_setRegReady_4_put),
.EN_specUpdate_incorrectSpeculation(coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation),
.RDY_enq(coreFix_memExe_rsMem$RDY_enq),
.canEnq(coreFix_memExe_rsMem$canEnq),
.RDY_canEnq(),
.RDY_setRobEnqTime(),
.dispatchData(coreFix_memExe_rsMem$dispatchData),
.RDY_dispatchData(coreFix_memExe_rsMem$RDY_dispatchData),
.RDY_doDispatch(coreFix_memExe_rsMem$RDY_doDispatch),
.RDY_setRegReady_0_put(),
.RDY_setRegReady_1_put(),
.RDY_setRegReady_2_put(),
.RDY_setRegReady_3_put(),
.RDY_setRegReady_4_put(),
.approximateCount(),
.RDY_approximateCount(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule coreFix_memExe_stb
mkStoreBufferEhr coreFix_memExe_stb(.CLK(CLK),
.RST_N(RST_N),
.deq_idx(coreFix_memExe_stb$deq_idx),
.enq_be(coreFix_memExe_stb$enq_be),
.enq_data(coreFix_memExe_stb$enq_data),
.enq_idx(coreFix_memExe_stb$enq_idx),
.enq_paddr(coreFix_memExe_stb$enq_paddr),
.getEnqIndex_paddr(coreFix_memExe_stb$getEnqIndex_paddr),
.noMatchLdQ_be(coreFix_memExe_stb$noMatchLdQ_be),
.noMatchLdQ_paddr(coreFix_memExe_stb$noMatchLdQ_paddr),
.noMatchStQ_be(coreFix_memExe_stb$noMatchStQ_be),
.noMatchStQ_paddr(coreFix_memExe_stb$noMatchStQ_paddr),
.search_be(coreFix_memExe_stb$search_be),
.search_paddr(coreFix_memExe_stb$search_paddr),
.EN_enq(coreFix_memExe_stb$EN_enq),
.EN_deq(coreFix_memExe_stb$EN_deq),
.EN_issue(coreFix_memExe_stb$EN_issue),
.isEmpty(coreFix_memExe_stb$isEmpty),
.RDY_isEmpty(),
.getEnqIndex(coreFix_memExe_stb$getEnqIndex),
.RDY_getEnqIndex(),
.RDY_enq(coreFix_memExe_stb$RDY_enq),
.deq(coreFix_memExe_stb$deq),
.RDY_deq(coreFix_memExe_stb$RDY_deq),
.issue(coreFix_memExe_stb$issue),
.RDY_issue(coreFix_memExe_stb$RDY_issue),
.search(coreFix_memExe_stb$search),
.RDY_search(),
.noMatchLdQ(coreFix_memExe_stb$noMatchLdQ),
.RDY_noMatchLdQ(),
.noMatchStQ(coreFix_memExe_stb$noMatchStQ),
.RDY_noMatchStQ());
// submodule coreFix_trainBPQ_0
FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_0(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_0$D_IN),
.ENQ(coreFix_trainBPQ_0$ENQ),
.DEQ(coreFix_trainBPQ_0$DEQ),
.CLR(coreFix_trainBPQ_0$CLR),
.D_OUT(coreFix_trainBPQ_0$D_OUT),
.FULL_N(coreFix_trainBPQ_0$FULL_N),
.EMPTY_N(coreFix_trainBPQ_0$EMPTY_N));
// submodule coreFix_trainBPQ_1
FIFO2 #(.width(32'd160), .guarded(32'd1)) coreFix_trainBPQ_1(.RST(RST_N),
.CLK(CLK),
.D_IN(coreFix_trainBPQ_1$D_IN),
.ENQ(coreFix_trainBPQ_1$ENQ),
.DEQ(coreFix_trainBPQ_1$DEQ),
.CLR(coreFix_trainBPQ_1$CLR),
.D_OUT(coreFix_trainBPQ_1$D_OUT),
.FULL_N(coreFix_trainBPQ_1$FULL_N),
.EMPTY_N(coreFix_trainBPQ_1$EMPTY_N));
// submodule csrInstOrInterruptInflight_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_0(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_0$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_0$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_0$Q_OUT));
// submodule csrInstOrInterruptInflight_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrInstOrInterruptInflight_dummy2_1(.CLK(CLK),
.D_IN(csrInstOrInterruptInflight_dummy2_1$D_IN),
.EN(csrInstOrInterruptInflight_dummy2_1$EN),
.Q_OUT(csrInstOrInterruptInflight_dummy2_1$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_0$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_mcycle_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_mcycle_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_mcycle_ehr_data_dummy2_1$D_IN),
.EN(csrf_mcycle_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_mcycle_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_0(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_0$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_0$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_0$Q_OUT));
// submodule csrf_minstret_ehr_data_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) csrf_minstret_ehr_data_dummy2_1(.CLK(CLK),
.D_IN(csrf_minstret_ehr_data_dummy2_1$D_IN),
.EN(csrf_minstret_ehr_data_dummy2_1$EN),
.Q_OUT(csrf_minstret_ehr_data_dummy2_1$Q_OUT));
// submodule csrf_stats_module_writeQ
FIFO1 #(.width(32'd1),
.guarded(32'd1)) csrf_stats_module_writeQ(.RST(RST_N),
.CLK(CLK),
.D_IN(csrf_stats_module_writeQ$D_IN),
.ENQ(csrf_stats_module_writeQ$ENQ),
.DEQ(csrf_stats_module_writeQ$DEQ),
.CLR(csrf_stats_module_writeQ$CLR),
.D_OUT(csrf_stats_module_writeQ$D_OUT),
.FULL_N(csrf_stats_module_writeQ$FULL_N),
.EMPTY_N(csrf_stats_module_writeQ$EMPTY_N));
// submodule csrf_terminate_module_terminateQ
FIFO10 #(.guarded(32'd1)) csrf_terminate_module_terminateQ(.RST(RST_N),
.CLK(CLK),
.ENQ(csrf_terminate_module_terminateQ$ENQ),
.DEQ(csrf_terminate_module_terminateQ$DEQ),
.CLR(csrf_terminate_module_terminateQ$CLR),
.FULL_N(csrf_terminate_module_terminateQ$FULL_N),
.EMPTY_N(csrf_terminate_module_terminateQ$EMPTY_N));
// submodule epochManager
mkEpochManager epochManager(.CLK(CLK),
.RST_N(RST_N),
.checkEpoch_0_check_e(epochManager$checkEpoch_0_check_e),
.checkEpoch_1_check_e(epochManager$checkEpoch_1_check_e),
.updatePrevEpoch_0_update_e(epochManager$updatePrevEpoch_0_update_e),
.updatePrevEpoch_1_update_e(epochManager$updatePrevEpoch_1_update_e),
.EN_updatePrevEpoch_0_update(epochManager$EN_updatePrevEpoch_0_update),
.EN_updatePrevEpoch_1_update(epochManager$EN_updatePrevEpoch_1_update),
.EN_incrementEpoch(epochManager$EN_incrementEpoch),
.checkEpoch_0_check(epochManager$checkEpoch_0_check),
.RDY_checkEpoch_0_check(),
.checkEpoch_1_check(epochManager$checkEpoch_1_check),
.RDY_checkEpoch_1_check(),
.RDY_updatePrevEpoch_0_update(),
.RDY_updatePrevEpoch_1_update(),
.getEpoch(),
.RDY_getEpoch(),
.RDY_incrementEpoch(epochManager$RDY_incrementEpoch),
.getEpochState(),
.RDY_getEpochState(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// submodule f_csr_reqs
FIFO1 #(.width(32'd77), .guarded(32'd1)) f_csr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_reqs$D_IN),
.ENQ(f_csr_reqs$ENQ),
.DEQ(f_csr_reqs$DEQ),
.CLR(f_csr_reqs$CLR),
.D_OUT(f_csr_reqs$D_OUT),
.FULL_N(f_csr_reqs$FULL_N),
.EMPTY_N(f_csr_reqs$EMPTY_N));
// submodule f_csr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_csr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_csr_rsps$D_IN),
.ENQ(f_csr_rsps$ENQ),
.DEQ(f_csr_rsps$DEQ),
.CLR(f_csr_rsps$CLR),
.D_OUT(f_csr_rsps$D_OUT),
.FULL_N(f_csr_rsps$FULL_N),
.EMPTY_N(f_csr_rsps$EMPTY_N));
// submodule f_fpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_fpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_reqs$D_IN),
.ENQ(f_fpr_reqs$ENQ),
.DEQ(f_fpr_reqs$DEQ),
.CLR(f_fpr_reqs$CLR),
.D_OUT(f_fpr_reqs$D_OUT),
.FULL_N(f_fpr_reqs$FULL_N),
.EMPTY_N(f_fpr_reqs$EMPTY_N));
// submodule f_fpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_fpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fpr_rsps$D_IN),
.ENQ(f_fpr_rsps$ENQ),
.DEQ(f_fpr_rsps$DEQ),
.CLR(f_fpr_rsps$CLR),
.D_OUT(f_fpr_rsps$D_OUT),
.FULL_N(f_fpr_rsps$FULL_N),
.EMPTY_N(f_fpr_rsps$EMPTY_N));
// submodule f_gpr_reqs
FIFO1 #(.width(32'd70), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_reqs$D_IN),
.ENQ(f_gpr_reqs$ENQ),
.DEQ(f_gpr_reqs$DEQ),
.CLR(f_gpr_reqs$CLR),
.D_OUT(f_gpr_reqs$D_OUT),
.FULL_N(f_gpr_reqs$FULL_N),
.EMPTY_N(f_gpr_reqs$EMPTY_N));
// submodule f_gpr_rsps
FIFO1 #(.width(32'd65), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_gpr_rsps$D_IN),
.ENQ(f_gpr_rsps$ENQ),
.DEQ(f_gpr_rsps$DEQ),
.CLR(f_gpr_rsps$CLR),
.D_OUT(f_gpr_rsps$D_OUT),
.FULL_N(f_gpr_rsps$FULL_N),
.EMPTY_N(f_gpr_rsps$EMPTY_N));
// submodule f_run_halt_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_reqs$D_IN),
.ENQ(f_run_halt_reqs$ENQ),
.DEQ(f_run_halt_reqs$DEQ),
.CLR(f_run_halt_reqs$CLR),
.D_OUT(f_run_halt_reqs$D_OUT),
.FULL_N(f_run_halt_reqs$FULL_N),
.EMPTY_N(f_run_halt_reqs$EMPTY_N));
// submodule f_run_halt_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_run_halt_rsps$D_IN),
.ENQ(f_run_halt_rsps$ENQ),
.DEQ(f_run_halt_rsps$DEQ),
.CLR(f_run_halt_rsps$CLR),
.D_OUT(f_run_halt_rsps$D_OUT),
.FULL_N(f_run_halt_rsps$FULL_N),
.EMPTY_N(f_run_halt_rsps$EMPTY_N));
// submodule fetchStage
mkFetchStage fetchStage(.CLK(CLK),
.RST_N(RST_N),
.iMemIfc_perf_req_r(fetchStage$iMemIfc_perf_req_r),
.iMemIfc_perf_setStatus_doStats(fetchStage$iMemIfc_perf_setStatus_doStats),
.iMemIfc_to_parent_fromP_enq_x(fetchStage$iMemIfc_to_parent_fromP_enq_x),
.iMemIfc_to_proc_request_put(fetchStage$iMemIfc_to_proc_request_put),
.iTlbIfc_perf_req_r(fetchStage$iTlbIfc_perf_req_r),
.iTlbIfc_perf_setStatus_doStats(fetchStage$iTlbIfc_perf_setStatus_doStats),
.iTlbIfc_toParent_rsFromP_enq_x(fetchStage$iTlbIfc_toParent_rsFromP_enq_x),
.iTlbIfc_to_proc_request_put(fetchStage$iTlbIfc_to_proc_request_put),
.iTlbIfc_updateVMInfo_vm(fetchStage$iTlbIfc_updateVMInfo_vm),
.mmioIfc_instResp_enq_x(fetchStage$mmioIfc_instResp_enq_x),
.mmioIfc_setHtifAddrs_fromHost(fetchStage$mmioIfc_setHtifAddrs_fromHost),
.mmioIfc_setHtifAddrs_toHost(fetchStage$mmioIfc_setHtifAddrs_toHost),
.perf_req_r(fetchStage$perf_req_r),
.perf_setStatus_doStats(fetchStage$perf_setStatus_doStats),
.redirect_pc(fetchStage$redirect_pc),
.start_pc(fetchStage$start_pc),
.train_predictors_dpTrain(fetchStage$train_predictors_dpTrain),
.train_predictors_iType(fetchStage$train_predictors_iType),
.train_predictors_isCompressed(fetchStage$train_predictors_isCompressed),
.train_predictors_mispred(fetchStage$train_predictors_mispred),
.train_predictors_next_pc(fetchStage$train_predictors_next_pc),
.train_predictors_pc(fetchStage$train_predictors_pc),
.train_predictors_taken(fetchStage$train_predictors_taken),
.EN_pipelines_0_deq(fetchStage$EN_pipelines_0_deq),
.EN_pipelines_1_deq(fetchStage$EN_pipelines_1_deq),
.EN_iTlbIfc_flush(fetchStage$EN_iTlbIfc_flush),
.EN_iTlbIfc_updateVMInfo(fetchStage$EN_iTlbIfc_updateVMInfo),
.EN_iTlbIfc_to_proc_request_put(fetchStage$EN_iTlbIfc_to_proc_request_put),
.EN_iTlbIfc_to_proc_response_get(fetchStage$EN_iTlbIfc_to_proc_response_get),
.EN_iTlbIfc_toParent_rqToP_deq(fetchStage$EN_iTlbIfc_toParent_rqToP_deq),
.EN_iTlbIfc_toParent_rsFromP_enq(fetchStage$EN_iTlbIfc_toParent_rsFromP_enq),
.EN_iTlbIfc_toParent_flush_request_get(fetchStage$EN_iTlbIfc_toParent_flush_request_get),
.EN_iTlbIfc_toParent_flush_response_put(fetchStage$EN_iTlbIfc_toParent_flush_response_put),
.EN_iTlbIfc_perf_setStatus(fetchStage$EN_iTlbIfc_perf_setStatus),
.EN_iTlbIfc_perf_req(fetchStage$EN_iTlbIfc_perf_req),
.EN_iTlbIfc_perf_resp(fetchStage$EN_iTlbIfc_perf_resp),
.EN_iMemIfc_to_proc_request_put(fetchStage$EN_iMemIfc_to_proc_request_put),
.EN_iMemIfc_to_proc_response_get(fetchStage$EN_iMemIfc_to_proc_response_get),
.EN_iMemIfc_flush(fetchStage$EN_iMemIfc_flush),
.EN_iMemIfc_perf_setStatus(fetchStage$EN_iMemIfc_perf_setStatus),
.EN_iMemIfc_perf_req(fetchStage$EN_iMemIfc_perf_req),
.EN_iMemIfc_perf_resp(fetchStage$EN_iMemIfc_perf_resp),
.EN_iMemIfc_to_parent_rsToP_deq(fetchStage$EN_iMemIfc_to_parent_rsToP_deq),
.EN_iMemIfc_to_parent_rqToP_deq(fetchStage$EN_iMemIfc_to_parent_rqToP_deq),
.EN_iMemIfc_to_parent_fromP_enq(fetchStage$EN_iMemIfc_to_parent_fromP_enq),
.EN_iMemIfc_cRqStuck_get(fetchStage$EN_iMemIfc_cRqStuck_get),
.EN_iMemIfc_pRqStuck_get(fetchStage$EN_iMemIfc_pRqStuck_get),
.EN_mmioIfc_instReq_deq(fetchStage$EN_mmioIfc_instReq_deq),
.EN_mmioIfc_instResp_enq(fetchStage$EN_mmioIfc_instResp_enq),
.EN_mmioIfc_setHtifAddrs(fetchStage$EN_mmioIfc_setHtifAddrs),
.EN_start(fetchStage$EN_start),
.EN_stop(fetchStage$EN_stop),
.EN_setWaitRedirect(fetchStage$EN_setWaitRedirect),
.EN_redirect(fetchStage$EN_redirect),
.EN_setWaitFlush(fetchStage$EN_setWaitFlush),
.EN_done_flushing(fetchStage$EN_done_flushing),
.EN_train_predictors(fetchStage$EN_train_predictors),
.EN_flush_predictors(fetchStage$EN_flush_predictors),
.EN_perf_setStatus(fetchStage$EN_perf_setStatus),
.EN_perf_req(fetchStage$EN_perf_req),
.EN_perf_resp(fetchStage$EN_perf_resp),
.pipelines_0_canDeq(fetchStage$pipelines_0_canDeq),
.RDY_pipelines_0_canDeq(),
.RDY_pipelines_0_deq(fetchStage$RDY_pipelines_0_deq),
.pipelines_0_first(fetchStage$pipelines_0_first),
.RDY_pipelines_0_first(fetchStage$RDY_pipelines_0_first),
.pipelines_1_canDeq(fetchStage$pipelines_1_canDeq),
.RDY_pipelines_1_canDeq(),
.RDY_pipelines_1_deq(fetchStage$RDY_pipelines_1_deq),
.pipelines_1_first(fetchStage$pipelines_1_first),
.RDY_pipelines_1_first(fetchStage$RDY_pipelines_1_first),
.iTlbIfc_flush_done(fetchStage$iTlbIfc_flush_done),
.RDY_iTlbIfc_flush_done(),
.RDY_iTlbIfc_flush(fetchStage$RDY_iTlbIfc_flush),
.RDY_iTlbIfc_updateVMInfo(),
.iTlbIfc_noPendingReq(fetchStage$iTlbIfc_noPendingReq),
.RDY_iTlbIfc_noPendingReq(),
.RDY_iTlbIfc_to_proc_request_put(),
.iTlbIfc_to_proc_response_get(),
.RDY_iTlbIfc_to_proc_response_get(),
.iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_notEmpty(),
.RDY_iTlbIfc_toParent_rqToP_deq(fetchStage$RDY_iTlbIfc_toParent_rqToP_deq),
.iTlbIfc_toParent_rqToP_first(fetchStage$iTlbIfc_toParent_rqToP_first),
.RDY_iTlbIfc_toParent_rqToP_first(fetchStage$RDY_iTlbIfc_toParent_rqToP_first),
.iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_notFull(),
.RDY_iTlbIfc_toParent_rsFromP_enq(fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq),
.RDY_iTlbIfc_toParent_flush_request_get(fetchStage$RDY_iTlbIfc_toParent_flush_request_get),
.RDY_iTlbIfc_toParent_flush_response_put(fetchStage$RDY_iTlbIfc_toParent_flush_response_put),
.RDY_iTlbIfc_perf_setStatus(),
.RDY_iTlbIfc_perf_req(),
.iTlbIfc_perf_resp(),
.RDY_iTlbIfc_perf_resp(),
.iTlbIfc_perf_respValid(),
.RDY_iTlbIfc_perf_respValid(),
.RDY_iMemIfc_to_proc_request_put(),
.iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_to_proc_response_get(),
.RDY_iMemIfc_flush(),
.iMemIfc_flush_done(fetchStage$iMemIfc_flush_done),
.RDY_iMemIfc_flush_done(),
.RDY_iMemIfc_perf_setStatus(),
.RDY_iMemIfc_perf_req(),
.iMemIfc_perf_resp(),
.RDY_iMemIfc_perf_resp(),
.iMemIfc_perf_respValid(),
.RDY_iMemIfc_perf_respValid(),
.iMemIfc_to_parent_rsToP_notEmpty(fetchStage$iMemIfc_to_parent_rsToP_notEmpty),
.RDY_iMemIfc_to_parent_rsToP_notEmpty(),
.RDY_iMemIfc_to_parent_rsToP_deq(fetchStage$RDY_iMemIfc_to_parent_rsToP_deq),
.iMemIfc_to_parent_rsToP_first(fetchStage$iMemIfc_to_parent_rsToP_first),
.RDY_iMemIfc_to_parent_rsToP_first(fetchStage$RDY_iMemIfc_to_parent_rsToP_first),
.iMemIfc_to_parent_rqToP_notEmpty(fetchStage$iMemIfc_to_parent_rqToP_notEmpty),
.RDY_iMemIfc_to_parent_rqToP_notEmpty(),
.RDY_iMemIfc_to_parent_rqToP_deq(fetchStage$RDY_iMemIfc_to_parent_rqToP_deq),
.iMemIfc_to_parent_rqToP_first(fetchStage$iMemIfc_to_parent_rqToP_first),
.RDY_iMemIfc_to_parent_rqToP_first(fetchStage$RDY_iMemIfc_to_parent_rqToP_first),
.iMemIfc_to_parent_fromP_notFull(fetchStage$iMemIfc_to_parent_fromP_notFull),
.RDY_iMemIfc_to_parent_fromP_notFull(),
.RDY_iMemIfc_to_parent_fromP_enq(fetchStage$RDY_iMemIfc_to_parent_fromP_enq),
.iMemIfc_cRqStuck_get(fetchStage$iMemIfc_cRqStuck_get),
.RDY_iMemIfc_cRqStuck_get(fetchStage$RDY_iMemIfc_cRqStuck_get),
.iMemIfc_pRqStuck_get(fetchStage$iMemIfc_pRqStuck_get),
.RDY_iMemIfc_pRqStuck_get(fetchStage$RDY_iMemIfc_pRqStuck_get),
.mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_notEmpty(),
.RDY_mmioIfc_instReq_deq(fetchStage$RDY_mmioIfc_instReq_deq),
.mmioIfc_instReq_first_fst(fetchStage$mmioIfc_instReq_first_fst),
.RDY_mmioIfc_instReq_first_fst(fetchStage$RDY_mmioIfc_instReq_first_fst),
.mmioIfc_instReq_first_snd(fetchStage$mmioIfc_instReq_first_snd),
.RDY_mmioIfc_instReq_first_snd(fetchStage$RDY_mmioIfc_instReq_first_snd),
.mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_notFull(),
.RDY_mmioIfc_instResp_enq(fetchStage$RDY_mmioIfc_instResp_enq),
.RDY_mmioIfc_setHtifAddrs(),
.RDY_start(),
.RDY_stop(),
.RDY_setWaitRedirect(),
.RDY_redirect(),
.RDY_setWaitFlush(),
.RDY_done_flushing(fetchStage$RDY_done_flushing),
.RDY_train_predictors(),
.emptyForFlush(fetchStage$emptyForFlush),
.RDY_emptyForFlush(),
.RDY_flush_predictors(),
.flush_predictors_done(fetchStage$flush_predictors_done),
.RDY_flush_predictors_done(),
.getFetchState(),
.RDY_getFetchState(),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule l2Tlb
mkL2Tlb l2Tlb(.CLK(CLK),
.RST_N(RST_N),
.perf_req_r(l2Tlb$perf_req_r),
.perf_setStatus_doStats(l2Tlb$perf_setStatus_doStats),
.toChildren_rqFromC_put(l2Tlb$toChildren_rqFromC_put),
.toMem_respLd_enq_x(l2Tlb$toMem_respLd_enq_x),
.updateVMInfo_vmD(l2Tlb$updateVMInfo_vmD),
.updateVMInfo_vmI(l2Tlb$updateVMInfo_vmI),
.EN_updateVMInfo(l2Tlb$EN_updateVMInfo),
.EN_toChildren_rqFromC_put(l2Tlb$EN_toChildren_rqFromC_put),
.EN_toChildren_rsToC_deq(l2Tlb$EN_toChildren_rsToC_deq),
.EN_toChildren_iTlbReqFlush_put(l2Tlb$EN_toChildren_iTlbReqFlush_put),
.EN_toChildren_dTlbReqFlush_put(l2Tlb$EN_toChildren_dTlbReqFlush_put),
.EN_toChildren_flushDone_get(l2Tlb$EN_toChildren_flushDone_get),
.EN_toMem_memReq_deq(l2Tlb$EN_toMem_memReq_deq),
.EN_toMem_respLd_enq(l2Tlb$EN_toMem_respLd_enq),
.EN_perf_setStatus(l2Tlb$EN_perf_setStatus),
.EN_perf_req(l2Tlb$EN_perf_req),
.EN_perf_resp(l2Tlb$EN_perf_resp),
.RDY_updateVMInfo(),
.RDY_toChildren_rqFromC_put(l2Tlb$RDY_toChildren_rqFromC_put),
.toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_notEmpty(),
.RDY_toChildren_rsToC_deq(l2Tlb$RDY_toChildren_rsToC_deq),
.toChildren_rsToC_first(l2Tlb$toChildren_rsToC_first),
.RDY_toChildren_rsToC_first(l2Tlb$RDY_toChildren_rsToC_first),
.RDY_toChildren_iTlbReqFlush_put(l2Tlb$RDY_toChildren_iTlbReqFlush_put),
.RDY_toChildren_dTlbReqFlush_put(l2Tlb$RDY_toChildren_dTlbReqFlush_put),
.RDY_toChildren_flushDone_get(l2Tlb$RDY_toChildren_flushDone_get),
.toMem_memReq_notEmpty(l2Tlb$toMem_memReq_notEmpty),
.RDY_toMem_memReq_notEmpty(),
.RDY_toMem_memReq_deq(l2Tlb$RDY_toMem_memReq_deq),
.toMem_memReq_first(l2Tlb$toMem_memReq_first),
.RDY_toMem_memReq_first(l2Tlb$RDY_toMem_memReq_first),
.toMem_respLd_notFull(l2Tlb$toMem_respLd_notFull),
.RDY_toMem_respLd_notFull(),
.RDY_toMem_respLd_enq(l2Tlb$RDY_toMem_respLd_enq),
.RDY_perf_setStatus(),
.RDY_perf_req(),
.perf_resp(),
.RDY_perf_resp(),
.perf_respValid(),
.RDY_perf_respValid());
// submodule mmio_cRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_cRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_cRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_cRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_cRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_cRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_cRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_cRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_cRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_cRsQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataPendQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataPendQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataPendQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataPendQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataPendQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataPendQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataPendQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataPendQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataReqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataReqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataReqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataReqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_clearReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_dataRespQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_dataRespQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_deqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_dataRespQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_0$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_1$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_dataRespQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_dataRespQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_dataRespQ_enqReq_dummy2_2$D_IN),
.EN(mmio_dataRespQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_dataRespQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRqQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRqQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRqQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRqQ_enqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) mmio_pRsQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_clearReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_clearReq_dummy2_1$EN),
.Q_OUT(mmio_pRsQ_clearReq_dummy2_1$Q_OUT));
// submodule mmio_pRsQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_deqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_deqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_deqReq_dummy2_2$Q_OUT));
// submodule mmio_pRsQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_0$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_1$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule mmio_pRsQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) mmio_pRsQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(mmio_pRsQ_enqReq_dummy2_2$D_IN),
.EN(mmio_pRsQ_enqReq_dummy2_2$EN),
.Q_OUT(mmio_pRsQ_enqReq_dummy2_2$Q_OUT));
// submodule perfReqQ
FIFO1 #(.width(32'd9), .guarded(32'd1)) perfReqQ(.RST(RST_N),
.CLK(CLK),
.D_IN(perfReqQ$D_IN),
.ENQ(perfReqQ$ENQ),
.DEQ(perfReqQ$DEQ),
.CLR(perfReqQ$CLR),
.D_OUT(perfReqQ$D_OUT),
.FULL_N(perfReqQ$FULL_N),
.EMPTY_N(perfReqQ$EMPTY_N));
// submodule regRenamingTable
mkRegRenamingTable regRenamingTable(.CLK(CLK),
.RST_N(RST_N),
.rename_0_claimRename_r(regRenamingTable$rename_0_claimRename_r),
.rename_0_claimRename_sb(regRenamingTable$rename_0_claimRename_sb),
.rename_0_getRename_r(regRenamingTable$rename_0_getRename_r),
.rename_1_claimRename_r(regRenamingTable$rename_1_claimRename_r),
.rename_1_claimRename_sb(regRenamingTable$rename_1_claimRename_sb),
.rename_1_getRename_r(regRenamingTable$rename_1_getRename_r),
.specUpdate_correctSpeculation_mask(regRenamingTable$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(regRenamingTable$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(regRenamingTable$specUpdate_incorrectSpeculation_kill_tag),
.EN_rename_0_claimRename(regRenamingTable$EN_rename_0_claimRename),
.EN_rename_1_claimRename(regRenamingTable$EN_rename_1_claimRename),
.EN_commit_0_commit(regRenamingTable$EN_commit_0_commit),
.EN_commit_1_commit(regRenamingTable$EN_commit_1_commit),
.EN_specUpdate_incorrectSpeculation(regRenamingTable$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(regRenamingTable$EN_specUpdate_correctSpeculation),
.rename_0_getRename(regRenamingTable$rename_0_getRename),
.RDY_rename_0_getRename(regRenamingTable$RDY_rename_0_getRename),
.RDY_rename_0_claimRename(regRenamingTable$RDY_rename_0_claimRename),
.rename_0_canRename(regRenamingTable$rename_0_canRename),
.RDY_rename_0_canRename(),
.rename_1_getRename(regRenamingTable$rename_1_getRename),
.RDY_rename_1_getRename(regRenamingTable$RDY_rename_1_getRename),
.RDY_rename_1_claimRename(regRenamingTable$RDY_rename_1_claimRename),
.rename_1_canRename(regRenamingTable$rename_1_canRename),
.RDY_rename_1_canRename(),
.RDY_commit_0_commit(regRenamingTable$RDY_commit_0_commit),
.commit_0_canCommit(),
.RDY_commit_0_canCommit(),
.RDY_commit_1_commit(regRenamingTable$RDY_commit_1_commit),
.commit_1_canCommit(),
.RDY_commit_1_canCommit(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule rf
mkRFileSynth rf(.CLK(CLK),
.RST_N(RST_N),
.read_0_rd1_rindx(rf$read_0_rd1_rindx),
.read_0_rd2_rindx(rf$read_0_rd2_rindx),
.read_0_rd3_rindx(rf$read_0_rd3_rindx),
.read_1_rd1_rindx(rf$read_1_rd1_rindx),
.read_1_rd2_rindx(rf$read_1_rd2_rindx),
.read_1_rd3_rindx(rf$read_1_rd3_rindx),
.read_2_rd1_rindx(rf$read_2_rd1_rindx),
.read_2_rd2_rindx(rf$read_2_rd2_rindx),
.read_2_rd3_rindx(rf$read_2_rd3_rindx),
.read_3_rd1_rindx(rf$read_3_rd1_rindx),
.read_3_rd2_rindx(rf$read_3_rd2_rindx),
.read_3_rd3_rindx(rf$read_3_rd3_rindx),
.read_4_rd1_rindx(rf$read_4_rd1_rindx),
.read_4_rd2_rindx(rf$read_4_rd2_rindx),
.read_4_rd3_rindx(rf$read_4_rd3_rindx),
.write_0_wr_data(rf$write_0_wr_data),
.write_0_wr_rindx(rf$write_0_wr_rindx),
.write_1_wr_data(rf$write_1_wr_data),
.write_1_wr_rindx(rf$write_1_wr_rindx),
.write_2_wr_data(rf$write_2_wr_data),
.write_2_wr_rindx(rf$write_2_wr_rindx),
.write_3_wr_data(rf$write_3_wr_data),
.write_3_wr_rindx(rf$write_3_wr_rindx),
.write_4_wr_data(rf$write_4_wr_data),
.write_4_wr_rindx(rf$write_4_wr_rindx),
.EN_write_0_wr(rf$EN_write_0_wr),
.EN_write_1_wr(rf$EN_write_1_wr),
.EN_write_2_wr(rf$EN_write_2_wr),
.EN_write_3_wr(rf$EN_write_3_wr),
.EN_write_4_wr(rf$EN_write_4_wr),
.RDY_write_0_wr(),
.RDY_write_1_wr(),
.RDY_write_2_wr(),
.RDY_write_3_wr(),
.RDY_write_4_wr(),
.read_0_rd1(rf$read_0_rd1),
.RDY_read_0_rd1(),
.read_0_rd2(rf$read_0_rd2),
.RDY_read_0_rd2(),
.read_0_rd3(),
.RDY_read_0_rd3(),
.read_1_rd1(rf$read_1_rd1),
.RDY_read_1_rd1(),
.read_1_rd2(rf$read_1_rd2),
.RDY_read_1_rd2(),
.read_1_rd3(),
.RDY_read_1_rd3(),
.read_2_rd1(rf$read_2_rd1),
.RDY_read_2_rd1(),
.read_2_rd2(rf$read_2_rd2),
.RDY_read_2_rd2(),
.read_2_rd3(rf$read_2_rd3),
.RDY_read_2_rd3(),
.read_3_rd1(rf$read_3_rd1),
.RDY_read_3_rd1(),
.read_3_rd2(rf$read_3_rd2),
.RDY_read_3_rd2(),
.read_3_rd3(),
.RDY_read_3_rd3(),
.read_4_rd1(rf$read_4_rd1),
.RDY_read_4_rd1(),
.read_4_rd2(),
.RDY_read_4_rd2(),
.read_4_rd3(),
.RDY_read_4_rd3());
// submodule rob
mkReorderBufferSynth rob(.CLK(CLK),
.RST_N(RST_N),
.enqPort_0_enq_x(rob$enqPort_0_enq_x),
.enqPort_1_enq_x(rob$enqPort_1_enq_x),
.getOrigPC_0_get_x(rob$getOrigPC_0_get_x),
.getOrigPC_1_get_x(rob$getOrigPC_1_get_x),
.getOrigPC_2_get_x(rob$getOrigPC_2_get_x),
.getOrigPredPC_0_get_x(rob$getOrigPredPC_0_get_x),
.getOrigPredPC_1_get_x(rob$getOrigPredPC_1_get_x),
.getOrig_Inst_0_get_x(rob$getOrig_Inst_0_get_x),
.getOrig_Inst_1_get_x(rob$getOrig_Inst_1_get_x),
.setExecuted_deqLSQ_cause(rob$setExecuted_deqLSQ_cause),
.setExecuted_deqLSQ_ld_killed(rob$setExecuted_deqLSQ_ld_killed),
.setExecuted_deqLSQ_x(rob$setExecuted_deqLSQ_x),
.setExecuted_doFinishAlu_0_set_cf(rob$setExecuted_doFinishAlu_0_set_cf),
.setExecuted_doFinishAlu_0_set_csrData(rob$setExecuted_doFinishAlu_0_set_csrData),
.setExecuted_doFinishAlu_0_set_x(rob$setExecuted_doFinishAlu_0_set_x),
.setExecuted_doFinishAlu_1_set_cf(rob$setExecuted_doFinishAlu_1_set_cf),
.setExecuted_doFinishAlu_1_set_csrData(rob$setExecuted_doFinishAlu_1_set_csrData),
.setExecuted_doFinishAlu_1_set_x(rob$setExecuted_doFinishAlu_1_set_x),
.setExecuted_doFinishFpuMulDiv_0_set_fflags(rob$setExecuted_doFinishFpuMulDiv_0_set_fflags),
.setExecuted_doFinishFpuMulDiv_0_set_x(rob$setExecuted_doFinishFpuMulDiv_0_set_x),
.setExecuted_doFinishMem_access_at_commit(rob$setExecuted_doFinishMem_access_at_commit),
.setExecuted_doFinishMem_non_mmio_st_done(rob$setExecuted_doFinishMem_non_mmio_st_done),
.setExecuted_doFinishMem_vaddr(rob$setExecuted_doFinishMem_vaddr),
.setExecuted_doFinishMem_x(rob$setExecuted_doFinishMem_x),
.setLSQAtCommitNotified_x(rob$setLSQAtCommitNotified_x),
.specUpdate_correctSpeculation_mask(rob$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_inst_tag(rob$specUpdate_incorrectSpeculation_inst_tag),
.specUpdate_incorrectSpeculation_kill_all(rob$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_spec_tag(rob$specUpdate_incorrectSpeculation_spec_tag),
.EN_enqPort_0_enq(rob$EN_enqPort_0_enq),
.EN_enqPort_1_enq(rob$EN_enqPort_1_enq),
.EN_deqPort_0_deq(rob$EN_deqPort_0_deq),
.EN_deqPort_1_deq(rob$EN_deqPort_1_deq),
.EN_setLSQAtCommitNotified(rob$EN_setLSQAtCommitNotified),
.EN_setExecuted_deqLSQ(rob$EN_setExecuted_deqLSQ),
.EN_setExecuted_doFinishAlu_0_set(rob$EN_setExecuted_doFinishAlu_0_set),
.EN_setExecuted_doFinishAlu_1_set(rob$EN_setExecuted_doFinishAlu_1_set),
.EN_setExecuted_doFinishFpuMulDiv_0_set(rob$EN_setExecuted_doFinishFpuMulDiv_0_set),
.EN_setExecuted_doFinishMem(rob$EN_setExecuted_doFinishMem),
.EN_specUpdate_incorrectSpeculation(rob$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(rob$EN_specUpdate_correctSpeculation),
.enqPort_0_canEnq(rob$enqPort_0_canEnq),
.RDY_enqPort_0_canEnq(),
.RDY_enqPort_0_enq(rob$RDY_enqPort_0_enq),
.enqPort_0_getEnqInstTag(rob$enqPort_0_getEnqInstTag),
.RDY_enqPort_0_getEnqInstTag(),
.enqPort_1_canEnq(rob$enqPort_1_canEnq),
.RDY_enqPort_1_canEnq(),
.RDY_enqPort_1_enq(rob$RDY_enqPort_1_enq),
.enqPort_1_getEnqInstTag(rob$enqPort_1_getEnqInstTag),
.RDY_enqPort_1_getEnqInstTag(),
.isEmpty(rob$isEmpty),
.RDY_isEmpty(),
.deqPort_0_canDeq(rob$deqPort_0_canDeq),
.RDY_deqPort_0_canDeq(),
.RDY_deqPort_0_deq(rob$RDY_deqPort_0_deq),
.deqPort_0_getDeqInstTag(rob$deqPort_0_getDeqInstTag),
.RDY_deqPort_0_getDeqInstTag(),
.deqPort_0_deq_data(rob$deqPort_0_deq_data),
.RDY_deqPort_0_deq_data(rob$RDY_deqPort_0_deq_data),
.deqPort_1_canDeq(rob$deqPort_1_canDeq),
.RDY_deqPort_1_canDeq(),
.RDY_deqPort_1_deq(rob$RDY_deqPort_1_deq),
.deqPort_1_getDeqInstTag(),
.RDY_deqPort_1_getDeqInstTag(),
.deqPort_1_deq_data(rob$deqPort_1_deq_data),
.RDY_deqPort_1_deq_data(rob$RDY_deqPort_1_deq_data),
.RDY_setLSQAtCommitNotified(rob$RDY_setLSQAtCommitNotified),
.RDY_setExecuted_deqLSQ(rob$RDY_setExecuted_deqLSQ),
.RDY_setExecuted_doFinishAlu_0_set(rob$RDY_setExecuted_doFinishAlu_0_set),
.RDY_setExecuted_doFinishAlu_1_set(rob$RDY_setExecuted_doFinishAlu_1_set),
.RDY_setExecuted_doFinishFpuMulDiv_0_set(rob$RDY_setExecuted_doFinishFpuMulDiv_0_set),
.RDY_setExecuted_doFinishMem(rob$RDY_setExecuted_doFinishMem),
.getOrigPC_0_get(rob$getOrigPC_0_get),
.RDY_getOrigPC_0_get(),
.getOrigPC_1_get(rob$getOrigPC_1_get),
.RDY_getOrigPC_1_get(),
.getOrigPC_2_get(),
.RDY_getOrigPC_2_get(),
.getOrigPredPC_0_get(rob$getOrigPredPC_0_get),
.RDY_getOrigPredPC_0_get(),
.getOrigPredPC_1_get(rob$getOrigPredPC_1_get),
.RDY_getOrigPredPC_1_get(),
.getOrig_Inst_0_get(rob$getOrig_Inst_0_get),
.RDY_getOrig_Inst_0_get(),
.getOrig_Inst_1_get(rob$getOrig_Inst_1_get),
.RDY_getOrig_Inst_1_get(),
.getEnqTime(rob$getEnqTime),
.RDY_getEnqTime(),
.isEmpty_ehrPort0(),
.RDY_isEmpty_ehrPort0(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation());
// submodule sbAggr
mkScoreboardAggr sbAggr(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbAggr$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbAggr$eagerLookup_1_get_r),
.setBusy_0_set_dst(sbAggr$setBusy_0_set_dst),
.setBusy_1_set_dst(sbAggr$setBusy_1_set_dst),
.setReady_0_put(sbAggr$setReady_0_put),
.setReady_1_put(sbAggr$setReady_1_put),
.setReady_2_put(sbAggr$setReady_2_put),
.setReady_3_put(sbAggr$setReady_3_put),
.setReady_4_put(sbAggr$setReady_4_put),
.EN_setBusy_0_set(sbAggr$EN_setBusy_0_set),
.EN_setBusy_1_set(sbAggr$EN_setBusy_1_set),
.EN_setReady_0_put(sbAggr$EN_setReady_0_put),
.EN_setReady_1_put(sbAggr$EN_setReady_1_put),
.EN_setReady_2_put(sbAggr$EN_setReady_2_put),
.EN_setReady_3_put(sbAggr$EN_setReady_3_put),
.EN_setReady_4_put(sbAggr$EN_setReady_4_put),
.eagerLookup_0_get(sbAggr$eagerLookup_0_get),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(sbAggr$eagerLookup_1_get),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.RDY_setReady_4_put());
// submodule sbCons
mkScoreboardCons sbCons(.CLK(CLK),
.RST_N(RST_N),
.eagerLookup_0_get_r(sbCons$eagerLookup_0_get_r),
.eagerLookup_1_get_r(sbCons$eagerLookup_1_get_r),
.lazyLookup_0_get_r(sbCons$lazyLookup_0_get_r),
.lazyLookup_1_get_r(sbCons$lazyLookup_1_get_r),
.lazyLookup_2_get_r(sbCons$lazyLookup_2_get_r),
.lazyLookup_3_get_r(sbCons$lazyLookup_3_get_r),
.lazyLookup_4_get_r(sbCons$lazyLookup_4_get_r),
.setBusy_0_set_dst(sbCons$setBusy_0_set_dst),
.setBusy_1_set_dst(sbCons$setBusy_1_set_dst),
.setReady_0_put(sbCons$setReady_0_put),
.setReady_1_put(sbCons$setReady_1_put),
.setReady_2_put(sbCons$setReady_2_put),
.setReady_3_put(sbCons$setReady_3_put),
.setReady_4_put(sbCons$setReady_4_put),
.EN_setBusy_0_set(sbCons$EN_setBusy_0_set),
.EN_setBusy_1_set(sbCons$EN_setBusy_1_set),
.EN_setReady_0_put(sbCons$EN_setReady_0_put),
.EN_setReady_1_put(sbCons$EN_setReady_1_put),
.EN_setReady_2_put(sbCons$EN_setReady_2_put),
.EN_setReady_3_put(sbCons$EN_setReady_3_put),
.EN_setReady_4_put(sbCons$EN_setReady_4_put),
.eagerLookup_0_get(),
.RDY_eagerLookup_0_get(),
.eagerLookup_1_get(),
.RDY_eagerLookup_1_get(),
.RDY_setBusy_0_set(),
.RDY_setBusy_1_set(),
.RDY_setReady_0_put(),
.RDY_setReady_1_put(),
.RDY_setReady_2_put(),
.RDY_setReady_3_put(),
.RDY_setReady_4_put(),
.lazyLookup_0_get(sbCons$lazyLookup_0_get),
.RDY_lazyLookup_0_get(),
.lazyLookup_1_get(sbCons$lazyLookup_1_get),
.RDY_lazyLookup_1_get(),
.lazyLookup_2_get(sbCons$lazyLookup_2_get),
.RDY_lazyLookup_2_get(),
.lazyLookup_3_get(sbCons$lazyLookup_3_get),
.RDY_lazyLookup_3_get(),
.lazyLookup_4_get(),
.RDY_lazyLookup_4_get());
// submodule specTagManager
mkSpecTagManager specTagManager(.CLK(CLK),
.RST_N(RST_N),
.specUpdate_correctSpeculation_mask(specTagManager$specUpdate_correctSpeculation_mask),
.specUpdate_incorrectSpeculation_kill_all(specTagManager$specUpdate_incorrectSpeculation_kill_all),
.specUpdate_incorrectSpeculation_kill_tag(specTagManager$specUpdate_incorrectSpeculation_kill_tag),
.EN_claimSpecTag(specTagManager$EN_claimSpecTag),
.EN_specUpdate_incorrectSpeculation(specTagManager$EN_specUpdate_incorrectSpeculation),
.EN_specUpdate_correctSpeculation(specTagManager$EN_specUpdate_correctSpeculation),
.currentSpecBits(specTagManager$currentSpecBits),
.RDY_currentSpecBits(),
.nextSpecTag(specTagManager$nextSpecTag),
.RDY_nextSpecTag(specTagManager$RDY_nextSpecTag),
.RDY_claimSpecTag(specTagManager$RDY_claimSpecTag),
.canClaim(specTagManager$canClaim),
.RDY_canClaim(),
.RDY_specUpdate_incorrectSpeculation(),
.RDY_specUpdate_correctSpeculation(),
.isFull_ehrPort0(),
.RDY_isFull_ehrPort0());
// submodule v_f_to_TV_0
FIFO2 #(.width(32'd320), .guarded(32'd1)) v_f_to_TV_0(.RST(RST_N),
.CLK(CLK),
.D_IN(v_f_to_TV_0$D_IN),
.ENQ(v_f_to_TV_0$ENQ),
.DEQ(v_f_to_TV_0$DEQ),
.CLR(v_f_to_TV_0$CLR),
.D_OUT(v_f_to_TV_0$D_OUT),
.FULL_N(v_f_to_TV_0$FULL_N),
.EMPTY_N(v_f_to_TV_0$EMPTY_N));
// submodule v_f_to_TV_1
FIFO2 #(.width(32'd320), .guarded(32'd1)) v_f_to_TV_1(.RST(RST_N),
.CLK(CLK),
.D_IN(v_f_to_TV_1$D_IN),
.ENQ(v_f_to_TV_1$ENQ),
.DEQ(v_f_to_TV_1$DEQ),
.CLR(v_f_to_TV_1$CLR),
.D_OUT(v_f_to_TV_1$D_OUT),
.FULL_N(v_f_to_TV_1$FULL_N),
.EMPTY_N(v_f_to_TV_1$EMPTY_N));
// rule RL_rl_outOfReset
assign CAN_FIRE_RL_rl_outOfReset = !outOfReset ;
assign WILL_FIRE_RL_rl_outOfReset = CAN_FIRE_RL_rl_outOfReset ;
// rule RL_sendDTlbReq
assign CAN_FIRE_RL_sendDTlbReq =
coreFix_memExe_dTlb$RDY_toParent_rqToP_first &&
coreFix_memExe_dTlb$RDY_toParent_rqToP_deq &&
l2Tlb$RDY_toChildren_rqFromC_put ;
assign WILL_FIRE_RL_sendDTlbReq = CAN_FIRE_RL_sendDTlbReq ;
// rule RL_sendITlbReq
assign CAN_FIRE_RL_sendITlbReq =
l2Tlb$RDY_toChildren_rqFromC_put &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_first &&
fetchStage$RDY_iTlbIfc_toParent_rqToP_deq ;
assign WILL_FIRE_RL_sendITlbReq =
CAN_FIRE_RL_sendITlbReq && !WILL_FIRE_RL_sendDTlbReq ;
// rule RL_sendRsToDTlb
assign CAN_FIRE_RL_sendRsToDTlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
coreFix_memExe_dTlb$RDY_toParent_ldTransRsFromP_enq &&
l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToDTlb = CAN_FIRE_RL_sendRsToDTlb ;
// rule RL_sendRsToITlb
assign CAN_FIRE_RL_sendRsToITlb =
l2Tlb$RDY_toChildren_rsToC_first &&
l2Tlb$RDY_toChildren_rsToC_deq &&
fetchStage$RDY_iTlbIfc_toParent_rsFromP_enq &&
!l2Tlb$toChildren_rsToC_first[83] ;
assign WILL_FIRE_RL_sendRsToITlb = CAN_FIRE_RL_sendRsToITlb ;
// rule RL_mkConnectionGetPut
assign CAN_FIRE_RL_mkConnectionGetPut =
coreFix_memExe_dTlb$RDY_toParent_flush_request_get &&
l2Tlb$RDY_toChildren_dTlbReqFlush_put ;
assign WILL_FIRE_RL_mkConnectionGetPut = CAN_FIRE_RL_mkConnectionGetPut ;
// rule RL_mkConnectionGetPut_1
assign CAN_FIRE_RL_mkConnectionGetPut_1 =
l2Tlb$RDY_toChildren_iTlbReqFlush_put &&
fetchStage$RDY_iTlbIfc_toParent_flush_request_get ;
assign WILL_FIRE_RL_mkConnectionGetPut_1 =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
// rule RL_sendFlushDone
assign CAN_FIRE_RL_sendFlushDone =
coreFix_memExe_dTlb$RDY_toParent_flush_response_put &&
l2Tlb$RDY_toChildren_flushDone_get &&
fetchStage$RDY_iTlbIfc_toParent_flush_response_put ;
assign WILL_FIRE_RL_sendFlushDone = CAN_FIRE_RL_sendFlushDone ;
// rule RL_sendRobEnqTime
assign CAN_FIRE_RL_sendRobEnqTime = 1'd1 ;
assign WILL_FIRE_RL_sendRobEnqTime = 1'd1 ;
// rule RL_setDoFlushCaches
assign CAN_FIRE_RL_setDoFlushCaches =
flush_caches && fetchStage$emptyForFlush &&
coreFix_memExe_lsq$noWrongPathLoads ;
assign WILL_FIRE_RL_setDoFlushCaches = CAN_FIRE_RL_setDoFlushCaches ;
// rule RL_setDoFlushBrPred
assign CAN_FIRE_RL_setDoFlushBrPred =
flush_brpred && fetchStage$emptyForFlush ;
assign WILL_FIRE_RL_setDoFlushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
// rule RL_readyToFetch
assign CAN_FIRE_RL_readyToFetch =
fetchStage$RDY_done_flushing &&
rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247 &&
!flush_brpred &&
fetchStage$iMemIfc_flush_done &&
fetchStage$flush_predictors_done ;
assign WILL_FIRE_RL_readyToFetch = CAN_FIRE_RL_readyToFetch ;
// rule RL_flushCaches
assign CAN_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;
assign WILL_FIRE_RL_flushCaches = CAN_FIRE_RL_setDoFlushCaches ;
// rule RL_flushBrPred
assign CAN_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
assign WILL_FIRE_RL_flushBrPred = CAN_FIRE_RL_setDoFlushBrPred ;
// rule RL_rl_debug_gpr_read
assign CAN_FIRE_RL_rl_debug_gpr_read =
regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_gpr_read = CAN_FIRE_RL_rl_debug_gpr_read ;
// rule RL_rl_debug_gpr_access_busy
assign CAN_FIRE_RL_rl_debug_gpr_access_busy =
f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_gpr_access_busy =
CAN_FIRE_RL_rl_debug_gpr_access_busy ;
// rule RL_rl_debug_fpr_read
assign CAN_FIRE_RL_rl_debug_fpr_read =
regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$EMPTY_N &&
!f_fpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_fpr_read = CAN_FIRE_RL_rl_debug_fpr_read ;
// rule RL_rl_debug_fpr_access_busy
assign CAN_FIRE_RL_rl_debug_fpr_access_busy =
f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_fpr_access_busy =
CAN_FIRE_RL_rl_debug_fpr_access_busy ;
// rule RL_rl_debug_csr_access_busy
assign CAN_FIRE_RL_rl_debug_csr_access_busy =
f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_rl_debug_csr_access_busy =
CAN_FIRE_RL_rl_debug_csr_access_busy ;
// rule RL_rl_debug_halt_req
assign CAN_FIRE_RL_rl_debug_halt_req =
f_run_halt_reqs$EMPTY_N && !renameStage_rg_m_halt_req[4] &&
rg_core_run_state == 2'd2 &&
!f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_halt_req = CAN_FIRE_RL_rl_debug_halt_req ;
// rule RL_rl_debug_halt_req_already_halted
assign CAN_FIRE_RL_rl_debug_halt_req_already_halted =
f_run_halt_reqs$EMPTY_N && rg_core_run_state != 2'd2 &&
!f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_halt_req_already_halted =
CAN_FIRE_RL_rl_debug_halt_req_already_halted ;
// rule RL_rl_debug_halted
assign CAN_FIRE_RL_rl_debug_halted =
f_run_halt_rsps$FULL_N && rg_core_run_state == 2'd0 ;
assign WILL_FIRE_RL_rl_debug_halted = CAN_FIRE_RL_rl_debug_halted ;
// rule RL_rl_debug_run_redundant
assign CAN_FIRE_RL_rl_debug_run_redundant =
f_run_halt_reqs$EMPTY_N && f_run_halt_rsps$FULL_N &&
rg_core_run_state == 2'd2 &&
f_run_halt_reqs$D_OUT ;
assign WILL_FIRE_RL_rl_debug_run_redundant =
CAN_FIRE_RL_rl_debug_run_redundant ;
// rule RL_csrf_minstret_ehr_setRead
assign CAN_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_setRead = 1'd1 ;
// rule RL_csrf_mcycle_ehr_setRead
assign CAN_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_setRead = 1'd1 ;
// rule RL_rl_debug_csr_read
assign CAN_FIRE_RL_rl_debug_csr_read =
f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_csr_reqs$D_OUT[76] ;
assign WILL_FIRE_RL_rl_debug_csr_read = CAN_FIRE_RL_rl_debug_csr_read ;
// rule RL_rl_debug_csr_write
assign CAN_FIRE_RL_rl_debug_csr_write =
f_csr_reqs$EMPTY_N &&
f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403 &&
rg_core_run_state == 2'd1 &&
f_csr_reqs$D_OUT[76] ;
assign WILL_FIRE_RL_rl_debug_csr_write = CAN_FIRE_RL_rl_debug_csr_write ;
// rule RL_mmio_handlePRq
assign CAN_FIRE_RL_mmio_handlePRq =
!mmio_pRqQ_empty && !mmio_cRsQ_full &&
(!csrInstOrInterruptInflight_dummy2_0$Q_OUT ||
!csrInstOrInterruptInflight_dummy2_1$Q_OUT ||
!csrInstOrInterruptInflight_rl) ;
assign WILL_FIRE_RL_mmio_handlePRq = CAN_FIRE_RL_mmio_handlePRq ;
// rule RL_mmio_sendDataReq
assign CAN_FIRE_RL_mmio_sendDataReq =
!mmio_dataReqQ_empty && !mmio_cRqQ_full ;
assign WILL_FIRE_RL_mmio_sendDataReq = CAN_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendInstReq
assign CAN_FIRE_RL_mmio_sendInstReq =
!mmio_cRqQ_full && fetchStage$RDY_mmioIfc_instReq_first_snd &&
fetchStage$RDY_mmioIfc_instReq_first_fst &&
fetchStage$RDY_mmioIfc_instReq_deq ;
assign WILL_FIRE_RL_mmio_sendInstReq =
CAN_FIRE_RL_mmio_sendInstReq && !WILL_FIRE_RL_mmio_sendDataReq ;
// rule RL_mmio_sendDataResp
assign CAN_FIRE_RL_mmio_sendDataResp =
!mmio_dataRespQ_full && !mmio_pRsQ_empty &&
mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendDataResp = CAN_FIRE_RL_mmio_sendDataResp ;
// rule RL_mmio_sendInstResp
assign CAN_FIRE_RL_mmio_sendInstResp =
!mmio_pRsQ_empty && fetchStage$RDY_mmioIfc_instResp_enq &&
!mmio_pRsQ_data_0[66] ;
assign WILL_FIRE_RL_mmio_sendInstResp = CAN_FIRE_RL_mmio_sendInstResp ;
// rule RL_mmio_cRqQ_canonicalize
assign CAN_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRqQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_canonicalize
assign CAN_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRsQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_canonicalize
assign CAN_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_canonicalize = 1'd1 ;
// rule RL_mmio_cRsQ_enqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_deqReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_cRsQ_clearReq_canon
assign CAN_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_cRsQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_doFetchTrainBP
assign CAN_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP = coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_doFetchTrainBP_1
assign CAN_FIRE_RL_coreFix_doFetchTrainBP_1 = coreFix_trainBPQ_0$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_doFetchTrainBP_1 =
coreFix_trainBPQ_0$EMPTY_N && !coreFix_trainBPQ_1$EMPTY_N ;
// rule RL_coreFix_memExe_doIssueSB
assign CAN_FIRE_RL_coreFix_memExe_doIssueSB =
(!coreFix_memExe_reqStQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqStQ_full_rl) &&
coreFix_memExe_stb$RDY_issue ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueSB =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_lsq$firstLd[101] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchLdQ &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
coreFix_memExe_lsq$firstLd[16] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstLd[90] || coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// rule RL_coreFix_memExe_dMem_perfReqQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_perfReqQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$FULL_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_sendRsToP_pRq_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$EMPTY_N ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$EMPTY_N &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$FULL_N &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[3] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ;
// rule RL_renameStage_doRenaming_wrongPath
assign CAN_FIRE_RL_renameStage_doRenaming_wrongPath =
fetchStage$RDY_pipelines_0_first &&
(!fetchStage$pipelines_0_canDeq ||
epochManager$checkEpoch_0_check ||
fetchStage$RDY_pipelines_0_deq) &&
NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712 &&
!epochManager$checkEpoch_0_check ;
assign WILL_FIRE_RL_renameStage_doRenaming_wrongPath =
CAN_FIRE_RL_renameStage_doRenaming_wrongPath ;
// rule RL_commitStage_doCommitTrap_flush
assign CAN_FIRE_RL_commitStage_doCommitTrap_flush =
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
v_f_to_TV_0$FULL_N &&
(rob$deqPort_0_deq_data[12] ||
epochManager$RDY_incrementEpoch) &&
!commitStage_rg_run_state &&
!commitStage_commitTrap[133] &&
rob$deqPort_0_deq_data[167] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_flush =
CAN_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_doCommitTrap_handle
assign CAN_FIRE_RL_commitStage_doCommitTrap_handle =
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506 &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530 &&
!commitStage_rg_run_state &&
commitStage_commitTrap[133] ;
assign WILL_FIRE_RL_commitStage_doCommitTrap_handle =
CAN_FIRE_RL_commitStage_doCommitTrap_handle &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_commitStage_doCommitKilledLd
assign CAN_FIRE_RL_commitStage_doCommitKilledLd =
epochManager$RDY_incrementEpoch && rob$RDY_deqPort_0_deq_data &&
rob$RDY_deqPort_0_deq &&
!commitStage_rg_run_state &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[18] ;
assign WILL_FIRE_RL_commitStage_doCommitKilledLd =
CAN_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_commitStage_doCommitSystemInst
assign CAN_FIRE_RL_commitStage_doCommitSystemInst =
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689 &&
NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 &&
(rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ;
assign WILL_FIRE_RL_commitStage_doCommitSystemInst =
CAN_FIRE_RL_commitStage_doCommitSystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_csr_write &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_csrf_incCycle
assign CAN_FIRE_RL_csrf_incCycle = 1'd1 ;
assign WILL_FIRE_RL_csrf_incCycle = 1'd1 ;
// rule RL_csrf_mcycle_ehr_data_canon
assign CAN_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_mcycle_ehr_data_canon = 1'd1 ;
// rule RL_commitStage_notifyLSQCommit
assign CAN_FIRE_RL_commitStage_notifyLSQCommit =
rob$RDY_setLSQAtCommitNotified && rob$RDY_deqPort_0_deq_data &&
!commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[25] &&
rob$deqPort_0_deq_data[15] &&
!rob$deqPort_0_deq_data[14] ;
assign WILL_FIRE_RL_commitStage_notifyLSQCommit =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
// rule RL_commitStage_doCommitNormalInst
assign CAN_FIRE_RL_commitStage_doCommitNormalInst =
rob$RDY_deqPort_0_deq_data &&
NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930 &&
NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd21 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20 ;
assign WILL_FIRE_RL_commitStage_doCommitNormalInst =
CAN_FIRE_RL_commitStage_doCommitNormalInst ;
// rule RL_csrf_minstret_ehr_data_canon
assign CAN_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
assign WILL_FIRE_RL_csrf_minstret_ehr_data_canon = 1'd1 ;
// rule RL_coreFix_aluExe_1_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_1$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
!WILL_FIRE_RL_rl_debug_resume ;
// rule RL_coreFix_aluExe_0_doFinishAlu_T
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
epochManager$RDY_incrementEpoch &&
coreFix_trainBPQ_0$FULL_N ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doExeMem &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault &&
!WILL_FIRE_RL_rl_debug_resume ;
// rule RL_coreFix_aluExe_0_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
!coreFix_aluExe_0_exeToFinQ$first[17] &&
coreFix_aluExe_0_exeToFinQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doFinishAlu_F
assign CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
!coreFix_aluExe_1_exeToFinQ$first[17] &&
coreFix_aluExe_1_exeToFinQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F =
CAN_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ;
// rule RL_coreFix_aluExe_1_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu =
coreFix_aluExe_1_regToExeQ$RDY_deq &&
coreFix_aluExe_1_exeToFinQ$RDY_enq &&
coreFix_aluExe_1_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doExeAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu =
coreFix_aluExe_0_regToExeQ$RDY_deq &&
coreFix_aluExe_0_exeToFinQ$RDY_enq &&
coreFix_aluExe_0_regToExeQ$RDY_first ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
coreFix_aluExe_1_dispToRegQ$RDY_deq &&
coreFix_aluExe_1_regToExeQ$RDY_enq &&
coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_1_dispToRegQ_first__1311_BIT_13_ETC___d11396 ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doRegReadAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
coreFix_aluExe_0_dispToRegQ$RDY_deq &&
coreFix_aluExe_0_regToExeQ$RDY_enq &&
coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227 ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doRegReadAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_0_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
coreFix_aluExe_0_dispToRegQ$RDY_enq &&
coreFix_aluExe_0_rsAlu$RDY_doDispatch &&
coreFix_aluExe_0_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_aluExe_1_doDispatchAlu
assign CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
coreFix_aluExe_1_dispToRegQ$RDY_enq &&
coreFix_aluExe_1_rsAlu$RDY_doDispatch &&
coreFix_aluExe_1_rsAlu$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu =
CAN_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSimple
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_first &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpFma
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_deq &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntMul
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_fpuMulDivExe_0_doFinishIntDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_deq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8101 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
!WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
// rule RL_coreFix_memExe_doDeqLdQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_lsq$firstLd[7] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_Ld_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
!coreFix_memExe_lsq$firstLd[7] &&
!coreFix_memExe_lsq$firstLd[101] &&
!coreFix_memExe_lsq$firstLd[16] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ;
// rule RL_coreFix_memExe_doDeqLdQ_Lr_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqLdQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doFinishMem
assign CAN_FIRE_RL_coreFix_memExe_doFinishMem =
rob$RDY_setExecuted_doFinishMem &&
coreFix_memExe_dTlb$RDY_deqProcResp &&
coreFix_memExe_dTlb$RDY_procResp ;
assign WILL_FIRE_RL_coreFix_memExe_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
!coreFix_memExe_lsq$firstSt[77] &&
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1 ||
coreFix_memExe_lsq$firstSt[158:157] == 2'd2) &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
coreFix_memExe_stb$noMatchStQ &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_issue
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
!mmio_dataReqQ_full && !mmio_dataPendQ_full &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] != 2'd3 &&
coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd0 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
// rule RL_mmio_dataReqQ_canonicalize
assign CAN_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataReqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataReqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataReqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLrScAmoToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
(!coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
!coreFix_memExe_reqLrScAmoQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_doIssueLdFromIssueQ
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
coreFix_memExe_lsq$RDY_getIssueLd &&
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doIssueLdFromUpdate
assign CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
!coreFix_memExe_forwardQ_full &&
NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 &&
coreFix_memExe_issueLd$whas ;
assign WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate =
CAN_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_lsq$firstSt[4] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_Fence
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
rob$RDY_setExecuted_deqLSQ && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd3 &&
(!coreFix_memExe_lsq$firstSt[151] ||
coreFix_memExe_stb$isEmpty) ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_ScAmo_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
!coreFix_memExe_respLrScAmoQ_empty &&
rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] == 2'd2 ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_deq
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_coreFix_memExe_doDeqStQ_MMIO_fault
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
!mmio_dataRespQ_empty &&
NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd0 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd1 &&
coreFix_memExe_waitLrScAmoMMIOResp[2:1] != 2'd2 &&
!coreFix_memExe_waitLrScAmoMMIOResp[0] &&
!mmio_dataRespQ_data_0[64] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ;
// rule RL_mmio_dataRespQ_canonicalize
assign CAN_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataRespQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataRespQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataRespQ_clearReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_canonicalize
assign CAN_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_canonicalize = 1'd1 ;
// rule RL_mmio_dataPendQ_enqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_deqReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_dataPendQ_clearReq_canon
assign CAN_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_dataPendQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_sendLdToMem
assign CAN_FIRE_RL_coreFix_memExe_sendLdToMem =
(!coreFix_memExe_reqLdQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_reqLdQ_empty_lat_0$whas ||
!coreFix_memExe_reqLdQ_empty_rl) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 ;
assign WILL_FIRE_RL_coreFix_memExe_sendLdToMem =
CAN_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_sendStToMem
assign CAN_FIRE_RL_coreFix_memExe_sendStToMem =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 &&
(!coreFix_memExe_reqStQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_reqStQ_empty_dummy2_2$Q_OUT ||
CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
!coreFix_memExe_reqStQ_empty_rl) ;
assign WILL_FIRE_RL_coreFix_memExe_sendStToMem =
CAN_FIRE_RL_coreFix_memExe_sendStToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
!WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673 &&
!coreFix_memExe_dMem_cache_m_banks_0_processAmo[160] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd0 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] !=
2'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doDeqStQ_St_Mem
assign CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
coreFix_memExe_stb$RDY_enq && coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt &&
!coreFix_memExe_lsq$firstSt[4] &&
coreFix_memExe_lsq$firstSt[158:157] == 2'd0 &&
!coreFix_memExe_lsq$firstSt[77] &&
coreFix_memExe_stb$getEnqIndex[2] ;
assign WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem =
CAN_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doRespLdMem
assign CAN_FIRE_RL_coreFix_memExe_doRespLdMem =
!coreFix_memExe_memRespLdQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdMem =
CAN_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_coreFix_memExe_doRespLdForward
assign CAN_FIRE_RL_coreFix_memExe_doRespLdForward =
!coreFix_memExe_forwardQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_doRespLdForward =
CAN_FIRE_RL_coreFix_memExe_doRespLdForward &&
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
!WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
// rule RL_rl_debug_gpr_write
assign CAN_FIRE_RL_rl_debug_gpr_write =
regRenamingTable$RDY_rename_0_getRename && f_gpr_reqs$EMPTY_N &&
f_gpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
f_gpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_gpr_write = CAN_FIRE_RL_rl_debug_gpr_write ;
// rule RL_rl_debug_fpr_write
assign CAN_FIRE_RL_rl_debug_fpr_write =
regRenamingTable$RDY_rename_0_getRename && f_fpr_reqs$EMPTY_N &&
f_fpr_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
!f_gpr_reqs$EMPTY_N &&
f_fpr_reqs$D_OUT[69] ;
assign WILL_FIRE_RL_rl_debug_fpr_write = CAN_FIRE_RL_rl_debug_fpr_write ;
// rule RL_coreFix_memExe_doExeMem
assign CAN_FIRE_RL_coreFix_memExe_doExeMem =
coreFix_memExe_regToExeQ$RDY_deq &&
coreFix_memExe_regToExeQ$RDY_first &&
coreFix_memExe_dTlb$RDY_procReq ;
assign WILL_FIRE_RL_coreFix_memExe_doExeMem =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
// rule RL_prepareCachesAndTlbs
assign CAN_FIRE_RL_prepareCachesAndTlbs =
(!flush_tlbs ||
coreFix_memExe_dTlb$RDY_flush &&
fetchStage$RDY_iTlbIfc_flush) &&
(flush_reservation || flush_tlbs || update_vm_info) ;
assign WILL_FIRE_RL_prepareCachesAndTlbs =
CAN_FIRE_RL_prepareCachesAndTlbs ;
// rule RL_rl_debug_resume
assign CAN_FIRE_RL_rl_debug_resume =
commitStage_rg_run_state && coreFix_memExe_dTlb$RDY_flush &&
fetchStage$RDY_iTlbIfc_flush &&
f_run_halt_reqs$EMPTY_N &&
f_run_halt_rsps$FULL_N &&
rg_core_run_state == 2'd1 &&
f_run_halt_reqs$D_OUT &&
!f_gpr_reqs$EMPTY_N &&
!f_fpr_reqs$EMPTY_N &&
!f_csr_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_debug_resume = MUX_started$write_1__SEL_1 ;
// rule RL_coreFix_memExe_doRegReadMem
assign CAN_FIRE_RL_coreFix_memExe_doRegReadMem =
coreFix_memExe_dispToRegQ$RDY_deq &&
coreFix_memExe_regToExeQ$RDY_enq &&
coreFix_memExe_dispToRegQ$RDY_first &&
sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 ;
assign WILL_FIRE_RL_coreFix_memExe_doRegReadMem =
CAN_FIRE_RL_coreFix_memExe_doRegReadMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_doDispatchMem
assign CAN_FIRE_RL_coreFix_memExe_doDispatchMem =
coreFix_memExe_dispToRegQ$RDY_enq &&
coreFix_memExe_rsMem$RDY_doDispatch &&
coreFix_memExe_rsMem$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_memExe_doDispatchMem =
CAN_FIRE_RL_coreFix_memExe_doDispatchMem &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_getEmptyEntryInit &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
(!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$Q_OUT ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_cRqTransfer_getEmptyEntryInit &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer &&
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_send &&
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_canonicalize =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_canon =
1'd1 ;
// rule RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_canon =
1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_respLrScAmoQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_respLrScAmoQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_memRespLdQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_memRespLdQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_canonicalize
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_canonicalize = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_clearReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_deqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_deqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_forwardQ_enqReq_canon
assign CAN_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_forwardQ_enqReq_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqStQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqStQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLrScAmoQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLrScAmoQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_full_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_full_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_empty_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_empty_canon = 1'd1 ;
// rule RL_coreFix_memExe_reqLdQ_data_0_canon
assign CAN_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_memExe_reqLdQ_data_0_canon = 1'd1 ;
// rule RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
coreFix_fpuMulDivExe_0_regToExeQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_first &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_deq &&
coreFix_fpuMulDivExe_0_regToExeQ$RDY_enq &&
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_enq &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_doDispatch &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_dispatchData ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv &&
!WILL_FIRE_RL_commitStage_doCommitKilledLd &&
!WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
!coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// rule RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon
assign CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
assign WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_canon = 1'd1 ;
// rule RL_renameStage_doRenaming_Trap
assign CAN_FIRE_RL_renameStage_doRenaming_Trap =
epochManager$RDY_incrementEpoch && rob$RDY_enqPort_0_enq &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987 &&
rob$isEmpty &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_renameStage_doRenaming_Trap =
CAN_FIRE_RL_renameStage_doRenaming_Trap &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_renameStage_doRenaming_SystemInst
assign CAN_FIRE_RL_renameStage_doRenaming_SystemInst =
epochManager$RDY_incrementEpoch &&
rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293 &&
rg_core_run_state == 2'd2 ;
assign WILL_FIRE_RL_renameStage_doRenaming_SystemInst =
CAN_FIRE_RL_renameStage_doRenaming_SystemInst &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_csrInstOrInterruptInflight_canon
assign CAN_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
assign WILL_FIRE_RL_csrInstOrInterruptInflight_canon = 1'd1 ;
// rule RL_commitStage_doSetLSQAtCommit
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit =
MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 ||
WILL_FIRE_RL_commitStage_notifyLSQCommit ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
// rule RL_commitStage_doSetLSQAtCommit_1
assign CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 &&
rob$deqPort_1_deq_data[13] ;
assign WILL_FIRE_RL_commitStage_doSetLSQAtCommit_1 =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
// rule RL_renameStage_doRenaming
assign CAN_FIRE_RL_renameStage_doRenaming =
(!fetchStage$pipelines_0_canDeq ||
IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361) &&
IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825 &&
IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007 &&
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011 ;
assign WILL_FIRE_RL_renameStage_doRenaming =
CAN_FIRE_RL_renameStage_doRenaming &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_rl_debug_halt_req ;
// rule RL_mmio_pRqQ_canonicalize
assign CAN_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_canonicalize = 1'd1 ;
// rule RL_mmio_pRqQ_enqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_enqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_deqReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_deqReq_canon = 1'd1 ;
// rule RL_mmio_pRqQ_clearReq_canon
assign CAN_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_mmio_pRqQ_clearReq_canon = 1'd1 ;
// rule RL_coreFix_globalSpecUpdate_canon_correct_spec
assign CAN_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
assign WILL_FIRE_RL_coreFix_globalSpecUpdate_canon_correct_spec = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_1 =
WILL_FIRE_RL_renameStage_doRenaming ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_2 =
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign MUX_regRenamingTable$rename_0_getRename_1__SEL_3 =
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign MUX_commitStage_rg_run_state$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ;
assign MUX_commitStage_setLSQAtCommit_0$wset_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[13] ;
assign MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3 =
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013) ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634) ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ;
assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601) ;
assign MUX_coreFix_memExe_lsq$getHit_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626) ;
assign MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign MUX_coreFix_trainBPQ_0$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ;
assign MUX_coreFix_trainBPQ_1$enq_1__SEL_1 =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 ;
assign MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd3) ;
assign MUX_csrf_external_int_en_vec_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd9 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd22) ;
assign MUX_csrf_external_int_en_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ;
assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd16 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd29) ;
assign MUX_csrf_external_int_pend_vec_0$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd29 ;
assign MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ;
assign MUX_csrf_fflags_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 ;
assign MUX_csrf_fflags_reg$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd2) ;
assign MUX_csrf_fflags_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
assign MUX_csrf_frm_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd2) ;
assign MUX_csrf_fs_reg$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd2 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18) ;
assign MUX_csrf_fs_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3 ||
f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
assign MUX_csrf_ie_vec_0$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18) ;
assign MUX_csrf_ie_vec_0$write_1__SEL_2 =
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
assign MUX_csrf_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_ie_vec_1$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ;
assign MUX_csrf_ie_vec_3$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ;
assign MUX_csrf_mcause_code_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd27 ;
assign MUX_csrf_mcause_code_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ;
assign MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ;
assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2816 ;
assign MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd30 ;
assign MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ;
assign MUX_csrf_mepc_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd26 ;
assign MUX_csrf_mepc_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd833 ;
assign MUX_csrf_mideleg_11_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ;
assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2818 ;
assign MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd31 ;
assign MUX_csrf_mpp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_mscratch_csr$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd832 ;
assign MUX_csrf_mtval_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd28 ;
assign MUX_csrf_mtval_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd835 ;
assign MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ;
assign MUX_csrf_ppn_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ;
assign MUX_csrf_prev_ie_vec_1$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_prev_ie_vec_3$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ;
assign MUX_csrf_prv_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ;
assign MUX_csrf_prv_reg$write_1__SEL_2 =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ;
assign MUX_csrf_prv_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ;
assign MUX_csrf_rg_dcsr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd36 ;
assign MUX_csrf_rg_dpc$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd37 ;
assign MUX_csrf_rg_dpc$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1969 ;
assign MUX_csrf_rg_dscratch0$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1970 ;
assign MUX_csrf_rg_dscratch1$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1971 ;
assign MUX_csrf_scause_code_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd14 ;
assign MUX_csrf_scause_code_reg$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ;
assign MUX_csrf_scounteren_cy_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ;
assign MUX_csrf_sepc_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd13 ;
assign MUX_csrf_sepc_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd321 ;
assign MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 =
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd0 &&
mmio_pRqQ_data_0[37:36] != 2'd1 ;
assign MUX_csrf_spp_reg$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ;
assign MUX_csrf_sscratch_csr$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd320 ;
assign MUX_csrf_stats_module_writeQ$enq_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2049 ;
assign MUX_csrf_stval_csr$write_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd15 ;
assign MUX_csrf_stval_csr$write_1__SEL_3 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd323 ;
assign MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ;
assign MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ;
assign MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 &&
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ;
assign MUX_flush_reservation$write_1__SEL_2 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ;
assign MUX_flush_tlbs$write_1__SEL_1 =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ;
assign MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign MUX_renameStage_rg_m_halt_req$write_1__SEL_1 =
MUX_renameStage_rg_m_halt_req$write_1__PSEL_1 &&
csrf_rg_dcsr[2] ;
assign MUX_renameStage_rg_m_halt_req$write_1__SEL_2 =
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
csrf_rg_dcsr[2] ;
assign MUX_rf$write_3_wr_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_2 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_rf$write_3_wr_1__SEL_3 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_1__SEL_4 =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_rf$write_3_wr_1__PSEL_5 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
assign MUX_rf$write_3_wr_1__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
assign MUX_rf$write_3_wr_2__SEL_5 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
assign MUX_rg_core_run_state$write_1__SEL_4 =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ;
assign MUX_rob$setExecuted_deqLSQ_1__SEL_1 =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ;
assign MUX_sbAggr$setReady_4_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbAggr$setReady_4_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_sbCons$setReady_3_put_1__SEL_1 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_1 &&
coreFix_memExe_lsq$firstSt[150] ;
assign MUX_sbCons$setReady_3_put_1__SEL_2 =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 &&
coreFix_memExe_lsq$firstLd[89] ;
assign MUX_sbCons$setReady_3_put_1__SEL_3 =
MUX_rf$write_3_wr_1__PSEL_5 && coreFix_memExe_lsq$respLd[72] ;
assign MUX_started$write_1__SEL_1 =
CAN_FIRE_RL_rl_debug_resume &&
!WILL_FIRE_RL_prepareCachesAndTlbs ;
assign MUX_v_f_to_TV_0$enq_1__SEL_1 =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ;
assign MUX_regRenamingTable$rename_0_getRename_1__VAL_2 =
{ 2'd2, f_gpr_reqs$D_OUT[68:64], 20'd345386 } ;
assign MUX_regRenamingTable$rename_0_getRename_1__VAL_3 =
{ 2'd3, f_fpr_reqs$D_OUT[68:64], 20'd345386 } ;
assign MUX_commitStage_commitTrap$write_1__VAL_2 =
{ 1'd1,
rob$deqPort_0_deq_data[282:219],
x__h692236,
rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302 } ;
assign MUX_commitStage_rg_serialnum$write_1__VAL_1 =
commitStage_rg_serialnum + 64'd1 ;
assign MUX_commitStage_rg_serialnum$write_1__VAL_2 =
commitStage_rg_serialnum + y__h714114 ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 =
(k__h664083 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510,
fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h678574,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
5'd10,
sbAggr$eagerLookup_0_get } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 =
{ 1'd1, coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 =
{ 1'd1,
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6 =
{ 1'd1,
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 =
{ 1'd1, coreFix_memExe_lsq$firstSt[149:143] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 =
{ 1'd1, coreFix_memExe_lsq$firstLd[88:82] } ;
assign MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 =
{ 1'd1, coreFix_memExe_lsq$getHit[7:1] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
3'd3 :
3'd5) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 } :
58'h155555555555554) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
55'h15555555555555 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ (!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } :
{ (!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0]) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 =
{ coreFix_memExe_dMem_cache_m_banks_0_processAmo[151:100],
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0],
IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd0) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) :
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522 ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq[147:84],
x__h283692 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 =
{ 517'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
x__h285138,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 =
{ 518'h1AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4 =
{ 2'd2,
addr__h287914,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 =
{ x__h153444, x__h153450, 84'h82AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 =
{ x__h156991, x__h156997, 84'hCAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3 =
{ x__h159807,
x__h159811,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247,
x__h161659,
IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263,
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
resp_addr__h289818,
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData } ;
assign MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq,
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData } ;
assign MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 =
{ prv__h715770,
prv__h715770 != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$getIssueLd[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_issueLd$wget[76:72],
coreFix_memExe_lsq$issueLd[63:0] } ;
assign MUX_coreFix_memExe_lsq$getHit_1__VAL_1 =
{ 1'd0,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148] } ;
assign MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 =
{ coreFix_memExe_stb$search[67],
coreFix_memExe_stb$search[67] ?
coreFix_memExe_stb$search[66:65] :
2'h2,
coreFix_memExe_stb$search[64],
coreFix_memExe_stb$search[64] ?
coreFix_memExe_stb$search[63:0] :
64'hAAAAAAAAAAAAAAAA } ;
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_0[68:64];
1'd1:
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 =
coreFix_memExe_forwardQ_data_1[68:64];
endcase
end
always@(coreFix_memExe_memRespLdQ_deqP or
coreFix_memExe_memRespLdQ_data_0 or
coreFix_memExe_memRespLdQ_data_1)
begin
case (coreFix_memExe_memRespLdQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 =
coreFix_memExe_memRespLdQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_forwardQ_deqP or
coreFix_memExe_forwardQ_data_0 or coreFix_memExe_forwardQ_data_1)
begin
case (coreFix_memExe_forwardQ_deqP)
1'd0:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_0[63:0];
1'd1:
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 =
coreFix_memExe_forwardQ_data_1[63:0];
endcase
end
assign MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[152:148],
x__h194973 } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 =
{ 5'd0,
coreFix_memExe_lsq$firstSt[141:78],
2'd3,
(coreFix_memExe_lsq$firstSt[158:157] == 2'd1) ? 3'd3 : 3'd4,
coreFix_memExe_lsq$firstSt[76:5],
coreFix_memExe_lsq$firstSt[156:153],
coreFix_memExe_lsq$firstSt[69] &&
coreFix_memExe_lsq$firstSt[70] &&
coreFix_memExe_lsq$firstSt[71] &&
coreFix_memExe_lsq$firstSt[72] &&
coreFix_memExe_lsq$firstSt[73] &&
coreFix_memExe_lsq$firstSt[74] &&
coreFix_memExe_lsq$firstSt[75] &&
coreFix_memExe_lsq$firstSt[76],
coreFix_memExe_lsq$firstSt[152:151] } ;
assign MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 =
{ 5'd0,
coreFix_memExe_lsq$firstLd[80:17],
84'h92AAAAAAAAAAAAAAAAAAA } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
((!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } :
65'h10000000000000001) :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566 ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } ;
assign MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3 =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_processAmo[6] ?
curData__h190763 :
{ {32{x__h191526[31]}}, x__h191526 } } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_1 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[326:322],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[300:277],
1'd0,
coreFix_aluExe_0_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_0$enq_1__VAL_2 =
{ coreFix_aluExe_0_exeToFinQ$first[146:19],
coreFix_aluExe_0_exeToFinQ$first[326:322],
coreFix_aluExe_0_exeToFinQ$first[18],
coreFix_aluExe_0_exeToFinQ$first[300:277],
1'd1,
coreFix_aluExe_0_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_1 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[326:322],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[300:277],
1'd0,
coreFix_aluExe_1_exeToFinQ$first[276] } ;
assign MUX_coreFix_trainBPQ_1$enq_1__VAL_2 =
{ coreFix_aluExe_1_exeToFinQ$first[146:19],
coreFix_aluExe_1_exeToFinQ$first[326:322],
coreFix_aluExe_1_exeToFinQ$first[18],
coreFix_aluExe_1_exeToFinQ$first[300:277],
1'd1,
coreFix_aluExe_1_exeToFinQ$first[276] } ;
assign MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 =
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_1 ||
MUX_csrInstOrInterruptInflight_dummy2_0$write_1__SEL_2 ;
assign MUX_csrf_fflags_reg$write_1__VAL_1 =
csrf_fflags_reg | fflags__h714091 ;
assign MUX_csrf_frm_reg$write_1__VAL_1 =
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd1) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q270[2:0] :
robdeqPort_0_deq_data_BITS_95_TO_32__q270[7:5] ;
assign MUX_csrf_frm_reg$write_1__VAL_2 =
(f_csr_reqs$D_OUT[75:64] == 12'd2) ?
f_csr_reqs$D_OUT[2:0] :
f_csr_reqs$D_OUT[7:5] ;
always@(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 or
robdeqPort_0_deq_data_BITS_95_TO_32__q270)
begin
case (IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674)
6'd0, 6'd1, 6'd2: MUX_csrf_fs_reg$write_1__VAL_2 = 2'b11;
default: MUX_csrf_fs_reg$write_1__VAL_2 =
robdeqPort_0_deq_data_BITS_95_TO_32__q270[14:13];
endcase
end
always@(f_csr_reqs$D_OUT)
begin
case (f_csr_reqs$D_OUT[75:64])
12'd1, 12'd2, 12'd3: MUX_csrf_fs_reg$write_1__VAL_3 = 2'b11;
default: MUX_csrf_fs_reg$write_1__VAL_3 = f_csr_reqs$D_OUT[14:13];
endcase
end
assign MUX_csrf_ie_vec_1$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18)) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q270[1] :
csrf_prev_ie_vec_1 ;
assign MUX_csrf_ie_vec_3$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18) ?
robdeqPort_0_deq_data_BITS_95_TO_32__q270[3] :
csrf_prev_ie_vec_3 ;
assign MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2 =
rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 =
n__read__h709918 + 64'd1 ;
assign MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 =
n__read__h709918 + { 62'd0, x__h714333 } ;
assign MUX_csrf_mpp_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18) ?
MUX_csrf_minstret_ehr_data_lat_0$wset_1__VAL_2[12:11] :
2'd0 ;
assign MUX_csrf_mtval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_mtval_csr$write_1__VAL_2 =
commitStage_commitTrap[4] ? 64'd0 : trap_val__h699101 ;
assign MUX_csrf_prev_ie_vec_1$write_1__VAL_1 =
rob$deqPort_0_deq_data[186:182] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 !=
6'd8 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 !=
6'd18 ||
MUX_csrf_mtval_csr$write_1__VAL_1[5] ;
assign MUX_csrf_prev_ie_vec_3$write_1__VAL_1 =
rob$deqPort_0_deq_data[186:182] != 5'd13 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 !=
6'd18 ||
MUX_csrf_mtval_csr$write_1__VAL_1[7] ;
assign MUX_csrf_prv_reg$write_1__VAL_1 =
(rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd36) ?
MUX_csrf_mtval_csr$write_1__VAL_1[1:0] :
((rob$deqPort_0_deq_data[186:182] == 5'd19) ?
x__h709324 :
csrf_mpp_reg) ;
assign MUX_csrf_prv_reg$write_1__VAL_2 =
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ?
2'd1 :
2'd3 ;
assign MUX_csrf_rg_dcsr$write_1__VAL_2 =
{ 32'b0,
csrf_rg_dcsr[31:9],
dcsr_cause__h697582,
csrf_rg_dcsr[5:2],
csrf_prv_reg } ;
assign MUX_csrf_sepc_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 =
(mmio_pRqQ_data_0[37:36] == 2'd2) ?
mmio_pRqQ_data_0[0] :
amoExec___d880[0] ;
assign MUX_csrf_spp_reg$write_1__VAL_1 =
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18) &&
MUX_csrf_sepc_csr$write_1__VAL_1[8] ;
assign MUX_csrf_stval_csr$write_1__VAL_1 = rob$deqPort_0_deq_data[95:32] ;
assign MUX_f_csr_rsps$enq_1__VAL_3 = { 1'd1, data_out__h718171 } ;
assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, rf$read_4_rd1 } ;
assign MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 =
{ csrf_prv_reg,
csrf_prv_reg != 2'd3 && csrf_vm_mode_sv39_reg,
csrf_mxr_reg,
csrf_sum_reg,
csrf_ppn_reg } ;
assign MUX_fetchStage$redirect_1__VAL_1 =
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ?
y_avValue__h698948 :
y_avValue__h700717 ;
always@(rob$deqPort_0_deq_data or
next_pc__h709264 or csrf_sepc_csr or csrf_mepc_csr)
begin
case (rob$deqPort_0_deq_data[186:182])
5'd19: MUX_fetchStage$redirect_1__VAL_6 = csrf_sepc_csr;
5'd20: MUX_fetchStage$redirect_1__VAL_6 = csrf_mepc_csr;
default: MUX_fetchStage$redirect_1__VAL_6 = next_pc__h709264;
endcase
end
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 =
{ 1'd1,
coreFix_memExe_dTlb$toParent_rqToP_first[1:0],
coreFix_memExe_dTlb$toParent_rqToP_first[28:2] } ;
assign MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 =
{ 3'd2, fetchStage$iTlbIfc_toParent_rqToP_first } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
mmio_dataReqQ_data_0[141:78],
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q271,
mmio_dataReqQ_data_0[71:0] } ;
assign MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
fetchStage$mmioIfc_instReq_first_fst,
5'd2,
fetchStage$mmioIfc_instReq_first_snd,
72'hAAAAAAAAAAAAAAAAAA } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
coreFix_memExe_lsq$firstSt[141:78],
(coreFix_memExe_lsq$firstSt[158:157] == 2'd0) ?
6'd42 :
{ 2'd3, coreFix_memExe_lsq$firstSt[156:153] },
coreFix_memExe_lsq$firstSt[76:5] } ;
assign MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
coreFix_memExe_lsq$firstLd[80:17],
6'd26,
coreFix_memExe_lsq$firstLd[15:0],
56'hAAAAAAAAAAAAAA } ;
assign MUX_rf$write_2_wr_2__VAL_1 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[33] ?
data___1__h473660 :
data__h473126 ;
assign MUX_rf$write_2_wr_2__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
res_data__h335718 :
res_data__h335713 ;
assign MUX_rf$write_2_wr_2__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
res_data__h381420 :
res_data__h381415 ;
assign MUX_rf$write_2_wr_2__VAL_5 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
res_data__h427115 :
res_data__h427110 ;
assign MUX_rf$write_2_wr_2__VAL_6 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[33] ?
data___1__h472852 :
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 ;
assign MUX_rf$write_3_wr_2__VAL_3 =
coreFix_memExe_lsq$firstLd[100] ?
coreFix_memExe_respLrScAmoQ_data_0 :
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 ;
assign MUX_rf$write_3_wr_2__VAL_4 =
coreFix_memExe_lsq$firstLd[100] ?
mmio_dataRespQ_data_0[63:0] :
IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 ;
assign MUX_rob$enqPort_0_enq_1__VAL_1 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 &&
fetchStage$pipelines_0_first[194:192] != 3'd2 &&
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4,
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083 } ;
assign MUX_rob$enqPort_0_enq_1__VAL_2 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908,
2'd1,
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000,
IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215,
fetchStage$pipelines_0_first[63:0],
2'd0,
fetchStage$pipelines_0_first[323:260],
20'd13601,
specTagManager$currentSpecBits } ;
assign MUX_rob$enqPort_0_enq_1__VAL_3 =
{ fetchStage$pipelines_0_first[387:324],
fetchStage$pipelines_0_first[127:96],
fetchStage$pipelines_0_first[199:195],
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908,
73'h1280000000000000000,
fetchStage$pipelines_0_first[323:260],
5'd0,
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74],
fetchStage$pipelines_0_first[194:192] != 3'd0,
13'h1521,
specTagManager$currentSpecBits } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_2 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q272 } ;
assign MUX_rob$setExecuted_deqLSQ_2__VAL_6 =
{ 1'd1,
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q273 } ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] :
res_fflags__h335714 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] :
res_fflags__h381416 ;
assign MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[39] ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] :
res_fflags__h427111 ;
assign MUX_v_f_to_TV_0$enq_1__VAL_1 =
{ commitStage_rg_serialnum,
rob$deqPort_0_deq_data[282:181],
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q274,
rob$deqPort_0_deq_data[167],
rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302,
rob$deqPort_0_deq_data[161:98],
CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q275,
rob$deqPort_0_deq_data[95:26] } ;
// inlined wires
assign csrf_minstret_ehr_data_lat_0$whas =
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ||
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_2 ;
assign csrf_minstret_ehr_data_lat_1$whas =
WILL_FIRE_RL_commitStage_doCommitSystemInst ||
WILL_FIRE_RL_commitStage_doCommitNormalInst ;
assign csrf_minstret_ehr_data_dummy_1_0$whas =
WILL_FIRE_RL_commitStage_doCommitNormalInst ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign csrf_mcycle_ehr_data_lat_0$whas =
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ||
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_2 ;
assign csrInstOrInterruptInflight_lat_1$whas =
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
WILL_FIRE_RL_renameStage_doRenaming_Trap &&
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229 ;
assign mmio_dataReqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ?
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_dataReqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_dataReqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
assign mmio_dataRespQ_enqReq_lat_0$wget = { 1'd1, mmio_pRsQ_data_0[64:0] } ;
assign mmio_dataRespQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ;
assign mmio_dataPendQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ;
assign mmio_cRqQ_enqReq_lat_0$wget =
WILL_FIRE_RL_mmio_sendDataReq ?
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_mmio_cRqQ_enqReq_lat_0$wset_1__VAL_2 ;
assign mmio_cRqQ_enqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendDataReq || WILL_FIRE_RL_mmio_sendInstReq ;
assign mmio_pRsQ_enqReq_lat_0$wget = { 1'd1, mmioToPlatform_pRs_enq_x } ;
assign mmio_pRsQ_deqReq_lat_0$whas =
WILL_FIRE_RL_mmio_sendInstResp ||
WILL_FIRE_RL_mmio_sendDataResp ;
assign mmio_pRqQ_enqReq_lat_0$wget =
{ 1'd1,
mmioToPlatform_pRq_enq_x[38],
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q276,
mmioToPlatform_pRq_enq_x[31:0] } ;
assign mmio_cRsQ_enqReq_lat_0$wget =
{ 1'd1, csrf_software_int_pend_vec_3 } ;
assign coreFix_globalSpecUpdate_correctSpecTag_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
coreFix_aluExe_0_exeToFinQ$first[16] ;
assign coreFix_globalSpecUpdate_correctSpecTag_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
coreFix_aluExe_1_exeToFinQ$first[16] ;
assign coreFix_aluExe_0_bypassWire_0$wget =
{ coreFix_aluExe_0_regToExeQ$first[348:342],
basicExec___d12557[321:258] } ;
assign coreFix_aluExe_0_bypassWire_0$whas =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu &&
coreFix_aluExe_0_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_1$wget =
{ coreFix_aluExe_1_regToExeQ$first[348:342],
basicExec___d11911[321:258] } ;
assign coreFix_aluExe_0_bypassWire_1$whas =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu &&
coreFix_aluExe_1_regToExeQ$first[349] ;
assign coreFix_aluExe_0_bypassWire_2$wget =
{ coreFix_aluExe_0_exeToFinQ$first[320:314],
coreFix_aluExe_0_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_2$whas =
_dor1coreFix_aluExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_aluExe_0_bypassWire_3$wget =
{ coreFix_aluExe_1_exeToFinQ$first[320:314],
coreFix_aluExe_1_exeToFinQ$first[275:212] } ;
assign coreFix_aluExe_0_bypassWire_3$whas =
_dor1coreFix_aluExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_aluExe_1_bypassWire_2$whas =
_dor1coreFix_aluExe_1_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_aluExe_1_bypassWire_3$whas =
_dor1coreFix_aluExe_1_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_fpuMulDivExe_0_bypassWire_3$whas =
_dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[226:225])
2'd0, 2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget =
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225];
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget = 2'd2;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_memExe_bypassWire_2$whas =
_dor1coreFix_memExe_bypassWire_2$EN_wset &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign coreFix_memExe_bypassWire_3$whas =
_dor1coreFix_memExe_bypassWire_3$EN_wset &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign coreFix_memExe_issueLd$wget =
{ coreFix_memExe_dTlb$procResp[89:85],
coreFix_memExe_dTlb$procResp[174:111],
coreFix_memExe_dTlb$procResp[84:77] } ;
assign coreFix_memExe_issueLd$whas =
WILL_FIRE_RL_coreFix_memExe_doFinishMem &&
coreFix_memExe_dTlb$procResp[105:103] == 3'd0 &&
NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 &&
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 &&
!coreFix_memExe_lsq$updateAddr ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$wget =
MUX_coreFix_memExe_reqLdQ_data_0_lat_0$wset_1__SEL_1 ?
coreFix_memExe_issueLd$wget[76:8] :
coreFix_memExe_lsq$getIssueLd[76:8] ;
assign coreFix_memExe_reqLdQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_empty_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLdQ_full_lat_0$whas =
_dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ?
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ;
assign coreFix_memExe_reqStQ_data_0_lat_0$wget =
{ coreFix_memExe_stb$issue[635:576], 6'd0 } ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ?
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_forwardQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_1 ||
MUX_coreFix_memExe_forwardQ_enqReq_lat_0$wset_1__SEL_2 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_memRespLdQ_enqReq_lat_0$wset_1__VAL_1 ;
assign coreFix_memExe_memRespLdQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
MUX_coreFix_memExe_lsq$getHit_1__SEL_2 ;
always@(MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wset_1__VAL_3;
default: coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas =
MUX_coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
always@(WILL_FIRE_RL_coreFix_memExe_sendLdToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_sendStToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem or
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_sendLdToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_sendStToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem:
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wset_1__VAL_3;
default: coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wset_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[147:84],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[54:53],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq[83:82],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot[57:55] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget =
{ 1'd1, dCacheToParent_fromP_enq_x } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget =
{ 1'd1,
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[2:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645 ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wset_1__VAL_2;
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3:
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget =
59'h2AAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas =
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_1 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_2 ||
MUX_coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$write_1__SEL_3 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas =
WILL_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// register commitStage_commitTrap
assign commitStage_commitTrap$D_IN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ?
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_commitStage_commitTrap$write_1__VAL_2 ;
assign commitStage_commitTrap$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
// register commitStage_rg_run_state
assign commitStage_rg_run_state$D_IN =
MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign commitStage_rg_run_state$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
WILL_FIRE_RL_rl_debug_resume ;
// register commitStage_rg_serialnum
assign commitStage_rg_serialnum$D_IN =
WILL_FIRE_RL_commitStage_doCommitSystemInst ?
MUX_commitStage_rg_serialnum$write_1__VAL_1 :
MUX_commitStage_rg_serialnum$write_1__VAL_2 ;
assign commitStage_rg_serialnum$EN = csrf_minstret_ehr_data_lat_1$whas ;
// register coreFix_doStatsReg
assign coreFix_doStatsReg$D_IN = 1'b0 ;
assign coreFix_doStatsReg$EN = 1'b0 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt + 4'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit ;
// register coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN = 1'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_doInit &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt == 4'd15 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas ?
v__h602372 :
v__h601727 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN =
{ coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas,
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$wget } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN = 1'd1 ;
// register coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd2 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd4 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd5 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd6 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
_theResult_____2__h294368 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN =
1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl) ?
3'd0 :
v__h293788 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN =
4'b0010 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN =
1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN =
{ !coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582]),
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
_theResult_____2__h302364 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
v__h297133 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN =
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000,
IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_processAmo
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
default: coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_processAmo$write_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas &&
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[71:0] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[71:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
_theResult_____2__h308358 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
v__h307647 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN =
73'h0AAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN =
{ x_addr__h311921,
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[514:513] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[514:513],
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 ||
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[512] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[512]),
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[511:0] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd0 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP == 1'd1 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
_theResult_____2__h316212 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
v__h311523 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN =
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN =
NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_clearReq_rl
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_data_0
assign coreFix_memExe_dMem_perfReqQ_data_0$D_IN =
coreFix_memExe_dMem_perfReqQ_enqReq_rl[3:0] ;
assign coreFix_memExe_dMem_perfReqQ_data_0$EN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ;
// register coreFix_memExe_dMem_perfReqQ_deqReq_rl
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_empty
assign coreFix_memExe_dMem_perfReqQ_empty$D_IN =
coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_clearReq_rl ||
NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923 ;
assign coreFix_memExe_dMem_perfReqQ_empty$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_enqReq_rl
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN = 5'b01010 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_dMem_perfReqQ_full
assign coreFix_memExe_dMem_perfReqQ_full$D_IN =
NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 &&
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907 ;
assign coreFix_memExe_dMem_perfReqQ_full$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_clearReq_rl
assign coreFix_memExe_forwardQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_data_0
assign coreFix_memExe_forwardQ_data_0$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_0$EN =
coreFix_memExe_forwardQ_enqP == 1'd0 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ;
// register coreFix_memExe_forwardQ_data_1
assign coreFix_memExe_forwardQ_data_1$D_IN =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_forwardQ_enqReq_rl[68:0] ;
assign coreFix_memExe_forwardQ_data_1$EN =
coreFix_memExe_forwardQ_enqP == 1'd1 &&
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ;
// register coreFix_memExe_forwardQ_deqP
assign coreFix_memExe_forwardQ_deqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
_theResult_____2__h329781 ;
assign coreFix_memExe_forwardQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_deqReq_rl
assign coreFix_memExe_forwardQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_forwardQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_empty
assign coreFix_memExe_forwardQ_empty$D_IN =
coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_forwardQ_clearReq_rl ||
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 &&
NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768 ;
assign coreFix_memExe_forwardQ_empty$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqP
assign coreFix_memExe_forwardQ_enqP$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
v__h329349 ;
assign coreFix_memExe_forwardQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_enqReq_rl
assign coreFix_memExe_forwardQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_forwardQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_forwardQ_full
assign coreFix_memExe_forwardQ_full$D_IN =
NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 &&
IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 &&
coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755 ;
assign coreFix_memExe_forwardQ_full$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_clearReq_rl
assign coreFix_memExe_memRespLdQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_data_0
assign coreFix_memExe_memRespLdQ_data_0$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_0$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd0 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ;
// register coreFix_memExe_memRespLdQ_data_1
assign coreFix_memExe_memRespLdQ_data_1$D_IN =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[68:0] :
coreFix_memExe_memRespLdQ_enqReq_rl[68:0] ;
assign coreFix_memExe_memRespLdQ_data_1$EN =
coreFix_memExe_memRespLdQ_enqP == 1'd1 &&
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ;
// register coreFix_memExe_memRespLdQ_deqP
assign coreFix_memExe_memRespLdQ_deqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
_theResult_____2__h326556 ;
assign coreFix_memExe_memRespLdQ_deqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_deqReq_rl
assign coreFix_memExe_memRespLdQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_memRespLdQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_empty
assign coreFix_memExe_memRespLdQ_empty$D_IN =
coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_memRespLdQ_clearReq_rl ||
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 &&
NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674 ;
assign coreFix_memExe_memRespLdQ_empty$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqP
assign coreFix_memExe_memRespLdQ_enqP$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
v__h326124 ;
assign coreFix_memExe_memRespLdQ_enqP$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_enqReq_rl
assign coreFix_memExe_memRespLdQ_enqReq_rl$D_IN = 70'h0AAAAAAAAAAAAAAAAA ;
assign coreFix_memExe_memRespLdQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_memRespLdQ_full
assign coreFix_memExe_memRespLdQ_full$D_IN =
NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 &&
IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 &&
coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661 ;
assign coreFix_memExe_memRespLdQ_full$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_data_0_rl
assign coreFix_memExe_reqLdQ_data_0_rl$D_IN =
coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget :
coreFix_memExe_reqLdQ_data_0_rl ;
assign coreFix_memExe_reqLdQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_empty_rl
assign coreFix_memExe_reqLdQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ||
!coreFix_memExe_reqLdQ_empty_lat_0$whas &&
coreFix_memExe_reqLdQ_empty_rl ;
assign coreFix_memExe_reqLdQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLdQ_full_rl
assign coreFix_memExe_reqLdQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendLdToMem &&
(coreFix_memExe_reqLdQ_full_lat_0$whas ||
coreFix_memExe_reqLdQ_full_rl) ;
assign coreFix_memExe_reqLdQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_data_0_rl
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN =
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget :
coreFix_memExe_reqLrScAmoQ_data_0_rl ;
assign coreFix_memExe_reqLrScAmoQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_empty_rl
assign coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ||
!coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas &&
coreFix_memExe_reqLrScAmoQ_empty_rl ;
assign coreFix_memExe_reqLrScAmoQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqLrScAmoQ_full_rl
assign coreFix_memExe_reqLrScAmoQ_full_rl$D_IN =
!CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem &&
(coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ||
coreFix_memExe_reqLrScAmoQ_full_rl) ;
assign coreFix_memExe_reqLrScAmoQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_data_0_rl
assign coreFix_memExe_reqStQ_data_0_rl$D_IN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget :
coreFix_memExe_reqStQ_data_0_rl ;
assign coreFix_memExe_reqStQ_data_0_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_empty_rl
assign coreFix_memExe_reqStQ_empty_rl$D_IN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ||
!CAN_FIRE_RL_coreFix_memExe_doIssueSB &&
coreFix_memExe_reqStQ_empty_rl ;
assign coreFix_memExe_reqStQ_empty_rl$EN = 1'd1 ;
// register coreFix_memExe_reqStQ_full_rl
assign coreFix_memExe_reqStQ_full_rl$D_IN =
!WILL_FIRE_RL_coreFix_memExe_sendStToMem &&
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ||
coreFix_memExe_reqStQ_full_rl) ;
assign coreFix_memExe_reqStQ_full_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_clearReq_rl
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_data_0
assign coreFix_memExe_respLrScAmoQ_data_0$D_IN =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[63:0] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[63:0] ;
assign coreFix_memExe_respLrScAmoQ_data_0$EN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 ;
// register coreFix_memExe_respLrScAmoQ_deqReq_rl
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN = 1'd0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_empty
assign coreFix_memExe_respLrScAmoQ_empty$D_IN =
coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT &&
coreFix_memExe_respLrScAmoQ_clearReq_rl ||
NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585 ;
assign coreFix_memExe_respLrScAmoQ_empty$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_enqReq_rl
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN = 65'h0AAAAAAAAAAAAAAAA ;
assign coreFix_memExe_respLrScAmoQ_enqReq_rl$EN = 1'd1 ;
// register coreFix_memExe_respLrScAmoQ_full
assign coreFix_memExe_respLrScAmoQ_full$D_IN =
NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 &&
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570 ;
assign coreFix_memExe_respLrScAmoQ_full$EN = 1'd1 ;
// register coreFix_memExe_waitLrScAmoMMIOResp
always@(MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1 or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_waitLrScAmoMMIOResp$write_1__SEL_1:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd0;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd4;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd2;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd6;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue:
coreFix_memExe_waitLrScAmoMMIOResp$D_IN = 3'd7;
default: coreFix_memExe_waitLrScAmoMMIOResp$D_IN =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_waitLrScAmoMMIOResp$EN =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_issue ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_issue ;
// register csrInstOrInterruptInflight_rl
assign csrInstOrInterruptInflight_rl$D_IN =
csrInstOrInterruptInflight_lat_1$whas ?
1'd1 :
(MUX_csrInstOrInterruptInflight_dummy_1_0$wset_1__VAL_1 ?
1'd0 :
csrInstOrInterruptInflight_rl) ;
assign csrInstOrInterruptInflight_rl$EN = 1'd1 ;
// register csrf_external_int_en_vec_0
assign csrf_external_int_en_vec_0$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[8] :
f_csr_reqs$D_OUT[8] ;
assign csrf_external_int_en_vec_0$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_external_int_en_vec_1
assign csrf_external_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[9] :
f_csr_reqs$D_OUT[9] ;
assign csrf_external_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_external_int_en_vec_3
assign csrf_external_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[11] :
MUX_csrf_stval_csr$write_1__VAL_1[11] ;
assign csrf_external_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd22 ;
// register csrf_external_int_pend_vec_0
assign csrf_external_int_pend_vec_0$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[8] :
f_csr_reqs$D_OUT[8] ;
assign csrf_external_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_external_int_pend_vec_1
always@(MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_external_int_pend_vec_0$write_1__SEL_2 or
f_csr_reqs$D_OUT or EN_setSEIP or setSEIP_v)
case (1'b1)
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1:
csrf_external_int_pend_vec_1$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[9];
MUX_csrf_external_int_pend_vec_0$write_1__SEL_2:
csrf_external_int_pend_vec_1$D_IN = f_csr_reqs$D_OUT[9];
EN_setSEIP: csrf_external_int_pend_vec_1$D_IN = setSEIP_v;
default: csrf_external_int_pend_vec_1$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_external_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ||
EN_setSEIP ;
// register csrf_external_int_pend_vec_3
always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or
f_csr_reqs$D_OUT or EN_setMEIP or setMEIP_v)
case (1'b1)
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1:
csrf_external_int_pend_vec_3$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[11];
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2:
csrf_external_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[11];
EN_setMEIP: csrf_external_int_pend_vec_3$D_IN = setMEIP_v;
default: csrf_external_int_pend_vec_3$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_external_int_pend_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd29 ||
EN_setMEIP ;
// register csrf_fflags_reg
always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
MUX_csrf_fflags_reg$write_1__VAL_1 or
MUX_csrf_fflags_reg$write_1__SEL_2 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_fflags_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_fflags_reg$write_1__SEL_1:
csrf_fflags_reg$D_IN = MUX_csrf_fflags_reg$write_1__VAL_1;
MUX_csrf_fflags_reg$write_1__SEL_2:
csrf_fflags_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[4:0];
MUX_csrf_fflags_reg$write_1__SEL_3:
csrf_fflags_reg$D_IN = f_csr_reqs$D_OUT[4:0];
default: csrf_fflags_reg$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign csrf_fflags_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd0 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd2) ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
// register csrf_frm_reg
assign csrf_frm_reg$D_IN =
MUX_csrf_frm_reg$write_1__SEL_1 ?
MUX_csrf_frm_reg$write_1__VAL_1 :
MUX_csrf_frm_reg$write_1__VAL_2 ;
assign csrf_frm_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd1 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd2) ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3) ;
// register csrf_fs_reg
always@(MUX_csrf_fflags_reg$write_1__SEL_1 or
MUX_csrf_fs_reg$write_1__SEL_2 or
MUX_csrf_fs_reg$write_1__VAL_2 or
MUX_csrf_fs_reg$write_1__SEL_3 or MUX_csrf_fs_reg$write_1__VAL_3)
case (1'b1)
MUX_csrf_fflags_reg$write_1__SEL_1: csrf_fs_reg$D_IN = 2'b11;
MUX_csrf_fs_reg$write_1__SEL_2:
csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_2;
MUX_csrf_fs_reg$write_1__SEL_3:
csrf_fs_reg$D_IN = MUX_csrf_fs_reg$write_1__VAL_3;
default: csrf_fs_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_fs_reg$EN =
MUX_csrf_fs_reg$write_1__SEL_2 ||
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd1 ||
f_csr_reqs$D_OUT[75:64] == 12'd2 ||
f_csr_reqs$D_OUT[75:64] == 12'd3 ||
f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_0
assign csrf_ie_vec_0$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[0] :
f_csr_reqs$D_OUT[0] ;
assign csrf_ie_vec_0$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_1
always@(MUX_csrf_ie_vec_1$write_1__SEL_1 or
MUX_csrf_ie_vec_1$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_ie_vec_1$write_1__SEL_1:
csrf_ie_vec_1$D_IN = MUX_csrf_ie_vec_1$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_ie_vec_1$D_IN = 1'd0;
MUX_csrf_ie_vec_0$write_1__SEL_2:
csrf_ie_vec_1$D_IN = f_csr_reqs$D_OUT[1];
default: csrf_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ie_vec_3
always@(MUX_csrf_ie_vec_3$write_1__SEL_1 or
MUX_csrf_ie_vec_3$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_ie_vec_3$write_1__SEL_1:
csrf_ie_vec_3$D_IN = MUX_csrf_ie_vec_3$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_ie_vec_3$D_IN = 1'd0;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_ie_vec_3$D_IN = f_csr_reqs$D_OUT[3];
default: csrf_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ;
// register csrf_mcause_code_reg
always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
cause_code__h698062 or
MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mcause_code_reg$write_1__SEL_1:
csrf_mcause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mcause_code_reg$D_IN = cause_code__h698062;
MUX_csrf_mcause_code_reg$write_1__SEL_3:
csrf_mcause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
default: csrf_mcause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign csrf_mcause_code_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd27 ;
// register csrf_mcause_interrupt_reg
always@(MUX_csrf_mcause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_mcause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mcause_code_reg$write_1__SEL_1:
csrf_mcause_interrupt_reg$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[63];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mcause_interrupt_reg$D_IN = commitStage_commitTrap[4];
MUX_csrf_mcause_code_reg$write_1__SEL_3:
csrf_mcause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
default: csrf_mcause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_mcause_interrupt_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd834 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd27 ;
// register csrf_mcounteren_cy_reg
assign csrf_mcounteren_cy_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_mcounteren_cy_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd24 ;
// register csrf_mcounteren_ir_reg
assign csrf_mcounteren_ir_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[2] :
MUX_csrf_stval_csr$write_1__VAL_1[2] ;
assign csrf_mcounteren_ir_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd24 ;
// register csrf_mcounteren_tm_reg
assign csrf_mcounteren_tm_reg$D_IN =
MUX_csrf_mcounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1] :
MUX_csrf_stval_csr$write_1__VAL_1[1] ;
assign csrf_mcounteren_tm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd774 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd24 ;
// register csrf_mcycle_ehr_data_rl
assign csrf_mcycle_ehr_data_rl$D_IN = upd__h5309 ;
assign csrf_mcycle_ehr_data_rl$EN = 1'd1 ;
// register csrf_medeleg_13_11_reg
assign csrf_medeleg_13_11_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[13:11] :
MUX_csrf_stval_csr$write_1__VAL_1[13:11] ;
assign csrf_medeleg_13_11_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd20 ;
// register csrf_medeleg_15_reg
assign csrf_medeleg_15_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[15] :
MUX_csrf_stval_csr$write_1__VAL_1[15] ;
assign csrf_medeleg_15_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd20 ;
// register csrf_medeleg_9_0_reg
assign csrf_medeleg_9_0_reg$D_IN =
MUX_csrf_medeleg_13_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[9:0] :
MUX_csrf_stval_csr$write_1__VAL_1[9:0] ;
assign csrf_medeleg_9_0_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd770 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd20 ;
// register csrf_mepc_csr
always@(MUX_csrf_mepc_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_mepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mepc_csr$write_1__SEL_1:
csrf_mepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mepc_csr$D_IN = commitStage_commitTrap[132:69];
MUX_csrf_mepc_csr$write_1__SEL_3:
csrf_mepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_mepc_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_mepc_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd833 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd26 ;
// register csrf_mideleg_11_reg
assign csrf_mideleg_11_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[11] :
MUX_csrf_stval_csr$write_1__VAL_1[11] ;
assign csrf_mideleg_11_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd21 ;
// register csrf_mideleg_1_0_reg
assign csrf_mideleg_1_0_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1:0] :
MUX_csrf_stval_csr$write_1__VAL_1[1:0] ;
assign csrf_mideleg_1_0_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd21 ;
// register csrf_mideleg_5_3_reg
assign csrf_mideleg_5_3_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[5:3] :
MUX_csrf_stval_csr$write_1__VAL_1[5:3] ;
assign csrf_mideleg_5_3_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd21 ;
// register csrf_mideleg_9_7_reg
assign csrf_mideleg_9_7_reg$D_IN =
MUX_csrf_mideleg_11_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[9:7] :
MUX_csrf_stval_csr$write_1__VAL_1[9:7] ;
assign csrf_mideleg_9_7_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd771 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd21 ;
// register csrf_minstret_ehr_data_rl
assign csrf_minstret_ehr_data_rl$D_IN =
csrf_minstret_ehr_data_lat_1$whas ?
upd__h3992 :
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 ;
assign csrf_minstret_ehr_data_rl$EN = 1'd1 ;
// register csrf_mpp_reg
always@(MUX_csrf_mpp_reg$write_1__SEL_1 or
MUX_csrf_mpp_reg$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
csrf_prv_reg or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mpp_reg$write_1__SEL_1:
csrf_mpp_reg$D_IN = MUX_csrf_mpp_reg$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_mpp_reg$D_IN = csrf_prv_reg;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_mpp_reg$D_IN = f_csr_reqs$D_OUT[12:11];
default: csrf_mpp_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_mpp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ;
// register csrf_mprv_reg
assign csrf_mprv_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[17] :
MUX_csrf_stval_csr$write_1__VAL_1[17] ;
assign csrf_mprv_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18 ;
// register csrf_mscratch_csr
assign csrf_mscratch_csr$D_IN =
MUX_csrf_mscratch_csr$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_mscratch_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd832 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd25 ;
// register csrf_mtval_csr
always@(MUX_csrf_mtval_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
MUX_csrf_mtval_csr$write_1__VAL_2 or
MUX_csrf_mtval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_mtval_csr$write_1__SEL_1:
csrf_mtval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_3$write_1__SEL_2:
csrf_mtval_csr$D_IN = MUX_csrf_mtval_csr$write_1__VAL_2;
MUX_csrf_mtval_csr$write_1__SEL_3:
csrf_mtval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_mtval_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_mtval_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd835 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd28 ;
// register csrf_mtvec_base_hi_reg
assign csrf_mtvec_base_hi_reg$D_IN =
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:2] :
MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
assign csrf_mtvec_base_hi_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd23 ;
// register csrf_mtvec_mode_low_reg
assign csrf_mtvec_mode_low_reg$D_IN =
MUX_csrf_mtvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_mtvec_mode_low_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd773 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd23 ;
// register csrf_mxr_reg
assign csrf_mxr_reg$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[19] :
f_csr_reqs$D_OUT[19] ;
assign csrf_mxr_reg$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_ppn_reg
assign csrf_ppn_reg$D_IN =
MUX_csrf_ppn_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[43:0] :
MUX_csrf_stval_csr$write_1__VAL_1[43:0] ;
assign csrf_ppn_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd17 ;
// register csrf_prev_ie_vec_0
assign csrf_prev_ie_vec_0$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[4] :
f_csr_reqs$D_OUT[4] ;
assign csrf_prev_ie_vec_0$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_prev_ie_vec_1
always@(MUX_csrf_prev_ie_vec_1$write_1__SEL_1 or
MUX_csrf_prev_ie_vec_1$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
csrf_ie_vec_1 or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prev_ie_vec_1$write_1__SEL_1:
csrf_prev_ie_vec_1$D_IN = MUX_csrf_prev_ie_vec_1$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_prev_ie_vec_1$D_IN = csrf_ie_vec_1;
MUX_csrf_ie_vec_0$write_1__SEL_2:
csrf_prev_ie_vec_1$D_IN = f_csr_reqs$D_OUT[5];
default: csrf_prev_ie_vec_1$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_prev_ie_vec_1$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_prev_ie_vec_3
always@(MUX_csrf_prev_ie_vec_3$write_1__SEL_1 or
MUX_csrf_prev_ie_vec_3$write_1__VAL_1 or
MUX_csrf_ie_vec_3$write_1__SEL_2 or
csrf_ie_vec_3 or
MUX_csrf_ie_vec_3$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prev_ie_vec_3$write_1__SEL_1:
csrf_prev_ie_vec_3$D_IN = MUX_csrf_prev_ie_vec_3$write_1__VAL_1;
MUX_csrf_ie_vec_3$write_1__SEL_2: csrf_prev_ie_vec_3$D_IN = csrf_ie_vec_3;
MUX_csrf_ie_vec_3$write_1__SEL_3:
csrf_prev_ie_vec_3$D_IN = f_csr_reqs$D_OUT[7];
default: csrf_prev_ie_vec_3$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_prev_ie_vec_3$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo26 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 ;
// register csrf_prv_reg
always@(MUX_csrf_prv_reg$write_1__SEL_1 or
MUX_csrf_prv_reg$write_1__VAL_1 or
MUX_csrf_prv_reg$write_1__SEL_2 or
MUX_csrf_prv_reg$write_1__VAL_2 or
MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_prv_reg$write_1__SEL_1:
csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_1;
MUX_csrf_prv_reg$write_1__SEL_2:
csrf_prv_reg$D_IN = MUX_csrf_prv_reg$write_1__VAL_2;
MUX_csrf_prv_reg$write_1__SEL_3:
csrf_prv_reg$D_IN = f_csr_reqs$D_OUT[1:0];
default: csrf_prv_reg$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign csrf_prv_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo24 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ;
// register csrf_rg_dcsr
always@(MUX_csrf_rg_dcsr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_commitStage_rg_run_state$write_1__SEL_1 or
MUX_csrf_rg_dcsr$write_1__VAL_2 or
MUX_csrf_prv_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_rg_dcsr$write_1__SEL_1:
csrf_rg_dcsr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_commitStage_rg_run_state$write_1__SEL_1:
csrf_rg_dcsr$D_IN = MUX_csrf_rg_dcsr$write_1__VAL_2;
MUX_csrf_prv_reg$write_1__SEL_3:
csrf_rg_dcsr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_rg_dcsr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_rg_dcsr$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1968 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd36 ;
// register csrf_rg_dpc
always@(MUX_csrf_rg_dpc$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_commitStage_rg_run_state$write_1__SEL_1 or
commitStage_commitTrap or
MUX_csrf_rg_dpc$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_rg_dpc$write_1__SEL_1:
csrf_rg_dpc$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_commitStage_rg_run_state$write_1__SEL_1:
csrf_rg_dpc$D_IN = commitStage_commitTrap[132:69];
MUX_csrf_rg_dpc$write_1__SEL_3: csrf_rg_dpc$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_rg_dpc$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_rg_dpc$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1969 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd37 ;
// register csrf_rg_dscratch0
assign csrf_rg_dscratch0$D_IN =
MUX_csrf_rg_dscratch0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_dscratch0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1970 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd38 ;
// register csrf_rg_dscratch1
assign csrf_rg_dscratch1$D_IN =
MUX_csrf_rg_dscratch1$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_rg_dscratch1$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd1971 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd39 ;
// register csrf_scause_code_reg
always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
cause_code__h698062 or
MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_scause_code_reg$write_1__SEL_1:
csrf_scause_code_reg$D_IN = MUX_csrf_stval_csr$write_1__VAL_1[3:0];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_scause_code_reg$D_IN = cause_code__h698062;
MUX_csrf_scause_code_reg$write_1__SEL_3:
csrf_scause_code_reg$D_IN = f_csr_reqs$D_OUT[3:0];
default: csrf_scause_code_reg$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign csrf_scause_code_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd14 ;
// register csrf_scause_interrupt_reg
always@(MUX_csrf_scause_code_reg$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_scause_code_reg$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_scause_code_reg$write_1__SEL_1:
csrf_scause_interrupt_reg$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[63];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_scause_interrupt_reg$D_IN = commitStage_commitTrap[4];
MUX_csrf_scause_code_reg$write_1__SEL_3:
csrf_scause_interrupt_reg$D_IN = f_csr_reqs$D_OUT[63];
default: csrf_scause_interrupt_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_scause_interrupt_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd322 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd14 ;
// register csrf_scounteren_cy_reg
assign csrf_scounteren_cy_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_scounteren_cy_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd11 ;
// register csrf_scounteren_ir_reg
assign csrf_scounteren_ir_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[2] :
MUX_csrf_stval_csr$write_1__VAL_1[2] ;
assign csrf_scounteren_ir_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd11 ;
// register csrf_scounteren_tm_reg
assign csrf_scounteren_tm_reg$D_IN =
MUX_csrf_scounteren_cy_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[1] :
MUX_csrf_stval_csr$write_1__VAL_1[1] ;
assign csrf_scounteren_tm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd262 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd11 ;
// register csrf_sepc_csr
always@(MUX_csrf_sepc_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
commitStage_commitTrap or
MUX_csrf_sepc_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_sepc_csr$write_1__SEL_1:
csrf_sepc_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_sepc_csr$D_IN = commitStage_commitTrap[132:69];
MUX_csrf_sepc_csr$write_1__SEL_3:
csrf_sepc_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_sepc_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_sepc_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd321 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd13 ;
// register csrf_software_int_en_vec_0
assign csrf_software_int_en_vec_0$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[0] :
f_csr_reqs$D_OUT[0] ;
assign csrf_software_int_en_vec_0$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_software_int_en_vec_1
assign csrf_software_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[1] :
f_csr_reqs$D_OUT[1] ;
assign csrf_software_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_software_int_en_vec_3
assign csrf_software_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[3] :
MUX_csrf_stval_csr$write_1__VAL_1[3] ;
assign csrf_software_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd22 ;
// register csrf_software_int_pend_vec_0
assign csrf_software_int_pend_vec_0$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[0] :
f_csr_reqs$D_OUT[0] ;
assign csrf_software_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_software_int_pend_vec_1
assign csrf_software_int_pend_vec_1$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[1] :
f_csr_reqs$D_OUT[1] ;
assign csrf_software_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_software_int_pend_vec_3
always@(MUX_csrf_external_int_pend_vec_3$write_1__SEL_1 or
MUX_csrf_stval_csr$write_1__VAL_1 or
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2 or
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2 or
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_external_int_pend_vec_3$write_1__SEL_1:
csrf_software_int_pend_vec_3$D_IN =
MUX_csrf_stval_csr$write_1__VAL_1[3];
MUX_csrf_software_int_pend_vec_3$write_1__SEL_2:
csrf_software_int_pend_vec_3$D_IN =
MUX_csrf_software_int_pend_vec_3$write_1__VAL_2;
MUX_csrf_external_int_pend_vec_3$write_1__SEL_2:
csrf_software_int_pend_vec_3$D_IN = f_csr_reqs$D_OUT[3];
default: csrf_software_int_pend_vec_3$D_IN =
1'b0 /* unspecified value */ ;
endcase
assign csrf_software_int_pend_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd836 ||
WILL_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] != 2'd0 &&
mmio_pRqQ_data_0[37:36] != 2'd1 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd29 ;
// register csrf_spp_reg
always@(MUX_csrf_spp_reg$write_1__SEL_1 or
MUX_csrf_spp_reg$write_1__VAL_1 or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
csrf_prv_reg or
MUX_csrf_ie_vec_0$write_1__SEL_2 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_spp_reg$write_1__SEL_1:
csrf_spp_reg$D_IN = MUX_csrf_spp_reg$write_1__VAL_1;
MUX_csrf_ie_vec_1$write_1__SEL_2: csrf_spp_reg$D_IN = csrf_prv_reg[0];
MUX_csrf_ie_vec_0$write_1__SEL_2: csrf_spp_reg$D_IN = f_csr_reqs$D_OUT[8];
default: csrf_spp_reg$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign csrf_spp_reg$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst && _dfoo32 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_sscratch_csr
assign csrf_sscratch_csr$D_IN =
MUX_csrf_sscratch_csr$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign csrf_sscratch_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd320 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd12 ;
// register csrf_stats_module_doStats
assign csrf_stats_module_doStats$D_IN = recvDoStats_x ;
assign csrf_stats_module_doStats$EN = EN_recvDoStats ;
// register csrf_stval_csr
always@(MUX_csrf_stval_csr$write_1__SEL_1 or
rob$deqPort_0_deq_data or
MUX_csrf_ie_vec_1$write_1__SEL_2 or
MUX_csrf_mtval_csr$write_1__VAL_2 or
MUX_csrf_stval_csr$write_1__SEL_3 or f_csr_reqs$D_OUT)
case (1'b1)
MUX_csrf_stval_csr$write_1__SEL_1:
csrf_stval_csr$D_IN = rob$deqPort_0_deq_data[95:32];
MUX_csrf_ie_vec_1$write_1__SEL_2:
csrf_stval_csr$D_IN = MUX_csrf_mtval_csr$write_1__VAL_2;
MUX_csrf_stval_csr$write_1__SEL_3:
csrf_stval_csr$D_IN = f_csr_reqs$D_OUT[63:0];
default: csrf_stval_csr$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign csrf_stval_csr$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd323 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 &&
csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd15 ;
// register csrf_stvec_base_hi_reg
assign csrf_stvec_base_hi_reg$D_IN =
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:2] :
MUX_csrf_stval_csr$write_1__VAL_1[63:2] ;
assign csrf_stvec_base_hi_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd10 ;
// register csrf_stvec_mode_low_reg
assign csrf_stvec_mode_low_reg$D_IN =
MUX_csrf_stvec_base_hi_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_stvec_mode_low_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd261 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd10 ;
// register csrf_sum_reg
assign csrf_sum_reg$D_IN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[18] :
f_csr_reqs$D_OUT[18] ;
assign csrf_sum_reg$EN =
MUX_csrf_ie_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd256 ||
f_csr_reqs$D_OUT[75:64] == 12'd768) ;
// register csrf_time_reg
assign csrf_time_reg$D_IN = mmioToPlatform_setTime_t ;
assign csrf_time_reg$EN = EN_mmioToPlatform_setTime ;
// register csrf_timer_int_en_vec_0
assign csrf_timer_int_en_vec_0$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[4] :
f_csr_reqs$D_OUT[4] ;
assign csrf_timer_int_en_vec_0$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_timer_int_en_vec_1
assign csrf_timer_int_en_vec_1$D_IN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[5] :
f_csr_reqs$D_OUT[5] ;
assign csrf_timer_int_en_vec_1$EN =
MUX_csrf_external_int_en_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd260 ||
f_csr_reqs$D_OUT[75:64] == 12'd772) ;
// register csrf_timer_int_en_vec_3
assign csrf_timer_int_en_vec_3$D_IN =
MUX_csrf_external_int_en_vec_3$write_1__SEL_1 ?
f_csr_reqs$D_OUT[7] :
MUX_csrf_stval_csr$write_1__VAL_1[7] ;
assign csrf_timer_int_en_vec_3$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd772 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd22 ;
// register csrf_timer_int_pend_vec_0
assign csrf_timer_int_pend_vec_0$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[4] :
f_csr_reqs$D_OUT[4] ;
assign csrf_timer_int_pend_vec_0$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_timer_int_pend_vec_1
assign csrf_timer_int_pend_vec_1$D_IN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ?
MUX_csrf_stval_csr$write_1__VAL_1[5] :
f_csr_reqs$D_OUT[5] ;
assign csrf_timer_int_pend_vec_1$EN =
MUX_csrf_external_int_pend_vec_0$write_1__SEL_1 ||
WILL_FIRE_RL_rl_debug_csr_write &&
(f_csr_reqs$D_OUT[75:64] == 12'd324 ||
f_csr_reqs$D_OUT[75:64] == 12'd836) ;
// register csrf_timer_int_pend_vec_3
assign csrf_timer_int_pend_vec_3$D_IN = mmio_pRqQ_data_0[0] ;
assign csrf_timer_int_pend_vec_3$EN =
WILL_FIRE_RL_mmio_handlePRq && mmio_pRqQ_data_0[38] &&
mmio_pRqQ_data_0[37:36] == 2'd2 ;
// register csrf_tsr_reg
assign csrf_tsr_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[22] :
MUX_csrf_stval_csr$write_1__VAL_1[22] ;
assign csrf_tsr_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18 ;
// register csrf_tvm_reg
assign csrf_tvm_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[20] :
MUX_csrf_stval_csr$write_1__VAL_1[20] ;
assign csrf_tvm_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18 ;
// register csrf_tw_reg
assign csrf_tw_reg$D_IN =
MUX_csrf_ie_vec_3$write_1__SEL_3 ?
f_csr_reqs$D_OUT[21] :
MUX_csrf_stval_csr$write_1__VAL_1[21] ;
assign csrf_tw_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd768 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18 ;
// register csrf_vm_mode_sv39_reg
assign csrf_vm_mode_sv39_reg$D_IN =
MUX_csrf_ppn_reg$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63] :
MUX_csrf_stval_csr$write_1__VAL_1[63] ;
assign csrf_vm_mode_sv39_reg$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd384 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd17 ;
// register flush_brpred
assign flush_brpred$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign flush_brpred$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
WILL_FIRE_RL_flushBrPred ;
// register flush_caches
assign flush_caches$D_IN = MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign flush_caches$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
WILL_FIRE_RL_flushCaches ;
// register flush_reservation
assign flush_reservation$D_IN = !MUX_flush_reservation$write_1__SEL_2 ;
assign flush_reservation$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
WILL_FIRE_RL_prepareCachesAndTlbs && flush_reservation ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
// register flush_tlbs
assign flush_tlbs$D_IN = !MUX_flush_tlbs$write_1__SEL_1 ;
assign flush_tlbs$EN =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
(rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd17) ;
// register mmio_cRqQ_clearReq_rl
assign mmio_cRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_data_0
assign mmio_cRqQ_data_0$D_IN =
{ x__h46077,
(mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[72] :
mmio_cRqQ_enqReq_rl[72] } :
IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463,
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[71:64] :
mmio_cRqQ_enqReq_rl[71:64],
x__h48613 } ;
assign mmio_cRqQ_data_0$EN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ;
// register mmio_cRqQ_deqReq_rl
assign mmio_cRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_empty
assign mmio_cRqQ_empty$D_IN =
mmio_cRqQ_clearReq_dummy2_1$Q_OUT && mmio_cRqQ_clearReq_rl ||
NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 ;
assign mmio_cRqQ_empty$EN = 1'd1 ;
// register mmio_cRqQ_enqReq_rl
assign mmio_cRqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_cRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRqQ_full
assign mmio_cRqQ_full$D_IN =
NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 &&
mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 ;
assign mmio_cRqQ_full$EN = 1'd1 ;
// register mmio_cRsQ_clearReq_rl
assign mmio_cRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_data_0
assign mmio_cRsQ_data_0$D_IN =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[0] :
mmio_cRsQ_enqReq_rl[0] ;
assign mmio_cRsQ_data_0$EN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ;
// register mmio_cRsQ_deqReq_rl
assign mmio_cRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_cRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_empty
assign mmio_cRsQ_empty$D_IN =
mmio_cRsQ_clearReq_dummy2_1$Q_OUT && mmio_cRsQ_clearReq_rl ||
NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 ;
assign mmio_cRsQ_empty$EN = 1'd1 ;
// register mmio_cRsQ_enqReq_rl
assign mmio_cRsQ_enqReq_rl$D_IN = 2'b0 ;
assign mmio_cRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_cRsQ_full
assign mmio_cRsQ_full$D_IN =
NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 &&
mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 ;
assign mmio_cRsQ_full$EN = 1'd1 ;
// register mmio_dataPendQ_clearReq_rl
assign mmio_dataPendQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_deqReq_rl
assign mmio_dataPendQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_empty
assign mmio_dataPendQ_empty$D_IN =
mmio_dataPendQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataPendQ_clearReq_rl ||
NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 ;
assign mmio_dataPendQ_empty$EN = 1'd1 ;
// register mmio_dataPendQ_enqReq_rl
assign mmio_dataPendQ_enqReq_rl$D_IN = 1'd0 ;
assign mmio_dataPendQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataPendQ_full
assign mmio_dataPendQ_full$D_IN =
(!mmio_dataPendQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataPendQ_clearReq_rl) &&
mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 ;
assign mmio_dataPendQ_full$EN = 1'd1 ;
// register mmio_dataReqQ_clearReq_rl
assign mmio_dataReqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_data_0
assign mmio_dataReqQ_data_0$D_IN =
{ x__h18170,
(mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd0 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd0) ?
{ 5'd2,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[72] :
mmio_dataReqQ_enqReq_rl[72] } :
IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172,
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[71:64] :
mmio_dataReqQ_enqReq_rl[71:64],
x__h20708 } ;
assign mmio_dataReqQ_data_0$EN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ;
// register mmio_dataReqQ_deqReq_rl
assign mmio_dataReqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataReqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_empty
assign mmio_dataReqQ_empty$D_IN =
mmio_dataReqQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataReqQ_clearReq_rl ||
NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 ;
assign mmio_dataReqQ_empty$EN = 1'd1 ;
// register mmio_dataReqQ_enqReq_rl
assign mmio_dataReqQ_enqReq_rl$D_IN =
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign mmio_dataReqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataReqQ_full
assign mmio_dataReqQ_full$D_IN =
NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 &&
mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 ;
assign mmio_dataReqQ_full$EN = 1'd1 ;
// register mmio_dataRespQ_clearReq_rl
assign mmio_dataRespQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_clearReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_data_0
assign mmio_dataRespQ_data_0$D_IN =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[64:0] :
mmio_dataRespQ_enqReq_rl[64:0] ;
assign mmio_dataRespQ_data_0$EN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ;
// register mmio_dataRespQ_deqReq_rl
assign mmio_dataRespQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_dataRespQ_deqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_empty
assign mmio_dataRespQ_empty$D_IN =
mmio_dataRespQ_clearReq_dummy2_1$Q_OUT &&
mmio_dataRespQ_clearReq_rl ||
NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 ;
assign mmio_dataRespQ_empty$EN = 1'd1 ;
// register mmio_dataRespQ_enqReq_rl
assign mmio_dataRespQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
assign mmio_dataRespQ_enqReq_rl$EN = 1'd1 ;
// register mmio_dataRespQ_full
assign mmio_dataRespQ_full$D_IN =
NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 &&
mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 ;
assign mmio_dataRespQ_full$EN = 1'd1 ;
// register mmio_fromHostAddr
assign mmio_fromHostAddr$D_IN = coreReq_start_fromHostAddr[63:3] ;
assign mmio_fromHostAddr$EN = EN_coreReq_start ;
// register mmio_pRqQ_clearReq_rl
assign mmio_pRqQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_data_0
assign mmio_pRqQ_data_0$D_IN =
{ EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[38] :
mmio_pRqQ_enqReq_rl[38],
(EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd0 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd0) ?
{ 5'd2,
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[32] :
mmio_pRqQ_enqReq_rl[32] } :
IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766,
x_data__h65871 } ;
assign mmio_pRqQ_data_0$EN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ;
// register mmio_pRqQ_deqReq_rl
assign mmio_pRqQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRqQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_empty
assign mmio_pRqQ_empty$D_IN =
mmio_pRqQ_clearReq_dummy2_1$Q_OUT && mmio_pRqQ_clearReq_rl ||
NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 ;
assign mmio_pRqQ_empty$EN = 1'd1 ;
// register mmio_pRqQ_enqReq_rl
assign mmio_pRqQ_enqReq_rl$D_IN = 40'h2AAAAAAAAA ;
assign mmio_pRqQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRqQ_full
assign mmio_pRqQ_full$D_IN =
NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 &&
mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 ;
assign mmio_pRqQ_full$EN = 1'd1 ;
// register mmio_pRsQ_clearReq_rl
assign mmio_pRsQ_clearReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_clearReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_data_0
assign mmio_pRsQ_data_0$D_IN =
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[66] :
mmio_pRsQ_enqReq_rl[66],
IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 } ;
assign mmio_pRsQ_data_0$EN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ;
// register mmio_pRsQ_deqReq_rl
assign mmio_pRsQ_deqReq_rl$D_IN = 1'd0 ;
assign mmio_pRsQ_deqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_empty
assign mmio_pRsQ_empty$D_IN =
mmio_pRsQ_clearReq_dummy2_1$Q_OUT && mmio_pRsQ_clearReq_rl ||
NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 ;
assign mmio_pRsQ_empty$EN = 1'd1 ;
// register mmio_pRsQ_enqReq_rl
assign mmio_pRsQ_enqReq_rl$D_IN = 68'h2AAAAAAAAAAAAAAAA ;
assign mmio_pRsQ_enqReq_rl$EN = 1'd1 ;
// register mmio_pRsQ_full
assign mmio_pRsQ_full$D_IN =
NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 &&
mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 ;
assign mmio_pRsQ_full$EN = 1'd1 ;
// register mmio_toHostAddr
assign mmio_toHostAddr$D_IN = coreReq_start_toHostAddr[63:3] ;
assign mmio_toHostAddr$EN = EN_coreReq_start ;
// register outOfReset
assign outOfReset$D_IN = 1'd1 ;
assign outOfReset$EN = CAN_FIRE_RL_rl_outOfReset ;
// register renameStage_rg_m_halt_req
always@(WILL_FIRE_RL_rl_debug_resume or
WILL_FIRE_RL_rl_debug_halt_req or
MUX_renameStage_rg_m_halt_req$write_1__SEL_1 or
MUX_renameStage_rg_m_halt_req$write_1__SEL_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_resume: renameStage_rg_m_halt_req$D_IN = 5'd10;
WILL_FIRE_RL_rl_debug_halt_req: renameStage_rg_m_halt_req$D_IN = 5'd30;
MUX_renameStage_rg_m_halt_req$write_1__SEL_1 ||
MUX_renameStage_rg_m_halt_req$write_1__SEL_2:
renameStage_rg_m_halt_req$D_IN = 5'd31;
default: renameStage_rg_m_halt_req$D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign renameStage_rg_m_halt_req$EN =
(WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap) &&
csrf_rg_dcsr[2] ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
csrf_rg_dcsr[2] ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_rl_debug_halt_req ;
// register rg_core_run_state
always@(WILL_FIRE_RL_rl_debug_resume or
WILL_FIRE_RL_rl_debug_halted or
EN_coreReq_start or MUX_rg_core_run_state$write_1__SEL_4)
case (1'b1)
WILL_FIRE_RL_rl_debug_resume: rg_core_run_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_debug_halted: rg_core_run_state$D_IN = 2'd1;
EN_coreReq_start: rg_core_run_state$D_IN = 2'd2;
MUX_rg_core_run_state$write_1__SEL_4: rg_core_run_state$D_IN = 2'd0;
default: rg_core_run_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_core_run_state$EN =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
WILL_FIRE_RL_rl_debug_halted ||
WILL_FIRE_RL_rl_debug_resume ||
EN_coreReq_start ;
// register started
assign started$D_IN = WILL_FIRE_RL_rl_debug_resume || EN_coreReq_start ;
assign started$EN =
WILL_FIRE_RL_readyToFetch && commitStage_rg_run_state ||
WILL_FIRE_RL_rl_debug_resume ||
EN_coreReq_start ;
// register update_vm_info
assign update_vm_info$D_IN =
!MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ;
assign update_vm_info$EN =
WILL_FIRE_RL_commitStage_doCommitTrap_handle && _dfoo20 ||
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
// submodule coreFix_aluExe_0_dispToRegQ
assign coreFix_aluExe_0_dispToRegQ$enq_x =
{ coreFix_aluExe_0_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278,
coreFix_aluExe_0_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279,
coreFix_aluExe_0_rsAlu$dispatchData[122:90],
coreFix_aluExe_0_rsAlu$dispatchData[65:21],
coreFix_aluExe_0_rsAlu$dispatchData[89:66],
coreFix_aluExe_0_rsAlu$dispatchData[8:4],
coreFix_aluExe_0_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
!WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T &&
!WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_exeToFinQ
assign coreFix_aluExe_0_exeToFinQ$enq_x =
{ coreFix_aluExe_0_regToExeQ$first[421:417],
coreFix_aluExe_0_regToExeQ$first[349:305],
coreFix_aluExe_0_regToExeQ$first[18:17] != 2'b11,
basicExec___d12557[321:258],
coreFix_aluExe_0_regToExeQ$first[395],
basicExec___d12557[257:194],
basicExec___d12557[129:0],
coreFix_aluExe_0_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_regToExeQ
assign coreFix_aluExe_0_regToExeQ$enq_x =
{ coreFix_aluExe_0_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q281,
coreFix_aluExe_0_dispToRegQ$first[131],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282,
coreFix_aluExe_0_dispToRegQ$first[118:86],
coreFix_aluExe_0_dispToRegQ$first[61:17],
x__h636385,
x__h636386,
rob$getOrigPC_0_get,
rob$getOrigPredPC_0_get,
rob$getOrig_Inst_0_get,
coreFix_aluExe_0_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_0_doRegReadAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_0_doExeAlu ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_0_rsAlu
assign coreFix_aluExe_0_rsAlu$enq_x =
MUX_coreFix_aluExe_0_rsAlu$enq_1__SEL_1 ?
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_1 :
MUX_coreFix_aluExe_0_rsAlu$enq_1__VAL_2 ;
assign coreFix_aluExe_0_rsAlu$setRegReady_0_put =
{ 1'd1, coreFix_aluExe_0_rsAlu$dispatchData[40:34] } ;
assign coreFix_aluExe_0_rsAlu$setRegReady_1_put =
{ 1'd1, coreFix_aluExe_1_rsAlu$dispatchData[40:34] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_0_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_0_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRegReady_3_put =
{ 1'd1, coreFix_memExe_lsq$issueLd[71:65] } ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_0_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_aluExe_0_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_0_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_0_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_0_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo18 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst &&
fetchStage$pipelines_0_first[194:192] == 3'd0 ;
assign coreFix_aluExe_0_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_0_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_0_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_0_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_dispToRegQ
assign coreFix_aluExe_1_dispToRegQ$enq_x =
{ coreFix_aluExe_1_rsAlu$dispatchData[161:157],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284,
coreFix_aluExe_1_rsAlu$dispatchData[135],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285,
coreFix_aluExe_1_rsAlu$dispatchData[122:90],
coreFix_aluExe_1_rsAlu$dispatchData[65:21],
coreFix_aluExe_1_rsAlu$dispatchData[89:66],
coreFix_aluExe_1_rsAlu$dispatchData[8:4],
coreFix_aluExe_1_rsAlu$dispatchData[20:9] } ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_exeToFinQ
assign coreFix_aluExe_1_exeToFinQ$enq_x =
{ coreFix_aluExe_1_regToExeQ$first[421:417],
coreFix_aluExe_1_regToExeQ$first[349:305],
coreFix_aluExe_1_regToExeQ$first[18:17] != 2'b11,
basicExec___d11911[321:258],
coreFix_aluExe_1_regToExeQ$first[395],
basicExec___d11911[257:194],
basicExec___d11911[129:0],
coreFix_aluExe_1_regToExeQ$first[16:0] } ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_exeToFinQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_exeToFinQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_exeToFinQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_exeToFinQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_regToExeQ
assign coreFix_aluExe_1_regToExeQ$enq_x =
{ coreFix_aluExe_1_dispToRegQ$first[157:153],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q287,
coreFix_aluExe_1_dispToRegQ$first[131],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q288,
coreFix_aluExe_1_dispToRegQ$first[118:86],
coreFix_aluExe_1_dispToRegQ$first[61:17],
x__h614524,
x__h614525,
rob$getOrigPC_1_get,
rob$getOrigPredPC_1_get,
rob$getOrig_Inst_1_get,
coreFix_aluExe_1_dispToRegQ$first[16:0] } ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_aluExe_1_doRegReadAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_aluExe_1_doExeAlu ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_aluExe_1_rsAlu
assign coreFix_aluExe_1_rsAlu$enq_x =
(k__h664083 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017) ?
{ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826,
fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908,
fetchStage$pipelines_0_first[160:128],
fetchStage$pipelines_0_first[255:232],
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510,
fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594,
fetchStage$pipelines_1_first[160:128],
fetchStage$pipelines_1_first[255:232],
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h678574,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_aluExe_1_rsAlu$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_aluExe_1_rsAlu$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_aluExe_1_rsAlu$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_aluExe_1_rsAlu$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_1:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_aluExe_1_rsAlu$setRegReady_4_put_1__SEL_2:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_aluExe_1_rsAlu$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_aluExe_1_rsAlu$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_aluExe_1_rsAlu$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_aluExe_1_rsAlu$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_aluExe_1_rsAlu$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo16 ;
assign coreFix_aluExe_1_rsAlu$EN_setRobEnqTime = 1'd1 ;
assign coreFix_aluExe_1_rsAlu$EN_doDispatch =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
_dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_aluExe_1_rsAlu$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_aluExe_1_rsAlu$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_fpuMulDivExe_0_dispToRegQ
assign coreFix_fpuMulDivExe_0_dispToRegQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[65:9] } ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_dispToRegQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_divQ
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714,
coreFix_fpuMulDivExe_0_regToExeQ$first[225],
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10851,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10887,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10935,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10977,
!coreFix_fpuMulDivExe_0_regToExeQ$first[225] &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11019,
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_div
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10651,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd3 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_div$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_fma
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$request_put =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q291,
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fma$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_double_sqrt
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$request_put =
{ IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171,
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 } ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_request_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$EN_response_get =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_fmaQ
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_fmaQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd2 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqFmaPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_simpleQ
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$enq_x =
{ execFpuSimple___d11053,
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_simpleQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd25 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd26 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd27 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_deq =
CAN_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_simpleQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_fpuExec_sqrtQ
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$enq_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$enq_x ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd4 ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_fpuExec_deqSqrtPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divQ
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_divQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tdata =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___fst__h601214 :
a__h600792 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tuser =
{ b__h600793 == 64'd0,
a__h600792,
coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0,
x__h601228,
a__h600792[63],
8'd0 } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tdata =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
_theResult___snd__h601215 :
b__h600793 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tvalid =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tvalid =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd0 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] != 2'd1 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tready =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqDivPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulQ
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$enq_x =
{ coreFix_fpuMulDivExe_0_regToExeQ$first[229:227],
coreFix_fpuMulDivExe_0_regToExeQ$first[224:204],
coreFix_fpuMulDivExe_0_regToExeQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_mulDivExec_mulQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv &&
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd3 &&
(coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[229:228] == 2'd1) ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_mulDivExec_deqMulPoisoned ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$A = a__h600792 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$B = b__h600793 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$A =
a__h600792 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$B =
b__h600793 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$A =
a__h600792 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$B =
b__h600793 ;
// submodule coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ
always@(coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P)
begin
case (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[1:0])
2'd0:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSigned$P;
2'd1:
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulUnsigned$P;
default: coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_IN =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_mulSignedUnsigned$P;
endcase
end
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$ENQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1[2] ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$DEQ =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$CLR = 1'b0 ;
// submodule coreFix_fpuMulDivExe_0_regToExeQ
assign coreFix_fpuMulDivExe_0_regToExeQ$enq_x =
{ CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294,
coreFix_fpuMulDivExe_0_dispToRegQ$first[32:12],
x__h479514,
x__h479515,
x__h479516,
coreFix_fpuMulDivExe_0_dispToRegQ$first[11:0] } ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doRegReadFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_deq =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doExeFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_regToExeQ$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_fpuMulDivExe_0_rsFpuMulDiv
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029) ?
{ IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h678574,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_1:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put_1__SEL_2:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_fpuMulDivExe_0_rsFpuMulDiv$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163) ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRobEnqTime = 1'd1 ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_doDispatch =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doDispatchFpuMulDiv ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
_dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_specUpdate_correctSpeculation =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getEmptyEntryInit_r =
{ x__h285126,
x__h285138,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824,
x__h286992,
IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840,
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$cRqTransfer_getRq_n =
x__h283692 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[578:577] ==
2'd0) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] :
3'd0) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSlot_n =
3'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq_n ;
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1 or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574];
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[159:157];
default: coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_n =
3'b010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain_addr =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:84] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_d =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_n =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_slot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_state =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 :
3'd3 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_n =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setSucc_succ =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRqToP_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getState_n =
3'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_setWaitSt_setSlot_clearData_slot =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[57:55],
55'h15555555555555 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_cRqTransfer_getEmptyEntryInit =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_sendRsToP_cRq_setWaitSt_setSlot_clearData =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setStateSlot =
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_pipelineResp_setSucc =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_0$EN =
EN_dCacheToParent_fromP_enq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 &&
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ==
2'd0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$EN =
MUX_flush_reservation$write_1__SEL_2 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pRqMshr
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$getEmptyEntryInit_r =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getState_n =
2'h0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_d =
{ !coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd3,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_setDone_setData_n =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[575:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getData_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_getRq_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$sendRsToP_pRq_releaseEntry_n =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_getEmptyEntryInit =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_sendRsToP_pRq_releaseEntry =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_releaseEntry =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_pipelineResp_setDone_setData =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$EN_stuck_get = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_pipeline
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
coreFix_memExe_dMem_cache_m_banks_0_processAmo or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[3:0];
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq = 4'd2;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_swapRq =
4'b1010 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_3__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd0;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'd1;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_updateRep =
1'b0 /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2 or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_1;
MUX_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_releaseEntry_1__SEL_2:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_2__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_wrRam =
570'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3 or
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer or
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_1;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_2;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_3;
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer:
coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_1__VAL_4;
default: coreFix_memExe_dMem_cache_m_banks_0_pipeline$send_r =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_send =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRqTransfer ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pRsTransfer ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline$EN_deqWrite =
MUX_coreFix_memExe_dMem_cache_m_banks_0_pipeline$deqWrite_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_deqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$EN =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_new ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$D_IN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_OUT :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_OUT ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$DEQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromPipelineResp ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$D_IN =
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_OUT[2:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$ENQ =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_rqIndexFromSendRsToP ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_sendRsToP$CLR =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rqToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$D_IN =
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__SEL_1 ?
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_1 :
MUX_coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$enq_1__VAL_2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$ENQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$DEQ =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$CLR = 1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_0$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_0$EN =
EN_dCacheToParent_rsToP_deq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_pRq ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRsToP_cRq ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$D_IN =
1'b0 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_1$EN =
1'b0 ;
// submodule coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$D_IN =
1'd1 ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$EN =
1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_dTlb
assign coreFix_memExe_dTlb$perf_req_r = 3'h0 ;
assign coreFix_memExe_dTlb$perf_setStatus_doStats = 1'b0 ;
assign coreFix_memExe_dTlb$procReq_req =
{ coreFix_memExe_regToExeQ$first[192:190],
coreFix_memExe_regToExeQ$first[157:140],
coreFix_memExe_lsq$getOrigBE << vaddr__h181135[2:0],
vaddr__h181135,
coreFix_memExe_lsq$getOrigBE[7] ?
vaddr__h181135[2:0] != 3'd0 :
(coreFix_memExe_lsq$getOrigBE[3] ?
vaddr__h181135[1:0] != 2'd0 :
coreFix_memExe_lsq$getOrigBE[1] && vaddr__h181135[0]),
coreFix_memExe_regToExeQ$first[11:0] } ;
assign coreFix_memExe_dTlb$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dTlb$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dTlb$toParent_ldTransRsFromP_enq_x =
{ l2Tlb$toChildren_rsToC_first[80:0],
l2Tlb$toChildren_rsToC_first[82:81] } ;
assign coreFix_memExe_dTlb$updateVMInfo_vm =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
assign coreFix_memExe_dTlb$EN_flush =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_rl_debug_resume ;
assign coreFix_memExe_dTlb$EN_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign coreFix_memExe_dTlb$EN_procReq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_dTlb$EN_deqProcResp =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_dTlb$EN_toParent_rqToP_deq = CAN_FIRE_RL_sendDTlbReq ;
assign coreFix_memExe_dTlb$EN_toParent_ldTransRsFromP_enq =
CAN_FIRE_RL_sendRsToDTlb ;
assign coreFix_memExe_dTlb$EN_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut ;
assign coreFix_memExe_dTlb$EN_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign coreFix_memExe_dTlb$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dTlb$EN_specUpdate_correctSpeculation = 1'd1 ;
assign coreFix_memExe_dTlb$EN_perf_setStatus = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_req = 1'b0 ;
assign coreFix_memExe_dTlb$EN_perf_resp = 1'b0 ;
// submodule coreFix_memExe_dispToRegQ
assign coreFix_memExe_dispToRegQ$enq_x =
{ coreFix_memExe_rsMem$dispatchData[106:72],
coreFix_memExe_rsMem$dispatchData[65:21],
coreFix_memExe_rsMem$dispatchData[71:66],
coreFix_memExe_rsMem$dispatchData[20:9] } ;
assign coreFix_memExe_dispToRegQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_dispToRegQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_dispToRegQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_dispToRegQ$EN_deq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_dispToRegQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_0
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_clearReq_dummy2_1
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_0
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_1
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_deqReq_dummy2_2
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_0
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_0$EN =
_dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_1
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_forwardQ_enqReq_dummy2_2
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_lsq
assign coreFix_memExe_lsq$enqLd_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqLd_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqLd_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqLd_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h678574 ;
assign coreFix_memExe_lsq$enqSt_dst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ?
regRenamingTable$rename_0_getRename[8:0] :
regRenamingTable$rename_1_getRename[8:0] ;
assign coreFix_memExe_lsq$enqSt_inst_tag =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ?
rob$enqPort_0_getEnqInstTag :
rob$enqPort_1_getEnqInstTag ;
assign coreFix_memExe_lsq$enqSt_mem_inst =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ?
fetchStage$pipelines_0_first[191:174] :
fetchStage$pipelines_1_first[191:174] ;
assign coreFix_memExe_lsq$enqSt_spec_bits =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063) ?
specTagManager$currentSpecBits :
renaming_spec_bits__h678574 ;
assign coreFix_memExe_lsq$getHit_t =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ?
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 :
MUX_coreFix_memExe_lsq$getHit_1__VAL_1 ;
assign coreFix_memExe_lsq$getOrigBE_t =
coreFix_memExe_regToExeQ$first[145:140] ;
assign coreFix_memExe_lsq$issueLd_lsqTag =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[76:72] :
coreFix_memExe_issueLd$wget[76:72] ;
assign coreFix_memExe_lsq$issueLd_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_lsq$issueLd_sbRes =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
MUX_coreFix_memExe_lsq$issueLd_4__VAL_1 :
coreFix_memExe_stb$search ;
assign coreFix_memExe_lsq$issueLd_shiftedBE =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_lsq$respLd_alignedData =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_2__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_2__VAL_2 ;
assign coreFix_memExe_lsq$respLd_t =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ?
MUX_coreFix_memExe_lsq$respLd_1__VAL_1 :
MUX_coreFix_memExe_lsq$respLd_1__VAL_2 ;
assign coreFix_memExe_lsq$setAtCommit_0_put =
rob$deqPort_0_deq_data[24:19] ;
assign coreFix_memExe_lsq$setAtCommit_1_put =
rob$deqPort_1_deq_data[24:19] ;
assign coreFix_memExe_lsq$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_lsq$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_lsq$updateAddr_fault =
{ (!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
coreFix_memExe_dTlb$procResp[12] :
coreFix_memExe_dTlb$procResp[12] ||
coreFix_memExe_dTlb$procResp[110],
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857 } ;
assign coreFix_memExe_lsq$updateAddr_isMMIO =
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 ;
assign coreFix_memExe_lsq$updateAddr_lsqTag =
coreFix_memExe_dTlb$procResp[90:85] ;
assign coreFix_memExe_lsq$updateAddr_paddr =
coreFix_memExe_dTlb$procResp[174:111] ;
assign coreFix_memExe_lsq$updateAddr_shiftedBE =
coreFix_memExe_dTlb$procResp[84:77] ;
assign coreFix_memExe_lsq$updateData_d =
(coreFix_memExe_regToExeQ$first[192:190] == 3'd4) ?
coreFix_memExe_regToExeQ$first[75:12] :
shiftData__h181140 ;
assign coreFix_memExe_lsq$updateData_t =
coreFix_memExe_regToExeQ$first[143:140] ;
assign coreFix_memExe_lsq$wakeupLdStalledBySB_sbIdx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_lsq$EN_enqLd =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo7 ;
assign coreFix_memExe_lsq$EN_enqSt =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo2 ;
assign coreFix_memExe_lsq$EN_getHit =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign coreFix_memExe_lsq$EN_updateData =
WILL_FIRE_RL_coreFix_memExe_doExeMem &&
coreFix_memExe_regToExeQ$first[145] ;
assign coreFix_memExe_lsq$EN_updateAddr =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign coreFix_memExe_lsq$EN_issueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign coreFix_memExe_lsq$EN_getIssueLd =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ;
assign coreFix_memExe_lsq$EN_respLd =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ;
assign coreFix_memExe_lsq$EN_deqLd =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ;
assign coreFix_memExe_lsq$EN_deqSt =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ;
assign coreFix_memExe_lsq$EN_wakeupLdStalledBySB =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_lsq$EN_setAtCommit_0_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit ;
assign coreFix_memExe_lsq$EN_setAtCommit_1_put =
CAN_FIRE_RL_commitStage_doSetLSQAtCommit_1 ;
assign coreFix_memExe_lsq$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_lsq$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_0
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_clearReq_dummy2_1
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_deqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_0
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_0$EN =
MUX_coreFix_memExe_lsq$getHit_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_1
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_memRespLdQ_enqReq_dummy2_2
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_regToExeQ
assign coreFix_memExe_regToExeQ$enq_x =
{ coreFix_memExe_dispToRegQ$first[97:63],
coreFix_memExe_dispToRegQ$first[29:12],
x__h181049,
x__h181050,
coreFix_memExe_dispToRegQ$first[11:0] } ;
assign coreFix_memExe_regToExeQ$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_regToExeQ$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_regToExeQ$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doRegReadMem ;
assign coreFix_memExe_regToExeQ$EN_deq =
CAN_FIRE_RL_coreFix_memExe_doExeMem ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_regToExeQ$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_0
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_data_0_dummy2_1
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_0
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_deqP_dummy2_1
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_0
assign coreFix_memExe_reqLdQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_1
assign coreFix_memExe_reqLdQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_empty_dummy2_2
assign coreFix_memExe_reqLdQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_0
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_enqP_dummy2_1
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_0
assign coreFix_memExe_reqLdQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_0$EN =
_dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write &&
coreFix_memExe_lsq$issueLd[74:73] == 2'd0 ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_1
assign coreFix_memExe_reqLdQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLdQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendLdToMem ;
// submodule coreFix_memExe_reqLdQ_full_dummy2_2
assign coreFix_memExe_reqLdQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLdQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_empty_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_0
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_0$EN =
coreFix_memExe_reqLrScAmoQ_enqP_lat_0$whas ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_1
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_1$EN =
CAN_FIRE_RL_coreFix_memExe_sendLrScAmoToMem ;
// submodule coreFix_memExe_reqLrScAmoQ_full_dummy2_2
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqLrScAmoQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_0
assign coreFix_memExe_reqStQ_data_0_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_data_0_dummy2_1
assign coreFix_memExe_reqStQ_data_0_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_data_0_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_0
assign coreFix_memExe_reqStQ_deqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_deqP_dummy2_1
assign coreFix_memExe_reqStQ_deqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_deqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_0
assign coreFix_memExe_reqStQ_empty_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_1
assign coreFix_memExe_reqStQ_empty_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_empty_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_empty_dummy2_2
assign coreFix_memExe_reqStQ_empty_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_empty_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_0
assign coreFix_memExe_reqStQ_enqP_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_enqP_dummy2_1
assign coreFix_memExe_reqStQ_enqP_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_enqP_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_reqStQ_full_dummy2_0
assign coreFix_memExe_reqStQ_full_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_0$EN =
CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_memExe_reqStQ_full_dummy2_1
assign coreFix_memExe_reqStQ_full_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_reqStQ_full_dummy2_1$EN =
WILL_FIRE_RL_coreFix_memExe_sendStToMem ;
// submodule coreFix_memExe_reqStQ_full_dummy2_2
assign coreFix_memExe_reqStQ_full_dummy2_2$D_IN = 1'b0 ;
assign coreFix_memExe_reqStQ_full_dummy2_2$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_0$EN =
coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_doProcessAmo ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule coreFix_memExe_rsMem
assign coreFix_memExe_rsMem$enq_x =
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035) ?
{ fetchStage$pipelines_0_first[191:189],
IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051,
regRenamingTable$rename_0_getRename,
rob$enqPort_0_getEnqInstTag,
specTagManager$currentSpecBits,
fetchStage$pipelines_0_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_0_get } :
{ fetchStage$pipelines_1_first[191:189],
IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180,
regRenamingTable$rename_1_getRename,
rob$enqPort_1_getEnqInstTag,
renaming_spec_bits__h678574,
fetchStage$pipelines_1_first[194:192] == 3'd1,
specTagManager$nextSpecTag,
sbAggr$eagerLookup_1_get } ;
assign coreFix_memExe_rsMem$setRegReady_0_put =
coreFix_aluExe_0_rsAlu$setRegReady_0_put ;
assign coreFix_memExe_rsMem$setRegReady_1_put =
coreFix_aluExe_0_rsAlu$setRegReady_1_put ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
coreFix_memExe_rsMem$setRegReady_2_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__VAL_6;
default: coreFix_memExe_rsMem$setRegReady_2_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRegReady_3_put =
coreFix_aluExe_0_rsAlu$setRegReady_3_put ;
always@(MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1 or
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_1:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_1;
MUX_coreFix_memExe_rsMem$setRegReady_4_put_1__SEL_2:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_2;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
coreFix_memExe_rsMem$setRegReady_4_put =
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__VAL_3;
default: coreFix_memExe_rsMem$setRegReady_4_put =
8'b10101010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$setRobEnqTime_t = rob$getEnqTime ;
assign coreFix_memExe_rsMem$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: coreFix_memExe_rsMem$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign coreFix_memExe_rsMem$EN_enq =
WILL_FIRE_RL_renameStage_doRenaming && _dfoo12 ;
assign coreFix_memExe_rsMem$EN_setRobEnqTime = 1'd1 ;
assign coreFix_memExe_rsMem$EN_doDispatch =
WILL_FIRE_RL_coreFix_memExe_doDispatchMem ;
assign coreFix_memExe_rsMem$EN_setRegReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign coreFix_memExe_rsMem$EN_setRegReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign coreFix_memExe_rsMem$EN_setRegReady_3_put =
_dor1coreFix_memExe_rsMem$EN_setRegReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign coreFix_memExe_rsMem$EN_setRegReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_rsMem$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign coreFix_memExe_rsMem$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule coreFix_memExe_stb
assign coreFix_memExe_stb$deq_idx =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[149:148] ;
assign coreFix_memExe_stb$enq_be = coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$enq_data = coreFix_memExe_lsq$firstSt[68:5] ;
assign coreFix_memExe_stb$enq_idx = coreFix_memExe_stb$getEnqIndex[1:0] ;
assign coreFix_memExe_stb$enq_paddr = coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$getEnqIndex_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$noMatchLdQ_be = coreFix_memExe_lsq$firstLd[15:8] ;
assign coreFix_memExe_stb$noMatchLdQ_paddr =
coreFix_memExe_lsq$firstLd[80:17] ;
assign coreFix_memExe_stb$noMatchStQ_be =
coreFix_memExe_lsq$firstSt[76:69] ;
assign coreFix_memExe_stb$noMatchStQ_paddr =
coreFix_memExe_lsq$firstSt[141:78] ;
assign coreFix_memExe_stb$search_be =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[7:0] :
coreFix_memExe_issueLd$wget[7:0] ;
assign coreFix_memExe_stb$search_paddr =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ?
coreFix_memExe_lsq$getIssueLd[71:8] :
coreFix_memExe_issueLd$wget[71:8] ;
assign coreFix_memExe_stb$EN_enq =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_St_Mem ;
assign coreFix_memExe_stb$EN_deq =
MUX_coreFix_memExe_lsq$wakeupLdStalledBySB_1__SEL_1 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign coreFix_memExe_stb$EN_issue = CAN_FIRE_RL_coreFix_memExe_doIssueSB ;
// submodule coreFix_trainBPQ_0
assign coreFix_trainBPQ_0$D_IN =
MUX_coreFix_trainBPQ_0$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_0$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_0$enq_1__VAL_2 ;
assign coreFix_trainBPQ_0$ENQ =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_0_exeToFinQ$first[326:322] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign coreFix_trainBPQ_0$DEQ = WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign coreFix_trainBPQ_0$CLR = 1'b0 ;
// submodule coreFix_trainBPQ_1
assign coreFix_trainBPQ_1$D_IN =
MUX_coreFix_trainBPQ_1$enq_1__SEL_1 ?
MUX_coreFix_trainBPQ_1$enq_1__VAL_1 :
MUX_coreFix_trainBPQ_1$enq_1__VAL_2 ;
assign coreFix_trainBPQ_1$ENQ =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd9 ||
coreFix_aluExe_1_exeToFinQ$first[326:322] == 5'd10) ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign coreFix_trainBPQ_1$DEQ = coreFix_trainBPQ_1$EMPTY_N ;
assign coreFix_trainBPQ_1$CLR = 1'b0 ;
// submodule csrInstOrInterruptInflight_dummy2_0
assign csrInstOrInterruptInflight_dummy2_0$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_0$EN =
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd3) ;
// submodule csrInstOrInterruptInflight_dummy2_1
assign csrInstOrInterruptInflight_dummy2_1$D_IN = 1'd1 ;
assign csrInstOrInterruptInflight_dummy2_1$EN =
csrInstOrInterruptInflight_lat_1$whas ;
// submodule csrf_mcycle_ehr_data_dummy2_0
assign csrf_mcycle_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2816 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd30 ;
// submodule csrf_mcycle_ehr_data_dummy2_1
assign csrf_mcycle_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_mcycle_ehr_data_dummy2_1$EN = 1'd1 ;
// submodule csrf_minstret_ehr_data_dummy2_0
assign csrf_minstret_ehr_data_dummy2_0$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_0$EN =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2818 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd31 ;
// submodule csrf_minstret_ehr_data_dummy2_1
assign csrf_minstret_ehr_data_dummy2_1$D_IN = 1'd1 ;
assign csrf_minstret_ehr_data_dummy2_1$EN =
csrf_minstret_ehr_data_dummy_1_0$whas ;
// submodule csrf_stats_module_writeQ
assign csrf_stats_module_writeQ$D_IN =
MUX_csrf_stats_module_writeQ$enq_1__SEL_1 ?
f_csr_reqs$D_OUT[0] :
MUX_csrf_stval_csr$write_1__VAL_1[0] ;
assign csrf_stats_module_writeQ$ENQ =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2049 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd7 ;
assign csrf_stats_module_writeQ$DEQ = EN_sendDoStats ;
assign csrf_stats_module_writeQ$CLR = 1'b0 ;
// submodule csrf_terminate_module_terminateQ
assign csrf_terminate_module_terminateQ$ENQ =
WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2048 ||
WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd6 ;
assign csrf_terminate_module_terminateQ$DEQ = EN_coreIndInv_terminate ;
assign csrf_terminate_module_terminateQ$CLR = 1'b0 ;
// submodule epochManager
assign epochManager$checkEpoch_0_check_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$checkEpoch_1_check_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$updatePrevEpoch_0_update_e =
fetchStage$pipelines_0_first[259:256] ;
assign epochManager$updatePrevEpoch_1_update_e =
fetchStage$pipelines_1_first[259:256] ;
assign epochManager$EN_updatePrevEpoch_0_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign epochManager$EN_updatePrevEpoch_1_update =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 &&
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ;
assign epochManager$EN_incrementEpoch =
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
// submodule f_csr_reqs
assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ;
assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ;
assign f_csr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_csr_access_busy ||
WILL_FIRE_RL_rl_debug_csr_write ||
WILL_FIRE_RL_rl_debug_csr_read ;
assign f_csr_reqs$CLR = 1'b0 ;
// submodule f_csr_rsps
always@(WILL_FIRE_RL_rl_debug_csr_access_busy or
WILL_FIRE_RL_rl_debug_csr_write or
WILL_FIRE_RL_rl_debug_csr_read or MUX_f_csr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_csr_access_busy:
f_csr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_csr_write:
f_csr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_csr_read:
f_csr_rsps$D_IN = MUX_f_csr_rsps$enq_1__VAL_3;
default: f_csr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_csr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_csr_access_busy ||
WILL_FIRE_RL_rl_debug_csr_write ||
WILL_FIRE_RL_rl_debug_csr_read ;
assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ;
assign f_csr_rsps$CLR = 1'b0 ;
// submodule f_fpr_reqs
assign f_fpr_reqs$D_IN = hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$ENQ = EN_hart0_fpr_mem_server_request_put ;
assign f_fpr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_fpr_access_busy ||
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign f_fpr_reqs$CLR = 1'b0 ;
// submodule f_fpr_rsps
always@(WILL_FIRE_RL_rl_debug_fpr_access_busy or
WILL_FIRE_RL_rl_debug_fpr_write or
WILL_FIRE_RL_rl_debug_fpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_fpr_access_busy:
f_fpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_fpr_write:
f_fpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_fpr_read:
f_fpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
default: f_fpr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fpr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_fpr_access_busy ||
WILL_FIRE_RL_rl_debug_fpr_write ||
WILL_FIRE_RL_rl_debug_fpr_read ;
assign f_fpr_rsps$DEQ = EN_hart0_fpr_mem_server_response_get ;
assign f_fpr_rsps$CLR = 1'b0 ;
// submodule f_gpr_reqs
assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ;
assign f_gpr_reqs$DEQ =
WILL_FIRE_RL_rl_debug_gpr_access_busy ||
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign f_gpr_reqs$CLR = 1'b0 ;
// submodule f_gpr_rsps
always@(WILL_FIRE_RL_rl_debug_gpr_access_busy or
WILL_FIRE_RL_rl_debug_gpr_write or
WILL_FIRE_RL_rl_debug_gpr_read or MUX_f_fpr_rsps$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_debug_gpr_access_busy:
f_gpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_gpr_write:
f_gpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_debug_gpr_read:
f_gpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
default: f_gpr_rsps$D_IN =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_gpr_rsps$ENQ =
WILL_FIRE_RL_rl_debug_gpr_access_busy ||
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_gpr_read ;
assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ;
assign f_gpr_rsps$CLR = 1'b0 ;
// submodule f_run_halt_reqs
assign f_run_halt_reqs$D_IN = hart0_run_halt_server_request_put ;
assign f_run_halt_reqs$ENQ = EN_hart0_run_halt_server_request_put ;
assign f_run_halt_reqs$DEQ =
WILL_FIRE_RL_rl_debug_run_redundant ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_rl_debug_halt_req_already_halted ||
WILL_FIRE_RL_rl_debug_halt_req ;
assign f_run_halt_reqs$CLR = 1'b0 ;
// submodule f_run_halt_rsps
assign f_run_halt_rsps$D_IN = !WILL_FIRE_RL_rl_debug_halted ;
assign f_run_halt_rsps$ENQ =
WILL_FIRE_RL_rl_debug_halted ||
WILL_FIRE_RL_rl_debug_run_redundant ||
WILL_FIRE_RL_rl_debug_resume ;
assign f_run_halt_rsps$DEQ = EN_hart0_run_halt_server_response_get ;
assign f_run_halt_rsps$CLR = 1'b0 ;
// submodule fetchStage
assign fetchStage$iMemIfc_perf_req_r = 2'h0 ;
assign fetchStage$iMemIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iMemIfc_to_parent_fromP_enq_x =
iCacheToParent_fromP_enq_x ;
assign fetchStage$iMemIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_perf_req_r = 3'h0 ;
assign fetchStage$iTlbIfc_perf_setStatus_doStats = 1'b0 ;
assign fetchStage$iTlbIfc_toParent_rsFromP_enq_x =
l2Tlb$toChildren_rsToC_first[80:0] ;
assign fetchStage$iTlbIfc_to_proc_request_put = 64'h0 ;
assign fetchStage$iTlbIfc_updateVMInfo_vm =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 :
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ;
assign fetchStage$mmioIfc_instResp_enq_x = mmio_pRsQ_data_0[65:0] ;
assign fetchStage$mmioIfc_setHtifAddrs_fromHost =
coreReq_start_fromHostAddr ;
assign fetchStage$mmioIfc_setHtifAddrs_toHost = coreReq_start_toHostAddr ;
assign fetchStage$perf_req_r = 2'h0 ;
assign fetchStage$perf_setStatus_doStats = 1'b0 ;
always@(MUX_csrf_prv_reg$write_1__SEL_2 or
MUX_fetchStage$redirect_1__VAL_1 or
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
WILL_FIRE_RL_commitStage_doCommitKilledLd or
rob$deqPort_0_deq_data or
WILL_FIRE_RL_rl_debug_resume or
csrf_rg_dpc or
WILL_FIRE_RL_commitStage_doCommitSystemInst or
MUX_fetchStage$redirect_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_csrf_prv_reg$write_1__SEL_2:
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_1;
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_1_exeToFinQ$first[82:19];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
fetchStage$redirect_pc = coreFix_aluExe_0_exeToFinQ$first[82:19];
WILL_FIRE_RL_commitStage_doCommitKilledLd:
fetchStage$redirect_pc = rob$deqPort_0_deq_data[282:219];
WILL_FIRE_RL_rl_debug_resume: fetchStage$redirect_pc = csrf_rg_dpc;
WILL_FIRE_RL_commitStage_doCommitSystemInst:
fetchStage$redirect_pc = MUX_fetchStage$redirect_1__VAL_6;
default: fetchStage$redirect_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fetchStage$start_pc = coreReq_start_startpc ;
assign fetchStage$train_predictors_dpTrain =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[25:2] :
coreFix_trainBPQ_0$D_OUT[25:2] ;
assign fetchStage$train_predictors_iType =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[31:27] :
coreFix_trainBPQ_0$D_OUT[31:27] ;
assign fetchStage$train_predictors_isCompressed =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[0] :
coreFix_trainBPQ_0$D_OUT[0] ;
assign fetchStage$train_predictors_mispred =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[1] :
coreFix_trainBPQ_0$D_OUT[1] ;
assign fetchStage$train_predictors_next_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[95:32] :
coreFix_trainBPQ_0$D_OUT[95:32] ;
assign fetchStage$train_predictors_pc =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[159:96] :
coreFix_trainBPQ_0$D_OUT[159:96] ;
assign fetchStage$train_predictors_taken =
coreFix_trainBPQ_1$EMPTY_N ?
coreFix_trainBPQ_1$D_OUT[26] :
coreFix_trainBPQ_0$D_OUT[26] ;
assign fetchStage$EN_pipelines_0_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_0_canDeq ||
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_pipelines_1_deq =
WILL_FIRE_RL_renameStage_doRenaming_wrongPath &&
fetchStage$pipelines_1_canDeq &&
!epochManager$checkEpoch_1_check ||
WILL_FIRE_RL_renameStage_doRenaming &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 &&
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ;
assign fetchStage$EN_iTlbIfc_flush =
WILL_FIRE_RL_prepareCachesAndTlbs && flush_tlbs ||
WILL_FIRE_RL_rl_debug_resume ;
assign fetchStage$EN_iTlbIfc_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign fetchStage$EN_iTlbIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iTlbIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iTlbIfc_toParent_rqToP_deq = WILL_FIRE_RL_sendITlbReq ;
assign fetchStage$EN_iTlbIfc_toParent_rsFromP_enq =
CAN_FIRE_RL_sendRsToITlb ;
assign fetchStage$EN_iTlbIfc_toParent_flush_request_get =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign fetchStage$EN_iTlbIfc_toParent_flush_response_put =
CAN_FIRE_RL_sendFlushDone ;
assign fetchStage$EN_iTlbIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iTlbIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_request_put = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_proc_response_get = 1'b0 ;
assign fetchStage$EN_iMemIfc_flush = CAN_FIRE_RL_setDoFlushCaches ;
assign fetchStage$EN_iMemIfc_perf_setStatus = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_req = 1'b0 ;
assign fetchStage$EN_iMemIfc_perf_resp = 1'b0 ;
assign fetchStage$EN_iMemIfc_to_parent_rsToP_deq =
EN_iCacheToParent_rsToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_rqToP_deq =
EN_iCacheToParent_rqToP_deq ;
assign fetchStage$EN_iMemIfc_to_parent_fromP_enq =
EN_iCacheToParent_fromP_enq ;
assign fetchStage$EN_iMemIfc_cRqStuck_get = EN_deadlock_iCacheCRqStuck_get ;
assign fetchStage$EN_iMemIfc_pRqStuck_get = EN_deadlock_iCachePRqStuck_get ;
assign fetchStage$EN_mmioIfc_instReq_deq = WILL_FIRE_RL_mmio_sendInstReq ;
assign fetchStage$EN_mmioIfc_instResp_enq = CAN_FIRE_RL_mmio_sendInstResp ;
assign fetchStage$EN_mmioIfc_setHtifAddrs = EN_coreReq_start ;
assign fetchStage$EN_start = EN_coreReq_start ;
assign fetchStage$EN_stop = 1'b0 ;
assign fetchStage$EN_setWaitRedirect =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
!rob$deqPort_0_deq_data[12] ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ;
assign fetchStage$EN_redirect =
WILL_FIRE_RL_commitStage_doCommitTrap_handle &&
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_rl_debug_resume ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign fetchStage$EN_setWaitFlush =
MUX_commitStage_rg_run_state$write_1__SEL_1 ;
assign fetchStage$EN_done_flushing = CAN_FIRE_RL_readyToFetch ;
assign fetchStage$EN_train_predictors =
coreFix_trainBPQ_1$EMPTY_N ||
WILL_FIRE_RL_coreFix_doFetchTrainBP_1 ;
assign fetchStage$EN_flush_predictors = CAN_FIRE_RL_setDoFlushBrPred ;
assign fetchStage$EN_perf_setStatus = 1'b0 ;
assign fetchStage$EN_perf_req = 1'b0 ;
assign fetchStage$EN_perf_resp = 1'b0 ;
// submodule l2Tlb
assign l2Tlb$perf_req_r = 4'h0 ;
assign l2Tlb$perf_setStatus_doStats = 1'b0 ;
assign l2Tlb$toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq ?
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_1 :
MUX_l2Tlb$toChildren_rqFromC_put_1__VAL_2 ;
assign l2Tlb$toMem_respLd_enq_x = tlbToMem_respLd_enq_x ;
assign l2Tlb$updateVMInfo_vmD =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 :
MUX_coreFix_memExe_dTlb$updateVMInfo_1__VAL_1 ;
assign l2Tlb$updateVMInfo_vmI =
MUX_coreFix_memExe_dTlb$updateVMInfo_1__SEL_1 ?
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 :
MUX_fetchStage$iTlbIfc_updateVMInfo_1__VAL_1 ;
assign l2Tlb$EN_updateVMInfo =
WILL_FIRE_RL_prepareCachesAndTlbs && update_vm_info ||
WILL_FIRE_RL_rl_debug_resume ;
assign l2Tlb$EN_toChildren_rqFromC_put =
WILL_FIRE_RL_sendDTlbReq || WILL_FIRE_RL_sendITlbReq ;
assign l2Tlb$EN_toChildren_rsToC_deq =
WILL_FIRE_RL_sendRsToITlb || WILL_FIRE_RL_sendRsToDTlb ;
assign l2Tlb$EN_toChildren_iTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut_1 ;
assign l2Tlb$EN_toChildren_dTlbReqFlush_put =
CAN_FIRE_RL_mkConnectionGetPut ;
assign l2Tlb$EN_toChildren_flushDone_get = CAN_FIRE_RL_sendFlushDone ;
assign l2Tlb$EN_toMem_memReq_deq = EN_tlbToMem_memReq_deq ;
assign l2Tlb$EN_toMem_respLd_enq = EN_tlbToMem_respLd_enq ;
assign l2Tlb$EN_perf_setStatus = 1'b0 ;
assign l2Tlb$EN_perf_req = 1'b0 ;
assign l2Tlb$EN_perf_resp = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_0
assign mmio_cRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRqQ_clearReq_dummy2_1
assign mmio_cRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRqQ_deqReq_dummy2_0
assign mmio_cRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRq_deq ;
// submodule mmio_cRqQ_deqReq_dummy2_1
assign mmio_cRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_deqReq_dummy2_2
assign mmio_cRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRqQ_enqReq_dummy2_0
assign mmio_cRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_mmio_sendInstReq || WILL_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_cRqQ_enqReq_dummy2_1
assign mmio_cRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRqQ_enqReq_dummy2_2
assign mmio_cRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_clearReq_dummy2_0
assign mmio_cRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_cRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_cRsQ_clearReq_dummy2_1
assign mmio_cRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_cRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_cRsQ_deqReq_dummy2_0
assign mmio_cRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_0$EN = EN_mmioToPlatform_cRs_deq ;
// submodule mmio_cRsQ_deqReq_dummy2_1
assign mmio_cRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_deqReq_dummy2_2
assign mmio_cRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_cRsQ_enqReq_dummy2_0
assign mmio_cRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_cRsQ_enqReq_dummy2_1
assign mmio_cRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_cRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_cRsQ_enqReq_dummy2_2
assign mmio_cRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_cRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_clearReq_dummy2_0
assign mmio_dataPendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataPendQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataPendQ_clearReq_dummy2_1
assign mmio_dataPendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataPendQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataPendQ_deqReq_dummy2_0
assign mmio_dataPendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataPendQ_deqReq_dummy2_1
assign mmio_dataPendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_deqReq_dummy2_2
assign mmio_dataPendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataPendQ_enqReq_dummy2_0
assign mmio_dataPendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_0$EN =
mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataPendQ_enqReq_dummy2_1
assign mmio_dataPendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataPendQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataPendQ_enqReq_dummy2_2
assign mmio_dataPendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataPendQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_clearReq_dummy2_0
assign mmio_dataReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataReqQ_clearReq_dummy2_1
assign mmio_dataReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataReqQ_deqReq_dummy2_0
assign mmio_dataReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataReq ;
// submodule mmio_dataReqQ_deqReq_dummy2_1
assign mmio_dataReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_deqReq_dummy2_2
assign mmio_dataReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataReqQ_enqReq_dummy2_0
assign mmio_dataReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_0$EN = mmio_dataPendQ_enqReq_lat_0$whas ;
// submodule mmio_dataReqQ_enqReq_dummy2_1
assign mmio_dataReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataReqQ_enqReq_dummy2_2
assign mmio_dataReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_clearReq_dummy2_0
assign mmio_dataRespQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_dataRespQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_dataRespQ_clearReq_dummy2_1
assign mmio_dataRespQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_dataRespQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_dataRespQ_deqReq_dummy2_0
assign mmio_dataRespQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_0$EN =
mmio_dataRespQ_deqReq_lat_0$whas ;
// submodule mmio_dataRespQ_deqReq_dummy2_1
assign mmio_dataRespQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_deqReq_dummy2_2
assign mmio_dataRespQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_dataRespQ_enqReq_dummy2_0
assign mmio_dataRespQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_sendDataResp ;
// submodule mmio_dataRespQ_enqReq_dummy2_1
assign mmio_dataRespQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_dataRespQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_dataRespQ_enqReq_dummy2_2
assign mmio_dataRespQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_dataRespQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_clearReq_dummy2_0
assign mmio_pRqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRqQ_clearReq_dummy2_1
assign mmio_pRqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRqQ_deqReq_dummy2_0
assign mmio_pRqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_0$EN = CAN_FIRE_RL_mmio_handlePRq ;
// submodule mmio_pRqQ_deqReq_dummy2_1
assign mmio_pRqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_deqReq_dummy2_2
assign mmio_pRqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRqQ_enqReq_dummy2_0
assign mmio_pRqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRq_enq ;
// submodule mmio_pRqQ_enqReq_dummy2_1
assign mmio_pRqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRqQ_enqReq_dummy2_2
assign mmio_pRqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRqQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_clearReq_dummy2_0
assign mmio_pRsQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign mmio_pRsQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule mmio_pRsQ_clearReq_dummy2_1
assign mmio_pRsQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign mmio_pRsQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule mmio_pRsQ_deqReq_dummy2_0
assign mmio_pRsQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_0$EN = mmio_pRsQ_deqReq_lat_0$whas ;
// submodule mmio_pRsQ_deqReq_dummy2_1
assign mmio_pRsQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_deqReq_dummy2_2
assign mmio_pRsQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule mmio_pRsQ_enqReq_dummy2_0
assign mmio_pRsQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_0$EN = EN_mmioToPlatform_pRs_enq ;
// submodule mmio_pRsQ_enqReq_dummy2_1
assign mmio_pRsQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign mmio_pRsQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule mmio_pRsQ_enqReq_dummy2_2
assign mmio_pRsQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign mmio_pRsQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule perfReqQ
assign perfReqQ$D_IN = { coreReq_perfReq_loc, coreReq_perfReq_t } ;
assign perfReqQ$ENQ = EN_coreReq_perfReq ;
assign perfReqQ$DEQ = EN_coreIndInv_perfResp ;
assign perfReqQ$CLR = 1'b0 ;
// submodule regRenamingTable
assign regRenamingTable$rename_0_claimRename_r =
fetchStage$pipelines_0_first[95:69] ;
assign regRenamingTable$rename_0_claimRename_sb =
specTagManager$currentSpecBits ;
always@(MUX_regRenamingTable$rename_0_getRename_1__SEL_1 or
fetchStage$pipelines_0_first or
MUX_regRenamingTable$rename_0_getRename_1__SEL_2 or
MUX_regRenamingTable$rename_0_getRename_1__VAL_2 or
MUX_regRenamingTable$rename_0_getRename_1__SEL_3 or
MUX_regRenamingTable$rename_0_getRename_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_regRenamingTable$rename_0_getRename_1__SEL_1:
regRenamingTable$rename_0_getRename_r =
fetchStage$pipelines_0_first[95:69];
MUX_regRenamingTable$rename_0_getRename_1__SEL_2:
regRenamingTable$rename_0_getRename_r =
MUX_regRenamingTable$rename_0_getRename_1__VAL_2;
MUX_regRenamingTable$rename_0_getRename_1__SEL_3:
regRenamingTable$rename_0_getRename_r =
MUX_regRenamingTable$rename_0_getRename_1__VAL_3;
default: regRenamingTable$rename_0_getRename_r =
27'b010101010101010101010101010 /* unspecified value */ ;
endcase
end
assign regRenamingTable$rename_1_claimRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$rename_1_claimRename_sb =
renaming_spec_bits__h678574 ;
assign regRenamingTable$rename_1_getRename_r =
fetchStage$pipelines_1_first[95:69] ;
assign regRenamingTable$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign regRenamingTable$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: regRenamingTable$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign regRenamingTable$EN_rename_0_claimRename =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign regRenamingTable$EN_rename_1_claimRename =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign regRenamingTable$EN_commit_0_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign regRenamingTable$EN_commit_1_commit =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 ;
assign regRenamingTable$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign regRenamingTable$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule rf
assign rf$read_0_rd1_rindx = coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign rf$read_0_rd2_rindx = coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign rf$read_0_rd3_rindx = 7'h0 ;
assign rf$read_1_rd1_rindx = coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign rf$read_1_rd2_rindx = coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign rf$read_1_rd3_rindx = 7'h0 ;
assign rf$read_2_rd1_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign rf$read_2_rd2_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign rf$read_2_rd3_rindx =
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign rf$read_3_rd1_rindx = coreFix_memExe_dispToRegQ$first[61:55] ;
assign rf$read_3_rd2_rindx = coreFix_memExe_dispToRegQ$first[53:47] ;
assign rf$read_3_rd3_rindx = 7'h0 ;
assign rf$read_4_rd1_rindx = regRenamingTable$rename_0_getRename[31:25] ;
assign rf$read_4_rd2_rindx = 7'h0 ;
assign rf$read_4_rd3_rindx = 7'h0 ;
assign rf$write_0_wr_data = coreFix_aluExe_0_exeToFinQ$first[275:212] ;
assign rf$write_0_wr_rindx = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
assign rf$write_1_wr_data = coreFix_aluExe_1_exeToFinQ$first[275:212] ;
assign rf$write_1_wr_rindx = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
MUX_rf$write_2_wr_2__VAL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
MUX_rf$write_2_wr_2__VAL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
MUX_rf$write_2_wr_2__VAL_4 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
MUX_rf$write_2_wr_2__VAL_5 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
MUX_rf$write_2_wr_2__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_1;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_data =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[101:38];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_3;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_4;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_5;
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_data = MUX_rf$write_2_wr_2__VAL_6;
default: rf$write_2_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
rf$write_2_wr_rindx =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
default: rf$write_2_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_1 or
coreFix_memExe_respLrScAmoQ_data_0 or
MUX_rf$write_3_wr_1__SEL_2 or
mmio_dataRespQ_data_0 or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_2__VAL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
MUX_rf$write_3_wr_2__VAL_4 or
MUX_rf$write_3_wr_2__SEL_5 or coreFix_memExe_lsq$respLd)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_1:
rf$write_3_wr_data = coreFix_memExe_respLrScAmoQ_data_0;
MUX_rf$write_3_wr_1__SEL_2:
rf$write_3_wr_data = mmio_dataRespQ_data_0[63:0];
MUX_rf$write_3_wr_1__SEL_3:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_3;
MUX_rf$write_3_wr_1__SEL_4:
rf$write_3_wr_data = MUX_rf$write_3_wr_2__VAL_4;
MUX_rf$write_3_wr_2__SEL_5:
rf$write_3_wr_data = coreFix_memExe_lsq$respLd[63:0];
default: rf$write_3_wr_data =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_rf$write_3_wr_1__SEL_5 or
coreFix_memExe_lsq$respLd or
MUX_rf$write_3_wr_1__SEL_3 or
MUX_rf$write_3_wr_1__SEL_4 or
coreFix_memExe_lsq$firstLd or
MUX_rf$write_3_wr_1__SEL_1 or
MUX_rf$write_3_wr_1__SEL_2 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_rf$write_3_wr_1__SEL_5:
rf$write_3_wr_rindx = coreFix_memExe_lsq$respLd[71:65];
MUX_rf$write_3_wr_1__SEL_3 || MUX_rf$write_3_wr_1__SEL_4:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstLd[88:82];
MUX_rf$write_3_wr_1__SEL_1 || MUX_rf$write_3_wr_1__SEL_2:
rf$write_3_wr_rindx = coreFix_memExe_lsq$firstSt[149:143];
default: rf$write_3_wr_rindx = 7'b0101010 /* unspecified value */ ;
endcase
end
assign rf$write_4_wr_data =
WILL_FIRE_RL_rl_debug_gpr_write ?
f_gpr_reqs$D_OUT[63:0] :
f_fpr_reqs$D_OUT[63:0] ;
assign rf$write_4_wr_rindx = regRenamingTable$rename_0_getRename[31:25] ;
assign rf$EN_write_0_wr =
_dor1rf$EN_write_0_wr && coreFix_aluExe_0_exeToFinQ$first[321] ;
assign rf$EN_write_1_wr =
_dor1rf$EN_write_1_wr && coreFix_aluExe_1_exeToFinQ$first[321] ;
assign rf$EN_write_2_wr =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign rf$EN_write_3_wr =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq &&
coreFix_memExe_lsq$firstSt[150] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq &&
coreFix_memExe_lsq$firstLd[89] ||
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[72] ;
assign rf$EN_write_4_wr =
WILL_FIRE_RL_rl_debug_gpr_write ||
WILL_FIRE_RL_rl_debug_fpr_write ;
// submodule rob
always@(MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2 or
MUX_rob$enqPort_0_enq_1__VAL_1 or
WILL_FIRE_RL_renameStage_doRenaming_Trap or
MUX_rob$enqPort_0_enq_1__VAL_2 or
WILL_FIRE_RL_renameStage_doRenaming_SystemInst or
MUX_rob$enqPort_0_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_epochManager$updatePrevEpoch_0_update_1__SEL_2:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_1;
WILL_FIRE_RL_renameStage_doRenaming_Trap:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_2;
WILL_FIRE_RL_renameStage_doRenaming_SystemInst:
rob$enqPort_0_enq_x = MUX_rob$enqPort_0_enq_1__VAL_3;
default: rob$enqPort_0_enq_x =
283'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rob$enqPort_1_enq_x =
{ fetchStage$pipelines_1_first[387:324],
fetchStage$pipelines_1_first[127:96],
fetchStage$pipelines_1_first[199:195],
fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594,
73'h1280000000000000000,
fetchStage$pipelines_1_first[323:260],
5'd0,
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74],
fetchStage$pipelines_1_first[194:192] != 3'd0 &&
fetchStage$pipelines_1_first[194:192] != 3'd1 &&
fetchStage$pipelines_1_first[194:192] != 3'd2 &&
fetchStage$pipelines_1_first[194:192] != 3'd3 &&
fetchStage$pipelines_1_first[194:192] != 3'd4,
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211 ||
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174,
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221,
7'd32,
renaming_spec_bits__h678574 } ;
assign rob$getOrigPC_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrigPC_2_get_x = 12'h0 ;
assign rob$getOrigPredPC_0_get_x =
coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrigPredPC_1_get_x =
coreFix_aluExe_1_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_0_get_x = coreFix_aluExe_0_dispToRegQ$first[52:41] ;
assign rob$getOrig_Inst_1_get_x = coreFix_aluExe_1_dispToRegQ$first[52:41] ;
always@(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_2 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault or
MUX_rob$setExecuted_deqLSQ_2__VAL_6 or
MUX_rob$setExecuted_deqLSQ_1__SEL_1 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem or
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault or
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_2;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault:
rob$setExecuted_deqLSQ_cause = MUX_rob$setExecuted_deqLSQ_2__VAL_6;
MUX_rob$setExecuted_deqLSQ_1__SEL_1 ||
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem:
rob$setExecuted_deqLSQ_cause = 5'd10;
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd21;
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault:
rob$setExecuted_deqLSQ_cause = 5'd23;
default: rob$setExecuted_deqLSQ_cause =
5'b01010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_deqLSQ_ld_killed =
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ?
coreFix_memExe_lsq$firstLd[2:0] :
3'd2 ;
assign rob$setExecuted_deqLSQ_x =
(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__PSEL_2 ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault) ?
coreFix_memExe_lsq$firstLd[113:102] :
coreFix_memExe_lsq$firstSt[170:159] ;
assign rob$setExecuted_doFinishAlu_0_set_cf =
coreFix_aluExe_0_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_0_set_csrData =
coreFix_aluExe_0_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_0_set_x =
coreFix_aluExe_0_exeToFinQ$first[312:301] ;
assign rob$setExecuted_doFinishAlu_1_set_cf =
coreFix_aluExe_1_exeToFinQ$first[146:17] ;
assign rob$setExecuted_doFinishAlu_1_set_csrData =
coreFix_aluExe_1_exeToFinQ$first[211:147] ;
assign rob$setExecuted_doFinishAlu_1_set_x =
coreFix_aluExe_1_exeToFinQ$first[312:301] ;
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4 or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[37:33];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_2;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_3;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
MUX_rob$setExecuted_doFinishFpuMulDiv_0_set_2__VAL_4;
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_fflags = 5'd0;
default: rob$setExecuted_doFinishFpuMulDiv_0_set_fflags =
5'b01010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data or
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[23:12];
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv:
rob$setExecuted_doFinishFpuMulDiv_0_set_x =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[23:12];
default: rob$setExecuted_doFinishFpuMulDiv_0_set_x =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$setExecuted_doFinishMem_access_at_commit =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 &&
(coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd3 ||
coreFix_memExe_dTlb$procResp[105:103] == 3'd4) ;
assign rob$setExecuted_doFinishMem_non_mmio_st_done =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 &&
NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 &&
coreFix_memExe_dTlb$procResp[105:103] == 3'd1 ;
assign rob$setExecuted_doFinishMem_vaddr =
coreFix_memExe_dTlb$procResp[76:13] ;
assign rob$setExecuted_doFinishMem_x =
coreFix_memExe_dTlb$procResp[102:91] ;
assign rob$setLSQAtCommitNotified_x = rob$deqPort_0_getDeqInstTag ;
assign rob$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_1_exeToFinQ$first[312:301];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_inst_tag =
coreFix_aluExe_0_exeToFinQ$first[312:301];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_inst_tag =
12'b101010101010 /* unspecified value */ ;
endcase
end
assign rob$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
rob$specUpdate_incorrectSpeculation_spec_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
default: rob$specUpdate_incorrectSpeculation_spec_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign rob$EN_enqPort_0_enq =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ||
WILL_FIRE_RL_renameStage_doRenaming_Trap ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign rob$EN_enqPort_1_enq =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign rob$EN_deqPort_0_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign rob$EN_deqPort_1_deq =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 ;
assign rob$EN_setLSQAtCommitNotified =
CAN_FIRE_RL_commitStage_notifyLSQCommit ;
assign rob$EN_setExecuted_deqLSQ =
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_Fence ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Ld_Mem ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_fault ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_fault ;
assign rob$EN_setExecuted_doFinishAlu_0_set =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishAlu_1_set =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign rob$EN_setExecuted_doFinishFpuMulDiv_0_set =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv ;
assign rob$EN_setExecuted_doFinishMem =
CAN_FIRE_RL_coreFix_memExe_doFinishMem ;
assign rob$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign rob$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule sbAggr
assign sbAggr$eagerLookup_0_get_r = regRenamingTable$rename_0_getRename ;
assign sbAggr$eagerLookup_1_get_r = regRenamingTable$rename_1_getRename ;
assign sbAggr$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbAggr$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbAggr$setReady_0_put = coreFix_aluExe_0_rsAlu$dispatchData[40:34] ;
assign sbAggr$setReady_1_put = coreFix_aluExe_1_rsAlu$dispatchData[40:34] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbAggr$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
default: sbAggr$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$setReady_3_put = coreFix_memExe_lsq$issueLd[71:65] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4 or
coreFix_memExe_lsq$getHit or
MUX_sbAggr$setReady_4_put_1__SEL_2 or
coreFix_memExe_lsq$firstLd or
MUX_sbAggr$setReady_4_put_1__SEL_1 or coreFix_memExe_lsq$firstSt)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_3 ||
MUX_coreFix_aluExe_0_rsAlu$setRegReady_4_put_1__SEL_4:
sbAggr$setReady_4_put = coreFix_memExe_lsq$getHit[7:1];
MUX_sbAggr$setReady_4_put_1__SEL_2:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstLd[88:82];
MUX_sbAggr$setReady_4_put_1__SEL_1:
sbAggr$setReady_4_put = coreFix_memExe_lsq$firstSt[149:143];
default: sbAggr$setReady_4_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbAggr$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbAggr$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbAggr$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doDispatchAlu &&
coreFix_aluExe_0_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doDispatchAlu &&
coreFix_aluExe_1_rsAlu$dispatchData[41] ;
assign sbAggr$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign sbAggr$EN_setReady_3_put =
_dor1sbAggr$EN_setReady_3_put &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd0 &&
coreFix_memExe_lsq$issueLd[74:73] != 2'd1 &&
coreFix_memExe_lsq$issueLd[72] ;
assign sbAggr$EN_setReady_4_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_cRq &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 ||
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_pipelineResp_pRs &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
// submodule sbCons
assign sbCons$eagerLookup_0_get_r = 33'h0 ;
assign sbCons$eagerLookup_1_get_r = 33'h0 ;
assign sbCons$lazyLookup_0_get_r =
coreFix_aluExe_0_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_1_get_r =
coreFix_aluExe_1_dispToRegQ$first[85:53] ;
assign sbCons$lazyLookup_2_get_r =
coreFix_fpuMulDivExe_0_dispToRegQ$first[56:24] ;
assign sbCons$lazyLookup_3_get_r = coreFix_memExe_dispToRegQ$first[62:30] ;
assign sbCons$lazyLookup_4_get_r = 33'h0 ;
assign sbCons$setBusy_0_set_dst = regRenamingTable$rename_0_getRename[8:0] ;
assign sbCons$setBusy_1_set_dst = regRenamingTable$rename_1_getRename[8:0] ;
assign sbCons$setReady_0_put = coreFix_aluExe_0_exeToFinQ$first[320:314] ;
assign sbCons$setReady_1_put = coreFix_aluExe_1_exeToFinQ$first[320:314] ;
always@(MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1 or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2 or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3 or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4 or
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5 or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6 or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data)
begin
case (1'b1) // synopsys parallel_case
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_1:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_2:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_3:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_4:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_5:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[31:25];
MUX_coreFix_aluExe_0_rsAlu$setRegReady_2_put_1__SEL_6:
sbCons$setReady_2_put =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[31:25];
default: sbCons$setReady_2_put = 7'b0101010 /* unspecified value */ ;
endcase
end
always@(MUX_sbCons$setReady_3_put_1__SEL_1 or
coreFix_memExe_lsq$firstSt or
MUX_sbCons$setReady_3_put_1__SEL_2 or
coreFix_memExe_lsq$firstLd or
MUX_sbCons$setReady_3_put_1__SEL_3 or coreFix_memExe_lsq$respLd)
begin
case (1'b1) // synopsys parallel_case
MUX_sbCons$setReady_3_put_1__SEL_1:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstSt[149:143];
MUX_sbCons$setReady_3_put_1__SEL_2:
sbCons$setReady_3_put = coreFix_memExe_lsq$firstLd[88:82];
MUX_sbCons$setReady_3_put_1__SEL_3:
sbCons$setReady_3_put = coreFix_memExe_lsq$respLd[71:65];
default: sbCons$setReady_3_put = 7'b0101010 /* unspecified value */ ;
endcase
end
assign sbCons$setReady_4_put = 7'h0 ;
assign sbCons$EN_setBusy_0_set =
WILL_FIRE_RL_renameStage_doRenaming &&
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ||
WILL_FIRE_RL_renameStage_doRenaming_SystemInst ;
assign sbCons$EN_setBusy_1_set =
MUX_epochManager$updatePrevEpoch_1_update_1__SEL_2 ;
assign sbCons$EN_setReady_0_put =
_dor1sbCons$EN_setReady_0_put &&
coreFix_aluExe_0_exeToFinQ$first[321] ;
assign sbCons$EN_setReady_1_put =
_dor1sbCons$EN_setReady_1_put &&
coreFix_aluExe_1_exeToFinQ$first[321] ;
assign sbCons$EN_setReady_2_put =
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntDiv &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSimple &&
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$first[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpFma &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpDiv &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishFpSqrt &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[32] ||
WILL_FIRE_RL_coreFix_fpuMulDivExe_0_doFinishIntMul &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[32] ;
assign sbCons$EN_setReady_3_put =
(WILL_FIRE_RL_coreFix_memExe_doDeqStQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqStQ_ScAmo_deq) &&
coreFix_memExe_lsq$firstSt[150] ||
(WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_MMIO_deq ||
WILL_FIRE_RL_coreFix_memExe_doDeqLdQ_Lr_deq) &&
coreFix_memExe_lsq$firstLd[89] ||
(WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
WILL_FIRE_RL_coreFix_memExe_doRespLdMem) &&
coreFix_memExe_lsq$respLd[72] ;
assign sbCons$EN_setReady_4_put = 1'b0 ;
// submodule specTagManager
assign specTagManager$specUpdate_correctSpeculation_mask =
IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 ;
assign specTagManager$specUpdate_incorrectSpeculation_kill_all =
coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_kill_all ;
always@(WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T or
coreFix_aluExe_1_exeToFinQ$first or
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T or
coreFix_aluExe_0_exeToFinQ$first or
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_1_exeToFinQ$first[15:12];
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
coreFix_aluExe_0_exeToFinQ$first[15:12];
MUX_coreFix_aluExe_0_dispToRegQ$specUpdate_incorrectSpeculation_1__SEL_3:
specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
default: specTagManager$specUpdate_incorrectSpeculation_kill_tag =
4'b1010 /* unspecified value */ ;
endcase
end
assign specTagManager$EN_claimSpecTag =
WILL_FIRE_RL_renameStage_doRenaming &&
(fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198) ;
assign specTagManager$EN_specUpdate_incorrectSpeculation =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ||
WILL_FIRE_RL_commitStage_doCommitKilledLd ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ;
assign specTagManager$EN_specUpdate_correctSpeculation = 1'd1 ;
// submodule v_f_to_TV_0
assign v_f_to_TV_0$D_IN =
MUX_v_f_to_TV_0$enq_1__SEL_1 ?
MUX_v_f_to_TV_0$enq_1__VAL_1 :
MUX_v_f_to_TV_0$enq_1__VAL_1 ;
assign v_f_to_TV_0$ENQ =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq ||
WILL_FIRE_RL_commitStage_doCommitTrap_flush ||
WILL_FIRE_RL_commitStage_doCommitSystemInst ;
assign v_f_to_TV_0$DEQ = EN_v_to_TV_0_get ;
assign v_f_to_TV_0$CLR = 1'b0 ;
// submodule v_f_to_TV_1
assign v_f_to_TV_1$D_IN =
{ x__h712697,
rob$deqPort_1_deq_data[282:181],
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296,
6'd10,
rob$deqPort_1_deq_data[161:98],
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q297,
rob$deqPort_1_deq_data[95:26] } ;
assign v_f_to_TV_1$ENQ =
WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 ;
assign v_f_to_TV_1$DEQ = EN_v_to_TV_1_get ;
assign v_f_to_TV_1$CLR = 1'b0 ;
// remaining internal signals
module_amoExec instance_amoExec_2(.amoExec_amo_inst(coreFix_memExe_dMem_cache_m_banks_0_processAmo[10:4]),
.amoExec_current_data(curData__h190763),
.amoExec_in_data(coreFix_memExe_dMem_cache_m_banks_0_processAmo[74:11]),
.amoExec_upper_32_bits(coreFix_memExe_dMem_cache_m_banks_0_processAmo[90]),
.amoExec(n__h192301));
module_amoExec instance_amoExec_3(.amoExec_amo_inst({ mmio_pRqQ_data_0[35:32],
3'd0 }),
.amoExec_current_data({ 63'd0,
msip__h75907 }),
.amoExec_in_data({ 32'd0, x__h76022 }),
.amoExec_upper_32_bits(1'd0),
.amoExec(amoExec___d880));
module_basicExec instance_basicExec_6(.basicExec_dInst({ coreFix_aluExe_1_regToExeQ$first[421:417],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228,
{ coreFix_aluExe_1_regToExeQ$first[395],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229,
coreFix_aluExe_1_regToExeQ$first[382],
coreFix_aluExe_1_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_1_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_1_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_1_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_1_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_1_regToExeQ$first[48:17]),
.basicExec(basicExec___d11911));
module_basicExec instance_basicExec_5(.basicExec_dInst({ coreFix_aluExe_0_regToExeQ$first[421:417],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231,
{ coreFix_aluExe_0_regToExeQ$first[395],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232,
coreFix_aluExe_0_regToExeQ$first[382],
coreFix_aluExe_0_regToExeQ$first[381:350] } }),
.basicExec_rVal1(coreFix_aluExe_0_regToExeQ$first[304:241]),
.basicExec_rVal2(coreFix_aluExe_0_regToExeQ$first[240:177]),
.basicExec_pc(coreFix_aluExe_0_regToExeQ$first[176:113]),
.basicExec_ppc(coreFix_aluExe_0_regToExeQ$first[112:49]),
.basicExec_orig_inst(coreFix_aluExe_0_regToExeQ$first[48:17]),
.basicExec(basicExec___d12557));
module_checkForException instance_checkForException_0(.checkForException_dInst({ fetchStage$pipelines_0_first[199:195],
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826,
{ { fetchStage$pipelines_0_first[173],
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 },
fetchStage$pipelines_0_first[160],
x_data_imm__h671051 } }),
.checkForException_regs({ fetchStage$pipelines_0_first[95],
fetchStage$pipelines_0_first[94:89],
{ fetchStage$pipelines_0_first[88],
fetchStage$pipelines_0_first[87:82] },
{ fetchStage$pipelines_0_first[81],
fetchStage$pipelines_0_first[80:76],
fetchStage$pipelines_0_first[75],
fetchStage$pipelines_0_first[74:69] } }),
.checkForException_csrState({ x_decodeInfo_frm__h651589,
r1__read_BITS_13_TO_12___h651774 !=
2'd0,
{ prv__h715726,
csrf_tvm_reg,
{ r1__read_BIT_20___h652434,
csrf_tsr_reg,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d12942));
module_checkForException instance_checkForException_1(.checkForException_dInst({ fetchStage$pipelines_1_first[199:195],
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510,
{ fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594,
fetchStage$pipelines_1_first[160],
x_data_imm__h685982 } }),
.checkForException_regs({ fetchStage$pipelines_1_first[95],
fetchStage$pipelines_1_first[94:89],
{ fetchStage$pipelines_1_first[88],
fetchStage$pipelines_1_first[87:82] },
{ fetchStage$pipelines_1_first[81],
fetchStage$pipelines_1_first[80:76],
fetchStage$pipelines_1_first[75],
fetchStage$pipelines_1_first[74:69] } }),
.checkForException_csrState({ x_decodeInfo_frm__h651589,
r1__read_BITS_13_TO_12___h651774 !=
2'd0,
{ prv__h715726,
csrf_tvm_reg,
{ r1__read_BIT_20___h652434,
csrf_tsr_reg,
{ csrf_mcounteren_cy_reg,
csrf_mcounteren_cy_reg &&
csrf_scounteren_cy_reg,
{ csrf_mcounteren_ir_reg,
csrf_mcounteren_ir_reg &&
csrf_scounteren_ir_reg,
{ csrf_mcounteren_tm_reg,
csrf_mcounteren_tm_reg &&
csrf_scounteren_tm_reg } } } } } }),
.checkForException(checkForException___d13615));
module_execFpuSimple instance_execFpuSimple_4(.execFpuSimple_fpu_inst({ coreFix_fpuMulDivExe_0_regToExeQ$first[233:229],
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253,
coreFix_fpuMulDivExe_0_regToExeQ$first[225] }),
.execFpuSimple_rVal1(rVal1__h479605),
.execFpuSimple_rVal2(rVal2__h479606),
.execFpuSimple(execFpuSimple___d11053));
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 ?
_theResult___snd__h352103 :
_theResult____h343929 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 ?
_theResult___snd__h397800 :
_theResult____h389628 ;
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 ?
_theResult___snd__h443495 :
_theResult____h435323 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894 ?
_theResult___snd__h509012 :
_theResult____h500713 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609 ?
_theResult___snd__h587169 :
_theResult____h578870 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379 ?
_theResult___snd__h547865 :
_theResult____h539566 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 ?
_theResult___snd__h461261 :
_theResult____h452960 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 ?
_theResult___snd__h369869 :
_theResult____h361568 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 ?
_theResult___snd__h415566 :
_theResult____h407265 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582 ?
_theResult___snd__h499361 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944 ?
_theResult___snd__h499361 :
_theResult___snd__h517766 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312 ?
_theResult___snd__h577518 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659 ?
_theResult___snd__h577518 :
_theResult___snd__h595923 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082 ?
_theResult___snd__h538214 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181 =
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429 ?
_theResult___snd__h538214 :
_theResult___snd__h556619 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 ?
_theResult___snd__h452077 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 ?
_theResult___snd__h452077 :
_theResult___snd__h469867 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 ?
_theResult___snd__h360685 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 ?
_theResult___snd__h360685 :
_theResult___snd__h378475 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 ?
_theResult___snd__h406382 :
57'd0 ;
assign IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78 =
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 ?
_theResult___snd__h406382 :
_theResult___snd__h424172 ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
((_theResult___fst_exp__h352040 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050) :
((_theResult___fst_exp__h360696 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
((_theResult___fst_exp__h352040 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106) :
((_theResult___fst_exp__h360696 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
((_theResult___fst_exp__h397737 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442) :
((_theResult___fst_exp__h406393 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
((_theResult___fst_exp__h397737 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498) :
((_theResult___fst_exp__h406393 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
((_theResult___fst_exp__h443432 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834) :
((_theResult___fst_exp__h452088 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847) ;
assign IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
((_theResult___fst_exp__h443432 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890) :
((_theResult___fst_exp__h452088 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897) ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 =
(_theResult____h343929[56] ?
6'd0 :
(_theResult____h343929[55] ?
6'd1 :
(_theResult____h343929[54] ?
6'd2 :
(_theResult____h343929[53] ?
6'd3 :
(_theResult____h343929[52] ?
6'd4 :
(_theResult____h343929[51] ?
6'd5 :
(_theResult____h343929[50] ?
6'd6 :
(_theResult____h343929[49] ?
6'd7 :
(_theResult____h343929[48] ?
6'd8 :
(_theResult____h343929[47] ?
6'd9 :
(_theResult____h343929[46] ?
6'd10 :
(_theResult____h343929[45] ?
6'd11 :
(_theResult____h343929[44] ?
6'd12 :
(_theResult____h343929[43] ?
6'd13 :
(_theResult____h343929[42] ?
6'd14 :
(_theResult____h343929[41] ?
6'd15 :
(_theResult____h343929[40] ?
6'd16 :
(_theResult____h343929[39] ?
6'd17 :
(_theResult____h343929[38] ?
6'd18 :
(_theResult____h343929[37] ?
6'd19 :
(_theResult____h343929[36] ?
6'd20 :
(_theResult____h343929[35] ?
6'd21 :
(_theResult____h343929[34] ?
6'd22 :
(_theResult____h343929[33] ?
6'd23 :
(_theResult____h343929[32] ?
6'd24 :
(_theResult____h343929[31] ?
6'd25 :
(_theResult____h343929[30] ?
6'd26 :
(_theResult____h343929[29] ?
6'd27 :
(_theResult____h343929[28] ?
6'd28 :
(_theResult____h343929[27] ?
6'd29 :
(_theResult____h343929[26] ?
6'd30 :
(_theResult____h343929[25] ?
6'd31 :
(_theResult____h343929[24] ?
6'd32 :
(_theResult____h343929[23] ?
6'd33 :
(_theResult____h343929[22] ?
6'd34 :
(_theResult____h343929[21] ?
6'd35 :
(_theResult____h343929[20] ?
6'd36 :
(_theResult____h343929[19] ?
6'd37 :
(_theResult____h343929[18] ?
6'd38 :
(_theResult____h343929[17] ?
6'd39 :
(_theResult____h343929[16] ?
6'd40 :
(_theResult____h343929[15] ?
6'd41 :
(_theResult____h343929[14] ?
6'd42 :
(_theResult____h343929[13] ?
6'd43 :
(_theResult____h343929[12] ?
6'd44 :
(_theResult____h343929[11] ?
6'd45 :
(_theResult____h343929[10] ?
6'd46 :
(_theResult____h343929[9] ?
6'd47 :
(_theResult____h343929[8] ?
6'd48 :
(_theResult____h343929[7] ?
6'd49 :
(_theResult____h343929[6] ?
6'd50 :
(_theResult____h343929[5] ?
6'd51 :
(_theResult____h343929[4] ?
6'd52 :
(_theResult____h343929[3] ?
6'd53 :
(_theResult____h343929[2] ?
6'd54 :
(_theResult____h343929[1] ?
6'd55 :
(_theResult____h343929[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 =
(_theResult____h389628[56] ?
6'd0 :
(_theResult____h389628[55] ?
6'd1 :
(_theResult____h389628[54] ?
6'd2 :
(_theResult____h389628[53] ?
6'd3 :
(_theResult____h389628[52] ?
6'd4 :
(_theResult____h389628[51] ?
6'd5 :
(_theResult____h389628[50] ?
6'd6 :
(_theResult____h389628[49] ?
6'd7 :
(_theResult____h389628[48] ?
6'd8 :
(_theResult____h389628[47] ?
6'd9 :
(_theResult____h389628[46] ?
6'd10 :
(_theResult____h389628[45] ?
6'd11 :
(_theResult____h389628[44] ?
6'd12 :
(_theResult____h389628[43] ?
6'd13 :
(_theResult____h389628[42] ?
6'd14 :
(_theResult____h389628[41] ?
6'd15 :
(_theResult____h389628[40] ?
6'd16 :
(_theResult____h389628[39] ?
6'd17 :
(_theResult____h389628[38] ?
6'd18 :
(_theResult____h389628[37] ?
6'd19 :
(_theResult____h389628[36] ?
6'd20 :
(_theResult____h389628[35] ?
6'd21 :
(_theResult____h389628[34] ?
6'd22 :
(_theResult____h389628[33] ?
6'd23 :
(_theResult____h389628[32] ?
6'd24 :
(_theResult____h389628[31] ?
6'd25 :
(_theResult____h389628[30] ?
6'd26 :
(_theResult____h389628[29] ?
6'd27 :
(_theResult____h389628[28] ?
6'd28 :
(_theResult____h389628[27] ?
6'd29 :
(_theResult____h389628[26] ?
6'd30 :
(_theResult____h389628[25] ?
6'd31 :
(_theResult____h389628[24] ?
6'd32 :
(_theResult____h389628[23] ?
6'd33 :
(_theResult____h389628[22] ?
6'd34 :
(_theResult____h389628[21] ?
6'd35 :
(_theResult____h389628[20] ?
6'd36 :
(_theResult____h389628[19] ?
6'd37 :
(_theResult____h389628[18] ?
6'd38 :
(_theResult____h389628[17] ?
6'd39 :
(_theResult____h389628[16] ?
6'd40 :
(_theResult____h389628[15] ?
6'd41 :
(_theResult____h389628[14] ?
6'd42 :
(_theResult____h389628[13] ?
6'd43 :
(_theResult____h389628[12] ?
6'd44 :
(_theResult____h389628[11] ?
6'd45 :
(_theResult____h389628[10] ?
6'd46 :
(_theResult____h389628[9] ?
6'd47 :
(_theResult____h389628[8] ?
6'd48 :
(_theResult____h389628[7] ?
6'd49 :
(_theResult____h389628[6] ?
6'd50 :
(_theResult____h389628[5] ?
6'd51 :
(_theResult____h389628[4] ?
6'd52 :
(_theResult____h389628[3] ?
6'd53 :
(_theResult____h389628[2] ?
6'd54 :
(_theResult____h389628[1] ?
6'd55 :
(_theResult____h389628[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 =
(_theResult____h435323[56] ?
6'd0 :
(_theResult____h435323[55] ?
6'd1 :
(_theResult____h435323[54] ?
6'd2 :
(_theResult____h435323[53] ?
6'd3 :
(_theResult____h435323[52] ?
6'd4 :
(_theResult____h435323[51] ?
6'd5 :
(_theResult____h435323[50] ?
6'd6 :
(_theResult____h435323[49] ?
6'd7 :
(_theResult____h435323[48] ?
6'd8 :
(_theResult____h435323[47] ?
6'd9 :
(_theResult____h435323[46] ?
6'd10 :
(_theResult____h435323[45] ?
6'd11 :
(_theResult____h435323[44] ?
6'd12 :
(_theResult____h435323[43] ?
6'd13 :
(_theResult____h435323[42] ?
6'd14 :
(_theResult____h435323[41] ?
6'd15 :
(_theResult____h435323[40] ?
6'd16 :
(_theResult____h435323[39] ?
6'd17 :
(_theResult____h435323[38] ?
6'd18 :
(_theResult____h435323[37] ?
6'd19 :
(_theResult____h435323[36] ?
6'd20 :
(_theResult____h435323[35] ?
6'd21 :
(_theResult____h435323[34] ?
6'd22 :
(_theResult____h435323[33] ?
6'd23 :
(_theResult____h435323[32] ?
6'd24 :
(_theResult____h435323[31] ?
6'd25 :
(_theResult____h435323[30] ?
6'd26 :
(_theResult____h435323[29] ?
6'd27 :
(_theResult____h435323[28] ?
6'd28 :
(_theResult____h435323[27] ?
6'd29 :
(_theResult____h435323[26] ?
6'd30 :
(_theResult____h435323[25] ?
6'd31 :
(_theResult____h435323[24] ?
6'd32 :
(_theResult____h435323[23] ?
6'd33 :
(_theResult____h435323[22] ?
6'd34 :
(_theResult____h435323[21] ?
6'd35 :
(_theResult____h435323[20] ?
6'd36 :
(_theResult____h435323[19] ?
6'd37 :
(_theResult____h435323[18] ?
6'd38 :
(_theResult____h435323[17] ?
6'd39 :
(_theResult____h435323[16] ?
6'd40 :
(_theResult____h435323[15] ?
6'd41 :
(_theResult____h435323[14] ?
6'd42 :
(_theResult____h435323[13] ?
6'd43 :
(_theResult____h435323[12] ?
6'd44 :
(_theResult____h435323[11] ?
6'd45 :
(_theResult____h435323[10] ?
6'd46 :
(_theResult____h435323[9] ?
6'd47 :
(_theResult____h435323[8] ?
6'd48 :
(_theResult____h435323[7] ?
6'd49 :
(_theResult____h435323[6] ?
6'd50 :
(_theResult____h435323[5] ?
6'd51 :
(_theResult____h435323[4] ?
6'd52 :
(_theResult____h435323[3] ?
6'd53 :
(_theResult____h435323[2] ?
6'd54 :
(_theResult____h435323[1] ?
6'd55 :
(_theResult____h435323[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 =
(_theResult____h539566[56] ?
6'd0 :
(_theResult____h539566[55] ?
6'd1 :
(_theResult____h539566[54] ?
6'd2 :
(_theResult____h539566[53] ?
6'd3 :
(_theResult____h539566[52] ?
6'd4 :
(_theResult____h539566[51] ?
6'd5 :
(_theResult____h539566[50] ?
6'd6 :
(_theResult____h539566[49] ?
6'd7 :
(_theResult____h539566[48] ?
6'd8 :
(_theResult____h539566[47] ?
6'd9 :
(_theResult____h539566[46] ?
6'd10 :
(_theResult____h539566[45] ?
6'd11 :
(_theResult____h539566[44] ?
6'd12 :
(_theResult____h539566[43] ?
6'd13 :
(_theResult____h539566[42] ?
6'd14 :
(_theResult____h539566[41] ?
6'd15 :
(_theResult____h539566[40] ?
6'd16 :
(_theResult____h539566[39] ?
6'd17 :
(_theResult____h539566[38] ?
6'd18 :
(_theResult____h539566[37] ?
6'd19 :
(_theResult____h539566[36] ?
6'd20 :
(_theResult____h539566[35] ?
6'd21 :
(_theResult____h539566[34] ?
6'd22 :
(_theResult____h539566[33] ?
6'd23 :
(_theResult____h539566[32] ?
6'd24 :
(_theResult____h539566[31] ?
6'd25 :
(_theResult____h539566[30] ?
6'd26 :
(_theResult____h539566[29] ?
6'd27 :
(_theResult____h539566[28] ?
6'd28 :
(_theResult____h539566[27] ?
6'd29 :
(_theResult____h539566[26] ?
6'd30 :
(_theResult____h539566[25] ?
6'd31 :
(_theResult____h539566[24] ?
6'd32 :
(_theResult____h539566[23] ?
6'd33 :
(_theResult____h539566[22] ?
6'd34 :
(_theResult____h539566[21] ?
6'd35 :
(_theResult____h539566[20] ?
6'd36 :
(_theResult____h539566[19] ?
6'd37 :
(_theResult____h539566[18] ?
6'd38 :
(_theResult____h539566[17] ?
6'd39 :
(_theResult____h539566[16] ?
6'd40 :
(_theResult____h539566[15] ?
6'd41 :
(_theResult____h539566[14] ?
6'd42 :
(_theResult____h539566[13] ?
6'd43 :
(_theResult____h539566[12] ?
6'd44 :
(_theResult____h539566[11] ?
6'd45 :
(_theResult____h539566[10] ?
6'd46 :
(_theResult____h539566[9] ?
6'd47 :
(_theResult____h539566[8] ?
6'd48 :
(_theResult____h539566[7] ?
6'd49 :
(_theResult____h539566[6] ?
6'd50 :
(_theResult____h539566[5] ?
6'd51 :
(_theResult____h539566[4] ?
6'd52 :
(_theResult____h539566[3] ?
6'd53 :
(_theResult____h539566[2] ?
6'd54 :
(_theResult____h539566[1] ?
6'd55 :
(_theResult____h539566[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 =
(_theResult____h500713[56] ?
6'd0 :
(_theResult____h500713[55] ?
6'd1 :
(_theResult____h500713[54] ?
6'd2 :
(_theResult____h500713[53] ?
6'd3 :
(_theResult____h500713[52] ?
6'd4 :
(_theResult____h500713[51] ?
6'd5 :
(_theResult____h500713[50] ?
6'd6 :
(_theResult____h500713[49] ?
6'd7 :
(_theResult____h500713[48] ?
6'd8 :
(_theResult____h500713[47] ?
6'd9 :
(_theResult____h500713[46] ?
6'd10 :
(_theResult____h500713[45] ?
6'd11 :
(_theResult____h500713[44] ?
6'd12 :
(_theResult____h500713[43] ?
6'd13 :
(_theResult____h500713[42] ?
6'd14 :
(_theResult____h500713[41] ?
6'd15 :
(_theResult____h500713[40] ?
6'd16 :
(_theResult____h500713[39] ?
6'd17 :
(_theResult____h500713[38] ?
6'd18 :
(_theResult____h500713[37] ?
6'd19 :
(_theResult____h500713[36] ?
6'd20 :
(_theResult____h500713[35] ?
6'd21 :
(_theResult____h500713[34] ?
6'd22 :
(_theResult____h500713[33] ?
6'd23 :
(_theResult____h500713[32] ?
6'd24 :
(_theResult____h500713[31] ?
6'd25 :
(_theResult____h500713[30] ?
6'd26 :
(_theResult____h500713[29] ?
6'd27 :
(_theResult____h500713[28] ?
6'd28 :
(_theResult____h500713[27] ?
6'd29 :
(_theResult____h500713[26] ?
6'd30 :
(_theResult____h500713[25] ?
6'd31 :
(_theResult____h500713[24] ?
6'd32 :
(_theResult____h500713[23] ?
6'd33 :
(_theResult____h500713[22] ?
6'd34 :
(_theResult____h500713[21] ?
6'd35 :
(_theResult____h500713[20] ?
6'd36 :
(_theResult____h500713[19] ?
6'd37 :
(_theResult____h500713[18] ?
6'd38 :
(_theResult____h500713[17] ?
6'd39 :
(_theResult____h500713[16] ?
6'd40 :
(_theResult____h500713[15] ?
6'd41 :
(_theResult____h500713[14] ?
6'd42 :
(_theResult____h500713[13] ?
6'd43 :
(_theResult____h500713[12] ?
6'd44 :
(_theResult____h500713[11] ?
6'd45 :
(_theResult____h500713[10] ?
6'd46 :
(_theResult____h500713[9] ?
6'd47 :
(_theResult____h500713[8] ?
6'd48 :
(_theResult____h500713[7] ?
6'd49 :
(_theResult____h500713[6] ?
6'd50 :
(_theResult____h500713[5] ?
6'd51 :
(_theResult____h500713[4] ?
6'd52 :
(_theResult____h500713[3] ?
6'd53 :
(_theResult____h500713[2] ?
6'd54 :
(_theResult____h500713[1] ?
6'd55 :
(_theResult____h500713[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 =
(_theResult____h578870[56] ?
6'd0 :
(_theResult____h578870[55] ?
6'd1 :
(_theResult____h578870[54] ?
6'd2 :
(_theResult____h578870[53] ?
6'd3 :
(_theResult____h578870[52] ?
6'd4 :
(_theResult____h578870[51] ?
6'd5 :
(_theResult____h578870[50] ?
6'd6 :
(_theResult____h578870[49] ?
6'd7 :
(_theResult____h578870[48] ?
6'd8 :
(_theResult____h578870[47] ?
6'd9 :
(_theResult____h578870[46] ?
6'd10 :
(_theResult____h578870[45] ?
6'd11 :
(_theResult____h578870[44] ?
6'd12 :
(_theResult____h578870[43] ?
6'd13 :
(_theResult____h578870[42] ?
6'd14 :
(_theResult____h578870[41] ?
6'd15 :
(_theResult____h578870[40] ?
6'd16 :
(_theResult____h578870[39] ?
6'd17 :
(_theResult____h578870[38] ?
6'd18 :
(_theResult____h578870[37] ?
6'd19 :
(_theResult____h578870[36] ?
6'd20 :
(_theResult____h578870[35] ?
6'd21 :
(_theResult____h578870[34] ?
6'd22 :
(_theResult____h578870[33] ?
6'd23 :
(_theResult____h578870[32] ?
6'd24 :
(_theResult____h578870[31] ?
6'd25 :
(_theResult____h578870[30] ?
6'd26 :
(_theResult____h578870[29] ?
6'd27 :
(_theResult____h578870[28] ?
6'd28 :
(_theResult____h578870[27] ?
6'd29 :
(_theResult____h578870[26] ?
6'd30 :
(_theResult____h578870[25] ?
6'd31 :
(_theResult____h578870[24] ?
6'd32 :
(_theResult____h578870[23] ?
6'd33 :
(_theResult____h578870[22] ?
6'd34 :
(_theResult____h578870[21] ?
6'd35 :
(_theResult____h578870[20] ?
6'd36 :
(_theResult____h578870[19] ?
6'd37 :
(_theResult____h578870[18] ?
6'd38 :
(_theResult____h578870[17] ?
6'd39 :
(_theResult____h578870[16] ?
6'd40 :
(_theResult____h578870[15] ?
6'd41 :
(_theResult____h578870[14] ?
6'd42 :
(_theResult____h578870[13] ?
6'd43 :
(_theResult____h578870[12] ?
6'd44 :
(_theResult____h578870[11] ?
6'd45 :
(_theResult____h578870[10] ?
6'd46 :
(_theResult____h578870[9] ?
6'd47 :
(_theResult____h578870[8] ?
6'd48 :
(_theResult____h578870[7] ?
6'd49 :
(_theResult____h578870[6] ?
6'd50 :
(_theResult____h578870[5] ?
6'd51 :
(_theResult____h578870[4] ?
6'd52 :
(_theResult____h578870[3] ?
6'd53 :
(_theResult____h578870[2] ?
6'd54 :
(_theResult____h578870[1] ?
6'd55 :
(_theResult____h578870[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 =
(_theResult____h361568[56] ?
6'd0 :
(_theResult____h361568[55] ?
6'd1 :
(_theResult____h361568[54] ?
6'd2 :
(_theResult____h361568[53] ?
6'd3 :
(_theResult____h361568[52] ?
6'd4 :
(_theResult____h361568[51] ?
6'd5 :
(_theResult____h361568[50] ?
6'd6 :
(_theResult____h361568[49] ?
6'd7 :
(_theResult____h361568[48] ?
6'd8 :
(_theResult____h361568[47] ?
6'd9 :
(_theResult____h361568[46] ?
6'd10 :
(_theResult____h361568[45] ?
6'd11 :
(_theResult____h361568[44] ?
6'd12 :
(_theResult____h361568[43] ?
6'd13 :
(_theResult____h361568[42] ?
6'd14 :
(_theResult____h361568[41] ?
6'd15 :
(_theResult____h361568[40] ?
6'd16 :
(_theResult____h361568[39] ?
6'd17 :
(_theResult____h361568[38] ?
6'd18 :
(_theResult____h361568[37] ?
6'd19 :
(_theResult____h361568[36] ?
6'd20 :
(_theResult____h361568[35] ?
6'd21 :
(_theResult____h361568[34] ?
6'd22 :
(_theResult____h361568[33] ?
6'd23 :
(_theResult____h361568[32] ?
6'd24 :
(_theResult____h361568[31] ?
6'd25 :
(_theResult____h361568[30] ?
6'd26 :
(_theResult____h361568[29] ?
6'd27 :
(_theResult____h361568[28] ?
6'd28 :
(_theResult____h361568[27] ?
6'd29 :
(_theResult____h361568[26] ?
6'd30 :
(_theResult____h361568[25] ?
6'd31 :
(_theResult____h361568[24] ?
6'd32 :
(_theResult____h361568[23] ?
6'd33 :
(_theResult____h361568[22] ?
6'd34 :
(_theResult____h361568[21] ?
6'd35 :
(_theResult____h361568[20] ?
6'd36 :
(_theResult____h361568[19] ?
6'd37 :
(_theResult____h361568[18] ?
6'd38 :
(_theResult____h361568[17] ?
6'd39 :
(_theResult____h361568[16] ?
6'd40 :
(_theResult____h361568[15] ?
6'd41 :
(_theResult____h361568[14] ?
6'd42 :
(_theResult____h361568[13] ?
6'd43 :
(_theResult____h361568[12] ?
6'd44 :
(_theResult____h361568[11] ?
6'd45 :
(_theResult____h361568[10] ?
6'd46 :
(_theResult____h361568[9] ?
6'd47 :
(_theResult____h361568[8] ?
6'd48 :
(_theResult____h361568[7] ?
6'd49 :
(_theResult____h361568[6] ?
6'd50 :
(_theResult____h361568[5] ?
6'd51 :
(_theResult____h361568[4] ?
6'd52 :
(_theResult____h361568[3] ?
6'd53 :
(_theResult____h361568[2] ?
6'd54 :
(_theResult____h361568[1] ?
6'd55 :
(_theResult____h361568[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 =
(_theResult____h407265[56] ?
6'd0 :
(_theResult____h407265[55] ?
6'd1 :
(_theResult____h407265[54] ?
6'd2 :
(_theResult____h407265[53] ?
6'd3 :
(_theResult____h407265[52] ?
6'd4 :
(_theResult____h407265[51] ?
6'd5 :
(_theResult____h407265[50] ?
6'd6 :
(_theResult____h407265[49] ?
6'd7 :
(_theResult____h407265[48] ?
6'd8 :
(_theResult____h407265[47] ?
6'd9 :
(_theResult____h407265[46] ?
6'd10 :
(_theResult____h407265[45] ?
6'd11 :
(_theResult____h407265[44] ?
6'd12 :
(_theResult____h407265[43] ?
6'd13 :
(_theResult____h407265[42] ?
6'd14 :
(_theResult____h407265[41] ?
6'd15 :
(_theResult____h407265[40] ?
6'd16 :
(_theResult____h407265[39] ?
6'd17 :
(_theResult____h407265[38] ?
6'd18 :
(_theResult____h407265[37] ?
6'd19 :
(_theResult____h407265[36] ?
6'd20 :
(_theResult____h407265[35] ?
6'd21 :
(_theResult____h407265[34] ?
6'd22 :
(_theResult____h407265[33] ?
6'd23 :
(_theResult____h407265[32] ?
6'd24 :
(_theResult____h407265[31] ?
6'd25 :
(_theResult____h407265[30] ?
6'd26 :
(_theResult____h407265[29] ?
6'd27 :
(_theResult____h407265[28] ?
6'd28 :
(_theResult____h407265[27] ?
6'd29 :
(_theResult____h407265[26] ?
6'd30 :
(_theResult____h407265[25] ?
6'd31 :
(_theResult____h407265[24] ?
6'd32 :
(_theResult____h407265[23] ?
6'd33 :
(_theResult____h407265[22] ?
6'd34 :
(_theResult____h407265[21] ?
6'd35 :
(_theResult____h407265[20] ?
6'd36 :
(_theResult____h407265[19] ?
6'd37 :
(_theResult____h407265[18] ?
6'd38 :
(_theResult____h407265[17] ?
6'd39 :
(_theResult____h407265[16] ?
6'd40 :
(_theResult____h407265[15] ?
6'd41 :
(_theResult____h407265[14] ?
6'd42 :
(_theResult____h407265[13] ?
6'd43 :
(_theResult____h407265[12] ?
6'd44 :
(_theResult____h407265[11] ?
6'd45 :
(_theResult____h407265[10] ?
6'd46 :
(_theResult____h407265[9] ?
6'd47 :
(_theResult____h407265[8] ?
6'd48 :
(_theResult____h407265[7] ?
6'd49 :
(_theResult____h407265[6] ?
6'd50 :
(_theResult____h407265[5] ?
6'd51 :
(_theResult____h407265[4] ?
6'd52 :
(_theResult____h407265[3] ?
6'd53 :
(_theResult____h407265[2] ?
6'd54 :
(_theResult____h407265[1] ?
6'd55 :
(_theResult____h407265[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 =
(_theResult____h452960[56] ?
6'd0 :
(_theResult____h452960[55] ?
6'd1 :
(_theResult____h452960[54] ?
6'd2 :
(_theResult____h452960[53] ?
6'd3 :
(_theResult____h452960[52] ?
6'd4 :
(_theResult____h452960[51] ?
6'd5 :
(_theResult____h452960[50] ?
6'd6 :
(_theResult____h452960[49] ?
6'd7 :
(_theResult____h452960[48] ?
6'd8 :
(_theResult____h452960[47] ?
6'd9 :
(_theResult____h452960[46] ?
6'd10 :
(_theResult____h452960[45] ?
6'd11 :
(_theResult____h452960[44] ?
6'd12 :
(_theResult____h452960[43] ?
6'd13 :
(_theResult____h452960[42] ?
6'd14 :
(_theResult____h452960[41] ?
6'd15 :
(_theResult____h452960[40] ?
6'd16 :
(_theResult____h452960[39] ?
6'd17 :
(_theResult____h452960[38] ?
6'd18 :
(_theResult____h452960[37] ?
6'd19 :
(_theResult____h452960[36] ?
6'd20 :
(_theResult____h452960[35] ?
6'd21 :
(_theResult____h452960[34] ?
6'd22 :
(_theResult____h452960[33] ?
6'd23 :
(_theResult____h452960[32] ?
6'd24 :
(_theResult____h452960[31] ?
6'd25 :
(_theResult____h452960[30] ?
6'd26 :
(_theResult____h452960[29] ?
6'd27 :
(_theResult____h452960[28] ?
6'd28 :
(_theResult____h452960[27] ?
6'd29 :
(_theResult____h452960[26] ?
6'd30 :
(_theResult____h452960[25] ?
6'd31 :
(_theResult____h452960[24] ?
6'd32 :
(_theResult____h452960[23] ?
6'd33 :
(_theResult____h452960[22] ?
6'd34 :
(_theResult____h452960[21] ?
6'd35 :
(_theResult____h452960[20] ?
6'd36 :
(_theResult____h452960[19] ?
6'd37 :
(_theResult____h452960[18] ?
6'd38 :
(_theResult____h452960[17] ?
6'd39 :
(_theResult____h452960[16] ?
6'd40 :
(_theResult____h452960[15] ?
6'd41 :
(_theResult____h452960[14] ?
6'd42 :
(_theResult____h452960[13] ?
6'd43 :
(_theResult____h452960[12] ?
6'd44 :
(_theResult____h452960[11] ?
6'd45 :
(_theResult____h452960[10] ?
6'd46 :
(_theResult____h452960[9] ?
6'd47 :
(_theResult____h452960[8] ?
6'd48 :
(_theResult____h452960[7] ?
6'd49 :
(_theResult____h452960[6] ?
6'd50 :
(_theResult____h452960[5] ?
6'd51 :
(_theResult____h452960[4] ?
6'd52 :
(_theResult____h452960[3] ?
6'd53 :
(_theResult____h452960[2] ?
6'd54 :
(_theResult____h452960[1] ?
6'd55 :
(_theResult____h452960[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10421 =
(_theResult___fst_exp__h547802 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10688 =
(_theResult___fst_exp__h547802 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8936 =
(_theResult___fst_exp__h508949 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9651 =
(_theResult___fst_exp__h587106 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163) ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9919 =
(_theResult___fst_exp__h587106 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 =
(guard__h343939 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h352040 :
_theResult___exp__h352556 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 =
(guard__h343939 == 2'b0) ?
_theResult___fst_exp__h352040 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h352556 :
_theResult___fst_exp__h352040) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 =
(guard__h343939 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h352034[56:34] :
_theResult___sfd__h352557 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 =
(guard__h343939 == 2'b0) ?
sfdin__h352034[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h352557 :
sfdin__h352034[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 =
(guard__h389638 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h397737 :
_theResult___exp__h398253 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 =
(guard__h389638 == 2'b0) ?
_theResult___fst_exp__h397737 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h398253 :
_theResult___fst_exp__h397737) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 =
(guard__h389638 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h397731[56:34] :
_theResult___sfd__h398254 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 =
(guard__h389638 == 2'b0) ?
sfdin__h397731[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h398254 :
sfdin__h397731[56:34]) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 =
(guard__h435333 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h443432 :
_theResult___exp__h443948 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 =
(guard__h435333 == 2'b0) ?
_theResult___fst_exp__h443432 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h443948 :
_theResult___fst_exp__h443432) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 =
(guard__h435333 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h443426[56:34] :
_theResult___sfd__h443949 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 =
(guard__h435333 == 2'b0) ?
sfdin__h443426[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h443949 :
sfdin__h443426[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533 =
(guard__h539576 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h547802 :
_theResult___exp__h548531 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535 =
(guard__h539576 == 2'b0) ?
_theResult___fst_exp__h547802 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h548531 :
_theResult___fst_exp__h547802) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616 =
(guard__h539576 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
sfdin__h547796[56:5] :
_theResult___sfd__h548532 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618 =
(guard__h539576 == 2'b0) ?
sfdin__h547796[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h548532 :
sfdin__h547796[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053 =
(guard__h500723 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h508949 :
_theResult___exp__h509678 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055 =
(guard__h500723 == 2'b0) ?
_theResult___fst_exp__h508949 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h509678 :
_theResult___fst_exp__h508949) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137 =
(guard__h500723 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
sfdin__h508943[56:5] :
_theResult___sfd__h509679 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139 =
(guard__h500723 == 2'b0) ?
sfdin__h508943[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h509679 :
sfdin__h508943[56:5]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 =
(guard__h578880 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h587106 :
_theResult___exp__h587835 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 =
(guard__h578880 == 2'b0) ?
_theResult___fst_exp__h587106 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h587835 :
_theResult___fst_exp__h587106) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846 =
(guard__h578880 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
sfdin__h587100[56:5] :
_theResult___sfd__h587836 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848 =
(guard__h578880 == 2'b0) ?
sfdin__h587100[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h587836 :
sfdin__h587100[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 =
(guard__h361578 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h369806 :
_theResult___exp__h370322 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 =
(guard__h361578 == 2'b0) ?
_theResult___fst_exp__h369806 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h370322 :
_theResult___fst_exp__h369806) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 =
(guard__h361578 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
sfdin__h369800[56:34] :
_theResult___sfd__h370323 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 =
(guard__h361578 == 2'b0) ?
sfdin__h369800[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h370323 :
sfdin__h369800[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 =
(guard__h407275 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h415503 :
_theResult___exp__h416019 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 =
(guard__h407275 == 2'b0) ?
_theResult___fst_exp__h415503 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h416019 :
_theResult___fst_exp__h415503) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 =
(guard__h407275 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
sfdin__h415497[56:34] :
_theResult___sfd__h416020 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 =
(guard__h407275 == 2'b0) ?
sfdin__h415497[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h416020 :
sfdin__h415497[56:34]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 =
(guard__h452970 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h461198 :
_theResult___exp__h461714 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 =
(guard__h452970 == 2'b0) ?
_theResult___fst_exp__h461198 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h461714 :
_theResult___fst_exp__h461198) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 =
(guard__h452970 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
sfdin__h461192[56:34] :
_theResult___sfd__h461715 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 =
(guard__h452970 == 2'b0) ?
sfdin__h461192[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h461715 :
sfdin__h461192[56:34]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495 =
(guard__h530264 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h538225 :
_theResult___exp__h538880 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497 =
(guard__h530264 == 2'b0) ?
_theResult___fst_exp__h538225 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h538880 :
_theResult___fst_exp__h538225) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564 =
(guard__h548645 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___fst_exp__h556635 :
_theResult___exp__h557315 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566 =
(guard__h548645 == 2'b0) ?
_theResult___fst_exp__h556635 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___exp__h557315 :
_theResult___fst_exp__h556635) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590 =
(guard__h530264 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h538176[56:5] :
_theResult___sfd__h538881 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592 =
(guard__h530264 == 2'b0) ?
_theResult___snd__h538176[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h538881 :
_theResult___snd__h538176[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635 =
(guard__h548645 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___snd__h556581[56:5] :
_theResult___sfd__h557316 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637 =
(guard__h548645 == 2'b0) ?
_theResult___snd__h556581[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
_theResult___sfd__h557316 :
_theResult___snd__h556581[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010 =
(guard__h491411 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h499372 :
_theResult___exp__h500027 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012 =
(guard__h491411 == 2'b0) ?
_theResult___fst_exp__h499372 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h500027 :
_theResult___fst_exp__h499372) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084 =
(guard__h509792 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___fst_exp__h517782 :
_theResult___exp__h518462 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086 =
(guard__h509792 == 2'b0) ?
_theResult___fst_exp__h517782 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___exp__h518462 :
_theResult___fst_exp__h517782) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110 =
(guard__h491411 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h499323[56:5] :
_theResult___sfd__h500028 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112 =
(guard__h491411 == 2'b0) ?
_theResult___snd__h499323[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h500028 :
_theResult___snd__h499323[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156 =
(guard__h509792 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___snd__h517728[56:5] :
_theResult___sfd__h518463 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158 =
(guard__h509792 == 2'b0) ?
_theResult___snd__h517728[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
_theResult___sfd__h518463 :
_theResult___snd__h517728[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725 =
(guard__h569568 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h577529 :
_theResult___exp__h578184 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727 =
(guard__h569568 == 2'b0) ?
_theResult___fst_exp__h577529 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h578184 :
_theResult___fst_exp__h577529) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794 =
(guard__h587949 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___fst_exp__h595939 :
_theResult___exp__h596619 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796 =
(guard__h587949 == 2'b0) ?
_theResult___fst_exp__h595939 :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___exp__h596619 :
_theResult___fst_exp__h595939) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820 =
(guard__h569568 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h577480[56:5] :
_theResult___sfd__h578185 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822 =
(guard__h569568 == 2'b0) ?
_theResult___snd__h577480[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h578185 :
_theResult___snd__h577480[56:5]) ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865 =
(guard__h587949 == 2'b0 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___snd__h595885[56:5] :
_theResult___sfd__h596620 ;
assign IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867 =
(guard__h587949 == 2'b0) ?
_theResult___snd__h595885[56:5] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
_theResult___sfd__h596620 :
_theResult___snd__h595885[56:5]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 =
(guard__h352648 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h360696 :
_theResult___exp__h361138 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 =
(guard__h352648 == 2'b0) ?
_theResult___fst_exp__h360696 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h361138 :
_theResult___fst_exp__h360696) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 =
(guard__h370414 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___fst_exp__h378491 :
_theResult___exp__h378958 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 =
(guard__h370414 == 2'b0) ?
_theResult___fst_exp__h378491 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___exp__h378958 :
_theResult___fst_exp__h378491) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 =
(guard__h352648 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h360647[56:34] :
_theResult___sfd__h361139 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 =
(guard__h352648 == 2'b0) ?
_theResult___snd__h360647[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h361139 :
_theResult___snd__h360647[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 =
(guard__h370414 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68]) ?
_theResult___snd__h378437[56:34] :
_theResult___sfd__h378959 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 =
(guard__h370414 == 2'b0) ?
_theResult___snd__h378437[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
_theResult___sfd__h378959 :
_theResult___snd__h378437[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 =
(guard__h398345 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h406393 :
_theResult___exp__h406835 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 =
(guard__h398345 == 2'b0) ?
_theResult___fst_exp__h406393 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h406835 :
_theResult___fst_exp__h406393) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 =
(guard__h416111 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___fst_exp__h424188 :
_theResult___exp__h424655 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 =
(guard__h416111 == 2'b0) ?
_theResult___fst_exp__h424188 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___exp__h424655 :
_theResult___fst_exp__h424188) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 =
(guard__h398345 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h406344[56:34] :
_theResult___sfd__h406836 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 =
(guard__h398345 == 2'b0) ?
_theResult___snd__h406344[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h406836 :
_theResult___snd__h406344[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 =
(guard__h416111 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68]) ?
_theResult___snd__h424134[56:34] :
_theResult___sfd__h424656 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 =
(guard__h416111 == 2'b0) ?
_theResult___snd__h424134[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
_theResult___sfd__h424656 :
_theResult___snd__h424134[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 =
(guard__h444040 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h452088 :
_theResult___exp__h452530 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 =
(guard__h444040 == 2'b0) ?
_theResult___fst_exp__h452088 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h452530 :
_theResult___fst_exp__h452088) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 =
(guard__h461806 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___fst_exp__h469883 :
_theResult___exp__h470350 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 =
(guard__h461806 == 2'b0) ?
_theResult___fst_exp__h469883 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___exp__h470350 :
_theResult___fst_exp__h469883) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 =
(guard__h444040 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h452039[56:34] :
_theResult___sfd__h452531 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 =
(guard__h444040 == 2'b0) ?
_theResult___snd__h452039[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h452531 :
_theResult___snd__h452039[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 =
(guard__h461806 == 2'b0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68]) ?
_theResult___snd__h469829[56:34] :
_theResult___sfd__h470351 ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 =
(guard__h461806 == 2'b0) ?
_theResult___snd__h469829[56:34] :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
_theResult___sfd__h470351 :
_theResult___snd__h469829[56:34]) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467 =
(_theResult___fst_exp__h556635 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10673 =
(_theResult___fst_exp__h538225 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10700 =
(_theResult___fst_exp__h556635 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8982 =
(_theResult___fst_exp__h517782 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9697 =
(_theResult___fst_exp__h595939 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9904 =
(_theResult___fst_exp__h577529 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173) ;
assign IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9931 =
(_theResult___fst_exp__h595939 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171) ;
assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767 =
(_theResult____h647726 == 16'd0 &&
(csrf_prv_reg == 2'd0 ||
csrf_prv_reg == 2'd1 && csrf_ie_vec_1)) ?
enabled_ints__h648298 :
_theResult____h647726 ;
assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984 =
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] ||
checkForException___d12942[4] ||
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977 ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673 =
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] ||
checkForException___d12942[4] ||
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 ;
assign IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710 =
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] ||
checkForException___d13615[4] ||
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 =
((f2_exp__h518978 == 8'd0) ?
(f2_sfd__h518979[22] ?
6'd2 :
(f2_sfd__h518979[21] ?
6'd3 :
(f2_sfd__h518979[20] ?
6'd4 :
(f2_sfd__h518979[19] ?
6'd5 :
(f2_sfd__h518979[18] ?
6'd6 :
(f2_sfd__h518979[17] ?
6'd7 :
(f2_sfd__h518979[16] ?
6'd8 :
(f2_sfd__h518979[15] ?
6'd9 :
(f2_sfd__h518979[14] ?
6'd10 :
(f2_sfd__h518979[13] ?
6'd11 :
(f2_sfd__h518979[12] ?
6'd12 :
(f2_sfd__h518979[11] ?
6'd13 :
(f2_sfd__h518979[10] ?
6'd14 :
(f2_sfd__h518979[9] ?
6'd15 :
(f2_sfd__h518979[8] ?
6'd16 :
(f2_sfd__h518979[7] ?
6'd17 :
(f2_sfd__h518979[6] ?
6'd18 :
(f2_sfd__h518979[5] ?
6'd19 :
(f2_sfd__h518979[4] ?
6'd20 :
(f2_sfd__h518979[3] ?
6'd21 :
(f2_sfd__h518979[2] ?
6'd22 :
(f2_sfd__h518979[1] ?
6'd23 :
(f2_sfd__h518979[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10471 =
(f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0 ||
(f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) &&
f2_sfd__h518979 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((f2_exp__h518978 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10469) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648 =
(f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0) ?
_theResult___snd_fst_sfd__h519294 :
_theResult___fst_sfd__h557434 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649 =
{ (f2_exp__h518978 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h557430,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10648 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703 =
(f2_exp__h518978 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10673) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10675) :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10702 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704 =
(f2_exp__h518978 == 8'd255 && f2_sfd__h518979 != 23'd0 ||
(f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) &&
f2_sfd__h518979 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10703 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10759 =
(f1_exp__h479984 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10800 =
(f2_exp__h518978 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10844 =
(f3_exp__h558282 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[4] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[4] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10859 =
(f1_exp__h479984 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10869 =
(f2_exp__h518978 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10880 =
(f3_exp__h558282 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 &&
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[3] :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 &&
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[3] ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10899 =
(f1_exp__h479984 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10913 =
(f2_exp__h518978 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10911 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10928 =
(f3_exp__h558282 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[2] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10926 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10945 =
(f1_exp__h479984 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10943 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10957 =
(f2_exp__h518978 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10955 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10970 =
(f3_exp__h558282 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 &&
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ||
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[1]) :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 &&
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10968 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 =
(f1_exp__h479984 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10985 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10999 =
(f2_exp__h518978 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10997 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11012 =
(f3_exp__h558282 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ||
!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 &&
_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823[0] :
!SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ||
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11010 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 =
((f1_exp__h479984 == 8'd0) ?
(f1_sfd__h479985[22] ?
6'd2 :
(f1_sfd__h479985[21] ?
6'd3 :
(f1_sfd__h479985[20] ?
6'd4 :
(f1_sfd__h479985[19] ?
6'd5 :
(f1_sfd__h479985[18] ?
6'd6 :
(f1_sfd__h479985[17] ?
6'd7 :
(f1_sfd__h479985[16] ?
6'd8 :
(f1_sfd__h479985[15] ?
6'd9 :
(f1_sfd__h479985[14] ?
6'd10 :
(f1_sfd__h479985[13] ?
6'd11 :
(f1_sfd__h479985[12] ?
6'd12 :
(f1_sfd__h479985[11] ?
6'd13 :
(f1_sfd__h479985[10] ?
6'd14 :
(f1_sfd__h479985[9] ?
6'd15 :
(f1_sfd__h479985[8] ?
6'd16 :
(f1_sfd__h479985[7] ?
6'd17 :
(f1_sfd__h479985[6] ?
6'd18 :
(f1_sfd__h479985[5] ?
6'd19 :
(f1_sfd__h479985[4] ?
6'd20 :
(f1_sfd__h479985[3] ?
6'd21 :
(f1_sfd__h479985[2] ?
6'd22 :
(f1_sfd__h479985[1] ?
6'd23 :
(f1_sfd__h479985[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8986 =
(f1_exp__h479984 == 8'd255 && f1_sfd__h479985 != 23'd0 ||
(f1_exp__h479984 == 8'd255 || f1_exp__h479984 == 8'd0) &&
f1_sfd__h479985 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((f1_exp__h479984 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8984) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169 =
(f1_exp__h479984 == 8'd255 && f1_sfd__h479985 != 23'd0) ?
_theResult___snd_fst_sfd__h480300 :
_theResult___fst_sfd__h518581 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9170 =
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8986,
(f1_exp__h479984 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h518577,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9169 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 =
((f3_exp__h558282 == 8'd0) ?
(f3_sfd__h558283[22] ?
6'd2 :
(f3_sfd__h558283[21] ?
6'd3 :
(f3_sfd__h558283[20] ?
6'd4 :
(f3_sfd__h558283[19] ?
6'd5 :
(f3_sfd__h558283[18] ?
6'd6 :
(f3_sfd__h558283[17] ?
6'd7 :
(f3_sfd__h558283[16] ?
6'd8 :
(f3_sfd__h558283[15] ?
6'd9 :
(f3_sfd__h558283[14] ?
6'd10 :
(f3_sfd__h558283[13] ?
6'd11 :
(f3_sfd__h558283[12] ?
6'd12 :
(f3_sfd__h558283[11] ?
6'd13 :
(f3_sfd__h558283[10] ?
6'd14 :
(f3_sfd__h558283[9] ?
6'd15 :
(f3_sfd__h558283[8] ?
6'd16 :
(f3_sfd__h558283[7] ?
6'd17 :
(f3_sfd__h558283[6] ?
6'd18 :
(f3_sfd__h558283[5] ?
6'd19 :
(f3_sfd__h558283[4] ?
6'd20 :
(f3_sfd__h558283[3] ?
6'd21 :
(f3_sfd__h558283[2] ?
6'd22 :
(f3_sfd__h558283[1] ?
6'd23 :
(f3_sfd__h558283[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9701 =
(f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0 ||
(f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) &&
f3_sfd__h558283 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((f3_exp__h558282 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356 :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9699) ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878 =
(f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0) ?
_theResult___snd_fst_sfd__h558598 :
_theResult___fst_sfd__h596738 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879 =
{ (f3_exp__h558282 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h596734,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9878 } ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9934 =
(f3_exp__h558282 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9904) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9906) :
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9933 ;
assign IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9935 =
(f3_exp__h558282 == 8'd255 && f3_sfd__h558283 != 23'd0 ||
(f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) &&
f3_sfd__h558283 == 23'd0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9934 ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 ?
4'd11 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 ?
4'd12 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844 ?
4'd13 :
4'd15)) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 ?
4'd8 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 ?
4'd9 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1847) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 ?
4'd6 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 ?
4'd7 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1849) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 ?
4'd4 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 ?
4'd5 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1851) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 ?
4'd2 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 ?
4'd3 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1853) ;
assign IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1857 =
IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 ?
4'd0 :
(IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 ?
4'd1 :
IF_IF_coreFix_memExe_dTlb_procResp__712_BIT_11_ETC___d1855) ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd12 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd12) ?
4'd13 :
4'd15 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd11 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd11) ?
4'd12 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13130 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd10 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd10) ?
4'd11 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13131 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd9 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd9) ?
4'd9 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13132 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd8 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd8) ?
4'd8 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13133 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd7 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd7) ?
4'd7 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13134 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd6 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd6) ?
4'd6 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13135 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd5 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd5) ?
4'd5 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13136 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd4 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd4) ?
4'd4 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13137 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd3 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd3) ?
4'd3 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13138 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd2 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd2) ?
4'd2 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13139 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd1 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd1) ?
4'd1 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13140 ;
assign IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142 =
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 ==
4'd0 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 ==
4'd0) ?
4'd0 :
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13141 ;
assign IF_IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmi_ETC___d463 =
{ (mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_cRqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[75:72] :
mmio_cRqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN__ETC___d172 =
{ (mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd1 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd1) ?
2'd1 :
((mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[77:76] == 2'd2 :
mmio_dataReqQ_enqReq_rl[77:76] == 2'd2) ?
2'd2 :
2'd3),
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[75:72] :
mmio_dataReqQ_enqReq_rl[75:72] } ;
assign IF_IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmi_ETC___d766 =
{ (EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd1 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd1) ?
2'd1 :
((EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[37:36] == 2'd2 :
mmio_pRqQ_enqReq_rl[37:36] == 2'd2) ?
2'd2 :
2'd3),
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[35:32] :
mmio_pRqQ_enqReq_rl[35:32] } ;
assign IF_IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_NOT_ETC___d627 =
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[66] :
!mmio_pRsQ_enqReq_rl[66]) ?
{ EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[65] :
mmio_pRsQ_enqReq_rl[65],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:33] :
mmio_pRsQ_enqReq_rl[64:33],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[32] :
mmio_pRsQ_enqReq_rl[32],
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[31:0] :
mmio_pRsQ_enqReq_rl[31:0] } :
{ 1'h0,
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[64:0] :
mmio_pRsQ_enqReq_rl[64:0] } ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d10126 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ||
_theResult___fst_exp__h538225 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d8641 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ||
_theResult___fst_exp__h499372 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146) ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMu_ETC___d9356 =
(!_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ||
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ||
_theResult___fst_exp__h577529 == 11'd2047) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
((coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165) ;
assign IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 =
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ?
4'd0 :
(IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ?
4'd1 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2]) ?
4'd2 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3]) ?
4'd3 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4]) ?
4'd4 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6]) ?
4'd5 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7]) ?
4'd6 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8]) ?
4'd7 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10]) ?
4'd8 :
((IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13]) ?
4'd9 :
4'd10))))))))) ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12197 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12198 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210)) ?
coreFix_aluExe_0_bypassWire_2$whas &&
coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214 :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12222 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 ?
coreFix_aluExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12223 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12396 ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12408 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11366 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11367 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11355 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11366 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11368 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11367 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11391 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11392 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379)) ?
coreFix_aluExe_1_bypassWire_2$whas &&
coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11383 :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11391 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11393 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386 ?
coreFix_aluExe_1_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11392 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11750 ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11762 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8239 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8238 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8240 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8239 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8262 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8263 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8262 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8264 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8263 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8286 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8287 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274)) ?
coreFix_fpuMulDivExe_0_bypassWire_2$whas &&
coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278 :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8286 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8288 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ?
coreFix_fpuMulDivExe_0_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8287 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8333 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8344 ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8355 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8355 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1602 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1603 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
coreFix_aluExe_0_bypassWire_1$whas &&
coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 :
coreFix_aluExe_0_bypassWire_0$whas ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ?
coreFix_memExe_bypassWire_2$whas &&
coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1626 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ?
coreFix_memExe_bypassWire_3$whas &&
coreFix_aluExe_0_bypassWire_3$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1627 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1647 ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
coreFix_aluExe_0_bypassWire_1$wget[63:0] :
coreFix_aluExe_0_bypassWire_0$wget[63:0] ;
assign IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 =
((!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614)) ?
coreFix_aluExe_0_bypassWire_2$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1658 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2506 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } :
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2 } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 =
(!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb$procResp[12]) ?
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20 :
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13825 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392) &&
fetchStage$pipelines_1_canDeq) ?
fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_NOT_fetchStage_pipelines_0_canDeq__2695_269_ETC___d13833 =
((!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392) &&
fetchStage$pipelines_1_canDeq) ?
IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 ;
assign IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748 =
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) ?
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731 :
((fetchStage$pipelines_1_first[194:192] == 3'd2) ?
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740 ||
NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) :
_0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746) ;
assign IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13832 =
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656 ?
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 :
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 ;
assign IF_NOT_renameStage_rg_m_halt_req_2724_BIT_4_27_ETC___d13215 =
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034 ?
IF_IF_fetchStage_pipelines_0_first__2697_BIT_6_ETC___d13142 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd0 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd0) ?
4'd0 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd1 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd1) ?
4'd1 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd3 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd2) ?
4'd3 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd4 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd3) ?
4'd4 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd5 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd4) ?
4'd5 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd7 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd5) ?
4'd7 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] == 4'd8 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd6) ?
4'd8 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd9 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd7) ?
4'd9 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd11 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd8) ?
4'd11 :
((renameStage_rg_m_halt_req[4] ?
renameStage_rg_m_halt_req[3:0] ==
4'd14 :
IF_NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3__ETC___d13175 ==
4'd9) ?
4'd14 :
4'd15)))))))))) ;
assign IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ||
rob$deqPort_1_deq_data[26] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10469 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10421 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10467) :
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10702 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d10688 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d10700) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10675 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10897 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[2] :
_theResult___fst_exp__h518565 == 11'd2047 &&
_theResult___fst_sfd__h518566 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10911 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[2] :
_theResult___fst_exp__h557418 == 11'd2047 &&
_theResult___fst_sfd__h557419 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10926 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[2] :
_theResult___fst_exp__h596722 == 11'd2047 &&
_theResult___fst_sfd__h596723 == 52'd0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10943 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[1] :
_theResult___fst_exp__h517782 == 11'd0 &&
guard__h509792 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10955 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[1] :
_theResult___fst_exp__h556635 == 11'd0 &&
guard__h548645 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10968 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[1] :
_theResult___fst_exp__h595939 == 11'd0 &&
guard__h587949 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10985 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755[0] :
_theResult___fst_exp__h517782 != 11'd2047 &&
guard__h509792 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10997 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796[0] :
_theResult___fst_exp__h556635 != 11'd2047 &&
guard__h548645 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d11010 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840[0] :
_theResult___fst_exp__h595939 != 11'd2047 &&
guard__h587949 != 2'b0 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8984 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d8936 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d8982) :
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658 =
((SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157[10],
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 }) -
12'd3074 ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9699 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9651 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9697) :
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9933 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ?
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ?
IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivE_ETC___d9919 :
IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_firs_ETC___d9931) :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9906 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
((_theResult___fst_exp__h369806 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080) :
((_theResult___fst_exp__h378491 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
((_theResult___fst_exp__h369806 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123) :
((_theResult___fst_exp__h378491 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[2] :
_theResult___fst_exp__h379039 == 8'd255 &&
_theResult___fst_sfd__h379040 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[1] :
_theResult___fst_exp__h378491 == 8'd0 &&
guard__h370414 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[0] :
_theResult___fst_exp__h378491 != 8'd255 &&
guard__h370414 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
((_theResult___fst_exp__h415503 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472) :
((_theResult___fst_exp__h424188 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
((_theResult___fst_exp__h415503 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515) :
((_theResult___fst_exp__h424188 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[2] :
_theResult___fst_exp__h424736 == 8'd255 &&
_theResult___fst_sfd__h424737 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[1] :
_theResult___fst_exp__h424188 == 8'd0 &&
guard__h416111 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[0] :
_theResult___fst_exp__h424188 != 8'd255 &&
guard__h416111 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 =
((SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112[7],
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112 }) -
9'd386 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
((_theResult___fst_exp__h461198 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864) :
((_theResult___fst_exp__h469883 == 8'd255) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
((_theResult___fst_exp__h461198 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907) :
((_theResult___fst_exp__h469883 == 8'd255) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914) ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[2] :
_theResult___fst_exp__h470431 == 8'd255 &&
_theResult___fst_sfd__h470432 == 23'd0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[1] :
_theResult___fst_exp__h469883 == 8'd0 &&
guard__h461806 != 2'b0 ;
assign IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[0] :
_theResult___fst_exp__h469883 != 8'd255 &&
guard__h461806 != 2'b0 ;
assign IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091 =
checkForException___d12942[4] ?
CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 :
4'd2 ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207 =
(coreFix_aluExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11342 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11376 =
(coreFix_aluExe_1_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_aluExe_1_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8271 =
(coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_fpuMulDivExe_0_dispToRegQ$RDY_first ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489) :
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6489 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6457 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6487 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6526 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d6507 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6524 :
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6572 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6615 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6628 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6641 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5065 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5095 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d5115 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5132 :
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5205 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5223 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5232 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5236 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d5249 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd51 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd52 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7849 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7879 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
IF_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_ETC___d7899 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7916 :
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[4] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 &&
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978[3] ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8007 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 &&
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8020 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029 :
!SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ||
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d8033 ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5097) :
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5134) ;
assign IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ?
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7881) :
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0 ||
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7918) ;
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066 =
(coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_data[35:34] ==
2'd0) ?
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[63:0] :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$D_OUT[127:64] ;
assign IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 =
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC___d8066[31:0] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10651 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10471,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10675 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8427 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] == 3'd4) ?
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 &&
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 :
coreFix_fpuMulDivExe_0_regToExeQ$first[245:243] != 3'd3 ||
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] :
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9170 ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9881 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:12] :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9701,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879 } ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9906 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] ;
assign IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9937 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[75],
coreFix_fpuMulDivExe_0_regToExeQ$first[74:12] } :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9935,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9879 } ;
assign IF_coreFix_globalSpecUpdate_correctSpecTag_1_w_ETC___d12638 =
coreFix_globalSpecUpdate_correctSpecTag_1$whas ?
result__h643303 :
w__h643298 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2080 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPIndexQ_pipelineResp$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 :
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2099 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194 =
{ (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd7) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd6) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd5) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd4) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2194,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd3) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd2) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2199,
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd1) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64],
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87] ==
3'd0) ?
n___1__h196376 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:516],
4'd2,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } :
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
{ 3'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
1'd1,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] },
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2519 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:0] :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2535 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
3'd5 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
3'd2 :
3'd3) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2546 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1) ?
58'h155555555555554 :
((coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ?
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
2'd0,
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
1'd0 } :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[573:571],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
53'h15555555555555 }) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
x__h194973 :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ?
64'd0 :
64'd1) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042 =
WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3054 =
_theResult_____2__h294368 == v__h293788 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3156 =
_theResult_____2__h302364 == v__h297133 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 =
EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[583] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[583] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3243 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 &&
(EN_dCacheToParent_fromP_enq ?
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[582] :
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[582])) ?
{ 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[65:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[65:0] } :
{ EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[581:518] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[581:518],
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[517:516] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[517:516],
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176 ||
(EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[515] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[515]),
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[514:3] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[514:3],
x__h299998 } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3000 =
!MUX_flush_reservation$write_1__SEL_2 &&
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[58] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_linkAdd_ETC___d3008 =
MUX_flush_reservation$write_1__SEL_2 ?
58'h2AAAAAAAAAAAAAA :
(coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_lat_0$wget[57:0] :
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0]) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ?
!coreFix_memExe_respLrScAmoQ_full :
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2) ?
!coreFix_memExe_respLrScAmoQ_full :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2043 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_first &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0) ?
!coreFix_memExe_memRespLdQ_full :
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2045 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 =
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2102 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ?
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2054 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2100 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2104 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ?
IF_NOT_coreFix_memExe_dMem_cache_m_banks_0_pip_ETC___d2082 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite) :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2103 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140 =
{ (coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82]) ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2518 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ?
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96],
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2140,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 } :
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2517 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2566 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023)) ?
{ 1'd1,
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2563 } :
65'h10000000000000001 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2700 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ?
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$RDY_pipelineResp_releaseEntry :
coreFix_memExe_dMem_cache_m_banks_0_rsToPIndexQ$FULL_N ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2709 =
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[570] ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696) ?
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:512] :
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ?
2'd0 :
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0],
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515:512] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994 =
{ (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd7) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd6) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd5) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1994,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd4) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd3) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d2004 =
{ IF_coreFix_memExe_dMem_cache_m_banks_0_process_ETC___d1999,
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd2) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128],
(coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91] ==
3'd1) ?
n__h192301 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64] } ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2785 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2789 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqFromC_ETC___d2832 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 =
CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320 =
EN_dCacheToParent_rqToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3328 =
_theResult_____2__h308358 == v__h307647 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416 =
EN_dCacheToParent_rsToP_deq ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3424 =
_theResult_____2__h316212 == v__h311523 ;
assign IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[579] :
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[579] ;
assign IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 =
(coreFix_memExe_dTlb$procResp[105:103] == 3'd3) ?
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1740 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
coreFix_memExe_dTlb$procResp[105:103] != 3'd3 &&
!coreFix_memExe_dTlb$procResp[12] :
!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1796 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd0 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd0 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1800 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd1 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd1 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1804 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd2 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd2 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1808 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd3 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd3 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1812 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd4 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd4 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1816 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] == 3'd2 ||
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd5 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd5 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1820 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd6 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd6 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1824 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd7 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd7 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1828 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd8 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd8 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1832 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd9 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd9 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1836 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd10 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd10 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1840 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd11 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd11 ;
assign IF_coreFix_memExe_dTlb_procResp__712_BIT_110_7_ETC___d1844 =
(!coreFix_memExe_dTlb$procResp[12] &&
!coreFix_memExe_dTlb$procResp[110] &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731) ?
coreFix_memExe_dTlb$procResp[105:103] != 3'd2 &&
IF_coreFix_memExe_dTlb_procResp__712_BITS_105__ETC___d1792 ==
4'd12 :
IF_NOT_coreFix_memExe_dTlb_procResp__712_BIT_1_ETC___d1791 ==
4'd12 ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 =
(coreFix_memExe_dispToRegQ$RDY_first &&
coreFix_aluExe_0_bypassWire_0$whas &&
coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) ?
!coreFix_aluExe_0_bypassWire_0$whas ||
coreFix_memExe_dispToRegQ$RDY_first :
!coreFix_aluExe_0_bypassWire_1$whas ||
coreFix_memExe_dispToRegQ$RDY_first ;
assign IF_coreFix_memExe_forwardQ_deqReq_dummy2_2_rea_ETC___d3746 =
_theResult_____2__h329781 == v__h329349 ;
assign IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 =
WILL_FIRE_RL_coreFix_memExe_doRespLdForward ||
coreFix_memExe_forwardQ_deqReq_rl ;
assign IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 =
coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
coreFix_memExe_forwardQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 } :
{ {48{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359[15]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 } :
{ {56{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373[7]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 }) ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 =
coreFix_memExe_lsq$firstLd[94] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 48'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 } :
{ {48{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407[15]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 }) :
(coreFix_memExe_lsq$firstLd[92] ?
{ 56'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 } :
{ {56{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420[7]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 }) ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1378 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 } :
{ {32{SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348[31]}},
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 }) :
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1377 ;
assign IF_coreFix_memExe_lsq_firstLd__277_BIT_96_342__ETC___d1425 =
coreFix_memExe_lsq$firstLd[96] ?
(coreFix_memExe_lsq$firstLd[92] ?
{ 32'd0,
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 } :
{ {32{SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398[31]}},
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 }) :
IF_coreFix_memExe_lsq_firstLd__277_BIT_94_352__ETC___d1424 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_dummy2_2_r_ETC___d3652 =
_theResult_____2__h326556 == v__h326124 ;
assign IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 =
WILL_FIRE_RL_coreFix_memExe_doRespLdMem ||
coreFix_memExe_memRespLdQ_deqReq_rl ;
assign IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 =
coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
coreFix_memExe_memRespLdQ_enqReq_rl[69] ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1208 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[83:82] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[83:82]) :
2'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1212 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[81:79] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[81:79]) :
3'd0 ;
assign IF_coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1__ETC___d1255 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[6:3] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[6:3]) :
4'd0 ;
assign IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 =
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
coreFix_memExe_respLrScAmoQ_enqReq_rl[64] ;
assign IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 =
csrf_minstret_ehr_data_lat_0$whas ?
upd__h710029 :
csrf_minstret_ehr_data_rl ;
assign IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361 =
(fetchStage$RDY_pipelines_0_first &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355) ?
fetchStage$RDY_pipelines_0_first :
!regRenamingTable$rename_0_canRename ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 =
(fetchStage$RDY_pipelines_1_first &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1)) ?
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 ||
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 ||
NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) :
fetchStage$RDY_pipelines_1_first &&
IF_NOT_fetchStage_pipelines_1_first__2706_BITS_ETC___d13748 ;
assign IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 =
(fetchStage$RDY_pipelines_1_first &&
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426 &&
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656) ?
IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 &&
(IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) :
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first ;
assign IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871 =
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 ||
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign IF_fetchStage_pipelines_0_first__2697_BIT_160__ETC___d14051 =
{ fetchStage$pipelines_0_first[159:128],
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 ?
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 } } ;
assign IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969 =
fetchStage$pipelines_0_first[173] ?
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 :
12'hCFF ;
assign IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001 =
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 &&
IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13750 &&
(IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 ||
rob$RDY_enqPort_1_enq &&
regRenamingTable$RDY_rename_1_claimRename &&
regRenamingTable$RDY_rename_1_getRename &&
fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995) ;
assign IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14221 =
(fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 &&
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175) ?
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 } ;
assign IF_fetchStage_pipelines_1_first__2706_BIT_160__ETC___d14180 =
{ fetchStage$pipelines_1_first[159:128],
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174,
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 ?
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 :
{ 1'h0,
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 } } ;
assign IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[142] :
mmio_cRqQ_enqReq_rl[142] ;
assign IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 =
CAN_FIRE_RL_mmio_handlePRq ?
mmio_cRsQ_enqReq_lat_0$wget[1] :
mmio_cRsQ_enqReq_rl[1] ;
assign IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[142] :
mmio_dataReqQ_enqReq_rl[142] ;
assign IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 =
CAN_FIRE_RL_mmio_sendDataResp ?
mmio_dataRespQ_enqReq_lat_0$wget[65] :
mmio_dataRespQ_enqReq_rl[65] ;
assign IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[39] :
mmio_pRqQ_enqReq_rl[39] ;
assign IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 =
EN_mmioToPlatform_pRs_enq ?
mmio_pRsQ_enqReq_lat_0$wget[67] :
mmio_pRsQ_enqReq_rl[67] ;
assign IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 =
rob$deqPort_0_canDeq ? y_avValue_fst__h712284 : 5'd0 ;
assign IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_fst__h712732 :
2'd0 ;
assign IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193 =
rob$deqPort_1_canDeq ?
IF_NOT_rob_deqPort_1_deq_data__4896_BIT_25_489_ETC___d15192 :
rob$deqPort_0_canDeq && rob$deqPort_0_deq_data[26] ;
assign IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139 =
sfdin__h508943[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74 =
sfdin__h415497[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99 =
sfdin__h443426[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179 =
sfdin__h547796[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29 =
sfdin__h352034[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109 =
sfdin__h461192[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39 =
sfdin__h369800[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156 =
sfdin__h587100[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64 =
sfdin__h397731[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66 =
_theResult___snd__h406344[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142 =
_theResult___snd__h517728[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79 =
_theResult___snd__h424134[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175 =
_theResult___snd__h538176[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101 =
_theResult___snd__h452039[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182 =
_theResult___snd__h556581[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31 =
_theResult___snd__h360647[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114 =
_theResult___snd__h469829[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152 =
_theResult___snd__h577480[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44 =
_theResult___snd__h378437[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159 =
_theResult___snd__h595885[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135 =
_theResult___snd__h499323[4] ? 2'd2 : 2'd0 ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5217 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d5245 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6609 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d6637 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[0]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8001 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[2] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivEx_ETC___d8029 =
!_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ||
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[0] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[0]) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272 =
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] &&
!checkForException___d12942[4] &&
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265 &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 =
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] &&
!checkForException___d12942[4] &&
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 ;
assign NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 =
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] &&
!checkForException___d13615[4] &&
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 ;
assign NOT_IF_NOT_rob_deqPort_0_canDeq__4888_4889_OR__ETC___d15198 =
(fflags__h714091 & csrf_fflags_reg) != fflags__h714091 ||
!r__h610340 &&
(IF_rob_deqPort_1_canDeq__4893_THEN_IF_NOT_rob__ETC___d15193 ||
fflags__h714091 != 5'd0) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 =
!f2_sfd__h518979[21] && !f2_sfd__h518979[20] &&
!f2_sfd__h518979[19] &&
!f2_sfd__h518979[18] &&
!f2_sfd__h518979[17] &&
!f2_sfd__h518979[16] &&
!f2_sfd__h518979[15] &&
!f2_sfd__h518979[14] &&
!f2_sfd__h518979[13] &&
!f2_sfd__h518979[12] &&
!f2_sfd__h518979[11] &&
!f2_sfd__h518979[10] &&
!f2_sfd__h518979[9] &&
!f2_sfd__h518979[8] &&
!f2_sfd__h518979[7] &&
!f2_sfd__h518979[6] &&
!f2_sfd__h518979[5] &&
!f2_sfd__h518979[4] &&
!f2_sfd__h518979[3] &&
!f2_sfd__h518979[2] &&
!f2_sfd__h518979[1] &&
!f2_sfd__h518979[0] ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762 =
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) &&
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) &&
(f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10759 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762 |
((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) &&
(f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) &&
(f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10800) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862 =
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) &&
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) &&
(f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10859 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862 |
((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) &&
(f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) &&
(f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10869) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902 =
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) &&
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) &&
(f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10899 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902 |
((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) &&
(f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) &&
(f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10913) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948 =
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) &&
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) &&
(f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10945 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948 |
((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) &&
(f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) &&
(f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10957) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990 =
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 == 23'd0) &&
(f1_exp__h479984 != 8'd255 || f1_sfd__h479985 != 23'd0) &&
(f1_exp__h479984 != 8'd0 || f1_sfd__h479985 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10987 ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990 |
((f2_exp__h518978 != 8'd255 || f2_sfd__h518979 == 23'd0) &&
(f2_exp__h518978 != 8'd255 || f2_sfd__h518979 != 23'd0) &&
(f2_exp__h518978 != 8'd0 || f2_sfd__h518979 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10999) ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 =
!f1_sfd__h479985[21] && !f1_sfd__h479985[20] &&
!f1_sfd__h479985[19] &&
!f1_sfd__h479985[18] &&
!f1_sfd__h479985[17] &&
!f1_sfd__h479985[16] &&
!f1_sfd__h479985[15] &&
!f1_sfd__h479985[14] &&
!f1_sfd__h479985[13] &&
!f1_sfd__h479985[12] &&
!f1_sfd__h479985[11] &&
!f1_sfd__h479985[10] &&
!f1_sfd__h479985[9] &&
!f1_sfd__h479985[8] &&
!f1_sfd__h479985[7] &&
!f1_sfd__h479985[6] &&
!f1_sfd__h479985[5] &&
!f1_sfd__h479985[4] &&
!f1_sfd__h479985[3] &&
!f1_sfd__h479985[2] &&
!f1_sfd__h479985[1] &&
!f1_sfd__h479985[0] ;
assign NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 =
!f3_sfd__h558283[21] && !f3_sfd__h558283[20] &&
!f3_sfd__h558283[19] &&
!f3_sfd__h558283[18] &&
!f3_sfd__h558283[17] &&
!f3_sfd__h558283[16] &&
!f3_sfd__h558283[15] &&
!f3_sfd__h558283[14] &&
!f3_sfd__h558283[13] &&
!f3_sfd__h558283[12] &&
!f3_sfd__h558283[11] &&
!f3_sfd__h558283[10] &&
!f3_sfd__h558283[9] &&
!f3_sfd__h558283[8] &&
!f3_sfd__h558283[7] &&
!f3_sfd__h558283[6] &&
!f3_sfd__h558283[5] &&
!f3_sfd__h558283[4] &&
!f3_sfd__h558283[3] &&
!f3_sfd__h558283[2] &&
!f3_sfd__h558283[1] &&
!f3_sfd__h558283[0] ;
assign NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 ;
assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499 =
(!commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd0 ||
commitStage_commitTrap[3:0] == 4'd1 ||
commitStage_commitTrap[3:0] == 4'd3 ||
commitStage_commitTrap[3:0] == 4'd4 ||
commitStage_commitTrap[3:0] == 4'd5 ||
commitStage_commitTrap[3:0] == 4'd7 ||
commitStage_commitTrap[3:0] == 4'd8 ||
commitStage_commitTrap[3:0] == 4'd9 ||
commitStage_commitTrap[3:0] == 4'd11) &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] != 4'd3 ||
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ;
assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14506 =
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14499 ||
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq ;
assign NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 =
(!commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] != 4'd14) &&
(!commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] == 4'd0 ||
commitStage_commitTrap[3:0] == 4'd1 ||
commitStage_commitTrap[3:0] == 4'd3 ||
commitStage_commitTrap[3:0] == 4'd4 ||
commitStage_commitTrap[3:0] == 4'd5 ||
commitStage_commitTrap[3:0] == 4'd7 ||
commitStage_commitTrap[3:0] == 4'd8 ||
commitStage_commitTrap[3:0] == 4'd9 ||
commitStage_commitTrap[3:0] == 4'd11 ||
commitStage_commitTrap[3:0] == 4'd14) &&
(commitStage_commitTrap[4] ||
commitStage_commitTrap[3:0] != 4'd3 ||
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243) ;
assign NOT_commitStage_rg_run_state_4243_4244_AND_NOT_ETC___d14696 =
!commitStage_rg_run_state && !commitStage_commitTrap[133] &&
!rob$deqPort_0_deq_data[167] &&
!rob$deqPort_0_deq_data[18] &&
rob$deqPort_0_deq_data[25] ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186) ;
assign NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210) &&
(!coreFix_aluExe_0_bypassWire_2$whas ||
!coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11355) ;
assign NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379) &&
(!coreFix_aluExe_1_bypassWire_2$whas ||
!coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11383) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254) ;
assign NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274) &&
(!coreFix_fpuMulDivExe_0_bypassWire_2$whas ||
!coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278) ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ;
assign NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] &&
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ;
assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591) ;
assign NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 =
(!coreFix_aluExe_0_bypassWire_0$whas ||
!coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608) &&
(!coreFix_aluExe_0_bypassWire_1$whas ||
!coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614) &&
(!coreFix_memExe_bypassWire_2$whas ||
!coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2522 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqMsh_ETC___d2662 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3053 =
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_cRqRet_ETC___d3074 =
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$whas ?
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_lat_0$wget[3] :
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl[3])) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3123 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_fromPQ_ETC___d3179 =
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3176) &&
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149 ||
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 =
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] ||
!coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2119 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2531 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState ==
3'd1 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2529) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2574) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd4 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2557) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2601 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2626 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd1 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2634 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2651 =
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) &&
(coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] ==
2'd0 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2673 =
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] ||
IF_coreFix_memExe_dMem_cache_m_banks_0_pipelin_ETC___d2046 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd4 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline$RDY_deqWrite &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd1 ||
coreFix_memExe_stb$RDY_deq)) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqFrom_ETC___d1133 =
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3294 =
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_ETC___d3351 =
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_sendRqToP ?
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_lat_0$wget[72] :
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl[72])) &&
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320 ||
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3390 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_ETC___d3447 =
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT ||
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3443) &&
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416 ||
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty) ;
assign NOT_coreFix_memExe_dMem_perfReqQ_clearReq_dumm_ETC___d1879 =
!coreFix_memExe_dMem_perfReqQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_clearReq_rl ;
assign NOT_coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_ETC___d1923 =
(!coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_enqReq_rl[4]) &&
(coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_deqReq_rl ||
coreFix_memExe_dMem_perfReqQ_empty) ;
assign NOT_coreFix_memExe_dTlb_procResp__712_BITS_174_ETC___d1751 =
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 &&
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 &&
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 &&
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 ;
assign NOT_coreFix_memExe_forwardQ_clearReq_dummy2_1__ETC___d3713 =
!coreFix_memExe_forwardQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_forwardQ_clearReq_rl ;
assign NOT_coreFix_memExe_forwardQ_enqReq_dummy2_2_re_ETC___d3768 =
(!coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_forwardQ_enqReq_lat_0$whas ?
!coreFix_memExe_forwardQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_forwardQ_enqReq_rl[69])) &&
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739 ||
coreFix_memExe_forwardQ_empty) ;
assign NOT_coreFix_memExe_memRespLdQ_clearReq_dummy2__ETC___d3619 =
!coreFix_memExe_memRespLdQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_memRespLdQ_clearReq_rl ;
assign NOT_coreFix_memExe_memRespLdQ_enqReq_dummy2_2__ETC___d3674 =
(!coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_memRespLdQ_enqReq_lat_0$whas ?
!coreFix_memExe_memRespLdQ_enqReq_lat_0$wget[69] :
!coreFix_memExe_memRespLdQ_enqReq_rl[69])) &&
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645 ||
coreFix_memExe_memRespLdQ_empty) ;
assign NOT_coreFix_memExe_reqLdQ_full_dummy2_0_read___ETC___d1473 =
!coreFix_memExe_reqLdQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLdQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLdQ_full_rl ;
assign NOT_coreFix_memExe_reqLrScAmoQ_full_dummy2_0_r_ETC___d1024 =
!coreFix_memExe_reqLrScAmoQ_full_dummy2_0$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_1$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_dummy2_2$Q_OUT ||
!coreFix_memExe_reqLrScAmoQ_full_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_clearReq_dummy_ETC___d3543 =
!coreFix_memExe_respLrScAmoQ_clearReq_dummy2_1$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_clearReq_rl ;
assign NOT_coreFix_memExe_respLrScAmoQ_enqReq_dummy2__ETC___d3585 =
(!coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT ||
(coreFix_memExe_respLrScAmoQ_enqReq_lat_0$whas ?
!coreFix_memExe_respLrScAmoQ_enqReq_lat_0$wget[64] :
!coreFix_memExe_respLrScAmoQ_enqReq_rl[64])) &&
(coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT &&
(coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas ||
coreFix_memExe_respLrScAmoQ_deqReq_rl) ||
coreFix_memExe_respLrScAmoQ_empty) ;
assign NOT_coreFix_memExe_respLrScAmoQ_full_948_949_A_ETC___d2078 =
!coreFix_memExe_respLrScAmoQ_full &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$RDY_pipelineResp_releaseEntry &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ||
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full) ;
assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13265 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[199:195] != 5'd13 ||
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261 &&
!csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974) ;
assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_0_first[95] ||
!fetchStage$pipelines_0_first[94]) &&
(!fetchStage$pipelines_0_first[88] ||
!fetchStage$pipelines_0_first[87]) &&
!fetchStage$pipelines_0_first[81] &&
(!fetchStage$pipelines_0_first[75] ||
!fetchStage$pipelines_0_first[74])) &&
(fetchStage$pipelines_0_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 =
(csrf_fs_reg != 2'd0 ||
(!fetchStage$pipelines_1_first[95] ||
!fetchStage$pipelines_1_first[94]) &&
(!fetchStage$pipelines_1_first[88] ||
!fetchStage$pipelines_1_first[87]) &&
!fetchStage$pipelines_1_first[81] &&
(!fetchStage$pipelines_1_first[75] ||
!fetchStage$pipelines_1_first[74])) &&
(fetchStage$pipelines_1_first[231:200] != 32'h10500073 ||
!csrf_tw_reg ||
csrf_prv_reg == 2'd3) ;
assign NOT_csrf_prv_reg_read__2727_ULE_1_4567_4608_OR_ETC___d14612 =
!csrf_prv_reg_read__2727_ULE_1___d14567 ||
(commitStage_commitTrap[4] ?
!_0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 :
!_0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587) ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13731 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 =
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445) &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953 =
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 &&
(fetchStage$pipelines_1_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14007 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873 &&
IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361) &&
fetchStage$RDY_pipelines_0_first &&
fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 =
(!fetchStage$pipelines_0_canDeq ||
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391) &&
fetchStage$pipelines_1_canDeq ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 =
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 &&
(fetchStage$pipelines_1_first[194:192] == 3'd0 ||
fetchStage$pipelines_1_first[194:192] == 3'd1) &&
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167 =
!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 ||
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 =
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14167 &&
coreFix_memExe_rsMem$canEnq &&
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 ;
assign NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14198 =
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 &&
specTagManager$canClaim &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 &&
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 &&
fetchStage$pipelines_1_first[194:192] == 3'd1 ;
assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13261 =
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
fetchStage$pipelines_0_first[178:174] != 5'd15) &&
rs1__h651905 == 5'd0 &&
imm__h651906 == 32'd0 ||
IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[11:10] !=
2'b11 ;
assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13392 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 ;
assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 &&
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 ;
assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 &&
(!coreFix_aluExe_0_rsAlu$canEnq ||
!coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370) ;
assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13830 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ;
assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq ;
assign NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14083 =
{ fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039,
(fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042) ?
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 :
{ 1'h0,
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 },
7'd32,
specTagManager$currentSpecBits } ;
assign NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403 =
!fetchStage$pipelines_0_first[68] &&
!checkForException___d12942[4] &&
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13346 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_fetchStage_pipelines_1_canDeq__2703_2704_O_ETC___d12712 =
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(epochManager$checkEpoch_1_check ||
fetchStage$RDY_pipelines_1_deq) ;
assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13426 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 ||
csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424) ;
assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13656 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13453 &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 ;
assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
(!fetchStage$pipelines_0_canDeq ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 ||
fetchStage$pipelines_0_first[194:192] != 3'd1) &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 ;
assign NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d14120 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14111 &&
specTagManager$canClaim) &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 ;
assign NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117 =
!fetchStage$pipelines_1_first[68] &&
!checkForException___d13615[4] &&
NOT_csrf_fs_reg_read__1527_EQ_0_2931_2932_OR_N_ETC___d13640 &&
rob$enqPort_1_canEnq &&
epochManager$checkEpoch_1_check &&
!csrf_rg_dcsr[2] ;
assign NOT_mmio_cRqQ_clearReq_dummy2_1_read__26_27_OR_ETC___d431 =
!mmio_cRqQ_clearReq_dummy2_1$Q_OUT || !mmio_cRqQ_clearReq_rl ;
assign NOT_mmio_cRqQ_enqReq_dummy2_2_read__32_47_OR_I_ETC___d452 =
(!mmio_cRqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_cRqQ_enqReq_lat_0$whas ?
!mmio_cRqQ_enqReq_lat_0$wget[142] :
!mmio_cRqQ_enqReq_rl[142])) &&
(mmio_cRqQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRq_deq || mmio_cRqQ_deqReq_rl) ||
mmio_cRqQ_empty) ;
assign NOT_mmio_cRsQ_clearReq_dummy2_1_read__18_19_OR_ETC___d823 =
!mmio_cRsQ_clearReq_dummy2_1$Q_OUT || !mmio_cRsQ_clearReq_rl ;
assign NOT_mmio_cRsQ_enqReq_dummy2_2_read__24_39_OR_I_ETC___d844 =
(!mmio_cRsQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_handlePRq ?
!mmio_cRsQ_enqReq_lat_0$wget[1] :
!mmio_cRsQ_enqReq_rl[1])) &&
(mmio_cRsQ_deqReq_dummy2_2$Q_OUT &&
(EN_mmioToPlatform_cRs_deq || mmio_cRsQ_deqReq_rl) ||
mmio_cRsQ_empty) ;
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1091 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqSt &&
coreFix_memExe_lsq$RDY_firstSt ;
assign NOT_mmio_dataPendQ_empty_23_090_AND_rob_RDY_se_ETC___d1390 =
!mmio_dataPendQ_empty && rob$RDY_setExecuted_deqLSQ &&
coreFix_memExe_lsq$RDY_deqLd &&
coreFix_memExe_lsq$RDY_firstLd ;
assign NOT_mmio_dataPendQ_enqReq_dummy2_2_read__00_15_ETC___d325 =
(!mmio_dataPendQ_enqReq_dummy2_2$Q_OUT ||
!mmio_dataPendQ_enqReq_lat_0$whas &&
!mmio_dataPendQ_enqReq_rl) &&
(mmio_dataPendQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataPendQ_deqReq_rl) ||
mmio_dataPendQ_empty) ;
assign NOT_mmio_dataReqQ_clearReq_dummy2_1_read__35_3_ETC___d140 =
!mmio_dataReqQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataReqQ_clearReq_rl ;
assign NOT_mmio_dataReqQ_enqReq_dummy2_2_read__41_56__ETC___d161 =
(!mmio_dataReqQ_enqReq_dummy2_2$Q_OUT ||
(mmio_dataReqQ_enqReq_lat_0$whas ?
!mmio_dataReqQ_enqReq_lat_0$wget[142] :
!mmio_dataReqQ_enqReq_rl[142])) &&
(mmio_dataReqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_sendDataReq || mmio_dataReqQ_deqReq_rl) ||
mmio_dataReqQ_empty) ;
assign NOT_mmio_dataRespQ_clearReq_dummy2_1_read__36__ETC___d241 =
!mmio_dataRespQ_clearReq_dummy2_1$Q_OUT ||
!mmio_dataRespQ_clearReq_rl ;
assign NOT_mmio_dataRespQ_enqReq_dummy2_2_read__42_57_ETC___d262 =
(!mmio_dataRespQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_mmio_sendDataResp ?
!mmio_dataRespQ_enqReq_lat_0$wget[65] :
!mmio_dataRespQ_enqReq_rl[65])) &&
(mmio_dataRespQ_deqReq_dummy2_2$Q_OUT &&
(mmio_dataRespQ_deqReq_lat_0$whas ||
mmio_dataRespQ_deqReq_rl) ||
mmio_dataRespQ_empty) ;
assign NOT_mmio_pRqQ_clearReq_dummy2_1_read__29_30_OR_ETC___d734 =
!mmio_pRqQ_clearReq_dummy2_1$Q_OUT || !mmio_pRqQ_clearReq_rl ;
assign NOT_mmio_pRqQ_enqReq_dummy2_2_read__35_50_OR_I_ETC___d755 =
(!mmio_pRqQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRq_enq ?
!mmio_pRqQ_enqReq_lat_0$wget[39] :
!mmio_pRqQ_enqReq_rl[39])) &&
(mmio_pRqQ_deqReq_dummy2_2$Q_OUT &&
(CAN_FIRE_RL_mmio_handlePRq || mmio_pRqQ_deqReq_rl) ||
mmio_pRqQ_empty) ;
assign NOT_mmio_pRsQ_clearReq_dummy2_1_read__88_89_OR_ETC___d593 =
!mmio_pRsQ_clearReq_dummy2_1$Q_OUT || !mmio_pRsQ_clearReq_rl ;
assign NOT_mmio_pRsQ_enqReq_dummy2_2_read__94_09_OR_I_ETC___d614 =
(!mmio_pRsQ_enqReq_dummy2_2$Q_OUT ||
(EN_mmioToPlatform_pRs_enq ?
!mmio_pRsQ_enqReq_lat_0$wget[67] :
!mmio_pRsQ_enqReq_rl[67])) &&
(mmio_pRsQ_deqReq_dummy2_2$Q_OUT &&
(mmio_pRsQ_deqReq_lat_0$whas || mmio_pRsQ_deqReq_rl) ||
mmio_pRsQ_empty) ;
assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676 ;
assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 =
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752 ;
assign NOT_regRenamingTable_rename_0_canRename__3329__ETC___d14099 =
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d12942[4] ||
!rob$enqPort_0_canEnq ;
assign NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718 =
!regRenamingTable$rename_1_canRename ||
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716 ;
assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13034 =
!renameStage_rg_m_halt_req[4] &&
(fetchStage$pipelines_0_first[68] ||
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] &&
!IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15]) ;
assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 &&
rob$enqPort_0_canEnq &&
epochManager$checkEpoch_0_check ;
assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651 ;
assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793 ;
assign NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813 =
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_1_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13642 &&
rob$enqPort_1_canEnq &&
epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811 ;
assign NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_RDY_ETC___d14930 =
(!rob$deqPort_0_canDeq ||
rob$RDY_deqPort_0_deq && regRenamingTable$RDY_commit_0_commit &&
v_f_to_TV_0$FULL_N) &&
(!rob$deqPort_1_canDeq ||
rob$RDY_deqPort_1_deq_data &&
NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927) ;
assign NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 =
(!rob$deqPort_0_canDeq ||
rob$deqPort_0_deq_data[25] && !rob$deqPort_0_deq_data[18] &&
!rob$deqPort_0_deq_data[167] &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd21 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20) &&
rob$deqPort_1_canDeq ;
assign NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684 =
rob$deqPort_0_deq_data[186:182] != 5'd13 ||
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 !=
6'd7 ||
csrf_stats_module_writeQ$FULL_N) &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 !=
6'd6 ||
csrf_terminate_module_terminateQ$FULL_N) ;
assign NOT_rob_deqPort_1_deq_data__4896_BIT_25_4897_4_ETC___d14927 =
!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20 ||
rob$RDY_deqPort_1_deq && regRenamingTable$RDY_commit_1_commit &&
v_f_to_TV_1$FULL_N ;
assign NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924 =
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991 =
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 ||
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2916,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2925,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254,
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2941 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261,
!CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262,
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2934,
x__h289463 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rq_ETC___d15604 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560 =
{ CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15560,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 } ;
assign SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15578 =
{ SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_rs_ETC___d15569,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256,
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 =
{ {4{f2_exp18978_MINUS_127__q176[7]}},
f2_exp18978_MINUS_127__q176 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 =
{ {4{f1_exp79984_MINUS_127__q136[7]}},
f1_exp79984_MINUS_127__q136 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 =
{ {4{f3_exp58282_MINUS_127__q153[7]}},
f3_exp58282_MINUS_127__q153 } ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q140 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
11'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q157 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
11'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 +
12'd1023 ;
assign SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q180 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
11'd1023 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71[10],
coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q77 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36[10],
coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q42 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] -
8'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106[10],
coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106 } ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ^
12'h800) <=
12'd2175 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ^
12'h800) <
12'd1922 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 +
12'd127 ;
assign SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q112 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165 =
{ 3'd0,
_theResult___fst_exp__h352040 == 8'd0 &&
(sfdin__h352034[56:34] == 23'd0 || guard__h343939 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h352637 == 8'd255 &&
_theResult___fst_sfd__h352638 == 23'd0,
1'd0,
_theResult___fst_exp__h352040 != 8'd255 &&
guard__h343939 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557 =
{ 3'd0,
_theResult___fst_exp__h397737 == 8'd0 &&
(sfdin__h397731[56:34] == 23'd0 || guard__h389638 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h398334 == 8'd255 &&
_theResult___fst_sfd__h398335 == 23'd0,
1'd0,
_theResult___fst_exp__h397737 != 8'd255 &&
guard__h389638 != 2'b0 } ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949 =
{ 3'd0,
_theResult___fst_exp__h443432 == 8'd0 &&
(sfdin__h443426[56:34] == 23'd0 || guard__h435333 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h444029 == 8'd255 &&
_theResult___fst_sfd__h444030 == 23'd0,
1'd0,
_theResult___fst_exp__h443432 != 8'd255 &&
guard__h435333 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10755 =
{ 3'd0,
_theResult___fst_exp__h508949 == 11'd0 &&
(sfdin__h508943[56:5] == 52'd0 || guard__h500723 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h509781 == 11'd2047 &&
_theResult___fst_sfd__h509782 == 52'd0,
1'd0,
_theResult___fst_exp__h508949 != 11'd2047 &&
guard__h500723 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10796 =
{ 3'd0,
_theResult___fst_exp__h547802 == 11'd0 &&
(sfdin__h547796[56:5] == 52'd0 || guard__h539576 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h548634 == 11'd2047 &&
_theResult___fst_sfd__h548635 == 52'd0,
1'd0,
_theResult___fst_exp__h547802 != 11'd2047 &&
guard__h539576 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10840 =
{ 3'd0,
_theResult___fst_exp__h587106 == 11'd0 &&
(sfdin__h587100[56:5] == 52'd0 || guard__h578880 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h587938 == 11'd2047 &&
_theResult___fst_sfd__h587939 == 52'd0,
1'd0,
_theResult___fst_exp__h587106 != 11'd2047 &&
guard__h578880 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d5194 =
{ 3'd0,
_theResult___fst_exp__h369806 == 8'd0 &&
(sfdin__h369800[56:34] == 23'd0 || guard__h361578 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h370403 == 8'd255 &&
_theResult___fst_sfd__h370404 == 23'd0,
1'd0,
_theResult___fst_exp__h369806 != 8'd255 &&
guard__h361578 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6586 =
{ 3'd0,
_theResult___fst_exp__h415503 == 8'd0 &&
(sfdin__h415497[56:34] == 23'd0 || guard__h407275 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h416100 == 8'd255 &&
_theResult___fst_sfd__h416101 == 23'd0,
1'd0,
_theResult___fst_exp__h415503 != 8'd255 &&
guard__h407275 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7978 =
{ 3'd0,
_theResult___fst_exp__h461198 == 8'd0 &&
(sfdin__h461192[56:34] == 23'd0 || guard__h452970 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h461795 == 8'd255 &&
_theResult___fst_sfd__h461796 == 23'd0,
1'd0,
_theResult___fst_exp__h461198 != 8'd255 &&
guard__h452970 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428 ^
12'h800) ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10738 =
{ 3'd0,
_theResult___fst_exp__h499372 == 11'd0 &&
guard__h491411 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h500130 == 11'd2047 &&
_theResult___fst_sfd__h500131 == 52'd0,
1'd0,
_theResult___fst_exp__h499372 != 11'd2047 &&
guard__h491411 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10779 =
{ 3'd0,
_theResult___fst_exp__h538225 == 11'd0 &&
guard__h530264 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h538983 == 11'd2047 &&
_theResult___fst_sfd__h538984 == 52'd0,
1'd0,
_theResult___fst_exp__h538225 != 11'd2047 &&
guard__h530264 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10823 =
{ 3'd0,
_theResult___fst_exp__h577529 == 11'd0 &&
guard__h569568 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h578287 == 11'd2047 &&
_theResult___fst_sfd__h578288 == 52'd0,
1'd0,
_theResult___fst_exp__h577529 != 11'd2047 &&
guard__h569568 != 2'b0 } ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943 ^
12'h800) ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659 =
({ 6'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ^
12'h800) <=
(IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658 ^
12'h800) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177 =
{ 3'd0,
_theResult___fst_exp__h360696 == 8'd0 &&
guard__h352648 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h361219 == 8'd255 &&
_theResult___fst_sfd__h361220 == 23'd0,
1'd0,
_theResult___fst_exp__h360696 != 8'd255 &&
guard__h352648 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569 =
{ 3'd0,
_theResult___fst_exp__h406393 == 8'd0 &&
guard__h398345 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h406916 == 8'd255 &&
_theResult___fst_sfd__h406917 == 23'd0,
1'd0,
_theResult___fst_exp__h406393 != 8'd255 &&
guard__h398345 != 2'b0 } ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653 =
({ 3'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ^
9'h100) <=
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652 ^
9'h100) ;
assign _0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961 =
{ 3'd0,
_theResult___fst_exp__h452088 == 8'd0 &&
guard__h444040 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h452611 == 8'd255 &&
_theResult___fst_sfd__h452612 == 23'd0,
1'd0,
_theResult___fst_exp__h452088 != 8'd255 &&
guard__h444040 != 2'b0 } ;
assign _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735 =
{ 4'd0,
csrf_external_int_en_vec_3 & csrf_external_int_pend_vec_3,
1'd0,
csrf_external_int_en_vec_1 & csrf_external_int_pend_vec_1,
csrf_external_int_en_vec_0 & csrf_external_int_pend_vec_0 } ;
assign _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740 =
{ _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12735,
csrf_timer_int_en_vec_3 & csrf_timer_int_pend_vec_3,
1'd0,
csrf_timer_int_en_vec_1 & csrf_timer_int_pend_vec_1,
csrf_timer_int_en_vec_0 & csrf_timer_int_pend_vec_0 } ;
assign _0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845 =
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 ;
assign _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13746 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
!fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first) &&
(fetchStage$RDY_pipelines_0_first &&
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 ||
NOT_regRenamingTable_rename_1_canRename__3456__ETC___d13718) ;
assign _0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937 =
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_nextSpecTag) &&
CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135 =
sfd__h519340 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650 =
sfd__h480346 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ;
assign _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365 =
sfd__h558644 >>
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554 =
sfd__h336324 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946 =
sfd__h382026 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942) ;
assign _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338 =
sfd__h427721 >>
(_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334[11] ?
12'hAAA :
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334) ;
assign _0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587 =
medeleg_csr__read__h608155[i__h698077] ;
assign _0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 =
mideleg_csr__read__h608250[i__h698237] ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4007 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5180 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5205 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5232 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5165[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5177[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5399 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6572 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6597 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6624 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d6557[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6569[1]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 =
12'd3074 -
{ 6'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56] ?
6'd0 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[55] ?
6'd1 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[54] ?
6'd2 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[53] ?
6'd3 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[52] ?
6'd4 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[51] ?
6'd5 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[50] ?
6'd6 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[49] ?
6'd7 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[48] ?
6'd8 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[47] ?
6'd9 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[46] ?
6'd10 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[45] ?
6'd11 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[44] ?
6'd12 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[43] ?
6'd13 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[42] ?
6'd14 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[41] ?
6'd15 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[40] ?
6'd16 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[39] ?
6'd17 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[38] ?
6'd18 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[37] ?
6'd19 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[36] ?
6'd20 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[35] ?
6'd21 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[34] ?
6'd22 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[33] ?
6'd23 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[32] ?
6'd24 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[31] ?
6'd25 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[30] ?
6'd26 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[29] ?
6'd27 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[28] ?
6'd28 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[27] ?
6'd29 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[26] ?
6'd30 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[25] ?
6'd31 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[24] ?
6'd32 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[23] ?
6'd33 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[22] ?
6'd34 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[21] ?
6'd35 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[20] ?
6'd36 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[19] ?
6'd37 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[18] ?
6'd38 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[17] ?
6'd39 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[16] ?
6'd40 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[15] ?
6'd41 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[14] ?
6'd42 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[13] ?
6'd43 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[12] ?
6'd44 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[11] ?
6'd45 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[10] ?
6'd46 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[9] ?
6'd47 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[8] ?
6'd48 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[7] ?
6'd49 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[6] ?
6'd50 :
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[5] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 =
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6791 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7964 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[4] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[4]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d7989 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[3] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[3]) ;
assign _3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d8016 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 &&
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7949[1] :
_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7961[1]) ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10128 ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8643 ;
assign _3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 =
12'd3074 -
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9358 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10006 =
12'd3970 -
{ 7'd0,
f2_sfd__h518979[22] ?
5'd0 :
(f2_sfd__h518979[21] ?
5'd1 :
(f2_sfd__h518979[20] ?
5'd2 :
(f2_sfd__h518979[19] ?
5'd3 :
(f2_sfd__h518979[18] ?
5'd4 :
(f2_sfd__h518979[17] ?
5'd5 :
(f2_sfd__h518979[16] ?
5'd6 :
(f2_sfd__h518979[15] ?
5'd7 :
(f2_sfd__h518979[14] ?
5'd8 :
(f2_sfd__h518979[13] ?
5'd9 :
(f2_sfd__h518979[12] ?
5'd10 :
(f2_sfd__h518979[11] ?
5'd11 :
(f2_sfd__h518979[10] ?
5'd12 :
(f2_sfd__h518979[9] ?
5'd13 :
(f2_sfd__h518979[8] ?
5'd14 :
(f2_sfd__h518979[7] ?
5'd15 :
(f2_sfd__h518979[6] ?
5'd16 :
(f2_sfd__h518979[5] ?
5'd17 :
(f2_sfd__h518979[4] ?
5'd18 :
(f2_sfd__h518979[3] ?
5'd19 :
(f2_sfd__h518979[2] ?
5'd20 :
(f2_sfd__h518979[1] ?
5'd21 :
(f2_sfd__h518979[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10006 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10006 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8506 =
12'd3970 -
{ 7'd0,
f1_sfd__h479985[22] ?
5'd0 :
(f1_sfd__h479985[21] ?
5'd1 :
(f1_sfd__h479985[20] ?
5'd2 :
(f1_sfd__h479985[19] ?
5'd3 :
(f1_sfd__h479985[18] ?
5'd4 :
(f1_sfd__h479985[17] ?
5'd5 :
(f1_sfd__h479985[16] ?
5'd6 :
(f1_sfd__h479985[15] ?
5'd7 :
(f1_sfd__h479985[14] ?
5'd8 :
(f1_sfd__h479985[13] ?
5'd9 :
(f1_sfd__h479985[12] ?
5'd10 :
(f1_sfd__h479985[11] ?
5'd11 :
(f1_sfd__h479985[10] ?
5'd12 :
(f1_sfd__h479985[9] ?
5'd13 :
(f1_sfd__h479985[8] ?
5'd14 :
(f1_sfd__h479985[7] ?
5'd15 :
(f1_sfd__h479985[6] ?
5'd16 :
(f1_sfd__h479985[5] ?
5'd17 :
(f1_sfd__h479985[4] ?
5'd18 :
(f1_sfd__h479985[3] ?
5'd19 :
(f1_sfd__h479985[2] ?
5'd20 :
(f1_sfd__h479985[1] ?
5'd21 :
(f1_sfd__h479985[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8506 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8506 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9236 =
12'd3970 -
{ 7'd0,
f3_sfd__h558283[22] ?
5'd0 :
(f3_sfd__h558283[21] ?
5'd1 :
(f3_sfd__h558283[20] ?
5'd2 :
(f3_sfd__h558283[19] ?
5'd3 :
(f3_sfd__h558283[18] ?
5'd4 :
(f3_sfd__h558283[17] ?
5'd5 :
(f3_sfd__h558283[16] ?
5'd6 :
(f3_sfd__h558283[15] ?
5'd7 :
(f3_sfd__h558283[14] ?
5'd8 :
(f3_sfd__h558283[13] ?
5'd9 :
(f3_sfd__h558283[12] ?
5'd10 :
(f3_sfd__h558283[11] ?
5'd11 :
(f3_sfd__h558283[10] ?
5'd12 :
(f3_sfd__h558283[9] ?
5'd13 :
(f3_sfd__h558283[8] ?
5'd14 :
(f3_sfd__h558283[7] ?
5'd15 :
(f3_sfd__h558283[6] ?
5'd16 :
(f3_sfd__h558283[5] ?
5'd17 :
(f3_sfd__h558283[4] ?
5'd18 :
(f3_sfd__h558283[3] ?
5'd19 :
(f3_sfd__h558283[2] ?
5'd20 :
(f3_sfd__h558283[1] ?
5'd21 :
(f3_sfd__h558283[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9236 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 =
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9236 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4547 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5939 ;
assign _3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 =
12'd3970 -
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7331 ;
assign _dfoo12 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 &&
fetchStage$pipelines_1_first[199:195] != 5'd14 ;
assign _dfoo16 =
k__h664083 == 1'd1 &&
fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 ||
(fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104) ==
1'd1 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 ;
assign _dfoo18 =
k__h664083 == 1'd0 &&
fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 ||
(fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14104) ==
1'd0 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14123 ;
assign _dfoo2 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 &&
fetchStage$pipelines_1_first[191:189] != 3'd0 &&
fetchStage$pipelines_1_first[191:189] != 3'd2 ;
assign _dfoo20 =
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
NOT_commitStage_commitTrap_4245_BIT_4_4464_446_ETC___d14566 ;
assign _dfoo24 =
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd36 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20 ;
assign _dfoo26 =
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd20 ;
assign _dfoo32 =
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
(IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd8 ||
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 ==
6'd18) ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ;
assign _dfoo7 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055 ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14109 &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 &&
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d14168 &&
(fetchStage$pipelines_1_first[191:189] == 3'd0 ||
fetchStage$pipelines_1_first[191:189] == 3'd2) ;
assign _dor1coreFix_aluExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_0_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_aluExe_1_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_aluExe_1_rsAlu$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_fpuMulDivExe_0_rsFpuMulDiv$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_bypassWire_2$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1coreFix_memExe_bypassWire_3$EN_wset =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1coreFix_memExe_forwardQ_enqReq_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_data_0_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_empty_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_enqP_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_dummy2_0$EN_write =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_reqLdQ_full_lat_0$EN_wset =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1coreFix_memExe_rsMem$EN_setRegReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1rf$EN_write_0_wr =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1rf$EN_write_1_wr =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _dor1sbAggr$EN_setReady_3_put =
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromIssueQ ||
WILL_FIRE_RL_coreFix_memExe_doIssueLdFromUpdate ;
assign _dor1sbCons$EN_setReady_0_put =
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_0_doFinishAlu_T ;
assign _dor1sbCons$EN_setReady_1_put =
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_F ||
WILL_FIRE_RL_coreFix_aluExe_1_doFinishAlu_T ;
assign _theResult_____2__h294368 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3042) ?
next_deqP___1__h294647 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ;
assign _theResult_____2__h302364 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3149) ?
next_deqP___1__h302643 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP ;
assign _theResult_____2__h308358 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3320) ?
next_deqP___1__h308924 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP ;
assign _theResult_____2__h316212 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3416) ?
next_deqP___1__h316778 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP ;
assign _theResult_____2__h326556 =
(coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_deqReq_lat_1_whas_ETC___d3645) ?
next_deqP___1__h326835 :
coreFix_memExe_memRespLdQ_deqP ;
assign _theResult_____2__h329781 =
(coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_deqReq_lat_1_whas___ETC___d3739) ?
next_deqP___1__h330060 :
coreFix_memExe_forwardQ_deqP ;
assign _theResult____h343929 =
(value__h344551 == 54'd0) ? sfd__h336324 : 57'd1 ;
assign _theResult____h361568 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ^
12'h800) <
12'd2105) ?
result__h362181 :
_theResult____h343929 ;
assign _theResult____h389628 =
(value__h390248 == 54'd0) ? sfd__h382026 : 57'd1 ;
assign _theResult____h407265 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ^
12'h800) <
12'd2105) ?
result__h407878 :
_theResult____h389628 ;
assign _theResult____h435323 =
(value__h435943 == 54'd0) ? sfd__h427721 : 57'd1 ;
assign _theResult____h452960 =
((_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ^
12'h800) <
12'd2105) ?
result__h453573 :
_theResult____h435323 ;
assign _theResult____h500713 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ^
12'h800) <
12'd2105) ?
result__h501326 :
((value__h484929 == 25'd0) ? sfd__h480346 : 57'd1) ;
assign _theResult____h539566 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ^
12'h800) <
12'd2105) ?
result__h540179 :
((value__h523782 == 25'd0) ? sfd__h519340 : 57'd1) ;
assign _theResult____h578870 =
((_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ^
12'h800) <
12'd2105) ?
result__h579483 :
((value__h563086 == 25'd0) ? sfd__h558644 : 57'd1) ;
assign _theResult____h647726 =
(csrf_prv_reg != 2'd3 || csrf_ie_vec_3) ?
enabled_ints___1__h648251 :
16'd0 ;
assign _theResult___exp__h352556 =
sfd__h352132[24] ?
((_theResult___fst_exp__h352040 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379073) :
((_theResult___fst_exp__h352040 == 8'd0 &&
sfd__h352132[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h352040) ;
assign _theResult___exp__h361138 =
sfd__h360714[24] ?
((_theResult___fst_exp__h360696 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379097) :
((_theResult___fst_exp__h360696 == 8'd0 &&
sfd__h360714[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h360696) ;
assign _theResult___exp__h370322 =
sfd__h369898[24] ?
((_theResult___fst_exp__h369806 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379127) :
((_theResult___fst_exp__h369806 == 8'd0 &&
sfd__h369898[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h369806) ;
assign _theResult___exp__h378958 =
sfd__h378510[24] ?
((_theResult___fst_exp__h378491 == 8'd254) ?
8'd255 :
din_inc___2_exp__h379151) :
((_theResult___fst_exp__h378491 == 8'd0 &&
sfd__h378510[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h378491) ;
assign _theResult___exp__h379060 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h379051 ;
assign _theResult___exp__h398253 =
sfd__h397829[24] ?
((_theResult___fst_exp__h397737 == 8'd254) ?
8'd255 :
din_inc___2_exp__h424770) :
((_theResult___fst_exp__h397737 == 8'd0 &&
sfd__h397829[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h397737) ;
assign _theResult___exp__h406835 =
sfd__h406411[24] ?
((_theResult___fst_exp__h406393 == 8'd254) ?
8'd255 :
din_inc___2_exp__h424794) :
((_theResult___fst_exp__h406393 == 8'd0 &&
sfd__h406411[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h406393) ;
assign _theResult___exp__h416019 =
sfd__h415595[24] ?
((_theResult___fst_exp__h415503 == 8'd254) ?
8'd255 :
din_inc___2_exp__h424824) :
((_theResult___fst_exp__h415503 == 8'd0 &&
sfd__h415595[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h415503) ;
assign _theResult___exp__h424655 =
sfd__h424207[24] ?
((_theResult___fst_exp__h424188 == 8'd254) ?
8'd255 :
din_inc___2_exp__h424848) :
((_theResult___fst_exp__h424188 == 8'd0 &&
sfd__h424207[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h424188) ;
assign _theResult___exp__h424757 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h424748 ;
assign _theResult___exp__h443948 =
sfd__h443524[24] ?
((_theResult___fst_exp__h443432 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470465) :
((_theResult___fst_exp__h443432 == 8'd0 &&
sfd__h443524[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h443432) ;
assign _theResult___exp__h452530 =
sfd__h452106[24] ?
((_theResult___fst_exp__h452088 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470489) :
((_theResult___fst_exp__h452088 == 8'd0 &&
sfd__h452106[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h452088) ;
assign _theResult___exp__h461714 =
sfd__h461290[24] ?
((_theResult___fst_exp__h461198 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470519) :
((_theResult___fst_exp__h461198 == 8'd0 &&
sfd__h461290[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h461198) ;
assign _theResult___exp__h470350 =
sfd__h469902[24] ?
((_theResult___fst_exp__h469883 == 8'd254) ?
8'd255 :
din_inc___2_exp__h470543) :
((_theResult___fst_exp__h469883 == 8'd0 &&
sfd__h469902[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h469883) ;
assign _theResult___exp__h470452 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h470443 ;
assign _theResult___exp__h500027 =
sfd__h499390[53] ?
((_theResult___fst_exp__h499372 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h518622) :
((_theResult___fst_exp__h499372 == 11'd0 &&
sfd__h499390[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h499372) ;
assign _theResult___exp__h509678 =
sfd__h509041[53] ?
((_theResult___fst_exp__h508949 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h518657) :
((_theResult___fst_exp__h508949 == 11'd0 &&
sfd__h509041[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h508949) ;
assign _theResult___exp__h518462 =
sfd__h517801[53] ?
((_theResult___fst_exp__h517782 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h518683) :
((_theResult___fst_exp__h517782 == 11'd0 &&
sfd__h517801[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h517782) ;
assign _theResult___exp__h538880 =
sfd__h538243[53] ?
((_theResult___fst_exp__h538225 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h557475) :
((_theResult___fst_exp__h538225 == 11'd0 &&
sfd__h538243[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h538225) ;
assign _theResult___exp__h548531 =
sfd__h547894[53] ?
((_theResult___fst_exp__h547802 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h557510) :
((_theResult___fst_exp__h547802 == 11'd0 &&
sfd__h547894[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h547802) ;
assign _theResult___exp__h557315 =
sfd__h556654[53] ?
((_theResult___fst_exp__h556635 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h557536) :
((_theResult___fst_exp__h556635 == 11'd0 &&
sfd__h556654[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h556635) ;
assign _theResult___exp__h578184 =
sfd__h577547[53] ?
((_theResult___fst_exp__h577529 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h596779) :
((_theResult___fst_exp__h577529 == 11'd0 &&
sfd__h577547[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h577529) ;
assign _theResult___exp__h587835 =
sfd__h587198[53] ?
((_theResult___fst_exp__h587106 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h596814) :
((_theResult___fst_exp__h587106 == 11'd0 &&
sfd__h587198[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h587106) ;
assign _theResult___exp__h596619 =
sfd__h595958[53] ?
((_theResult___fst_exp__h595939 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h596840) :
((_theResult___fst_exp__h595939 == 11'd0 &&
sfd__h595958[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h595939) ;
assign _theResult___fst__h601214 =
a__h600792[63] ? a___1__h601219 : a__h600792 ;
assign _theResult___fst_exp__h352040 =
_theResult____h343929[56] ?
8'd2 :
_theResult___fst_exp__h352114 ;
assign _theResult___fst_exp__h352105 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 } ;
assign _theResult___fst_exp__h352111 =
(!_theResult____h343929[56] && !_theResult____h343929[55] &&
!_theResult____h343929[54] &&
!_theResult____h343929[53] &&
!_theResult____h343929[52] &&
!_theResult____h343929[51] &&
!_theResult____h343929[50] &&
!_theResult____h343929[49] &&
!_theResult____h343929[48] &&
!_theResult____h343929[47] &&
!_theResult____h343929[46] &&
!_theResult____h343929[45] &&
!_theResult____h343929[44] &&
!_theResult____h343929[43] &&
!_theResult____h343929[42] &&
!_theResult____h343929[41] &&
!_theResult____h343929[40] &&
!_theResult____h343929[39] &&
!_theResult____h343929[38] &&
!_theResult____h343929[37] &&
!_theResult____h343929[36] &&
!_theResult____h343929[35] &&
!_theResult____h343929[34] &&
!_theResult____h343929[33] &&
!_theResult____h343929[32] &&
!_theResult____h343929[31] &&
!_theResult____h343929[30] &&
!_theResult____h343929[29] &&
!_theResult____h343929[28] &&
!_theResult____h343929[27] &&
!_theResult____h343929[26] &&
!_theResult____h343929[25] &&
!_theResult____h343929[24] &&
!_theResult____h343929[23] &&
!_theResult____h343929[22] &&
!_theResult____h343929[21] &&
!_theResult____h343929[20] &&
!_theResult____h343929[19] &&
!_theResult____h343929[18] &&
!_theResult____h343929[17] &&
!_theResult____h343929[16] &&
!_theResult____h343929[15] &&
!_theResult____h343929[14] &&
!_theResult____h343929[13] &&
!_theResult____h343929[12] &&
!_theResult____h343929[11] &&
!_theResult____h343929[10] &&
!_theResult____h343929[9] &&
!_theResult____h343929[8] &&
!_theResult____h343929[7] &&
!_theResult____h343929[6] &&
!_theResult____h343929[5] &&
!_theResult____h343929[4] &&
!_theResult____h343929[3] &&
!_theResult____h343929[2] &&
!_theResult____h343929[1] &&
!_theResult____h343929[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d4245) ?
8'd0 :
_theResult___fst_exp__h352105 ;
assign _theResult___fst_exp__h352114 =
(!_theResult____h343929[56] && _theResult____h343929[55]) ?
8'd1 :
_theResult___fst_exp__h352111 ;
assign _theResult___fst_exp__h352637 =
(_theResult___fst_exp__h352040 == 8'd255) ?
_theResult___fst_exp__h352040 :
_theResult___fst_exp__h352634 ;
assign _theResult___fst_exp__h360687 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ;
assign _theResult___fst_exp__h360693 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4476) ?
8'd0 :
_theResult___fst_exp__h360687 ;
assign _theResult___fst_exp__h360696 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h360693 :
8'd129 ;
assign _theResult___fst_exp__h361219 =
(_theResult___fst_exp__h360696 == 8'd255) ?
_theResult___fst_exp__h360696 :
_theResult___fst_exp__h361216 ;
assign _theResult___fst_exp__h369806 =
_theResult____h361568[56] ?
8'd2 :
_theResult___fst_exp__h369880 ;
assign _theResult___fst_exp__h369871 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 } ;
assign _theResult___fst_exp__h369877 =
(!_theResult____h361568[56] && !_theResult____h361568[55] &&
!_theResult____h361568[54] &&
!_theResult____h361568[53] &&
!_theResult____h361568[52] &&
!_theResult____h361568[51] &&
!_theResult____h361568[50] &&
!_theResult____h361568[49] &&
!_theResult____h361568[48] &&
!_theResult____h361568[47] &&
!_theResult____h361568[46] &&
!_theResult____h361568[45] &&
!_theResult____h361568[44] &&
!_theResult____h361568[43] &&
!_theResult____h361568[42] &&
!_theResult____h361568[41] &&
!_theResult____h361568[40] &&
!_theResult____h361568[39] &&
!_theResult____h361568[38] &&
!_theResult____h361568[37] &&
!_theResult____h361568[36] &&
!_theResult____h361568[35] &&
!_theResult____h361568[34] &&
!_theResult____h361568[33] &&
!_theResult____h361568[32] &&
!_theResult____h361568[31] &&
!_theResult____h361568[30] &&
!_theResult____h361568[29] &&
!_theResult____h361568[28] &&
!_theResult____h361568[27] &&
!_theResult____h361568[26] &&
!_theResult____h361568[25] &&
!_theResult____h361568[24] &&
!_theResult____h361568[23] &&
!_theResult____h361568[22] &&
!_theResult____h361568[21] &&
!_theResult____h361568[20] &&
!_theResult____h361568[19] &&
!_theResult____h361568[18] &&
!_theResult____h361568[17] &&
!_theResult____h361568[16] &&
!_theResult____h361568[15] &&
!_theResult____h361568[14] &&
!_theResult____h361568[13] &&
!_theResult____h361568[12] &&
!_theResult____h361568[11] &&
!_theResult____h361568[10] &&
!_theResult____h361568[9] &&
!_theResult____h361568[8] &&
!_theResult____h361568[7] &&
!_theResult____h361568[6] &&
!_theResult____h361568[5] &&
!_theResult____h361568[4] &&
!_theResult____h361568[3] &&
!_theResult____h361568[2] &&
!_theResult____h361568[1] &&
!_theResult____h361568[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d4796) ?
8'd0 :
_theResult___fst_exp__h369871 ;
assign _theResult___fst_exp__h369880 =
(!_theResult____h361568[56] && _theResult____h361568[55]) ?
8'd1 :
_theResult___fst_exp__h369877 ;
assign _theResult___fst_exp__h370403 =
(_theResult___fst_exp__h369806 == 8'd255) ?
_theResult___fst_exp__h369806 :
_theResult___fst_exp__h370400 ;
assign _theResult___fst_exp__h378443 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] ;
assign _theResult___fst_exp__h378482 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC__q37[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 } ;
assign _theResult___fst_exp__h378488 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d4869) ?
8'd0 :
_theResult___fst_exp__h378482 ;
assign _theResult___fst_exp__h378491 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h378488 :
_theResult___fst_exp__h378443 ;
assign _theResult___fst_exp__h379039 =
(_theResult___fst_exp__h378491 == 8'd255) ?
_theResult___fst_exp__h378491 :
_theResult___fst_exp__h379036 ;
assign _theResult___fst_exp__h379048 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
_theResult___snd_fst_exp__h361222 :
_theResult___fst_exp__h343911) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
_theResult___snd_fst_exp__h379042 :
_theResult___fst_exp__h343911) ;
assign _theResult___fst_exp__h379051 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h379048 ;
assign _theResult___fst_exp__h397737 =
_theResult____h389628[56] ?
8'd2 :
_theResult___fst_exp__h397811 ;
assign _theResult___fst_exp__h397802 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 } ;
assign _theResult___fst_exp__h397808 =
(!_theResult____h389628[56] && !_theResult____h389628[55] &&
!_theResult____h389628[54] &&
!_theResult____h389628[53] &&
!_theResult____h389628[52] &&
!_theResult____h389628[51] &&
!_theResult____h389628[50] &&
!_theResult____h389628[49] &&
!_theResult____h389628[48] &&
!_theResult____h389628[47] &&
!_theResult____h389628[46] &&
!_theResult____h389628[45] &&
!_theResult____h389628[44] &&
!_theResult____h389628[43] &&
!_theResult____h389628[42] &&
!_theResult____h389628[41] &&
!_theResult____h389628[40] &&
!_theResult____h389628[39] &&
!_theResult____h389628[38] &&
!_theResult____h389628[37] &&
!_theResult____h389628[36] &&
!_theResult____h389628[35] &&
!_theResult____h389628[34] &&
!_theResult____h389628[33] &&
!_theResult____h389628[32] &&
!_theResult____h389628[31] &&
!_theResult____h389628[30] &&
!_theResult____h389628[29] &&
!_theResult____h389628[28] &&
!_theResult____h389628[27] &&
!_theResult____h389628[26] &&
!_theResult____h389628[25] &&
!_theResult____h389628[24] &&
!_theResult____h389628[23] &&
!_theResult____h389628[22] &&
!_theResult____h389628[21] &&
!_theResult____h389628[20] &&
!_theResult____h389628[19] &&
!_theResult____h389628[18] &&
!_theResult____h389628[17] &&
!_theResult____h389628[16] &&
!_theResult____h389628[15] &&
!_theResult____h389628[14] &&
!_theResult____h389628[13] &&
!_theResult____h389628[12] &&
!_theResult____h389628[11] &&
!_theResult____h389628[10] &&
!_theResult____h389628[9] &&
!_theResult____h389628[8] &&
!_theResult____h389628[7] &&
!_theResult____h389628[6] &&
!_theResult____h389628[5] &&
!_theResult____h389628[4] &&
!_theResult____h389628[3] &&
!_theResult____h389628[2] &&
!_theResult____h389628[1] &&
!_theResult____h389628[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d5637) ?
8'd0 :
_theResult___fst_exp__h397802 ;
assign _theResult___fst_exp__h397811 =
(!_theResult____h389628[56] && _theResult____h389628[55]) ?
8'd1 :
_theResult___fst_exp__h397808 ;
assign _theResult___fst_exp__h398334 =
(_theResult___fst_exp__h397737 == 8'd255) ?
_theResult___fst_exp__h397737 :
_theResult___fst_exp__h398331 ;
assign _theResult___fst_exp__h406384 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ;
assign _theResult___fst_exp__h406390 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d5868) ?
8'd0 :
_theResult___fst_exp__h406384 ;
assign _theResult___fst_exp__h406393 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h406390 :
8'd129 ;
assign _theResult___fst_exp__h406916 =
(_theResult___fst_exp__h406393 == 8'd255) ?
_theResult___fst_exp__h406393 :
_theResult___fst_exp__h406913 ;
assign _theResult___fst_exp__h415503 =
_theResult____h407265[56] ?
8'd2 :
_theResult___fst_exp__h415577 ;
assign _theResult___fst_exp__h415568 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 } ;
assign _theResult___fst_exp__h415574 =
(!_theResult____h407265[56] && !_theResult____h407265[55] &&
!_theResult____h407265[54] &&
!_theResult____h407265[53] &&
!_theResult____h407265[52] &&
!_theResult____h407265[51] &&
!_theResult____h407265[50] &&
!_theResult____h407265[49] &&
!_theResult____h407265[48] &&
!_theResult____h407265[47] &&
!_theResult____h407265[46] &&
!_theResult____h407265[45] &&
!_theResult____h407265[44] &&
!_theResult____h407265[43] &&
!_theResult____h407265[42] &&
!_theResult____h407265[41] &&
!_theResult____h407265[40] &&
!_theResult____h407265[39] &&
!_theResult____h407265[38] &&
!_theResult____h407265[37] &&
!_theResult____h407265[36] &&
!_theResult____h407265[35] &&
!_theResult____h407265[34] &&
!_theResult____h407265[33] &&
!_theResult____h407265[32] &&
!_theResult____h407265[31] &&
!_theResult____h407265[30] &&
!_theResult____h407265[29] &&
!_theResult____h407265[28] &&
!_theResult____h407265[27] &&
!_theResult____h407265[26] &&
!_theResult____h407265[25] &&
!_theResult____h407265[24] &&
!_theResult____h407265[23] &&
!_theResult____h407265[22] &&
!_theResult____h407265[21] &&
!_theResult____h407265[20] &&
!_theResult____h407265[19] &&
!_theResult____h407265[18] &&
!_theResult____h407265[17] &&
!_theResult____h407265[16] &&
!_theResult____h407265[15] &&
!_theResult____h407265[14] &&
!_theResult____h407265[13] &&
!_theResult____h407265[12] &&
!_theResult____h407265[11] &&
!_theResult____h407265[10] &&
!_theResult____h407265[9] &&
!_theResult____h407265[8] &&
!_theResult____h407265[7] &&
!_theResult____h407265[6] &&
!_theResult____h407265[5] &&
!_theResult____h407265[4] &&
!_theResult____h407265[3] &&
!_theResult____h407265[2] &&
!_theResult____h407265[1] &&
!_theResult____h407265[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d6188) ?
8'd0 :
_theResult___fst_exp__h415568 ;
assign _theResult___fst_exp__h415577 =
(!_theResult____h407265[56] && _theResult____h407265[55]) ?
8'd1 :
_theResult___fst_exp__h415574 ;
assign _theResult___fst_exp__h416100 =
(_theResult___fst_exp__h415503 == 8'd255) ?
_theResult___fst_exp__h415503 :
_theResult___fst_exp__h416097 ;
assign _theResult___fst_exp__h424140 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] ;
assign _theResult___fst_exp__h424179 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC__q72[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 } ;
assign _theResult___fst_exp__h424185 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d6261) ?
8'd0 :
_theResult___fst_exp__h424179 ;
assign _theResult___fst_exp__h424188 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h424185 :
_theResult___fst_exp__h424140 ;
assign _theResult___fst_exp__h424736 =
(_theResult___fst_exp__h424188 == 8'd255) ?
_theResult___fst_exp__h424188 :
_theResult___fst_exp__h424733 ;
assign _theResult___fst_exp__h424745 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
_theResult___snd_fst_exp__h406919 :
_theResult___fst_exp__h389610) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
_theResult___snd_fst_exp__h424739 :
_theResult___fst_exp__h389610) ;
assign _theResult___fst_exp__h424748 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h424745 ;
assign _theResult___fst_exp__h443432 =
_theResult____h435323[56] ?
8'd2 :
_theResult___fst_exp__h443506 ;
assign _theResult___fst_exp__h443497 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 } ;
assign _theResult___fst_exp__h443503 =
(!_theResult____h435323[56] && !_theResult____h435323[55] &&
!_theResult____h435323[54] &&
!_theResult____h435323[53] &&
!_theResult____h435323[52] &&
!_theResult____h435323[51] &&
!_theResult____h435323[50] &&
!_theResult____h435323[49] &&
!_theResult____h435323[48] &&
!_theResult____h435323[47] &&
!_theResult____h435323[46] &&
!_theResult____h435323[45] &&
!_theResult____h435323[44] &&
!_theResult____h435323[43] &&
!_theResult____h435323[42] &&
!_theResult____h435323[41] &&
!_theResult____h435323[40] &&
!_theResult____h435323[39] &&
!_theResult____h435323[38] &&
!_theResult____h435323[37] &&
!_theResult____h435323[36] &&
!_theResult____h435323[35] &&
!_theResult____h435323[34] &&
!_theResult____h435323[33] &&
!_theResult____h435323[32] &&
!_theResult____h435323[31] &&
!_theResult____h435323[30] &&
!_theResult____h435323[29] &&
!_theResult____h435323[28] &&
!_theResult____h435323[27] &&
!_theResult____h435323[26] &&
!_theResult____h435323[25] &&
!_theResult____h435323[24] &&
!_theResult____h435323[23] &&
!_theResult____h435323[22] &&
!_theResult____h435323[21] &&
!_theResult____h435323[20] &&
!_theResult____h435323[19] &&
!_theResult____h435323[18] &&
!_theResult____h435323[17] &&
!_theResult____h435323[16] &&
!_theResult____h435323[15] &&
!_theResult____h435323[14] &&
!_theResult____h435323[13] &&
!_theResult____h435323[12] &&
!_theResult____h435323[11] &&
!_theResult____h435323[10] &&
!_theResult____h435323[9] &&
!_theResult____h435323[8] &&
!_theResult____h435323[7] &&
!_theResult____h435323[6] &&
!_theResult____h435323[5] &&
!_theResult____h435323[4] &&
!_theResult____h435323[3] &&
!_theResult____h435323[2] &&
!_theResult____h435323[1] &&
!_theResult____h435323[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDi_ETC___d7029) ?
8'd0 :
_theResult___fst_exp__h443497 ;
assign _theResult___fst_exp__h443506 =
(!_theResult____h435323[56] && _theResult____h435323[55]) ?
8'd1 :
_theResult___fst_exp__h443503 ;
assign _theResult___fst_exp__h444029 =
(_theResult___fst_exp__h443432 == 8'd255) ?
_theResult___fst_exp__h443432 :
_theResult___fst_exp__h444026 ;
assign _theResult___fst_exp__h452079 =
8'd129 -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ;
assign _theResult___fst_exp__h452085 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7260) ?
8'd0 :
_theResult___fst_exp__h452079 ;
assign _theResult___fst_exp__h452088 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h452085 :
8'd129 ;
assign _theResult___fst_exp__h452611 =
(_theResult___fst_exp__h452088 == 8'd255) ?
_theResult___fst_exp__h452088 :
_theResult___fst_exp__h452608 ;
assign _theResult___fst_exp__h461198 =
_theResult____h452960[56] ?
8'd2 :
_theResult___fst_exp__h461272 ;
assign _theResult___fst_exp__h461263 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 } ;
assign _theResult___fst_exp__h461269 =
(!_theResult____h452960[56] && !_theResult____h452960[55] &&
!_theResult____h452960[54] &&
!_theResult____h452960[53] &&
!_theResult____h452960[52] &&
!_theResult____h452960[51] &&
!_theResult____h452960[50] &&
!_theResult____h452960[49] &&
!_theResult____h452960[48] &&
!_theResult____h452960[47] &&
!_theResult____h452960[46] &&
!_theResult____h452960[45] &&
!_theResult____h452960[44] &&
!_theResult____h452960[43] &&
!_theResult____h452960[42] &&
!_theResult____h452960[41] &&
!_theResult____h452960[40] &&
!_theResult____h452960[39] &&
!_theResult____h452960[38] &&
!_theResult____h452960[37] &&
!_theResult____h452960[36] &&
!_theResult____h452960[35] &&
!_theResult____h452960[34] &&
!_theResult____h452960[33] &&
!_theResult____h452960[32] &&
!_theResult____h452960[31] &&
!_theResult____h452960[30] &&
!_theResult____h452960[29] &&
!_theResult____h452960[28] &&
!_theResult____h452960[27] &&
!_theResult____h452960[26] &&
!_theResult____h452960[25] &&
!_theResult____h452960[24] &&
!_theResult____h452960[23] &&
!_theResult____h452960[22] &&
!_theResult____h452960[21] &&
!_theResult____h452960[20] &&
!_theResult____h452960[19] &&
!_theResult____h452960[18] &&
!_theResult____h452960[17] &&
!_theResult____h452960[16] &&
!_theResult____h452960[15] &&
!_theResult____h452960[14] &&
!_theResult____h452960[13] &&
!_theResult____h452960[12] &&
!_theResult____h452960[11] &&
!_theResult____h452960[10] &&
!_theResult____h452960[9] &&
!_theResult____h452960[8] &&
!_theResult____h452960[7] &&
!_theResult____h452960[6] &&
!_theResult____h452960[5] &&
!_theResult____h452960[4] &&
!_theResult____h452960[3] &&
!_theResult____h452960[2] &&
!_theResult____h452960[1] &&
!_theResult____h452960[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulD_ETC___d7580) ?
8'd0 :
_theResult___fst_exp__h461263 ;
assign _theResult___fst_exp__h461272 =
(!_theResult____h452960[56] && _theResult____h452960[55]) ?
8'd1 :
_theResult___fst_exp__h461269 ;
assign _theResult___fst_exp__h461795 =
(_theResult___fst_exp__h461198 == 8'd255) ?
_theResult___fst_exp__h461198 :
_theResult___fst_exp__h461792 ;
assign _theResult___fst_exp__h469835 =
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ==
8'd0) ?
8'd1 :
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] ;
assign _theResult___fst_exp__h469874 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC__q107[7:0] -
{ 2'd0,
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 } ;
assign _theResult___fst_exp__h469880 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203 ||
!_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec_dou_ETC___d7653) ?
8'd0 :
_theResult___fst_exp__h469874 ;
assign _theResult___fst_exp__h469883 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___fst_exp__h469880 :
_theResult___fst_exp__h469835 ;
assign _theResult___fst_exp__h470431 =
(_theResult___fst_exp__h469883 == 8'd255) ?
_theResult___fst_exp__h469883 :
_theResult___fst_exp__h470428 ;
assign _theResult___fst_exp__h470440 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
_theResult___snd_fst_exp__h452614 :
_theResult___fst_exp__h435305) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
_theResult___snd_fst_exp__h470434 :
_theResult___fst_exp__h435305) ;
assign _theResult___fst_exp__h470443 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
8'd0 :
_theResult___fst_exp__h470440 ;
assign _theResult___fst_exp__h484299 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 ;
assign _theResult___fst_exp__h499363 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ;
assign _theResult___fst_exp__h499369 =
(f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8582) ?
11'd0 :
_theResult___fst_exp__h499363 ;
assign _theResult___fst_exp__h499372 =
(f1_exp__h479984 == 8'd0) ?
_theResult___fst_exp__h499369 :
11'd897 ;
assign _theResult___fst_exp__h500127 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 ;
assign _theResult___fst_exp__h500130 =
(_theResult___fst_exp__h499372 == 11'd2047) ?
_theResult___fst_exp__h499372 :
_theResult___fst_exp__h500127 ;
assign _theResult___fst_exp__h508949 =
_theResult____h500713[56] ?
11'd2 :
_theResult___fst_exp__h509023 ;
assign _theResult___fst_exp__h509014 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 } ;
assign _theResult___fst_exp__h509020 =
(!_theResult____h500713[56] && !_theResult____h500713[55] &&
!_theResult____h500713[54] &&
!_theResult____h500713[53] &&
!_theResult____h500713[52] &&
!_theResult____h500713[51] &&
!_theResult____h500713[50] &&
!_theResult____h500713[49] &&
!_theResult____h500713[48] &&
!_theResult____h500713[47] &&
!_theResult____h500713[46] &&
!_theResult____h500713[45] &&
!_theResult____h500713[44] &&
!_theResult____h500713[43] &&
!_theResult____h500713[42] &&
!_theResult____h500713[41] &&
!_theResult____h500713[40] &&
!_theResult____h500713[39] &&
!_theResult____h500713[38] &&
!_theResult____h500713[37] &&
!_theResult____h500713[36] &&
!_theResult____h500713[35] &&
!_theResult____h500713[34] &&
!_theResult____h500713[33] &&
!_theResult____h500713[32] &&
!_theResult____h500713[31] &&
!_theResult____h500713[30] &&
!_theResult____h500713[29] &&
!_theResult____h500713[28] &&
!_theResult____h500713[27] &&
!_theResult____h500713[26] &&
!_theResult____h500713[25] &&
!_theResult____h500713[24] &&
!_theResult____h500713[23] &&
!_theResult____h500713[22] &&
!_theResult____h500713[21] &&
!_theResult____h500713[20] &&
!_theResult____h500713[19] &&
!_theResult____h500713[18] &&
!_theResult____h500713[17] &&
!_theResult____h500713[16] &&
!_theResult____h500713[15] &&
!_theResult____h500713[14] &&
!_theResult____h500713[13] &&
!_theResult____h500713[12] &&
!_theResult____h500713[11] &&
!_theResult____h500713[10] &&
!_theResult____h500713[9] &&
!_theResult____h500713[8] &&
!_theResult____h500713[7] &&
!_theResult____h500713[6] &&
!_theResult____h500713[5] &&
!_theResult____h500713[4] &&
!_theResult____h500713[3] &&
!_theResult____h500713[2] &&
!_theResult____h500713[1] &&
!_theResult____h500713[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d8894) ?
11'd0 :
_theResult___fst_exp__h509014 ;
assign _theResult___fst_exp__h509023 =
(!_theResult____h500713[56] && _theResult____h500713[55]) ?
11'd1 :
_theResult___fst_exp__h509020 ;
assign _theResult___fst_exp__h509778 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 ;
assign _theResult___fst_exp__h509781 =
(_theResult___fst_exp__h508949 == 11'd2047) ?
_theResult___fst_exp__h508949 :
_theResult___fst_exp__h509778 ;
assign _theResult___fst_exp__h517734 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] ;
assign _theResult___fst_exp__h517773 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q137[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 } ;
assign _theResult___fst_exp__h517779 =
(f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d8944) ?
11'd0 :
_theResult___fst_exp__h517773 ;
assign _theResult___fst_exp__h517782 =
(f1_exp__h479984 == 8'd0) ?
_theResult___fst_exp__h517779 :
_theResult___fst_exp__h517734 ;
assign _theResult___fst_exp__h518562 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 ;
assign _theResult___fst_exp__h518565 =
(_theResult___fst_exp__h517782 == 11'd2047) ?
_theResult___fst_exp__h517782 :
_theResult___fst_exp__h518562 ;
assign _theResult___fst_exp__h518574 =
(f1_exp__h479984 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ?
_theResult___snd_fst_exp__h500133 :
_theResult___fst_exp__h484299) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ?
_theResult___snd_fst_exp__h518568 :
_theResult___fst_exp__h484299) ;
assign _theResult___fst_exp__h518577 =
(f1_exp__h479984 == 8'd0 && f1_sfd__h479985 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h518574 ;
assign _theResult___fst_exp__h523152 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 ;
assign _theResult___fst_exp__h538216 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ;
assign _theResult___fst_exp__h538222 =
(f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10082) ?
11'd0 :
_theResult___fst_exp__h538216 ;
assign _theResult___fst_exp__h538225 =
(f2_exp__h518978 == 8'd0) ?
_theResult___fst_exp__h538222 :
11'd897 ;
assign _theResult___fst_exp__h538980 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 ;
assign _theResult___fst_exp__h538983 =
(_theResult___fst_exp__h538225 == 11'd2047) ?
_theResult___fst_exp__h538225 :
_theResult___fst_exp__h538980 ;
assign _theResult___fst_exp__h547802 =
_theResult____h539566[56] ?
11'd2 :
_theResult___fst_exp__h547876 ;
assign _theResult___fst_exp__h547867 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 } ;
assign _theResult___fst_exp__h547873 =
(!_theResult____h539566[56] && !_theResult____h539566[55] &&
!_theResult____h539566[54] &&
!_theResult____h539566[53] &&
!_theResult____h539566[52] &&
!_theResult____h539566[51] &&
!_theResult____h539566[50] &&
!_theResult____h539566[49] &&
!_theResult____h539566[48] &&
!_theResult____h539566[47] &&
!_theResult____h539566[46] &&
!_theResult____h539566[45] &&
!_theResult____h539566[44] &&
!_theResult____h539566[43] &&
!_theResult____h539566[42] &&
!_theResult____h539566[41] &&
!_theResult____h539566[40] &&
!_theResult____h539566[39] &&
!_theResult____h539566[38] &&
!_theResult____h539566[37] &&
!_theResult____h539566[36] &&
!_theResult____h539566[35] &&
!_theResult____h539566[34] &&
!_theResult____h539566[33] &&
!_theResult____h539566[32] &&
!_theResult____h539566[31] &&
!_theResult____h539566[30] &&
!_theResult____h539566[29] &&
!_theResult____h539566[28] &&
!_theResult____h539566[27] &&
!_theResult____h539566[26] &&
!_theResult____h539566[25] &&
!_theResult____h539566[24] &&
!_theResult____h539566[23] &&
!_theResult____h539566[22] &&
!_theResult____h539566[21] &&
!_theResult____h539566[20] &&
!_theResult____h539566[19] &&
!_theResult____h539566[18] &&
!_theResult____h539566[17] &&
!_theResult____h539566[16] &&
!_theResult____h539566[15] &&
!_theResult____h539566[14] &&
!_theResult____h539566[13] &&
!_theResult____h539566[12] &&
!_theResult____h539566[11] &&
!_theResult____h539566[10] &&
!_theResult____h539566[9] &&
!_theResult____h539566[8] &&
!_theResult____h539566[7] &&
!_theResult____h539566[6] &&
!_theResult____h539566[5] &&
!_theResult____h539566[4] &&
!_theResult____h539566[3] &&
!_theResult____h539566[2] &&
!_theResult____h539566[1] &&
!_theResult____h539566[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d10379) ?
11'd0 :
_theResult___fst_exp__h547867 ;
assign _theResult___fst_exp__h547876 =
(!_theResult____h539566[56] && _theResult____h539566[55]) ?
11'd1 :
_theResult___fst_exp__h547873 ;
assign _theResult___fst_exp__h548631 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 ;
assign _theResult___fst_exp__h548634 =
(_theResult___fst_exp__h547802 == 11'd2047) ?
_theResult___fst_exp__h547802 :
_theResult___fst_exp__h548631 ;
assign _theResult___fst_exp__h556587 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] ;
assign _theResult___fst_exp__h556626 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q177[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 } ;
assign _theResult___fst_exp__h556632 =
(f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d10429) ?
11'd0 :
_theResult___fst_exp__h556626 ;
assign _theResult___fst_exp__h556635 =
(f2_exp__h518978 == 8'd0) ?
_theResult___fst_exp__h556632 :
_theResult___fst_exp__h556587 ;
assign _theResult___fst_exp__h557415 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 ;
assign _theResult___fst_exp__h557418 =
(_theResult___fst_exp__h556635 == 11'd2047) ?
_theResult___fst_exp__h556635 :
_theResult___fst_exp__h557415 ;
assign _theResult___fst_exp__h557427 =
(f2_exp__h518978 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ?
_theResult___snd_fst_exp__h538986 :
_theResult___fst_exp__h523152) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ?
_theResult___snd_fst_exp__h557421 :
_theResult___fst_exp__h523152) ;
assign _theResult___fst_exp__h557430 =
(f2_exp__h518978 == 8'd0 && f2_sfd__h518979 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h557427 ;
assign _theResult___fst_exp__h562456 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
11'd2047 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 ;
assign _theResult___fst_exp__h577520 =
11'd897 -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ;
assign _theResult___fst_exp__h577526 =
(f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9312) ?
11'd0 :
_theResult___fst_exp__h577520 ;
assign _theResult___fst_exp__h577529 =
(f3_exp__h558282 == 8'd0) ?
_theResult___fst_exp__h577526 :
11'd897 ;
assign _theResult___fst_exp__h578284 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 ;
assign _theResult___fst_exp__h578287 =
(_theResult___fst_exp__h577529 == 11'd2047) ?
_theResult___fst_exp__h577529 :
_theResult___fst_exp__h578284 ;
assign _theResult___fst_exp__h587106 =
_theResult____h578870[56] ?
11'd2 :
_theResult___fst_exp__h587180 ;
assign _theResult___fst_exp__h587171 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 } ;
assign _theResult___fst_exp__h587177 =
(!_theResult____h578870[56] && !_theResult____h578870[55] &&
!_theResult____h578870[54] &&
!_theResult____h578870[53] &&
!_theResult____h578870[52] &&
!_theResult____h578870[51] &&
!_theResult____h578870[50] &&
!_theResult____h578870[49] &&
!_theResult____h578870[48] &&
!_theResult____h578870[47] &&
!_theResult____h578870[46] &&
!_theResult____h578870[45] &&
!_theResult____h578870[44] &&
!_theResult____h578870[43] &&
!_theResult____h578870[42] &&
!_theResult____h578870[41] &&
!_theResult____h578870[40] &&
!_theResult____h578870[39] &&
!_theResult____h578870[38] &&
!_theResult____h578870[37] &&
!_theResult____h578870[36] &&
!_theResult____h578870[35] &&
!_theResult____h578870[34] &&
!_theResult____h578870[33] &&
!_theResult____h578870[32] &&
!_theResult____h578870[31] &&
!_theResult____h578870[30] &&
!_theResult____h578870[29] &&
!_theResult____h578870[28] &&
!_theResult____h578870[27] &&
!_theResult____h578870[26] &&
!_theResult____h578870[25] &&
!_theResult____h578870[24] &&
!_theResult____h578870[23] &&
!_theResult____h578870[22] &&
!_theResult____h578870[21] &&
!_theResult____h578870[20] &&
!_theResult____h578870[19] &&
!_theResult____h578870[18] &&
!_theResult____h578870[17] &&
!_theResult____h578870[16] &&
!_theResult____h578870[15] &&
!_theResult____h578870[14] &&
!_theResult____h578870[13] &&
!_theResult____h578870[12] &&
!_theResult____h578870[11] &&
!_theResult____h578870[10] &&
!_theResult____h578870[9] &&
!_theResult____h578870[8] &&
!_theResult____h578870[7] &&
!_theResult____h578870[6] &&
!_theResult____h578870[5] &&
!_theResult____h578870[4] &&
!_theResult____h578870[3] &&
!_theResult____h578870[2] &&
!_theResult____h578870[1] &&
!_theResult____h578870[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuM_ETC___d9609) ?
11'd0 :
_theResult___fst_exp__h587171 ;
assign _theResult___fst_exp__h587180 =
(!_theResult____h578870[56] && _theResult____h578870[55]) ?
11'd1 :
_theResult___fst_exp__h587177 ;
assign _theResult___fst_exp__h587935 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 ;
assign _theResult___fst_exp__h587938 =
(_theResult___fst_exp__h587106 == 11'd2047) ?
_theResult___fst_exp__h587106 :
_theResult___fst_exp__h587935 ;
assign _theResult___fst_exp__h595891 =
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] ;
assign _theResult___fst_exp__h595930 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC__q154[10:0] -
{ 5'd0,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 } ;
assign _theResult___fst_exp__h595936 =
(f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283 ||
!_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regToExe_ETC___d9659) ?
11'd0 :
_theResult___fst_exp__h595930 ;
assign _theResult___fst_exp__h595939 =
(f3_exp__h558282 == 8'd0) ?
_theResult___fst_exp__h595936 :
_theResult___fst_exp__h595891 ;
assign _theResult___fst_exp__h596719 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 ;
assign _theResult___fst_exp__h596722 =
(_theResult___fst_exp__h595939 == 11'd2047) ?
_theResult___fst_exp__h595939 :
_theResult___fst_exp__h596719 ;
assign _theResult___fst_exp__h596731 =
(f3_exp__h558282 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ?
_theResult___snd_fst_exp__h578290 :
_theResult___fst_exp__h562456) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ?
_theResult___snd_fst_exp__h596725 :
_theResult___fst_exp__h562456) ;
assign _theResult___fst_exp__h596734 =
(f3_exp__h558282 == 8'd0 && f3_sfd__h558283 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h596731 ;
assign _theResult___fst_sfd__h352638 =
(_theResult___fst_exp__h352040 == 8'd255) ?
sfdin__h352034[56:34] :
_theResult___fst_sfd__h352635 ;
assign _theResult___fst_sfd__h361220 =
(_theResult___fst_exp__h360696 == 8'd255) ?
_theResult___snd__h360647[56:34] :
_theResult___fst_sfd__h361217 ;
assign _theResult___fst_sfd__h370404 =
(_theResult___fst_exp__h369806 == 8'd255) ?
sfdin__h369800[56:34] :
_theResult___fst_sfd__h370401 ;
assign _theResult___fst_sfd__h379040 =
(_theResult___fst_exp__h378491 == 8'd255) ?
_theResult___snd__h378437[56:34] :
_theResult___fst_sfd__h379037 ;
assign _theResult___fst_sfd__h379049 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4008 ?
_theResult___snd_fst_sfd__h361223 :
_theResult___fst_sfd__h343912) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4548 ?
_theResult___snd_fst_sfd__h379043 :
_theResult___fst_sfd__h343912) ;
assign _theResult___fst_sfd__h379055 =
((coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h379049 ;
assign _theResult___fst_sfd__h398335 =
(_theResult___fst_exp__h397737 == 8'd255) ?
sfdin__h397731[56:34] :
_theResult___fst_sfd__h398332 ;
assign _theResult___fst_sfd__h406917 =
(_theResult___fst_exp__h406393 == 8'd255) ?
_theResult___snd__h406344[56:34] :
_theResult___fst_sfd__h406914 ;
assign _theResult___fst_sfd__h416101 =
(_theResult___fst_exp__h415503 == 8'd255) ?
sfdin__h415497[56:34] :
_theResult___fst_sfd__h416098 ;
assign _theResult___fst_sfd__h424737 =
(_theResult___fst_exp__h424188 == 8'd255) ?
_theResult___snd__h424134[56:34] :
_theResult___fst_sfd__h424734 ;
assign _theResult___fst_sfd__h424746 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5400 ?
_theResult___snd_fst_sfd__h406920 :
_theResult___fst_sfd__h389611) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5940 ?
_theResult___snd_fst_sfd__h424740 :
_theResult___fst_sfd__h389611) ;
assign _theResult___fst_sfd__h424752 =
((coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h424746 ;
assign _theResult___fst_sfd__h444030 =
(_theResult___fst_exp__h443432 == 8'd255) ?
sfdin__h443426[56:34] :
_theResult___fst_sfd__h444027 ;
assign _theResult___fst_sfd__h452612 =
(_theResult___fst_exp__h452088 == 8'd255) ?
_theResult___snd__h452039[56:34] :
_theResult___fst_sfd__h452609 ;
assign _theResult___fst_sfd__h461796 =
(_theResult___fst_exp__h461198 == 8'd255) ?
sfdin__h461192[56:34] :
_theResult___fst_sfd__h461793 ;
assign _theResult___fst_sfd__h470432 =
(_theResult___fst_exp__h469883 == 8'd255) ?
_theResult___snd__h469829[56:34] :
_theResult___fst_sfd__h470429 ;
assign _theResult___fst_sfd__h470441 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
(_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6792 ?
_theResult___snd_fst_sfd__h452615 :
_theResult___fst_sfd__h435306) :
(SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7332 ?
_theResult___snd_fst_sfd__h470435 :
_theResult___fst_sfd__h435306) ;
assign _theResult___fst_sfd__h470447 =
((coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) ?
23'd0 :
_theResult___fst_sfd__h470441 ;
assign _theResult___fst_sfd__h484300 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 ;
assign _theResult___fst_sfd__h500128 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 ;
assign _theResult___fst_sfd__h500131 =
(_theResult___fst_exp__h499372 == 11'd2047) ?
_theResult___snd__h499323[56:5] :
_theResult___fst_sfd__h500128 ;
assign _theResult___fst_sfd__h509779 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 ;
assign _theResult___fst_sfd__h509782 =
(_theResult___fst_exp__h508949 == 11'd2047) ?
sfdin__h508943[56:5] :
_theResult___fst_sfd__h509779 ;
assign _theResult___fst_sfd__h518563 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 ;
assign _theResult___fst_sfd__h518566 =
(_theResult___fst_exp__h517782 == 11'd2047) ?
_theResult___snd__h517728[56:5] :
_theResult___fst_sfd__h518563 ;
assign _theResult___fst_sfd__h518575 =
(f1_exp__h479984 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8507 ?
_theResult___snd_fst_sfd__h500134 :
_theResult___fst_sfd__h484300) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8644 ?
_theResult___snd_fst_sfd__h518569 :
_theResult___fst_sfd__h484300) ;
assign _theResult___fst_sfd__h518581 =
((f1_exp__h479984 == 8'd255 || f1_exp__h479984 == 8'd0) &&
f1_sfd__h479985 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h518575 ;
assign _theResult___fst_sfd__h523153 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 ;
assign _theResult___fst_sfd__h538981 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 ;
assign _theResult___fst_sfd__h538984 =
(_theResult___fst_exp__h538225 == 11'd2047) ?
_theResult___snd__h538176[56:5] :
_theResult___fst_sfd__h538981 ;
assign _theResult___fst_sfd__h548632 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 ;
assign _theResult___fst_sfd__h548635 =
(_theResult___fst_exp__h547802 == 11'd2047) ?
sfdin__h547796[56:5] :
_theResult___fst_sfd__h548632 ;
assign _theResult___fst_sfd__h557416 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 ;
assign _theResult___fst_sfd__h557419 =
(_theResult___fst_exp__h556635 == 11'd2047) ?
_theResult___snd__h556581[56:5] :
_theResult___fst_sfd__h557416 ;
assign _theResult___fst_sfd__h557428 =
(f2_exp__h518978 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10007 ?
_theResult___snd_fst_sfd__h538987 :
_theResult___fst_sfd__h523153) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10129 ?
_theResult___snd_fst_sfd__h557422 :
_theResult___fst_sfd__h523153) ;
assign _theResult___fst_sfd__h557434 =
((f2_exp__h518978 == 8'd255 || f2_exp__h518978 == 8'd0) &&
f2_sfd__h518979 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h557428 ;
assign _theResult___fst_sfd__h562457 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3) ?
52'd0 :
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 ;
assign _theResult___fst_sfd__h578285 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 ;
assign _theResult___fst_sfd__h578288 =
(_theResult___fst_exp__h577529 == 11'd2047) ?
_theResult___snd__h577480[56:5] :
_theResult___fst_sfd__h578285 ;
assign _theResult___fst_sfd__h587936 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 ;
assign _theResult___fst_sfd__h587939 =
(_theResult___fst_exp__h587106 == 11'd2047) ?
sfdin__h587100[56:5] :
_theResult___fst_sfd__h587936 ;
assign _theResult___fst_sfd__h596720 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd2 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd3 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd4) ?
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 :
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 ;
assign _theResult___fst_sfd__h596723 =
(_theResult___fst_exp__h595939 == 11'd2047) ?
_theResult___snd__h595885[56:5] :
_theResult___fst_sfd__h596720 ;
assign _theResult___fst_sfd__h596732 =
(f3_exp__h558282 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9237 ?
_theResult___snd_fst_sfd__h578291 :
_theResult___fst_sfd__h562457) :
(SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9359 ?
_theResult___snd_fst_sfd__h596726 :
_theResult___fst_sfd__h562457) ;
assign _theResult___fst_sfd__h596738 =
((f3_exp__h558282 == 8'd255 || f3_exp__h558282 == 8'd0) &&
f3_sfd__h558283 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h596732 ;
assign _theResult___sfd__h352557 =
sfd__h352132[24] ?
((_theResult___fst_exp__h352040 == 8'd254) ?
23'd0 :
sfd__h352132[23:1]) :
sfd__h352132[22:0] ;
assign _theResult___sfd__h361139 =
sfd__h360714[24] ?
((_theResult___fst_exp__h360696 == 8'd254) ?
23'd0 :
sfd__h360714[23:1]) :
sfd__h360714[22:0] ;
assign _theResult___sfd__h370323 =
sfd__h369898[24] ?
((_theResult___fst_exp__h369806 == 8'd254) ?
23'd0 :
sfd__h369898[23:1]) :
sfd__h369898[22:0] ;
assign _theResult___sfd__h378959 =
sfd__h378510[24] ?
((_theResult___fst_exp__h378491 == 8'd254) ?
23'd0 :
sfd__h378510[23:1]) :
sfd__h378510[22:0] ;
assign _theResult___sfd__h379061 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h336274 :
_theResult___fst_sfd__h379055 ;
assign _theResult___sfd__h398254 =
sfd__h397829[24] ?
((_theResult___fst_exp__h397737 == 8'd254) ?
23'd0 :
sfd__h397829[23:1]) :
sfd__h397829[22:0] ;
assign _theResult___sfd__h406836 =
sfd__h406411[24] ?
((_theResult___fst_exp__h406393 == 8'd254) ?
23'd0 :
sfd__h406411[23:1]) :
sfd__h406411[22:0] ;
assign _theResult___sfd__h416020 =
sfd__h415595[24] ?
((_theResult___fst_exp__h415503 == 8'd254) ?
23'd0 :
sfd__h415595[23:1]) :
sfd__h415595[22:0] ;
assign _theResult___sfd__h424656 =
sfd__h424207[24] ?
((_theResult___fst_exp__h424188 == 8'd254) ?
23'd0 :
sfd__h424207[23:1]) :
sfd__h424207[22:0] ;
assign _theResult___sfd__h424758 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h381976 :
_theResult___fst_sfd__h424752 ;
assign _theResult___sfd__h443949 =
sfd__h443524[24] ?
((_theResult___fst_exp__h443432 == 8'd254) ?
23'd0 :
sfd__h443524[23:1]) :
sfd__h443524[22:0] ;
assign _theResult___sfd__h452531 =
sfd__h452106[24] ?
((_theResult___fst_exp__h452088 == 8'd254) ?
23'd0 :
sfd__h452106[23:1]) :
sfd__h452106[22:0] ;
assign _theResult___sfd__h461715 =
sfd__h461290[24] ?
((_theResult___fst_exp__h461198 == 8'd254) ?
23'd0 :
sfd__h461290[23:1]) :
sfd__h461290[22:0] ;
assign _theResult___sfd__h470351 =
sfd__h469902[24] ?
((_theResult___fst_exp__h469883 == 8'd254) ?
23'd0 :
sfd__h469902[23:1]) :
sfd__h469902[22:0] ;
assign _theResult___sfd__h470453 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
_theResult___snd_fst_sfd__h427671 :
_theResult___fst_sfd__h470447 ;
assign _theResult___sfd__h500028 =
sfd__h499390[53] ?
((_theResult___fst_exp__h499372 == 11'd2046) ?
52'd0 :
sfd__h499390[52:1]) :
sfd__h499390[51:0] ;
assign _theResult___sfd__h509679 =
sfd__h509041[53] ?
((_theResult___fst_exp__h508949 == 11'd2046) ?
52'd0 :
sfd__h509041[52:1]) :
sfd__h509041[51:0] ;
assign _theResult___sfd__h518463 =
sfd__h517801[53] ?
((_theResult___fst_exp__h517782 == 11'd2046) ?
52'd0 :
sfd__h517801[52:1]) :
sfd__h517801[51:0] ;
assign _theResult___sfd__h538881 =
sfd__h538243[53] ?
((_theResult___fst_exp__h538225 == 11'd2046) ?
52'd0 :
sfd__h538243[52:1]) :
sfd__h538243[51:0] ;
assign _theResult___sfd__h548532 =
sfd__h547894[53] ?
((_theResult___fst_exp__h547802 == 11'd2046) ?
52'd0 :
sfd__h547894[52:1]) :
sfd__h547894[51:0] ;
assign _theResult___sfd__h557316 =
sfd__h556654[53] ?
((_theResult___fst_exp__h556635 == 11'd2046) ?
52'd0 :
sfd__h556654[52:1]) :
sfd__h556654[51:0] ;
assign _theResult___sfd__h578185 =
sfd__h577547[53] ?
((_theResult___fst_exp__h577529 == 11'd2046) ?
52'd0 :
sfd__h577547[52:1]) :
sfd__h577547[51:0] ;
assign _theResult___sfd__h587836 =
sfd__h587198[53] ?
((_theResult___fst_exp__h587106 == 11'd2046) ?
52'd0 :
sfd__h587198[52:1]) :
sfd__h587198[51:0] ;
assign _theResult___sfd__h596620 =
sfd__h595958[53] ?
((_theResult___fst_exp__h595939 == 11'd2046) ?
52'd0 :
sfd__h595958[52:1]) :
sfd__h595958[51:0] ;
assign _theResult___snd__h352051 = { _theResult____h343929[55:0], 1'd0 } ;
assign _theResult___snd__h352062 =
(!_theResult____h343929[56] && _theResult____h343929[55]) ?
_theResult___snd__h352064 :
_theResult___snd__h352074 ;
assign _theResult___snd__h352064 = { _theResult____h343929[54:0], 2'd0 } ;
assign _theResult___snd__h352074 =
(!_theResult____h343929[56] && !_theResult____h343929[55] &&
!_theResult____h343929[54] &&
!_theResult____h343929[53] &&
!_theResult____h343929[52] &&
!_theResult____h343929[51] &&
!_theResult____h343929[50] &&
!_theResult____h343929[49] &&
!_theResult____h343929[48] &&
!_theResult____h343929[47] &&
!_theResult____h343929[46] &&
!_theResult____h343929[45] &&
!_theResult____h343929[44] &&
!_theResult____h343929[43] &&
!_theResult____h343929[42] &&
!_theResult____h343929[41] &&
!_theResult____h343929[40] &&
!_theResult____h343929[39] &&
!_theResult____h343929[38] &&
!_theResult____h343929[37] &&
!_theResult____h343929[36] &&
!_theResult____h343929[35] &&
!_theResult____h343929[34] &&
!_theResult____h343929[33] &&
!_theResult____h343929[32] &&
!_theResult____h343929[31] &&
!_theResult____h343929[30] &&
!_theResult____h343929[29] &&
!_theResult____h343929[28] &&
!_theResult____h343929[27] &&
!_theResult____h343929[26] &&
!_theResult____h343929[25] &&
!_theResult____h343929[24] &&
!_theResult____h343929[23] &&
!_theResult____h343929[22] &&
!_theResult____h343929[21] &&
!_theResult____h343929[20] &&
!_theResult____h343929[19] &&
!_theResult____h343929[18] &&
!_theResult____h343929[17] &&
!_theResult____h343929[16] &&
!_theResult____h343929[15] &&
!_theResult____h343929[14] &&
!_theResult____h343929[13] &&
!_theResult____h343929[12] &&
!_theResult____h343929[11] &&
!_theResult____h343929[10] &&
!_theResult____h343929[9] &&
!_theResult____h343929[8] &&
!_theResult____h343929[7] &&
!_theResult____h343929[6] &&
!_theResult____h343929[5] &&
!_theResult____h343929[4] &&
!_theResult____h343929[3] &&
!_theResult____h343929[2] &&
!_theResult____h343929[1] &&
!_theResult____h343929[0]) ?
_theResult____h343929 :
_theResult___snd__h352080 ;
assign _theResult___snd__h352080 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q28[54:0],
2'd0 } ;
assign _theResult___snd__h352103 =
_theResult____h343929 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d4243 ;
assign _theResult___snd__h360647 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h360656 :
_theResult___snd__h360649 ;
assign _theResult___snd__h360649 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h360656 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ?
sfd__h336324 :
_theResult___snd__h360662 ;
assign _theResult___snd__h360662 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q30[54:0],
2'd0 } ;
assign _theResult___snd__h360685 =
sfd__h336324 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d4474 ;
assign _theResult___snd__h369817 = { _theResult____h361568[55:0], 1'd0 } ;
assign _theResult___snd__h369828 =
(!_theResult____h361568[56] && _theResult____h361568[55]) ?
_theResult___snd__h369830 :
_theResult___snd__h369840 ;
assign _theResult___snd__h369830 = { _theResult____h361568[54:0], 2'd0 } ;
assign _theResult___snd__h369840 =
(!_theResult____h361568[56] && !_theResult____h361568[55] &&
!_theResult____h361568[54] &&
!_theResult____h361568[53] &&
!_theResult____h361568[52] &&
!_theResult____h361568[51] &&
!_theResult____h361568[50] &&
!_theResult____h361568[49] &&
!_theResult____h361568[48] &&
!_theResult____h361568[47] &&
!_theResult____h361568[46] &&
!_theResult____h361568[45] &&
!_theResult____h361568[44] &&
!_theResult____h361568[43] &&
!_theResult____h361568[42] &&
!_theResult____h361568[41] &&
!_theResult____h361568[40] &&
!_theResult____h361568[39] &&
!_theResult____h361568[38] &&
!_theResult____h361568[37] &&
!_theResult____h361568[36] &&
!_theResult____h361568[35] &&
!_theResult____h361568[34] &&
!_theResult____h361568[33] &&
!_theResult____h361568[32] &&
!_theResult____h361568[31] &&
!_theResult____h361568[30] &&
!_theResult____h361568[29] &&
!_theResult____h361568[28] &&
!_theResult____h361568[27] &&
!_theResult____h361568[26] &&
!_theResult____h361568[25] &&
!_theResult____h361568[24] &&
!_theResult____h361568[23] &&
!_theResult____h361568[22] &&
!_theResult____h361568[21] &&
!_theResult____h361568[20] &&
!_theResult____h361568[19] &&
!_theResult____h361568[18] &&
!_theResult____h361568[17] &&
!_theResult____h361568[16] &&
!_theResult____h361568[15] &&
!_theResult____h361568[14] &&
!_theResult____h361568[13] &&
!_theResult____h361568[12] &&
!_theResult____h361568[11] &&
!_theResult____h361568[10] &&
!_theResult____h361568[9] &&
!_theResult____h361568[8] &&
!_theResult____h361568[7] &&
!_theResult____h361568[6] &&
!_theResult____h361568[5] &&
!_theResult____h361568[4] &&
!_theResult____h361568[3] &&
!_theResult____h361568[2] &&
!_theResult____h361568[1] &&
!_theResult____h361568[0]) ?
_theResult____h361568 :
_theResult___snd__h369846 ;
assign _theResult___snd__h369846 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q38[54:0],
2'd0 } ;
assign _theResult___snd__h369869 =
_theResult____h361568 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d4794 ;
assign _theResult___snd__h378437 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0) ?
_theResult___snd__h378451 :
_theResult___snd__h360649 ;
assign _theResult___snd__h378451 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_fma__ETC___d4419) ?
sfd__h336324 :
_theResult___snd__h378457 ;
assign _theResult___snd__h378457 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q43[54:0],
2'd0 } ;
assign _theResult___snd__h378475 =
sfd__h336324 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d4868) ;
assign _theResult___snd__h397748 = { _theResult____h389628[55:0], 1'd0 } ;
assign _theResult___snd__h397759 =
(!_theResult____h389628[56] && _theResult____h389628[55]) ?
_theResult___snd__h397761 :
_theResult___snd__h397771 ;
assign _theResult___snd__h397761 = { _theResult____h389628[54:0], 2'd0 } ;
assign _theResult___snd__h397771 =
(!_theResult____h389628[56] && !_theResult____h389628[55] &&
!_theResult____h389628[54] &&
!_theResult____h389628[53] &&
!_theResult____h389628[52] &&
!_theResult____h389628[51] &&
!_theResult____h389628[50] &&
!_theResult____h389628[49] &&
!_theResult____h389628[48] &&
!_theResult____h389628[47] &&
!_theResult____h389628[46] &&
!_theResult____h389628[45] &&
!_theResult____h389628[44] &&
!_theResult____h389628[43] &&
!_theResult____h389628[42] &&
!_theResult____h389628[41] &&
!_theResult____h389628[40] &&
!_theResult____h389628[39] &&
!_theResult____h389628[38] &&
!_theResult____h389628[37] &&
!_theResult____h389628[36] &&
!_theResult____h389628[35] &&
!_theResult____h389628[34] &&
!_theResult____h389628[33] &&
!_theResult____h389628[32] &&
!_theResult____h389628[31] &&
!_theResult____h389628[30] &&
!_theResult____h389628[29] &&
!_theResult____h389628[28] &&
!_theResult____h389628[27] &&
!_theResult____h389628[26] &&
!_theResult____h389628[25] &&
!_theResult____h389628[24] &&
!_theResult____h389628[23] &&
!_theResult____h389628[22] &&
!_theResult____h389628[21] &&
!_theResult____h389628[20] &&
!_theResult____h389628[19] &&
!_theResult____h389628[18] &&
!_theResult____h389628[17] &&
!_theResult____h389628[16] &&
!_theResult____h389628[15] &&
!_theResult____h389628[14] &&
!_theResult____h389628[13] &&
!_theResult____h389628[12] &&
!_theResult____h389628[11] &&
!_theResult____h389628[10] &&
!_theResult____h389628[9] &&
!_theResult____h389628[8] &&
!_theResult____h389628[7] &&
!_theResult____h389628[6] &&
!_theResult____h389628[5] &&
!_theResult____h389628[4] &&
!_theResult____h389628[3] &&
!_theResult____h389628[2] &&
!_theResult____h389628[1] &&
!_theResult____h389628[0]) ?
_theResult____h389628 :
_theResult___snd__h397777 ;
assign _theResult___snd__h397777 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q63[54:0],
2'd0 } ;
assign _theResult___snd__h397800 =
_theResult____h389628 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d5635 ;
assign _theResult___snd__h406344 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h406353 :
_theResult___snd__h406346 ;
assign _theResult___snd__h406346 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h406353 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ?
sfd__h382026 :
_theResult___snd__h406359 ;
assign _theResult___snd__h406359 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q65[54:0],
2'd0 } ;
assign _theResult___snd__h406382 =
sfd__h382026 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d5866 ;
assign _theResult___snd__h415514 = { _theResult____h407265[55:0], 1'd0 } ;
assign _theResult___snd__h415525 =
(!_theResult____h407265[56] && _theResult____h407265[55]) ?
_theResult___snd__h415527 :
_theResult___snd__h415537 ;
assign _theResult___snd__h415527 = { _theResult____h407265[54:0], 2'd0 } ;
assign _theResult___snd__h415537 =
(!_theResult____h407265[56] && !_theResult____h407265[55] &&
!_theResult____h407265[54] &&
!_theResult____h407265[53] &&
!_theResult____h407265[52] &&
!_theResult____h407265[51] &&
!_theResult____h407265[50] &&
!_theResult____h407265[49] &&
!_theResult____h407265[48] &&
!_theResult____h407265[47] &&
!_theResult____h407265[46] &&
!_theResult____h407265[45] &&
!_theResult____h407265[44] &&
!_theResult____h407265[43] &&
!_theResult____h407265[42] &&
!_theResult____h407265[41] &&
!_theResult____h407265[40] &&
!_theResult____h407265[39] &&
!_theResult____h407265[38] &&
!_theResult____h407265[37] &&
!_theResult____h407265[36] &&
!_theResult____h407265[35] &&
!_theResult____h407265[34] &&
!_theResult____h407265[33] &&
!_theResult____h407265[32] &&
!_theResult____h407265[31] &&
!_theResult____h407265[30] &&
!_theResult____h407265[29] &&
!_theResult____h407265[28] &&
!_theResult____h407265[27] &&
!_theResult____h407265[26] &&
!_theResult____h407265[25] &&
!_theResult____h407265[24] &&
!_theResult____h407265[23] &&
!_theResult____h407265[22] &&
!_theResult____h407265[21] &&
!_theResult____h407265[20] &&
!_theResult____h407265[19] &&
!_theResult____h407265[18] &&
!_theResult____h407265[17] &&
!_theResult____h407265[16] &&
!_theResult____h407265[15] &&
!_theResult____h407265[14] &&
!_theResult____h407265[13] &&
!_theResult____h407265[12] &&
!_theResult____h407265[11] &&
!_theResult____h407265[10] &&
!_theResult____h407265[9] &&
!_theResult____h407265[8] &&
!_theResult____h407265[7] &&
!_theResult____h407265[6] &&
!_theResult____h407265[5] &&
!_theResult____h407265[4] &&
!_theResult____h407265[3] &&
!_theResult____h407265[2] &&
!_theResult____h407265[1] &&
!_theResult____h407265[0]) ?
_theResult____h407265 :
_theResult___snd__h415543 ;
assign _theResult___snd__h415543 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q73[54:0],
2'd0 } ;
assign _theResult___snd__h415566 =
_theResult____h407265 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d6186 ;
assign _theResult___snd__h424134 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0) ?
_theResult___snd__h424148 :
_theResult___snd__h406346 ;
assign _theResult___snd__h424148 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_div__ETC___d5811) ?
sfd__h382026 :
_theResult___snd__h424154 ;
assign _theResult___snd__h424154 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q78[54:0],
2'd0 } ;
assign _theResult___snd__h424172 =
sfd__h382026 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d6260) ;
assign _theResult___snd__h443443 = { _theResult____h435323[55:0], 1'd0 } ;
assign _theResult___snd__h443454 =
(!_theResult____h435323[56] && _theResult____h435323[55]) ?
_theResult___snd__h443456 :
_theResult___snd__h443466 ;
assign _theResult___snd__h443456 = { _theResult____h435323[54:0], 2'd0 } ;
assign _theResult___snd__h443466 =
(!_theResult____h435323[56] && !_theResult____h435323[55] &&
!_theResult____h435323[54] &&
!_theResult____h435323[53] &&
!_theResult____h435323[52] &&
!_theResult____h435323[51] &&
!_theResult____h435323[50] &&
!_theResult____h435323[49] &&
!_theResult____h435323[48] &&
!_theResult____h435323[47] &&
!_theResult____h435323[46] &&
!_theResult____h435323[45] &&
!_theResult____h435323[44] &&
!_theResult____h435323[43] &&
!_theResult____h435323[42] &&
!_theResult____h435323[41] &&
!_theResult____h435323[40] &&
!_theResult____h435323[39] &&
!_theResult____h435323[38] &&
!_theResult____h435323[37] &&
!_theResult____h435323[36] &&
!_theResult____h435323[35] &&
!_theResult____h435323[34] &&
!_theResult____h435323[33] &&
!_theResult____h435323[32] &&
!_theResult____h435323[31] &&
!_theResult____h435323[30] &&
!_theResult____h435323[29] &&
!_theResult____h435323[28] &&
!_theResult____h435323[27] &&
!_theResult____h435323[26] &&
!_theResult____h435323[25] &&
!_theResult____h435323[24] &&
!_theResult____h435323[23] &&
!_theResult____h435323[22] &&
!_theResult____h435323[21] &&
!_theResult____h435323[20] &&
!_theResult____h435323[19] &&
!_theResult____h435323[18] &&
!_theResult____h435323[17] &&
!_theResult____h435323[16] &&
!_theResult____h435323[15] &&
!_theResult____h435323[14] &&
!_theResult____h435323[13] &&
!_theResult____h435323[12] &&
!_theResult____h435323[11] &&
!_theResult____h435323[10] &&
!_theResult____h435323[9] &&
!_theResult____h435323[8] &&
!_theResult____h435323[7] &&
!_theResult____h435323[6] &&
!_theResult____h435323[5] &&
!_theResult____h435323[4] &&
!_theResult____h435323[3] &&
!_theResult____h435323[2] &&
!_theResult____h435323[1] &&
!_theResult____h435323[0]) ?
_theResult____h435323 :
_theResult___snd__h443472 ;
assign _theResult___snd__h443472 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMu_ETC__q98[54:0],
2'd0 } ;
assign _theResult___snd__h443495 =
_theResult____h435323 <<
IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fp_ETC___d7027 ;
assign _theResult___snd__h452039 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h452048 :
_theResult___snd__h452041 ;
assign _theResult___snd__h452041 =
{ coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5],
5'd0 } ;
assign _theResult___snd__h452048 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ?
sfd__h427721 :
_theResult___snd__h452054 ;
assign _theResult___snd__h452054 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q100[54:0],
2'd0 } ;
assign _theResult___snd__h452077 =
sfd__h427721 <<
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7258 ;
assign _theResult___snd__h461209 = { _theResult____h452960[55:0], 1'd0 } ;
assign _theResult___snd__h461220 =
(!_theResult____h452960[56] && _theResult____h452960[55]) ?
_theResult___snd__h461222 :
_theResult___snd__h461232 ;
assign _theResult___snd__h461222 = { _theResult____h452960[54:0], 2'd0 } ;
assign _theResult___snd__h461232 =
(!_theResult____h452960[56] && !_theResult____h452960[55] &&
!_theResult____h452960[54] &&
!_theResult____h452960[53] &&
!_theResult____h452960[52] &&
!_theResult____h452960[51] &&
!_theResult____h452960[50] &&
!_theResult____h452960[49] &&
!_theResult____h452960[48] &&
!_theResult____h452960[47] &&
!_theResult____h452960[46] &&
!_theResult____h452960[45] &&
!_theResult____h452960[44] &&
!_theResult____h452960[43] &&
!_theResult____h452960[42] &&
!_theResult____h452960[41] &&
!_theResult____h452960[40] &&
!_theResult____h452960[39] &&
!_theResult____h452960[38] &&
!_theResult____h452960[37] &&
!_theResult____h452960[36] &&
!_theResult____h452960[35] &&
!_theResult____h452960[34] &&
!_theResult____h452960[33] &&
!_theResult____h452960[32] &&
!_theResult____h452960[31] &&
!_theResult____h452960[30] &&
!_theResult____h452960[29] &&
!_theResult____h452960[28] &&
!_theResult____h452960[27] &&
!_theResult____h452960[26] &&
!_theResult____h452960[25] &&
!_theResult____h452960[24] &&
!_theResult____h452960[23] &&
!_theResult____h452960[22] &&
!_theResult____h452960[21] &&
!_theResult____h452960[20] &&
!_theResult____h452960[19] &&
!_theResult____h452960[18] &&
!_theResult____h452960[17] &&
!_theResult____h452960[16] &&
!_theResult____h452960[15] &&
!_theResult____h452960[14] &&
!_theResult____h452960[13] &&
!_theResult____h452960[12] &&
!_theResult____h452960[11] &&
!_theResult____h452960[10] &&
!_theResult____h452960[9] &&
!_theResult____h452960[8] &&
!_theResult____h452960[7] &&
!_theResult____h452960[6] &&
!_theResult____h452960[5] &&
!_theResult____h452960[4] &&
!_theResult____h452960[3] &&
!_theResult____h452960[2] &&
!_theResult____h452960[1] &&
!_theResult____h452960[0]) ?
_theResult____h452960 :
_theResult___snd__h461238 ;
assign _theResult___snd__h461238 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_coreFix_fpuM_ETC__q108[54:0],
2'd0 } ;
assign _theResult___snd__h461261 =
_theResult____h452960 <<
IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_f_ETC___d7578 ;
assign _theResult___snd__h469829 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0) ?
_theResult___snd__h469843 :
_theResult___snd__h452041 ;
assign _theResult___snd__h469843 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd0 &&
NOT_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt_ETC___d7203) ?
sfd__h427721 :
_theResult___snd__h469849 ;
assign _theResult___snd__h469849 =
{ IF_0_CONCAT_IF_coreFix_fpuMulDivExe_0_fpuExec__ETC__q113[54:0],
2'd0 } ;
assign _theResult___snd__h469867 =
sfd__h427721 <<
(IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652[8] ?
9'h0AA :
IF_SEXT_coreFix_fpuMulDivExe_0_fpuExec_double__ETC___d7652) ;
assign _theResult___snd__h499323 =
(f1_exp__h479984 == 8'd0) ?
_theResult___snd__h499332 :
_theResult___snd__h499325 ;
assign _theResult___snd__h499325 = { f1_sfd__h479985, 34'd0 } ;
assign _theResult___snd__h499332 =
(f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553) ?
sfd__h480346 :
_theResult___snd__h499338 ;
assign _theResult___snd__h499338 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q134[54:0],
2'd0 } ;
assign _theResult___snd__h499361 =
sfd__h480346 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d8580 ;
assign _theResult___snd__h508960 = { _theResult____h500713[55:0], 1'd0 } ;
assign _theResult___snd__h508971 =
(!_theResult____h500713[56] && _theResult____h500713[55]) ?
_theResult___snd__h508973 :
_theResult___snd__h508983 ;
assign _theResult___snd__h508973 = { _theResult____h500713[54:0], 2'd0 } ;
assign _theResult___snd__h508983 =
(!_theResult____h500713[56] && !_theResult____h500713[55] &&
!_theResult____h500713[54] &&
!_theResult____h500713[53] &&
!_theResult____h500713[52] &&
!_theResult____h500713[51] &&
!_theResult____h500713[50] &&
!_theResult____h500713[49] &&
!_theResult____h500713[48] &&
!_theResult____h500713[47] &&
!_theResult____h500713[46] &&
!_theResult____h500713[45] &&
!_theResult____h500713[44] &&
!_theResult____h500713[43] &&
!_theResult____h500713[42] &&
!_theResult____h500713[41] &&
!_theResult____h500713[40] &&
!_theResult____h500713[39] &&
!_theResult____h500713[38] &&
!_theResult____h500713[37] &&
!_theResult____h500713[36] &&
!_theResult____h500713[35] &&
!_theResult____h500713[34] &&
!_theResult____h500713[33] &&
!_theResult____h500713[32] &&
!_theResult____h500713[31] &&
!_theResult____h500713[30] &&
!_theResult____h500713[29] &&
!_theResult____h500713[28] &&
!_theResult____h500713[27] &&
!_theResult____h500713[26] &&
!_theResult____h500713[25] &&
!_theResult____h500713[24] &&
!_theResult____h500713[23] &&
!_theResult____h500713[22] &&
!_theResult____h500713[21] &&
!_theResult____h500713[20] &&
!_theResult____h500713[19] &&
!_theResult____h500713[18] &&
!_theResult____h500713[17] &&
!_theResult____h500713[16] &&
!_theResult____h500713[15] &&
!_theResult____h500713[14] &&
!_theResult____h500713[13] &&
!_theResult____h500713[12] &&
!_theResult____h500713[11] &&
!_theResult____h500713[10] &&
!_theResult____h500713[9] &&
!_theResult____h500713[8] &&
!_theResult____h500713[7] &&
!_theResult____h500713[6] &&
!_theResult____h500713[5] &&
!_theResult____h500713[4] &&
!_theResult____h500713[3] &&
!_theResult____h500713[2] &&
!_theResult____h500713[1] &&
!_theResult____h500713[0]) ?
_theResult____h500713 :
_theResult___snd__h508989 ;
assign _theResult___snd__h508989 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q138[54:0],
2'd0 } ;
assign _theResult___snd__h509012 =
_theResult____h500713 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d8892 ;
assign _theResult___snd__h517728 =
(f1_exp__h479984 == 8'd0) ?
_theResult___snd__h517742 :
_theResult___snd__h499325 ;
assign _theResult___snd__h517742 =
(f1_exp__h479984 == 8'd0 && !f1_sfd__h479985[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d8553) ?
sfd__h480346 :
_theResult___snd__h517748 ;
assign _theResult___snd__h517748 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q141[54:0],
2'd0 } ;
assign _theResult___snd__h517766 =
sfd__h480346 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d8943 ;
assign _theResult___snd__h538176 =
(f2_exp__h518978 == 8'd0) ?
_theResult___snd__h538185 :
_theResult___snd__h538178 ;
assign _theResult___snd__h538178 = { f2_sfd__h518979, 34'd0 } ;
assign _theResult___snd__h538185 =
(f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053) ?
sfd__h519340 :
_theResult___snd__h538191 ;
assign _theResult___snd__h538191 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q174[54:0],
2'd0 } ;
assign _theResult___snd__h538214 =
sfd__h519340 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10080 ;
assign _theResult___snd__h547813 = { _theResult____h539566[55:0], 1'd0 } ;
assign _theResult___snd__h547824 =
(!_theResult____h539566[56] && _theResult____h539566[55]) ?
_theResult___snd__h547826 :
_theResult___snd__h547836 ;
assign _theResult___snd__h547826 = { _theResult____h539566[54:0], 2'd0 } ;
assign _theResult___snd__h547836 =
(!_theResult____h539566[56] && !_theResult____h539566[55] &&
!_theResult____h539566[54] &&
!_theResult____h539566[53] &&
!_theResult____h539566[52] &&
!_theResult____h539566[51] &&
!_theResult____h539566[50] &&
!_theResult____h539566[49] &&
!_theResult____h539566[48] &&
!_theResult____h539566[47] &&
!_theResult____h539566[46] &&
!_theResult____h539566[45] &&
!_theResult____h539566[44] &&
!_theResult____h539566[43] &&
!_theResult____h539566[42] &&
!_theResult____h539566[41] &&
!_theResult____h539566[40] &&
!_theResult____h539566[39] &&
!_theResult____h539566[38] &&
!_theResult____h539566[37] &&
!_theResult____h539566[36] &&
!_theResult____h539566[35] &&
!_theResult____h539566[34] &&
!_theResult____h539566[33] &&
!_theResult____h539566[32] &&
!_theResult____h539566[31] &&
!_theResult____h539566[30] &&
!_theResult____h539566[29] &&
!_theResult____h539566[28] &&
!_theResult____h539566[27] &&
!_theResult____h539566[26] &&
!_theResult____h539566[25] &&
!_theResult____h539566[24] &&
!_theResult____h539566[23] &&
!_theResult____h539566[22] &&
!_theResult____h539566[21] &&
!_theResult____h539566[20] &&
!_theResult____h539566[19] &&
!_theResult____h539566[18] &&
!_theResult____h539566[17] &&
!_theResult____h539566[16] &&
!_theResult____h539566[15] &&
!_theResult____h539566[14] &&
!_theResult____h539566[13] &&
!_theResult____h539566[12] &&
!_theResult____h539566[11] &&
!_theResult____h539566[10] &&
!_theResult____h539566[9] &&
!_theResult____h539566[8] &&
!_theResult____h539566[7] &&
!_theResult____h539566[6] &&
!_theResult____h539566[5] &&
!_theResult____h539566[4] &&
!_theResult____h539566[3] &&
!_theResult____h539566[2] &&
!_theResult____h539566[1] &&
!_theResult____h539566[0]) ?
_theResult____h539566 :
_theResult___snd__h547842 ;
assign _theResult___snd__h547842 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q178[54:0],
2'd0 } ;
assign _theResult___snd__h547865 =
_theResult____h539566 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d10377 ;
assign _theResult___snd__h556581 =
(f2_exp__h518978 == 8'd0) ?
_theResult___snd__h556595 :
_theResult___snd__h538178 ;
assign _theResult___snd__h556595 =
(f2_exp__h518978 == 8'd0 && !f2_sfd__h518979[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10053) ?
sfd__h519340 :
_theResult___snd__h556601 ;
assign _theResult___snd__h556601 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q181[54:0],
2'd0 } ;
assign _theResult___snd__h556619 =
sfd__h519340 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d10428 ;
assign _theResult___snd__h577480 =
(f3_exp__h558282 == 8'd0) ?
_theResult___snd__h577489 :
_theResult___snd__h577482 ;
assign _theResult___snd__h577482 = { f3_sfd__h558283, 34'd0 } ;
assign _theResult___snd__h577489 =
(f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283) ?
sfd__h558644 :
_theResult___snd__h577495 ;
assign _theResult___snd__h577495 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q151[54:0],
2'd0 } ;
assign _theResult___snd__h577518 =
sfd__h558644 <<
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d9310 ;
assign _theResult___snd__h587117 = { _theResult____h578870[55:0], 1'd0 } ;
assign _theResult___snd__h587128 =
(!_theResult____h578870[56] && _theResult____h578870[55]) ?
_theResult___snd__h587130 :
_theResult___snd__h587140 ;
assign _theResult___snd__h587130 = { _theResult____h578870[54:0], 2'd0 } ;
assign _theResult___snd__h587140 =
(!_theResult____h578870[56] && !_theResult____h578870[55] &&
!_theResult____h578870[54] &&
!_theResult____h578870[53] &&
!_theResult____h578870[52] &&
!_theResult____h578870[51] &&
!_theResult____h578870[50] &&
!_theResult____h578870[49] &&
!_theResult____h578870[48] &&
!_theResult____h578870[47] &&
!_theResult____h578870[46] &&
!_theResult____h578870[45] &&
!_theResult____h578870[44] &&
!_theResult____h578870[43] &&
!_theResult____h578870[42] &&
!_theResult____h578870[41] &&
!_theResult____h578870[40] &&
!_theResult____h578870[39] &&
!_theResult____h578870[38] &&
!_theResult____h578870[37] &&
!_theResult____h578870[36] &&
!_theResult____h578870[35] &&
!_theResult____h578870[34] &&
!_theResult____h578870[33] &&
!_theResult____h578870[32] &&
!_theResult____h578870[31] &&
!_theResult____h578870[30] &&
!_theResult____h578870[29] &&
!_theResult____h578870[28] &&
!_theResult____h578870[27] &&
!_theResult____h578870[26] &&
!_theResult____h578870[25] &&
!_theResult____h578870[24] &&
!_theResult____h578870[23] &&
!_theResult____h578870[22] &&
!_theResult____h578870[21] &&
!_theResult____h578870[20] &&
!_theResult____h578870[19] &&
!_theResult____h578870[18] &&
!_theResult____h578870[17] &&
!_theResult____h578870[16] &&
!_theResult____h578870[15] &&
!_theResult____h578870[14] &&
!_theResult____h578870[13] &&
!_theResult____h578870[12] &&
!_theResult____h578870[11] &&
!_theResult____h578870[10] &&
!_theResult____h578870[9] &&
!_theResult____h578870[8] &&
!_theResult____h578870[7] &&
!_theResult____h578870[6] &&
!_theResult____h578870[5] &&
!_theResult____h578870[4] &&
!_theResult____h578870[3] &&
!_theResult____h578870[2] &&
!_theResult____h578870[1] &&
!_theResult____h578870[0]) ?
_theResult____h578870 :
_theResult___snd__h587146 ;
assign _theResult___snd__h587146 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_coreFix_f_ETC__q155[54:0],
2'd0 } ;
assign _theResult___snd__h587169 =
_theResult____h578870 <<
IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe__ETC___d9607 ;
assign _theResult___snd__h595885 =
(f3_exp__h558282 == 8'd0) ?
_theResult___snd__h595899 :
_theResult___snd__h577482 ;
assign _theResult___snd__h595899 =
(f3_exp__h558282 == 8'd0 && !f3_sfd__h558283[22] &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d9283) ?
sfd__h558644 :
_theResult___snd__h595905 ;
assign _theResult___snd__h595905 =
{ IF_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_0_regTo_ETC__q158[54:0],
2'd0 } ;
assign _theResult___snd__h595923 =
sfd__h558644 <<
IF_SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_fi_ETC___d9658 ;
assign _theResult___snd__h601215 =
b__h600793[63] ? b___1__h601264 : b__h600793 ;
assign _theResult___snd_fst_exp__h361222 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_theResult___fst_exp__h352637 :
_theResult___fst_exp__h361219 ;
assign _theResult___snd_fst_exp__h379042 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_theResult___fst_exp__h370403 :
_theResult___fst_exp__h379039 ;
assign _theResult___snd_fst_exp__h406919 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_theResult___fst_exp__h398334 :
_theResult___fst_exp__h406916 ;
assign _theResult___snd_fst_exp__h424739 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_theResult___fst_exp__h416100 :
_theResult___fst_exp__h424736 ;
assign _theResult___snd_fst_exp__h452614 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_theResult___fst_exp__h444029 :
_theResult___fst_exp__h452611 ;
assign _theResult___snd_fst_exp__h470434 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_theResult___fst_exp__h461795 :
_theResult___fst_exp__h470431 ;
assign _theResult___snd_fst_exp__h500133 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ?
11'd0 :
_theResult___fst_exp__h500130 ;
assign _theResult___snd_fst_exp__h518568 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ?
_theResult___fst_exp__h509781 :
_theResult___fst_exp__h518565 ;
assign _theResult___snd_fst_exp__h538986 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ?
11'd0 :
_theResult___fst_exp__h538983 ;
assign _theResult___snd_fst_exp__h557421 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ?
_theResult___fst_exp__h548634 :
_theResult___fst_exp__h557418 ;
assign _theResult___snd_fst_exp__h578290 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ?
11'd0 :
_theResult___fst_exp__h578287 ;
assign _theResult___snd_fst_exp__h596725 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ?
_theResult___fst_exp__h587938 :
_theResult___fst_exp__h596722 ;
assign _theResult___snd_fst_sfd__h336274 =
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h361223 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d4009 ?
_theResult___fst_sfd__h352638 :
_theResult___fst_sfd__h361220 ;
assign _theResult___snd_fst_sfd__h379043 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_fma_ETC___d4549 ?
_theResult___fst_sfd__h370404 :
_theResult___fst_sfd__h379040 ;
assign _theResult___snd_fst_sfd__h381976 =
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h406920 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d5401 ?
_theResult___fst_sfd__h398335 :
_theResult___fst_sfd__h406917 ;
assign _theResult___snd_fst_sfd__h424740 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_div_ETC___d5941 ?
_theResult___fst_sfd__h416101 :
_theResult___fst_sfd__h424737 ;
assign _theResult___snd_fst_sfd__h427671 =
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ==
23'd0) ?
23'd2097152 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:34] ;
assign _theResult___snd_fst_sfd__h452615 =
_3074_MINUS_0_CONCAT_IF_coreFix_fpuMulDivExe_0__ETC___d6793 ?
_theResult___fst_sfd__h444030 :
_theResult___fst_sfd__h452612 ;
assign _theResult___snd_fst_sfd__h470435 =
SEXT_coreFix_fpuMulDivExe_0_fpuExec_double_sqr_ETC___d7333 ?
_theResult___fst_sfd__h461796 :
_theResult___fst_sfd__h470432 ;
assign _theResult___snd_fst_sfd__h480300 =
(f1_sfd__h479985 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h480048 ;
assign _theResult___snd_fst_sfd__h500134 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d8509 ?
52'd0 :
_theResult___fst_sfd__h500131 ;
assign _theResult___snd_fst_sfd__h518569 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d8645 ?
_theResult___fst_sfd__h509782 :
_theResult___fst_sfd__h518566 ;
assign _theResult___snd_fst_sfd__h519294 =
(f2_sfd__h518979 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h519042 ;
assign _theResult___snd_fst_sfd__h538987 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d10009 ?
52'd0 :
_theResult___fst_sfd__h538984 ;
assign _theResult___snd_fst_sfd__h557422 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d10130 ?
_theResult___fst_sfd__h548635 :
_theResult___fst_sfd__h557419 ;
assign _theResult___snd_fst_sfd__h558598 =
(f3_sfd__h558283 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h558346 ;
assign _theResult___snd_fst_sfd__h578291 =
_3970_MINUS_0_CONCAT_IF_IF_coreFix_fpuMulDivExe_ETC___d9239 ?
52'd0 :
_theResult___fst_sfd__h578288 ;
assign _theResult___snd_fst_sfd__h596726 =
SEXT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first_ETC___d9360 ?
_theResult___fst_sfd__h587939 :
_theResult___fst_sfd__h596723 ;
assign a___1__h600933 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd1) ?
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] } :
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10 } ;
assign a___1__h601219 = 64'd0 - a__h600792 ;
assign a__h600792 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
a___1__h600933 :
coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign b___1__h600934 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[226:225] == 2'd0) ?
{ {32{coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11[31]}},
coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11 } :
{ 32'd0, coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] } ;
assign b___1__h601264 = 64'd0 - b__h600793 ;
assign b__h600793 =
coreFix_fpuMulDivExe_0_regToExeQ$first[227] ?
b___1__h600934 :
coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign base__h700680 = { csrf_stvec_base_hi_reg, 2'b0 } ;
assign base__h700883 = { csrf_mtvec_base_hi_reg, 2'b0 } ;
assign cause_code__h698062 =
commitStage_commitTrap[4] ? i__h698237 : i__h698077 ;
assign commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 =
commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] != 4'd0 &&
commitStage_commitTrap[3:0] != 4'd1 &&
commitStage_commitTrap[3:0] != 4'd3 &&
commitStage_commitTrap[3:0] != 4'd4 &&
commitStage_commitTrap[3:0] != 4'd5 &&
commitStage_commitTrap[3:0] != 4'd7 &&
commitStage_commitTrap[3:0] != 4'd8 &&
commitStage_commitTrap[3:0] != 4'd9 &&
commitStage_commitTrap[3:0] != 4'd11 ||
!commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] == 4'd3 &&
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 ;
assign commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14530 =
commitStage_commitTrap_4245_BIT_4_4464_AND_com_ETC___d14529 ||
coreFix_memExe_stb$isEmpty && coreFix_memExe_lsq$stqEmpty &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq ;
assign coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12165 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_0_wget__2163_BITS__ETC___d12204 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12178 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_1_wget__2176_BITS__ETC___d12210 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12186 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_0_bypassWire_2_wget__2184_BITS__ETC___d12214 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_0_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_0_dispToRegQ_first__2142_BIT_13_ETC___d12227 =
(coreFix_aluExe_0_dispToRegQ$first[131] ||
sbCons$lazyLookup_0_get[3] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12173 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12199) &&
(sbCons$lazyLookup_0_get[2] ||
IF_coreFix_aluExe_0_dispToRegQ_RDY_first__2141_ETC___d12207 &&
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12224) ;
assign coreFix_aluExe_0_exeToFinQ_RDY_first__2581_AND_ETC___d12620 =
coreFix_aluExe_0_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_0_set &&
(coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_0_exeToFinQ$first[326:322] != 5'd10 ||
coreFix_trainBPQ_0$FULL_N) ;
assign coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 =
coreFix_aluExe_0_rsAlu$approximateCount <
coreFix_aluExe_1_rsAlu$approximateCount ;
assign coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11334 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_0_wget__1332_BITS__ETC___d11373 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11347 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_1_wget__1345_BITS__ETC___d11379 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11355 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[84:78] ;
assign coreFix_aluExe_1_bypassWire_2_wget__1353_BITS__ETC___d11383 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_aluExe_1_dispToRegQ$first[76:70] ;
assign coreFix_aluExe_1_dispToRegQ_first__1311_BIT_13_ETC___d11396 =
(coreFix_aluExe_1_dispToRegQ$first[131] ||
sbCons$lazyLookup_1_get[3] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11342 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11368) &&
(sbCons$lazyLookup_1_get[2] ||
IF_coreFix_aluExe_1_dispToRegQ_RDY_first__1310_ETC___d11376 &&
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11393) ;
assign coreFix_aluExe_1_exeToFinQ_RDY_first__1935_AND_ETC___d11975 =
coreFix_aluExe_1_exeToFinQ$RDY_first &&
rob$RDY_setExecuted_doFinishAlu_1_set &&
(coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd9 &&
coreFix_aluExe_1_exeToFinQ$first[326:322] != 5'd10 ||
coreFix_trainBPQ_1$FULL_N) ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8206 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8244 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_0_wget__204__ETC___d8268 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8219 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8250 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_1_wget__217__ETC___d8274 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8227 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[55:49] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8254 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[47:41] ;
assign coreFix_fpuMulDivExe_0_bypassWire_2_wget__225__ETC___d8278 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_fpuMulDivExe_0_dispToRegQ$first[39:33] ;
assign coreFix_fpuMulDivExe_0_fpuExec_divQ_RDY_first__ETC___d5268 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_divresp_ETC__q71 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_fmaresp_ETC__q36 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_double_sqrtres_ETC__q106 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] -
11'd1023 ;
assign coreFix_fpuMulDivExe_0_fpuExec_fmaQ_RDY_first__ETC___d3876 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_RDY_first_ETC___d6660 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_response_get &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_first_data ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8098 =
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY &&
(!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[32] ||
((coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
2'd2) ?
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid :
coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] !=
2'd3 ||
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid)) ;
assign coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divI_ETC___d8101 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tvalid &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ_RDY_fir_ETC___d8098 ;
assign coreFix_fpuMulDivExe_0_mulDivExec_mulQ_RDY_fir_ETC___d8052 =
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_poisoned &&
!coreFix_fpuMulDivExe_0_mulDivExec_mulQ$first_poisoned &&
rob$RDY_setExecuted_doFinishFpuMulDiv_0_set &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_first_data &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_respQ$EMPTY_N ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10849 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804 |
((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) &&
(f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) &&
(f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10844) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10885 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873 |
((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) &&
(f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) &&
(f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10880) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917 |
((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) &&
(f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) &&
(f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10928) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961 |
((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) &&
(f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) &&
(f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10970) ;
assign coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd25 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd26 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd27 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] == 5'd28) &&
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003 |
((f3_exp__h558282 != 8'd255 || f3_sfd__h558283 == 23'd0) &&
(f3_exp__h558282 != 8'd255 || f3_sfd__h558283 != 23'd0) &&
(f3_exp__h558282 != 8'd0 || f3_sfd__h558283 != 23'd0) &&
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d11012) ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_10_ETC__q11 =
coreFix_fpuMulDivExe_0_regToExeQ$first[107:76] ;
assign coreFix_fpuMulDivExe_0_regToExeQfirst_BITS_17_ETC__q10 =
coreFix_fpuMulDivExe_0_regToExeQ$first[171:140] ;
assign coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) ;
assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1570 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_0_wget__568_BITS_70__ETC___d1608 =
coreFix_aluExe_0_bypassWire_0$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1583 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_1_wget__581_BITS_70__ETC___d1614 =
coreFix_aluExe_0_bypassWire_1$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1591 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[61:55] ;
assign coreFix_memExe_bypassWire_2_wget__589_BITS_70__ETC___d1618 =
coreFix_aluExe_0_bypassWire_2$wget[70:64] ==
coreFix_memExe_dispToRegQ$first[53:47] ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_pi_ETC___d2573 =
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 ||
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] !=
2'd0 &&
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
y__h252650 ;
assign coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIn_ETC___d3063 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027 ||
(!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_dMem_cache_m_banks_0_cRqTransfer_retry &&
!coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enq_ETC___d3166 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134 ||
(!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_lat_0$whas &&
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:90] ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2066 ;
assign coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2723 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_0$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_dummy2_1$Q_OUT &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[58] &&
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl[57:0] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:8] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[514:512] ==
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[576:574] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[83:82] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <
2'd2 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[147:96] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2527 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2556 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd2 ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2561 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2560 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2578 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2553 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2577 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2595 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2588 ||
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2594 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2092 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2618 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
(!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023) &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd0 &&
coreFix_memExe_lsq$getHit[8] &&
!coreFix_memExe_lsq$getHit[9] ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2615 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] ==
3'd3 &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_linkAd_ETC___d2068 &&
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getSucc[3] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2645 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2639 ||
!coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[515] &&
(!coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_searchEndOfChain[3] ||
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getState !=
3'd1) &&
NOT_coreFix_memExe_dMem_cache_m_banks_0_pipeli_ETC___d2642 ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2647 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2013 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2021 &&
coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2023 &&
(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79] !=
3'd3 ||
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146) ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2693 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[517:516] <=
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[1:0] ;
assign coreFix_memExe_dMem_cache_m_banks_0_pipeline_f_ETC___d2696 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518] ==
coreFix_memExe_dMem_cache_m_banks_0_pRqMshr$pipelineResp_getRq[65:14] ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2793 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[78] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[78]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2797 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[77] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[77]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2801 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[76] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[76]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2806 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[75] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[75]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2810 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[74] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[74]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2815 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[73] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[73]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2819 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[72] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[72]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2824 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[71] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[71]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2836 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[2] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[2]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2840 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[1] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[1]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_d_ETC___d2844 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[0] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[0]) ;
assign coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enq_ETC___d3337 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rqToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full ;
assign coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enq_ETC___d3433 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401 ||
(!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_dummy2_2$Q_OUT ||
!EN_dCacheToParent_rsToP_deq &&
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl) &&
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full ;
assign coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2_r_ETC___d1907 =
coreFix_memExe_dMem_perfReqQ_enqReq_dummy2_2$Q_OUT &&
coreFix_memExe_dMem_perfReqQ_enqReq_rl[4] ||
(!coreFix_memExe_dMem_perfReqQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_dMem_perfReqQ_deqReq_rl) &&
coreFix_memExe_dMem_perfReqQ_full ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 =
coreFix_memExe_dTlb$procResp[174:114] < 61'd402653184 ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 =
coreFix_memExe_dTlb$procResp[174:114] < 61'd536870912 ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 =
coreFix_memExe_dTlb$procResp[174:114] == mmio_toHostAddr ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 =
coreFix_memExe_dTlb$procResp[174:114] == mmio_fromHostAddr ;
assign coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1731 =
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1722 ||
!coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1723 ||
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1727 ||
coreFix_memExe_dTlb_procResp__712_BITS_174_TO__ETC___d1730 ;
assign coreFix_memExe_forwardQ_enqReq_dummy2_2_read___ETC___d3755 =
coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724 ||
(!coreFix_memExe_forwardQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdForward &&
!coreFix_memExe_forwardQ_deqReq_rl) &&
coreFix_memExe_forwardQ_full ;
assign coreFix_memExe_memRespLdQ_enqReq_dummy2_2_read_ETC___d3661 =
coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630 ||
(!coreFix_memExe_memRespLdQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_coreFix_memExe_doRespLdMem &&
!coreFix_memExe_memRespLdQ_deqReq_rl) &&
coreFix_memExe_memRespLdQ_full ;
assign coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12 =
coreFix_memExe_regToExeQ$first[189:158] ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1216 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[78] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[78]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1220 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[77] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[77]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1224 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[76] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[76]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1229 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[75] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[75]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1233 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[74] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[74]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1238 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[73] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[73]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1242 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[72] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[72]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1247 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[71] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[71]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1259 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[2] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[2]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1263 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[1] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[1]) ;
assign coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1_rea_ETC___d1267 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT &&
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[0] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[0]) ;
assign coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2_re_ETC___d3570 =
coreFix_memExe_respLrScAmoQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_respLrScAmoQ_enqReq_lat_1_wh_ETC___d3554 ||
(!coreFix_memExe_respLrScAmoQ_deqReq_dummy2_2$Q_OUT ||
!coreFix_memExe_respLrScAmoQ_deqReq_lat_0$whas &&
!coreFix_memExe_respLrScAmoQ_deqReq_rl) &&
coreFix_memExe_respLrScAmoQ_full ;
assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d12977 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[199:195] == 5'd13 &&
(fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972 ||
csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974) ;
assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_0_first[95] &&
fetchStage$pipelines_0_first[94] ||
fetchStage$pipelines_0_first[88] &&
fetchStage$pipelines_0_first[87] ||
fetchStage$pipelines_0_first[81] ||
fetchStage$pipelines_0_first[75] &&
fetchStage$pipelines_0_first[74]) ||
fetchStage$pipelines_0_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 =
csrf_fs_reg == 2'd0 &&
(fetchStage$pipelines_1_first[95] &&
fetchStage$pipelines_1_first[94] ||
fetchStage$pipelines_1_first[88] &&
fetchStage$pipelines_1_first[87] ||
fetchStage$pipelines_1_first[81] ||
fetchStage$pipelines_1_first[75] &&
fetchStage$pipelines_1_first[74]) ||
fetchStage$pipelines_1_first[231:200] == 32'h10500073 &&
csrf_tw_reg &&
csrf_prv_reg != 2'd3 ;
assign csrf_prv_reg_read__2727_ULE_1_4567_AND_IF_comm_ETC___d14589 =
csrf_prv_reg_read__2727_ULE_1___d14567 &&
(commitStage_commitTrap[4] ?
_0b0_CONCAT_csrf_mideleg_11_reg_read__1640_1641_ETC___d14569 :
_0b0_CONCAT_csrf_medeleg_15_reg_read__1632_1633_ETC___d14587) ;
assign csrf_prv_reg_read__2727_ULE_1___d14567 = csrf_prv_reg <= 2'd1 ;
assign csrf_prv_reg_read__2727_ULT_IF_fetchStage_pipe_ETC___d12974 =
csrf_prv_reg <
IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[9:8] ;
assign csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424 =
csrf_rg_dcsr[2] || !fetchStage$pipelines_0_canDeq ||
fetchStage$RDY_pipelines_0_first &&
IF_fetchStage_RDY_pipelines_0_first__2694_AND__ETC___d13361 ;
assign data73126_BITS_31_TO_0__q13 = data__h473126[31:0] ;
assign data___1__h472852 =
{ {32{IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133[31]}},
IF_coreFix_fpuMulDivExe_0_mulDivExec_mulQ_firs_ETC__q133 } ;
assign data___1__h473660 =
{ {32{data73126_BITS_31_TO_0__q13[31]}},
data73126_BITS_31_TO_0__q13 } ;
assign data__h473126 =
(coreFix_fpuMulDivExe_0_mulDivExec_divQ$first_data[35:34] ==
2'd2) ?
x_quotient__h473040 :
x_remainder__h473041 ;
assign dcsr_cause__h697582 =
(commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] == 4'd14) ?
3'd3 :
((commitStage_commitTrap[4] &&
commitStage_commitTrap[3:0] != 4'd0 &&
commitStage_commitTrap[3:0] != 4'd1 &&
commitStage_commitTrap[3:0] != 4'd3 &&
commitStage_commitTrap[3:0] != 4'd4 &&
commitStage_commitTrap[3:0] != 4'd5 &&
commitStage_commitTrap[3:0] != 4'd7 &&
commitStage_commitTrap[3:0] != 4'd8 &&
commitStage_commitTrap[3:0] != 4'd9 &&
commitStage_commitTrap[3:0] != 4'd11 &&
commitStage_commitTrap[3:0] != 4'd14) ?
3'd4 :
3'd1) ;
assign din_inc___2_exp__h379073 = _theResult___fst_exp__h352040 + 8'd1 ;
assign din_inc___2_exp__h379097 = _theResult___fst_exp__h360696 + 8'd1 ;
assign din_inc___2_exp__h379127 = _theResult___fst_exp__h369806 + 8'd1 ;
assign din_inc___2_exp__h379151 = _theResult___fst_exp__h378491 + 8'd1 ;
assign din_inc___2_exp__h424770 = _theResult___fst_exp__h397737 + 8'd1 ;
assign din_inc___2_exp__h424794 = _theResult___fst_exp__h406393 + 8'd1 ;
assign din_inc___2_exp__h424824 = _theResult___fst_exp__h415503 + 8'd1 ;
assign din_inc___2_exp__h424848 = _theResult___fst_exp__h424188 + 8'd1 ;
assign din_inc___2_exp__h470465 = _theResult___fst_exp__h443432 + 8'd1 ;
assign din_inc___2_exp__h470489 = _theResult___fst_exp__h452088 + 8'd1 ;
assign din_inc___2_exp__h470519 = _theResult___fst_exp__h461198 + 8'd1 ;
assign din_inc___2_exp__h470543 = _theResult___fst_exp__h469883 + 8'd1 ;
assign din_inc___2_exp__h518622 = _theResult___fst_exp__h499372 + 11'd1 ;
assign din_inc___2_exp__h518657 = _theResult___fst_exp__h508949 + 11'd1 ;
assign din_inc___2_exp__h518683 = _theResult___fst_exp__h517782 + 11'd1 ;
assign din_inc___2_exp__h557475 = _theResult___fst_exp__h538225 + 11'd1 ;
assign din_inc___2_exp__h557510 = _theResult___fst_exp__h547802 + 11'd1 ;
assign din_inc___2_exp__h557536 = _theResult___fst_exp__h556635 + 11'd1 ;
assign din_inc___2_exp__h596779 = _theResult___fst_exp__h577529 + 11'd1 ;
assign din_inc___2_exp__h596814 = _theResult___fst_exp__h587106 + 11'd1 ;
assign din_inc___2_exp__h596840 = _theResult___fst_exp__h595939 + 11'd1 ;
assign enabled_ints___1__h648251 = pend_ints__h647724 & y__h648263 ;
assign enabled_ints__h648298 =
pend_ints__h647724 &
{ r1__read_BITS_13_TO_0___h648274, csrf_mideleg_1_0_reg } ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13651 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391) ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13793 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789) ;
assign epochManager_checkEpoch_1_check_fetchStage_pip_ETC___d13811 =
epochManager$checkEpoch_1_check && !csrf_rg_dcsr[2] &&
(!fetchStage$pipelines_0_canDeq ||
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807) ;
assign f1_exp79984_MINUS_127__q136 = f1_exp__h479984 - 8'd127 ;
assign f1_exp__h479984 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[170:163] :
8'd255 ;
assign f1_sfd__h479985 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[162:140] :
23'd4194304 ;
assign f2_exp18978_MINUS_127__q176 = f2_exp__h518978 - 8'd127 ;
assign f2_exp__h518978 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[106:99] :
8'd255 ;
assign f2_sfd__h518979 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[98:76] :
23'd4194304 ;
assign f3_exp58282_MINUS_127__q153 = f3_exp__h558282 - 8'd127 ;
assign f3_exp__h558282 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[42:35] :
8'd255 ;
assign f3_sfd__h558283 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[34:12] :
23'd4194304 ;
assign f_csr_rsps_i_notFull__5308_AND_f_csr_reqs_firs_ETC___d15403 =
f_csr_rsps$FULL_N &&
(f_csr_reqs$D_OUT[75:64] != 12'd2049 ||
csrf_stats_module_writeQ$FULL_N) &&
(f_csr_reqs$D_OUT[75:64] != 12'd2048 ||
csrf_terminate_module_terminateQ$FULL_N) ;
assign fcsr_csr__read__h607163 = { 56'd0, x__h610293 } ;
assign fetchStage_RDY_pipelines_1_deq__2709_AND_NOT_f_ETC___d13995 =
fetchStage$RDY_pipelines_1_deq &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13991) &&
(fetchStage$pipelines_1_first[194:192] != 3'd1 ||
specTagManager$RDY_claimSpecTag) ;
assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935 =
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931) &&
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ;
assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14017 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ;
assign fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d14091 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d14014 &&
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 ||
!coreFix_aluExe_0_rsAlu$canEnq ;
assign fetchStage_pipelines_0_canDeq__2695_AND_fetchS_ETC___d14005 =
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879 ||
!fetchStage$pipelines_1_canDeq ||
fetchStage$RDY_pipelines_1_first &&
(fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890 ||
!regRenamingTable$rename_1_canRename ||
fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902 ||
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d14001) &&
IF_fetchStage_RDY_pipelines_1_first__2705_AND__ETC___d13822 ;
assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) ;
assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970 =
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961) ;
assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982 =
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 ||
fetchStage$pipelines_0_canDeq &&
(fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13754 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973) ;
assign fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d14211 =
fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign fetchStage_pipelines_0_canDeq__2695_AND_specTa_ETC___d14069 =
fetchStage$pipelines_0_canDeq && specTagManager$canClaim &&
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d12972 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 &&
fetchStage$pipelines_0_first[178:174] == 5'd15 ||
rs1__h651905 != 5'd0 ||
imm__h651906 != 32'd0) &&
IF_fetchStage_pipelines_0_first__2697_BIT_173__ETC___d12969[11:10] ==
2'b11 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13662 =
(fetchStage$pipelines_0_first[194:192] == 3'd0 ||
fetchStage$pipelines_0_first[194:192] == 3'd1) &&
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 &&
(!coreFix_aluExe_1_rsAlu$canEnq ||
coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370) ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13873 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13871 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13879 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage$pipelines_0_first[68] ||
checkForException___d12942[4] ||
!rob$enqPort_0_canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
NOT_regRenamingTable_rename_0_canRename__3329__ETC___d13678 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ||
coreFix_aluExe_0_rsAlu$canEnq &&
coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ;
assign fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13931 =
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim ||
!regRenamingTable$rename_0_canRename ||
fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 ||
fetchStage$pipelines_0_first[194:192] != 3'd0 &&
fetchStage$pipelines_0_first[194:192] != 3'd1 ||
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ;
assign fetchStage_pipelines_0_first__2697_BITS_199_TO_ETC___d13435 =
fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d12942[4] ||
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_0_first__2697_BIT_68_2726_ETC___d13752 =
fetchStage$pipelines_0_first[68] ||
checkForException___d12942[4] ||
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13428 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign fetchStage_pipelines_1_first__2706_BITS_194_TO_ETC___d13890 =
fetchStage$pipelines_1_first[194:192] == 3'd1 &&
(fetchStage$pipelines_0_canDeq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887 ||
!specTagManager$canClaim) ;
assign fetchStage_pipelines_1_first__2706_BITS_199_TO_ETC___d13902 =
fetchStage$pipelines_1_first[199:195] == 5'd0 ||
fetchStage$pipelines_1_first[199:195] == 5'd21 ||
fetchStage$pipelines_1_first[199:195] == 5'd17 ||
fetchStage$pipelines_1_first[199:195] == 5'd18 ||
fetchStage$pipelines_1_first[199:195] == 5'd13 ||
fetchStage$pipelines_1_first[199:195] == 5'd16 ||
fetchStage$pipelines_1_first[199:195] == 5'd15 ||
fetchStage$pipelines_1_first[199:195] == 5'd19 ||
fetchStage$pipelines_1_first[199:195] == 5'd20 ||
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_1_first[68] ||
checkForException___d13615[4] ||
csrf_fs_reg_read__1527_EQ_0_2931_AND_fetchStag_ETC___d13708 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
csrf_rg_dcsr[2] ||
fetchStage$pipelines_0_canDeq &&
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13896 ;
assign fetchStage_pipelines_1_first__2706_BIT_173_351_ETC___d13594 =
{ fetchStage$pipelines_1_first[173],
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 } ;
assign fflags__h714091 =
NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ?
y_avValue_fst__h714034 :
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 ;
assign fflags_csr__read__h607138 = { 59'd0, csrf_fflags_reg } ;
assign frm_csr__read__h607149 = { 61'd0, csrf_frm_reg } ;
assign guard__h343939 =
{ IF_sfdin52034_BIT_33_THEN_2_ELSE_0__q29[1],
{ sfdin__h352034[32:0], 23'd0 } != 56'd0 } ;
assign guard__h352648 =
{ IF_theResult___snd60647_BIT_33_THEN_2_ELSE_0__q31[1],
{ _theResult___snd__h360647[32:0], 23'd0 } != 56'd0 } ;
assign guard__h361578 =
{ IF_sfdin69800_BIT_33_THEN_2_ELSE_0__q39[1],
{ sfdin__h369800[32:0], 23'd0 } != 56'd0 } ;
assign guard__h362176 = x__h362278 != 57'd0 ;
assign guard__h370414 =
{ IF_theResult___snd78437_BIT_33_THEN_2_ELSE_0__q44[1],
{ _theResult___snd__h378437[32:0], 23'd0 } != 56'd0 } ;
assign guard__h389638 =
{ IF_sfdin97731_BIT_33_THEN_2_ELSE_0__q64[1],
{ sfdin__h397731[32:0], 23'd0 } != 56'd0 } ;
assign guard__h398345 =
{ IF_theResult___snd06344_BIT_33_THEN_2_ELSE_0__q66[1],
{ _theResult___snd__h406344[32:0], 23'd0 } != 56'd0 } ;
assign guard__h407275 =
{ IF_sfdin15497_BIT_33_THEN_2_ELSE_0__q74[1],
{ sfdin__h415497[32:0], 23'd0 } != 56'd0 } ;
assign guard__h407873 = x__h407975 != 57'd0 ;
assign guard__h416111 =
{ IF_theResult___snd24134_BIT_33_THEN_2_ELSE_0__q79[1],
{ _theResult___snd__h424134[32:0], 23'd0 } != 56'd0 } ;
assign guard__h435333 =
{ IF_sfdin43426_BIT_33_THEN_2_ELSE_0__q99[1],
{ sfdin__h443426[32:0], 23'd0 } != 56'd0 } ;
assign guard__h444040 =
{ IF_theResult___snd52039_BIT_33_THEN_2_ELSE_0__q101[1],
{ _theResult___snd__h452039[32:0], 23'd0 } != 56'd0 } ;
assign guard__h452970 =
{ IF_sfdin61192_BIT_33_THEN_2_ELSE_0__q109[1],
{ sfdin__h461192[32:0], 23'd0 } != 56'd0 } ;
assign guard__h453568 = x__h453670 != 57'd0 ;
assign guard__h461806 =
{ IF_theResult___snd69829_BIT_33_THEN_2_ELSE_0__q114[1],
{ _theResult___snd__h469829[32:0], 23'd0 } != 56'd0 } ;
assign guard__h491411 =
{ IF_theResult___snd99323_BIT_4_THEN_2_ELSE_0__q135[1],
{ _theResult___snd__h499323[3:0], 52'd0 } != 56'd0 } ;
assign guard__h500723 =
{ IF_sfdin08943_BIT_4_THEN_2_ELSE_0__q139[1],
{ sfdin__h508943[3:0], 52'd0 } != 56'd0 } ;
assign guard__h501321 = x__h501421 != 57'd0 ;
assign guard__h509792 =
{ IF_theResult___snd17728_BIT_4_THEN_2_ELSE_0__q142[1],
{ _theResult___snd__h517728[3:0], 52'd0 } != 56'd0 } ;
assign guard__h530264 =
{ IF_theResult___snd38176_BIT_4_THEN_2_ELSE_0__q175[1],
{ _theResult___snd__h538176[3:0], 52'd0 } != 56'd0 } ;
assign guard__h539576 =
{ IF_sfdin47796_BIT_4_THEN_2_ELSE_0__q179[1],
{ sfdin__h547796[3:0], 52'd0 } != 56'd0 } ;
assign guard__h540174 = x__h540274 != 57'd0 ;
assign guard__h548645 =
{ IF_theResult___snd56581_BIT_4_THEN_2_ELSE_0__q182[1],
{ _theResult___snd__h556581[3:0], 52'd0 } != 56'd0 } ;
assign guard__h569568 =
{ IF_theResult___snd77480_BIT_4_THEN_2_ELSE_0__q152[1],
{ _theResult___snd__h577480[3:0], 52'd0 } != 56'd0 } ;
assign guard__h578880 =
{ IF_sfdin87100_BIT_4_THEN_2_ELSE_0__q156[1],
{ sfdin__h587100[3:0], 52'd0 } != 56'd0 } ;
assign guard__h579478 = x__h579578 != 57'd0 ;
assign guard__h587949 =
{ IF_theResult___snd95885_BIT_4_THEN_2_ELSE_0__q159[1],
{ _theResult___snd__h595885[3:0], 52'd0 } != 56'd0 } ;
assign idx__h678705 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 ||
!coreFix_aluExe_0_rsAlu$canEnq ||
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13687 ;
assign imm__h651906 =
fetchStage$pipelines_0_first[160] ?
fetchStage$pipelines_0_first[159:128] :
32'd0 ;
assign k__h664083 =
!coreFix_aluExe_0_rsAlu$canEnq ||
coreFix_aluExe_1_rsAlu$canEnq &&
!coreFix_aluExe_0_rsAlu_approximateCount__3368__ETC___d13370 ;
assign mcause_csr__read__h608803 =
{ r1__read__h611814, csrf_mcause_code_reg } ;
assign mcounteren_csr__read__h608548 =
{ r1__read__h611801, csrf_mcounteren_cy_reg } ;
assign medeleg_csr__read__h608155 =
{ r1__read__h611644, csrf_medeleg_9_0_reg } ;
assign mideleg_csr__read__h608250 =
{ r1__read__h611661, csrf_mideleg_1_0_reg } ;
assign mie_csr__read__h608374 =
{ r1__read__h611685, csrf_software_int_en_vec_0 } ;
assign mip_csr__read__h609036 =
{ r1__read__h611820, csrf_software_int_pend_vec_0 } ;
assign mmio_cRqQ_enqReq_dummy2_2_read__32_AND_IF_mmio_ETC___d444 =
mmio_cRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRqQ_enqReq_lat_1_whas__30_THEN_mmio_c_ETC___d339 ||
(!mmio_cRqQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRq_deq && !mmio_cRqQ_deqReq_rl) &&
mmio_cRqQ_full ;
assign mmio_cRsQ_enqReq_dummy2_2_read__24_AND_IF_mmio_ETC___d836 =
mmio_cRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_cRsQ_enqReq_lat_1_whas__74_THEN_mmio_c_ETC___d783 ||
(!mmio_cRsQ_deqReq_dummy2_2$Q_OUT ||
!EN_mmioToPlatform_cRs_deq && !mmio_cRsQ_deqReq_rl) &&
mmio_cRsQ_full ;
assign mmio_dataPendQ_enqReq_dummy2_2_read__00_AND_IF_ETC___d312 =
mmio_dataPendQ_enqReq_dummy2_2$Q_OUT &&
(mmio_dataPendQ_enqReq_lat_0$whas || mmio_dataPendQ_enqReq_rl) ||
(!mmio_dataPendQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataPendQ_deqReq_rl) &&
mmio_dataPendQ_full ;
assign mmio_dataReqQ_enqReq_dummy2_2_read__41_AND_IF__ETC___d153 =
mmio_dataReqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataReqQ_enqReq_lat_1_whas__7_THEN_mmi_ETC___d46 ||
(!mmio_dataReqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_sendDataReq && !mmio_dataReqQ_deqReq_rl) &&
mmio_dataReqQ_full ;
assign mmio_dataRespQ_enqReq_dummy2_2_read__42_AND_IF_ETC___d254 =
mmio_dataRespQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_dataRespQ_enqReq_lat_1_whas__92_THEN_m_ETC___d201 ||
(!mmio_dataRespQ_deqReq_dummy2_2$Q_OUT ||
!mmio_dataRespQ_deqReq_lat_0$whas &&
!mmio_dataRespQ_deqReq_rl) &&
mmio_dataRespQ_full ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d12987 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
(renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12984) ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13272 ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13293 =
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d13275 &&
(fetchStage$pipelines_0_first[199:195] == 5'd0 ||
fetchStage$pipelines_0_first[199:195] == 5'd21 ||
fetchStage$pipelines_0_first[199:195] == 5'd17 ||
fetchStage$pipelines_0_first[199:195] == 5'd18 ||
fetchStage$pipelines_0_first[199:195] == 5'd13 ||
fetchStage$pipelines_0_first[199:195] == 5'd16 ||
fetchStage$pipelines_0_first[199:195] == 5'd15 ||
fetchStage$pipelines_0_first[199:195] == 5'd19 ||
fetchStage$pipelines_0_first[199:195] == 5'd20) &&
rob$isEmpty ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009 =
mmio_pRqQ_empty && epochManager$checkEpoch_0_check &&
!renameStage_rg_m_halt_req[4] &&
!fetchStage$pipelines_0_first[68] &&
NOT_IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_272_ETC___d13348 ;
assign mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14011 =
mmio_pRqQ_empty_53_AND_epochManager_checkEpoch_ETC___d14009 &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
rg_core_run_state == 2'd2 ;
assign mmio_pRqQ_enqReq_dummy2_2_read__35_AND_IF_mmio_ETC___d747 =
mmio_pRqQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRqQ_enqReq_lat_1_whas__33_THEN_mmio_p_ETC___d642 ||
(!mmio_pRqQ_deqReq_dummy2_2$Q_OUT ||
!CAN_FIRE_RL_mmio_handlePRq && !mmio_pRqQ_deqReq_rl) &&
mmio_pRqQ_full ;
assign mmio_pRsQ_enqReq_dummy2_2_read__94_AND_IF_mmio_ETC___d606 =
mmio_pRsQ_enqReq_dummy2_2$Q_OUT &&
IF_mmio_pRsQ_enqReq_lat_1_whas__82_THEN_mmio_p_ETC___d491 ||
(!mmio_pRsQ_deqReq_dummy2_2$Q_OUT ||
!mmio_pRsQ_deqReq_lat_0$whas && !mmio_pRsQ_deqReq_rl) &&
mmio_pRsQ_full ;
assign msip__h75907 = csrf_software_int_pend_vec_3 ;
assign mstatus_csr__read__h608007 = { r1__read__h611519, csrf_ie_vec_0 } ;
assign mtvec_csr__read__h608456 =
{ r1__read__h611796, csrf_mtvec_mode_low_reg } ;
assign n___1__h196376 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[78] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[70:63] :
x__h194973[63:56],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[77] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[62:55] :
x__h194973[55:48],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[76] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[54:47] :
x__h194973[47:40],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[75] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[46:39] :
x__h194973[39:32],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[74] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[38:31] :
x__h194973[31:24],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[73] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[30:23] :
x__h194973[23:16],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[72] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[22:15] :
x__h194973[15:8],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[71] ?
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[14:7] :
x__h194973[7:0] } ;
assign n__read__h609140 =
(csrf_mcycle_ehr_data_dummy2_0$Q_OUT &&
csrf_mcycle_ehr_data_dummy2_1$Q_OUT) ?
csrf_mcycle_ehr_data_rl :
64'd0 ;
assign n__read__h609331 =
(csrf_minstret_ehr_data_dummy2_0$Q_OUT &&
csrf_minstret_ehr_data_dummy2_1$Q_OUT) ?
csrf_minstret_ehr_data_rl :
64'd0 ;
assign n__read__h6604 =
csrf_mcycle_ehr_data_dummy2_1$Q_OUT ?
(csrf_mcycle_ehr_data_lat_0$whas ?
upd__h6718 :
csrf_mcycle_ehr_data_rl) :
64'd0 ;
assign n__read__h709918 =
csrf_minstret_ehr_data_dummy2_1$Q_OUT ?
IF_csrf_minstret_ehr_data_lat_0_whas_THEN_csrf_ETC___d8 :
64'd0 ;
assign next_deqP___1__h294647 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP +
3'd1 ;
assign next_deqP___1__h302643 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP + 1'd1 ;
assign next_deqP___1__h308924 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP + 1'd1 ;
assign next_deqP___1__h316778 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP + 1'd1 ;
assign next_deqP___1__h326835 = coreFix_memExe_memRespLdQ_deqP + 1'd1 ;
assign next_deqP___1__h330060 = coreFix_memExe_forwardQ_deqP + 1'd1 ;
assign next_pc__h709264 =
(rob$deqPort_0_deq_data[97:96] == 2'd0) ?
rob$deqPort_0_deq_data[95:32] :
rob$deqPort_0_deq_data[282:219] + 64'd4 ;
assign out___1_sfd__h480048 = { f1_sfd__h479985, 29'd0 } ;
assign out___1_sfd__h519042 = { f2_sfd__h518979, 29'd0 } ;
assign out___1_sfd__h558346 = { f3_sfd__h558283, 29'd0 } ;
assign out_exp__h352559 =
sfdin__h352034[34] ?
_theResult___exp__h352556 :
_theResult___fst_exp__h352040 ;
assign out_exp__h361141 =
_theResult___snd__h360647[34] ?
_theResult___exp__h361138 :
_theResult___fst_exp__h360696 ;
assign out_exp__h370325 =
sfdin__h369800[34] ?
_theResult___exp__h370322 :
_theResult___fst_exp__h369806 ;
assign out_exp__h378961 =
_theResult___snd__h378437[34] ?
_theResult___exp__h378958 :
_theResult___fst_exp__h378491 ;
assign out_exp__h398256 =
sfdin__h397731[34] ?
_theResult___exp__h398253 :
_theResult___fst_exp__h397737 ;
assign out_exp__h406838 =
_theResult___snd__h406344[34] ?
_theResult___exp__h406835 :
_theResult___fst_exp__h406393 ;
assign out_exp__h416022 =
sfdin__h415497[34] ?
_theResult___exp__h416019 :
_theResult___fst_exp__h415503 ;
assign out_exp__h424658 =
_theResult___snd__h424134[34] ?
_theResult___exp__h424655 :
_theResult___fst_exp__h424188 ;
assign out_exp__h443951 =
sfdin__h443426[34] ?
_theResult___exp__h443948 :
_theResult___fst_exp__h443432 ;
assign out_exp__h452533 =
_theResult___snd__h452039[34] ?
_theResult___exp__h452530 :
_theResult___fst_exp__h452088 ;
assign out_exp__h461717 =
sfdin__h461192[34] ?
_theResult___exp__h461714 :
_theResult___fst_exp__h461198 ;
assign out_exp__h470353 =
_theResult___snd__h469829[34] ?
_theResult___exp__h470350 :
_theResult___fst_exp__h469883 ;
assign out_exp__h500030 =
_theResult___snd__h499323[5] ?
_theResult___exp__h500027 :
_theResult___fst_exp__h499372 ;
assign out_exp__h509681 =
sfdin__h508943[5] ?
_theResult___exp__h509678 :
_theResult___fst_exp__h508949 ;
assign out_exp__h518465 =
_theResult___snd__h517728[5] ?
_theResult___exp__h518462 :
_theResult___fst_exp__h517782 ;
assign out_exp__h538883 =
_theResult___snd__h538176[5] ?
_theResult___exp__h538880 :
_theResult___fst_exp__h538225 ;
assign out_exp__h548534 =
sfdin__h547796[5] ?
_theResult___exp__h548531 :
_theResult___fst_exp__h547802 ;
assign out_exp__h557318 =
_theResult___snd__h556581[5] ?
_theResult___exp__h557315 :
_theResult___fst_exp__h556635 ;
assign out_exp__h578187 =
_theResult___snd__h577480[5] ?
_theResult___exp__h578184 :
_theResult___fst_exp__h577529 ;
assign out_exp__h587838 =
sfdin__h587100[5] ?
_theResult___exp__h587835 :
_theResult___fst_exp__h587106 ;
assign out_exp__h596622 =
_theResult___snd__h595885[5] ?
_theResult___exp__h596619 :
_theResult___fst_exp__h595939 ;
assign out_f_exp__h379337 =
(_theResult___exp__h379060 == 8'd255 &&
_theResult___sfd__h379061 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h379051 ;
assign out_f_exp__h425034 =
(_theResult___exp__h424757 == 8'd255 &&
_theResult___sfd__h424758 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h424748 ;
assign out_f_exp__h470729 =
(_theResult___exp__h470452 == 8'd255 &&
_theResult___sfd__h470453 != 23'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047) ?
8'd255 :
_theResult___fst_exp__h470443 ;
assign out_f_sfd__h379338 =
(_theResult___exp__h379060 == 8'd255 &&
_theResult___sfd__h379061 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h379061 ;
assign out_f_sfd__h425035 =
(_theResult___exp__h424757 == 8'd255 &&
_theResult___sfd__h424758 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h424758 ;
assign out_f_sfd__h470730 =
(_theResult___exp__h470452 == 8'd255 &&
_theResult___sfd__h470453 != 23'd0) ?
23'd4194304 :
_theResult___sfd__h470453 ;
assign out_sfd__h352560 =
sfdin__h352034[34] ?
_theResult___sfd__h352557 :
sfdin__h352034[56:34] ;
assign out_sfd__h361142 =
_theResult___snd__h360647[34] ?
_theResult___sfd__h361139 :
_theResult___snd__h360647[56:34] ;
assign out_sfd__h370326 =
sfdin__h369800[34] ?
_theResult___sfd__h370323 :
sfdin__h369800[56:34] ;
assign out_sfd__h378962 =
_theResult___snd__h378437[34] ?
_theResult___sfd__h378959 :
_theResult___snd__h378437[56:34] ;
assign out_sfd__h398257 =
sfdin__h397731[34] ?
_theResult___sfd__h398254 :
sfdin__h397731[56:34] ;
assign out_sfd__h406839 =
_theResult___snd__h406344[34] ?
_theResult___sfd__h406836 :
_theResult___snd__h406344[56:34] ;
assign out_sfd__h416023 =
sfdin__h415497[34] ?
_theResult___sfd__h416020 :
sfdin__h415497[56:34] ;
assign out_sfd__h424659 =
_theResult___snd__h424134[34] ?
_theResult___sfd__h424656 :
_theResult___snd__h424134[56:34] ;
assign out_sfd__h443952 =
sfdin__h443426[34] ?
_theResult___sfd__h443949 :
sfdin__h443426[56:34] ;
assign out_sfd__h452534 =
_theResult___snd__h452039[34] ?
_theResult___sfd__h452531 :
_theResult___snd__h452039[56:34] ;
assign out_sfd__h461718 =
sfdin__h461192[34] ?
_theResult___sfd__h461715 :
sfdin__h461192[56:34] ;
assign out_sfd__h470354 =
_theResult___snd__h469829[34] ?
_theResult___sfd__h470351 :
_theResult___snd__h469829[56:34] ;
assign out_sfd__h500031 =
_theResult___snd__h499323[5] ?
_theResult___sfd__h500028 :
_theResult___snd__h499323[56:5] ;
assign out_sfd__h509682 =
sfdin__h508943[5] ?
_theResult___sfd__h509679 :
sfdin__h508943[56:5] ;
assign out_sfd__h518466 =
_theResult___snd__h517728[5] ?
_theResult___sfd__h518463 :
_theResult___snd__h517728[56:5] ;
assign out_sfd__h538884 =
_theResult___snd__h538176[5] ?
_theResult___sfd__h538881 :
_theResult___snd__h538176[56:5] ;
assign out_sfd__h548535 =
sfdin__h547796[5] ?
_theResult___sfd__h548532 :
sfdin__h547796[56:5] ;
assign out_sfd__h557319 =
_theResult___snd__h556581[5] ?
_theResult___sfd__h557316 :
_theResult___snd__h556581[56:5] ;
assign out_sfd__h578188 =
_theResult___snd__h577480[5] ?
_theResult___sfd__h578185 :
_theResult___snd__h577480[56:5] ;
assign out_sfd__h587839 =
sfdin__h587100[5] ?
_theResult___sfd__h587836 :
sfdin__h587100[56:5] ;
assign out_sfd__h596623 =
_theResult___snd__h595885[5] ?
_theResult___sfd__h596620 :
_theResult___snd__h595885[56:5] ;
assign pend_ints__h647724 =
{ _0_CONCAT_csrf_external_int_en_vec_3_read__1651_ETC___d12740,
csrf_software_int_en_vec_3 & csrf_software_int_pend_vec_3,
1'd0,
csrf_software_int_en_vec_1 & csrf_software_int_pend_vec_1,
csrf_software_int_en_vec_0 & csrf_software_int_pend_vec_0 } ;
assign prv__h715726 = csrf_prv_reg ;
assign prv__h715770 = csrf_mprv_reg ? csrf_mpp_reg : csrf_prv_reg ;
assign q___1__h473725 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64] ;
assign r1__read_BITS_13_TO_0___h648274 =
{ 4'd0,
csrf_mideleg_11_reg,
1'b0,
csrf_mideleg_9_7_reg,
1'b0,
csrf_mideleg_5_3_reg,
1'b0 } ;
assign r1__read_BITS_13_TO_12___h651774 = csrf_fs_reg ;
assign r1__read_BIT_20___h652434 = csrf_tw_reg ;
assign r1__read__h610308 = { r1__read__h610310, csrf_ie_vec_1 } ;
assign r1__read__h610310 = { r1__read__h610312, 2'b0 } ;
assign r1__read__h610312 = { r1__read__h610314, csrf_prev_ie_vec_0 } ;
assign r1__read__h610314 = { r1__read__h610316, csrf_prev_ie_vec_1 } ;
assign r1__read__h610316 = { r1__read__h610318, 2'b0 } ;
assign r1__read__h610318 = { r1__read__h610320, csrf_spp_reg } ;
assign r1__read__h610320 = { r1__read__h610322, 4'b0 } ;
assign r1__read__h610322 = { r1__read__h610324, csrf_fs_reg } ;
assign r1__read__h610324 = { r1__read__h610326, 2'd0 } ;
assign r1__read__h610326 = { r1__read__h610328, 1'b0 } ;
assign r1__read__h610328 = { r1__read__h610330, csrf_sum_reg } ;
assign r1__read__h610330 = { r1__read__h610332, csrf_mxr_reg } ;
assign r1__read__h610332 = { r1__read__h610334, 12'b0 } ;
assign r1__read__h610334 = { r1__read__h610336, 2'b10 } ;
assign r1__read__h610336 = { r__h610340, 29'b0 } ;
assign r1__read__h610712 =
{ r1__read__h610714, csrf_software_int_en_vec_1 } ;
assign r1__read__h610714 = { r1__read__h610716, 2'b0 } ;
assign r1__read__h610716 = { r1__read__h610718, csrf_timer_int_en_vec_0 } ;
assign r1__read__h610718 = { r1__read__h610720, csrf_timer_int_en_vec_1 } ;
assign r1__read__h610720 = { r1__read__h610722, 2'b0 } ;
assign r1__read__h610722 =
{ r1__read__h610724, csrf_external_int_en_vec_0 } ;
assign r1__read__h610724 = { 54'b0, csrf_external_int_en_vec_1 } ;
assign r1__read__h611242 = { csrf_stvec_base_hi_reg, 1'b0 } ;
assign r1__read__h611247 = { r1__read__h611249, csrf_scounteren_tm_reg } ;
assign r1__read__h611249 = { 61'd0, csrf_scounteren_ir_reg } ;
assign r1__read__h611260 = { csrf_scause_interrupt_reg, 59'b0 } ;
assign r1__read__h611266 =
{ r1__read__h611268, csrf_software_int_pend_vec_1 } ;
assign r1__read__h611268 = { r1__read__h611270, 2'b0 } ;
assign r1__read__h611270 =
{ r1__read__h611272, csrf_timer_int_pend_vec_0 } ;
assign r1__read__h611272 =
{ r1__read__h611274, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h611274 = { r1__read__h611276, 2'b0 } ;
assign r1__read__h611276 =
{ r1__read__h611278, csrf_external_int_pend_vec_0 } ;
assign r1__read__h611278 = { 54'b0, csrf_external_int_pend_vec_1 } ;
assign r1__read__h611496 = { vm_mode_reg__read__h611502, 16'd0 } ;
assign r1__read__h611519 = { r1__read__h611521, csrf_ie_vec_1 } ;
assign r1__read__h611521 = { r1__read__h611523, 1'b0 } ;
assign r1__read__h611523 = { r1__read__h611525, csrf_ie_vec_3 } ;
assign r1__read__h611525 = { r1__read__h611527, csrf_prev_ie_vec_0 } ;
assign r1__read__h611527 = { r1__read__h611529, csrf_prev_ie_vec_1 } ;
assign r1__read__h611529 = { r1__read__h611531, 1'b0 } ;
assign r1__read__h611531 = { r1__read__h611533, csrf_prev_ie_vec_3 } ;
assign r1__read__h611533 = { r1__read__h611535, csrf_spp_reg } ;
assign r1__read__h611535 = { r1__read__h611537, 2'b0 } ;
assign r1__read__h611537 = { r1__read__h611539, csrf_mpp_reg } ;
assign r1__read__h611539 = { r1__read__h611541, csrf_fs_reg } ;
assign r1__read__h611541 = { r1__read__h611543, 2'd0 } ;
assign r1__read__h611543 = { r1__read__h611545, csrf_mprv_reg } ;
assign r1__read__h611545 = { r1__read__h611547, csrf_sum_reg } ;
assign r1__read__h611547 = { r1__read__h611549, csrf_mxr_reg } ;
assign r1__read__h611549 = { r1__read__h611551, csrf_tvm_reg } ;
assign r1__read__h611551 = { r1__read__h611553, csrf_tw_reg } ;
assign r1__read__h611553 = { r1__read__h611555, csrf_tsr_reg } ;
assign r1__read__h611555 = { r1__read__h611557, 9'b0 } ;
assign r1__read__h611557 = { r1__read__h611559, 2'b10 } ;
assign r1__read__h611559 = { r1__read__h611561, 2'b10 } ;
assign r1__read__h611561 = { r__h610340, 27'b0 } ;
assign r1__read__h611644 = { r1__read__h611646, 1'b0 } ;
assign r1__read__h611646 = { r1__read__h611648, csrf_medeleg_13_11_reg } ;
assign r1__read__h611648 = { r1__read__h611650, 1'b0 } ;
assign r1__read__h611650 = { 48'b0, csrf_medeleg_15_reg } ;
assign r1__read__h611661 = { r1__read__h611663, 1'b0 } ;
assign r1__read__h611663 = { r1__read__h611665, csrf_mideleg_5_3_reg } ;
assign r1__read__h611665 = { r1__read__h611667, 1'b0 } ;
assign r1__read__h611667 = { r1__read__h611669, csrf_mideleg_9_7_reg } ;
assign r1__read__h611669 = { r1__read__h611671, 1'b0 } ;
assign r1__read__h611671 = { 52'b0, csrf_mideleg_11_reg } ;
assign r1__read__h611685 =
{ r1__read__h611687, csrf_software_int_en_vec_1 } ;
assign r1__read__h611687 = { r1__read__h611689, 1'b0 } ;
assign r1__read__h611689 =
{ r1__read__h611691, csrf_software_int_en_vec_3 } ;
assign r1__read__h611691 = { r1__read__h611693, csrf_timer_int_en_vec_0 } ;
assign r1__read__h611693 = { r1__read__h611695, csrf_timer_int_en_vec_1 } ;
assign r1__read__h611695 = { r1__read__h611697, 1'b0 } ;
assign r1__read__h611697 = { r1__read__h611699, csrf_timer_int_en_vec_3 } ;
assign r1__read__h611699 =
{ r1__read__h611701, csrf_external_int_en_vec_0 } ;
assign r1__read__h611701 =
{ r1__read__h611703, csrf_external_int_en_vec_1 } ;
assign r1__read__h611703 = { r1__read__h611705, 1'b0 } ;
assign r1__read__h611705 = { 52'b0, csrf_external_int_en_vec_3 } ;
assign r1__read__h611796 = { csrf_mtvec_base_hi_reg, 1'b0 } ;
assign r1__read__h611801 = { r1__read__h611803, csrf_mcounteren_tm_reg } ;
assign r1__read__h611803 = { 61'd0, csrf_mcounteren_ir_reg } ;
assign r1__read__h611814 = { csrf_mcause_interrupt_reg, 59'b0 } ;
assign r1__read__h611820 =
{ r1__read__h611822, csrf_software_int_pend_vec_1 } ;
assign r1__read__h611822 = { r1__read__h611824, 1'b0 } ;
assign r1__read__h611824 =
{ r1__read__h611826, csrf_software_int_pend_vec_3 } ;
assign r1__read__h611826 =
{ r1__read__h611828, csrf_timer_int_pend_vec_0 } ;
assign r1__read__h611828 =
{ r1__read__h611830, csrf_timer_int_pend_vec_1 } ;
assign r1__read__h611830 = { r1__read__h611832, 1'b0 } ;
assign r1__read__h611832 =
{ r1__read__h611834, csrf_timer_int_pend_vec_3 } ;
assign r1__read__h611834 =
{ r1__read__h611836, csrf_external_int_pend_vec_0 } ;
assign r1__read__h611836 =
{ r1__read__h611838, csrf_external_int_pend_vec_1 } ;
assign r1__read__h611838 = { r1__read__h611840, 1'b0 } ;
assign r1__read__h611840 = { 52'b0, csrf_external_int_pend_vec_3 } ;
assign rVal1__h479605 = coreFix_fpuMulDivExe_0_regToExeQ$first[203:140] ;
assign rVal2__h479606 = coreFix_fpuMulDivExe_0_regToExeQ$first[139:76] ;
assign r___1__h473751 =
64'd0 -
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0] ;
assign r__h610340 = csrf_fs_reg == 2'b11 ;
assign regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858 =
regRenamingTable$RDY_rename_0_getRename &&
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 &&
(fetchStage$pipelines_0_first[199:195] == 5'd14 ||
coreFix_memExe_rsMem$RDY_enq) ;
assign regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939 =
regRenamingTable$RDY_rename_1_getRename &&
(!fetchStage$pipelines_0_canDeq ||
NOT_specTagManager_canClaim__3327_3418_OR_NOT__ETC___d13924) &&
_0_OR_NOT_fetchStage_pipelines_1_first__2706_BI_ETC___d13937 ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 =
regRenamingTable$rename_0_canRename &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13353 ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 =
regRenamingTable$rename_0_canRename &&
fetchStage$pipelines_0_first[199:195] != 5'd0 &&
fetchStage$pipelines_0_first[199:195] != 5'd21 &&
fetchStage$pipelines_0_first[199:195] != 5'd17 &&
fetchStage$pipelines_0_first[199:195] != 5'd18 &&
fetchStage$pipelines_0_first[199:195] != 5'd13 &&
fetchStage$pipelines_0_first[199:195] != 5'd16 &&
fetchStage$pipelines_0_first[199:195] != 5'd15 &&
fetchStage$pipelines_0_first[199:195] != 5'd19 &&
fetchStage$pipelines_0_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_0_first__2697_BIT_68__ETC___d13403 ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13419 =
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ||
!specTagManager$canClaim ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13740 =
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13405 &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 ||
!coreFix_memExe_rsMem$canEnq ||
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d13887 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 &&
fetchStage$pipelines_0_first[194:192] == 3'd1 ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14029 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq &&
(fetchStage$pipelines_0_first[194:192] == 3'd3 ||
fetchStage$pipelines_0_first[194:192] == 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14035 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 &&
fetchStage$pipelines_0_first[199:195] != 5'd14 ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14055 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 &&
(fetchStage$pipelines_0_first[191:189] == 3'd0 ||
fetchStage$pipelines_0_first[191:189] == 3'd2) ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14063 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 &&
fetchStage$pipelines_0_first[191:189] != 3'd0 &&
fetchStage$pipelines_0_first[191:189] != 3'd2 ;
assign regRenamingTable_rename_0_canRename__3329_AND__ETC___d14209 =
regRenamingTable$rename_0_canRename &&
!checkForException___d12942[4] &&
rob$enqPort_0_canEnq &&
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 ;
assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13653 ;
assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13795 ;
assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_renameStage_rg_m_halt_req_2724_BIT_4_2725__ETC___d13813 ;
assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 =
regRenamingTable$rename_1_canRename &&
fetchStage$pipelines_1_first[199:195] != 5'd0 &&
fetchStage$pipelines_1_first[199:195] != 5'd21 &&
fetchStage$pipelines_1_first[199:195] != 5'd17 &&
fetchStage$pipelines_1_first[199:195] != 5'd18 &&
fetchStage$pipelines_1_first[199:195] != 5'd13 &&
fetchStage$pipelines_1_first[199:195] != 5'd16 &&
fetchStage$pipelines_1_first[199:195] != 5'd15 &&
fetchStage$pipelines_1_first[199:195] != 5'd19 &&
fetchStage$pipelines_1_first[199:195] != 5'd20 &&
NOT_fetchStage_pipelines_1_first__2706_BIT_68__ETC___d14117 ;
assign regRenamingTable_rename_1_canRename__3456_AND__ETC___d14163 =
regRenamingTable_rename_1_canRename__3456_AND__ETC___d14119 &&
(fetchStage$pipelines_1_first[194:192] == 3'd3 ||
fetchStage$pipelines_1_first[194:192] == 3'd4) &&
(!fetchStage$pipelines_0_canDeq ||
!regRenamingTable$rename_0_canRename ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 ||
fetchStage$pipelines_0_first[194:192] != 3'd3 &&
fetchStage$pipelines_0_first[194:192] != 3'd4) &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ;
assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000 =
renameStage_rg_m_halt_req[4] ||
!fetchStage$pipelines_0_first[68] &&
(IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15]) ;
assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13229 =
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_N_ETC___d13000 ||
(fetchStage$pipelines_0_first[68] ?
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 :
IF_checkForException_2942_BIT_4_2943_THEN_IF_c_ETC___d13091) ==
4'd3 ;
assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13676 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13673 ||
!rob$enqPort_0_canEnq ||
!epochManager$checkEpoch_0_check ;
assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13716 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_1_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d13710 ||
!rob$enqPort_1_canEnq ||
!epochManager$checkEpoch_1_check ||
csrf_rg_dcsr_read__1700_BIT_2_2994_OR_NOT_fetc_ETC___d13424 ;
assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[0] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[1] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[2] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[3] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[4] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[5] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[6] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[7] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[8] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[9] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[10] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[11] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[12] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[13] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[14] ||
IF_IF_NOT_csrf_prv_reg_read__2727_EQ_3_2728_27_ETC___d12767[15] ;
assign renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13837 =
renameStage_rg_m_halt_req[4] ||
fetchStage$pipelines_0_first[68] ||
checkForException___d12942[4] ||
!rob$enqPort_0_canEnq ;
assign renaming_spec_bits__h678574 =
fetchStage$pipelines_0_canDeq ?
y_avValue_fst__h675037 :
specTagManager$currentSpecBits ;
assign res_data__h335713 = { 32'hFFFFFFFF, x__h335728 } ;
assign res_data__h335718 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:5] } ;
assign res_data__h381415 = { 32'hFFFFFFFF, x__h381430 } ;
assign res_data__h381420 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:5] } ;
assign res_data__h427110 = { 32'hFFFFFFFF, x__h427125 } ;
assign res_data__h427115 =
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[33] ^
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68],
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] ==
11'd2047 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) ?
63'h7FF8000000000000 :
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:5] } ;
assign res_fflags__h335714 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5198,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5209,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5225,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5238,
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_fma_r_ETC___d5251 } ;
assign res_fflags__h381416 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399003 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6590,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399003 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6601,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399003 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6617,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399003 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6630,
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
(value_BIT_52___h399003 ||
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_div_r_ETC___d6643 } ;
assign res_fflags__h427111 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[38:34] |
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[4:0] |
{ (coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7982,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d7993,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8009,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8022,
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] ==
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd2047 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
(coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0 ||
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] !=
52'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_double_sqrt__ETC___d8035 } ;
assign resp_addr__h289818 =
{ coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getSlot[52:1],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$sendRsToP_cRq_getRq[95:84] } ;
assign result__h362181 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d4554[0] |
guard__h362176 } ;
assign result__h407878 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d5946[0] |
guard__h407873 } ;
assign result__h453573 =
{ _0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[56:1],
_0b0_CONCAT_NOT_coreFix_fpuMulDivExe_0_fpuExec__ETC___d7338[0] |
guard__h453568 } ;
assign result__h501326 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d8650[0] |
guard__h501321 } ;
assign result__h540179 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d10135[0] |
guard__h540174 } ;
assign result__h579483 =
{ _0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365[56:1],
_0b0_CONCAT_NOT_IF_coreFix_fpuMulDivExe_0_regTo_ETC___d9365[0] |
guard__h579478 } ;
assign result__h643303 = w__h643298 & y__h643332 ;
assign result__h643354 = ~x__h643353 ;
assign rg_core_run_state_read__2990_EQ_2_2991_AND_NOT_ETC___d15247 =
rg_core_run_state == 2'd2 && !flush_reservation && !flush_tlbs &&
!update_vm_info &&
fetchStage$iTlbIfc_flush_done &&
coreFix_memExe_dTlb$flush_done &&
!flush_caches ;
assign rob_RDY_deqPort_0_deq_data__4234_AND_rob_RDY_d_ETC___d14689 =
rob$RDY_deqPort_0_deq_data && rob$RDY_deqPort_0_deq &&
regRenamingTable$RDY_commit_0_commit &&
v_f_to_TV_0$FULL_N &&
fetchStage$iTlbIfc_noPendingReq &&
coreFix_memExe_dTlb$noPendingReq &&
NOT_rob_deqPort_0_deq_data__4237_BITS_186_TO_1_ETC___d14684 ;
assign rob_RDY_enqPort_0_enq__2719_AND_regRenamingTab_ETC___d13239 =
rob$RDY_enqPort_0_enq &&
regRenamingTable$RDY_rename_0_claimRename &&
regRenamingTable$RDY_rename_0_getRename &&
fetchStage$RDY_pipelines_0_first &&
fetchStage$RDY_pipelines_0_deq &&
(fetchStage$pipelines_0_first[194:192] != 3'd0 ||
coreFix_aluExe_0_rsAlu$RDY_enq) ;
assign rob_deqPort_0_deq_data__4237_BIT_166_4253_CONC_ETC___d14302 =
{ rob$deqPort_0_deq_data[166],
rob$deqPort_0_deq_data[166] ?
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 :
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 } ;
assign robdeqPort_0_deq_data_BITS_95_TO_32__q270 =
rob$deqPort_0_deq_data[95:32] ;
assign rs1__h651905 =
(fetchStage$pipelines_0_first[88] &&
!fetchStage$pipelines_0_first[87]) ?
fetchStage$pipelines_0_first[86:82] :
5'd0 ;
assign satp_csr__read__h607864 = { r1__read__h611496, csrf_ppn_reg } ;
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 =
(sbCons$lazyLookup_2_get[2] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8247 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8264) &&
(sbCons$lazyLookup_2_get[1] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8271 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8288) ;
assign sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8292 =
(sbCons$lazyLookup_2_get[3] ||
IF_coreFix_fpuMulDivExe_0_dispToRegQ_RDY_first_ETC___d8214 &&
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8240) &&
sbCons_lazyLookup_2_get_coreFix_fpuMulDivExe_0_ETC___d8291 ;
assign sbCons_lazyLookup_3_get_coreFix_memExe_dispToR_ETC___d1631 =
(sbCons$lazyLookup_3_get[3] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1578 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1604) &&
(sbCons$lazyLookup_3_get[2] ||
IF_coreFix_memExe_dispToRegQ_RDY_first__548_AN_ETC___d1611 &&
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1628) ;
assign sbIdx__h156870 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[65:64] :
coreFix_memExe_reqStQ_data_0_rl[65:64]) :
2'd0 ;
assign scause_csr__read__h607662 =
{ r1__read__h611260, csrf_scause_code_reg } ;
assign scounteren_csr__read__h607524 =
{ r1__read__h611247, csrf_scounteren_cy_reg } ;
assign sfd__h336324 = { value__h344551, 3'd0 } ;
assign sfd__h352132 =
{ 1'b0,
_theResult___fst_exp__h352040 != 8'd0,
sfdin__h352034[56:34] } +
25'd1 ;
assign sfd__h360714 =
{ 1'b0,
_theResult___fst_exp__h360696 != 8'd0,
_theResult___snd__h360647[56:34] } +
25'd1 ;
assign sfd__h369898 =
{ 1'b0,
_theResult___fst_exp__h369806 != 8'd0,
sfdin__h369800[56:34] } +
25'd1 ;
assign sfd__h378510 =
{ 1'b0,
_theResult___fst_exp__h378491 != 8'd0,
_theResult___snd__h378437[56:34] } +
25'd1 ;
assign sfd__h382026 = { value__h390248, 3'd0 } ;
assign sfd__h397829 =
{ 1'b0,
_theResult___fst_exp__h397737 != 8'd0,
sfdin__h397731[56:34] } +
25'd1 ;
assign sfd__h406411 =
{ 1'b0,
_theResult___fst_exp__h406393 != 8'd0,
_theResult___snd__h406344[56:34] } +
25'd1 ;
assign sfd__h415595 =
{ 1'b0,
_theResult___fst_exp__h415503 != 8'd0,
sfdin__h415497[56:34] } +
25'd1 ;
assign sfd__h424207 =
{ 1'b0,
_theResult___fst_exp__h424188 != 8'd0,
_theResult___snd__h424134[56:34] } +
25'd1 ;
assign sfd__h427721 = { value__h435943, 3'd0 } ;
assign sfd__h443524 =
{ 1'b0,
_theResult___fst_exp__h443432 != 8'd0,
sfdin__h443426[56:34] } +
25'd1 ;
assign sfd__h452106 =
{ 1'b0,
_theResult___fst_exp__h452088 != 8'd0,
_theResult___snd__h452039[56:34] } +
25'd1 ;
assign sfd__h461290 =
{ 1'b0,
_theResult___fst_exp__h461198 != 8'd0,
sfdin__h461192[56:34] } +
25'd1 ;
assign sfd__h469902 =
{ 1'b0,
_theResult___fst_exp__h469883 != 8'd0,
_theResult___snd__h469829[56:34] } +
25'd1 ;
assign sfd__h480346 = { value__h484929, 32'd0 } ;
assign sfd__h499390 =
{ 1'b0,
_theResult___fst_exp__h499372 != 11'd0,
_theResult___snd__h499323[56:5] } +
54'd1 ;
assign sfd__h509041 =
{ 1'b0,
_theResult___fst_exp__h508949 != 11'd0,
sfdin__h508943[56:5] } +
54'd1 ;
assign sfd__h517801 =
{ 1'b0,
_theResult___fst_exp__h517782 != 11'd0,
_theResult___snd__h517728[56:5] } +
54'd1 ;
assign sfd__h519340 = { value__h523782, 32'd0 } ;
assign sfd__h538243 =
{ 1'b0,
_theResult___fst_exp__h538225 != 11'd0,
_theResult___snd__h538176[56:5] } +
54'd1 ;
assign sfd__h547894 =
{ 1'b0,
_theResult___fst_exp__h547802 != 11'd0,
sfdin__h547796[56:5] } +
54'd1 ;
assign sfd__h556654 =
{ 1'b0,
_theResult___fst_exp__h556635 != 11'd0,
_theResult___snd__h556581[56:5] } +
54'd1 ;
assign sfd__h558644 = { value__h563086, 32'd0 } ;
assign sfd__h577547 =
{ 1'b0,
_theResult___fst_exp__h577529 != 11'd0,
_theResult___snd__h577480[56:5] } +
54'd1 ;
assign sfd__h587198 =
{ 1'b0,
_theResult___fst_exp__h587106 != 11'd0,
sfdin__h587100[56:5] } +
54'd1 ;
assign sfd__h595958 =
{ 1'b0,
_theResult___fst_exp__h595939 != 11'd0,
_theResult___snd__h595885[56:5] } +
54'd1 ;
assign sfdin__h352034 =
_theResult____h343929[56] ?
_theResult___snd__h352051 :
_theResult___snd__h352062 ;
assign sfdin__h369800 =
_theResult____h361568[56] ?
_theResult___snd__h369817 :
_theResult___snd__h369828 ;
assign sfdin__h397731 =
_theResult____h389628[56] ?
_theResult___snd__h397748 :
_theResult___snd__h397759 ;
assign sfdin__h415497 =
_theResult____h407265[56] ?
_theResult___snd__h415514 :
_theResult___snd__h415525 ;
assign sfdin__h443426 =
_theResult____h435323[56] ?
_theResult___snd__h443443 :
_theResult___snd__h443454 ;
assign sfdin__h461192 =
_theResult____h452960[56] ?
_theResult___snd__h461209 :
_theResult___snd__h461220 ;
assign sfdin__h508943 =
_theResult____h500713[56] ?
_theResult___snd__h508960 :
_theResult___snd__h508971 ;
assign sfdin__h547796 =
_theResult____h539566[56] ?
_theResult___snd__h547813 :
_theResult___snd__h547824 ;
assign sfdin__h587100 =
_theResult____h578870[56] ?
_theResult___snd__h587117 :
_theResult___snd__h587128 ;
assign shiftData__h181140 =
coreFix_memExe_regToExeQ$first[75:12] << x__h181272 ;
assign sie_csr__read__h607428 =
{ r1__read__h610712, csrf_software_int_en_vec_0 } ;
assign sip_csr__read__h607801 =
{ r1__read__h611266, csrf_software_int_pend_vec_0 } ;
assign spec_bits__h681701 = specTagManager$currentSpecBits | y__h681714 ;
assign sstatus_csr__read__h607359 = { r1__read__h610308, csrf_ie_vec_0 } ;
assign stvec_csr__read__h607471 =
{ r1__read__h611242, csrf_stvec_mode_low_reg } ;
assign upd__h3992 =
WILL_FIRE_RL_commitStage_doCommitSystemInst ?
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_1 :
MUX_csrf_minstret_ehr_data_lat_1$wset_1__VAL_2 ;
assign upd__h5309 = n__read__h6604 + 64'd1 ;
assign upd__h6718 =
MUX_csrf_mcycle_ehr_data_dummy2_0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign upd__h710029 =
MUX_csrf_minstret_ehr_data_dummy2_0$write_1__SEL_1 ?
f_csr_reqs$D_OUT[63:0] :
rob$deqPort_0_deq_data[95:32] ;
assign v__h293788 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqRetr_ETC___d3027) ?
v__h294019 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ;
assign v__h294019 =
(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP ==
3'd7) ?
3'd0 :
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP +
3'd1 ;
assign v__h297133 =
(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_fromPQ__ETC___d3134) ?
v__h297651 :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP ;
assign v__h297651 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP + 1'd1 ;
assign v__h307647 =
(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rqToPQ__ETC___d3305) ?
v__h307878 :
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP ;
assign v__h307878 = coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP + 1'd1 ;
assign v__h311523 =
(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_dMem_cache_m_banks_0_rsToPQ__ETC___d3401) ?
v__h311754 :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP ;
assign v__h311754 = coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP + 1'd1 ;
assign v__h326124 =
(coreFix_memExe_memRespLdQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_memRespLdQ_enqReq_lat_1_whas_ETC___d3630) ?
v__h326355 :
coreFix_memExe_memRespLdQ_enqP ;
assign v__h326355 = coreFix_memExe_memRespLdQ_enqP + 1'd1 ;
assign v__h329349 =
(coreFix_memExe_forwardQ_enqReq_dummy2_2$Q_OUT &&
IF_coreFix_memExe_forwardQ_enqReq_lat_1_whas___ETC___d3724) ?
v__h329580 :
coreFix_memExe_forwardQ_enqP ;
assign v__h329580 = coreFix_memExe_forwardQ_enqP + 1'd1 ;
assign v__h601727 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas ?
v__h601737 :
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit ;
assign v__h601737 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit + 2'd1 ;
assign v__h602372 = v__h601727 - 2'd1 ;
assign v__h605746 =
sbCons$lazyLookup_1_get[3] ? rf$read_1_rd1 : y_avValue__h606651 ;
assign v__h630040 =
sbCons$lazyLookup_0_get[3] ? rf$read_0_rd1 : y_avValue__h630793 ;
assign vaddr__h181135 =
coreFix_memExe_regToExeQ$first[139:76] +
{ {32{coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12[31]}},
coreFix_memExe_regToExeQfirst_BITS_189_TO_158__q12 } ;
assign value_BIT_52___h399003 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[67:57] !=
11'd0 ;
assign value__h344551 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[56:5] } ;
assign value__h390248 =
{ 1'b0,
value_BIT_52___h399003,
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[56:5] } ;
assign value__h435943 =
{ 1'b0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[67:57] !=
11'd0,
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[56:5] } ;
assign value__h484929 = { 1'b0, f1_exp__h479984 != 8'd0, f1_sfd__h479985 } ;
assign value__h523782 = { 1'b0, f2_exp__h518978 != 8'd0, f2_sfd__h518979 } ;
assign value__h563086 = { 1'b0, f3_exp__h558282 != 8'd0, f3_sfd__h558283 } ;
assign vm_mode_reg__read__h611502 = { csrf_vm_mode_sv39_reg, 3'b0 } ;
assign w__h643298 =
coreFix_globalSpecUpdate_correctSpecTag_0$whas ?
result__h643354 :
12'd4095 ;
assign x__h153444 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[68:64] :
coreFix_memExe_reqLdQ_data_0_rl[68:64]) :
5'd0 ;
assign x__h153450 =
coreFix_memExe_reqLdQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLdQ_data_0_lat_0$whas ?
coreFix_memExe_reqLdQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqLdQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h156991 = { 3'd0, sbIdx__h156870 } ;
assign x__h156997 =
coreFix_memExe_reqStQ_data_0_dummy2_1$Q_OUT ?
(CAN_FIRE_RL_coreFix_memExe_doIssueSB ?
coreFix_memExe_reqStQ_data_0_lat_0$wget[63:0] :
coreFix_memExe_reqStQ_data_0_rl[63:0]) :
64'd0 ;
assign x__h159807 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h159811 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h161659 =
coreFix_memExe_reqLrScAmoQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_reqLrScAmoQ_data_0_lat_0$whas ?
coreFix_memExe_reqLrScAmoQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_reqLrScAmoQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h181049 =
sbCons$lazyLookup_3_get[3] ? rf$read_3_rd1 : y_avValue__h180137 ;
assign x__h181050 =
sbCons$lazyLookup_3_get[2] ? rf$read_3_rd2 : y_avValue__h180743 ;
assign x__h181272 = { vaddr__h181135[2:0], 3'b0 } ;
assign x__h18170 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[141:78] :
mmio_dataReqQ_enqReq_rl[141:78] ;
assign x__h191526 =
coreFix_memExe_dMem_cache_m_banks_0_processAmo[90] ?
curData__h190763[63:32] :
curData__h190763[31:0] ;
assign x__h20708 =
mmio_dataReqQ_enqReq_lat_0$whas ?
mmio_dataReqQ_enqReq_lat_0$wget[63:0] :
mmio_dataReqQ_enqReq_rl[63:0] ;
assign x__h285126 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[152:148] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[152:148]) :
5'd0 ;
assign x__h285138 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[147:84] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[147:84]) :
64'd0 ;
assign x__h286992 =
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_dummy2_1$Q_OUT ?
(coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_lat_0$wget[70:7] :
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl[70:7]) :
64'd0 ;
assign x__h299998 =
EN_dCacheToParent_fromP_enq ?
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_lat_0$wget[2:0] :
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl[2:0] ;
assign x__h335728 =
{ (_theResult___exp__h379060 != 8'd255 ||
_theResult___sfd__h379061 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5136,
out_f_exp__h379337,
out_f_sfd__h379338 } ;
assign x__h362278 =
sfd__h336324 << (x__h362311[11] ? 12'hAAA : x__h362311) ;
assign x__h362311 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d4550 ;
assign x__h381430 =
{ (_theResult___exp__h424757 != 8'd255 ||
_theResult___sfd__h424758 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6528,
out_f_exp__h425034,
out_f_sfd__h425035 } ;
assign x__h407975 =
sfd__h382026 << (x__h408008[11] ? 12'hAAA : x__h408008) ;
assign x__h408008 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d5942 ;
assign x__h427125 =
{ (_theResult___exp__h470452 != 8'd255 ||
_theResult___sfd__h470453 == 23'd0) &&
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7920,
out_f_exp__h470729,
out_f_sfd__h470730 } ;
assign x__h453670 =
sfd__h427721 << (x__h453703[11] ? 12'hAAA : x__h453703) ;
assign x__h453703 =
12'd57 -
_3970_MINUS_SEXT_coreFix_fpuMulDivExe_0_fpuExec_ETC___d7334 ;
assign x__h46077 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[141:78] :
mmio_cRqQ_enqReq_rl[141:78] ;
assign x__h479514 =
sbCons$lazyLookup_2_get[3] ? rf$read_2_rd1 : y_avValue__h476650 ;
assign x__h479515 =
sbCons$lazyLookup_2_get[2] ? rf$read_2_rd2 : y_avValue__h477258 ;
assign x__h479516 =
sbCons$lazyLookup_2_get[1] ? rf$read_2_rd3 : y_avValue__h477860 ;
assign x__h48613 =
mmio_cRqQ_enqReq_lat_0$whas ?
mmio_cRqQ_enqReq_lat_0$wget[63:0] :
mmio_cRqQ_enqReq_rl[63:0] ;
assign x__h501421 = sfd__h480346 << x__h501454 ;
assign x__h501454 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d8646 ;
assign x__h540274 = sfd__h519340 << x__h540307 ;
assign x__h540307 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d10131 ;
assign x__h579578 = sfd__h558644 << x__h579611 ;
assign x__h579611 =
12'd57 -
_3074_MINUS_SEXT_IF_coreFix_fpuMulDivExe_0_regT_ETC___d9361 ;
assign x__h601228 = a__h600792[63] ^ b__h600793[63] ;
assign x__h610293 = { csrf_frm_reg, csrf_fflags_reg } ;
assign x__h614524 =
coreFix_aluExe_1_dispToRegQ$first[131] ?
rVal1__h606861 :
v__h605746 ;
assign x__h614525 =
sbCons$lazyLookup_1_get[2] ? rf$read_1_rd2 : y_avValue__h612381 ;
assign x__h636385 =
coreFix_aluExe_0_dispToRegQ$first[131] ?
rVal1__h631001 :
v__h630040 ;
assign x__h636386 =
sbCons$lazyLookup_0_get[2] ? rf$read_0_rd2 : y_avValue__h634252 ;
assign x__h643302 = 12'd1 << coreFix_aluExe_1_exeToFinQ$first[15:12] ;
assign x__h643353 = 12'd1 << coreFix_aluExe_0_exeToFinQ$first[15:12] ;
assign x__h692236 =
(!rob$deqPort_0_deq_data[166] &&
(rob$deqPort_0_deq_data[165:162] == 4'd1 ||
rob$deqPort_0_deq_data[165:162] == 4'd12)) ?
rob$deqPort_0_deq_data[161:98] :
rob$deqPort_0_deq_data[95:32] ;
assign x__h700695 = { cause_code__h698062, 2'b0 } ;
assign x__h709324 = { 1'b0, csrf_spp_reg } ;
assign x__h712697 = commitStage_rg_serialnum + y__h712723 ;
assign x__h714333 =
NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ?
y_avValue_snd_snd_snd_fst__h714157 :
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 ;
assign x__h76022 = mmio_pRqQ_data_0[31:0] ;
assign x_addr__h311921 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$whas ?
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_lat_0$wget[578:515] :
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl[578:515] ;
assign x_data__h65871 =
EN_mmioToPlatform_pRq_enq ?
mmio_pRqQ_enqReq_lat_0$wget[31:0] :
mmio_pRqQ_enqReq_rl[31:0] ;
assign x_data_imm__h671051 = fetchStage$pipelines_0_first[159:128] ;
assign x_data_imm__h685982 = fetchStage$pipelines_1_first[159:128] ;
assign x_decodeInfo_frm__h651589 = csrf_frm_reg ;
assign x_quotient__h473040 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
64'hFFFFFFFFFFFFFFFF :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[9]) ?
q___1__h473725 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[127:64]) ;
assign x_reg_ifc__read__h607268 = { 63'd0, csrf_stats_module_doStats } ;
assign x_remainder__h473041 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[75] ?
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[74:11] :
((coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[10] &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tuser[8]) ?
r___1__h473751 :
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$m_axis_dout_tdata[63:0]) ;
assign y__h252650 =
{ coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[569:518],
coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[95:90] } ;
assign y__h643332 = ~x__h643302 ;
assign y__h648263 =
{ 4'd15,
~csrf_mideleg_11_reg,
1'd1,
~csrf_mideleg_9_7_reg,
1'd1,
~csrf_mideleg_5_3_reg,
1'd1,
~csrf_mideleg_1_0_reg } ;
assign y__h681714 = 12'd1 << specTagManager$nextSpecTag ;
assign y__h712723 =
rob$deqPort_0_canDeq ?
y_avValue_snd_snd_snd_snd_snd__h712738 :
64'd0 ;
assign y__h714114 =
NOT_rob_deqPort_0_canDeq__4888_4889_OR_rob_deq_ETC___d15172 ?
y_avValue_snd_snd_snd_snd_snd__h714163 :
y__h712723 ;
assign y_avValue__h180137 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1594 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1648 ;
assign y_avValue__h180743 =
NOT_coreFix_memExe_bypassWire_0_whas__567_573__ETC___d1621 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_memExe_bypassWire_0_whas__567_5_ETC___d1659 ;
assign y_avValue__h476650 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8230 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8334 ;
assign y_avValue__h477258 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8257 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8345 ;
assign y_avValue__h477860 =
NOT_coreFix_fpuMulDivExe_0_bypassWire_0_whas___ETC___d8281 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_fpuMulDivExe_0_bypassWire_0_wha_ETC___d8356 ;
assign y_avValue__h606651 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11358 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11751 ;
assign y_avValue__h612381 =
NOT_coreFix_aluExe_1_bypassWire_0_whas__1331_1_ETC___d11386 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_1_bypassWire_0_whas__133_ETC___d11763 ;
assign y_avValue__h630793 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12189 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12397 ;
assign y_avValue__h634252 =
NOT_coreFix_aluExe_0_bypassWire_0_whas__2162_2_ETC___d12217 ?
coreFix_aluExe_0_bypassWire_3$wget[63:0] :
IF_NOT_coreFix_aluExe_0_bypassWire_0_whas__216_ETC___d12409 ;
assign y_avValue__h698948 =
(csrf_stvec_mode_low_reg && commitStage_commitTrap[4]) ?
base__h700680 + { 58'd0, x__h700695 } :
base__h700680 ;
assign y_avValue__h700717 =
(csrf_mtvec_mode_low_reg && commitStage_commitTrap[4]) ?
base__h700883 + { 58'd0, x__h700695 } :
base__h700883 ;
assign y_avValue_fst__h674974 =
(fetchStage$pipelines_0_first[194:192] == 3'd1) ?
spec_bits__h681701 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h675003 =
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 ?
y_avValue_fst__h674974 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h675037 =
((fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim) &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355) ?
y_avValue_fst__h675003 :
specTagManager$currentSpecBits ;
assign y_avValue_fst__h712284 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ?
5'd0 :
rob$deqPort_0_deq_data[31:27] ;
assign y_avValue_fst__h714006 =
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 |
rob$deqPort_1_deq_data[31:27] ;
assign y_avValue_fst__h714034 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15179 :
y_avValue_fst__h714006 ;
assign y_avValue_snd_snd_snd_fst__h712732 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ?
2'd0 :
2'd1 ;
assign y_avValue_snd_snd_snd_fst__h714157 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 :
y_avValue_snd_snd_snd_fst__h714186 ;
assign y_avValue_snd_snd_snd_fst__h714186 =
IF_rob_deqPort_0_canDeq__4888_THEN_IF_NOT_rob__ETC___d15201 +
2'd1 ;
assign y_avValue_snd_snd_snd_snd_snd__h712738 =
(!rob$deqPort_0_deq_data[25] || rob$deqPort_0_deq_data[18] ||
rob$deqPort_0_deq_data[167] ||
rob$deqPort_0_deq_data[186:182] == 5'd0 ||
rob$deqPort_0_deq_data[186:182] == 5'd21 ||
rob$deqPort_0_deq_data[186:182] == 5'd17 ||
rob$deqPort_0_deq_data[186:182] == 5'd18 ||
rob$deqPort_0_deq_data[186:182] == 5'd13 ||
rob$deqPort_0_deq_data[186:182] == 5'd16 ||
rob$deqPort_0_deq_data[186:182] == 5'd15 ||
rob$deqPort_0_deq_data[186:182] == 5'd19 ||
rob$deqPort_0_deq_data[186:182] == 5'd20) ?
64'd0 :
64'd1 ;
assign y_avValue_snd_snd_snd_snd_snd__h714163 =
(!rob$deqPort_1_deq_data[25] || rob$deqPort_1_deq_data[18] ||
rob$deqPort_1_deq_data[167] ||
rob$deqPort_1_deq_data[186:182] == 5'd0 ||
rob$deqPort_1_deq_data[186:182] == 5'd21 ||
rob$deqPort_1_deq_data[186:182] == 5'd17 ||
rob$deqPort_1_deq_data[186:182] == 5'd18 ||
rob$deqPort_1_deq_data[186:182] == 5'd13 ||
rob$deqPort_1_deq_data[186:182] == 5'd16 ||
rob$deqPort_1_deq_data[186:182] == 5'd15 ||
rob$deqPort_1_deq_data[186:182] == 5'd19 ||
rob$deqPort_1_deq_data[186:182] == 5'd20) ?
y__h712723 :
y_avValue_snd_snd_snd_snd_snd__h714192 ;
assign y_avValue_snd_snd_snd_snd_snd__h714192 = y__h712723 + 64'd1 ;
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[153:142])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1 =
v_f_to_TV_1$D_OUT[153:142];
default: CASE_v_f_to_TV_1D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q1 =
12'd2303;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[139:136])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2 =
v_f_to_TV_1$D_OUT[139:136];
default: CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q2 = 4'd15;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[139:136])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3 =
v_f_to_TV_1$D_OUT[139:136];
default: CASE_v_f_to_TV_1D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q3 = 4'd15;
endcase
end
always@(v_f_to_TV_1$D_OUT)
begin
case (v_f_to_TV_1$D_OUT[71:70])
2'd0, 2'd1:
CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4 =
v_f_to_TV_1$D_OUT[71:70];
default: CASE_v_f_to_TV_1D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q4 = 2'd2;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[153:142])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5 =
v_f_to_TV_0$D_OUT[153:142];
default: CASE_v_f_to_TV_0D_OUT_BITS_153_TO_142_1_v_f_t_ETC__q5 =
12'd2303;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[139:136])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6 =
v_f_to_TV_0$D_OUT[139:136];
default: CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q6 = 4'd15;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[139:136])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7 =
v_f_to_TV_0$D_OUT[139:136];
default: CASE_v_f_to_TV_0D_OUT_BITS_139_TO_136_0_v_f_t_ETC__q7 = 4'd15;
endcase
end
always@(v_f_to_TV_0$D_OUT)
begin
case (v_f_to_TV_0$D_OUT[71:70])
2'd0, 2'd1:
CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8 =
v_f_to_TV_0$D_OUT[71:70];
default: CASE_v_f_to_TV_0D_OUT_BITS_71_TO_70_0_v_f_to__ETC__q8 = 2'd2;
endcase
end
always@(mmio_cRqQ_data_0)
begin
case (mmio_cRqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
mmio_cRqQ_data_0[77:72];
2'd3:
CASE_mmio_cRqQ_data_0_BITS_77_TO_76_0_mmio_cRq_ETC__q9 =
{ 2'd3, mmio_cRqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[89:87])
3'd0:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
x__h194973 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 or
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP)
3'd0:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0;
3'd1:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1;
3'd2:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2;
3'd3:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3;
3'd4:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4;
3'd5:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5;
3'd6:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6;
3'd7:
x__h283692 =
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
addr__h287914 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[581:518];
1'd1:
addr__h287914 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[581:518];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_processAmo or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_processAmo[93:91])
3'd0:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:0];
3'd1:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:64];
3'd2:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:128];
3'd3:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:192];
3'd4:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:256];
3'd5:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:320];
3'd6:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:384];
3'd7:
curData__h190763 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:448];
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0, 4'd3: trap_val__h699101 = commitStage_commitTrap[132:69];
default: trap_val__h699101 =
(commitStage_commitTrap[3:0] != 4'd2 &&
commitStage_commitTrap[3:0] != 4'd8 &&
commitStage_commitTrap[3:0] != 4'd9 &&
commitStage_commitTrap[3:0] != 4'd11) ?
commitStage_commitTrap[68:5] :
64'd0;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
x__h289463 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[2:0];
1'd1:
x__h289463 = coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[2:0];
endcase
end
always@(f_csr_reqs$D_OUT or
fflags_csr__read__h607138 or
frm_csr__read__h607149 or
fcsr_csr__read__h607163 or
sstatus_csr__read__h607359 or
sie_csr__read__h607428 or
stvec_csr__read__h607471 or
scounteren_csr__read__h607524 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h607662 or
csrf_stval_csr or
sip_csr__read__h607801 or
satp_csr__read__h607864 or
mstatus_csr__read__h608007 or
medeleg_csr__read__h608155 or
mideleg_csr__read__h608250 or
mie_csr__read__h608374 or
mtvec_csr__read__h608456 or
mcounteren_csr__read__h608548 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h608803 or
csrf_mtval_csr or
mip_csr__read__h609036 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h607268 or
n__read__h609140 or n__read__h609331 or csrf_time_reg)
begin
case (f_csr_reqs$D_OUT[75:64])
12'd1: data_out__h718171 = fflags_csr__read__h607138;
12'd2: data_out__h718171 = frm_csr__read__h607149;
12'd3: data_out__h718171 = fcsr_csr__read__h607163;
12'd256: data_out__h718171 = sstatus_csr__read__h607359;
12'd260: data_out__h718171 = sie_csr__read__h607428;
12'd261: data_out__h718171 = stvec_csr__read__h607471;
12'd262: data_out__h718171 = scounteren_csr__read__h607524;
12'd320: data_out__h718171 = csrf_sscratch_csr;
12'd321: data_out__h718171 = csrf_sepc_csr;
12'd322: data_out__h718171 = scause_csr__read__h607662;
12'd323: data_out__h718171 = csrf_stval_csr;
12'd324: data_out__h718171 = sip_csr__read__h607801;
12'd384: data_out__h718171 = satp_csr__read__h607864;
12'd768: data_out__h718171 = mstatus_csr__read__h608007;
12'd769: data_out__h718171 = 64'h800000000014112D;
12'd770: data_out__h718171 = medeleg_csr__read__h608155;
12'd771: data_out__h718171 = mideleg_csr__read__h608250;
12'd772: data_out__h718171 = mie_csr__read__h608374;
12'd773: data_out__h718171 = mtvec_csr__read__h608456;
12'd774: data_out__h718171 = mcounteren_csr__read__h608548;
12'd832: data_out__h718171 = csrf_mscratch_csr;
12'd833: data_out__h718171 = csrf_mepc_csr;
12'd834: data_out__h718171 = mcause_csr__read__h608803;
12'd835: data_out__h718171 = csrf_mtval_csr;
12'd836: data_out__h718171 = mip_csr__read__h609036;
12'd1968: data_out__h718171 = csrf_rg_dcsr;
12'd1969: data_out__h718171 = csrf_rg_dpc;
12'd1970: data_out__h718171 = csrf_rg_dscratch0;
12'd1971: data_out__h718171 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
data_out__h718171 = 64'd0;
12'd2049: data_out__h718171 = x_reg_ifc__read__h607268;
12'd2816, 12'd3072: data_out__h718171 = n__read__h609140;
12'd2818, 12'd3074: data_out__h718171 = n__read__h609331;
12'd3073: data_out__h718171 = csrf_time_reg;
default: data_out__h718171 = 64'b0;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
fflags_csr__read__h607138 or
frm_csr__read__h607149 or
fcsr_csr__read__h607163 or
sstatus_csr__read__h607359 or
sie_csr__read__h607428 or
stvec_csr__read__h607471 or
scounteren_csr__read__h607524 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h607662 or
csrf_stval_csr or
sip_csr__read__h607801 or
satp_csr__read__h607864 or
mstatus_csr__read__h608007 or
medeleg_csr__read__h608155 or
mideleg_csr__read__h608250 or
mie_csr__read__h608374 or
mtvec_csr__read__h608456 or
mcounteren_csr__read__h608548 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h608803 or
csrf_mtval_csr or
mip_csr__read__h609036 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h607268 or
n__read__h609140 or n__read__h609331 or csrf_time_reg)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1: rVal1__h606861 = fflags_csr__read__h607138;
12'd2: rVal1__h606861 = frm_csr__read__h607149;
12'd3: rVal1__h606861 = fcsr_csr__read__h607163;
12'd256: rVal1__h606861 = sstatus_csr__read__h607359;
12'd260: rVal1__h606861 = sie_csr__read__h607428;
12'd261: rVal1__h606861 = stvec_csr__read__h607471;
12'd262: rVal1__h606861 = scounteren_csr__read__h607524;
12'd320: rVal1__h606861 = csrf_sscratch_csr;
12'd321: rVal1__h606861 = csrf_sepc_csr;
12'd322: rVal1__h606861 = scause_csr__read__h607662;
12'd323: rVal1__h606861 = csrf_stval_csr;
12'd324: rVal1__h606861 = sip_csr__read__h607801;
12'd384: rVal1__h606861 = satp_csr__read__h607864;
12'd768: rVal1__h606861 = mstatus_csr__read__h608007;
12'd769: rVal1__h606861 = 64'h800000000014112D;
12'd770: rVal1__h606861 = medeleg_csr__read__h608155;
12'd771: rVal1__h606861 = mideleg_csr__read__h608250;
12'd772: rVal1__h606861 = mie_csr__read__h608374;
12'd773: rVal1__h606861 = mtvec_csr__read__h608456;
12'd774: rVal1__h606861 = mcounteren_csr__read__h608548;
12'd832: rVal1__h606861 = csrf_mscratch_csr;
12'd833: rVal1__h606861 = csrf_mepc_csr;
12'd834: rVal1__h606861 = mcause_csr__read__h608803;
12'd835: rVal1__h606861 = csrf_mtval_csr;
12'd836: rVal1__h606861 = mip_csr__read__h609036;
12'd1968: rVal1__h606861 = csrf_rg_dcsr;
12'd1969: rVal1__h606861 = csrf_rg_dpc;
12'd1970: rVal1__h606861 = csrf_rg_dscratch0;
12'd1971: rVal1__h606861 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
rVal1__h606861 = 64'd0;
12'd2049: rVal1__h606861 = x_reg_ifc__read__h607268;
12'd2816, 12'd3072: rVal1__h606861 = n__read__h609140;
12'd2818, 12'd3074: rVal1__h606861 = n__read__h609331;
12'd3073: rVal1__h606861 = csrf_time_reg;
default: rVal1__h606861 = 64'b0;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
fflags_csr__read__h607138 or
frm_csr__read__h607149 or
fcsr_csr__read__h607163 or
sstatus_csr__read__h607359 or
sie_csr__read__h607428 or
stvec_csr__read__h607471 or
scounteren_csr__read__h607524 or
csrf_sscratch_csr or
csrf_sepc_csr or
scause_csr__read__h607662 or
csrf_stval_csr or
sip_csr__read__h607801 or
satp_csr__read__h607864 or
mstatus_csr__read__h608007 or
medeleg_csr__read__h608155 or
mideleg_csr__read__h608250 or
mie_csr__read__h608374 or
mtvec_csr__read__h608456 or
mcounteren_csr__read__h608548 or
csrf_mscratch_csr or
csrf_mepc_csr or
mcause_csr__read__h608803 or
csrf_mtval_csr or
mip_csr__read__h609036 or
csrf_rg_dcsr or
csrf_rg_dpc or
csrf_rg_dscratch0 or
csrf_rg_dscratch1 or
x_reg_ifc__read__h607268 or
n__read__h609140 or n__read__h609331 or csrf_time_reg)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1: rVal1__h631001 = fflags_csr__read__h607138;
12'd2: rVal1__h631001 = frm_csr__read__h607149;
12'd3: rVal1__h631001 = fcsr_csr__read__h607163;
12'd256: rVal1__h631001 = sstatus_csr__read__h607359;
12'd260: rVal1__h631001 = sie_csr__read__h607428;
12'd261: rVal1__h631001 = stvec_csr__read__h607471;
12'd262: rVal1__h631001 = scounteren_csr__read__h607524;
12'd320: rVal1__h631001 = csrf_sscratch_csr;
12'd321: rVal1__h631001 = csrf_sepc_csr;
12'd322: rVal1__h631001 = scause_csr__read__h607662;
12'd323: rVal1__h631001 = csrf_stval_csr;
12'd324: rVal1__h631001 = sip_csr__read__h607801;
12'd384: rVal1__h631001 = satp_csr__read__h607864;
12'd768: rVal1__h631001 = mstatus_csr__read__h608007;
12'd769: rVal1__h631001 = 64'h800000000014112D;
12'd770: rVal1__h631001 = medeleg_csr__read__h608155;
12'd771: rVal1__h631001 = mideleg_csr__read__h608250;
12'd772: rVal1__h631001 = mie_csr__read__h608374;
12'd773: rVal1__h631001 = mtvec_csr__read__h608456;
12'd774: rVal1__h631001 = mcounteren_csr__read__h608548;
12'd832: rVal1__h631001 = csrf_mscratch_csr;
12'd833: rVal1__h631001 = csrf_mepc_csr;
12'd834: rVal1__h631001 = mcause_csr__read__h608803;
12'd835: rVal1__h631001 = csrf_mtval_csr;
12'd836: rVal1__h631001 = mip_csr__read__h609036;
12'd1968: rVal1__h631001 = csrf_rg_dcsr;
12'd1969: rVal1__h631001 = csrf_rg_dpc;
12'd1970: rVal1__h631001 = csrf_rg_dscratch0;
12'd1971: rVal1__h631001 = csrf_rg_dscratch1;
12'd2048, 12'd3857, 12'd3858, 12'd3859, 12'd3860:
rVal1__h631001 = 64'd0;
12'd2049: rVal1__h631001 = x_reg_ifc__read__h607268;
12'd2816, 12'd3072: rVal1__h631001 = n__read__h609140;
12'd2818, 12'd3074: rVal1__h631001 = n__read__h609331;
12'd3073: rVal1__h631001 = csrf_time_reg;
default: rVal1__h631001 = 64'b0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h343911 = 8'd255;
3'd2:
_theResult___fst_exp__h343911 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h343911 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h343911 = 8'd254;
default: _theResult___fst_exp__h343911 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h343912 = 23'd0;
3'd2:
_theResult___fst_sfd__h343912 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h343912 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h343912 = 23'd8388607;
default: _theResult___fst_sfd__h343912 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h389611 = 23'd0;
3'd2:
_theResult___fst_sfd__h389611 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h389611 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h389611 = 23'd8388607;
default: _theResult___fst_sfd__h389611 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h389610 = 8'd255;
3'd2:
_theResult___fst_exp__h389610 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h389610 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h389610 = 8'd254;
default: _theResult___fst_exp__h389610 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_exp__h435305 = 8'd255;
3'd2:
_theResult___fst_exp__h435305 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd254 :
8'd255;
3'd3:
_theResult___fst_exp__h435305 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
8'd255 :
8'd254;
3'd4: _theResult___fst_exp__h435305 = 8'd254;
default: _theResult___fst_exp__h435305 = 8'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1: _theResult___fst_sfd__h435306 = 23'd0;
3'd2:
_theResult___fst_sfd__h435306 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd8388607 :
23'd0;
3'd3:
_theResult___fst_sfd__h435306 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] ?
23'd0 :
23'd8388607;
3'd4: _theResult___fst_sfd__h435306 = 23'd8388607;
default: _theResult___fst_sfd__h435306 = 23'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q14 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q15 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q16 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q17 = 52'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd2046;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
11'd2047 :
11'd2046;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
11'd2046 :
11'd2047;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q18 = 11'd0;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
52'hFFFFFFFFFFFFF;
3'd2:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 =
(coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q19 = 52'd0;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
i__h698077 = commitStage_commitTrap[3:0];
default: i__h698077 = 4'd15;
endcase
end
always@(commitStage_commitTrap)
begin
case (commitStage_commitTrap[3:0])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
i__h698237 = commitStage_commitTrap[3:0];
default: i__h698237 = 4'd15;
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
coreFix_memExe_respLrScAmoQ_data_0[31:0];
1'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1348 =
coreFix_memExe_respLrScAmoQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[15:0];
2'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[31:16];
2'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[47:32];
2'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1359 =
coreFix_memExe_respLrScAmoQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or coreFix_memExe_respLrScAmoQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[7:0];
3'd1:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[15:8];
3'd2:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[23:16];
3'd3:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[31:24];
3'd4:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[39:32];
3'd5:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[47:40];
3'd6:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[55:48];
3'd7:
SEL_ARR_coreFix_memExe_respLrScAmoQ_data_0_071_ETC___d1373 =
coreFix_memExe_respLrScAmoQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19])
1'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
mmio_dataRespQ_data_0[31:0];
1'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_31_TO_0_ETC___d1398 =
mmio_dataRespQ_data_0[63:32];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:18])
2'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[15:0];
2'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[31:16];
2'd2:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[47:32];
2'd3:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_15_TO_0_ETC___d1407 =
mmio_dataRespQ_data_0[63:48];
endcase
end
always@(coreFix_memExe_lsq$firstLd or mmio_dataRespQ_data_0)
begin
case (coreFix_memExe_lsq$firstLd[19:17])
3'd0:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[7:0];
3'd1:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[15:8];
3'd2:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[23:16];
3'd3:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[31:24];
3'd4:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[39:32];
3'd5:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[47:40];
3'd6:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[55:48];
3'd7:
SEL_ARR_mmio_dataRespQ_data_0_101_BITS_7_TO_0__ETC___d1420 =
mmio_dataRespQ_data_0[63:56];
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[105:103])
3'd0, 3'd2:
CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20 = 4'd4;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_105_TO__ETC__q20 = 4'd6;
endcase
end
always@(coreFix_memExe_dTlb$procResp)
begin
case (coreFix_memExe_dTlb$procResp[109:106])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 =
coreFix_memExe_dTlb$procResp[109:106];
4'd11: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 = 4'd10;
4'd12: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 = 4'd11;
4'd13: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 = 4'd12;
default: CASE_coreFix_memExe_dTlbprocResp_BITS_109_TO__ETC__q21 = 4'd13;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[65:2];
1'd1:
SEL_ARR_coreFix_memExe_dMem_cache_m_banks_0_fr_ETC___d2871 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[65:2];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[514:451];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q22 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[514:451];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[450:387];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q23 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[450:387];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[386:323];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q24 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[386:323];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[322:259];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q25 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[322:259];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[258:195];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q26 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[258:195];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[194:131];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q27 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[194:131];
endcase
end
always@(guard__h352648 or
_theResult___fst_exp__h360696 or
out_exp__h361141 or _theResult___exp__h361138)
begin
case (guard__h352648)
2'b0, 2'b01:
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 =
_theResult___fst_exp__h360696;
2'b10:
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 =
out_exp__h361141;
2'b11:
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 =
_theResult___exp__h361138;
endcase
end
always@(guard__h352648 or
_theResult___fst_exp__h360696 or _theResult___exp__h361138)
begin
case (guard__h352648)
2'b0:
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 =
_theResult___fst_exp__h360696;
2'b01, 2'b10, 2'b11:
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 =
_theResult___exp__h361138;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32 or
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530 or
_theResult___fst_exp__h360696)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h361216 =
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q32;
3'd1:
_theResult___fst_exp__h361216 =
CASE_guard52648_0b0_theResult___fst_exp60696_0_ETC__q33;
3'd2:
_theResult___fst_exp__h361216 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4528;
3'd3:
_theResult___fst_exp__h361216 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4530;
3'd4: _theResult___fst_exp__h361216 = _theResult___fst_exp__h360696;
default: _theResult___fst_exp__h361216 = 8'd0;
endcase
end
always@(guard__h343939 or
_theResult___fst_exp__h352040 or
out_exp__h352559 or _theResult___exp__h352556)
begin
case (guard__h343939)
2'b0, 2'b01:
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 =
_theResult___fst_exp__h352040;
2'b10:
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 =
out_exp__h352559;
2'b11:
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 =
_theResult___exp__h352556;
endcase
end
always@(guard__h343939 or
_theResult___fst_exp__h352040 or _theResult___exp__h352556)
begin
case (guard__h343939)
2'b0:
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 =
_theResult___fst_exp__h352040;
2'b01, 2'b10, 2'b11:
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 =
_theResult___exp__h352556;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34 or
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309 or
_theResult___fst_exp__h352040)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h352634 =
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q34;
3'd1:
_theResult___fst_exp__h352634 =
CASE_guard43939_0b0_theResult___fst_exp52040_0_ETC__q35;
3'd2:
_theResult___fst_exp__h352634 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4306;
3'd3:
_theResult___fst_exp__h352634 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4309;
3'd4: _theResult___fst_exp__h352634 = _theResult___fst_exp__h352040;
default: _theResult___fst_exp__h352634 = 8'd0;
endcase
end
always@(guard__h361578 or
_theResult___fst_exp__h369806 or
out_exp__h370325 or _theResult___exp__h370322)
begin
case (guard__h361578)
2'b0, 2'b01:
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 =
_theResult___fst_exp__h369806;
2'b10:
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 =
out_exp__h370325;
2'b11:
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 =
_theResult___exp__h370322;
endcase
end
always@(guard__h361578 or
_theResult___fst_exp__h369806 or _theResult___exp__h370322)
begin
case (guard__h361578)
2'b0:
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 =
_theResult___fst_exp__h369806;
2'b01, 2'b10, 2'b11:
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 =
_theResult___exp__h370322;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40 or
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855 or
_theResult___fst_exp__h369806)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h370400 =
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q40;
3'd1:
_theResult___fst_exp__h370400 =
CASE_guard61578_0b0_theResult___fst_exp69806_0_ETC__q41;
3'd2:
_theResult___fst_exp__h370400 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4853;
3'd3:
_theResult___fst_exp__h370400 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4855;
3'd4: _theResult___fst_exp__h370400 = _theResult___fst_exp__h369806;
default: _theResult___fst_exp__h370400 = 8'd0;
endcase
end
always@(guard__h370414 or
_theResult___fst_exp__h378491 or
out_exp__h378961 or _theResult___exp__h378958)
begin
case (guard__h370414)
2'b0, 2'b01:
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 =
_theResult___fst_exp__h378491;
2'b10:
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 =
out_exp__h378961;
2'b11:
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 =
_theResult___exp__h378958;
endcase
end
always@(guard__h370414 or
_theResult___fst_exp__h378491 or _theResult___exp__h378958)
begin
case (guard__h370414)
2'b0:
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 =
_theResult___fst_exp__h378491;
2'b01, 2'b10, 2'b11:
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 =
_theResult___exp__h378958;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45 or
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924 or
_theResult___fst_exp__h378491)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h379036 =
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q45;
3'd1:
_theResult___fst_exp__h379036 =
CASE_guard70414_0b0_theResult___fst_exp78491_0_ETC__q46;
3'd2:
_theResult___fst_exp__h379036 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4922;
3'd3:
_theResult___fst_exp__h379036 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4924;
3'd4: _theResult___fst_exp__h379036 = _theResult___fst_exp__h378491;
default: _theResult___fst_exp__h379036 = 8'd0;
endcase
end
always@(guard__h352648 or
_theResult___snd__h360647 or
out_sfd__h361142 or _theResult___sfd__h361139)
begin
case (guard__h352648)
2'b0, 2'b01:
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 =
_theResult___snd__h360647[56:34];
2'b10:
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 =
out_sfd__h361142;
2'b11:
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 =
_theResult___sfd__h361139;
endcase
end
always@(guard__h352648 or
_theResult___snd__h360647 or _theResult___sfd__h361139)
begin
case (guard__h352648)
2'b0:
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 =
_theResult___snd__h360647[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 =
_theResult___sfd__h361139;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47 or
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974 or
_theResult___snd__h360647)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h361217 =
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q47;
3'd1:
_theResult___fst_sfd__h361217 =
CASE_guard52648_0b0_theResult___snd60647_BITS__ETC__q48;
3'd2:
_theResult___fst_sfd__h361217 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4972;
3'd3:
_theResult___fst_sfd__h361217 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d4974;
3'd4: _theResult___fst_sfd__h361217 = _theResult___snd__h360647[56:34];
default: _theResult___fst_sfd__h361217 = 23'd0;
endcase
end
always@(guard__h343939 or
sfdin__h352034 or out_sfd__h352560 or _theResult___sfd__h352557)
begin
case (guard__h343939)
2'b0, 2'b01:
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 =
sfdin__h352034[56:34];
2'b10:
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 =
out_sfd__h352560;
2'b11:
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 =
_theResult___sfd__h352557;
endcase
end
always@(guard__h343939 or sfdin__h352034 or _theResult___sfd__h352557)
begin
case (guard__h343939)
2'b0:
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 =
sfdin__h352034[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 =
_theResult___sfd__h352557;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49 or
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955 or
sfdin__h352034)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h352635 =
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q49;
3'd1:
_theResult___fst_sfd__h352635 =
CASE_guard43939_0b0_sfdin52034_BITS_56_TO_34_0_ETC__q50;
3'd2:
_theResult___fst_sfd__h352635 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4953;
3'd3:
_theResult___fst_sfd__h352635 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d4955;
3'd4: _theResult___fst_sfd__h352635 = sfdin__h352034[56:34];
default: _theResult___fst_sfd__h352635 = 23'd0;
endcase
end
always@(guard__h361578 or
sfdin__h369800 or out_sfd__h370326 or _theResult___sfd__h370323)
begin
case (guard__h361578)
2'b0, 2'b01:
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 =
sfdin__h369800[56:34];
2'b10:
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 =
out_sfd__h370326;
2'b11:
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 =
_theResult___sfd__h370323;
endcase
end
always@(guard__h361578 or sfdin__h369800 or _theResult___sfd__h370323)
begin
case (guard__h361578)
2'b0:
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 =
sfdin__h369800[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 =
_theResult___sfd__h370323;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51 or
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001 or
sfdin__h369800)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h370401 =
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q51;
3'd1:
_theResult___fst_sfd__h370401 =
CASE_guard61578_0b0_sfdin69800_BITS_56_TO_34_0_ETC__q52;
3'd2:
_theResult___fst_sfd__h370401 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d4999;
3'd3:
_theResult___fst_sfd__h370401 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d5001;
3'd4: _theResult___fst_sfd__h370401 = sfdin__h369800[56:34];
default: _theResult___fst_sfd__h370401 = 23'd0;
endcase
end
always@(guard__h343939 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h343939)
2'b0, 2'b01, 2'b10:
CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 =
guard__h343939 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53 or
guard__h343939)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
CASE_guard43939_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q53;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
(guard__h343939 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h343939 == 2'b01 || guard__h343939 == 2'b10 ||
guard__h343939 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5106 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h370414 or
_theResult___snd__h378437 or
out_sfd__h378962 or _theResult___sfd__h378959)
begin
case (guard__h370414)
2'b0, 2'b01:
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 =
_theResult___snd__h378437[56:34];
2'b10:
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 =
out_sfd__h378962;
2'b11:
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 =
_theResult___sfd__h378959;
endcase
end
always@(guard__h370414 or
_theResult___snd__h378437 or _theResult___sfd__h378959)
begin
case (guard__h370414)
2'b0:
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 =
_theResult___snd__h378437[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 =
_theResult___sfd__h378959;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54 or
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020 or
_theResult___snd__h378437)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h379037 =
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q54;
3'd1:
_theResult___fst_sfd__h379037 =
CASE_guard70414_0b0_theResult___snd78437_BITS__ETC__q55;
3'd2:
_theResult___fst_sfd__h379037 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5018;
3'd3:
_theResult___fst_sfd__h379037 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5020;
3'd4: _theResult___fst_sfd__h379037 = _theResult___snd__h378437[56:34];
default: _theResult___fst_sfd__h379037 = 23'd0;
endcase
end
always@(guard__h343939 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h343939)
2'b0, 2'b01, 2'b10:
CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 =
guard__h343939 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56 or
guard__h343939)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
CASE_guard43939_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q56;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
(guard__h343939 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h343939 != 2'b01 && guard__h343939 != 2'b10 &&
guard__h343939 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5050 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h352648 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h352648)
2'b0, 2'b01, 2'b10:
CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 =
guard__h352648 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57 or
guard__h352648)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
CASE_guard52648_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q57;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
(guard__h352648 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h352648 == 2'b01 || guard__h352648 == 2'b10 ||
guard__h352648 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5113 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h352648 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h352648)
2'b0, 2'b01, 2'b10:
CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 =
guard__h352648 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58 or
guard__h352648)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
CASE_guard52648_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q58;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
(guard__h352648 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h352648 != 2'b01 && guard__h352648 != 2'b10 &&
guard__h352648 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5063 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h361578 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h361578)
2'b0, 2'b01, 2'b10:
CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 =
guard__h361578 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59 or
guard__h361578)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
CASE_guard61578_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q59;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
(guard__h361578 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h361578 == 2'b01 || guard__h361578 == 2'b10 ||
guard__h361578 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5123 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h361578 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h361578)
2'b0, 2'b01, 2'b10:
CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 =
guard__h361578 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60 or
guard__h361578)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
CASE_guard61578_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q60;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
(guard__h361578 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h361578 != 2'b01 && guard__h361578 != 2'b10 &&
guard__h361578 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5080 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h370414 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h370414)
2'b0, 2'b01, 2'b10:
CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 =
guard__h370414 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61 or
guard__h370414)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
CASE_guard70414_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q61;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
(guard__h370414 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
(guard__h370414 == 2'b01 || guard__h370414 == 2'b10 ||
guard__h370414 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5130 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h370414 or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (guard__h370414)
2'b0, 2'b01, 2'b10:
CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
2'd3:
CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 =
guard__h370414 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get or
CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62 or
guard__h370414)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
CASE_guard70414_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q62;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
(guard__h370414 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68] :
guard__h370414 != 2'b01 && guard__h370414 != 2'b10 &&
guard__h370414 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5093 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5116 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_fmaQ_first_d_ETC___d5067 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_fma$response_get[68];
endcase
end
always@(guard__h398345 or
_theResult___fst_exp__h406393 or
out_exp__h406838 or _theResult___exp__h406835)
begin
case (guard__h398345)
2'b0, 2'b01:
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 =
_theResult___fst_exp__h406393;
2'b10:
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 =
out_exp__h406838;
2'b11:
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 =
_theResult___exp__h406835;
endcase
end
always@(guard__h398345 or
_theResult___fst_exp__h406393 or _theResult___exp__h406835)
begin
case (guard__h398345)
2'b0:
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 =
_theResult___fst_exp__h406393;
2'b01, 2'b10, 2'b11:
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 =
_theResult___exp__h406835;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67 or
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922 or
_theResult___fst_exp__h406393)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h406913 =
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q67;
3'd1:
_theResult___fst_exp__h406913 =
CASE_guard98345_0b0_theResult___fst_exp06393_0_ETC__q68;
3'd2:
_theResult___fst_exp__h406913 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5920;
3'd3:
_theResult___fst_exp__h406913 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d5922;
3'd4: _theResult___fst_exp__h406913 = _theResult___fst_exp__h406393;
default: _theResult___fst_exp__h406913 = 8'd0;
endcase
end
always@(guard__h389638 or
_theResult___fst_exp__h397737 or
out_exp__h398256 or _theResult___exp__h398253)
begin
case (guard__h389638)
2'b0, 2'b01:
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 =
_theResult___fst_exp__h397737;
2'b10:
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 =
out_exp__h398256;
2'b11:
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 =
_theResult___exp__h398253;
endcase
end
always@(guard__h389638 or
_theResult___fst_exp__h397737 or _theResult___exp__h398253)
begin
case (guard__h389638)
2'b0:
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 =
_theResult___fst_exp__h397737;
2'b01, 2'b10, 2'b11:
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 =
_theResult___exp__h398253;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69 or
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701 or
_theResult___fst_exp__h397737)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h398331 =
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q69;
3'd1:
_theResult___fst_exp__h398331 =
CASE_guard89638_0b0_theResult___fst_exp97737_0_ETC__q70;
3'd2:
_theResult___fst_exp__h398331 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5698;
3'd3:
_theResult___fst_exp__h398331 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d5701;
3'd4: _theResult___fst_exp__h398331 = _theResult___fst_exp__h397737;
default: _theResult___fst_exp__h398331 = 8'd0;
endcase
end
always@(guard__h407275 or
_theResult___fst_exp__h415503 or
out_exp__h416022 or _theResult___exp__h416019)
begin
case (guard__h407275)
2'b0, 2'b01:
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 =
_theResult___fst_exp__h415503;
2'b10:
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 =
out_exp__h416022;
2'b11:
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 =
_theResult___exp__h416019;
endcase
end
always@(guard__h407275 or
_theResult___fst_exp__h415503 or _theResult___exp__h416019)
begin
case (guard__h407275)
2'b0:
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 =
_theResult___fst_exp__h415503;
2'b01, 2'b10, 2'b11:
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 =
_theResult___exp__h416019;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75 or
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247 or
_theResult___fst_exp__h415503)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h416097 =
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q75;
3'd1:
_theResult___fst_exp__h416097 =
CASE_guard07275_0b0_theResult___fst_exp15503_0_ETC__q76;
3'd2:
_theResult___fst_exp__h416097 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6245;
3'd3:
_theResult___fst_exp__h416097 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6247;
3'd4: _theResult___fst_exp__h416097 = _theResult___fst_exp__h415503;
default: _theResult___fst_exp__h416097 = 8'd0;
endcase
end
always@(guard__h416111 or
_theResult___fst_exp__h424188 or
out_exp__h424658 or _theResult___exp__h424655)
begin
case (guard__h416111)
2'b0, 2'b01:
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 =
_theResult___fst_exp__h424188;
2'b10:
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 =
out_exp__h424658;
2'b11:
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 =
_theResult___exp__h424655;
endcase
end
always@(guard__h416111 or
_theResult___fst_exp__h424188 or _theResult___exp__h424655)
begin
case (guard__h416111)
2'b0:
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 =
_theResult___fst_exp__h424188;
2'b01, 2'b10, 2'b11:
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 =
_theResult___exp__h424655;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80 or
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316 or
_theResult___fst_exp__h424188)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h424733 =
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q80;
3'd1:
_theResult___fst_exp__h424733 =
CASE_guard16111_0b0_theResult___fst_exp24188_0_ETC__q81;
3'd2:
_theResult___fst_exp__h424733 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6314;
3'd3:
_theResult___fst_exp__h424733 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6316;
3'd4: _theResult___fst_exp__h424733 = _theResult___fst_exp__h424188;
default: _theResult___fst_exp__h424733 = 8'd0;
endcase
end
always@(guard__h398345 or
_theResult___snd__h406344 or
out_sfd__h406839 or _theResult___sfd__h406836)
begin
case (guard__h398345)
2'b0, 2'b01:
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 =
_theResult___snd__h406344[56:34];
2'b10:
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 =
out_sfd__h406839;
2'b11:
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 =
_theResult___sfd__h406836;
endcase
end
always@(guard__h398345 or
_theResult___snd__h406344 or _theResult___sfd__h406836)
begin
case (guard__h398345)
2'b0:
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 =
_theResult___snd__h406344[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 =
_theResult___sfd__h406836;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82 or
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366 or
_theResult___snd__h406344)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h406914 =
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q82;
3'd1:
_theResult___fst_sfd__h406914 =
CASE_guard98345_0b0_theResult___snd06344_BITS__ETC__q83;
3'd2:
_theResult___fst_sfd__h406914 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6364;
3'd3:
_theResult___fst_sfd__h406914 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6366;
3'd4: _theResult___fst_sfd__h406914 = _theResult___snd__h406344[56:34];
default: _theResult___fst_sfd__h406914 = 23'd0;
endcase
end
always@(guard__h389638 or
sfdin__h397731 or out_sfd__h398257 or _theResult___sfd__h398254)
begin
case (guard__h389638)
2'b0, 2'b01:
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 =
sfdin__h397731[56:34];
2'b10:
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 =
out_sfd__h398257;
2'b11:
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 =
_theResult___sfd__h398254;
endcase
end
always@(guard__h389638 or sfdin__h397731 or _theResult___sfd__h398254)
begin
case (guard__h389638)
2'b0:
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 =
sfdin__h397731[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 =
_theResult___sfd__h398254;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84 or
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347 or
sfdin__h397731)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h398332 =
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q84;
3'd1:
_theResult___fst_sfd__h398332 =
CASE_guard89638_0b0_sfdin97731_BITS_56_TO_34_0_ETC__q85;
3'd2:
_theResult___fst_sfd__h398332 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6345;
3'd3:
_theResult___fst_sfd__h398332 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d6347;
3'd4: _theResult___fst_sfd__h398332 = sfdin__h397731[56:34];
default: _theResult___fst_sfd__h398332 = 23'd0;
endcase
end
always@(guard__h407275 or
sfdin__h415497 or out_sfd__h416023 or _theResult___sfd__h416020)
begin
case (guard__h407275)
2'b0, 2'b01:
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 =
sfdin__h415497[56:34];
2'b10:
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 =
out_sfd__h416023;
2'b11:
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 =
_theResult___sfd__h416020;
endcase
end
always@(guard__h407275 or sfdin__h415497 or _theResult___sfd__h416020)
begin
case (guard__h407275)
2'b0:
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 =
sfdin__h415497[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 =
_theResult___sfd__h416020;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86 or
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393 or
sfdin__h415497)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h416098 =
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q86;
3'd1:
_theResult___fst_sfd__h416098 =
CASE_guard07275_0b0_sfdin15497_BITS_56_TO_34_0_ETC__q87;
3'd2:
_theResult___fst_sfd__h416098 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6391;
3'd3:
_theResult___fst_sfd__h416098 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d6393;
3'd4: _theResult___fst_sfd__h416098 = sfdin__h415497[56:34];
default: _theResult___fst_sfd__h416098 = 23'd0;
endcase
end
always@(guard__h416111 or
_theResult___snd__h424134 or
out_sfd__h424659 or _theResult___sfd__h424656)
begin
case (guard__h416111)
2'b0, 2'b01:
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 =
_theResult___snd__h424134[56:34];
2'b10:
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 =
out_sfd__h424659;
2'b11:
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 =
_theResult___sfd__h424656;
endcase
end
always@(guard__h416111 or
_theResult___snd__h424134 or _theResult___sfd__h424656)
begin
case (guard__h416111)
2'b0:
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 =
_theResult___snd__h424134[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 =
_theResult___sfd__h424656;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88 or
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412 or
_theResult___snd__h424134)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h424734 =
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q88;
3'd1:
_theResult___fst_sfd__h424734 =
CASE_guard16111_0b0_theResult___snd24134_BITS__ETC__q89;
3'd2:
_theResult___fst_sfd__h424734 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6410;
3'd3:
_theResult___fst_sfd__h424734 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d6412;
3'd4: _theResult___fst_sfd__h424734 = _theResult___snd__h424134[56:34];
default: _theResult___fst_sfd__h424734 = 23'd0;
endcase
end
always@(guard__h389638 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h389638)
2'b0, 2'b01, 2'b10:
CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 =
guard__h389638 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90 or
guard__h389638)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
CASE_guard89638_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q90;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
(guard__h389638 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h389638 == 2'b01 || guard__h389638 == 2'b10 ||
guard__h389638 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6498 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h389638 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h389638)
2'b0, 2'b01, 2'b10:
CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 =
guard__h389638 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91 or
guard__h389638)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
CASE_guard89638_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q91;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
(guard__h389638 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h389638 != 2'b01 && guard__h389638 != 2'b10 &&
guard__h389638 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6442 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h398345 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h398345)
2'b0, 2'b01, 2'b10:
CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 =
guard__h398345 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92 or
guard__h398345)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
CASE_guard98345_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q92;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
(guard__h398345 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h398345 == 2'b01 || guard__h398345 == 2'b10 ||
guard__h398345 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6505 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h398345 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h398345)
2'b0, 2'b01, 2'b10:
CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 =
guard__h398345 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93 or
guard__h398345)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
CASE_guard98345_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q93;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
(guard__h398345 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h398345 != 2'b01 && guard__h398345 != 2'b10 &&
guard__h398345 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6455 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h407275 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h407275)
2'b0, 2'b01, 2'b10:
CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 =
guard__h407275 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94 or
guard__h407275)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
CASE_guard07275_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q94;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
(guard__h407275 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h407275 == 2'b01 || guard__h407275 == 2'b10 ||
guard__h407275 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6515 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h407275 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h407275)
2'b0, 2'b01, 2'b10:
CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 =
guard__h407275 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95 or
guard__h407275)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
CASE_guard07275_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q95;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
(guard__h407275 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h407275 != 2'b01 && guard__h407275 != 2'b10 &&
guard__h407275 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6472 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h416111 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h416111)
2'b0, 2'b01, 2'b10:
CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 =
guard__h416111 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96 or
guard__h416111)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
CASE_guard16111_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q96;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
(guard__h416111 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
(guard__h416111 == 2'b01 || guard__h416111 == 2'b10 ||
guard__h416111 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6522 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h416111 or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (guard__h416111)
2'b0, 2'b01, 2'b10:
CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
2'd3:
CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 =
guard__h416111 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get or
CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97 or
guard__h416111)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
CASE_guard16111_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q97;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
(guard__h416111 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68] :
guard__h416111 != 2'b01 && guard__h416111 != 2'b10 &&
guard__h416111 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6485 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6508 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_divQ_first_d_ETC___d6459 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_div$response_get[68];
endcase
end
always@(guard__h444040 or
_theResult___fst_exp__h452088 or
out_exp__h452533 or _theResult___exp__h452530)
begin
case (guard__h444040)
2'b0, 2'b01:
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 =
_theResult___fst_exp__h452088;
2'b10:
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 =
out_exp__h452533;
2'b11:
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 =
_theResult___exp__h452530;
endcase
end
always@(guard__h444040 or
_theResult___fst_exp__h452088 or _theResult___exp__h452530)
begin
case (guard__h444040)
2'b0:
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 =
_theResult___fst_exp__h452088;
2'b01, 2'b10, 2'b11:
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 =
_theResult___exp__h452530;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102 or
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314 or
_theResult___fst_exp__h452088)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h452608 =
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q102;
3'd1:
_theResult___fst_exp__h452608 =
CASE_guard44040_0b0_theResult___fst_exp52088_0_ETC__q103;
3'd2:
_theResult___fst_exp__h452608 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7312;
3'd3:
_theResult___fst_exp__h452608 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7314;
3'd4: _theResult___fst_exp__h452608 = _theResult___fst_exp__h452088;
default: _theResult___fst_exp__h452608 = 8'd0;
endcase
end
always@(guard__h435333 or
_theResult___fst_exp__h443432 or
out_exp__h443951 or _theResult___exp__h443948)
begin
case (guard__h435333)
2'b0, 2'b01:
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 =
_theResult___fst_exp__h443432;
2'b10:
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 =
out_exp__h443951;
2'b11:
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 =
_theResult___exp__h443948;
endcase
end
always@(guard__h435333 or
_theResult___fst_exp__h443432 or _theResult___exp__h443948)
begin
case (guard__h435333)
2'b0:
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 =
_theResult___fst_exp__h443432;
2'b01, 2'b10, 2'b11:
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 =
_theResult___exp__h443948;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104 or
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093 or
_theResult___fst_exp__h443432)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h444026 =
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q104;
3'd1:
_theResult___fst_exp__h444026 =
CASE_guard35333_0b0_theResult___fst_exp43432_0_ETC__q105;
3'd2:
_theResult___fst_exp__h444026 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7090;
3'd3:
_theResult___fst_exp__h444026 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7093;
3'd4: _theResult___fst_exp__h444026 = _theResult___fst_exp__h443432;
default: _theResult___fst_exp__h444026 = 8'd0;
endcase
end
always@(guard__h452970 or
_theResult___fst_exp__h461198 or
out_exp__h461717 or _theResult___exp__h461714)
begin
case (guard__h452970)
2'b0, 2'b01:
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 =
_theResult___fst_exp__h461198;
2'b10:
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 =
out_exp__h461717;
2'b11:
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 =
_theResult___exp__h461714;
endcase
end
always@(guard__h452970 or
_theResult___fst_exp__h461198 or _theResult___exp__h461714)
begin
case (guard__h452970)
2'b0:
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 =
_theResult___fst_exp__h461198;
2'b01, 2'b10, 2'b11:
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 =
_theResult___exp__h461714;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110 or
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639 or
_theResult___fst_exp__h461198)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h461792 =
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q110;
3'd1:
_theResult___fst_exp__h461792 =
CASE_guard52970_0b0_theResult___fst_exp61198_0_ETC__q111;
3'd2:
_theResult___fst_exp__h461792 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7637;
3'd3:
_theResult___fst_exp__h461792 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7639;
3'd4: _theResult___fst_exp__h461792 = _theResult___fst_exp__h461198;
default: _theResult___fst_exp__h461792 = 8'd0;
endcase
end
always@(guard__h461806 or
_theResult___fst_exp__h469883 or
out_exp__h470353 or _theResult___exp__h470350)
begin
case (guard__h461806)
2'b0, 2'b01:
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 =
_theResult___fst_exp__h469883;
2'b10:
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 =
out_exp__h470353;
2'b11:
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 =
_theResult___exp__h470350;
endcase
end
always@(guard__h461806 or
_theResult___fst_exp__h469883 or _theResult___exp__h470350)
begin
case (guard__h461806)
2'b0:
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 =
_theResult___fst_exp__h469883;
2'b01, 2'b10, 2'b11:
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 =
_theResult___exp__h470350;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115 or
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708 or
_theResult___fst_exp__h469883)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_exp__h470428 =
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q115;
3'd1:
_theResult___fst_exp__h470428 =
CASE_guard61806_0b0_theResult___fst_exp69883_0_ETC__q116;
3'd2:
_theResult___fst_exp__h470428 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7706;
3'd3:
_theResult___fst_exp__h470428 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7708;
3'd4: _theResult___fst_exp__h470428 = _theResult___fst_exp__h469883;
default: _theResult___fst_exp__h470428 = 8'd0;
endcase
end
always@(guard__h444040 or
_theResult___snd__h452039 or
out_sfd__h452534 or _theResult___sfd__h452531)
begin
case (guard__h444040)
2'b0, 2'b01:
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 =
_theResult___snd__h452039[56:34];
2'b10:
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 =
out_sfd__h452534;
2'b11:
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 =
_theResult___sfd__h452531;
endcase
end
always@(guard__h444040 or
_theResult___snd__h452039 or _theResult___sfd__h452531)
begin
case (guard__h444040)
2'b0:
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 =
_theResult___snd__h452039[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 =
_theResult___sfd__h452531;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117 or
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758 or
_theResult___snd__h452039)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h452609 =
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q117;
3'd1:
_theResult___fst_sfd__h452609 =
CASE_guard44040_0b0_theResult___snd52039_BITS__ETC__q118;
3'd2:
_theResult___fst_sfd__h452609 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7756;
3'd3:
_theResult___fst_sfd__h452609 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7758;
3'd4: _theResult___fst_sfd__h452609 = _theResult___snd__h452039[56:34];
default: _theResult___fst_sfd__h452609 = 23'd0;
endcase
end
always@(guard__h435333 or
sfdin__h443426 or out_sfd__h443952 or _theResult___sfd__h443949)
begin
case (guard__h435333)
2'b0, 2'b01:
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 =
sfdin__h443426[56:34];
2'b10:
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 =
out_sfd__h443952;
2'b11:
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 =
_theResult___sfd__h443949;
endcase
end
always@(guard__h435333 or sfdin__h443426 or _theResult___sfd__h443949)
begin
case (guard__h435333)
2'b0:
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 =
sfdin__h443426[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 =
_theResult___sfd__h443949;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119 or
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737 or
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739 or
sfdin__h443426)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h444027 =
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q119;
3'd1:
_theResult___fst_sfd__h444027 =
CASE_guard35333_0b0_sfdin43426_BITS_56_TO_34_0_ETC__q120;
3'd2:
_theResult___fst_sfd__h444027 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7737;
3'd3:
_theResult___fst_sfd__h444027 =
IF_IF_IF_IF_0b0_CONCAT_NOT_coreFix_fpuMulDivEx_ETC___d7739;
3'd4: _theResult___fst_sfd__h444027 = sfdin__h443426[56:34];
default: _theResult___fst_sfd__h444027 = 23'd0;
endcase
end
always@(guard__h452970 or
sfdin__h461192 or out_sfd__h461718 or _theResult___sfd__h461715)
begin
case (guard__h452970)
2'b0, 2'b01:
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 =
sfdin__h461192[56:34];
2'b10:
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 =
out_sfd__h461718;
2'b11:
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 =
_theResult___sfd__h461715;
endcase
end
always@(guard__h452970 or sfdin__h461192 or _theResult___sfd__h461715)
begin
case (guard__h452970)
2'b0:
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 =
sfdin__h461192[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 =
_theResult___sfd__h461715;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121 or
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783 or
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785 or
sfdin__h461192)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h461793 =
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q121;
3'd1:
_theResult___fst_sfd__h461793 =
CASE_guard52970_0b0_sfdin61192_BITS_56_TO_34_0_ETC__q122;
3'd2:
_theResult___fst_sfd__h461793 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7783;
3'd3:
_theResult___fst_sfd__h461793 =
IF_IF_IF_IF_3970_MINUS_SEXT_coreFix_fpuMulDivE_ETC___d7785;
3'd4: _theResult___fst_sfd__h461793 = sfdin__h461192[56:34];
default: _theResult___fst_sfd__h461793 = 23'd0;
endcase
end
always@(guard__h461806 or
_theResult___snd__h469829 or
out_sfd__h470354 or _theResult___sfd__h470351)
begin
case (guard__h461806)
2'b0, 2'b01:
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 =
_theResult___snd__h469829[56:34];
2'b10:
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 =
out_sfd__h470354;
2'b11:
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 =
_theResult___sfd__h470351;
endcase
end
always@(guard__h461806 or
_theResult___snd__h469829 or _theResult___sfd__h470351)
begin
case (guard__h461806)
2'b0:
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 =
_theResult___snd__h469829[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 =
_theResult___sfd__h470351;
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123 or
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802 or
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804 or
_theResult___snd__h469829)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
_theResult___fst_sfd__h470429 =
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q123;
3'd1:
_theResult___fst_sfd__h470429 =
CASE_guard61806_0b0_theResult___snd69829_BITS__ETC__q124;
3'd2:
_theResult___fst_sfd__h470429 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7802;
3'd3:
_theResult___fst_sfd__h470429 =
IF_IF_IF_coreFix_fpuMulDivExe_0_fpuExec_double_ETC___d7804;
3'd4: _theResult___fst_sfd__h470429 = _theResult___snd__h469829[56:34];
default: _theResult___fst_sfd__h470429 = 23'd0;
endcase
end
always@(guard__h435333 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h435333)
2'b0, 2'b01, 2'b10:
CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 =
guard__h435333 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125 or
guard__h435333)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
CASE_guard35333_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q125;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
(guard__h435333 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h435333 != 2'b01 && guard__h435333 != 2'b10 &&
guard__h435333 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7834 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h435333 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h435333)
2'b0, 2'b01, 2'b10:
CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 =
guard__h435333 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126 or
guard__h435333)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
CASE_guard35333_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q126;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
(guard__h435333 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h435333 == 2'b01 || guard__h435333 == 2'b10 ||
guard__h435333 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7890 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h444040 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h444040)
2'b0, 2'b01, 2'b10:
CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 =
guard__h444040 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127 or
guard__h444040)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
CASE_guard44040_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q127;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
(guard__h444040 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h444040 == 2'b01 || guard__h444040 == 2'b10 ||
guard__h444040 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7897 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h444040 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h444040)
2'b0, 2'b01, 2'b10:
CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 =
guard__h444040 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128 or
guard__h444040)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
CASE_guard44040_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q128;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
(guard__h444040 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h444040 != 2'b01 && guard__h444040 != 2'b10 &&
guard__h444040 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7847 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h452970 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h452970)
2'b0, 2'b01, 2'b10:
CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 =
guard__h452970 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129 or
guard__h452970)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
CASE_guard52970_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q129;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
(guard__h452970 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h452970 == 2'b01 || guard__h452970 == 2'b10 ||
guard__h452970 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7907 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h461806 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h461806)
2'b0, 2'b01, 2'b10:
CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 =
guard__h461806 == 2'b11 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130 or
guard__h461806)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
CASE_guard61806_0b0_coreFix_fpuMulDivExe_0_fpu_ETC__q130;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
(guard__h461806 == 2'b0) ?
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
(guard__h461806 == 2'b01 || guard__h461806 == 2'b10 ||
guard__h461806 == 2'b11) &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7914 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h452970 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h452970)
2'b0, 2'b01, 2'b10:
CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 =
guard__h452970 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131 or
guard__h452970)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
CASE_guard52970_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q131;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
(guard__h452970 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h452970 != 2'b01 && guard__h452970 != 2'b10 &&
guard__h452970 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7864 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(guard__h461806 or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (guard__h461806)
2'b0, 2'b01, 2'b10:
CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
2'd3:
CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 =
guard__h461806 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get or
CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132 or
guard__h461806)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
CASE_guard61806_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q132;
3'd1:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
(guard__h461806 == 2'b0) ?
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68] :
guard__h461806 != 2'b01 && guard__h461806 != 2'b10 &&
guard__h461806 != 2'b11 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7877 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7900 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] ==
3'd4 &&
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get)
begin
case (coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40])
3'd0, 3'd1, 3'd2, 3'd3:
IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
default: IF_coreFix_fpuMulDivExe_0_fpuExec_sqrtQ_first__ETC___d7851 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$first_data[42:40] !=
3'd4 ||
!coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$response_get[68];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put or
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 =
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 =
coreFix_fpuMulDivExe_0_fpuExec_double_div$RDY_request_put;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 =
coreFix_fpuMulDivExe_0_fpuExec_double_sqrt$RDY_request_put;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8393 =
coreFix_fpuMulDivExe_0_regToExeQ$first[233:229] != 5'd28 ||
coreFix_fpuMulDivExe_0_fpuExec_double_fma$RDY_request_put;
endcase
end
always@(guard__h491411 or
_theResult___fst_exp__h499372 or _theResult___exp__h500027)
begin
case (guard__h491411)
2'b0:
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143 =
_theResult___fst_exp__h499372;
2'b01, 2'b10, 2'b11:
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143 =
_theResult___exp__h500027;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h499372 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010 or
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 =
_theResult___fst_exp__h499372;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9012;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9010;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 =
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q143;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9016 =
11'd0;
endcase
end
always@(guard__h491411 or
_theResult___fst_exp__h499372 or
out_exp__h500030 or _theResult___exp__h500027)
begin
case (guard__h491411)
2'b0, 2'b01:
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 =
_theResult___fst_exp__h499372;
2'b10:
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 =
out_exp__h500030;
2'b11:
CASE_guard91411_0b0_theResult___fst_exp99372_0_ETC__q144 =
_theResult___exp__h500027;
endcase
end
always@(guard__h491411 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h491411)
2'b0, 2'b01, 2'b10:
CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard91411_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q145 =
guard__h491411 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h491411)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
(guard__h491411 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h491411 == 2'b01 || guard__h491411 == 2'b10 ||
guard__h491411 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q146 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h500723 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h500723)
2'b0, 2'b01, 2'b10:
CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard00723_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q147 =
guard__h500723 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h500723)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
(guard__h500723 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h500723 == 2'b01 || guard__h500723 == 2'b10 ||
guard__h500723 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q148 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h509792 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h509792)
2'b0, 2'b01, 2'b10:
CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
2'd3:
CASE_guard09792_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q149 =
guard__h509792 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h509792)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
(guard__h509792 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171] :
(guard__h509792 == 2'b01 || guard__h509792 == 2'b10 ||
guard__h509792 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q150 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[203:172] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[171];
endcase
end
always@(guard__h569568 or
_theResult___fst_exp__h577529 or _theResult___exp__h578184)
begin
case (guard__h569568)
2'b0:
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160 =
_theResult___fst_exp__h577529;
2'b01, 2'b10, 2'b11:
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160 =
_theResult___exp__h578184;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h577529 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725 or
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 =
_theResult___fst_exp__h577529;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9727;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9725;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 =
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q160;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9731 =
11'd0;
endcase
end
always@(guard__h569568 or
_theResult___fst_exp__h577529 or
out_exp__h578187 or _theResult___exp__h578184)
begin
case (guard__h569568)
2'b0, 2'b01:
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 =
_theResult___fst_exp__h577529;
2'b10:
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 =
out_exp__h578187;
2'b11:
CASE_guard69568_0b0_theResult___fst_exp77529_0_ETC__q161 =
_theResult___exp__h578184;
endcase
end
always@(guard__h578880 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h578880)
2'b0, 2'b01, 2'b10:
CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard78880_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q162 =
guard__h578880 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578880)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
(guard__h578880 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h578880 == 2'b01 || guard__h578880 == 2'b10 ||
guard__h578880 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q163 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h569568 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h569568)
2'b0, 2'b01, 2'b10:
CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard69568_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q164 =
guard__h569568 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569568)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
(guard__h569568 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h569568 == 2'b01 || guard__h569568 == 2'b10 ||
guard__h569568 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q165 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h587949 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h587949)
2'b0, 2'b01, 2'b10:
CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard87949_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q166 =
guard__h587949 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587949)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] == 32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
(guard__h587949 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
(guard__h587949 == 2'b01 || guard__h587949 == 2'b10 ||
guard__h587949 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q167 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h578880 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h578880)
2'b0, 2'b01, 2'b10:
CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard78880_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q168 =
guard__h578880 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h578880)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
(guard__h578880 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h578880 != 2'b01 && guard__h578880 != 2'b10 &&
guard__h578880 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q169 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h587949 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h587949)
2'b0, 2'b01, 2'b10:
CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard87949_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q170 =
guard__h587949 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h587949)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
(guard__h587949 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h587949 != 2'b01 && guard__h587949 != 2'b10 &&
guard__h587949 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q171 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h569568 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h569568)
2'b0, 2'b01, 2'b10:
CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
2'd3:
CASE_guard69568_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q172 =
guard__h569568 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h569568)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] != 32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
(guard__h569568 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43] :
guard__h569568 != 2'b01 && guard__h569568 != 2'b10 &&
guard__h569568 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q173 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[75:44] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[43];
endcase
end
always@(guard__h530264 or
_theResult___fst_exp__h538225 or _theResult___exp__h538880)
begin
case (guard__h530264)
2'b0:
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183 =
_theResult___fst_exp__h538225;
2'b01, 2'b10, 2'b11:
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183 =
_theResult___exp__h538880;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h538225 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495 or
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 =
_theResult___fst_exp__h538225;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10497;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10495;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 =
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q183;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10501 =
11'd0;
endcase
end
always@(guard__h530264 or
_theResult___fst_exp__h538225 or
out_exp__h538883 or _theResult___exp__h538880)
begin
case (guard__h530264)
2'b0, 2'b01:
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 =
_theResult___fst_exp__h538225;
2'b10:
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 =
out_exp__h538883;
2'b11:
CASE_guard30264_0b0_theResult___fst_exp38225_0_ETC__q184 =
_theResult___exp__h538880;
endcase
end
always@(guard__h539576 or
_theResult___fst_exp__h547802 or _theResult___exp__h548531)
begin
case (guard__h539576)
2'b0:
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185 =
_theResult___fst_exp__h547802;
2'b01, 2'b10, 2'b11:
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185 =
_theResult___exp__h548531;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h547802 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533 or
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 =
_theResult___fst_exp__h547802;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10535;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10533;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 =
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q185;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10539 =
11'd0;
endcase
end
always@(guard__h539576 or
_theResult___fst_exp__h547802 or
out_exp__h548534 or _theResult___exp__h548531)
begin
case (guard__h539576)
2'b0, 2'b01:
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 =
_theResult___fst_exp__h547802;
2'b10:
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 =
out_exp__h548534;
2'b11:
CASE_guard39576_0b0_theResult___fst_exp47802_0_ETC__q186 =
_theResult___exp__h548531;
endcase
end
always@(guard__h548645 or
_theResult___fst_exp__h556635 or _theResult___exp__h557315)
begin
case (guard__h548645)
2'b0:
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187 =
_theResult___fst_exp__h556635;
2'b01, 2'b10, 2'b11:
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187 =
_theResult___exp__h557315;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h556635 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564 or
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 =
_theResult___fst_exp__h556635;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10566;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10564;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 =
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q187;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10570 =
11'd0;
endcase
end
always@(guard__h548645 or
_theResult___fst_exp__h556635 or
out_exp__h557318 or _theResult___exp__h557315)
begin
case (guard__h548645)
2'b0, 2'b01:
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 =
_theResult___fst_exp__h556635;
2'b10:
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 =
out_exp__h557318;
2'b11:
CASE_guard48645_0b0_theResult___fst_exp56635_0_ETC__q188 =
_theResult___exp__h557315;
endcase
end
always@(guard__h587949 or
_theResult___fst_exp__h595939 or _theResult___exp__h596619)
begin
case (guard__h587949)
2'b0:
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189 =
_theResult___fst_exp__h595939;
2'b01, 2'b10, 2'b11:
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189 =
_theResult___exp__h596619;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h595939 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794 or
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 =
_theResult___fst_exp__h595939;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9796;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9794;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 =
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q189;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9800 =
11'd0;
endcase
end
always@(guard__h587949 or
_theResult___fst_exp__h595939 or
out_exp__h596622 or _theResult___exp__h596619)
begin
case (guard__h587949)
2'b0, 2'b01:
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 =
_theResult___fst_exp__h595939;
2'b10:
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 =
out_exp__h596622;
2'b11:
CASE_guard87949_0b0_theResult___fst_exp95939_0_ETC__q190 =
_theResult___exp__h596619;
endcase
end
always@(guard__h578880 or
_theResult___fst_exp__h587106 or _theResult___exp__h587835)
begin
case (guard__h578880)
2'b0:
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191 =
_theResult___fst_exp__h587106;
2'b01, 2'b10, 2'b11:
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191 =
_theResult___exp__h587835;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h587106 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763 or
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 =
_theResult___fst_exp__h587106;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9765;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9763;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 =
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q191;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9769 =
11'd0;
endcase
end
always@(guard__h578880 or
_theResult___fst_exp__h587106 or
out_exp__h587838 or _theResult___exp__h587835)
begin
case (guard__h578880)
2'b0, 2'b01:
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 =
_theResult___fst_exp__h587106;
2'b10:
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 =
out_exp__h587838;
2'b11:
CASE_guard78880_0b0_theResult___fst_exp87106_0_ETC__q192 =
_theResult___exp__h587835;
endcase
end
always@(guard__h530264 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h530264)
2'b0, 2'b01, 2'b10:
CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard30264_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q193 =
guard__h530264 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530264)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
(guard__h530264 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h530264 == 2'b01 || guard__h530264 == 2'b10 ||
guard__h530264 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q194 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h539576 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h539576)
2'b0, 2'b01, 2'b10:
CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard39576_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q195 =
guard__h539576 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539576)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
(guard__h539576 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h539576 == 2'b01 || guard__h539576 == 2'b10 ||
guard__h539576 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q196 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h548645 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h548645)
2'b0, 2'b01, 2'b10:
CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard48645_0b0_coreFix_fpuMulDivExe_0_reg_ETC__q197 =
guard__h548645 == 2'b11 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548645)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
(guard__h548645 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
(guard__h548645 == 2'b01 || guard__h548645 == 2'b10 ||
guard__h548645 == 2'b11) &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q198 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] == 3'd1 &&
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] ==
32'hFFFFFFFF &&
coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h539576 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h539576)
2'b0, 2'b01, 2'b10:
CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard39576_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q199 =
guard__h539576 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h539576)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
(guard__h539576 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h539576 != 2'b01 && guard__h539576 != 2'b10 &&
guard__h539576 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q200 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h548645 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h548645)
2'b0, 2'b01, 2'b10:
CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard48645_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q201 =
guard__h548645 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h548645)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
(guard__h548645 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h548645 != 2'b01 && guard__h548645 != 2'b10 &&
guard__h548645 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q202 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h530264 or coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (guard__h530264)
2'b0, 2'b01, 2'b10:
CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
2'd3:
CASE_guard30264_0b0_NOT_coreFix_fpuMulDivExe_0_ETC__q203 =
guard__h530264 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or guard__h530264)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
3'd4:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
(guard__h530264 == 2'b0) ?
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107] :
guard__h530264 != 2'b01 && guard__h530264 != 2'b10 &&
guard__h530264 != 2'b11 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q204 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226] != 3'd1 ||
coreFix_fpuMulDivExe_0_regToExeQ$first[139:108] !=
32'hFFFFFFFF ||
!coreFix_fpuMulDivExe_0_regToExeQ$first[107];
endcase
end
always@(guard__h530264 or
_theResult___snd__h538176 or _theResult___sfd__h538881)
begin
case (guard__h530264)
2'b0:
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205 =
_theResult___snd__h538176[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205 =
_theResult___sfd__h538881;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h538176 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590 or
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 =
_theResult___snd__h538176[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10592;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10590;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 =
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q205;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10596 =
52'd0;
endcase
end
always@(guard__h530264 or
_theResult___snd__h538176 or
out_sfd__h538884 or _theResult___sfd__h538881)
begin
case (guard__h530264)
2'b0, 2'b01:
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 =
_theResult___snd__h538176[56:5];
2'b10:
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 =
out_sfd__h538884;
2'b11:
CASE_guard30264_0b0_theResult___snd38176_BITS__ETC__q206 =
_theResult___sfd__h538881;
endcase
end
always@(guard__h539576 or sfdin__h547796 or _theResult___sfd__h548532)
begin
case (guard__h539576)
2'b0:
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207 =
sfdin__h547796[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207 =
_theResult___sfd__h548532;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h547796 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616 or
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 =
sfdin__h547796[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10618;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d10616;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 =
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q207;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10622 =
52'd0;
endcase
end
always@(guard__h539576 or
sfdin__h547796 or out_sfd__h548535 or _theResult___sfd__h548532)
begin
case (guard__h539576)
2'b0, 2'b01:
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 =
sfdin__h547796[56:5];
2'b10:
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 =
out_sfd__h548535;
2'b11:
CASE_guard39576_0b0_sfdin47796_BITS_56_TO_5_0b_ETC__q208 =
_theResult___sfd__h548532;
endcase
end
always@(guard__h548645 or
_theResult___snd__h556581 or _theResult___sfd__h557316)
begin
case (guard__h548645)
2'b0:
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209 =
_theResult___snd__h556581[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209 =
_theResult___sfd__h557316;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h556581 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635 or
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 =
_theResult___snd__h556581[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10637;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d10635;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 =
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q209;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10641 =
52'd0;
endcase
end
always@(guard__h548645 or
_theResult___snd__h556581 or
out_sfd__h557319 or _theResult___sfd__h557316)
begin
case (guard__h548645)
2'b0, 2'b01:
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 =
_theResult___snd__h556581[56:5];
2'b10:
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 =
out_sfd__h557319;
2'b11:
CASE_guard48645_0b0_theResult___snd56581_BITS__ETC__q210 =
_theResult___sfd__h557316;
endcase
end
always@(guard__h500723 or
_theResult___fst_exp__h508949 or _theResult___exp__h509678)
begin
case (guard__h500723)
2'b0:
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211 =
_theResult___fst_exp__h508949;
2'b01, 2'b10, 2'b11:
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211 =
_theResult___exp__h509678;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h508949 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053 or
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 =
_theResult___fst_exp__h508949;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9055;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9053;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 =
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q211;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9059 =
11'd0;
endcase
end
always@(guard__h500723 or
_theResult___fst_exp__h508949 or
out_exp__h509681 or _theResult___exp__h509678)
begin
case (guard__h500723)
2'b0, 2'b01:
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 =
_theResult___fst_exp__h508949;
2'b10:
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 =
out_exp__h509681;
2'b11:
CASE_guard00723_0b0_theResult___fst_exp08949_0_ETC__q212 =
_theResult___exp__h509678;
endcase
end
always@(guard__h509792 or
_theResult___fst_exp__h517782 or _theResult___exp__h518462)
begin
case (guard__h509792)
2'b0:
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213 =
_theResult___fst_exp__h517782;
2'b01, 2'b10, 2'b11:
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213 =
_theResult___exp__h518462;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___fst_exp__h517782 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084 or
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 =
_theResult___fst_exp__h517782;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9086;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9084;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 =
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q213;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9090 =
11'd0;
endcase
end
always@(guard__h509792 or
_theResult___fst_exp__h517782 or
out_exp__h518465 or _theResult___exp__h518462)
begin
case (guard__h509792)
2'b0, 2'b01:
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 =
_theResult___fst_exp__h517782;
2'b10:
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 =
out_exp__h518465;
2'b11:
CASE_guard09792_0b0_theResult___fst_exp17782_0_ETC__q214 =
_theResult___exp__h518462;
endcase
end
always@(guard__h491411 or
_theResult___snd__h499323 or _theResult___sfd__h500028)
begin
case (guard__h491411)
2'b0:
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215 =
_theResult___snd__h499323[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215 =
_theResult___sfd__h500028;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h499323 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110 or
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 =
_theResult___snd__h499323[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9112;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9110;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 =
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q215;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9116 =
52'd0;
endcase
end
always@(guard__h491411 or
_theResult___snd__h499323 or
out_sfd__h500031 or _theResult___sfd__h500028)
begin
case (guard__h491411)
2'b0, 2'b01:
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 =
_theResult___snd__h499323[56:5];
2'b10:
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 =
out_sfd__h500031;
2'b11:
CASE_guard91411_0b0_theResult___snd99323_BITS__ETC__q216 =
_theResult___sfd__h500028;
endcase
end
always@(guard__h500723 or sfdin__h508943 or _theResult___sfd__h509679)
begin
case (guard__h500723)
2'b0:
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217 =
sfdin__h508943[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217 =
_theResult___sfd__h509679;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h508943 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137 or
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 =
sfdin__h508943[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9139;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9137;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 =
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q217;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9143 =
52'd0;
endcase
end
always@(guard__h500723 or
sfdin__h508943 or out_sfd__h509682 or _theResult___sfd__h509679)
begin
case (guard__h500723)
2'b0, 2'b01:
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 =
sfdin__h508943[56:5];
2'b10:
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 =
out_sfd__h509682;
2'b11:
CASE_guard00723_0b0_sfdin08943_BITS_56_TO_5_0b_ETC__q218 =
_theResult___sfd__h509679;
endcase
end
always@(guard__h509792 or
_theResult___snd__h517728 or _theResult___sfd__h518463)
begin
case (guard__h509792)
2'b0:
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219 =
_theResult___snd__h517728[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219 =
_theResult___sfd__h518463;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h517728 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156 or
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 =
_theResult___snd__h517728[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9158;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9156;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 =
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q219;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9162 =
52'd0;
endcase
end
always@(guard__h509792 or
_theResult___snd__h517728 or
out_sfd__h518466 or _theResult___sfd__h518463)
begin
case (guard__h509792)
2'b0, 2'b01:
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 =
_theResult___snd__h517728[56:5];
2'b10:
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 =
out_sfd__h518466;
2'b11:
CASE_guard09792_0b0_theResult___snd17728_BITS__ETC__q220 =
_theResult___sfd__h518463;
endcase
end
always@(guard__h569568 or
_theResult___snd__h577480 or _theResult___sfd__h578185)
begin
case (guard__h569568)
2'b0:
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221 =
_theResult___snd__h577480[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221 =
_theResult___sfd__h578185;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h577480 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820 or
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 =
_theResult___snd__h577480[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9822;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9820;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 =
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q221;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9826 =
52'd0;
endcase
end
always@(guard__h569568 or
_theResult___snd__h577480 or
out_sfd__h578188 or _theResult___sfd__h578185)
begin
case (guard__h569568)
2'b0, 2'b01:
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 =
_theResult___snd__h577480[56:5];
2'b10:
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 =
out_sfd__h578188;
2'b11:
CASE_guard69568_0b0_theResult___snd77480_BITS__ETC__q222 =
_theResult___sfd__h578185;
endcase
end
always@(guard__h578880 or sfdin__h587100 or _theResult___sfd__h587836)
begin
case (guard__h578880)
2'b0:
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223 =
sfdin__h587100[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223 =
_theResult___sfd__h587836;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
sfdin__h587100 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846 or
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 =
sfdin__h587100[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9848;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_coreFix_fpuMulD_ETC___d9846;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 =
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q223;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9852 =
52'd0;
endcase
end
always@(guard__h578880 or
sfdin__h587100 or out_sfd__h587839 or _theResult___sfd__h587836)
begin
case (guard__h578880)
2'b0, 2'b01:
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 =
sfdin__h587100[56:5];
2'b10:
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 =
out_sfd__h587839;
2'b11:
CASE_guard78880_0b0_sfdin87100_BITS_56_TO_5_0b_ETC__q224 =
_theResult___sfd__h587836;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10885 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10887 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10873;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10887 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10862;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10887 =
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10885;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10849 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10851 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10804;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10851 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10762;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10851 =
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10849;
endcase
end
always@(guard__h587949 or
_theResult___snd__h595885 or _theResult___sfd__h596620)
begin
case (guard__h587949)
2'b0:
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225 =
_theResult___snd__h595885[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225 =
_theResult___sfd__h596620;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
_theResult___snd__h595885 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867 or
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865 or
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 =
_theResult___snd__h595885[56:5];
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9867;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 =
IF_IF_IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_f_ETC___d9865;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 =
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q225;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9871 =
52'd0;
endcase
end
always@(guard__h587949 or
_theResult___snd__h595885 or
out_sfd__h596623 or _theResult___sfd__h596620)
begin
case (guard__h587949)
2'b0, 2'b01:
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 =
_theResult___snd__h595885[56:5];
2'b10:
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 =
out_sfd__h596623;
2'b11:
CASE_guard87949_0b0_theResult___snd95885_BITS__ETC__q226 =
_theResult___sfd__h596620;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10935 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10917;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10935 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10902;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10935 =
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10933;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10977 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10961;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10977 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10948;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10977 =
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d10975;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003 or
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11019 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d11003;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11019 =
NOT_IF_coreFix_fpuMulDivExe_0_regToExeQ_first__ETC___d10990;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d11019 =
coreFix_fpuMulDivExe_0_regToExeQ_first__368_BI_ETC___d11017;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 =
coreFix_aluExe_1_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first or
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227)
begin
case (coreFix_aluExe_1_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
coreFix_aluExe_1_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
{ coreFix_aluExe_1_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_1_regToExeQ$first[404:400],
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_399_ETC__q227,
coreFix_aluExe_1_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_416_ETC__q228 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_1_regToExeQ$first)
begin
case (coreFix_aluExe_1_regToExeQ$first[394:383])
12'd1971,
12'd1970,
12'd1969,
12'd1968,
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 =
coreFix_aluExe_1_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_1_regToExeQfirst_BITS_394_ETC__q229 =
12'd2303;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[399:397])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 =
coreFix_aluExe_0_regToExeQ$first[399:397];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first or
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230)
begin
case (coreFix_aluExe_0_regToExeQ$first[416:414])
3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
coreFix_aluExe_0_regToExeQ$first[416:396];
3'd4:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
{ coreFix_aluExe_0_regToExeQ$first[416:414],
9'h0AA,
coreFix_aluExe_0_regToExeQ$first[404:400],
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_399_ETC__q230,
coreFix_aluExe_0_regToExeQ$first[396] };
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_416_ETC__q231 =
{ 3'd5, 18'h2AAAA };
endcase
end
always@(coreFix_aluExe_0_regToExeQ$first)
begin
case (coreFix_aluExe_0_regToExeQ$first[394:383])
12'd1971,
12'd1970,
12'd1969,
12'd1968,
12'd3860,
12'd3859,
12'd3858,
12'd3857,
12'd2818,
12'd2816,
12'd836,
12'd835,
12'd834,
12'd833,
12'd832,
12'd774,
12'd773,
12'd772,
12'd771,
12'd770,
12'd769,
12'd768,
12'd384,
12'd324,
12'd323,
12'd322,
12'd321,
12'd320,
12'd262,
12'd261,
12'd260,
12'd256,
12'd2049,
12'd2048,
12'd3074,
12'd3073,
12'd3072,
12'd3,
12'd2,
12'd1:
CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 =
coreFix_aluExe_0_regToExeQ$first[394:383];
default: CASE_coreFix_aluExe_0_regToExeQfirst_BITS_394_ETC__q232 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 =
fetchStage$pipelines_0_first[172:161];
default: IF_fetchStage_pipelines_0_first__2697_BITS_172_ETC___d12908 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[67:64])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 =
fetchStage$pipelines_0_first[67:64];
4'd11:
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd10;
4'd12:
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd11;
4'd13:
IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 = 4'd12;
default: IF_fetchStage_pipelines_0_first__2697_BIT_68_2_ETC___d13062 =
4'd13;
endcase
end
always@(fetchStage$pipelines_0_first)
begin
case (fetchStage$pipelines_0_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 =
fetchStage$pipelines_0_first[177:175];
default: CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233 = 3'd7;
endcase
end
always@(fetchStage$pipelines_0_first or
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 =
fetchStage$pipelines_0_first[194:174];
3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 =
{ fetchStage$pipelines_0_first[194:192],
9'h0AA,
fetchStage$pipelines_0_first[182:178],
CASE_fetchStagepipelines_0_first_BITS_177_TO__ETC__q233,
fetchStage$pipelines_0_first[174] };
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d12826 =
21'd1485482;
endcase
end
always@(checkForException___d12942)
begin
case (checkForException___d12942[3:0])
4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9:
CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 =
checkForException___d12942[3:0];
4'd11: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd10;
4'd12: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd11;
4'd13: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 = 4'd12;
default: CASE_checkForException_2942_BITS_3_TO_0_0_chec_ETC__q234 =
4'd13;
endcase
end
always@(k__h664083 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h664083)
1'd0:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 =
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 =
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 =
coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13391 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387;
endcase
end
always@(k__h664083 or
coreFix_aluExe_0_rsAlu$canEnq or coreFix_aluExe_1_rsAlu$canEnq)
begin
case (k__h664083)
1'd0:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 =
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 =
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_0_first or
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355 or
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410 or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 =
NOT_SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__ETC___d13410;
3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 =
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13415 =
regRenamingTable_rename_0_canRename__3329_AND__ETC___d13355;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 =
!coreFix_memExe_lsq$enqLdTag[6];
default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 ||
fetchStage$pipelines_0_first[194:192] == 3'd1 &&
!specTagManager$canClaim;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13450 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445);
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[172:161])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
fetchStage$pipelines_1_first[172:161];
default: CASE_fetchStagepipelines_1_first_BITS_172_TO__ETC__q235 =
12'd2303;
endcase
end
always@(fetchStage$pipelines_1_first)
begin
case (fetchStage$pipelines_1_first[177:175])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 =
fetchStage$pipelines_1_first[177:175];
default: CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236 = 3'd7;
endcase
end
always@(fetchStage$pipelines_1_first or
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1, 3'd2, 3'd3:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 =
fetchStage$pipelines_1_first[194:174];
3'd4:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 =
{ fetchStage$pipelines_1_first[194:192],
9'h0AA,
fetchStage$pipelines_1_first[182:178],
CASE_fetchStagepipelines_1_first_BITS_177_TO__ETC__q236,
fetchStage$pipelines_1_first[174] };
default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13510 =
21'd1485482;
endcase
end
always@(idx__h678705 or
fetchStage$pipelines_0_canDeq or
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 or
coreFix_aluExe_0_rsAlu$canEnq or
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h678705)
1'd0:
SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13663 ||
!coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 =
fetchStage$pipelines_0_canDeq &&
NOT_fetchStage_pipelines_0_first__2697_BITS_19_ETC___d13669 ||
!coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
!coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q237 =
!coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_0_first or
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761 or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 ||
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13761;
3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 =
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13767 =
renameStage_rg_m_halt_req_2724_BIT_4_2725_OR_f_ETC___d13757;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13789 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387;
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 =
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13807 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
coreFix_memExe_lsq$enqLdTag[6];
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q238 =
coreFix_memExe_lsq$enqStTag[6];
endcase
end
always@(fetchStage$pipelines_1_first or
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 or
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773 or
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 or
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815 or
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 =
!SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 &&
NOT_fetchStage_pipelines_1_first__2706_BITS_19_ETC___d13773;
3'd2:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 =
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13804 &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13815;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 =
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13786 &&
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq &&
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13797;
default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13819 =
regRenamingTable_rename_1_canRename__3456_AND__ETC___d13655;
endcase
end
always@(k__h664083 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (k__h664083)
1'd0:
CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_k64083_0_coreFix_aluExe_0_rsAluRDY_enq_1_ETC__q239 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_0_first_BITS_191_TO__ETC__q240 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 =
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13864 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or
regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or
regRenamingTable$RDY_rename_0_getRename or
_0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 ||
regRenamingTable$RDY_rename_0_getRename &&
_0_OR_NOT_fetchStage_pipelines_0_first__2697_BI_ETC___d13845;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv$RDY_enq &&
regRenamingTable$RDY_rename_0_getRename;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13862 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 ||
regRenamingTable_RDY_rename_0_getRename__3231__ETC___d13858;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13878 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445);
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387 or
SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 or
specTagManager$canClaim or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 =
!SEL_ARR_NOT_coreFix_aluExe_0_rsAlu_canEnq__336_ETC___d13408 &&
(fetchStage$pipelines_0_first[194:192] != 3'd1 ||
specTagManager$canClaim);
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13885 =
fetchStage$pipelines_0_first[194:192] != 3'd2 ||
coreFix_memExe_rsMem$canEnq &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13387;
endcase
end
always@(idx__h678705 or
fetchStage$pipelines_0_canDeq or
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908 or
coreFix_aluExe_0_rsAlu$canEnq or
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915 or
coreFix_aluExe_1_rsAlu$canEnq)
begin
case (idx__h678705)
1'd0:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13908) &&
coreFix_aluExe_0_rsAlu$canEnq;
1'd1:
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 =
(!fetchStage$pipelines_0_canDeq ||
fetchStage_pipelines_0_first__2697_BITS_194_TO_ETC___d13915) &&
coreFix_aluExe_1_rsAlu$canEnq;
endcase
end
always@(fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935 or
coreFix_aluExe_0_rsAlu$RDY_enq or coreFix_aluExe_1_rsAlu$RDY_enq)
begin
case (fetchStage_pipelines_0_canDeq__2695_AND_NOT_fe_ETC___d13935)
1'd0:
CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 =
coreFix_aluExe_0_rsAlu$RDY_enq;
1'd1:
CASE_fetchStage_pipelines_0_canDeq__2695_AND_N_ETC__q241 =
coreFix_aluExe_1_rsAlu$RDY_enq;
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$RDY_enqSt or coreFix_memExe_lsq$RDY_enqLd)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
coreFix_memExe_lsq$RDY_enqLd;
default: CASE_fetchStagepipelines_1_first_BITS_191_TO__ETC__q242 =
coreFix_memExe_lsq$RDY_enqSt;
endcase
end
always@(fetchStage$pipelines_0_first or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374;
3'd3, 3'd4:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 =
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13973 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_rsMem$canEnq or
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445 or
SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374)
begin
case (fetchStage$pipelines_0_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961 =
!SEL_ARR_coreFix_aluExe_0_rsAlu_canEnq__3364_co_ETC___d13374;
default: IF_fetchStage_pipelines_0_first__2697_BITS_194_ETC___d13961 =
fetchStage$pipelines_0_first[194:192] == 3'd2 &&
(!coreFix_memExe_rsMem$canEnq ||
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d13445);
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982 or
SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689 or
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 =
SEL_ARR_fetchStage_pipelines_0_canDeq__2695_AN_ETC___d13689;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 =
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13970;
default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13985 =
fetchStage$pipelines_1_first[194:192] == 3'd2 &&
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13982;
endcase
end
always@(fetchStage$pipelines_1_first or
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 or
regRenamingTable$RDY_rename_1_getRename or
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953 or
SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 or
regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939 or
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 or
coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq or
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944)
begin
case (fetchStage$pipelines_1_first[194:192])
3'd0, 3'd1:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 =
!SEL_ARR_NOT_fetchStage_pipelines_0_canDeq__269_ETC___d13919 ||
regRenamingTable_RDY_rename_1_getRename__3921__ETC___d13939;
3'd3, 3'd4:
IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 =
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13941 ||
!coreFix_fpuMulDivExe_0_rsFpuMulDiv$canEnq ||
coreFix_fpuMulDivExe_0_rsFpuMulDiv_RDY_enq__38_ETC___d13944;
default: IF_fetchStage_pipelines_1_first__2706_BITS_194_ETC___d13958 =
fetchStage$pipelines_1_first[194:192] != 3'd2 ||
fetchStage_pipelines_0_canDeq__2695_AND_regRen_ETC___d13948 ||
regRenamingTable$RDY_rename_1_getRename &&
NOT_fetchStage_pipelines_0_canDeq__2695_2696_O_ETC___d13953;
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14042 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14039 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14048 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_0_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_0_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_0_first__2697_BITS_191_ETC___d14045 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 =
coreFix_memExe_lsq$enqLdTag[3:0];
default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14177 =
coreFix_memExe_lsq$enqStTag[3:0];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 =
!coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14175 =
!coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174 =
coreFix_memExe_lsq$enqLdTag[5];
default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14174 =
coreFix_memExe_lsq$enqStTag[5];
endcase
end
always@(fetchStage$pipelines_1_first or
coreFix_memExe_lsq$enqStTag or coreFix_memExe_lsq$enqLdTag)
begin
case (fetchStage$pipelines_1_first[191:189])
3'd0, 3'd2:
IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 =
coreFix_memExe_lsq$enqLdTag[4:0];
default: IF_fetchStage_pipelines_1_first__2706_BITS_191_ETC___d14176 =
coreFix_memExe_lsq$enqStTag[4:0];
endcase
end
always@(csrf_prv_reg or csrf_rg_dcsr)
begin
case (csrf_prv_reg)
2'd1:
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
!csrf_rg_dcsr[13];
2'd3:
CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
!csrf_rg_dcsr[15];
default: CASE_csrf_prv_reg_1_NOT_csrf_rg_dcsr_BIT_13_3__ETC__q243 =
!csrf_rg_dcsr[12];
endcase
end
always@(csrf_prv_reg or csrf_rg_dcsr)
begin
case (csrf_prv_reg)
2'd1:
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
csrf_rg_dcsr[13];
2'd3:
CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
csrf_rg_dcsr[15];
default: CASE_csrf_prv_reg_1_csrf_rg_dcsr_BIT_13_3_csrf_ETC__q244 =
csrf_rg_dcsr[12];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[180:169])
12'd1:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd0;
12'd2:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd1;
12'd3:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd2;
12'd256:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd8;
12'd260:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd9;
12'd261:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd10;
12'd262:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd11;
12'd320:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd12;
12'd321:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd13;
12'd322:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd14;
12'd323:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd15;
12'd324:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd16;
12'd384:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd17;
12'd768:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd18;
12'd769:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd19;
12'd770:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd20;
12'd771:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd21;
12'd772:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd22;
12'd773:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd23;
12'd774:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd24;
12'd832:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd25;
12'd833:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd26;
12'd834:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd27;
12'd835:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd28;
12'd836:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd29;
12'd1968:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd36;
12'd1969:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd37;
12'd1970:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd38;
12'd1971:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd39;
12'd2048:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd6;
12'd2049:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd7;
12'd2816:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd30;
12'd2818:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd31;
12'd3072:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd3;
12'd3073:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd4;
12'd3074:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd5;
12'd3857:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd32;
12'd3858:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd33;
12'd3859:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd34;
12'd3860:
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 = 6'd35;
default: IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 =
6'd40;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[511:448];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q245 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[511:448];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[447:384];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q246 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[447:384];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[383:320];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q247 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[383:320];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[319:256];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q248 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[319:256];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[255:192];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q249 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[255:192];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[191:128];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q250 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[191:128];
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0, 4'd1, 4'd3, 4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd11, 4'd14:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q251 =
4'd15;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[165:162])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 =
rob$deqPort_0_deq_data[165:162];
default: CASE_robdeqPort_0_deq_data_BITS_165_TO_162_0__ETC__q252 =
4'd15;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd0:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
3'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 = 3'd4;
3'd2:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 = 3'd3;
3'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 = 3'd2;
3'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 = 3'd1;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10714 =
3'd0;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq or
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first or
coreFix_memExe_stb$deq or
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 or
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_cRqMshr$pipelineResp_getRq[81:79])
3'd0, 3'd2, 3'd4:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
3'd1:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
{ coreFix_memExe_stb$deq[575] ?
coreFix_memExe_stb$deq[511:504] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:504],
coreFix_memExe_stb$deq[574] ?
coreFix_memExe_stb$deq[503:496] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[503:496],
coreFix_memExe_stb$deq[573] ?
coreFix_memExe_stb$deq[495:488] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[495:488],
coreFix_memExe_stb$deq[572] ?
coreFix_memExe_stb$deq[487:480] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[487:480],
coreFix_memExe_stb$deq[571] ?
coreFix_memExe_stb$deq[479:472] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[479:472],
coreFix_memExe_stb$deq[570] ?
coreFix_memExe_stb$deq[471:464] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[471:464],
coreFix_memExe_stb$deq[569] ?
coreFix_memExe_stb$deq[463:456] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[463:456],
coreFix_memExe_stb$deq[568] ?
coreFix_memExe_stb$deq[455:448] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[455:448],
coreFix_memExe_stb$deq[567] ?
coreFix_memExe_stb$deq[447:440] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[447:440],
coreFix_memExe_stb$deq[566] ?
coreFix_memExe_stb$deq[439:432] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[439:432],
coreFix_memExe_stb$deq[565] ?
coreFix_memExe_stb$deq[431:424] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[431:424],
coreFix_memExe_stb$deq[564] ?
coreFix_memExe_stb$deq[423:416] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[423:416],
coreFix_memExe_stb$deq[563] ?
coreFix_memExe_stb$deq[415:408] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[415:408],
coreFix_memExe_stb$deq[562] ?
coreFix_memExe_stb$deq[407:400] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[407:400],
coreFix_memExe_stb$deq[561] ?
coreFix_memExe_stb$deq[399:392] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[399:392],
coreFix_memExe_stb$deq[560] ?
coreFix_memExe_stb$deq[391:384] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[391:384],
coreFix_memExe_stb$deq[559] ?
coreFix_memExe_stb$deq[383:376] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[383:376],
coreFix_memExe_stb$deq[558] ?
coreFix_memExe_stb$deq[375:368] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[375:368],
coreFix_memExe_stb$deq[557] ?
coreFix_memExe_stb$deq[367:360] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[367:360],
coreFix_memExe_stb$deq[556] ?
coreFix_memExe_stb$deq[359:352] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[359:352],
coreFix_memExe_stb$deq[555] ?
coreFix_memExe_stb$deq[351:344] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[351:344],
coreFix_memExe_stb$deq[554] ?
coreFix_memExe_stb$deq[343:336] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[343:336],
coreFix_memExe_stb$deq[553] ?
coreFix_memExe_stb$deq[335:328] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[335:328],
coreFix_memExe_stb$deq[552] ?
coreFix_memExe_stb$deq[327:320] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[327:320],
coreFix_memExe_stb$deq[551] ?
coreFix_memExe_stb$deq[319:312] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[319:312],
coreFix_memExe_stb$deq[550] ?
coreFix_memExe_stb$deq[311:304] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[311:304],
coreFix_memExe_stb$deq[549] ?
coreFix_memExe_stb$deq[303:296] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[303:296],
coreFix_memExe_stb$deq[548] ?
coreFix_memExe_stb$deq[295:288] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[295:288],
coreFix_memExe_stb$deq[547] ?
coreFix_memExe_stb$deq[287:280] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[287:280],
coreFix_memExe_stb$deq[546] ?
coreFix_memExe_stb$deq[279:272] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[279:272],
coreFix_memExe_stb$deq[545] ?
coreFix_memExe_stb$deq[271:264] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[271:264],
coreFix_memExe_stb$deq[544] ?
coreFix_memExe_stb$deq[263:256] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[263:256],
coreFix_memExe_stb$deq[543] ?
coreFix_memExe_stb$deq[255:248] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[255:248],
coreFix_memExe_stb$deq[542] ?
coreFix_memExe_stb$deq[247:240] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[247:240],
coreFix_memExe_stb$deq[541] ?
coreFix_memExe_stb$deq[239:232] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[239:232],
coreFix_memExe_stb$deq[540] ?
coreFix_memExe_stb$deq[231:224] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[231:224],
coreFix_memExe_stb$deq[539] ?
coreFix_memExe_stb$deq[223:216] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[223:216],
coreFix_memExe_stb$deq[538] ?
coreFix_memExe_stb$deq[215:208] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[215:208],
coreFix_memExe_stb$deq[537] ?
coreFix_memExe_stb$deq[207:200] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[207:200],
coreFix_memExe_stb$deq[536] ?
coreFix_memExe_stb$deq[199:192] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[199:192],
coreFix_memExe_stb$deq[535] ?
coreFix_memExe_stb$deq[191:184] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[191:184],
coreFix_memExe_stb$deq[534] ?
coreFix_memExe_stb$deq[183:176] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[183:176],
coreFix_memExe_stb$deq[533] ?
coreFix_memExe_stb$deq[175:168] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[175:168],
coreFix_memExe_stb$deq[532] ?
coreFix_memExe_stb$deq[167:160] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[167:160],
coreFix_memExe_stb$deq[531] ?
coreFix_memExe_stb$deq[159:152] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[159:152],
coreFix_memExe_stb$deq[530] ?
coreFix_memExe_stb$deq[151:144] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[151:144],
coreFix_memExe_stb$deq[529] ?
coreFix_memExe_stb$deq[143:136] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[143:136],
coreFix_memExe_stb$deq[528] ?
coreFix_memExe_stb$deq[135:128] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[135:128],
coreFix_memExe_stb$deq[527] ?
coreFix_memExe_stb$deq[127:120] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[127:120],
coreFix_memExe_stb$deq[526] ?
coreFix_memExe_stb$deq[119:112] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[119:112],
coreFix_memExe_stb$deq[525] ?
coreFix_memExe_stb$deq[111:104] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[111:104],
coreFix_memExe_stb$deq[524] ?
coreFix_memExe_stb$deq[103:96] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[103:96],
coreFix_memExe_stb$deq[523] ?
coreFix_memExe_stb$deq[95:88] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[95:88],
coreFix_memExe_stb$deq[522] ?
coreFix_memExe_stb$deq[87:80] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[87:80],
coreFix_memExe_stb$deq[521] ?
coreFix_memExe_stb$deq[79:72] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[79:72],
coreFix_memExe_stb$deq[520] ?
coreFix_memExe_stb$deq[71:64] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[71:64],
coreFix_memExe_stb$deq[519] ?
coreFix_memExe_stb$deq[63:56] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[63:56],
coreFix_memExe_stb$deq[518] ?
coreFix_memExe_stb$deq[55:48] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[55:48],
coreFix_memExe_stb$deq[517] ?
coreFix_memExe_stb$deq[47:40] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[47:40],
coreFix_memExe_stb$deq[516] ?
coreFix_memExe_stb$deq[39:32] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[39:32],
coreFix_memExe_stb$deq[515] ?
coreFix_memExe_stb$deq[31:24] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[31:24],
coreFix_memExe_stb$deq[514] ?
coreFix_memExe_stb$deq[23:16] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[23:16],
coreFix_memExe_stb$deq[513] ?
coreFix_memExe_stb$deq[15:8] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[15:8],
coreFix_memExe_stb$deq[512] ?
coreFix_memExe_stb$deq[7:0] :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[7:0] };
3'd3:
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEh_ETC___d2146 ?
IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2204 :
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
default: IF_coreFix_memExe_dMem_cache_m_banks_0_cRqMshr_ETC___d2496 =
coreFix_memExe_dMem_cache_m_banks_0_pipeline$first[511:0];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[228:226])
3'd4, 3'd3, 3'd2, 3'd1, 3'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253 =
coreFix_fpuMulDivExe_0_regToExeQ$first[228:226];
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q253 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9881 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9937)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171;
5'd25:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9881;
5'd26, 5'd27:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9937;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9941 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9881;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[130:67];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q254 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[130:67];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[66:3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q255 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[66:3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[127:64];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q256 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[127:64];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[63:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q257 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[63:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[578:515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q258 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[578:515];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[514:513];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q259 =
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[514:513];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0[512];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rsToP_ETC__q260 =
!coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1[512];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[517:516];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q261 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[517:516];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[515];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q262 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[515];
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq or
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1, 5'd2, 5'd25, 5'd26, 5'd27, 5'd28:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 =
coreFix_fpuMulDivExe_0_fpuExec_fmaQ$RDY_enq;
5'd3:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 =
coreFix_fpuMulDivExe_0_fpuExec_divQ$RDY_enq;
5'd4:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 =
coreFix_fpuMulDivExe_0_fpuExec_sqrtQ$RDY_enq;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8406 =
coreFix_fpuMulDivExe_0_fpuExec_simpleQ$RDY_enq;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready or
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init or
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY or
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit or
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[229:228])
2'd0, 2'd1:
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425 =
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit != 2'd0 &&
coreFix_fpuMulDivExe_0_mulDivExec_mulQ$RDY_enq;
default: IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d8425 =
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_dividend_tready &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_divIfc$s_axis_divisor_tready &&
coreFix_fpuMulDivExe_0_mulDivExec_divQ$RDY_enq &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init &&
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_rg$IS_READY;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[5:4];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q263 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[5:4];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[3];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q264 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[3];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[2:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q265 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[2:0];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[71:8];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q266 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[71:8];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0[7:6];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_rqToP_ETC__q267 =
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1[7:6];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q268 =
!coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[582];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q269 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[582];
endcase
end
always@(mmio_dataReqQ_data_0)
begin
case (mmio_dataReqQ_data_0[77:76])
2'd0, 2'd1, 2'd2:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q271 =
mmio_dataReqQ_data_0[77:72];
2'd3:
CASE_mmio_dataReqQ_data_0_BITS_77_TO_76_0_mmio_ETC__q271 =
{ 2'd3, mmio_dataReqQ_data_0[75:72] };
endcase
end
always@(coreFix_memExe_lsq$firstSt)
begin
case (coreFix_memExe_lsq$firstSt[3:0])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q272 =
coreFix_memExe_lsq$firstSt[3:0];
default: CASE_coreFix_memExe_lsqfirstSt_BITS_3_TO_0_0__ETC__q272 =
4'd15;
endcase
end
always@(coreFix_memExe_lsq$firstLd)
begin
case (coreFix_memExe_lsq$firstLd[6:3])
4'd0,
4'd1,
4'd2,
4'd3,
4'd4,
4'd5,
4'd6,
4'd7,
4'd8,
4'd9,
4'd11,
4'd12,
4'd13:
CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q273 =
coreFix_memExe_lsq$firstLd[6:3];
default: CASE_coreFix_memExe_lsqfirstLd_BITS_6_TO_3_0__ETC__q273 =
4'd15;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q274 =
rob$deqPort_0_deq_data[180:169];
default: CASE_robdeqPort_0_deq_data_BITS_180_TO_169_1__ETC__q274 =
12'd2303;
endcase
end
always@(rob$deqPort_0_deq_data)
begin
case (rob$deqPort_0_deq_data[97:96])
2'd0, 2'd1:
CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q275 =
rob$deqPort_0_deq_data[97:96];
default: CASE_robdeqPort_0_deq_data_BITS_97_TO_96_0_ro_ETC__q275 = 2'd2;
endcase
end
always@(mmioToPlatform_pRq_enq_x)
begin
case (mmioToPlatform_pRq_enq_x[37:36])
2'd0, 2'd1, 2'd2:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q276 =
mmioToPlatform_pRq_enq_x[37:32];
2'd3:
CASE_mmioToPlatform_pRq_enq_x_BITS_37_TO_36_0__ETC__q276 =
{ 2'd3, mmioToPlatform_pRq_enq_x[35:32] };
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q277 =
coreFix_aluExe_0_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q277 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData or
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q277)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278 =
coreFix_aluExe_0_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278 =
{ coreFix_aluExe_0_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_0_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q277,
coreFix_aluExe_0_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q278 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_rsAlu$dispatchData)
begin
case (coreFix_aluExe_0_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279 =
coreFix_aluExe_0_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_0_rsAludispatchData_BITS__ETC__q279 =
12'd2303;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q280 =
coreFix_aluExe_0_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q280 = 3'd7;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first or
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q280)
begin
case (coreFix_aluExe_0_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q281 =
coreFix_aluExe_0_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q281 =
{ coreFix_aluExe_0_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_0_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q280,
coreFix_aluExe_0_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_15_ETC__q281 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_0_dispToRegQ$first)
begin
case (coreFix_aluExe_0_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282 =
coreFix_aluExe_0_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_0_dispToRegQfirst_BITS_13_ETC__q282 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[139:137])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q283 =
coreFix_aluExe_1_rsAlu$dispatchData[139:137];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q283 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData or
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q283)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[156:154])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284 =
coreFix_aluExe_1_rsAlu$dispatchData[156:136];
3'd4:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284 =
{ coreFix_aluExe_1_rsAlu$dispatchData[156:154],
9'h0AA,
coreFix_aluExe_1_rsAlu$dispatchData[144:140],
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q283,
coreFix_aluExe_1_rsAlu$dispatchData[136] };
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q284 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_rsAlu$dispatchData)
begin
case (coreFix_aluExe_1_rsAlu$dispatchData[134:123])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285 =
coreFix_aluExe_1_rsAlu$dispatchData[134:123];
default: CASE_coreFix_aluExe_1_rsAludispatchData_BITS__ETC__q285 =
12'd2303;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[135:133])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q286 =
coreFix_aluExe_1_dispToRegQ$first[135:133];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q286 = 3'd7;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first or
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q286)
begin
case (coreFix_aluExe_1_dispToRegQ$first[152:150])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q287 =
coreFix_aluExe_1_dispToRegQ$first[152:132];
3'd4:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q287 =
{ coreFix_aluExe_1_dispToRegQ$first[152:150],
9'h0AA,
coreFix_aluExe_1_dispToRegQ$first[140:136],
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q286,
coreFix_aluExe_1_dispToRegQ$first[132] };
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_15_ETC__q287 =
21'd1485482;
endcase
end
always@(coreFix_aluExe_1_dispToRegQ$first)
begin
case (coreFix_aluExe_1_dispToRegQ$first[130:119])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q288 =
coreFix_aluExe_1_dispToRegQ$first[130:119];
default: CASE_coreFix_aluExe_1_dispToRegQfirst_BITS_13_ETC__q288 =
12'd2303;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q289 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[69:67];
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q289 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData or
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q289)
begin
case (coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290 =
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:66];
3'd4:
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290 =
{ coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[86:84],
9'h0AA,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[74:70],
CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q289,
coreFix_fpuMulDivExe_0_rsFpuMulDiv$dispatchData[66] };
default: CASE_coreFix_fpuMulDivExe_0_rsFpuMulDivdispat_ETC__q290 =
21'd1485482;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171 or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10651 or
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704 or
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q291 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10651;
5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q291 =
coreFix_fpuMulDivExe_0_regToExeQ$first[225] ?
{ !coreFix_fpuMulDivExe_0_regToExeQ$first[139],
coreFix_fpuMulDivExe_0_regToExeQ$first[138:76] } :
{ IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10704,
IF_IF_coreFix_fpuMulDivExe_0_regToExeQ_first___ETC___d10649 };
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q291 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d9171;
endcase
end
always@(coreFix_fpuMulDivExe_0_regToExeQ$first or
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10651)
begin
case (coreFix_fpuMulDivExe_0_regToExeQ$first[233:229])
5'd0, 5'd1:
CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292 =
64'h3FF0000000000000;
default: CASE_coreFix_fpuMulDivExe_0_regToExeQfirst_BI_ETC__q292 =
IF_coreFix_fpuMulDivExe_0_regToExeQ_first__368_ETC___d10651;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58])
3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q293 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[60:58];
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q293 = 3'd7;
endcase
end
always@(coreFix_fpuMulDivExe_0_dispToRegQ$first or
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q293)
begin
case (coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75])
3'd0, 3'd1, 3'd2, 3'd3:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294 =
coreFix_fpuMulDivExe_0_dispToRegQ$first[77:57];
3'd4:
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294 =
{ coreFix_fpuMulDivExe_0_dispToRegQ$first[77:75],
9'h0AA,
coreFix_fpuMulDivExe_0_dispToRegQ$first[65:61],
CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q293,
coreFix_fpuMulDivExe_0_dispToRegQ$first[57] };
default: CASE_coreFix_fpuMulDivExe_0_dispToRegQfirst_B_ETC__q294 =
21'd1485482;
endcase
end
always@(coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 or
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1)
begin
case (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP)
1'd0:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0[1:0];
1'd1:
CASE_coreFix_memExe_dMem_cache_m_banks_0_fromP_ETC__q295 =
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1[1:0];
endcase
end
always@(rob$deqPort_1_deq_data)
begin
case (rob$deqPort_1_deq_data[180:169])
12'd1,
12'd2,
12'd3,
12'd256,
12'd260,
12'd261,
12'd262,
12'd320,
12'd321,
12'd322,
12'd323,
12'd324,
12'd384,
12'd768,
12'd769,
12'd770,
12'd771,
12'd772,
12'd773,
12'd774,
12'd832,
12'd833,
12'd834,
12'd835,
12'd836,
12'd1968,
12'd1969,
12'd1970,
12'd1971,
12'd2048,
12'd2049,
12'd2816,
12'd2818,
12'd3072,
12'd3073,
12'd3074,
12'd3857,
12'd3858,
12'd3859,
12'd3860:
CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296 =
rob$deqPort_1_deq_data[180:169];
default: CASE_robdeqPort_1_deq_data_BITS_180_TO_169_1__ETC__q296 =
12'd2303;
endcase
end
always@(rob$deqPort_1_deq_data)
begin
case (rob$deqPort_1_deq_data[97:96])
2'd0, 2'd1:
CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q297 =
rob$deqPort_1_deq_data[97:96];
default: CASE_robdeqPort_1_deq_data_BITS_97_TO_96_0_ro_ETC__q297 = 2'd2;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
134'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
commitStage_rg_serialnum <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
4'd0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
2'd3;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
3'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
3'd0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
4'd2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA80000000000000000;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
584'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
72'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
579'h00000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
1'd1;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
580'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
1'd0;
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY 69'd0;
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
70'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY 64'd0;
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY 5'd0;
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY 10'd0;
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY 3'd0;
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY 2'd0;
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY 44'd0;
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY 2'd3;
csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY 64'd1073741843;
csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY 64'd1879048192;
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY 4'd0;
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY 62'd0;
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY 64'd0;
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_brpred <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_caches <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_reservation <= `BSV_ASSIGNMENT_DELAY 1'd0;
flush_tlbs <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 2'd0;
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
142'h000000000000000004000000000000000000;
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
66'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 39'h0400000000;
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 40'h2AAAAAAAAA;
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY 67'h155555554AAAAAAAA;
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 68'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
outOfReset <= `BSV_ASSIGNMENT_DELAY 1'd0;
renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY 5'd10;
rg_core_run_state <= `BSV_ASSIGNMENT_DELAY 2'd2;
started <= `BSV_ASSIGNMENT_DELAY 1'd0;
update_vm_info <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (commitStage_commitTrap$EN)
commitStage_commitTrap <= `BSV_ASSIGNMENT_DELAY
commitStage_commitTrap$D_IN;
if (commitStage_rg_run_state$EN)
commitStage_rg_run_state <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_run_state$D_IN;
if (commitStage_rg_serialnum$EN)
commitStage_rg_serialnum <= `BSV_ASSIGNMENT_DELAY
commitStage_rg_serialnum$D_IN;
if (coreFix_doStatsReg$EN)
coreFix_doStatsReg <= `BSV_ASSIGNMENT_DELAY coreFix_doStatsReg$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$EN)
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0$D_IN;
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$EN)
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_processAmo$EN)
coreFix_memExe_dMem_cache_m_banks_0_processAmo <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_processAmo$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$EN)
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full$D_IN;
if (coreFix_memExe_dMem_perfReqQ_clearReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_clearReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_data_0$EN)
coreFix_memExe_dMem_perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_data_0$D_IN;
if (coreFix_memExe_dMem_perfReqQ_deqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_deqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_empty$EN)
coreFix_memExe_dMem_perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_empty$D_IN;
if (coreFix_memExe_dMem_perfReqQ_enqReq_rl$EN)
coreFix_memExe_dMem_perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_enqReq_rl$D_IN;
if (coreFix_memExe_dMem_perfReqQ_full$EN)
coreFix_memExe_dMem_perfReqQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_dMem_perfReqQ_full$D_IN;
if (coreFix_memExe_forwardQ_clearReq_rl$EN)
coreFix_memExe_forwardQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_clearReq_rl$D_IN;
if (coreFix_memExe_forwardQ_data_0$EN)
coreFix_memExe_forwardQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_0$D_IN;
if (coreFix_memExe_forwardQ_data_1$EN)
coreFix_memExe_forwardQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_data_1$D_IN;
if (coreFix_memExe_forwardQ_deqP$EN)
coreFix_memExe_forwardQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqP$D_IN;
if (coreFix_memExe_forwardQ_deqReq_rl$EN)
coreFix_memExe_forwardQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_deqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_empty$EN)
coreFix_memExe_forwardQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_empty$D_IN;
if (coreFix_memExe_forwardQ_enqP$EN)
coreFix_memExe_forwardQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqP$D_IN;
if (coreFix_memExe_forwardQ_enqReq_rl$EN)
coreFix_memExe_forwardQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_enqReq_rl$D_IN;
if (coreFix_memExe_forwardQ_full$EN)
coreFix_memExe_forwardQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_forwardQ_full$D_IN;
if (coreFix_memExe_memRespLdQ_clearReq_rl$EN)
coreFix_memExe_memRespLdQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_clearReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_data_0$EN)
coreFix_memExe_memRespLdQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_0$D_IN;
if (coreFix_memExe_memRespLdQ_data_1$EN)
coreFix_memExe_memRespLdQ_data_1 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_data_1$D_IN;
if (coreFix_memExe_memRespLdQ_deqP$EN)
coreFix_memExe_memRespLdQ_deqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqP$D_IN;
if (coreFix_memExe_memRespLdQ_deqReq_rl$EN)
coreFix_memExe_memRespLdQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_deqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_empty$EN)
coreFix_memExe_memRespLdQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_empty$D_IN;
if (coreFix_memExe_memRespLdQ_enqP$EN)
coreFix_memExe_memRespLdQ_enqP <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqP$D_IN;
if (coreFix_memExe_memRespLdQ_enqReq_rl$EN)
coreFix_memExe_memRespLdQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_enqReq_rl$D_IN;
if (coreFix_memExe_memRespLdQ_full$EN)
coreFix_memExe_memRespLdQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_memRespLdQ_full$D_IN;
if (coreFix_memExe_reqLdQ_data_0_rl$EN)
coreFix_memExe_reqLdQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLdQ_empty_rl$EN)
coreFix_memExe_reqLdQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_empty_rl$D_IN;
if (coreFix_memExe_reqLdQ_full_rl$EN)
coreFix_memExe_reqLdQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLdQ_full_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_data_0_rl$EN)
coreFix_memExe_reqLrScAmoQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_data_0_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_empty_rl$EN)
coreFix_memExe_reqLrScAmoQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_empty_rl$D_IN;
if (coreFix_memExe_reqLrScAmoQ_full_rl$EN)
coreFix_memExe_reqLrScAmoQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqLrScAmoQ_full_rl$D_IN;
if (coreFix_memExe_reqStQ_data_0_rl$EN)
coreFix_memExe_reqStQ_data_0_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_data_0_rl$D_IN;
if (coreFix_memExe_reqStQ_empty_rl$EN)
coreFix_memExe_reqStQ_empty_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_empty_rl$D_IN;
if (coreFix_memExe_reqStQ_full_rl$EN)
coreFix_memExe_reqStQ_full_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_reqStQ_full_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_clearReq_rl$EN)
coreFix_memExe_respLrScAmoQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_clearReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_data_0$EN)
coreFix_memExe_respLrScAmoQ_data_0 <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_data_0$D_IN;
if (coreFix_memExe_respLrScAmoQ_deqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_deqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_empty$EN)
coreFix_memExe_respLrScAmoQ_empty <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_empty$D_IN;
if (coreFix_memExe_respLrScAmoQ_enqReq_rl$EN)
coreFix_memExe_respLrScAmoQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_enqReq_rl$D_IN;
if (coreFix_memExe_respLrScAmoQ_full$EN)
coreFix_memExe_respLrScAmoQ_full <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_respLrScAmoQ_full$D_IN;
if (coreFix_memExe_waitLrScAmoMMIOResp$EN)
coreFix_memExe_waitLrScAmoMMIOResp <= `BSV_ASSIGNMENT_DELAY
coreFix_memExe_waitLrScAmoMMIOResp$D_IN;
if (csrInstOrInterruptInflight_rl$EN)
csrInstOrInterruptInflight_rl <= `BSV_ASSIGNMENT_DELAY
csrInstOrInterruptInflight_rl$D_IN;
if (csrf_external_int_en_vec_0$EN)
csrf_external_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_0$D_IN;
if (csrf_external_int_en_vec_1$EN)
csrf_external_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_1$D_IN;
if (csrf_external_int_en_vec_3$EN)
csrf_external_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_en_vec_3$D_IN;
if (csrf_external_int_pend_vec_0$EN)
csrf_external_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_0$D_IN;
if (csrf_external_int_pend_vec_1$EN)
csrf_external_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_1$D_IN;
if (csrf_external_int_pend_vec_3$EN)
csrf_external_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_external_int_pend_vec_3$D_IN;
if (csrf_fflags_reg$EN)
csrf_fflags_reg <= `BSV_ASSIGNMENT_DELAY csrf_fflags_reg$D_IN;
if (csrf_frm_reg$EN)
csrf_frm_reg <= `BSV_ASSIGNMENT_DELAY csrf_frm_reg$D_IN;
if (csrf_fs_reg$EN)
csrf_fs_reg <= `BSV_ASSIGNMENT_DELAY csrf_fs_reg$D_IN;
if (csrf_ie_vec_0$EN)
csrf_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_0$D_IN;
if (csrf_ie_vec_1$EN)
csrf_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_1$D_IN;
if (csrf_ie_vec_3$EN)
csrf_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_ie_vec_3$D_IN;
if (csrf_mcause_code_reg$EN)
csrf_mcause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_code_reg$D_IN;
if (csrf_mcause_interrupt_reg$EN)
csrf_mcause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcause_interrupt_reg$D_IN;
if (csrf_mcounteren_cy_reg$EN)
csrf_mcounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_cy_reg$D_IN;
if (csrf_mcounteren_ir_reg$EN)
csrf_mcounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_ir_reg$D_IN;
if (csrf_mcounteren_tm_reg$EN)
csrf_mcounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mcounteren_tm_reg$D_IN;
if (csrf_mcycle_ehr_data_rl$EN)
csrf_mcycle_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_mcycle_ehr_data_rl$D_IN;
if (csrf_medeleg_13_11_reg$EN)
csrf_medeleg_13_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_13_11_reg$D_IN;
if (csrf_medeleg_15_reg$EN)
csrf_medeleg_15_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_15_reg$D_IN;
if (csrf_medeleg_9_0_reg$EN)
csrf_medeleg_9_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_medeleg_9_0_reg$D_IN;
if (csrf_mepc_csr$EN)
csrf_mepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_mepc_csr$D_IN;
if (csrf_mideleg_11_reg$EN)
csrf_mideleg_11_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_11_reg$D_IN;
if (csrf_mideleg_1_0_reg$EN)
csrf_mideleg_1_0_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_1_0_reg$D_IN;
if (csrf_mideleg_5_3_reg$EN)
csrf_mideleg_5_3_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_5_3_reg$D_IN;
if (csrf_mideleg_9_7_reg$EN)
csrf_mideleg_9_7_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mideleg_9_7_reg$D_IN;
if (csrf_minstret_ehr_data_rl$EN)
csrf_minstret_ehr_data_rl <= `BSV_ASSIGNMENT_DELAY
csrf_minstret_ehr_data_rl$D_IN;
if (csrf_mpp_reg$EN)
csrf_mpp_reg <= `BSV_ASSIGNMENT_DELAY csrf_mpp_reg$D_IN;
if (csrf_mprv_reg$EN)
csrf_mprv_reg <= `BSV_ASSIGNMENT_DELAY csrf_mprv_reg$D_IN;
if (csrf_mscratch_csr$EN)
csrf_mscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_mscratch_csr$D_IN;
if (csrf_mtval_csr$EN)
csrf_mtval_csr <= `BSV_ASSIGNMENT_DELAY csrf_mtval_csr$D_IN;
if (csrf_mtvec_base_hi_reg$EN)
csrf_mtvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_base_hi_reg$D_IN;
if (csrf_mtvec_mode_low_reg$EN)
csrf_mtvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_mtvec_mode_low_reg$D_IN;
if (csrf_mxr_reg$EN)
csrf_mxr_reg <= `BSV_ASSIGNMENT_DELAY csrf_mxr_reg$D_IN;
if (csrf_ppn_reg$EN)
csrf_ppn_reg <= `BSV_ASSIGNMENT_DELAY csrf_ppn_reg$D_IN;
if (csrf_prev_ie_vec_0$EN)
csrf_prev_ie_vec_0 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_0$D_IN;
if (csrf_prev_ie_vec_1$EN)
csrf_prev_ie_vec_1 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_1$D_IN;
if (csrf_prev_ie_vec_3$EN)
csrf_prev_ie_vec_3 <= `BSV_ASSIGNMENT_DELAY csrf_prev_ie_vec_3$D_IN;
if (csrf_prv_reg$EN)
csrf_prv_reg <= `BSV_ASSIGNMENT_DELAY csrf_prv_reg$D_IN;
if (csrf_rg_dcsr$EN)
csrf_rg_dcsr <= `BSV_ASSIGNMENT_DELAY csrf_rg_dcsr$D_IN;
if (csrf_rg_dpc$EN)
csrf_rg_dpc <= `BSV_ASSIGNMENT_DELAY csrf_rg_dpc$D_IN;
if (csrf_scause_code_reg$EN)
csrf_scause_code_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_code_reg$D_IN;
if (csrf_scause_interrupt_reg$EN)
csrf_scause_interrupt_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scause_interrupt_reg$D_IN;
if (csrf_scounteren_cy_reg$EN)
csrf_scounteren_cy_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_cy_reg$D_IN;
if (csrf_scounteren_ir_reg$EN)
csrf_scounteren_ir_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_ir_reg$D_IN;
if (csrf_scounteren_tm_reg$EN)
csrf_scounteren_tm_reg <= `BSV_ASSIGNMENT_DELAY
csrf_scounteren_tm_reg$D_IN;
if (csrf_sepc_csr$EN)
csrf_sepc_csr <= `BSV_ASSIGNMENT_DELAY csrf_sepc_csr$D_IN;
if (csrf_software_int_en_vec_0$EN)
csrf_software_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_0$D_IN;
if (csrf_software_int_en_vec_1$EN)
csrf_software_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_1$D_IN;
if (csrf_software_int_en_vec_3$EN)
csrf_software_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_en_vec_3$D_IN;
if (csrf_software_int_pend_vec_0$EN)
csrf_software_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_0$D_IN;
if (csrf_software_int_pend_vec_1$EN)
csrf_software_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_1$D_IN;
if (csrf_software_int_pend_vec_3$EN)
csrf_software_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_software_int_pend_vec_3$D_IN;
if (csrf_spp_reg$EN)
csrf_spp_reg <= `BSV_ASSIGNMENT_DELAY csrf_spp_reg$D_IN;
if (csrf_sscratch_csr$EN)
csrf_sscratch_csr <= `BSV_ASSIGNMENT_DELAY csrf_sscratch_csr$D_IN;
if (csrf_stats_module_doStats$EN)
csrf_stats_module_doStats <= `BSV_ASSIGNMENT_DELAY
csrf_stats_module_doStats$D_IN;
if (csrf_stval_csr$EN)
csrf_stval_csr <= `BSV_ASSIGNMENT_DELAY csrf_stval_csr$D_IN;
if (csrf_stvec_base_hi_reg$EN)
csrf_stvec_base_hi_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_base_hi_reg$D_IN;
if (csrf_stvec_mode_low_reg$EN)
csrf_stvec_mode_low_reg <= `BSV_ASSIGNMENT_DELAY
csrf_stvec_mode_low_reg$D_IN;
if (csrf_sum_reg$EN)
csrf_sum_reg <= `BSV_ASSIGNMENT_DELAY csrf_sum_reg$D_IN;
if (csrf_time_reg$EN)
csrf_time_reg <= `BSV_ASSIGNMENT_DELAY csrf_time_reg$D_IN;
if (csrf_timer_int_en_vec_0$EN)
csrf_timer_int_en_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_0$D_IN;
if (csrf_timer_int_en_vec_1$EN)
csrf_timer_int_en_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_1$D_IN;
if (csrf_timer_int_en_vec_3$EN)
csrf_timer_int_en_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_en_vec_3$D_IN;
if (csrf_timer_int_pend_vec_0$EN)
csrf_timer_int_pend_vec_0 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_0$D_IN;
if (csrf_timer_int_pend_vec_1$EN)
csrf_timer_int_pend_vec_1 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_1$D_IN;
if (csrf_timer_int_pend_vec_3$EN)
csrf_timer_int_pend_vec_3 <= `BSV_ASSIGNMENT_DELAY
csrf_timer_int_pend_vec_3$D_IN;
if (csrf_tsr_reg$EN)
csrf_tsr_reg <= `BSV_ASSIGNMENT_DELAY csrf_tsr_reg$D_IN;
if (csrf_tvm_reg$EN)
csrf_tvm_reg <= `BSV_ASSIGNMENT_DELAY csrf_tvm_reg$D_IN;
if (csrf_tw_reg$EN)
csrf_tw_reg <= `BSV_ASSIGNMENT_DELAY csrf_tw_reg$D_IN;
if (csrf_vm_mode_sv39_reg$EN)
csrf_vm_mode_sv39_reg <= `BSV_ASSIGNMENT_DELAY
csrf_vm_mode_sv39_reg$D_IN;
if (flush_brpred$EN)
flush_brpred <= `BSV_ASSIGNMENT_DELAY flush_brpred$D_IN;
if (flush_caches$EN)
flush_caches <= `BSV_ASSIGNMENT_DELAY flush_caches$D_IN;
if (flush_reservation$EN)
flush_reservation <= `BSV_ASSIGNMENT_DELAY flush_reservation$D_IN;
if (flush_tlbs$EN)
flush_tlbs <= `BSV_ASSIGNMENT_DELAY flush_tlbs$D_IN;
if (mmio_cRqQ_clearReq_rl$EN)
mmio_cRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_clearReq_rl$D_IN;
if (mmio_cRqQ_data_0$EN)
mmio_cRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_data_0$D_IN;
if (mmio_cRqQ_deqReq_rl$EN)
mmio_cRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_deqReq_rl$D_IN;
if (mmio_cRqQ_empty$EN)
mmio_cRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_empty$D_IN;
if (mmio_cRqQ_enqReq_rl$EN)
mmio_cRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRqQ_enqReq_rl$D_IN;
if (mmio_cRqQ_full$EN)
mmio_cRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRqQ_full$D_IN;
if (mmio_cRsQ_clearReq_rl$EN)
mmio_cRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_clearReq_rl$D_IN;
if (mmio_cRsQ_data_0$EN)
mmio_cRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_data_0$D_IN;
if (mmio_cRsQ_deqReq_rl$EN)
mmio_cRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_deqReq_rl$D_IN;
if (mmio_cRsQ_empty$EN)
mmio_cRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_empty$D_IN;
if (mmio_cRsQ_enqReq_rl$EN)
mmio_cRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_cRsQ_enqReq_rl$D_IN;
if (mmio_cRsQ_full$EN)
mmio_cRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_cRsQ_full$D_IN;
if (mmio_dataPendQ_clearReq_rl$EN)
mmio_dataPendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_clearReq_rl$D_IN;
if (mmio_dataPendQ_deqReq_rl$EN)
mmio_dataPendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_deqReq_rl$D_IN;
if (mmio_dataPendQ_empty$EN)
mmio_dataPendQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_empty$D_IN;
if (mmio_dataPendQ_enqReq_rl$EN)
mmio_dataPendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_enqReq_rl$D_IN;
if (mmio_dataPendQ_full$EN)
mmio_dataPendQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataPendQ_full$D_IN;
if (mmio_dataReqQ_clearReq_rl$EN)
mmio_dataReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_clearReq_rl$D_IN;
if (mmio_dataReqQ_data_0$EN)
mmio_dataReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_data_0$D_IN;
if (mmio_dataReqQ_deqReq_rl$EN)
mmio_dataReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_deqReq_rl$D_IN;
if (mmio_dataReqQ_empty$EN)
mmio_dataReqQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_empty$D_IN;
if (mmio_dataReqQ_enqReq_rl$EN)
mmio_dataReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataReqQ_enqReq_rl$D_IN;
if (mmio_dataReqQ_full$EN)
mmio_dataReqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_dataReqQ_full$D_IN;
if (mmio_dataRespQ_clearReq_rl$EN)
mmio_dataRespQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_clearReq_rl$D_IN;
if (mmio_dataRespQ_data_0$EN)
mmio_dataRespQ_data_0 <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_data_0$D_IN;
if (mmio_dataRespQ_deqReq_rl$EN)
mmio_dataRespQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_deqReq_rl$D_IN;
if (mmio_dataRespQ_empty$EN)
mmio_dataRespQ_empty <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_empty$D_IN;
if (mmio_dataRespQ_enqReq_rl$EN)
mmio_dataRespQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_enqReq_rl$D_IN;
if (mmio_dataRespQ_full$EN)
mmio_dataRespQ_full <= `BSV_ASSIGNMENT_DELAY
mmio_dataRespQ_full$D_IN;
if (mmio_fromHostAddr$EN)
mmio_fromHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_fromHostAddr$D_IN;
if (mmio_pRqQ_clearReq_rl$EN)
mmio_pRqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_clearReq_rl$D_IN;
if (mmio_pRqQ_data_0$EN)
mmio_pRqQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_data_0$D_IN;
if (mmio_pRqQ_deqReq_rl$EN)
mmio_pRqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_deqReq_rl$D_IN;
if (mmio_pRqQ_empty$EN)
mmio_pRqQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_empty$D_IN;
if (mmio_pRqQ_enqReq_rl$EN)
mmio_pRqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRqQ_enqReq_rl$D_IN;
if (mmio_pRqQ_full$EN)
mmio_pRqQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRqQ_full$D_IN;
if (mmio_pRsQ_clearReq_rl$EN)
mmio_pRsQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_clearReq_rl$D_IN;
if (mmio_pRsQ_data_0$EN)
mmio_pRsQ_data_0 <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_data_0$D_IN;
if (mmio_pRsQ_deqReq_rl$EN)
mmio_pRsQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_deqReq_rl$D_IN;
if (mmio_pRsQ_empty$EN)
mmio_pRsQ_empty <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_empty$D_IN;
if (mmio_pRsQ_enqReq_rl$EN)
mmio_pRsQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
mmio_pRsQ_enqReq_rl$D_IN;
if (mmio_pRsQ_full$EN)
mmio_pRsQ_full <= `BSV_ASSIGNMENT_DELAY mmio_pRsQ_full$D_IN;
if (mmio_toHostAddr$EN)
mmio_toHostAddr <= `BSV_ASSIGNMENT_DELAY mmio_toHostAddr$D_IN;
if (outOfReset$EN)
outOfReset <= `BSV_ASSIGNMENT_DELAY outOfReset$D_IN;
if (renameStage_rg_m_halt_req$EN)
renameStage_rg_m_halt_req <= `BSV_ASSIGNMENT_DELAY
renameStage_rg_m_halt_req$D_IN;
if (rg_core_run_state$EN)
rg_core_run_state <= `BSV_ASSIGNMENT_DELAY rg_core_run_state$D_IN;
if (started$EN) started <= `BSV_ASSIGNMENT_DELAY started$D_IN;
if (update_vm_info$EN)
update_vm_info <= `BSV_ASSIGNMENT_DELAY update_vm_info$D_IN;
end
if (csrf_rg_dscratch0$EN)
csrf_rg_dscratch0 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch0$D_IN;
if (csrf_rg_dscratch1$EN)
csrf_rg_dscratch1 <= `BSV_ASSIGNMENT_DELAY csrf_rg_dscratch1$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
commitStage_commitTrap = 134'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
commitStage_rg_run_state = 1'h0;
commitStage_rg_serialnum = 64'hAAAAAAAAAAAAAAAA;
coreFix_doStatsReg = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_cnt = 4'hA;
coreFix_fpuMulDivExe_0_mulDivExec_divUnit_init_init = 1'h0;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit = 2'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_0 = 3'h2;
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_pipe_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_0 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_1 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_2 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_3 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_4 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_5 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_6 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_data_7 = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqP = 3'h2;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_enqReq_rl = 4'hA;
coreFix_memExe_dMem_cache_m_banks_0_cRqRetryIndexQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_0 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_data_1 =
583'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_enqReq_rl =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_fromPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_linkAddrEhr_rl = 59'h2AAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_processAmo =
161'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_empty_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqFromCQ_full_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_0 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_data_1 =
72'hAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_enqReq_rl =
73'h0AAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rqToPQ_full = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_0 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_data_1 =
579'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_empty = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqP = 1'h0;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_enqReq_rl =
580'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_dMem_cache_m_banks_0_rsToPQ_full = 1'h0;
coreFix_memExe_dMem_perfReqQ_clearReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_data_0 = 4'hA;
coreFix_memExe_dMem_perfReqQ_deqReq_rl = 1'h0;
coreFix_memExe_dMem_perfReqQ_empty = 1'h0;
coreFix_memExe_dMem_perfReqQ_enqReq_rl = 5'h0A;
coreFix_memExe_dMem_perfReqQ_full = 1'h0;
coreFix_memExe_forwardQ_clearReq_rl = 1'h0;
coreFix_memExe_forwardQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_deqP = 1'h0;
coreFix_memExe_forwardQ_deqReq_rl = 1'h0;
coreFix_memExe_forwardQ_empty = 1'h0;
coreFix_memExe_forwardQ_enqP = 1'h0;
coreFix_memExe_forwardQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_forwardQ_full = 1'h0;
coreFix_memExe_memRespLdQ_clearReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_data_0 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_data_1 = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_deqP = 1'h0;
coreFix_memExe_memRespLdQ_deqReq_rl = 1'h0;
coreFix_memExe_memRespLdQ_empty = 1'h0;
coreFix_memExe_memRespLdQ_enqP = 1'h0;
coreFix_memExe_memRespLdQ_enqReq_rl = 70'h2AAAAAAAAAAAAAAAAA;
coreFix_memExe_memRespLdQ_full = 1'h0;
coreFix_memExe_reqLdQ_data_0_rl = 69'h0AAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLdQ_empty_rl = 1'h0;
coreFix_memExe_reqLdQ_full_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_data_0_rl =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
coreFix_memExe_reqLrScAmoQ_empty_rl = 1'h0;
coreFix_memExe_reqLrScAmoQ_full_rl = 1'h0;
coreFix_memExe_reqStQ_data_0_rl = 66'h2AAAAAAAAAAAAAAAA;
coreFix_memExe_reqStQ_empty_rl = 1'h0;
coreFix_memExe_reqStQ_full_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_clearReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_data_0 = 64'hAAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_deqReq_rl = 1'h0;
coreFix_memExe_respLrScAmoQ_empty = 1'h0;
coreFix_memExe_respLrScAmoQ_enqReq_rl = 65'h0AAAAAAAAAAAAAAAA;
coreFix_memExe_respLrScAmoQ_full = 1'h0;
coreFix_memExe_waitLrScAmoMMIOResp = 3'h2;
csrInstOrInterruptInflight_rl = 1'h0;
csrf_external_int_en_vec_0 = 1'h0;
csrf_external_int_en_vec_1 = 1'h0;
csrf_external_int_en_vec_3 = 1'h0;
csrf_external_int_pend_vec_0 = 1'h0;
csrf_external_int_pend_vec_1 = 1'h0;
csrf_external_int_pend_vec_3 = 1'h0;
csrf_fflags_reg = 5'h0A;
csrf_frm_reg = 3'h2;
csrf_fs_reg = 2'h2;
csrf_ie_vec_0 = 1'h0;
csrf_ie_vec_1 = 1'h0;
csrf_ie_vec_3 = 1'h0;
csrf_mcause_code_reg = 4'hA;
csrf_mcause_interrupt_reg = 1'h0;
csrf_mcounteren_cy_reg = 1'h0;
csrf_mcounteren_ir_reg = 1'h0;
csrf_mcounteren_tm_reg = 1'h0;
csrf_mcycle_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_medeleg_13_11_reg = 3'h2;
csrf_medeleg_15_reg = 1'h0;
csrf_medeleg_9_0_reg = 10'h2AA;
csrf_mepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mideleg_11_reg = 1'h0;
csrf_mideleg_1_0_reg = 2'h2;
csrf_mideleg_5_3_reg = 3'h2;
csrf_mideleg_9_7_reg = 3'h2;
csrf_minstret_ehr_data_rl = 64'hAAAAAAAAAAAAAAAA;
csrf_mpp_reg = 2'h2;
csrf_mprv_reg = 1'h0;
csrf_mscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_mtvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_mtvec_mode_low_reg = 1'h0;
csrf_mxr_reg = 1'h0;
csrf_ppn_reg = 44'hAAAAAAAAAAA;
csrf_prev_ie_vec_0 = 1'h0;
csrf_prev_ie_vec_1 = 1'h0;
csrf_prev_ie_vec_3 = 1'h0;
csrf_prv_reg = 2'h2;
csrf_rg_dcsr = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dpc = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dscratch0 = 64'hAAAAAAAAAAAAAAAA;
csrf_rg_dscratch1 = 64'hAAAAAAAAAAAAAAAA;
csrf_scause_code_reg = 4'hA;
csrf_scause_interrupt_reg = 1'h0;
csrf_scounteren_cy_reg = 1'h0;
csrf_scounteren_ir_reg = 1'h0;
csrf_scounteren_tm_reg = 1'h0;
csrf_sepc_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_software_int_en_vec_0 = 1'h0;
csrf_software_int_en_vec_1 = 1'h0;
csrf_software_int_en_vec_3 = 1'h0;
csrf_software_int_pend_vec_0 = 1'h0;
csrf_software_int_pend_vec_1 = 1'h0;
csrf_software_int_pend_vec_3 = 1'h0;
csrf_spp_reg = 1'h0;
csrf_sscratch_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stats_module_doStats = 1'h0;
csrf_stval_csr = 64'hAAAAAAAAAAAAAAAA;
csrf_stvec_base_hi_reg = 62'h2AAAAAAAAAAAAAAA;
csrf_stvec_mode_low_reg = 1'h0;
csrf_sum_reg = 1'h0;
csrf_time_reg = 64'hAAAAAAAAAAAAAAAA;
csrf_timer_int_en_vec_0 = 1'h0;
csrf_timer_int_en_vec_1 = 1'h0;
csrf_timer_int_en_vec_3 = 1'h0;
csrf_timer_int_pend_vec_0 = 1'h0;
csrf_timer_int_pend_vec_1 = 1'h0;
csrf_timer_int_pend_vec_3 = 1'h0;
csrf_tsr_reg = 1'h0;
csrf_tvm_reg = 1'h0;
csrf_tw_reg = 1'h0;
csrf_vm_mode_sv39_reg = 1'h0;
flush_brpred = 1'h0;
flush_caches = 1'h0;
flush_reservation = 1'h0;
flush_tlbs = 1'h0;
mmio_cRqQ_clearReq_rl = 1'h0;
mmio_cRqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_deqReq_rl = 1'h0;
mmio_cRqQ_empty = 1'h0;
mmio_cRqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_cRqQ_full = 1'h0;
mmio_cRsQ_clearReq_rl = 1'h0;
mmio_cRsQ_data_0 = 1'h0;
mmio_cRsQ_deqReq_rl = 1'h0;
mmio_cRsQ_empty = 1'h0;
mmio_cRsQ_enqReq_rl = 2'h2;
mmio_cRsQ_full = 1'h0;
mmio_dataPendQ_clearReq_rl = 1'h0;
mmio_dataPendQ_deqReq_rl = 1'h0;
mmio_dataPendQ_empty = 1'h0;
mmio_dataPendQ_enqReq_rl = 1'h0;
mmio_dataPendQ_full = 1'h0;
mmio_dataReqQ_clearReq_rl = 1'h0;
mmio_dataReqQ_data_0 = 142'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_deqReq_rl = 1'h0;
mmio_dataReqQ_empty = 1'h0;
mmio_dataReqQ_enqReq_rl = 143'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
mmio_dataReqQ_full = 1'h0;
mmio_dataRespQ_clearReq_rl = 1'h0;
mmio_dataRespQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
mmio_dataRespQ_deqReq_rl = 1'h0;
mmio_dataRespQ_empty = 1'h0;
mmio_dataRespQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
mmio_dataRespQ_full = 1'h0;
mmio_fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
mmio_pRqQ_clearReq_rl = 1'h0;
mmio_pRqQ_data_0 = 39'h2AAAAAAAAA;
mmio_pRqQ_deqReq_rl = 1'h0;
mmio_pRqQ_empty = 1'h0;
mmio_pRqQ_enqReq_rl = 40'hAAAAAAAAAA;
mmio_pRqQ_full = 1'h0;
mmio_pRsQ_clearReq_rl = 1'h0;
mmio_pRsQ_data_0 = 67'h2AAAAAAAAAAAAAAAA;
mmio_pRsQ_deqReq_rl = 1'h0;
mmio_pRsQ_empty = 1'h0;
mmio_pRsQ_enqReq_rl = 68'hAAAAAAAAAAAAAAAAA;
mmio_pRsQ_full = 1'h0;
mmio_toHostAddr = 61'h0AAAAAAAAAAAAAAA;
outOfReset = 1'h0;
renameStage_rg_m_halt_req = 5'h0A;
rg_core_run_state = 2'h2;
started = 1'h0;
update_vm_info = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_outOfReset)
$fwrite(32'h80000002, "mkProc came out of reset\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_debug_csr_write &&
f_csr_reqs$D_OUT[75:64] == 12'd2048)
$display("[Terminate CSR] being written (val = %x), ",
"send terminate signal to host",
f_csr_reqs$D_OUT[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serialnum,
rob$deqPort_0_deq_data[282:219],
rob$deqPort_0_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd1 &&
rob$deqPort_0_deq_data[186:182] != 5'd2 &&
rob$deqPort_0_deq_data[186:182] != 5'd3 &&
rob$deqPort_0_deq_data[186:182] != 5'd4 &&
rob$deqPort_0_deq_data[186:182] != 5'd5 &&
rob$deqPort_0_deq_data[186:182] != 5'd6 &&
rob$deqPort_0_deq_data[186:182] != 5'd7 &&
rob$deqPort_0_deq_data[186:182] != 5'd8 &&
rob$deqPort_0_deq_data[186:182] != 5'd9 &&
rob$deqPort_0_deq_data[186:182] != 5'd10 &&
rob$deqPort_0_deq_data[186:182] != 5'd11 &&
rob$deqPort_0_deq_data[186:182] != 5'd12 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd14 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitTrap_flush)
$write(" [doCommitTrap]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serialnum,
rob$deqPort_0_deq_data[282:219],
rob$deqPort_0_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd0)
$write("Unsupported");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13)
$write("Csr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd15)
$write("FenceI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd16)
$write("SFence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd17)
$write("Ecall");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd18)
$write("Ebreak");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd19)
$write("Sret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd20)
$write("Mret");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] != 5'd0 &&
rob$deqPort_0_deq_data[186:182] != 5'd1 &&
rob$deqPort_0_deq_data[186:182] != 5'd2 &&
rob$deqPort_0_deq_data[186:182] != 5'd3 &&
rob$deqPort_0_deq_data[186:182] != 5'd4 &&
rob$deqPort_0_deq_data[186:182] != 5'd5 &&
rob$deqPort_0_deq_data[186:182] != 5'd6 &&
rob$deqPort_0_deq_data[186:182] != 5'd7 &&
rob$deqPort_0_deq_data[186:182] != 5'd8 &&
rob$deqPort_0_deq_data[186:182] != 5'd9 &&
rob$deqPort_0_deq_data[186:182] != 5'd10 &&
rob$deqPort_0_deq_data[186:182] != 5'd11 &&
rob$deqPort_0_deq_data[186:182] != 5'd12 &&
rob$deqPort_0_deq_data[186:182] != 5'd13 &&
rob$deqPort_0_deq_data[186:182] != 5'd14 &&
rob$deqPort_0_deq_data[186:182] != 5'd15 &&
rob$deqPort_0_deq_data[186:182] != 5'd16 &&
rob$deqPort_0_deq_data[186:182] != 5'd17 &&
rob$deqPort_0_deq_data[186:182] != 5'd18 &&
rob$deqPort_0_deq_data[186:182] != 5'd19 &&
rob$deqPort_0_deq_data[186:182] != 5'd20)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst)
$write(" [doCommitSystemInst]", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitSystemInst &&
rob$deqPort_0_deq_data[186:182] == 5'd13 &&
IF_rob_deqPort_0_deq_data__4237_BIT_181_4307_T_ETC___d14674 == 6'd6)
$display("[Terminate CSR] being written (val = %x), ",
"send terminate signal to host",
rob$deqPort_0_deq_data[95:32]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write("instret:%0d PC:0x%0h instr:0x%08h",
commitStage_rg_serialnum,
rob$deqPort_0_deq_data[282:219],
rob$deqPort_0_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_0_canDeq &&
rob$deqPort_0_deq_data[186:182] != 5'd1 &&
rob$deqPort_0_deq_data[186:182] != 5'd2 &&
rob$deqPort_0_deq_data[186:182] != 5'd3 &&
rob$deqPort_0_deq_data[186:182] != 5'd4 &&
rob$deqPort_0_deq_data[186:182] != 5'd5 &&
rob$deqPort_0_deq_data[186:182] != 5'd6 &&
rob$deqPort_0_deq_data[186:182] != 5'd7 &&
rob$deqPort_0_deq_data[186:182] != 5'd8 &&
rob$deqPort_0_deq_data[186:182] != 5'd9 &&
rob$deqPort_0_deq_data[186:182] != 5'd10 &&
rob$deqPort_0_deq_data[186:182] != 5'd11 &&
rob$deqPort_0_deq_data[186:182] != 5'd12 &&
rob$deqPort_0_deq_data[186:182] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst && rob$deqPort_0_canDeq)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd0), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20)
$write("instret:%0d PC:0x%0h instr:0x%08h",
x__h712697,
rob$deqPort_1_deq_data[282:219],
rob$deqPort_1_deq_data[218:187],
" iType:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd1)
$write("Nop");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd2)
$write("Amo");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd3)
$write("Alu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd4)
$write("Ld");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd5)
$write("St");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd6)
$write("Lr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd7)
$write("Sc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd8)
$write("J");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd9)
$write("Jr");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd10)
$write("Br");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd11)
$write("Auipc");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd12)
$write("Fpu");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] == 5'd14)
$write("Fence");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20 &&
rob$deqPort_1_deq_data[186:182] != 5'd1 &&
rob$deqPort_1_deq_data[186:182] != 5'd2 &&
rob$deqPort_1_deq_data[186:182] != 5'd3 &&
rob$deqPort_1_deq_data[186:182] != 5'd4 &&
rob$deqPort_1_deq_data[186:182] != 5'd5 &&
rob$deqPort_1_deq_data[186:182] != 5'd6 &&
rob$deqPort_1_deq_data[186:182] != 5'd7 &&
rob$deqPort_1_deq_data[186:182] != 5'd8 &&
rob$deqPort_1_deq_data[186:182] != 5'd9 &&
rob$deqPort_1_deq_data[186:182] != 5'd10 &&
rob$deqPort_1_deq_data[186:182] != 5'd11 &&
rob$deqPort_1_deq_data[186:182] != 5'd12 &&
rob$deqPort_1_deq_data[186:182] != 5'd14)
$write("Interrupt");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_commitStage_doCommitNormalInst &&
rob$deqPort_1_canDeq &&
rob$deqPort_1_deq_data[25] &&
!rob$deqPort_1_deq_data[18] &&
!rob$deqPort_1_deq_data[167] &&
rob$deqPort_1_deq_data[186:182] != 5'd0 &&
rob$deqPort_1_deq_data[186:182] != 5'd21 &&
rob$deqPort_1_deq_data[186:182] != 5'd17 &&
rob$deqPort_1_deq_data[186:182] != 5'd18 &&
rob$deqPort_1_deq_data[186:182] != 5'd13 &&
rob$deqPort_1_deq_data[186:182] != 5'd16 &&
rob$deqPort_1_deq_data[186:182] != 5'd15 &&
rob$deqPort_1_deq_data[186:182] != 5'd19 &&
rob$deqPort_1_deq_data[186:182] != 5'd20)
$write(" [doCommitNormalInst [%0d]]", $signed(32'd1), "\n");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_deqEn$whas &&
coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_credit == 2'd3)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
if (RST_N != `BSV_RESET_VALUE)
if (coreFix_fpuMulDivExe_0_mulDivExec_mulUnit_newReq$whas &&
v__h601727 == 2'd0)
$fdisplay(32'h80000002, "\n%m: ASSERT FAIL!!");
end
// synopsys translate_on
endmodule // mkCore
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