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e02b352bbb8a4af89ff729dca34aa43aa047a5dd
Toooba/src_SSITH_P3/Verilog_RTL/mkDM_System_Bus.v
rsnikhil 83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module 
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
2020-02-04 16:02:53 -05:00

1660 lines
59 KiB
Verilog
Raw Blame History

//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1 const
// av_read O 32
// RDY_av_read O 1
// RDY_write O 1
// master_awvalid O 1 reg
// master_awid O 4 reg
// master_awaddr O 64 reg
// master_awlen O 8 reg
// master_awsize O 3 reg
// master_awburst O 2 reg
// master_awlock O 1 reg
// master_awcache O 4 reg
// master_awprot O 3 reg
// master_awqos O 4 reg
// master_awregion O 4 reg
// master_wvalid O 1 reg
// master_wdata O 64 reg
// master_wstrb O 8 reg
// master_wlast O 1 reg
// master_bready O 1 reg
// master_arvalid O 1 reg
// master_arid O 4 reg
// master_araddr O 64 reg
// master_arlen O 8 reg
// master_arsize O 3 reg
// master_arburst O 2 reg
// master_arlock O 1 reg
// master_arcache O 4 reg
// master_arprot O 3 reg
// master_arqos O 4 reg
// master_arregion O 4 reg
// master_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// av_read_dm_addr I 7
// write_dm_addr I 7
// write_dm_word I 32
// master_awready I 1
// master_wready I 1
// master_bvalid I 1
// master_bid I 4 reg
// master_bresp I 2 reg
// master_arready I 1
// master_rvalid I 1
// master_rid I 4 reg
// master_rdata I 64 reg
// master_rresp I 2 reg
// master_rlast I 1 reg
// EN_reset I 1
// EN_write I 1
// EN_av_read I 1
//
// Combinational paths from inputs to outputs:
// av_read_dm_addr -> av_read
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkDM_System_Bus(CLK,
RST_N,
EN_reset,
RDY_reset,
av_read_dm_addr,
EN_av_read,
av_read,
RDY_av_read,
write_dm_addr,
write_dm_word,
EN_write,
RDY_write,
master_awvalid,
master_awid,
master_awaddr,
master_awlen,
master_awsize,
master_awburst,
master_awlock,
master_awcache,
master_awprot,
master_awqos,
master_awregion,
master_awready,
master_wvalid,
master_wdata,
master_wstrb,
master_wlast,
master_wready,
master_bvalid,
master_bid,
master_bresp,
master_bready,
master_arvalid,
master_arid,
master_araddr,
master_arlen,
master_arsize,
master_arburst,
master_arlock,
master_arcache,
master_arprot,
master_arqos,
master_arregion,
master_arready,
master_rvalid,
master_rid,
master_rdata,
master_rresp,
master_rlast,
master_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// actionvalue method av_read
input [6 : 0] av_read_dm_addr;
input EN_av_read;
output [31 : 0] av_read;
output RDY_av_read;
// action method write
input [6 : 0] write_dm_addr;
input [31 : 0] write_dm_word;
input EN_write;
output RDY_write;
// value method master_m_awvalid
output master_awvalid;
// value method master_m_awid
output [3 : 0] master_awid;
// value method master_m_awaddr
output [63 : 0] master_awaddr;
// value method master_m_awlen
output [7 : 0] master_awlen;
// value method master_m_awsize
output [2 : 0] master_awsize;
// value method master_m_awburst
output [1 : 0] master_awburst;
// value method master_m_awlock
output master_awlock;
// value method master_m_awcache
output [3 : 0] master_awcache;
// value method master_m_awprot
output [2 : 0] master_awprot;
// value method master_m_awqos
output [3 : 0] master_awqos;
// value method master_m_awregion
output [3 : 0] master_awregion;
// value method master_m_awuser
// action method master_m_awready
input master_awready;
// value method master_m_wvalid
output master_wvalid;
// value method master_m_wdata
output [63 : 0] master_wdata;
// value method master_m_wstrb
output [7 : 0] master_wstrb;
// value method master_m_wlast
output master_wlast;
// value method master_m_wuser
// action method master_m_wready
input master_wready;
// action method master_m_bvalid
input master_bvalid;
input [3 : 0] master_bid;
input [1 : 0] master_bresp;
// value method master_m_bready
output master_bready;
// value method master_m_arvalid
output master_arvalid;
// value method master_m_arid
output [3 : 0] master_arid;
// value method master_m_araddr
output [63 : 0] master_araddr;
// value method master_m_arlen
output [7 : 0] master_arlen;
// value method master_m_arsize
output [2 : 0] master_arsize;
// value method master_m_arburst
output [1 : 0] master_arburst;
// value method master_m_arlock
output master_arlock;
// value method master_m_arcache
output [3 : 0] master_arcache;
// value method master_m_arprot
output [2 : 0] master_arprot;
// value method master_m_arqos
output [3 : 0] master_arqos;
// value method master_m_arregion
output [3 : 0] master_arregion;
// value method master_m_aruser
// action method master_m_arready
input master_arready;
// action method master_m_rvalid
input master_rvalid;
input [3 : 0] master_rid;
input [63 : 0] master_rdata;
input [1 : 0] master_rresp;
input master_rlast;
// value method master_m_rready
output master_rready;
// signals for module outputs
reg [31 : 0] av_read;
wire [63 : 0] master_araddr, master_awaddr, master_wdata;
wire [7 : 0] master_arlen, master_awlen, master_wstrb;
wire [3 : 0] master_arcache,
master_arid,
master_arqos,
master_arregion,
master_awcache,
master_awid,
master_awqos,
master_awregion;
wire [2 : 0] master_arprot, master_arsize, master_awprot, master_awsize;
wire [1 : 0] master_arburst, master_awburst;
wire RDY_av_read,
RDY_reset,
RDY_write,
master_arlock,
master_arvalid,
master_awlock,
master_awvalid,
master_bready,
master_rready,
master_wlast,
master_wvalid;
// register rg_sb_state
reg [1 : 0] rg_sb_state;
wire [1 : 0] rg_sb_state$D_IN;
wire rg_sb_state$EN;
// register rg_sbaddress0
reg [31 : 0] rg_sbaddress0;
reg [31 : 0] rg_sbaddress0$D_IN;
wire rg_sbaddress0$EN;
// register rg_sbaddress1
reg [31 : 0] rg_sbaddress1;
reg [31 : 0] rg_sbaddress1$D_IN;
wire rg_sbaddress1$EN;
// register rg_sbaddress_reading
reg [63 : 0] rg_sbaddress_reading;
wire [63 : 0] rg_sbaddress_reading$D_IN;
wire rg_sbaddress_reading$EN;
// register rg_sbcs_sbaccess
reg [2 : 0] rg_sbcs_sbaccess;
wire [2 : 0] rg_sbcs_sbaccess$D_IN;
wire rg_sbcs_sbaccess$EN;
// register rg_sbcs_sbautoincrement
reg rg_sbcs_sbautoincrement;
wire rg_sbcs_sbautoincrement$D_IN, rg_sbcs_sbautoincrement$EN;
// register rg_sbcs_sbbusyerror
reg rg_sbcs_sbbusyerror;
reg rg_sbcs_sbbusyerror$D_IN;
wire rg_sbcs_sbbusyerror$EN;
// register rg_sbcs_sberror
reg [2 : 0] rg_sbcs_sberror;
reg [2 : 0] rg_sbcs_sberror$D_IN;
wire rg_sbcs_sberror$EN;
// register rg_sbcs_sbreadonaddr
reg rg_sbcs_sbreadonaddr;
wire rg_sbcs_sbreadonaddr$D_IN, rg_sbcs_sbreadonaddr$EN;
// register rg_sbcs_sbreadondata
reg rg_sbcs_sbreadondata;
wire rg_sbcs_sbreadondata$D_IN, rg_sbcs_sbreadondata$EN;
// register rg_sbdata0
reg [31 : 0] rg_sbdata0;
reg [31 : 0] rg_sbdata0$D_IN;
wire rg_sbdata0$EN;
// ports of submodule master_xactor_f_rd_addr
wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_sb_read_finish,
CAN_FIRE_RL_rl_sb_write_response,
CAN_FIRE_av_read,
CAN_FIRE_master_m_arready,
CAN_FIRE_master_m_awready,
CAN_FIRE_master_m_bvalid,
CAN_FIRE_master_m_rvalid,
CAN_FIRE_master_m_wready,
CAN_FIRE_reset,
CAN_FIRE_write,
WILL_FIRE_RL_rl_sb_read_finish,
WILL_FIRE_RL_rl_sb_write_response,
WILL_FIRE_av_read,
WILL_FIRE_master_m_arready,
WILL_FIRE_master_m_awready,
WILL_FIRE_master_m_bvalid,
WILL_FIRE_master_m_rvalid,
WILL_FIRE_master_m_wready,
WILL_FIRE_reset,
WILL_FIRE_write;
// inputs to muxes for submodule ports
reg [31 : 0] MUX_rg_sbaddress0$write_1__VAL_2,
MUX_rg_sbaddress1$write_1__VAL_2;
reg [2 : 0] MUX_rg_sbcs_sberror$write_1__VAL_4;
wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
wire MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_rg_sbaddress0$write_1__SEL_2,
MUX_rg_sbaddress0$write_1__SEL_3,
MUX_rg_sbaddress1$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2,
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_1,
MUX_rg_sbcs_sberror$write_1__SEL_3,
MUX_rg_sbcs_sberror$write_1__SEL_4,
MUX_rg_sbdata0$write_1__SEL_3;
// remaining internal signals
reg [63 : 0] CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1,
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53,
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66,
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103,
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79,
wrd_wdata__h4397;
reg [7 : 0] wrd_wstrb__h4398;
reg [2 : 0] x__h2654, x__h4302;
wire [63 : 0] _theResult___fst__h4340,
addr64__h3701,
result__h1250,
result__h1280,
result__h1307,
result__h1334,
result__h1361,
result__h1388,
result__h1415,
result__h1442,
result__h1487,
result__h1514,
result__h1541,
result__h1568,
result__h1609,
result__h1636,
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104,
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299,
sbaddress__h638,
word64__h4284;
wire [31 : 0] IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310,
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301,
v__h2132,
v__h2266;
wire [7 : 0] strobe64__h4339, strobe64__h4342, strobe64__h4345;
wire [5 : 0] shift_bits__h4287;
wire rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110,
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316,
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95,
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273,
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278,
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326;
// action method reset
assign RDY_reset = 1'd1 ;
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// actionvalue method av_read
always@(av_read_dm_addr or
v__h2132 or rg_sbaddress0 or rg_sbaddress1 or v__h2266)
begin
case (av_read_dm_addr)
7'h38: av_read = v__h2132;
7'h39: av_read = rg_sbaddress0;
7'h3A: av_read = rg_sbaddress1;
7'h3C: av_read = v__h2266;
default: av_read = 32'd0;
endcase
end
assign RDY_av_read =
rg_sb_state == 2'd0 &&
(rg_sbcs_sbbusyerror || rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadondata ||
master_xactor_f_rd_addr$FULL_N) ;
assign CAN_FIRE_av_read = RDY_av_read ;
assign WILL_FIRE_av_read = EN_av_read ;
// action method write
assign RDY_write = CAN_FIRE_write && !WILL_FIRE_RL_rl_sb_read_finish ;
assign CAN_FIRE_write =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
!rg_sbcs_sbreadonaddr ||
master_xactor_f_rd_addr$FULL_N) &&
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0 ||
master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N) ;
assign WILL_FIRE_write = EN_write ;
// value method master_m_awvalid
assign master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method master_m_awid
assign master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;
// value method master_m_awaddr
assign master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method master_m_awlen
assign master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method master_m_awsize
assign master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method master_m_awburst
assign master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method master_m_awlock
assign master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method master_m_awcache
assign master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method master_m_awprot
assign master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method master_m_awqos
assign master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method master_m_awregion
assign master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method master_m_awready
assign CAN_FIRE_master_m_awready = 1'd1 ;
assign WILL_FIRE_master_m_awready = 1'd1 ;
// value method master_m_wvalid
assign master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method master_m_wdata
assign master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method master_m_wstrb
assign master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method master_m_wlast
assign master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method master_m_wready
assign CAN_FIRE_master_m_wready = 1'd1 ;
assign WILL_FIRE_master_m_wready = 1'd1 ;
// action method master_m_bvalid
assign CAN_FIRE_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_master_m_bvalid = 1'd1 ;
// value method master_m_bready
assign master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method master_m_arvalid
assign master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method master_m_arid
assign master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;
// value method master_m_araddr
assign master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method master_m_arlen
assign master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method master_m_arsize
assign master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method master_m_arburst
assign master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method master_m_arlock
assign master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method master_m_arcache
assign master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method master_m_arprot
assign master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method master_m_arqos
assign master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method master_m_arregion
assign master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method master_m_arready
assign CAN_FIRE_master_m_arready = 1'd1 ;
assign WILL_FIRE_master_m_arready = 1'd1 ;
// action method master_m_rvalid
assign CAN_FIRE_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_master_m_rvalid = 1'd1 ;
// value method master_m_rready
assign master_rready = master_xactor_f_rd_data$FULL_N ;
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_sb_read_finish
assign CAN_FIRE_RL_rl_sb_read_finish =
master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 &&
rg_sbcs_sberror == 3'd0 ;
assign WILL_FIRE_RL_rl_sb_read_finish = CAN_FIRE_RL_rl_sb_read_finish ;
// rule RL_rl_sb_write_response
assign CAN_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_sb_write_response = master_xactor_f_wr_resp$EMPTY_N ;
// inputs to muxes for submodule ports
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ;
assign MUX_rg_sbaddress0$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
(rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
write_dm_addr == 7'h39 ||
write_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
assign MUX_rg_sbaddress0$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ;
assign MUX_rg_sbaddress1$write_1__SEL_2 =
EN_write && write_dm_addr != 7'h38 &&
((write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 ||
write_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95) ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ;
assign MUX_rg_sbcs_sbbusyerror$write_1__SEL_3 =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_1 =
master_xactor_f_wr_resp$EMPTY_N &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_3 =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_sbcs_sberror$write_1__SEL_4 =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ;
assign MUX_rg_sbdata0$write_1__SEL_3 =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 4'd0, sbaddress__h638, 8'd0, x__h2654, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 4'd0, addr64__h3701, 8'd0, x__h2654, 18'd65536 } ;
always@(write_dm_addr or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress0$write_1__VAL_2 =
IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310;
default: MUX_rg_sbaddress0$write_1__VAL_2 =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
endcase
end
always@(write_dm_addr or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 or
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301)
begin
case (write_dm_addr)
7'h39, 7'h3A:
MUX_rg_sbaddress1$write_1__VAL_2 =
IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301;
default: MUX_rg_sbaddress1$write_1__VAL_2 =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
endcase
end
always@(write_dm_word)
begin
case (write_dm_word[19:17])
3'd3, 3'd4: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd3;
default: MUX_rg_sbcs_sberror$write_1__VAL_4 = 3'd0;
endcase
end
// register rg_sb_state
assign rg_sb_state$D_IN =
(EN_reset || WILL_FIRE_RL_rl_sb_read_finish) ? 2'd0 : 2'd1 ;
assign rg_sb_state$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// register rg_sbaddress0
always@(EN_reset or
MUX_rg_sbaddress0$write_1__SEL_2 or
MUX_rg_sbaddress0$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
case (1'b1)
EN_reset: rg_sbaddress0$D_IN = 32'd0;
MUX_rg_sbaddress0$write_1__SEL_2:
rg_sbaddress0$D_IN = MUX_rg_sbaddress0$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress0$D_IN =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[31:0];
default: rg_sbaddress0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbaddress0$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
MUX_rg_sbaddress0$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress1
always@(EN_reset or
MUX_rg_sbaddress1$write_1__SEL_2 or
MUX_rg_sbaddress1$write_1__VAL_2 or
MUX_rg_sbaddress0$write_1__SEL_3 or
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104)
case (1'b1)
EN_reset: rg_sbaddress1$D_IN = 32'd0;
MUX_rg_sbaddress1$write_1__SEL_2:
rg_sbaddress1$D_IN = MUX_rg_sbaddress1$write_1__VAL_2;
MUX_rg_sbaddress0$write_1__SEL_3:
rg_sbaddress1$D_IN =
rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104[63:32];
default: rg_sbaddress1$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbaddress1$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 ||
MUX_rg_sbaddress1$write_1__SEL_2 ||
EN_reset ;
// register rg_sbaddress_reading
assign rg_sbaddress_reading$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
sbaddress__h638 :
addr64__h3701 ;
assign rg_sbaddress_reading$EN =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ;
// register rg_sbcs_sbaccess
assign rg_sbcs_sbaccess$D_IN = EN_reset ? 3'd2 : write_dm_word[19:17] ;
assign rg_sbcs_sbaccess$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbautoincrement
assign rg_sbcs_sbautoincrement$D_IN = !EN_reset && write_dm_word[16] ;
assign rg_sbcs_sbautoincrement$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbbusyerror
always@(EN_reset or
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2 or
write_dm_addr or MUX_rg_sbcs_sbbusyerror$write_1__SEL_3)
case (1'b1)
EN_reset: rg_sbcs_sbbusyerror$D_IN = 1'd0;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_2:
rg_sbcs_sbbusyerror$D_IN = write_dm_addr != 7'h38;
MUX_rg_sbcs_sbbusyerror$write_1__SEL_3: rg_sbcs_sbbusyerror$D_IN = 1'd1;
default: rg_sbcs_sbbusyerror$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign rg_sbcs_sbbusyerror$EN =
EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0 ||
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 ||
EN_reset ;
// register rg_sbcs_sberror
always@(MUX_rg_sbcs_sberror$write_1__SEL_1 or
EN_reset or
MUX_rg_sbcs_sberror$write_1__SEL_3 or
MUX_rg_sbcs_sberror$write_1__SEL_4 or
MUX_rg_sbcs_sberror$write_1__VAL_4)
case (1'b1)
MUX_rg_sbcs_sberror$write_1__SEL_1: rg_sbcs_sberror$D_IN = 3'd3;
EN_reset: rg_sbcs_sberror$D_IN = 3'd0;
MUX_rg_sbcs_sberror$write_1__SEL_3: rg_sbcs_sberror$D_IN = 3'd3;
MUX_rg_sbcs_sberror$write_1__SEL_4:
rg_sbcs_sberror$D_IN = MUX_rg_sbcs_sberror$write_1__VAL_4;
default: rg_sbcs_sberror$D_IN = 3'b010 /* unspecified value */ ;
endcase
assign rg_sbcs_sberror$EN =
WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
master_xactor_f_wr_resp$EMPTY_N &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ||
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 ||
EN_reset ;
// register rg_sbcs_sbreadonaddr
assign rg_sbcs_sbreadonaddr$D_IN = !EN_reset && write_dm_word[20] ;
assign rg_sbcs_sbreadonaddr$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbcs_sbreadondata
assign rg_sbcs_sbreadondata$D_IN = !EN_reset && write_dm_word[15] ;
assign rg_sbcs_sbreadondata$EN =
EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
EN_reset ;
// register rg_sbdata0
always@(EN_reset or
WILL_FIRE_RL_rl_sb_read_finish or
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 or
MUX_rg_sbdata0$write_1__SEL_3 or write_dm_word)
case (1'b1)
EN_reset: rg_sbdata0$D_IN = 32'd0;
WILL_FIRE_RL_rl_sb_read_finish:
rg_sbdata0$D_IN =
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79[31:0];
MUX_rg_sbdata0$write_1__SEL_3: rg_sbdata0$D_IN = write_dm_word;
default: rg_sbdata0$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
assign rg_sbdata0$EN =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ||
WILL_FIRE_RL_rl_sb_read_finish ||
EN_reset ;
// submodule master_xactor_f_rd_addr
assign master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 :
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ;
assign master_xactor_f_rd_addr$ENQ =
EN_av_read && av_read_dm_addr == 7'h3C &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 ||
EN_write && write_dm_addr == 7'h39 &&
rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && master_arready ;
assign master_xactor_f_rd_addr$CLR = 1'b0 ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ master_rid, master_rdata, master_rresp, master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
master_xactor_f_rd_data$EMPTY_N && rg_sb_state == 2'd1 &&
rg_sbcs_sberror == 3'd0 ;
assign master_xactor_f_rd_data$CLR = 1'b0 ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 4'd0, sbaddress__h638, 8'd0, x__h4302, 18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && master_awready ;
assign master_xactor_f_wr_addr$CLR = 1'b0 ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ wrd_wdata__h4397, wrd_wstrb__h4398, 1'd1 } ;
assign master_xactor_f_wr_data$ENQ =
EN_write &&
write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && master_wready ;
assign master_xactor_f_wr_data$CLR = 1'b0 ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { master_bid, master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = master_xactor_f_wr_resp$EMPTY_N ;
assign master_xactor_f_wr_resp$CLR = 1'b0 ;
// remaining internal signals
assign IF_rg_sbcs_sbreadonaddr_24_THEN_IF_rg_sbcs_sba_ETC___d310 =
rg_sbcs_sbreadonaddr ?
(rg_sbcs_sbautoincrement ?
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[31:0] :
write_dm_word) :
write_dm_word ;
assign IF_write_dm_addr_EQ_0x39_58_THEN_rg_sbaddress1_ETC___d301 =
(write_dm_addr == 7'h39) ?
rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299[63:32] :
write_dm_word ;
assign _theResult___fst__h4340 = word64__h4284 << shift_bits__h4287 ;
assign addr64__h3701 = { rg_sbaddress1, write_dm_word } ;
assign result__h1250 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h1280 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h1307 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h1334 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h1361 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h1388 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h1415 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h1442 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h1487 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h1514 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h1541 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h1568 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h1609 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h1636 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d110 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadondata ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d316 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbreadonaddr ;
assign rg_sb_state_EQ_0_7_AND_NOT_rg_sbcs_sbbusyerror_ETC___d95 =
rg_sb_state == 2'd0 && !rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 &&
rg_sbcs_sbautoincrement ;
assign rg_sbaddress1_7_CONCAT_rg_sbaddress0_8_9_PLUS__ETC___d104 =
sbaddress__h638 +
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
assign rg_sbaddress1_7_CONCAT_write_dm_word_98_PLUS_I_ETC___d299 =
addr64__h3701 +
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 ;
assign rg_sbcs_sberror_EQ_0_AND_rg_sbcs_sbreadonaddr__ETC___d291 =
rg_sbcs_sberror == 3'd0 &&
(rg_sbcs_sbreadonaddr && rg_sbcs_sbautoincrement ||
write_dm_addr != 7'h39) ;
assign sbaddress__h638 = { rg_sbaddress1, rg_sbaddress0 } ;
assign shift_bits__h4287 = { rg_sbaddress0[2:0], 3'b0 } ;
assign strobe64__h4339 = 8'b00000001 << rg_sbaddress0[2:0] ;
assign strobe64__h4342 = 8'b00000011 << rg_sbaddress0[2:0] ;
assign strobe64__h4345 = 8'b00001111 << rg_sbaddress0[2:0] ;
assign v__h2132 =
{ 9'd64,
rg_sbcs_sbbusyerror,
rg_sb_state != 2'd0,
rg_sbcs_sbreadonaddr,
rg_sbcs_sbaccess,
rg_sbcs_sbautoincrement,
rg_sbcs_sbreadondata,
rg_sbcs_sberror,
12'd2055 } ;
assign v__h2266 =
(rg_sb_state != 2'd0 || rg_sbcs_sbbusyerror ||
rg_sbcs_sberror != 3'd0) ?
32'd0 :
rg_sbdata0 ;
assign word64__h4284 = { 32'd0, write_dm_word } ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] != 3'd4 &&
write_dm_word[19:17] != 3'd3 ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d265 =
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d256 ||
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A ||
write_dm_addr == 7'h3C) &&
rg_sb_state != 2'd0 ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
rg_sbcs_sbbusyerror &&
!write_dm_word[22] ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d273 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) ;
assign write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278 =
write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
(write_dm_word[19:17] == 3'd4 || write_dm_word[19:17] == 3'd3) ;
assign write_dm_addr_EQ_0x3C_61_AND_rg_sb_state_EQ_0__ETC___d326 =
write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror == 3'd0 ;
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: x__h2654 = rg_sbcs_sbaccess;
default: x__h2654 = 3'b011;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2, 3'd3: x__h4302 = rg_sbcs_sbaccess;
default: x__h4302 = 3'b111;
endcase
end
always@(rg_sbcs_sbaccess or
strobe64__h4339 or strobe64__h4342 or strobe64__h4345)
begin
case (rg_sbcs_sbaccess)
3'd0: wrd_wstrb__h4398 = strobe64__h4339;
3'd1: wrd_wstrb__h4398 = strobe64__h4342;
3'd2: wrd_wstrb__h4398 = strobe64__h4345;
3'd3: wrd_wstrb__h4398 = 8'b11111111;
default: wrd_wstrb__h4398 = 8'd0;
endcase
end
always@(rg_sbcs_sbaccess or word64__h4284 or _theResult___fst__h4340)
begin
case (rg_sbcs_sbaccess)
3'd0, 3'd1, 3'd2: wrd_wdata__h4397 = _theResult___fst__h4340;
default: wrd_wdata__h4397 = word64__h4284;
endcase
end
always@(rg_sbcs_sbaccess)
begin
case (rg_sbcs_sbaccess)
3'd0: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd1;
3'd1: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd2;
3'd2: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd4;
3'd3: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 = 64'd8;
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_1_ELSE_IF_rg_ETC___d103 =
64'd16;
endcase
end
always@(rg_sbaddress_reading or
result__h1250 or
result__h1280 or
result__h1307 or
result__h1334 or
result__h1361 or result__h1388 or result__h1415 or result__h1442)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1250;
3'h1:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1280;
3'h2:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1307;
3'h3:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1334;
3'h4:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1361;
3'h5:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1388;
3'h6:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1415;
3'h7:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 =
result__h1442;
endcase
end
always@(rg_sbaddress_reading or
result__h1487 or result__h1514 or result__h1541 or result__h1568)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1487;
3'h2:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1514;
3'h4:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1541;
3'h6:
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
result__h1568;
default: IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 =
64'd0;
endcase
end
always@(rg_sbaddress_reading or result__h1609 or result__h1636)
begin
case (rg_sbaddress_reading[2:0])
3'h0:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
result__h1609;
3'h4:
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 =
result__h1636;
default: CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 = 64'd0;
endcase
end
always@(rg_sbcs_sbaccess or
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53 or
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66 or
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1 or
rg_sbaddress_reading or master_xactor_f_rd_data$D_OUT)
begin
case (rg_sbcs_sbaccess)
3'd0:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d53;
3'd1:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
IF_rg_sbaddress_reading_0_BITS_2_TO_0_1_EQ_0x0_ETC___d66;
3'd2:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
CASE_rg_sbaddress_reading_BITS_2_TO_0_0x0_resu_ETC__q1;
3'd3:
IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
(rg_sbaddress_reading[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
default: IF_rg_sbcs_sbaccess_8_EQ_0_9_THEN_IF_rg_sbaddr_ETC___d79 =
64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
end
else
begin
if (rg_sbaddress0$EN)
rg_sbaddress0 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress0$D_IN;
if (rg_sbaddress1$EN)
rg_sbaddress1 <= `BSV_ASSIGNMENT_DELAY rg_sbaddress1$D_IN;
end
if (rg_sb_state$EN) rg_sb_state <= `BSV_ASSIGNMENT_DELAY rg_sb_state$D_IN;
if (rg_sbaddress_reading$EN)
rg_sbaddress_reading <= `BSV_ASSIGNMENT_DELAY rg_sbaddress_reading$D_IN;
if (rg_sbcs_sbaccess$EN)
rg_sbcs_sbaccess <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbaccess$D_IN;
if (rg_sbcs_sbautoincrement$EN)
rg_sbcs_sbautoincrement <= `BSV_ASSIGNMENT_DELAY
rg_sbcs_sbautoincrement$D_IN;
if (rg_sbcs_sbbusyerror$EN)
rg_sbcs_sbbusyerror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbbusyerror$D_IN;
if (rg_sbcs_sberror$EN)
rg_sbcs_sberror <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sberror$D_IN;
if (rg_sbcs_sbreadonaddr$EN)
rg_sbcs_sbreadonaddr <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadonaddr$D_IN;
if (rg_sbcs_sbreadondata$EN)
rg_sbcs_sbreadondata <= `BSV_ASSIGNMENT_DELAY rg_sbcs_sbreadondata$D_IN;
if (rg_sbdata0$EN) rg_sbdata0 <= `BSV_ASSIGNMENT_DELAY rg_sbdata0$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_sb_state = 2'h2;
rg_sbaddress0 = 32'hAAAAAAAA;
rg_sbaddress1 = 32'hAAAAAAAA;
rg_sbaddress_reading = 64'hAAAAAAAAAAAAAAAA;
rg_sbcs_sbaccess = 3'h2;
rg_sbcs_sbautoincrement = 1'h0;
rg_sbcs_sbbusyerror = 1'h0;
rg_sbcs_sberror = 3'h2;
rg_sbcs_sbreadonaddr = 1'h0;
rg_sbcs_sbreadondata = 1'h0;
rg_sbdata0 = 32'hAAAAAAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.read: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.read: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.read: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("DM_System_Bus.read: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h14)
$write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h19)
$write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h40)
$write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h5F)
$write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h16)
$write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h18)
$write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3B)
$write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C &&
av_read_dm_addr != 7'h10 &&
av_read_dm_addr != 7'h11 &&
av_read_dm_addr != 7'h12 &&
av_read_dm_addr != 7'h13 &&
av_read_dm_addr != 7'h14 &&
av_read_dm_addr != 7'h15 &&
av_read_dm_addr != 7'h19 &&
av_read_dm_addr != 7'h30 &&
av_read_dm_addr != 7'h40 &&
av_read_dm_addr != 7'h5F &&
av_read_dm_addr != 7'h60 &&
av_read_dm_addr != 7'h16 &&
av_read_dm_addr != 7'h17 &&
av_read_dm_addr != 7'h04 &&
av_read_dm_addr != 7'h05 &&
av_read_dm_addr != 7'h06 &&
av_read_dm_addr != 7'h07 &&
av_read_dm_addr != 7'h08 &&
av_read_dm_addr != 7'h09 &&
av_read_dm_addr != 7'h0A &&
av_read_dm_addr != 7'h0B &&
av_read_dm_addr != 7'h0C &&
av_read_dm_addr != 7'h0D &&
av_read_dm_addr != 7'h0F &&
av_read_dm_addr != 7'h18 &&
av_read_dm_addr != 7'h20 &&
av_read_dm_addr != 7'h3B &&
av_read_dm_addr != 7'h3D &&
av_read_dm_addr != 7'h3E &&
av_read_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>",
av_read_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_av_read && av_read_dm_addr != 7'h38 &&
av_read_dm_addr != 7'h39 &&
av_read_dm_addr != 7'h3A &&
av_read_dm_addr != 7'h3C)
$write("] not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" ERROR: existing sberror (0x%0h) is not being cleared.",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 && rg_sbcs_sberror != 3'd0 &&
write_dm_word[14:12] == 3'd0)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display(" ERROR: existing sbbusyerror (%0d) is not being cleared.",
rg_sbcs_sbbusyerror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d271)
$display(" Must be cleared to re-enable system bus access.");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$display("DM_System_Bus.sbcs_write <= 0x%08h: ERROR", write_dm_word);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$write(" ERROR: sbaccess ");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd3)
$write("DM_SBACCESS_64_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h38 &&
(rg_sbcs_sberror == 3'd0 || write_dm_word[14:12] != 3'd0) &&
(!rg_sbcs_sbbusyerror || write_dm_word[22]) &&
write_dm_word[19:17] == 3'd4)
$write("DM_SBACCESS_128_BIT");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write &&
write_dm_addr_EQ_0x38_41_AND_rg_sbcs_sberror_E_ETC___d278)
$write(" not supported", "\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbaddress.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbaddress.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 &&
(write_dm_addr == 7'h39 || write_dm_addr == 7'h3A) &&
rg_sb_state != 2'd0)
$display("DM_System_Bus.sbaddress.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
rg_sbcs_sbbusyerror)
$display("DM_System_Bus.sbdata.write: ignoring due to sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state == 2'd0 &&
!rg_sbcs_sbbusyerror &&
rg_sbcs_sberror != 3'd0)
$display("DM_System_Bus.sbdata.write: ignoring due to sberror = 0x%0h",
rg_sbcs_sberror);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3C && rg_sb_state != 2'd0)
$display("DM_System_Bus.sbdata.write: busy, setting sbbusyerror");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("DM_System_Bus.write: [");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h10) $write("dm_addr_dmcontrol");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h11) $write("dm_addr_dmstatus");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h12) $write("dm_addr_hartinfo");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h13) $write("dm_addr_haltsum");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h14) $write("dm_addr_hawindowsel");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h15) $write("dm_addr_hawindow");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h19) $write("dm_addr_devtreeaddr0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h30) $write("dm_addr_authdata");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h40) $write("dm_addr_haltregion0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h5F) $write("dm_addr_haltregion31");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h60) $write("dm_addr_verbosity");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h16) $write("dm_addr_abstractcs");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h17) $write("dm_addr_command");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h04) $write("dm_addr_data0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h05) $write("dm_addr_data1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h06) $write("dm_addr_data2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h07) $write("dm_addr_data3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h08) $write("dm_addr_data4");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h09) $write("dm_addr_data5");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0A) $write("dm_addr_data6");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0B) $write("dm_addr_data7");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0C) $write("dm_addr_data8");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0D) $write("dm_addr_data9");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h0F) $write("dm_addr_data11");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h18) $write("dm_addr_abstractauto");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h20) $write("dm_addr_progbuf0");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3B) $write("dm_addr_sbaddress2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3D) $write("dm_addr_sbdata1");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3E) $write("dm_addr_sbdata2");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr == 7'h3F) $write("dm_addr_sbdata3");
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C &&
write_dm_addr != 7'h10 &&
write_dm_addr != 7'h11 &&
write_dm_addr != 7'h12 &&
write_dm_addr != 7'h13 &&
write_dm_addr != 7'h14 &&
write_dm_addr != 7'h15 &&
write_dm_addr != 7'h19 &&
write_dm_addr != 7'h30 &&
write_dm_addr != 7'h40 &&
write_dm_addr != 7'h5F &&
write_dm_addr != 7'h60 &&
write_dm_addr != 7'h16 &&
write_dm_addr != 7'h17 &&
write_dm_addr != 7'h04 &&
write_dm_addr != 7'h05 &&
write_dm_addr != 7'h06 &&
write_dm_addr != 7'h07 &&
write_dm_addr != 7'h08 &&
write_dm_addr != 7'h09 &&
write_dm_addr != 7'h0A &&
write_dm_addr != 7'h0B &&
write_dm_addr != 7'h0C &&
write_dm_addr != 7'h0D &&
write_dm_addr != 7'h0F &&
write_dm_addr != 7'h18 &&
write_dm_addr != 7'h20 &&
write_dm_addr != 7'h3B &&
write_dm_addr != 7'h3D &&
write_dm_addr != 7'h3E &&
write_dm_addr != 7'h3F)
$write("<Unknown dm_abstract_command dm_addr 0x%0h>", write_dm_addr);
if (RST_N != `BSV_RESET_VALUE)
if (EN_write && write_dm_addr != 7'h38 && write_dm_addr != 7'h39 &&
write_dm_addr != 7'h3A &&
write_dm_addr != 7'h3C)
$write("] <= 0x%08h; addr not supported", write_dm_word, "\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$display("DM_System_Bus.rule_sb_read_finish: setting rg_sbcs_sberror to DM_SBERROR_OTHER\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(" rdr = ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_sb_read_finish &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0)
$write("\n");
end
// synopsys translate_on
endmodule // mkDM_System_Bus
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