759 lines
23 KiB
Verilog
759 lines
23 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1
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// first_data O 36
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// RDY_first_data O 1
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// first_poisoned O 1
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// RDY_first_poisoned O 1
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// RDY_specUpdate_incorrectSpeculation O 1 const
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// RDY_specUpdate_correctSpeculation O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// enq_x I 36
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// specUpdate_incorrectSpeculation_kill_all I 1
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// specUpdate_incorrectSpeculation_kill_tag I 4
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// specUpdate_correctSpeculation_mask I 12
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// EN_enq I 1
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// EN_deq I 1
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// EN_specUpdate_incorrectSpeculation I 1
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// EN_specUpdate_correctSpeculation I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkDivExecQ(CLK,
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RST_N,
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enq_x,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first_data,
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RDY_first_data,
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first_poisoned,
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RDY_first_poisoned,
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specUpdate_incorrectSpeculation_kill_all,
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specUpdate_incorrectSpeculation_kill_tag,
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EN_specUpdate_incorrectSpeculation,
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RDY_specUpdate_incorrectSpeculation,
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specUpdate_correctSpeculation_mask,
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EN_specUpdate_correctSpeculation,
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RDY_specUpdate_correctSpeculation);
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input CLK;
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input RST_N;
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// action method enq
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input [35 : 0] enq_x;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first_data
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output [35 : 0] first_data;
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output RDY_first_data;
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// value method first_poisoned
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output first_poisoned;
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output RDY_first_poisoned;
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// action method specUpdate_incorrectSpeculation
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input specUpdate_incorrectSpeculation_kill_all;
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input [3 : 0] specUpdate_incorrectSpeculation_kill_tag;
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input EN_specUpdate_incorrectSpeculation;
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output RDY_specUpdate_incorrectSpeculation;
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// action method specUpdate_correctSpeculation
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input [11 : 0] specUpdate_correctSpeculation_mask;
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input EN_specUpdate_correctSpeculation;
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output RDY_specUpdate_correctSpeculation;
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// signals for module outputs
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reg RDY_deq, first_poisoned;
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wire [35 : 0] first_data;
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wire RDY_enq,
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RDY_first_data,
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RDY_first_poisoned,
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RDY_specUpdate_correctSpeculation,
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RDY_specUpdate_incorrectSpeculation;
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// inlined wires
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reg m_valid_for_enq_wire$wget;
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wire [11 : 0] m_specBits_0_lat_1$wget, m_specBits_1_lat_1$wget;
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wire m_poisoned_0_lat_0$whas,
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m_poisoned_1_lat_0$whas,
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m_valid_0_lat_0$whas,
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m_valid_0_lat_1$whas,
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m_valid_1_lat_0$whas,
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m_valid_1_lat_1$whas;
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// register m_deqP
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reg m_deqP;
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wire m_deqP$D_IN, m_deqP$EN;
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// register m_enqP
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reg m_enqP;
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wire m_enqP$D_IN, m_enqP$EN;
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// register m_poisoned_0_rl
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reg m_poisoned_0_rl;
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wire m_poisoned_0_rl$D_IN, m_poisoned_0_rl$EN;
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// register m_poisoned_1_rl
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reg m_poisoned_1_rl;
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wire m_poisoned_1_rl$D_IN, m_poisoned_1_rl$EN;
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// register m_row_0
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reg [23 : 0] m_row_0;
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wire [23 : 0] m_row_0$D_IN;
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wire m_row_0$EN;
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// register m_row_1
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reg [23 : 0] m_row_1;
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wire [23 : 0] m_row_1$D_IN;
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wire m_row_1$EN;
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// register m_specBits_0_rl
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reg [11 : 0] m_specBits_0_rl;
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wire [11 : 0] m_specBits_0_rl$D_IN;
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wire m_specBits_0_rl$EN;
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// register m_specBits_1_rl
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reg [11 : 0] m_specBits_1_rl;
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wire [11 : 0] m_specBits_1_rl$D_IN;
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wire m_specBits_1_rl$EN;
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// register m_valid_0_rl
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reg m_valid_0_rl;
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wire m_valid_0_rl$D_IN, m_valid_0_rl$EN;
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// register m_valid_1_rl
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reg m_valid_1_rl;
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wire m_valid_1_rl$D_IN, m_valid_1_rl$EN;
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// ports of submodule m_poisoned_0_dummy2_0
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wire m_poisoned_0_dummy2_0$D_IN,
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m_poisoned_0_dummy2_0$EN,
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m_poisoned_0_dummy2_0$Q_OUT;
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// ports of submodule m_poisoned_0_dummy2_1
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wire m_poisoned_0_dummy2_1$D_IN,
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m_poisoned_0_dummy2_1$EN,
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m_poisoned_0_dummy2_1$Q_OUT;
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// ports of submodule m_poisoned_1_dummy2_0
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wire m_poisoned_1_dummy2_0$D_IN,
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m_poisoned_1_dummy2_0$EN,
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m_poisoned_1_dummy2_0$Q_OUT;
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// ports of submodule m_poisoned_1_dummy2_1
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wire m_poisoned_1_dummy2_1$D_IN,
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m_poisoned_1_dummy2_1$EN,
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m_poisoned_1_dummy2_1$Q_OUT;
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// ports of submodule m_specBits_0_dummy2_0
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wire m_specBits_0_dummy2_0$D_IN,
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m_specBits_0_dummy2_0$EN,
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m_specBits_0_dummy2_0$Q_OUT;
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// ports of submodule m_specBits_0_dummy2_1
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wire m_specBits_0_dummy2_1$D_IN,
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m_specBits_0_dummy2_1$EN,
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m_specBits_0_dummy2_1$Q_OUT;
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// ports of submodule m_specBits_1_dummy2_0
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wire m_specBits_1_dummy2_0$D_IN,
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m_specBits_1_dummy2_0$EN,
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m_specBits_1_dummy2_0$Q_OUT;
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// ports of submodule m_specBits_1_dummy2_1
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wire m_specBits_1_dummy2_1$D_IN,
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m_specBits_1_dummy2_1$EN,
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m_specBits_1_dummy2_1$Q_OUT;
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// ports of submodule m_valid_0_dummy2_0
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wire m_valid_0_dummy2_0$D_IN,
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m_valid_0_dummy2_0$EN,
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m_valid_0_dummy2_0$Q_OUT;
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// ports of submodule m_valid_0_dummy2_1
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wire m_valid_0_dummy2_1$D_IN,
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m_valid_0_dummy2_1$EN,
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m_valid_0_dummy2_1$Q_OUT;
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// ports of submodule m_valid_1_dummy2_0
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wire m_valid_1_dummy2_0$D_IN,
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m_valid_1_dummy2_0$EN,
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m_valid_1_dummy2_0$Q_OUT;
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// ports of submodule m_valid_1_dummy2_1
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wire m_valid_1_dummy2_1$D_IN,
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m_valid_1_dummy2_1$EN,
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m_valid_1_dummy2_1$Q_OUT;
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// rule scheduling signals
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wire CAN_FIRE_RL_m_poisoned_0_canon,
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CAN_FIRE_RL_m_poisoned_1_canon,
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CAN_FIRE_RL_m_setEnqWire,
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CAN_FIRE_RL_m_specBits_0_canon,
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CAN_FIRE_RL_m_specBits_1_canon,
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CAN_FIRE_RL_m_valid_0_canon,
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CAN_FIRE_RL_m_valid_1_canon,
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CAN_FIRE_deq,
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CAN_FIRE_enq,
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CAN_FIRE_specUpdate_correctSpeculation,
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CAN_FIRE_specUpdate_incorrectSpeculation,
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WILL_FIRE_RL_m_poisoned_0_canon,
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WILL_FIRE_RL_m_poisoned_1_canon,
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WILL_FIRE_RL_m_setEnqWire,
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WILL_FIRE_RL_m_specBits_0_canon,
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WILL_FIRE_RL_m_specBits_1_canon,
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WILL_FIRE_RL_m_valid_0_canon,
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WILL_FIRE_RL_m_valid_1_canon,
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WILL_FIRE_deq,
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WILL_FIRE_enq,
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WILL_FIRE_specUpdate_correctSpeculation,
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WILL_FIRE_specUpdate_incorrectSpeculation;
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// remaining internal signals
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reg [11 : 0] CASE_m_deqP_0_bs0352_1_bs0584_DONTCARE__q9;
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reg [6 : 0] CASE_m_deqP_0_m_row_0_BITS_19_TO_13_1_m_row_1__ETC__q5;
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reg [5 : 0] CASE_m_deqP_0_m_row_0_BITS_5_TO_0_1_m_row_1_BI_ETC__q3;
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reg [4 : 0] CASE_m_deqP_0_m_row_0_BITS_10_TO_6_1_m_row_1_B_ETC__q2;
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reg [1 : 0] CASE_m_deqP_0_m_row_0_BITS_23_TO_22_1_m_row_1__ETC__q8;
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reg CASE_m_deqP_0_NOT_m_row_0_BIT_20_1_NOT_m_row_1_ETC__q4,
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CASE_m_deqP_0_m_row_0_BIT_11_1_m_row_1_BIT_11__ETC__q1,
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CASE_m_deqP_0_m_row_0_BIT_12_1_m_row_1_BIT_12__ETC__q6,
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CASE_m_deqP_0_m_row_0_BIT_21_1_m_row_1_BIT_21__ETC__q7;
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wire [21 : 0] SEL_ARR_m_row_0_5_BIT_21_1_m_row_1_7_BIT_21_2__ETC___d116;
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wire [11 : 0] IF_m_specBits_0_lat_0_whas__1_THEN_m_specBits__ETC___d34,
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IF_m_specBits_1_lat_0_whas__8_THEN_m_specBits__ETC___d41,
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SEL_ARR_m_row_0_5_BIT_11_03_m_row_1_7_BIT_11_0_ETC___d115,
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bs__h10352,
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bs__h10584,
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n__read__h10874,
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n__read__h11315,
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upd__h5443,
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upd__h6372;
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wire [8 : 0] NOT_SEL_ARR_NOT_m_row_0_5_BIT_20_5_6_NOT_m_row_ETC___d102;
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// action method enq
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assign RDY_enq = !m_valid_for_enq_wire$wget ;
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assign CAN_FIRE_enq = !m_valid_for_enq_wire$wget ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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always@(m_deqP or
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m_valid_0_dummy2_0$Q_OUT or
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m_valid_0_dummy2_1$Q_OUT or
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m_valid_0_rl or
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m_valid_1_dummy2_0$Q_OUT or
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m_valid_1_dummy2_1$Q_OUT or m_valid_1_rl)
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begin
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case (m_deqP)
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1'd0:
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RDY_deq =
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m_valid_0_dummy2_0$Q_OUT && m_valid_0_dummy2_1$Q_OUT &&
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m_valid_0_rl;
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1'd1:
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RDY_deq =
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m_valid_1_dummy2_0$Q_OUT && m_valid_1_dummy2_1$Q_OUT &&
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m_valid_1_rl;
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endcase
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end
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assign CAN_FIRE_deq = RDY_deq ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first_data
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assign first_data =
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{ CASE_m_deqP_0_m_row_0_BITS_23_TO_22_1_m_row_1__ETC__q8,
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SEL_ARR_m_row_0_5_BIT_21_1_m_row_1_7_BIT_21_2__ETC___d116,
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CASE_m_deqP_0_bs0352_1_bs0584_DONTCARE__q9 } ;
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assign RDY_first_data = RDY_deq ;
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// value method first_poisoned
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always@(m_deqP or
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m_poisoned_0_dummy2_0$Q_OUT or
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m_poisoned_0_dummy2_1$Q_OUT or
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m_poisoned_0_rl or
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m_poisoned_1_dummy2_0$Q_OUT or
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m_poisoned_1_dummy2_1$Q_OUT or m_poisoned_1_rl)
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begin
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case (m_deqP)
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1'd0:
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first_poisoned =
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m_poisoned_0_dummy2_0$Q_OUT && m_poisoned_0_dummy2_1$Q_OUT &&
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m_poisoned_0_rl;
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1'd1:
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first_poisoned =
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m_poisoned_1_dummy2_0$Q_OUT && m_poisoned_1_dummy2_1$Q_OUT &&
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m_poisoned_1_rl;
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endcase
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end
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assign RDY_first_poisoned = RDY_deq ;
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// action method specUpdate_incorrectSpeculation
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assign RDY_specUpdate_incorrectSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_incorrectSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_incorrectSpeculation =
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EN_specUpdate_incorrectSpeculation ;
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// action method specUpdate_correctSpeculation
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assign RDY_specUpdate_correctSpeculation = 1'd1 ;
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assign CAN_FIRE_specUpdate_correctSpeculation = 1'd1 ;
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assign WILL_FIRE_specUpdate_correctSpeculation =
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EN_specUpdate_correctSpeculation ;
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// submodule m_poisoned_0_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_poisoned_0_dummy2_0(.CLK(CLK),
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.D_IN(m_poisoned_0_dummy2_0$D_IN),
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.EN(m_poisoned_0_dummy2_0$EN),
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.Q_OUT(m_poisoned_0_dummy2_0$Q_OUT));
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// submodule m_poisoned_0_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_poisoned_0_dummy2_1(.CLK(CLK),
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.D_IN(m_poisoned_0_dummy2_1$D_IN),
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.EN(m_poisoned_0_dummy2_1$EN),
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.Q_OUT(m_poisoned_0_dummy2_1$Q_OUT));
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// submodule m_poisoned_1_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_poisoned_1_dummy2_0(.CLK(CLK),
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.D_IN(m_poisoned_1_dummy2_0$D_IN),
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.EN(m_poisoned_1_dummy2_0$EN),
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.Q_OUT(m_poisoned_1_dummy2_0$Q_OUT));
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// submodule m_poisoned_1_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_poisoned_1_dummy2_1(.CLK(CLK),
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.D_IN(m_poisoned_1_dummy2_1$D_IN),
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.EN(m_poisoned_1_dummy2_1$EN),
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.Q_OUT(m_poisoned_1_dummy2_1$Q_OUT));
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// submodule m_specBits_0_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_specBits_0_dummy2_0(.CLK(CLK),
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.D_IN(m_specBits_0_dummy2_0$D_IN),
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.EN(m_specBits_0_dummy2_0$EN),
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.Q_OUT(m_specBits_0_dummy2_0$Q_OUT));
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// submodule m_specBits_0_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_specBits_0_dummy2_1(.CLK(CLK),
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.D_IN(m_specBits_0_dummy2_1$D_IN),
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.EN(m_specBits_0_dummy2_1$EN),
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.Q_OUT(m_specBits_0_dummy2_1$Q_OUT));
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// submodule m_specBits_1_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_specBits_1_dummy2_0(.CLK(CLK),
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.D_IN(m_specBits_1_dummy2_0$D_IN),
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.EN(m_specBits_1_dummy2_0$EN),
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.Q_OUT(m_specBits_1_dummy2_0$Q_OUT));
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// submodule m_specBits_1_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_specBits_1_dummy2_1(.CLK(CLK),
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.D_IN(m_specBits_1_dummy2_1$D_IN),
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.EN(m_specBits_1_dummy2_1$EN),
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.Q_OUT(m_specBits_1_dummy2_1$Q_OUT));
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// submodule m_valid_0_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_valid_0_dummy2_0(.CLK(CLK),
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.D_IN(m_valid_0_dummy2_0$D_IN),
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.EN(m_valid_0_dummy2_0$EN),
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.Q_OUT(m_valid_0_dummy2_0$Q_OUT));
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// submodule m_valid_0_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_valid_0_dummy2_1(.CLK(CLK),
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.D_IN(m_valid_0_dummy2_1$D_IN),
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.EN(m_valid_0_dummy2_1$EN),
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.Q_OUT(m_valid_0_dummy2_1$Q_OUT));
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// submodule m_valid_1_dummy2_0
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RevertReg #(.width(32'd1), .init(1'd1)) m_valid_1_dummy2_0(.CLK(CLK),
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.D_IN(m_valid_1_dummy2_0$D_IN),
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.EN(m_valid_1_dummy2_0$EN),
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.Q_OUT(m_valid_1_dummy2_0$Q_OUT));
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// submodule m_valid_1_dummy2_1
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RevertReg #(.width(32'd1), .init(1'd1)) m_valid_1_dummy2_1(.CLK(CLK),
|
|
.D_IN(m_valid_1_dummy2_1$D_IN),
|
|
.EN(m_valid_1_dummy2_1$EN),
|
|
.Q_OUT(m_valid_1_dummy2_1$Q_OUT));
|
|
|
|
// rule RL_m_setEnqWire
|
|
assign CAN_FIRE_RL_m_setEnqWire = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_setEnqWire = 1'd1 ;
|
|
|
|
// rule RL_m_valid_0_canon
|
|
assign CAN_FIRE_RL_m_valid_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_valid_1_canon
|
|
assign CAN_FIRE_RL_m_valid_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_valid_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_poisoned_0_canon
|
|
assign CAN_FIRE_RL_m_poisoned_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_poisoned_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_poisoned_1_canon
|
|
assign CAN_FIRE_RL_m_poisoned_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_poisoned_1_canon = 1'd1 ;
|
|
|
|
// rule RL_m_specBits_0_canon
|
|
assign CAN_FIRE_RL_m_specBits_0_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_specBits_0_canon = 1'd1 ;
|
|
|
|
// rule RL_m_specBits_1_canon
|
|
assign CAN_FIRE_RL_m_specBits_1_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_m_specBits_1_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign m_valid_0_lat_0$whas = EN_deq && m_deqP == 1'd0 ;
|
|
assign m_valid_0_lat_1$whas = EN_enq && m_enqP == 1'd0 ;
|
|
assign m_valid_1_lat_0$whas = EN_deq && m_deqP == 1'd1 ;
|
|
assign m_valid_1_lat_1$whas = EN_enq && m_enqP == 1'd1 ;
|
|
assign m_poisoned_0_lat_0$whas =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
bs__h10352[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign m_poisoned_1_lat_0$whas =
|
|
EN_specUpdate_incorrectSpeculation &&
|
|
(specUpdate_incorrectSpeculation_kill_all ||
|
|
bs__h10584[specUpdate_incorrectSpeculation_kill_tag]) ;
|
|
assign m_specBits_0_lat_1$wget =
|
|
n__read__h10874 & specUpdate_correctSpeculation_mask ;
|
|
assign m_specBits_1_lat_1$wget =
|
|
n__read__h11315 & specUpdate_correctSpeculation_mask ;
|
|
always@(m_enqP or
|
|
m_valid_0_dummy2_0$Q_OUT or
|
|
m_valid_0_dummy2_1$Q_OUT or
|
|
m_valid_0_rl or
|
|
m_valid_1_dummy2_0$Q_OUT or
|
|
m_valid_1_dummy2_1$Q_OUT or m_valid_1_rl)
|
|
begin
|
|
case (m_enqP)
|
|
1'd0:
|
|
m_valid_for_enq_wire$wget =
|
|
m_valid_0_dummy2_0$Q_OUT && m_valid_0_dummy2_1$Q_OUT &&
|
|
m_valid_0_rl;
|
|
1'd1:
|
|
m_valid_for_enq_wire$wget =
|
|
m_valid_1_dummy2_0$Q_OUT && m_valid_1_dummy2_1$Q_OUT &&
|
|
m_valid_1_rl;
|
|
endcase
|
|
end
|
|
|
|
// register m_deqP
|
|
assign m_deqP$D_IN = m_deqP + 1'd1 ;
|
|
assign m_deqP$EN = EN_deq ;
|
|
|
|
// register m_enqP
|
|
assign m_enqP$D_IN = m_enqP + 1'd1 ;
|
|
assign m_enqP$EN = EN_enq ;
|
|
|
|
// register m_poisoned_0_rl
|
|
assign m_poisoned_0_rl$D_IN =
|
|
!m_valid_0_lat_1$whas &&
|
|
(m_poisoned_0_lat_0$whas || m_poisoned_0_rl) ;
|
|
assign m_poisoned_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_poisoned_1_rl
|
|
assign m_poisoned_1_rl$D_IN =
|
|
!m_valid_1_lat_1$whas &&
|
|
(m_poisoned_1_lat_0$whas || m_poisoned_1_rl) ;
|
|
assign m_poisoned_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_row_0
|
|
assign m_row_0$D_IN = enq_x[35:12] ;
|
|
assign m_row_0$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// register m_row_1
|
|
assign m_row_1$D_IN = enq_x[35:12] ;
|
|
assign m_row_1$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// register m_specBits_0_rl
|
|
assign m_specBits_0_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h5443 :
|
|
IF_m_specBits_0_lat_0_whas__1_THEN_m_specBits__ETC___d34 ;
|
|
assign m_specBits_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_specBits_1_rl
|
|
assign m_specBits_1_rl$D_IN =
|
|
EN_specUpdate_correctSpeculation ?
|
|
upd__h6372 :
|
|
IF_m_specBits_1_lat_0_whas__8_THEN_m_specBits__ETC___d41 ;
|
|
assign m_specBits_1_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_0_rl
|
|
assign m_valid_0_rl$D_IN =
|
|
m_valid_0_lat_1$whas || !m_valid_0_lat_0$whas && m_valid_0_rl ;
|
|
assign m_valid_0_rl$EN = 1'd1 ;
|
|
|
|
// register m_valid_1_rl
|
|
assign m_valid_1_rl$D_IN =
|
|
m_valid_1_lat_1$whas || !m_valid_1_lat_0$whas && m_valid_1_rl ;
|
|
assign m_valid_1_rl$EN = 1'd1 ;
|
|
|
|
// submodule m_poisoned_0_dummy2_0
|
|
assign m_poisoned_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_poisoned_0_dummy2_0$EN = m_poisoned_0_lat_0$whas ;
|
|
|
|
// submodule m_poisoned_0_dummy2_1
|
|
assign m_poisoned_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_poisoned_0_dummy2_1$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// submodule m_poisoned_1_dummy2_0
|
|
assign m_poisoned_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_poisoned_1_dummy2_0$EN = m_poisoned_1_lat_0$whas ;
|
|
|
|
// submodule m_poisoned_1_dummy2_1
|
|
assign m_poisoned_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_poisoned_1_dummy2_1$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// submodule m_specBits_0_dummy2_0
|
|
assign m_specBits_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_specBits_0_dummy2_0$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// submodule m_specBits_0_dummy2_1
|
|
assign m_specBits_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_specBits_0_dummy2_1$EN = EN_specUpdate_correctSpeculation ;
|
|
|
|
// submodule m_specBits_1_dummy2_0
|
|
assign m_specBits_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_specBits_1_dummy2_0$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// submodule m_specBits_1_dummy2_1
|
|
assign m_specBits_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_specBits_1_dummy2_1$EN = EN_specUpdate_correctSpeculation ;
|
|
|
|
// submodule m_valid_0_dummy2_0
|
|
assign m_valid_0_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_valid_0_dummy2_0$EN = m_valid_0_lat_0$whas ;
|
|
|
|
// submodule m_valid_0_dummy2_1
|
|
assign m_valid_0_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_valid_0_dummy2_1$EN = m_valid_0_lat_1$whas ;
|
|
|
|
// submodule m_valid_1_dummy2_0
|
|
assign m_valid_1_dummy2_0$D_IN = 1'd1 ;
|
|
assign m_valid_1_dummy2_0$EN = m_valid_1_lat_0$whas ;
|
|
|
|
// submodule m_valid_1_dummy2_1
|
|
assign m_valid_1_dummy2_1$D_IN = 1'd1 ;
|
|
assign m_valid_1_dummy2_1$EN = m_valid_1_lat_1$whas ;
|
|
|
|
// remaining internal signals
|
|
assign IF_m_specBits_0_lat_0_whas__1_THEN_m_specBits__ETC___d34 =
|
|
m_valid_0_lat_1$whas ? enq_x[11:0] : m_specBits_0_rl ;
|
|
assign IF_m_specBits_1_lat_0_whas__8_THEN_m_specBits__ETC___d41 =
|
|
m_valid_1_lat_1$whas ? enq_x[11:0] : m_specBits_1_rl ;
|
|
assign NOT_SEL_ARR_NOT_m_row_0_5_BIT_20_5_6_NOT_m_row_ETC___d102 =
|
|
{ !CASE_m_deqP_0_NOT_m_row_0_BIT_20_1_NOT_m_row_1_ETC__q4,
|
|
CASE_m_deqP_0_m_row_0_BITS_19_TO_13_1_m_row_1__ETC__q5,
|
|
CASE_m_deqP_0_m_row_0_BIT_12_1_m_row_1_BIT_12__ETC__q6 } ;
|
|
assign SEL_ARR_m_row_0_5_BIT_11_03_m_row_1_7_BIT_11_0_ETC___d115 =
|
|
{ CASE_m_deqP_0_m_row_0_BIT_11_1_m_row_1_BIT_11__ETC__q1,
|
|
CASE_m_deqP_0_m_row_0_BITS_10_TO_6_1_m_row_1_B_ETC__q2,
|
|
CASE_m_deqP_0_m_row_0_BITS_5_TO_0_1_m_row_1_BI_ETC__q3 } ;
|
|
assign SEL_ARR_m_row_0_5_BIT_21_1_m_row_1_7_BIT_21_2__ETC___d116 =
|
|
{ CASE_m_deqP_0_m_row_0_BIT_21_1_m_row_1_BIT_21__ETC__q7,
|
|
NOT_SEL_ARR_NOT_m_row_0_5_BIT_20_5_6_NOT_m_row_ETC___d102,
|
|
SEL_ARR_m_row_0_5_BIT_11_03_m_row_1_7_BIT_11_0_ETC___d115 } ;
|
|
assign bs__h10352 =
|
|
(m_specBits_0_dummy2_0$Q_OUT && m_specBits_0_dummy2_1$Q_OUT) ?
|
|
m_specBits_0_rl :
|
|
12'd0 ;
|
|
assign bs__h10584 =
|
|
(m_specBits_1_dummy2_0$Q_OUT && m_specBits_1_dummy2_1$Q_OUT) ?
|
|
m_specBits_1_rl :
|
|
12'd0 ;
|
|
assign n__read__h10874 =
|
|
m_specBits_0_dummy2_1$Q_OUT ?
|
|
IF_m_specBits_0_lat_0_whas__1_THEN_m_specBits__ETC___d34 :
|
|
12'd0 ;
|
|
assign n__read__h11315 =
|
|
m_specBits_1_dummy2_1$Q_OUT ?
|
|
IF_m_specBits_1_lat_0_whas__8_THEN_m_specBits__ETC___d41 :
|
|
12'd0 ;
|
|
assign upd__h5443 = m_specBits_0_lat_1$wget ;
|
|
assign upd__h6372 = m_specBits_1_lat_1$wget ;
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_m_row_0_BIT_11_1_m_row_1_BIT_11__ETC__q1 =
|
|
m_row_0[11];
|
|
1'd1:
|
|
CASE_m_deqP_0_m_row_0_BIT_11_1_m_row_1_BIT_11__ETC__q1 =
|
|
m_row_1[11];
|
|
endcase
|
|
end
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_m_row_0_BITS_10_TO_6_1_m_row_1_B_ETC__q2 =
|
|
m_row_0[10:6];
|
|
1'd1:
|
|
CASE_m_deqP_0_m_row_0_BITS_10_TO_6_1_m_row_1_B_ETC__q2 =
|
|
m_row_1[10:6];
|
|
endcase
|
|
end
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_m_row_0_BITS_5_TO_0_1_m_row_1_BI_ETC__q3 =
|
|
m_row_0[5:0];
|
|
1'd1:
|
|
CASE_m_deqP_0_m_row_0_BITS_5_TO_0_1_m_row_1_BI_ETC__q3 =
|
|
m_row_1[5:0];
|
|
endcase
|
|
end
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_NOT_m_row_0_BIT_20_1_NOT_m_row_1_ETC__q4 =
|
|
!m_row_0[20];
|
|
1'd1:
|
|
CASE_m_deqP_0_NOT_m_row_0_BIT_20_1_NOT_m_row_1_ETC__q4 =
|
|
!m_row_1[20];
|
|
endcase
|
|
end
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_m_row_0_BITS_19_TO_13_1_m_row_1__ETC__q5 =
|
|
m_row_0[19:13];
|
|
1'd1:
|
|
CASE_m_deqP_0_m_row_0_BITS_19_TO_13_1_m_row_1__ETC__q5 =
|
|
m_row_1[19:13];
|
|
endcase
|
|
end
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_m_row_0_BIT_12_1_m_row_1_BIT_12__ETC__q6 =
|
|
m_row_0[12];
|
|
1'd1:
|
|
CASE_m_deqP_0_m_row_0_BIT_12_1_m_row_1_BIT_12__ETC__q6 =
|
|
m_row_1[12];
|
|
endcase
|
|
end
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_m_row_0_BIT_21_1_m_row_1_BIT_21__ETC__q7 =
|
|
m_row_0[21];
|
|
1'd1:
|
|
CASE_m_deqP_0_m_row_0_BIT_21_1_m_row_1_BIT_21__ETC__q7 =
|
|
m_row_1[21];
|
|
endcase
|
|
end
|
|
always@(m_deqP or m_row_0 or m_row_1)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0:
|
|
CASE_m_deqP_0_m_row_0_BITS_23_TO_22_1_m_row_1__ETC__q8 =
|
|
m_row_0[23:22];
|
|
1'd1:
|
|
CASE_m_deqP_0_m_row_0_BITS_23_TO_22_1_m_row_1__ETC__q8 =
|
|
m_row_1[23:22];
|
|
endcase
|
|
end
|
|
always@(m_deqP or bs__h10352 or bs__h10584)
|
|
begin
|
|
case (m_deqP)
|
|
1'd0: CASE_m_deqP_0_bs0352_1_bs0584_DONTCARE__q9 = bs__h10352;
|
|
1'd1: CASE_m_deqP_0_bs0352_1_bs0584_DONTCARE__q9 = bs__h10584;
|
|
endcase
|
|
end
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
m_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_poisoned_0_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
|
|
m_poisoned_1_rl <= `BSV_ASSIGNMENT_DELAY 1'h0;
|
|
m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY 12'hAAA;
|
|
m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (m_deqP$EN) m_deqP <= `BSV_ASSIGNMENT_DELAY m_deqP$D_IN;
|
|
if (m_enqP$EN) m_enqP <= `BSV_ASSIGNMENT_DELAY m_enqP$D_IN;
|
|
if (m_poisoned_0_rl$EN)
|
|
m_poisoned_0_rl <= `BSV_ASSIGNMENT_DELAY m_poisoned_0_rl$D_IN;
|
|
if (m_poisoned_1_rl$EN)
|
|
m_poisoned_1_rl <= `BSV_ASSIGNMENT_DELAY m_poisoned_1_rl$D_IN;
|
|
if (m_specBits_0_rl$EN)
|
|
m_specBits_0_rl <= `BSV_ASSIGNMENT_DELAY m_specBits_0_rl$D_IN;
|
|
if (m_specBits_1_rl$EN)
|
|
m_specBits_1_rl <= `BSV_ASSIGNMENT_DELAY m_specBits_1_rl$D_IN;
|
|
if (m_valid_0_rl$EN)
|
|
m_valid_0_rl <= `BSV_ASSIGNMENT_DELAY m_valid_0_rl$D_IN;
|
|
if (m_valid_1_rl$EN)
|
|
m_valid_1_rl <= `BSV_ASSIGNMENT_DELAY m_valid_1_rl$D_IN;
|
|
end
|
|
if (m_row_0$EN) m_row_0 <= `BSV_ASSIGNMENT_DELAY m_row_0$D_IN;
|
|
if (m_row_1$EN) m_row_1 <= `BSV_ASSIGNMENT_DELAY m_row_1$D_IN;
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
m_deqP = 1'h0;
|
|
m_enqP = 1'h0;
|
|
m_poisoned_0_rl = 1'h0;
|
|
m_poisoned_1_rl = 1'h0;
|
|
m_row_0 = 24'hAAAAAA;
|
|
m_row_1 = 24'hAAAAAA;
|
|
m_specBits_0_rl = 12'hAAA;
|
|
m_specBits_1_rl = 12'hAAA;
|
|
m_valid_0_rl = 1'h0;
|
|
m_valid_1_rl = 1'h0;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkDivExecQ
|
|
|