1050 lines
34 KiB
Verilog
1050 lines
34 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// getFetchTarget O 2
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// RDY_getFetchTarget O 1 const
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// RDY_bootRomReq O 1
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// bootRomResp O 66 reg
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// RDY_bootRomResp O 1
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// toCore_instReq_notEmpty O 1
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// RDY_toCore_instReq_notEmpty O 1 const
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// RDY_toCore_instReq_deq O 1
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// toCore_instReq_first_fst O 64 reg
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// RDY_toCore_instReq_first_fst O 1
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// toCore_instReq_first_snd O 1 reg
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// RDY_toCore_instReq_first_snd O 1
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// toCore_instResp_notFull O 1
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// RDY_toCore_instResp_notFull O 1 const
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// RDY_toCore_instResp_enq O 1
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// RDY_toCore_setHtifAddrs O 1 const
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// CLK I 1 clock
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// RST_N I 1 reset
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// getFetchTarget_phyPc I 64
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// bootRomReq_phyPc I 64
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// bootRomReq_maxWay I 1
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// toCore_instResp_enq_x I 66
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// toCore_setHtifAddrs_toHost I 64 reg
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// toCore_setHtifAddrs_fromHost I 64 reg
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// EN_bootRomReq I 1
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// EN_toCore_instReq_deq I 1
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// EN_toCore_instResp_enq I 1
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// EN_toCore_setHtifAddrs I 1
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// EN_bootRomResp I 1
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//
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// Combinational paths from inputs to outputs:
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// getFetchTarget_phyPc -> getFetchTarget
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkMMIOInst(CLK,
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RST_N,
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getFetchTarget_phyPc,
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getFetchTarget,
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RDY_getFetchTarget,
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bootRomReq_phyPc,
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bootRomReq_maxWay,
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EN_bootRomReq,
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RDY_bootRomReq,
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EN_bootRomResp,
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bootRomResp,
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RDY_bootRomResp,
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toCore_instReq_notEmpty,
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RDY_toCore_instReq_notEmpty,
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EN_toCore_instReq_deq,
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RDY_toCore_instReq_deq,
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toCore_instReq_first_fst,
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RDY_toCore_instReq_first_fst,
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toCore_instReq_first_snd,
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RDY_toCore_instReq_first_snd,
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toCore_instResp_notFull,
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RDY_toCore_instResp_notFull,
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toCore_instResp_enq_x,
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EN_toCore_instResp_enq,
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RDY_toCore_instResp_enq,
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toCore_setHtifAddrs_toHost,
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toCore_setHtifAddrs_fromHost,
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EN_toCore_setHtifAddrs,
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RDY_toCore_setHtifAddrs);
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input CLK;
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input RST_N;
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// value method getFetchTarget
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input [63 : 0] getFetchTarget_phyPc;
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output [1 : 0] getFetchTarget;
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output RDY_getFetchTarget;
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// action method bootRomReq
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input [63 : 0] bootRomReq_phyPc;
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input bootRomReq_maxWay;
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input EN_bootRomReq;
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output RDY_bootRomReq;
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// actionvalue method bootRomResp
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input EN_bootRomResp;
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output [65 : 0] bootRomResp;
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output RDY_bootRomResp;
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// value method toCore_instReq_notEmpty
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output toCore_instReq_notEmpty;
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output RDY_toCore_instReq_notEmpty;
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// action method toCore_instReq_deq
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input EN_toCore_instReq_deq;
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output RDY_toCore_instReq_deq;
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// value method toCore_instReq_first_fst
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output [63 : 0] toCore_instReq_first_fst;
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output RDY_toCore_instReq_first_fst;
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// value method toCore_instReq_first_snd
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output toCore_instReq_first_snd;
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output RDY_toCore_instReq_first_snd;
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// value method toCore_instResp_notFull
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output toCore_instResp_notFull;
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output RDY_toCore_instResp_notFull;
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// action method toCore_instResp_enq
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input [65 : 0] toCore_instResp_enq_x;
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input EN_toCore_instResp_enq;
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output RDY_toCore_instResp_enq;
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// action method toCore_setHtifAddrs
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input [63 : 0] toCore_setHtifAddrs_toHost;
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input [63 : 0] toCore_setHtifAddrs_fromHost;
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input EN_toCore_setHtifAddrs;
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output RDY_toCore_setHtifAddrs;
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// signals for module outputs
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wire [65 : 0] bootRomResp;
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wire [63 : 0] toCore_instReq_first_fst;
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wire [1 : 0] getFetchTarget;
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wire RDY_bootRomReq,
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RDY_bootRomResp,
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RDY_getFetchTarget,
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RDY_toCore_instReq_deq,
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RDY_toCore_instReq_first_fst,
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RDY_toCore_instReq_first_snd,
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RDY_toCore_instReq_notEmpty,
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RDY_toCore_instResp_enq,
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RDY_toCore_instResp_notFull,
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RDY_toCore_setHtifAddrs,
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toCore_instReq_first_snd,
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toCore_instReq_notEmpty,
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toCore_instResp_notFull;
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// inlined wires
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wire [66 : 0] respQ_enqReq_lat_0$wget;
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wire [65 : 0] reqQ_enqReq_lat_0$wget;
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// register fromHostAddr
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reg [60 : 0] fromHostAddr;
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wire [60 : 0] fromHostAddr$D_IN;
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wire fromHostAddr$EN;
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// register pendQ_clearReq_rl
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reg pendQ_clearReq_rl;
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wire pendQ_clearReq_rl$D_IN, pendQ_clearReq_rl$EN;
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// register pendQ_deqReq_rl
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reg pendQ_deqReq_rl;
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wire pendQ_deqReq_rl$D_IN, pendQ_deqReq_rl$EN;
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// register pendQ_empty
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reg pendQ_empty;
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wire pendQ_empty$D_IN, pendQ_empty$EN;
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// register pendQ_enqReq_rl
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reg pendQ_enqReq_rl;
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wire pendQ_enqReq_rl$D_IN, pendQ_enqReq_rl$EN;
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// register pendQ_full
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reg pendQ_full;
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wire pendQ_full$D_IN, pendQ_full$EN;
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// register reqQ_clearReq_rl
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reg reqQ_clearReq_rl;
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wire reqQ_clearReq_rl$D_IN, reqQ_clearReq_rl$EN;
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// register reqQ_data_0
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reg [64 : 0] reqQ_data_0;
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wire [64 : 0] reqQ_data_0$D_IN;
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wire reqQ_data_0$EN;
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// register reqQ_deqReq_rl
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reg reqQ_deqReq_rl;
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wire reqQ_deqReq_rl$D_IN, reqQ_deqReq_rl$EN;
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// register reqQ_empty
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reg reqQ_empty;
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wire reqQ_empty$D_IN, reqQ_empty$EN;
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// register reqQ_enqReq_rl
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reg [65 : 0] reqQ_enqReq_rl;
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wire [65 : 0] reqQ_enqReq_rl$D_IN;
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wire reqQ_enqReq_rl$EN;
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// register reqQ_full
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reg reqQ_full;
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wire reqQ_full$D_IN, reqQ_full$EN;
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// register respQ_clearReq_rl
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reg respQ_clearReq_rl;
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wire respQ_clearReq_rl$D_IN, respQ_clearReq_rl$EN;
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// register respQ_data_0
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reg [65 : 0] respQ_data_0;
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wire [65 : 0] respQ_data_0$D_IN;
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wire respQ_data_0$EN;
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// register respQ_deqReq_rl
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reg respQ_deqReq_rl;
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wire respQ_deqReq_rl$D_IN, respQ_deqReq_rl$EN;
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// register respQ_empty
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reg respQ_empty;
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wire respQ_empty$D_IN, respQ_empty$EN;
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// register respQ_enqReq_rl
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reg [66 : 0] respQ_enqReq_rl;
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wire [66 : 0] respQ_enqReq_rl$D_IN;
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wire respQ_enqReq_rl$EN;
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// register respQ_full
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reg respQ_full;
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wire respQ_full$D_IN, respQ_full$EN;
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// register toHostAddr
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reg [60 : 0] toHostAddr;
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wire [60 : 0] toHostAddr$D_IN;
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wire toHostAddr$EN;
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// ports of submodule pendQ_clearReq_dummy2_0
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wire pendQ_clearReq_dummy2_0$D_IN, pendQ_clearReq_dummy2_0$EN;
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// ports of submodule pendQ_clearReq_dummy2_1
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wire pendQ_clearReq_dummy2_1$D_IN,
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pendQ_clearReq_dummy2_1$EN,
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pendQ_clearReq_dummy2_1$Q_OUT;
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// ports of submodule pendQ_deqReq_dummy2_0
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wire pendQ_deqReq_dummy2_0$D_IN, pendQ_deqReq_dummy2_0$EN;
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// ports of submodule pendQ_deqReq_dummy2_1
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wire pendQ_deqReq_dummy2_1$D_IN, pendQ_deqReq_dummy2_1$EN;
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// ports of submodule pendQ_deqReq_dummy2_2
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wire pendQ_deqReq_dummy2_2$D_IN,
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pendQ_deqReq_dummy2_2$EN,
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pendQ_deqReq_dummy2_2$Q_OUT;
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// ports of submodule pendQ_enqReq_dummy2_0
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wire pendQ_enqReq_dummy2_0$D_IN, pendQ_enqReq_dummy2_0$EN;
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// ports of submodule pendQ_enqReq_dummy2_1
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wire pendQ_enqReq_dummy2_1$D_IN, pendQ_enqReq_dummy2_1$EN;
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// ports of submodule pendQ_enqReq_dummy2_2
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wire pendQ_enqReq_dummy2_2$D_IN,
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pendQ_enqReq_dummy2_2$EN,
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pendQ_enqReq_dummy2_2$Q_OUT;
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// ports of submodule reqQ_clearReq_dummy2_0
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wire reqQ_clearReq_dummy2_0$D_IN, reqQ_clearReq_dummy2_0$EN;
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// ports of submodule reqQ_clearReq_dummy2_1
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wire reqQ_clearReq_dummy2_1$D_IN,
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reqQ_clearReq_dummy2_1$EN,
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reqQ_clearReq_dummy2_1$Q_OUT;
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// ports of submodule reqQ_deqReq_dummy2_0
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wire reqQ_deqReq_dummy2_0$D_IN, reqQ_deqReq_dummy2_0$EN;
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// ports of submodule reqQ_deqReq_dummy2_1
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wire reqQ_deqReq_dummy2_1$D_IN, reqQ_deqReq_dummy2_1$EN;
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// ports of submodule reqQ_deqReq_dummy2_2
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wire reqQ_deqReq_dummy2_2$D_IN,
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reqQ_deqReq_dummy2_2$EN,
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reqQ_deqReq_dummy2_2$Q_OUT;
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// ports of submodule reqQ_enqReq_dummy2_0
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wire reqQ_enqReq_dummy2_0$D_IN, reqQ_enqReq_dummy2_0$EN;
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// ports of submodule reqQ_enqReq_dummy2_1
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wire reqQ_enqReq_dummy2_1$D_IN, reqQ_enqReq_dummy2_1$EN;
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// ports of submodule reqQ_enqReq_dummy2_2
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wire reqQ_enqReq_dummy2_2$D_IN,
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reqQ_enqReq_dummy2_2$EN,
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reqQ_enqReq_dummy2_2$Q_OUT;
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// ports of submodule respQ_clearReq_dummy2_0
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wire respQ_clearReq_dummy2_0$D_IN, respQ_clearReq_dummy2_0$EN;
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// ports of submodule respQ_clearReq_dummy2_1
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wire respQ_clearReq_dummy2_1$D_IN,
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respQ_clearReq_dummy2_1$EN,
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respQ_clearReq_dummy2_1$Q_OUT;
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// ports of submodule respQ_deqReq_dummy2_0
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wire respQ_deqReq_dummy2_0$D_IN, respQ_deqReq_dummy2_0$EN;
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// ports of submodule respQ_deqReq_dummy2_1
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wire respQ_deqReq_dummy2_1$D_IN, respQ_deqReq_dummy2_1$EN;
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// ports of submodule respQ_deqReq_dummy2_2
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wire respQ_deqReq_dummy2_2$D_IN,
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respQ_deqReq_dummy2_2$EN,
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respQ_deqReq_dummy2_2$Q_OUT;
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// ports of submodule respQ_enqReq_dummy2_0
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wire respQ_enqReq_dummy2_0$D_IN, respQ_enqReq_dummy2_0$EN;
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// ports of submodule respQ_enqReq_dummy2_1
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wire respQ_enqReq_dummy2_1$D_IN, respQ_enqReq_dummy2_1$EN;
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// ports of submodule respQ_enqReq_dummy2_2
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wire respQ_enqReq_dummy2_2$D_IN,
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respQ_enqReq_dummy2_2$EN,
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respQ_enqReq_dummy2_2$Q_OUT;
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// ports of submodule soc_map
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wire [63 : 0] soc_map$m_is_IO_addr_addr,
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soc_map$m_is_mem_addr_addr,
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soc_map$m_is_near_mem_IO_addr_addr;
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wire soc_map$m_is_IO_addr;
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// rule scheduling signals
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wire CAN_FIRE_RL_pendQ_canonicalize,
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CAN_FIRE_RL_pendQ_clearReq_canon,
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CAN_FIRE_RL_pendQ_deqReq_canon,
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CAN_FIRE_RL_pendQ_enqReq_canon,
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CAN_FIRE_RL_reqQ_canonicalize,
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CAN_FIRE_RL_reqQ_clearReq_canon,
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CAN_FIRE_RL_reqQ_deqReq_canon,
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CAN_FIRE_RL_reqQ_enqReq_canon,
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CAN_FIRE_RL_respQ_canonicalize,
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CAN_FIRE_RL_respQ_clearReq_canon,
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CAN_FIRE_RL_respQ_deqReq_canon,
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CAN_FIRE_RL_respQ_enqReq_canon,
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CAN_FIRE_bootRomReq,
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CAN_FIRE_bootRomResp,
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CAN_FIRE_toCore_instReq_deq,
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CAN_FIRE_toCore_instResp_enq,
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CAN_FIRE_toCore_setHtifAddrs,
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WILL_FIRE_RL_pendQ_canonicalize,
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WILL_FIRE_RL_pendQ_clearReq_canon,
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WILL_FIRE_RL_pendQ_deqReq_canon,
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WILL_FIRE_RL_pendQ_enqReq_canon,
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WILL_FIRE_RL_reqQ_canonicalize,
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WILL_FIRE_RL_reqQ_clearReq_canon,
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WILL_FIRE_RL_reqQ_deqReq_canon,
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WILL_FIRE_RL_reqQ_enqReq_canon,
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WILL_FIRE_RL_respQ_canonicalize,
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WILL_FIRE_RL_respQ_clearReq_canon,
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WILL_FIRE_RL_respQ_deqReq_canon,
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WILL_FIRE_RL_respQ_enqReq_canon,
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WILL_FIRE_bootRomReq,
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WILL_FIRE_bootRomResp,
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WILL_FIRE_toCore_instReq_deq,
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WILL_FIRE_toCore_instResp_enq,
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WILL_FIRE_toCore_setHtifAddrs;
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// remaining internal signals
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wire IF_reqQ_enqReq_lat_1_whas_THEN_reqQ_enqReq_lat_ETC___d13,
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IF_respQ_enqReq_lat_1_whas__2_THEN_respQ_enqRe_ETC___d91,
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NOT_pendQ_enqReq_dummy2_2_read__34_49_OR_IF_pe_ETC___d259,
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NOT_reqQ_clearReq_dummy2_1_read__8_9_OR_IF_req_ETC___d53,
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NOT_reqQ_enqReq_dummy2_2_read__4_9_OR_IF_reqQ__ETC___d74,
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NOT_respQ_clearReq_dummy2_1_read__64_65_OR_IF__ETC___d169,
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NOT_respQ_enqReq_dummy2_2_read__70_85_OR_IF_re_ETC___d190,
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pendQ_enqReq_dummy2_2_read__34_AND_IF_pendQ_en_ETC___d246,
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reqQ_enqReq_dummy2_2_read__4_AND_IF_reqQ_enqRe_ETC___d66,
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respQ_enqReq_dummy2_2_read__70_AND_IF_respQ_en_ETC___d182;
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// value method getFetchTarget
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assign getFetchTarget =
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soc_map$m_is_IO_addr ?
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2'd1 :
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((getFetchTarget_phyPc[63:3] >= 61'd402653184 &&
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getFetchTarget_phyPc[63:3] < 61'd536870912 &&
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getFetchTarget_phyPc[63:3] != toHostAddr &&
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getFetchTarget_phyPc[63:3] != fromHostAddr) ?
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2'd0 :
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2'd2) ;
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assign RDY_getFetchTarget = 1'd1 ;
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// action method bootRomReq
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assign RDY_bootRomReq = !reqQ_full && !pendQ_full ;
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assign CAN_FIRE_bootRomReq = !reqQ_full && !pendQ_full ;
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assign WILL_FIRE_bootRomReq = EN_bootRomReq ;
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// actionvalue method bootRomResp
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assign bootRomResp = respQ_data_0 ;
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assign RDY_bootRomResp = !respQ_empty && !pendQ_empty ;
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assign CAN_FIRE_bootRomResp = !respQ_empty && !pendQ_empty ;
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assign WILL_FIRE_bootRomResp = EN_bootRomResp ;
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// value method toCore_instReq_notEmpty
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assign toCore_instReq_notEmpty = !reqQ_empty ;
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assign RDY_toCore_instReq_notEmpty = 1'd1 ;
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// action method toCore_instReq_deq
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assign RDY_toCore_instReq_deq = !reqQ_empty ;
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assign CAN_FIRE_toCore_instReq_deq = !reqQ_empty ;
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assign WILL_FIRE_toCore_instReq_deq = EN_toCore_instReq_deq ;
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// value method toCore_instReq_first_fst
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assign toCore_instReq_first_fst = reqQ_data_0[64:1] ;
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assign RDY_toCore_instReq_first_fst = !reqQ_empty ;
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// value method toCore_instReq_first_snd
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assign toCore_instReq_first_snd = reqQ_data_0[0] ;
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assign RDY_toCore_instReq_first_snd = !reqQ_empty ;
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// value method toCore_instResp_notFull
|
|
assign toCore_instResp_notFull = !respQ_full ;
|
|
assign RDY_toCore_instResp_notFull = 1'd1 ;
|
|
|
|
// action method toCore_instResp_enq
|
|
assign RDY_toCore_instResp_enq = !respQ_full ;
|
|
assign CAN_FIRE_toCore_instResp_enq = !respQ_full ;
|
|
assign WILL_FIRE_toCore_instResp_enq = EN_toCore_instResp_enq ;
|
|
|
|
// action method toCore_setHtifAddrs
|
|
assign RDY_toCore_setHtifAddrs = 1'd1 ;
|
|
assign CAN_FIRE_toCore_setHtifAddrs = 1'd1 ;
|
|
assign WILL_FIRE_toCore_setHtifAddrs = EN_toCore_setHtifAddrs ;
|
|
|
|
// submodule pendQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(pendQ_clearReq_dummy2_0$D_IN),
|
|
.EN(pendQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule pendQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(pendQ_clearReq_dummy2_1$D_IN),
|
|
.EN(pendQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(pendQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule pendQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(pendQ_deqReq_dummy2_0$D_IN),
|
|
.EN(pendQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule pendQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(pendQ_deqReq_dummy2_1$D_IN),
|
|
.EN(pendQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule pendQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(pendQ_deqReq_dummy2_2$D_IN),
|
|
.EN(pendQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(pendQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule pendQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(pendQ_enqReq_dummy2_0$D_IN),
|
|
.EN(pendQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule pendQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(pendQ_enqReq_dummy2_1$D_IN),
|
|
.EN(pendQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule pendQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) pendQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(pendQ_enqReq_dummy2_2$D_IN),
|
|
.EN(pendQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(pendQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule reqQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(reqQ_clearReq_dummy2_0$D_IN),
|
|
.EN(reqQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule reqQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(reqQ_clearReq_dummy2_1$D_IN),
|
|
.EN(reqQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(reqQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule reqQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(reqQ_deqReq_dummy2_0$D_IN),
|
|
.EN(reqQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule reqQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(reqQ_deqReq_dummy2_1$D_IN),
|
|
.EN(reqQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule reqQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(reqQ_deqReq_dummy2_2$D_IN),
|
|
.EN(reqQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(reqQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule reqQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(reqQ_enqReq_dummy2_0$D_IN),
|
|
.EN(reqQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule reqQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(reqQ_enqReq_dummy2_1$D_IN),
|
|
.EN(reqQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule reqQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) reqQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(reqQ_enqReq_dummy2_2$D_IN),
|
|
.EN(reqQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(reqQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule respQ_clearReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_clearReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respQ_clearReq_dummy2_0$D_IN),
|
|
.EN(respQ_clearReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respQ_clearReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_clearReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respQ_clearReq_dummy2_1$D_IN),
|
|
.EN(respQ_clearReq_dummy2_1$EN),
|
|
.Q_OUT(respQ_clearReq_dummy2_1$Q_OUT));
|
|
|
|
// submodule respQ_deqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_deqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respQ_deqReq_dummy2_0$D_IN),
|
|
.EN(respQ_deqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respQ_deqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_deqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respQ_deqReq_dummy2_1$D_IN),
|
|
.EN(respQ_deqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respQ_deqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_deqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(respQ_deqReq_dummy2_2$D_IN),
|
|
.EN(respQ_deqReq_dummy2_2$EN),
|
|
.Q_OUT(respQ_deqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule respQ_enqReq_dummy2_0
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_enqReq_dummy2_0(.CLK(CLK),
|
|
.D_IN(respQ_enqReq_dummy2_0$D_IN),
|
|
.EN(respQ_enqReq_dummy2_0$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respQ_enqReq_dummy2_1
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_enqReq_dummy2_1(.CLK(CLK),
|
|
.D_IN(respQ_enqReq_dummy2_1$D_IN),
|
|
.EN(respQ_enqReq_dummy2_1$EN),
|
|
.Q_OUT());
|
|
|
|
// submodule respQ_enqReq_dummy2_2
|
|
RevertReg #(.width(32'd1), .init(1'd1)) respQ_enqReq_dummy2_2(.CLK(CLK),
|
|
.D_IN(respQ_enqReq_dummy2_2$D_IN),
|
|
.EN(respQ_enqReq_dummy2_2$EN),
|
|
.Q_OUT(respQ_enqReq_dummy2_2$Q_OUT));
|
|
|
|
// submodule soc_map
|
|
mkSoC_Map soc_map(.CLK(CLK),
|
|
.RST_N(RST_N),
|
|
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
|
|
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
|
|
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
|
|
.m_plic_addr_base(),
|
|
.m_plic_addr_size(),
|
|
.m_plic_addr_lim(),
|
|
.m_near_mem_io_addr_base(),
|
|
.m_near_mem_io_addr_size(),
|
|
.m_near_mem_io_addr_lim(),
|
|
.m_flash_mem_addr_base(),
|
|
.m_flash_mem_addr_size(),
|
|
.m_flash_mem_addr_lim(),
|
|
.m_ethernet_0_addr_base(),
|
|
.m_ethernet_0_addr_size(),
|
|
.m_ethernet_0_addr_lim(),
|
|
.m_dma_0_addr_base(),
|
|
.m_dma_0_addr_size(),
|
|
.m_dma_0_addr_lim(),
|
|
.m_uart16550_0_addr_base(),
|
|
.m_uart16550_0_addr_size(),
|
|
.m_uart16550_0_addr_lim(),
|
|
.m_gpio_0_addr_base(),
|
|
.m_gpio_0_addr_size(),
|
|
.m_gpio_0_addr_lim(),
|
|
.m_boot_rom_addr_base(),
|
|
.m_boot_rom_addr_size(),
|
|
.m_boot_rom_addr_lim(),
|
|
.m_ddr4_0_uncached_addr_base(),
|
|
.m_ddr4_0_uncached_addr_size(),
|
|
.m_ddr4_0_uncached_addr_lim(),
|
|
.m_ddr4_0_cached_addr_base(),
|
|
.m_ddr4_0_cached_addr_size(),
|
|
.m_ddr4_0_cached_addr_lim(),
|
|
.m_mem0_controller_addr_base(),
|
|
.m_mem0_controller_addr_size(),
|
|
.m_mem0_controller_addr_lim(),
|
|
.m_is_mem_addr(),
|
|
.m_is_IO_addr(soc_map$m_is_IO_addr),
|
|
.m_is_near_mem_IO_addr(),
|
|
.m_pc_reset_value(),
|
|
.m_mtvec_reset_value(),
|
|
.m_nmivec_reset_value());
|
|
|
|
// rule RL_reqQ_canonicalize
|
|
assign CAN_FIRE_RL_reqQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_reqQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_reqQ_enqReq_canon
|
|
assign CAN_FIRE_RL_reqQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_reqQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_reqQ_deqReq_canon
|
|
assign CAN_FIRE_RL_reqQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_reqQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_reqQ_clearReq_canon
|
|
assign CAN_FIRE_RL_reqQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_reqQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respQ_canonicalize
|
|
assign CAN_FIRE_RL_respQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_respQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_respQ_enqReq_canon
|
|
assign CAN_FIRE_RL_respQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respQ_deqReq_canon
|
|
assign CAN_FIRE_RL_respQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_respQ_clearReq_canon
|
|
assign CAN_FIRE_RL_respQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_respQ_clearReq_canon = 1'd1 ;
|
|
|
|
// rule RL_pendQ_canonicalize
|
|
assign CAN_FIRE_RL_pendQ_canonicalize = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendQ_canonicalize = 1'd1 ;
|
|
|
|
// rule RL_pendQ_enqReq_canon
|
|
assign CAN_FIRE_RL_pendQ_enqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendQ_enqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_pendQ_deqReq_canon
|
|
assign CAN_FIRE_RL_pendQ_deqReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendQ_deqReq_canon = 1'd1 ;
|
|
|
|
// rule RL_pendQ_clearReq_canon
|
|
assign CAN_FIRE_RL_pendQ_clearReq_canon = 1'd1 ;
|
|
assign WILL_FIRE_RL_pendQ_clearReq_canon = 1'd1 ;
|
|
|
|
// inlined wires
|
|
assign reqQ_enqReq_lat_0$wget =
|
|
{ 1'd1, bootRomReq_phyPc, bootRomReq_maxWay } ;
|
|
assign respQ_enqReq_lat_0$wget = { 1'd1, toCore_instResp_enq_x } ;
|
|
|
|
// register fromHostAddr
|
|
assign fromHostAddr$D_IN = toCore_setHtifAddrs_fromHost[63:3] ;
|
|
assign fromHostAddr$EN = EN_toCore_setHtifAddrs ;
|
|
|
|
// register pendQ_clearReq_rl
|
|
assign pendQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign pendQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register pendQ_deqReq_rl
|
|
assign pendQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign pendQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register pendQ_empty
|
|
assign pendQ_empty$D_IN =
|
|
pendQ_clearReq_dummy2_1$Q_OUT && pendQ_clearReq_rl ||
|
|
NOT_pendQ_enqReq_dummy2_2_read__34_49_OR_IF_pe_ETC___d259 ;
|
|
assign pendQ_empty$EN = 1'd1 ;
|
|
|
|
// register pendQ_enqReq_rl
|
|
assign pendQ_enqReq_rl$D_IN = 1'd0 ;
|
|
assign pendQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register pendQ_full
|
|
assign pendQ_full$D_IN =
|
|
(!pendQ_clearReq_dummy2_1$Q_OUT || !pendQ_clearReq_rl) &&
|
|
pendQ_enqReq_dummy2_2_read__34_AND_IF_pendQ_en_ETC___d246 ;
|
|
assign pendQ_full$EN = 1'd1 ;
|
|
|
|
// register reqQ_clearReq_rl
|
|
assign reqQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign reqQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register reqQ_data_0
|
|
assign reqQ_data_0$D_IN =
|
|
EN_bootRomReq ?
|
|
reqQ_enqReq_lat_0$wget[64:0] :
|
|
reqQ_enqReq_rl[64:0] ;
|
|
assign reqQ_data_0$EN =
|
|
NOT_reqQ_clearReq_dummy2_1_read__8_9_OR_IF_req_ETC___d53 &&
|
|
reqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_reqQ_enqReq_lat_1_whas_THEN_reqQ_enqReq_lat_ETC___d13 ;
|
|
|
|
// register reqQ_deqReq_rl
|
|
assign reqQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign reqQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register reqQ_empty
|
|
assign reqQ_empty$D_IN =
|
|
reqQ_clearReq_dummy2_1$Q_OUT && reqQ_clearReq_rl ||
|
|
NOT_reqQ_enqReq_dummy2_2_read__4_9_OR_IF_reqQ__ETC___d74 ;
|
|
assign reqQ_empty$EN = 1'd1 ;
|
|
|
|
// register reqQ_enqReq_rl
|
|
assign reqQ_enqReq_rl$D_IN = 66'h0AAAAAAAAAAAAAAAA ;
|
|
assign reqQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register reqQ_full
|
|
assign reqQ_full$D_IN =
|
|
NOT_reqQ_clearReq_dummy2_1_read__8_9_OR_IF_req_ETC___d53 &&
|
|
reqQ_enqReq_dummy2_2_read__4_AND_IF_reqQ_enqRe_ETC___d66 ;
|
|
assign reqQ_full$EN = 1'd1 ;
|
|
|
|
// register respQ_clearReq_rl
|
|
assign respQ_clearReq_rl$D_IN = 1'd0 ;
|
|
assign respQ_clearReq_rl$EN = 1'd1 ;
|
|
|
|
// register respQ_data_0
|
|
assign respQ_data_0$D_IN =
|
|
{ EN_toCore_instResp_enq ?
|
|
respQ_enqReq_lat_0$wget[65] :
|
|
respQ_enqReq_rl[65],
|
|
EN_toCore_instResp_enq ?
|
|
respQ_enqReq_lat_0$wget[64:33] :
|
|
respQ_enqReq_rl[64:33],
|
|
EN_toCore_instResp_enq ?
|
|
respQ_enqReq_lat_0$wget[32] :
|
|
respQ_enqReq_rl[32],
|
|
EN_toCore_instResp_enq ?
|
|
respQ_enqReq_lat_0$wget[31:0] :
|
|
respQ_enqReq_rl[31:0] } ;
|
|
assign respQ_data_0$EN =
|
|
NOT_respQ_clearReq_dummy2_1_read__64_65_OR_IF__ETC___d169 &&
|
|
respQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_respQ_enqReq_lat_1_whas__2_THEN_respQ_enqRe_ETC___d91 ;
|
|
|
|
// register respQ_deqReq_rl
|
|
assign respQ_deqReq_rl$D_IN = 1'd0 ;
|
|
assign respQ_deqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respQ_empty
|
|
assign respQ_empty$D_IN =
|
|
respQ_clearReq_dummy2_1$Q_OUT && respQ_clearReq_rl ||
|
|
NOT_respQ_enqReq_dummy2_2_read__70_85_OR_IF_re_ETC___d190 ;
|
|
assign respQ_empty$EN = 1'd1 ;
|
|
|
|
// register respQ_enqReq_rl
|
|
assign respQ_enqReq_rl$D_IN = 67'h2AAAAAAAAAAAAAAAA ;
|
|
assign respQ_enqReq_rl$EN = 1'd1 ;
|
|
|
|
// register respQ_full
|
|
assign respQ_full$D_IN =
|
|
NOT_respQ_clearReq_dummy2_1_read__64_65_OR_IF__ETC___d169 &&
|
|
respQ_enqReq_dummy2_2_read__70_AND_IF_respQ_en_ETC___d182 ;
|
|
assign respQ_full$EN = 1'd1 ;
|
|
|
|
// register toHostAddr
|
|
assign toHostAddr$D_IN = toCore_setHtifAddrs_toHost[63:3] ;
|
|
assign toHostAddr$EN = EN_toCore_setHtifAddrs ;
|
|
|
|
// submodule pendQ_clearReq_dummy2_0
|
|
assign pendQ_clearReq_dummy2_0$D_IN = 1'b0 ;
|
|
assign pendQ_clearReq_dummy2_0$EN = 1'b0 ;
|
|
|
|
// submodule pendQ_clearReq_dummy2_1
|
|
assign pendQ_clearReq_dummy2_1$D_IN = 1'd1 ;
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assign pendQ_clearReq_dummy2_1$EN = 1'd1 ;
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// submodule pendQ_deqReq_dummy2_0
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assign pendQ_deqReq_dummy2_0$D_IN = 1'd1 ;
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assign pendQ_deqReq_dummy2_0$EN = EN_bootRomResp ;
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// submodule pendQ_deqReq_dummy2_1
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assign pendQ_deqReq_dummy2_1$D_IN = 1'b0 ;
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assign pendQ_deqReq_dummy2_1$EN = 1'b0 ;
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// submodule pendQ_deqReq_dummy2_2
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assign pendQ_deqReq_dummy2_2$D_IN = 1'd1 ;
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assign pendQ_deqReq_dummy2_2$EN = 1'd1 ;
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// submodule pendQ_enqReq_dummy2_0
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assign pendQ_enqReq_dummy2_0$D_IN = 1'd1 ;
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assign pendQ_enqReq_dummy2_0$EN = EN_bootRomReq ;
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// submodule pendQ_enqReq_dummy2_1
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assign pendQ_enqReq_dummy2_1$D_IN = 1'b0 ;
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assign pendQ_enqReq_dummy2_1$EN = 1'b0 ;
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// submodule pendQ_enqReq_dummy2_2
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assign pendQ_enqReq_dummy2_2$D_IN = 1'd1 ;
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assign pendQ_enqReq_dummy2_2$EN = 1'd1 ;
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// submodule reqQ_clearReq_dummy2_0
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assign reqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
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assign reqQ_clearReq_dummy2_0$EN = 1'b0 ;
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// submodule reqQ_clearReq_dummy2_1
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assign reqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
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assign reqQ_clearReq_dummy2_1$EN = 1'd1 ;
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// submodule reqQ_deqReq_dummy2_0
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assign reqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
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assign reqQ_deqReq_dummy2_0$EN = EN_toCore_instReq_deq ;
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// submodule reqQ_deqReq_dummy2_1
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assign reqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
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assign reqQ_deqReq_dummy2_1$EN = 1'b0 ;
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|
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// submodule reqQ_deqReq_dummy2_2
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assign reqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
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assign reqQ_deqReq_dummy2_2$EN = 1'd1 ;
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// submodule reqQ_enqReq_dummy2_0
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assign reqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
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assign reqQ_enqReq_dummy2_0$EN = EN_bootRomReq ;
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|
|
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// submodule reqQ_enqReq_dummy2_1
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assign reqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
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assign reqQ_enqReq_dummy2_1$EN = 1'b0 ;
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|
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// submodule reqQ_enqReq_dummy2_2
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assign reqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
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assign reqQ_enqReq_dummy2_2$EN = 1'd1 ;
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|
|
|
// submodule respQ_clearReq_dummy2_0
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|
assign respQ_clearReq_dummy2_0$D_IN = 1'b0 ;
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|
assign respQ_clearReq_dummy2_0$EN = 1'b0 ;
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|
|
|
// submodule respQ_clearReq_dummy2_1
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|
assign respQ_clearReq_dummy2_1$D_IN = 1'd1 ;
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|
assign respQ_clearReq_dummy2_1$EN = 1'd1 ;
|
|
|
|
// submodule respQ_deqReq_dummy2_0
|
|
assign respQ_deqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign respQ_deqReq_dummy2_0$EN = EN_bootRomResp ;
|
|
|
|
// submodule respQ_deqReq_dummy2_1
|
|
assign respQ_deqReq_dummy2_1$D_IN = 1'b0 ;
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|
assign respQ_deqReq_dummy2_1$EN = 1'b0 ;
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|
|
|
// submodule respQ_deqReq_dummy2_2
|
|
assign respQ_deqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign respQ_deqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule respQ_enqReq_dummy2_0
|
|
assign respQ_enqReq_dummy2_0$D_IN = 1'd1 ;
|
|
assign respQ_enqReq_dummy2_0$EN = EN_toCore_instResp_enq ;
|
|
|
|
// submodule respQ_enqReq_dummy2_1
|
|
assign respQ_enqReq_dummy2_1$D_IN = 1'b0 ;
|
|
assign respQ_enqReq_dummy2_1$EN = 1'b0 ;
|
|
|
|
// submodule respQ_enqReq_dummy2_2
|
|
assign respQ_enqReq_dummy2_2$D_IN = 1'd1 ;
|
|
assign respQ_enqReq_dummy2_2$EN = 1'd1 ;
|
|
|
|
// submodule soc_map
|
|
assign soc_map$m_is_IO_addr_addr = getFetchTarget_phyPc ;
|
|
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
|
|
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
|
|
|
|
// remaining internal signals
|
|
assign IF_reqQ_enqReq_lat_1_whas_THEN_reqQ_enqReq_lat_ETC___d13 =
|
|
EN_bootRomReq ? reqQ_enqReq_lat_0$wget[65] : reqQ_enqReq_rl[65] ;
|
|
assign IF_respQ_enqReq_lat_1_whas__2_THEN_respQ_enqRe_ETC___d91 =
|
|
EN_toCore_instResp_enq ?
|
|
respQ_enqReq_lat_0$wget[66] :
|
|
respQ_enqReq_rl[66] ;
|
|
assign NOT_pendQ_enqReq_dummy2_2_read__34_49_OR_IF_pe_ETC___d259 =
|
|
(!pendQ_enqReq_dummy2_2$Q_OUT ||
|
|
!EN_bootRomReq && !pendQ_enqReq_rl) &&
|
|
(pendQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_bootRomResp || pendQ_deqReq_rl) ||
|
|
pendQ_empty) ;
|
|
assign NOT_reqQ_clearReq_dummy2_1_read__8_9_OR_IF_req_ETC___d53 =
|
|
!reqQ_clearReq_dummy2_1$Q_OUT || !reqQ_clearReq_rl ;
|
|
assign NOT_reqQ_enqReq_dummy2_2_read__4_9_OR_IF_reqQ__ETC___d74 =
|
|
(!reqQ_enqReq_dummy2_2$Q_OUT ||
|
|
(EN_bootRomReq ?
|
|
!reqQ_enqReq_lat_0$wget[65] :
|
|
!reqQ_enqReq_rl[65])) &&
|
|
(reqQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_toCore_instReq_deq || reqQ_deqReq_rl) ||
|
|
reqQ_empty) ;
|
|
assign NOT_respQ_clearReq_dummy2_1_read__64_65_OR_IF__ETC___d169 =
|
|
!respQ_clearReq_dummy2_1$Q_OUT || !respQ_clearReq_rl ;
|
|
assign NOT_respQ_enqReq_dummy2_2_read__70_85_OR_IF_re_ETC___d190 =
|
|
(!respQ_enqReq_dummy2_2$Q_OUT ||
|
|
(EN_toCore_instResp_enq ?
|
|
!respQ_enqReq_lat_0$wget[66] :
|
|
!respQ_enqReq_rl[66])) &&
|
|
(respQ_deqReq_dummy2_2$Q_OUT &&
|
|
(EN_bootRomResp || respQ_deqReq_rl) ||
|
|
respQ_empty) ;
|
|
assign pendQ_enqReq_dummy2_2_read__34_AND_IF_pendQ_en_ETC___d246 =
|
|
pendQ_enqReq_dummy2_2$Q_OUT &&
|
|
(EN_bootRomReq || pendQ_enqReq_rl) ||
|
|
(!pendQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_bootRomResp && !pendQ_deqReq_rl) &&
|
|
pendQ_full ;
|
|
assign reqQ_enqReq_dummy2_2_read__4_AND_IF_reqQ_enqRe_ETC___d66 =
|
|
reqQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_reqQ_enqReq_lat_1_whas_THEN_reqQ_enqReq_lat_ETC___d13 ||
|
|
(!reqQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_toCore_instReq_deq && !reqQ_deqReq_rl) &&
|
|
reqQ_full ;
|
|
assign respQ_enqReq_dummy2_2_read__70_AND_IF_respQ_en_ETC___d182 =
|
|
respQ_enqReq_dummy2_2$Q_OUT &&
|
|
IF_respQ_enqReq_lat_1_whas__2_THEN_respQ_enqRe_ETC___d91 ||
|
|
(!respQ_deqReq_dummy2_2$Q_OUT ||
|
|
!EN_bootRomResp && !respQ_deqReq_rl) &&
|
|
respQ_full ;
|
|
|
|
// handling of inlined registers
|
|
|
|
always@(posedge CLK)
|
|
begin
|
|
if (RST_N == `BSV_RESET_VALUE)
|
|
begin
|
|
fromHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
|
|
pendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
pendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
pendQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
reqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
reqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 65'd0;
|
|
reqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
reqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
reqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 66'h0AAAAAAAAAAAAAAAA;
|
|
reqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respQ_data_0 <= `BSV_ASSIGNMENT_DELAY 66'h155555554AAAAAAAA;
|
|
respQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
respQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
|
|
respQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 67'h2AAAAAAAAAAAAAAAA;
|
|
respQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
|
|
toHostAddr <= `BSV_ASSIGNMENT_DELAY 61'd0;
|
|
end
|
|
else
|
|
begin
|
|
if (fromHostAddr$EN)
|
|
fromHostAddr <= `BSV_ASSIGNMENT_DELAY fromHostAddr$D_IN;
|
|
if (pendQ_clearReq_rl$EN)
|
|
pendQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY pendQ_clearReq_rl$D_IN;
|
|
if (pendQ_deqReq_rl$EN)
|
|
pendQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY pendQ_deqReq_rl$D_IN;
|
|
if (pendQ_empty$EN)
|
|
pendQ_empty <= `BSV_ASSIGNMENT_DELAY pendQ_empty$D_IN;
|
|
if (pendQ_enqReq_rl$EN)
|
|
pendQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY pendQ_enqReq_rl$D_IN;
|
|
if (pendQ_full$EN)
|
|
pendQ_full <= `BSV_ASSIGNMENT_DELAY pendQ_full$D_IN;
|
|
if (reqQ_clearReq_rl$EN)
|
|
reqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY reqQ_clearReq_rl$D_IN;
|
|
if (reqQ_data_0$EN)
|
|
reqQ_data_0 <= `BSV_ASSIGNMENT_DELAY reqQ_data_0$D_IN;
|
|
if (reqQ_deqReq_rl$EN)
|
|
reqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY reqQ_deqReq_rl$D_IN;
|
|
if (reqQ_empty$EN)
|
|
reqQ_empty <= `BSV_ASSIGNMENT_DELAY reqQ_empty$D_IN;
|
|
if (reqQ_enqReq_rl$EN)
|
|
reqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY reqQ_enqReq_rl$D_IN;
|
|
if (reqQ_full$EN) reqQ_full <= `BSV_ASSIGNMENT_DELAY reqQ_full$D_IN;
|
|
if (respQ_clearReq_rl$EN)
|
|
respQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY respQ_clearReq_rl$D_IN;
|
|
if (respQ_data_0$EN)
|
|
respQ_data_0 <= `BSV_ASSIGNMENT_DELAY respQ_data_0$D_IN;
|
|
if (respQ_deqReq_rl$EN)
|
|
respQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY respQ_deqReq_rl$D_IN;
|
|
if (respQ_empty$EN)
|
|
respQ_empty <= `BSV_ASSIGNMENT_DELAY respQ_empty$D_IN;
|
|
if (respQ_enqReq_rl$EN)
|
|
respQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY respQ_enqReq_rl$D_IN;
|
|
if (respQ_full$EN)
|
|
respQ_full <= `BSV_ASSIGNMENT_DELAY respQ_full$D_IN;
|
|
if (toHostAddr$EN)
|
|
toHostAddr <= `BSV_ASSIGNMENT_DELAY toHostAddr$D_IN;
|
|
end
|
|
end
|
|
|
|
// synopsys translate_off
|
|
`ifdef BSV_NO_INITIAL_BLOCKS
|
|
`else // not BSV_NO_INITIAL_BLOCKS
|
|
initial
|
|
begin
|
|
fromHostAddr = 61'h0AAAAAAAAAAAAAAA;
|
|
pendQ_clearReq_rl = 1'h0;
|
|
pendQ_deqReq_rl = 1'h0;
|
|
pendQ_empty = 1'h0;
|
|
pendQ_enqReq_rl = 1'h0;
|
|
pendQ_full = 1'h0;
|
|
reqQ_clearReq_rl = 1'h0;
|
|
reqQ_data_0 = 65'h0AAAAAAAAAAAAAAAA;
|
|
reqQ_deqReq_rl = 1'h0;
|
|
reqQ_empty = 1'h0;
|
|
reqQ_enqReq_rl = 66'h2AAAAAAAAAAAAAAAA;
|
|
reqQ_full = 1'h0;
|
|
respQ_clearReq_rl = 1'h0;
|
|
respQ_data_0 = 66'h2AAAAAAAAAAAAAAAA;
|
|
respQ_deqReq_rl = 1'h0;
|
|
respQ_empty = 1'h0;
|
|
respQ_enqReq_rl = 67'h2AAAAAAAAAAAAAAAA;
|
|
respQ_full = 1'h0;
|
|
toHostAddr = 61'h0AAAAAAAAAAAAAAA;
|
|
end
|
|
`endif // BSV_NO_INITIAL_BLOCKS
|
|
// synopsys translate_on
|
|
endmodule // mkMMIOInst
|
|
|