140 lines
2.9 KiB
Verilog
140 lines
2.9 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_enq O 1
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// RDY_deq O 1
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// first O 32
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// RDY_first O 1
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// notFull O 1
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// RDY_notFull O 1 const
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// notEmpty O 1
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// RDY_notEmpty O 1 const
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// CLK_srcClk I 1 clock
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// RST_N_srcRst I 1 unused
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// CLK_dstClk I 1 clock
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// enq_sendData I 32
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// EN_enq I 1
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// EN_deq I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkSyncFifo_w32_d16(CLK_srcClk,
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RST_N_srcRst,
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CLK_dstClk,
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enq_sendData,
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EN_enq,
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RDY_enq,
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EN_deq,
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RDY_deq,
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first,
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RDY_first,
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notFull,
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RDY_notFull,
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notEmpty,
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RDY_notEmpty);
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input CLK_srcClk;
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input RST_N_srcRst;
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input CLK_dstClk;
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// action method enq
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input [31 : 0] enq_sendData;
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input EN_enq;
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output RDY_enq;
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// action method deq
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input EN_deq;
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output RDY_deq;
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// value method first
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output [31 : 0] first;
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output RDY_first;
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// value method notFull
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output notFull;
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output RDY_notFull;
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// value method notEmpty
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output notEmpty;
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output RDY_notEmpty;
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// signals for module outputs
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wire [31 : 0] first;
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wire RDY_deq,
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RDY_enq,
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RDY_first,
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RDY_notEmpty,
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RDY_notFull,
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notEmpty,
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notFull;
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// ports of submodule q
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wire [31 : 0] q$din, q$dout;
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wire q$empty, q$full, q$rd_en, q$wr_en;
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// rule scheduling signals
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wire CAN_FIRE_deq, CAN_FIRE_enq, WILL_FIRE_deq, WILL_FIRE_enq;
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// action method enq
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assign RDY_enq = !q$full ;
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assign CAN_FIRE_enq = !q$full ;
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assign WILL_FIRE_enq = EN_enq ;
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// action method deq
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assign RDY_deq = !q$empty ;
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assign CAN_FIRE_deq = !q$empty ;
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assign WILL_FIRE_deq = EN_deq ;
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// value method first
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assign first = q$dout ;
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assign RDY_first = !q$empty ;
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// value method notFull
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assign notFull = !q$full ;
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assign RDY_notFull = 1'd1 ;
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// value method notEmpty
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assign notEmpty = !q$empty ;
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assign RDY_notEmpty = 1'd1 ;
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// submodule q
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sync_fifo_w32_d16 q(.wr_clk(CLK_srcClk),
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.rd_clk(CLK_dstClk),
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.din(q$din),
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.wr_en(q$wr_en),
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.rd_en(q$rd_en),
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.full(q$full),
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.empty(q$empty),
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.dout(q$dout));
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// submodule q
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assign q$din = enq_sendData ;
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assign q$wr_en = EN_enq ;
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assign q$rd_en = EN_deq ;
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endmodule // mkSyncFifo_w32_d16
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