150 lines
3.8 KiB
Verilog
150 lines
3.8 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// RDY_tv_in_put O 1 reg
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// axi_out_tvalid O 1 reg
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// axi_out_tdata O 608 reg
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// axi_out_tstrb O 76 reg
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// axi_out_tkeep O 76 reg
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// axi_out_tlast O 1 reg
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// CLK I 1 clock
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// RST_N I 1 reset
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// tv_in_put I 608 reg
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// axi_out_tready I 1
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// EN_tv_in_put I 1
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//
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// No combinational paths from inputs to outputs
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module mkTV_Xactor(CLK,
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RST_N,
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tv_in_put,
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EN_tv_in_put,
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RDY_tv_in_put,
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axi_out_tvalid,
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axi_out_tdata,
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axi_out_tstrb,
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axi_out_tkeep,
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axi_out_tlast,
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axi_out_tready);
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input CLK;
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input RST_N;
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// action method tv_in_put
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input [607 : 0] tv_in_put;
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input EN_tv_in_put;
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output RDY_tv_in_put;
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// value method axi_out_m_tvalid
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output axi_out_tvalid;
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// value method axi_out_m_tid
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// value method axi_out_m_tdata
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output [607 : 0] axi_out_tdata;
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// value method axi_out_m_tstrb
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output [75 : 0] axi_out_tstrb;
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// value method axi_out_m_tkeep
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output [75 : 0] axi_out_tkeep;
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// value method axi_out_m_tlast
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output axi_out_tlast;
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// value method axi_out_m_tdest
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// value method axi_out_m_tuser
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// action method axi_out_m_tready
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input axi_out_tready;
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// signals for module outputs
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wire [607 : 0] axi_out_tdata;
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wire [75 : 0] axi_out_tkeep, axi_out_tstrb;
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wire RDY_tv_in_put, axi_out_tlast, axi_out_tvalid;
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// ports of submodule tv_xactor_f_data
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wire [760 : 0] tv_xactor_f_data$D_IN, tv_xactor_f_data$D_OUT;
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wire tv_xactor_f_data$CLR,
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tv_xactor_f_data$DEQ,
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tv_xactor_f_data$EMPTY_N,
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tv_xactor_f_data$ENQ,
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tv_xactor_f_data$FULL_N;
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// rule scheduling signals
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wire CAN_FIRE_axi_out_m_tready,
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CAN_FIRE_tv_in_put,
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WILL_FIRE_axi_out_m_tready,
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WILL_FIRE_tv_in_put;
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// action method tv_in_put
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assign RDY_tv_in_put = tv_xactor_f_data$FULL_N ;
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assign CAN_FIRE_tv_in_put = tv_xactor_f_data$FULL_N ;
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assign WILL_FIRE_tv_in_put = EN_tv_in_put ;
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// value method axi_out_m_tvalid
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assign axi_out_tvalid = tv_xactor_f_data$EMPTY_N ;
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// value method axi_out_m_tdata
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assign axi_out_tdata = tv_xactor_f_data$D_OUT[760:153] ;
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// value method axi_out_m_tstrb
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assign axi_out_tstrb = tv_xactor_f_data$D_OUT[152:77] ;
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// value method axi_out_m_tkeep
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assign axi_out_tkeep = tv_xactor_f_data$D_OUT[76:1] ;
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// value method axi_out_m_tlast
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assign axi_out_tlast = tv_xactor_f_data$D_OUT[0] ;
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// action method axi_out_m_tready
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assign CAN_FIRE_axi_out_m_tready = 1'd1 ;
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assign WILL_FIRE_axi_out_m_tready = 1'd1 ;
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// submodule tv_xactor_f_data
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FIFO2 #(.width(32'd761), .guarded(32'd1)) tv_xactor_f_data(.RST(RST_N),
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.CLK(CLK),
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.D_IN(tv_xactor_f_data$D_IN),
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.ENQ(tv_xactor_f_data$ENQ),
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.DEQ(tv_xactor_f_data$DEQ),
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.CLR(tv_xactor_f_data$CLR),
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.D_OUT(tv_xactor_f_data$D_OUT),
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.FULL_N(tv_xactor_f_data$FULL_N),
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.EMPTY_N(tv_xactor_f_data$EMPTY_N));
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// submodule tv_xactor_f_data
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assign tv_xactor_f_data$D_IN =
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{ tv_in_put, 153'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF } ;
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assign tv_xactor_f_data$ENQ = EN_tv_in_put ;
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assign tv_xactor_f_data$DEQ = tv_xactor_f_data$EMPTY_N && axi_out_tready ;
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assign tv_xactor_f_data$CLR = 1'b0 ;
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endmodule // mkTV_Xactor
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