191 lines
6.1 KiB
Verilog
191 lines
6.1 KiB
Verilog
//
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// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
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//
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//
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//
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//
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// Ports:
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// Name I/O size props
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// amoExec O 64
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// amoExec_amo_inst I 7
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// amoExec_current_data I 64
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// amoExec_in_data I 64
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// amoExec_upper_32_bits I 1
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//
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// Combinational paths from inputs to outputs:
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// (amoExec_amo_inst,
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// amoExec_current_data,
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// amoExec_in_data,
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// amoExec_upper_32_bits) -> amoExec
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//
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//
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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`ifdef BSV_POSITIVE_RESET
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`define BSV_RESET_VALUE 1'b1
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`define BSV_RESET_EDGE posedge
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`else
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`define BSV_RESET_VALUE 1'b0
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`define BSV_RESET_EDGE negedge
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`endif
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module module_amoExec(amoExec_amo_inst,
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amoExec_current_data,
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amoExec_in_data,
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amoExec_upper_32_bits,
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amoExec);
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// value method amoExec
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input [6 : 0] amoExec_amo_inst;
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input [63 : 0] amoExec_current_data;
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input [63 : 0] amoExec_in_data;
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input amoExec_upper_32_bits;
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output [63 : 0] amoExec;
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// signals for module outputs
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wire [63 : 0] amoExec;
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// remaining internal signals
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reg [63 : 0] _theResult_____1__h29,
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_theResult___fst__h122,
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_theResult___fst__h183,
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_theResult___snd__h123;
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wire [63 : 0] SEXT_amoExec_current_data_BITS_31_TO_0_7___d18,
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SEXT_amoExec_current_data_BITS_63_TO_32_3___d14,
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SEXT_amoExec_in_data_BITS_31_TO_0____d8,
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_theResult___fst__h113,
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current_data__h27,
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in_data__h28,
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new_data__h249,
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new_data__h373,
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new_data__h379,
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new_data__h385,
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new_data__h391,
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new_data__h405,
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new_data__h419,
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new_data__h433;
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wire [31 : 0] amoExec_current_data_BITS_31_TO_0__q3,
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amoExec_current_data_BITS_63_TO_32__q1,
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amoExec_in_data_BITS_31_TO_0__q2;
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wire IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d30,
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IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d34;
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// value method amoExec
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assign amoExec =
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amoExec_amo_inst[2] ?
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_theResult_____1__h29 :
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(amoExec_upper_32_bits ?
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{ _theResult_____1__h29[31:0],
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amoExec_current_data[31:0] } :
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{ amoExec_current_data[63:32],
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_theResult_____1__h29[31:0] }) ;
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// remaining internal signals
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assign IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d30 =
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(current_data__h27 ^ 64'h8000000000000000) <=
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(in_data__h28 ^ 64'h8000000000000000) ;
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assign IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d34 =
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current_data__h27 <= in_data__h28 ;
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assign SEXT_amoExec_current_data_BITS_31_TO_0_7___d18 =
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{ {32{amoExec_current_data_BITS_31_TO_0__q3[31]}},
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amoExec_current_data_BITS_31_TO_0__q3 } ;
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assign SEXT_amoExec_current_data_BITS_63_TO_32_3___d14 =
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{ {32{amoExec_current_data_BITS_63_TO_32__q1[31]}},
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amoExec_current_data_BITS_63_TO_32__q1 } ;
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assign SEXT_amoExec_in_data_BITS_31_TO_0____d8 =
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{ {32{amoExec_in_data_BITS_31_TO_0__q2[31]}},
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amoExec_in_data_BITS_31_TO_0__q2 } ;
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assign _theResult___fst__h113 =
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amoExec_upper_32_bits ?
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_theResult___fst__h183 :
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_theResult___fst__h122 ;
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assign amoExec_current_data_BITS_31_TO_0__q3 = amoExec_current_data[31:0] ;
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assign amoExec_current_data_BITS_63_TO_32__q1 =
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amoExec_current_data[63:32] ;
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assign amoExec_in_data_BITS_31_TO_0__q2 = amoExec_in_data[31:0] ;
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assign current_data__h27 =
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amoExec_amo_inst[2] ?
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amoExec_current_data :
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_theResult___fst__h113 ;
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assign in_data__h28 =
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amoExec_amo_inst[2] ? amoExec_in_data : _theResult___snd__h123 ;
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assign new_data__h249 = current_data__h27 + in_data__h28 ;
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assign new_data__h373 = current_data__h27 ^ in_data__h28 ;
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assign new_data__h379 = current_data__h27 & in_data__h28 ;
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assign new_data__h385 = current_data__h27 | in_data__h28 ;
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assign new_data__h391 =
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IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d30 ?
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current_data__h27 :
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in_data__h28 ;
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assign new_data__h405 =
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IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d30 ?
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in_data__h28 :
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current_data__h27 ;
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assign new_data__h419 =
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IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d34 ?
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current_data__h27 :
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in_data__h28 ;
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assign new_data__h433 =
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IF_amoExec_amo_inst_BIT_2_THEN_amoExec_current_ETC___d34 ?
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in_data__h28 :
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current_data__h27 ;
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always@(amoExec_amo_inst or
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amoExec_current_data or
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SEXT_amoExec_current_data_BITS_63_TO_32_3___d14)
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begin
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case (amoExec_amo_inst[6:3])
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4'd5, 4'd6:
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_theResult___fst__h183 =
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SEXT_amoExec_current_data_BITS_63_TO_32_3___d14;
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default: _theResult___fst__h183 =
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{ 32'd0, amoExec_current_data[63:32] };
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endcase
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end
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always@(amoExec_amo_inst or
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amoExec_in_data or SEXT_amoExec_in_data_BITS_31_TO_0____d8)
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begin
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case (amoExec_amo_inst[6:3])
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4'd5, 4'd6:
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_theResult___snd__h123 = SEXT_amoExec_in_data_BITS_31_TO_0____d8;
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default: _theResult___snd__h123 = { 32'd0, amoExec_in_data[31:0] };
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endcase
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end
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always@(amoExec_amo_inst or
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amoExec_current_data or
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SEXT_amoExec_current_data_BITS_31_TO_0_7___d18)
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begin
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case (amoExec_amo_inst[6:3])
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4'd5, 4'd6:
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_theResult___fst__h122 =
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SEXT_amoExec_current_data_BITS_31_TO_0_7___d18;
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default: _theResult___fst__h122 = { 32'd0, amoExec_current_data[31:0] };
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endcase
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end
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always@(amoExec_amo_inst or
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in_data__h28 or
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new_data__h249 or
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new_data__h373 or
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new_data__h379 or
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new_data__h385 or
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new_data__h391 or
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new_data__h405 or new_data__h419 or new_data__h433)
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begin
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case (amoExec_amo_inst[6:3])
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4'd0: _theResult_____1__h29 = in_data__h28;
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4'd1: _theResult_____1__h29 = new_data__h249;
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4'd2: _theResult_____1__h29 = new_data__h373;
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4'd3: _theResult_____1__h29 = new_data__h379;
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4'd4: _theResult_____1__h29 = new_data__h385;
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4'd5: _theResult_____1__h29 = new_data__h391;
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4'd6: _theResult_____1__h29 = new_data__h405;
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4'd7: _theResult_____1__h29 = new_data__h419;
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4'd8: _theResult_____1__h29 = new_data__h433;
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default: _theResult_____1__h29 = 64'd0;
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endcase
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end
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endmodule // module_amoExec
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