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e02b352bbb8a4af89ff729dca34aa43aa047a5dd
Toooba/src_SSITH_P3/xilinx_ip/hdl
History
rsnikhil 83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module 
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
2020-02-04 16:02:53 -05:00
..
BRAM2.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
FIFO1.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO2.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFO10.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
FIFO20.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
FIFOL1.v
Add missing module (FIFOL1) to Xilinx import.
2019-04-24 21:34:52 -04:00
MakeClock.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
MakeResetA.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
mkAluDispToRegFifo.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkAluExeToFinFifo.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkAluRegToExeFifo.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkBht.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkCore.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkCoreW.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkDCRqMshrWrapper.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkDebug_Module.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkDirPredictor.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkDivExecQ.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkDM_Abstract_Commands.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkDM_CSR_Tap.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkDM_GPR_Tap.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkDM_Mem_Tap.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkDM_Run_Control.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkDM_System_Bus.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkDoubleDiv.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkDoubleFMA.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkDoubleSqrt.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkDPipeline.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkDPRqMshrWrapper.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkDTlbSynth.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkDummyStoreBuffer.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkEpochManager.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkFabric_2x3.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkFetchStage.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkFmaExecQ.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkFpuMulDivDispToRegFifo.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkFpuMulDivRegToExeFifo.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkGSelectGHistReg.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkGSelectPred.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkGShareGHistReg.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkGSharePred.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkIBankWrapper.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkICoCache.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkICRqMshrWrapper.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkIPipeline.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkIPRqMshrWrapper.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkITlb.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkJtagTap.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkL2Tlb.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkLastLvCRqMshr.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkLLCache.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkLLPipeline.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkLSQIssueLdQ.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkMemDispToRegFifo.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkMemLoader.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkMemRegToExeFifo.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkMinimumExecQ.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkMMIOInst.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkMulExecQ.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkNullTransCache.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkP3_Core.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkPLIC_16_2_7.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkProc.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkRas.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkRegRenamingTable.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkReorderBufferSynth.v
Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
2020-02-04 16:02:53 -05:00
mkReservationStationAlu.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkReservationStationFpuMulDiv.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkReservationStationMem.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkRFileSynth.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkRobRowSynth.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkScoreboardAggr.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkScoreboardCons.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkSimpleRespQ.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkSoC_Map.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkSpecTagManager.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkSplitLSQ.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkSplitTransCache.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkStoreBufferEhr.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkSyncBramFifo_w36_d512.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkSyncFifo_w32_d16.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkTourGHistReg.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkTourPred.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkTourPredSecure.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkTV_Encode.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
mkTV_Xactor.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkXilinxFpDiv.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkXilinxFpDivIP.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkXilinxFpDivSim.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkXilinxFpFma.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkXilinxFpFmaIP.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkXilinxFpFmaSim.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
mkXilinxFpSqrt.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkXilinxFpSqrtIP.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
mkXilinxFpSqrtSim.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
module_alu.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
module_aluBr.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
module_amoExec.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
module_basicExec.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
module_brAddrCalc.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
module_checkForException.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
module_decode.v
Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL
2020-01-28 21:33:56 -05:00
module_decodeBrPred.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
module_execFpuSimple.v
Updated SoC_Map in src_SSITH_P3 (synth version)
2020-01-30 14:04:29 -05:00
module_getControlFlow.v
Updated src_SSITH_P3 RTL for simulation
2020-01-13 12:19:20 -05:00
RegFile.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
reset_guard.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
ResetEither.v
Add missing files necessary for synthesis.
2019-04-09 14:32:41 -04:00
RevertReg.v
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
SizedFIFO0.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SizedFIFO.v
Update Verilog files for synthesis.
2019-04-09 17:45:27 -04:00
SyncFIFOLevel.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncHandshake.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00
SyncResetA.v
Added support for 'debug_external_interrupt_req'
2019-04-01 12:26:54 -04:00